Alessandro Angelino
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target-mcu-k64f
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MK64F12.h
00001 /* 00002 ** ################################################################### 00003 ** Processors: MK64FN1M0VDC12 00004 ** MK64FN1M0VLL12 00005 ** MK64FN1M0VLQ12 00006 ** MK64FN1M0VMD12 00007 ** 00008 ** Compilers: Keil ARM C/C++ Compiler 00009 ** Freescale C/C++ for Embedded ARM 00010 ** GNU C Compiler 00011 ** GNU C Compiler - CodeSourcery Sourcery G++ 00012 ** IAR ANSI C/C++ Compiler for ARM 00013 ** 00014 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 00015 ** Version: rev. 2.5, 2014-02-10 00016 ** Build: b140604 00017 ** 00018 ** Abstract: 00019 ** CMSIS Peripheral Access Layer for MK64F12 00020 ** 00021 ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc. 00022 ** All rights reserved. 00023 ** 00024 ** Redistribution and use in source and binary forms, with or without modification, 00025 ** are permitted provided that the following conditions are met: 00026 ** 00027 ** o Redistributions of source code must retain the above copyright notice, this list 00028 ** of conditions and the following disclaimer. 00029 ** 00030 ** o Redistributions in binary form must reproduce the above copyright notice, this 00031 ** list of conditions and the following disclaimer in the documentation and/or 00032 ** other materials provided with the distribution. 00033 ** 00034 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its 00035 ** contributors may be used to endorse or promote products derived from this 00036 ** software without specific prior written permission. 00037 ** 00038 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00039 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00040 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00041 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00042 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00043 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00044 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00045 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00046 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00047 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00048 ** 00049 ** http: www.freescale.com 00050 ** mail: support@freescale.com 00051 ** 00052 ** Revisions: 00053 ** - rev. 1.0 (2013-08-12) 00054 ** Initial version. 00055 ** - rev. 2.0 (2013-10-29) 00056 ** Register accessor macros added to the memory map. 00057 ** Symbols for Processor Expert memory map compatibility added to the memory map. 00058 ** Startup file for gcc has been updated according to CMSIS 3.2. 00059 ** System initialization updated. 00060 ** MCG - registers updated. 00061 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. 00062 ** - rev. 2.1 (2013-10-30) 00063 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. 00064 ** - rev. 2.2 (2013-12-09) 00065 ** DMA - EARS register removed. 00066 ** AIPS0, AIPS1 - MPRA register updated. 00067 ** - rev. 2.3 (2014-01-24) 00068 ** Update according to reference manual rev. 2 00069 ** ENET, MCG, MCM, SIM, USB - registers updated 00070 ** - rev. 2.4 (2014-02-10) 00071 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00072 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00073 ** - rev. 2.5 (2014-02-10) 00074 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00075 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00076 ** Module access macro module_BASES replaced by module_BASE_PTRS. 00077 ** 00078 ** ################################################################### 00079 */ 00080 00081 /*! 00082 * @file MK64F12.h 00083 * @version 2.5 00084 * @date 2014-02-10 00085 * @brief CMSIS Peripheral Access Layer for MK64F12 00086 * 00087 * CMSIS Peripheral Access Layer for MK64F12 00088 */ 00089 00090 00091 /* ---------------------------------------------------------------------------- 00092 -- MCU activation 00093 ---------------------------------------------------------------------------- */ 00094 00095 /* Prevention from multiple including the same memory map */ 00096 #if !defined(MK64F12_H_) /* Check if memory map has not been already included */ 00097 #define MK64F12_H_ 00098 #define MCU_MK64F12 00099 00100 /* Check if another memory map has not been also included */ 00101 #if (defined(MCU_ACTIVE)) 00102 #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included. 00103 #endif /* (defined(MCU_ACTIVE)) */ 00104 #define MCU_ACTIVE 00105 00106 #include <stdint.h> 00107 00108 /** Memory map major version (memory maps with equal major version number are 00109 * compatible) */ 00110 #define MCU_MEM_MAP_VERSION 0x0200u 00111 /** Memory map minor version */ 00112 #define MCU_MEM_MAP_VERSION_MINOR 0x0005u 00113 00114 /** 00115 * @brief Macro to calculate address of an aliased word in the peripheral 00116 * bitband area for a peripheral register and bit (bit band region 0x40000000 to 00117 * 0x400FFFFF). 00118 * @param Reg Register to access. 00119 * @param Bit Bit number to access. 00120 * @return Address of the aliased word in the peripheral bitband area. 00121 */ 00122 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) 00123 /** 00124 * @brief Macro to access a single bit of a peripheral register (bit band region 00125 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can 00126 * be used for peripherals with 32bit access allowed. 00127 * @param Reg Register to access. 00128 * @param Bit Bit number to access. 00129 * @return Value of the targeted bit in the bit band region. 00130 */ 00131 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) 00132 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit)) 00133 /** 00134 * @brief Macro to access a single bit of a peripheral register (bit band region 00135 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can 00136 * be used for peripherals with 16bit access allowed. 00137 * @param Reg Register to access. 00138 * @param Bit Bit number to access. 00139 * @return Value of the targeted bit in the bit band region. 00140 */ 00141 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) 00142 /** 00143 * @brief Macro to access a single bit of a peripheral register (bit band region 00144 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can 00145 * be used for peripherals with 8bit access allowed. 00146 * @param Reg Register to access. 00147 * @param Bit Bit number to access. 00148 * @return Value of the targeted bit in the bit band region. 00149 */ 00150 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) 00151 00152 /* ---------------------------------------------------------------------------- 00153 -- Interrupt vector numbers 00154 ---------------------------------------------------------------------------- */ 00155 00156 /*! 00157 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 00158 * @{ 00159 */ 00160 00161 /** Interrupt Number Definitions */ 00162 #define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */ 00163 00164 typedef enum IRQn { 00165 /* Core interrupts */ 00166 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 00167 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ 00168 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ 00169 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ 00170 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ 00171 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ 00172 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ 00173 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ 00174 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ 00175 00176 /* Device specific interrupts */ 00177 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */ 00178 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ 00179 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ 00180 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ 00181 DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ 00182 DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ 00183 DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ 00184 DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ 00185 DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ 00186 DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ 00187 DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ 00188 DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ 00189 DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ 00190 DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ 00191 DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ 00192 DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ 00193 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ 00194 MCM_IRQn = 17, /**< Normal Interrupt */ 00195 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */ 00196 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ 00197 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ 00198 LLW_IRQn = 21, /**< Low Leakage Wakeup */ 00199 Watchdog_IRQn = 22, /**< WDOG Interrupt */ 00200 RNG_IRQn = 23, /**< RNG Interrupt */ 00201 I2C0_IRQn = 24, /**< I2C0 interrupt */ 00202 I2C1_IRQn = 25, /**< I2C1 interrupt */ 00203 SPI0_IRQn = 26, /**< SPI0 Interrupt */ 00204 SPI1_IRQn = 27, /**< SPI1 Interrupt */ 00205 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */ 00206 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */ 00207 UART0_LON_IRQn = 30, /**< UART0 LON interrupt */ 00208 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ 00209 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */ 00210 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */ 00211 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */ 00212 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */ 00213 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */ 00214 UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */ 00215 UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */ 00216 ADC0_IRQn = 39, /**< ADC0 interrupt */ 00217 CMP0_IRQn = 40, /**< CMP0 interrupt */ 00218 CMP1_IRQn = 41, /**< CMP1 interrupt */ 00219 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */ 00220 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */ 00221 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */ 00222 CMT_IRQn = 45, /**< CMT interrupt */ 00223 RTC_IRQn = 46, /**< RTC interrupt */ 00224 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */ 00225 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */ 00226 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */ 00227 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */ 00228 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */ 00229 PDB0_IRQn = 52, /**< PDB0 Interrupt */ 00230 USB0_IRQn = 53, /**< USB0 interrupt */ 00231 USBDCD_IRQn = 54, /**< USBDCD Interrupt */ 00232 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */ 00233 DAC0_IRQn = 56, /**< DAC0 interrupt */ 00234 MCG_IRQn = 57, /**< MCG Interrupt */ 00235 LPTimer_IRQn = 58, /**< LPTimer interrupt */ 00236 PORTA_IRQn = 59, /**< Port A interrupt */ 00237 PORTB_IRQn = 60, /**< Port B interrupt */ 00238 PORTC_IRQn = 61, /**< Port C interrupt */ 00239 PORTD_IRQn = 62, /**< Port D interrupt */ 00240 PORTE_IRQn = 63, /**< Port E interrupt */ 00241 SWI_IRQn = 64, /**< Software interrupt */ 00242 SPI2_IRQn = 65, /**< SPI2 Interrupt */ 00243 UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */ 00244 UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */ 00245 UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */ 00246 UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */ 00247 CMP2_IRQn = 70, /**< CMP2 interrupt */ 00248 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ 00249 DAC1_IRQn = 72, /**< DAC1 interrupt */ 00250 ADC1_IRQn = 73, /**< ADC1 interrupt */ 00251 I2C2_IRQn = 74, /**< I2C2 interrupt */ 00252 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */ 00253 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */ 00254 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */ 00255 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */ 00256 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */ 00257 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */ 00258 SDHC_IRQn = 81, /**< SDHC interrupt */ 00259 ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */ 00260 ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */ 00261 ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */ 00262 ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */ 00263 } IRQn_Type; 00264 00265 /*! 00266 * @} 00267 */ /* end of group Interrupt_vector_numbers */ 00268 00269 00270 /* ---------------------------------------------------------------------------- 00271 -- Cortex M4 Core Configuration 00272 ---------------------------------------------------------------------------- */ 00273 00274 /*! 00275 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration 00276 * @{ 00277 */ 00278 00279 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 00280 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ 00281 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 00282 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ 00283 00284 #include "core_cm4.h" /* Core Peripheral Access Layer */ 00285 #include "system_MK64F12.h" /* Device specific configuration file */ 00286 00287 /*! 00288 * @} 00289 */ /* end of group Cortex_Core_Configuration */ 00290 00291 00292 /* ---------------------------------------------------------------------------- 00293 -- Device Peripheral Access Layer 00294 ---------------------------------------------------------------------------- */ 00295 00296 /*! 00297 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 00298 * @{ 00299 */ 00300 00301 00302 /* 00303 ** Start of section using anonymous unions 00304 */ 00305 00306 #if defined(__ARMCC_VERSION) 00307 #pragma push 00308 #pragma anon_unions 00309 #elif defined(__CWCC__) 00310 #pragma push 00311 #pragma cpp_extensions on 00312 #elif defined(__GNUC__) 00313 /* anonymous unions are enabled by default */ 00314 #elif defined(__IAR_SYSTEMS_ICC__) 00315 #pragma language=extended 00316 #else 00317 #error Not supported compiler type 00318 #endif 00319 00320 /* ---------------------------------------------------------------------------- 00321 -- ADC Peripheral Access Layer 00322 ---------------------------------------------------------------------------- */ 00323 00324 /*! 00325 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 00326 * @{ 00327 */ 00328 00329 /** ADC - Register Layout Typedef */ 00330 typedef struct { 00331 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ 00332 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ 00333 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ 00334 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ 00335 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ 00336 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ 00337 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ 00338 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ 00339 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ 00340 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ 00341 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ 00342 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ 00343 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ 00344 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ 00345 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ 00346 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ 00347 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ 00348 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ 00349 uint8_t RESERVED_0[4]; 00350 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ 00351 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ 00352 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ 00353 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ 00354 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ 00355 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ 00356 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ 00357 } ADC_Type, *ADC_MemMapPtr; 00358 00359 /* ---------------------------------------------------------------------------- 00360 -- ADC - Register accessor macros 00361 ---------------------------------------------------------------------------- */ 00362 00363 /*! 00364 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros 00365 * @{ 00366 */ 00367 00368 00369 /* ADC - Register accessors */ 00370 #define ADC_SC1_REG(base,index) ((base)->SC1[index]) 00371 #define ADC_CFG1_REG(base) ((base)->CFG1) 00372 #define ADC_CFG2_REG(base) ((base)->CFG2) 00373 #define ADC_R_REG(base,index) ((base)->R[index]) 00374 #define ADC_CV1_REG(base) ((base)->CV1) 00375 #define ADC_CV2_REG(base) ((base)->CV2) 00376 #define ADC_SC2_REG(base) ((base)->SC2) 00377 #define ADC_SC3_REG(base) ((base)->SC3) 00378 #define ADC_OFS_REG(base) ((base)->OFS) 00379 #define ADC_PG_REG(base) ((base)->PG) 00380 #define ADC_MG_REG(base) ((base)->MG) 00381 #define ADC_CLPD_REG(base) ((base)->CLPD) 00382 #define ADC_CLPS_REG(base) ((base)->CLPS) 00383 #define ADC_CLP4_REG(base) ((base)->CLP4) 00384 #define ADC_CLP3_REG(base) ((base)->CLP3) 00385 #define ADC_CLP2_REG(base) ((base)->CLP2) 00386 #define ADC_CLP1_REG(base) ((base)->CLP1) 00387 #define ADC_CLP0_REG(base) ((base)->CLP0) 00388 #define ADC_CLMD_REG(base) ((base)->CLMD) 00389 #define ADC_CLMS_REG(base) ((base)->CLMS) 00390 #define ADC_CLM4_REG(base) ((base)->CLM4) 00391 #define ADC_CLM3_REG(base) ((base)->CLM3) 00392 #define ADC_CLM2_REG(base) ((base)->CLM2) 00393 #define ADC_CLM1_REG(base) ((base)->CLM1) 00394 #define ADC_CLM0_REG(base) ((base)->CLM0) 00395 00396 /*! 00397 * @} 00398 */ /* end of group ADC_Register_Accessor_Macros */ 00399 00400 00401 /* ---------------------------------------------------------------------------- 00402 -- ADC Register Masks 00403 ---------------------------------------------------------------------------- */ 00404 00405 /*! 00406 * @addtogroup ADC_Register_Masks ADC Register Masks 00407 * @{ 00408 */ 00409 00410 /* SC1 Bit Fields */ 00411 #define ADC_SC1_ADCH_MASK 0x1Fu 00412 #define ADC_SC1_ADCH_SHIFT 0 00413 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK) 00414 #define ADC_SC1_DIFF_MASK 0x20u 00415 #define ADC_SC1_DIFF_SHIFT 5 00416 #define ADC_SC1_AIEN_MASK 0x40u 00417 #define ADC_SC1_AIEN_SHIFT 6 00418 #define ADC_SC1_COCO_MASK 0x80u 00419 #define ADC_SC1_COCO_SHIFT 7 00420 /* CFG1 Bit Fields */ 00421 #define ADC_CFG1_ADICLK_MASK 0x3u 00422 #define ADC_CFG1_ADICLK_SHIFT 0 00423 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK) 00424 #define ADC_CFG1_MODE_MASK 0xCu 00425 #define ADC_CFG1_MODE_SHIFT 2 00426 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK) 00427 #define ADC_CFG1_ADLSMP_MASK 0x10u 00428 #define ADC_CFG1_ADLSMP_SHIFT 4 00429 #define ADC_CFG1_ADIV_MASK 0x60u 00430 #define ADC_CFG1_ADIV_SHIFT 5 00431 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK) 00432 #define ADC_CFG1_ADLPC_MASK 0x80u 00433 #define ADC_CFG1_ADLPC_SHIFT 7 00434 /* CFG2 Bit Fields */ 00435 #define ADC_CFG2_ADLSTS_MASK 0x3u 00436 #define ADC_CFG2_ADLSTS_SHIFT 0 00437 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK) 00438 #define ADC_CFG2_ADHSC_MASK 0x4u 00439 #define ADC_CFG2_ADHSC_SHIFT 2 00440 #define ADC_CFG2_ADACKEN_MASK 0x8u 00441 #define ADC_CFG2_ADACKEN_SHIFT 3 00442 #define ADC_CFG2_MUXSEL_MASK 0x10u 00443 #define ADC_CFG2_MUXSEL_SHIFT 4 00444 /* R Bit Fields */ 00445 #define ADC_R_D_MASK 0xFFFFu 00446 #define ADC_R_D_SHIFT 0 00447 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK) 00448 /* CV1 Bit Fields */ 00449 #define ADC_CV1_CV_MASK 0xFFFFu 00450 #define ADC_CV1_CV_SHIFT 0 00451 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK) 00452 /* CV2 Bit Fields */ 00453 #define ADC_CV2_CV_MASK 0xFFFFu 00454 #define ADC_CV2_CV_SHIFT 0 00455 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK) 00456 /* SC2 Bit Fields */ 00457 #define ADC_SC2_REFSEL_MASK 0x3u 00458 #define ADC_SC2_REFSEL_SHIFT 0 00459 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK) 00460 #define ADC_SC2_DMAEN_MASK 0x4u 00461 #define ADC_SC2_DMAEN_SHIFT 2 00462 #define ADC_SC2_ACREN_MASK 0x8u 00463 #define ADC_SC2_ACREN_SHIFT 3 00464 #define ADC_SC2_ACFGT_MASK 0x10u 00465 #define ADC_SC2_ACFGT_SHIFT 4 00466 #define ADC_SC2_ACFE_MASK 0x20u 00467 #define ADC_SC2_ACFE_SHIFT 5 00468 #define ADC_SC2_ADTRG_MASK 0x40u 00469 #define ADC_SC2_ADTRG_SHIFT 6 00470 #define ADC_SC2_ADACT_MASK 0x80u 00471 #define ADC_SC2_ADACT_SHIFT 7 00472 /* SC3 Bit Fields */ 00473 #define ADC_SC3_AVGS_MASK 0x3u 00474 #define ADC_SC3_AVGS_SHIFT 0 00475 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK) 00476 #define ADC_SC3_AVGE_MASK 0x4u 00477 #define ADC_SC3_AVGE_SHIFT 2 00478 #define ADC_SC3_ADCO_MASK 0x8u 00479 #define ADC_SC3_ADCO_SHIFT 3 00480 #define ADC_SC3_CALF_MASK 0x40u 00481 #define ADC_SC3_CALF_SHIFT 6 00482 #define ADC_SC3_CAL_MASK 0x80u 00483 #define ADC_SC3_CAL_SHIFT 7 00484 /* OFS Bit Fields */ 00485 #define ADC_OFS_OFS_MASK 0xFFFFu 00486 #define ADC_OFS_OFS_SHIFT 0 00487 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK) 00488 /* PG Bit Fields */ 00489 #define ADC_PG_PG_MASK 0xFFFFu 00490 #define ADC_PG_PG_SHIFT 0 00491 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK) 00492 /* MG Bit Fields */ 00493 #define ADC_MG_MG_MASK 0xFFFFu 00494 #define ADC_MG_MG_SHIFT 0 00495 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK) 00496 /* CLPD Bit Fields */ 00497 #define ADC_CLPD_CLPD_MASK 0x3Fu 00498 #define ADC_CLPD_CLPD_SHIFT 0 00499 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK) 00500 /* CLPS Bit Fields */ 00501 #define ADC_CLPS_CLPS_MASK 0x3Fu 00502 #define ADC_CLPS_CLPS_SHIFT 0 00503 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK) 00504 /* CLP4 Bit Fields */ 00505 #define ADC_CLP4_CLP4_MASK 0x3FFu 00506 #define ADC_CLP4_CLP4_SHIFT 0 00507 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK) 00508 /* CLP3 Bit Fields */ 00509 #define ADC_CLP3_CLP3_MASK 0x1FFu 00510 #define ADC_CLP3_CLP3_SHIFT 0 00511 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK) 00512 /* CLP2 Bit Fields */ 00513 #define ADC_CLP2_CLP2_MASK 0xFFu 00514 #define ADC_CLP2_CLP2_SHIFT 0 00515 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK) 00516 /* CLP1 Bit Fields */ 00517 #define ADC_CLP1_CLP1_MASK 0x7Fu 00518 #define ADC_CLP1_CLP1_SHIFT 0 00519 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK) 00520 /* CLP0 Bit Fields */ 00521 #define ADC_CLP0_CLP0_MASK 0x3Fu 00522 #define ADC_CLP0_CLP0_SHIFT 0 00523 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK) 00524 /* CLMD Bit Fields */ 00525 #define ADC_CLMD_CLMD_MASK 0x3Fu 00526 #define ADC_CLMD_CLMD_SHIFT 0 00527 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK) 00528 /* CLMS Bit Fields */ 00529 #define ADC_CLMS_CLMS_MASK 0x3Fu 00530 #define ADC_CLMS_CLMS_SHIFT 0 00531 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK) 00532 /* CLM4 Bit Fields */ 00533 #define ADC_CLM4_CLM4_MASK 0x3FFu 00534 #define ADC_CLM4_CLM4_SHIFT 0 00535 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK) 00536 /* CLM3 Bit Fields */ 00537 #define ADC_CLM3_CLM3_MASK 0x1FFu 00538 #define ADC_CLM3_CLM3_SHIFT 0 00539 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK) 00540 /* CLM2 Bit Fields */ 00541 #define ADC_CLM2_CLM2_MASK 0xFFu 00542 #define ADC_CLM2_CLM2_SHIFT 0 00543 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK) 00544 /* CLM1 Bit Fields */ 00545 #define ADC_CLM1_CLM1_MASK 0x7Fu 00546 #define ADC_CLM1_CLM1_SHIFT 0 00547 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK) 00548 /* CLM0 Bit Fields */ 00549 #define ADC_CLM0_CLM0_MASK 0x3Fu 00550 #define ADC_CLM0_CLM0_SHIFT 0 00551 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK) 00552 00553 /*! 00554 * @} 00555 */ /* end of group ADC_Register_Masks */ 00556 00557 00558 /* ADC - Peripheral instance base addresses */ 00559 /** Peripheral ADC0 base address */ 00560 #define ADC0_BASE (0x4003B000u) 00561 /** Peripheral ADC0 base pointer */ 00562 #define ADC0 ((ADC_Type *)ADC0_BASE) 00563 #define ADC0_BASE_PTR (ADC0) 00564 /** Peripheral ADC1 base address */ 00565 #define ADC1_BASE (0x400BB000u) 00566 /** Peripheral ADC1 base pointer */ 00567 #define ADC1 ((ADC_Type *)ADC1_BASE) 00568 #define ADC1_BASE_PTR (ADC1) 00569 /** Array initializer of ADC peripheral base addresses */ 00570 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } 00571 /** Array initializer of ADC peripheral base pointers */ 00572 #define ADC_BASE_PTRS { ADC0, ADC1 } 00573 /** Interrupt vectors for the ADC peripheral type */ 00574 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } 00575 00576 /* ---------------------------------------------------------------------------- 00577 -- ADC - Register accessor macros 00578 ---------------------------------------------------------------------------- */ 00579 00580 /*! 00581 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros 00582 * @{ 00583 */ 00584 00585 00586 /* ADC - Register instance definitions */ 00587 /* ADC0 */ 00588 #define ADC0_SC1A ADC_SC1_REG(ADC0,0) 00589 #define ADC0_SC1B ADC_SC1_REG(ADC0,1) 00590 #define ADC0_CFG1 ADC_CFG1_REG(ADC0) 00591 #define ADC0_CFG2 ADC_CFG2_REG(ADC0) 00592 #define ADC0_RA ADC_R_REG(ADC0,0) 00593 #define ADC0_RB ADC_R_REG(ADC0,1) 00594 #define ADC0_CV1 ADC_CV1_REG(ADC0) 00595 #define ADC0_CV2 ADC_CV2_REG(ADC0) 00596 #define ADC0_SC2 ADC_SC2_REG(ADC0) 00597 #define ADC0_SC3 ADC_SC3_REG(ADC0) 00598 #define ADC0_OFS ADC_OFS_REG(ADC0) 00599 #define ADC0_PG ADC_PG_REG(ADC0) 00600 #define ADC0_MG ADC_MG_REG(ADC0) 00601 #define ADC0_CLPD ADC_CLPD_REG(ADC0) 00602 #define ADC0_CLPS ADC_CLPS_REG(ADC0) 00603 #define ADC0_CLP4 ADC_CLP4_REG(ADC0) 00604 #define ADC0_CLP3 ADC_CLP3_REG(ADC0) 00605 #define ADC0_CLP2 ADC_CLP2_REG(ADC0) 00606 #define ADC0_CLP1 ADC_CLP1_REG(ADC0) 00607 #define ADC0_CLP0 ADC_CLP0_REG(ADC0) 00608 #define ADC0_CLMD ADC_CLMD_REG(ADC0) 00609 #define ADC0_CLMS ADC_CLMS_REG(ADC0) 00610 #define ADC0_CLM4 ADC_CLM4_REG(ADC0) 00611 #define ADC0_CLM3 ADC_CLM3_REG(ADC0) 00612 #define ADC0_CLM2 ADC_CLM2_REG(ADC0) 00613 #define ADC0_CLM1 ADC_CLM1_REG(ADC0) 00614 #define ADC0_CLM0 ADC_CLM0_REG(ADC0) 00615 /* ADC1 */ 00616 #define ADC1_SC1A ADC_SC1_REG(ADC1,0) 00617 #define ADC1_SC1B ADC_SC1_REG(ADC1,1) 00618 #define ADC1_CFG1 ADC_CFG1_REG(ADC1) 00619 #define ADC1_CFG2 ADC_CFG2_REG(ADC1) 00620 #define ADC1_RA ADC_R_REG(ADC1,0) 00621 #define ADC1_RB ADC_R_REG(ADC1,1) 00622 #define ADC1_CV1 ADC_CV1_REG(ADC1) 00623 #define ADC1_CV2 ADC_CV2_REG(ADC1) 00624 #define ADC1_SC2 ADC_SC2_REG(ADC1) 00625 #define ADC1_SC3 ADC_SC3_REG(ADC1) 00626 #define ADC1_OFS ADC_OFS_REG(ADC1) 00627 #define ADC1_PG ADC_PG_REG(ADC1) 00628 #define ADC1_MG ADC_MG_REG(ADC1) 00629 #define ADC1_CLPD ADC_CLPD_REG(ADC1) 00630 #define ADC1_CLPS ADC_CLPS_REG(ADC1) 00631 #define ADC1_CLP4 ADC_CLP4_REG(ADC1) 00632 #define ADC1_CLP3 ADC_CLP3_REG(ADC1) 00633 #define ADC1_CLP2 ADC_CLP2_REG(ADC1) 00634 #define ADC1_CLP1 ADC_CLP1_REG(ADC1) 00635 #define ADC1_CLP0 ADC_CLP0_REG(ADC1) 00636 #define ADC1_CLMD ADC_CLMD_REG(ADC1) 00637 #define ADC1_CLMS ADC_CLMS_REG(ADC1) 00638 #define ADC1_CLM4 ADC_CLM4_REG(ADC1) 00639 #define ADC1_CLM3 ADC_CLM3_REG(ADC1) 00640 #define ADC1_CLM2 ADC_CLM2_REG(ADC1) 00641 #define ADC1_CLM1 ADC_CLM1_REG(ADC1) 00642 #define ADC1_CLM0 ADC_CLM0_REG(ADC1) 00643 00644 /* ADC - Register array accessors */ 00645 #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index) 00646 #define ADC1_SC1(index) ADC_SC1_REG(ADC1,index) 00647 #define ADC0_R(index) ADC_R_REG(ADC0,index) 00648 #define ADC1_R(index) ADC_R_REG(ADC1,index) 00649 00650 /*! 00651 * @} 00652 */ /* end of group ADC_Register_Accessor_Macros */ 00653 00654 00655 /*! 00656 * @} 00657 */ /* end of group ADC_Peripheral_Access_Layer */ 00658 00659 00660 /* ---------------------------------------------------------------------------- 00661 -- AIPS Peripheral Access Layer 00662 ---------------------------------------------------------------------------- */ 00663 00664 /*! 00665 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer 00666 * @{ 00667 */ 00668 00669 /** AIPS - Register Layout Typedef */ 00670 typedef struct { 00671 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */ 00672 uint8_t RESERVED_0[28]; 00673 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */ 00674 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */ 00675 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */ 00676 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */ 00677 uint8_t RESERVED_1[16]; 00678 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */ 00679 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */ 00680 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */ 00681 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */ 00682 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */ 00683 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */ 00684 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */ 00685 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */ 00686 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */ 00687 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */ 00688 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */ 00689 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */ 00690 uint8_t RESERVED_2[16]; 00691 __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */ 00692 } AIPS_Type, *AIPS_MemMapPtr; 00693 00694 /* ---------------------------------------------------------------------------- 00695 -- AIPS - Register accessor macros 00696 ---------------------------------------------------------------------------- */ 00697 00698 /*! 00699 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros 00700 * @{ 00701 */ 00702 00703 00704 /* AIPS - Register accessors */ 00705 #define AIPS_MPRA_REG(base) ((base)->MPRA) 00706 #define AIPS_PACRA_REG(base) ((base)->PACRA) 00707 #define AIPS_PACRB_REG(base) ((base)->PACRB) 00708 #define AIPS_PACRC_REG(base) ((base)->PACRC) 00709 #define AIPS_PACRD_REG(base) ((base)->PACRD) 00710 #define AIPS_PACRE_REG(base) ((base)->PACRE) 00711 #define AIPS_PACRF_REG(base) ((base)->PACRF) 00712 #define AIPS_PACRG_REG(base) ((base)->PACRG) 00713 #define AIPS_PACRH_REG(base) ((base)->PACRH) 00714 #define AIPS_PACRI_REG(base) ((base)->PACRI) 00715 #define AIPS_PACRJ_REG(base) ((base)->PACRJ) 00716 #define AIPS_PACRK_REG(base) ((base)->PACRK) 00717 #define AIPS_PACRL_REG(base) ((base)->PACRL) 00718 #define AIPS_PACRM_REG(base) ((base)->PACRM) 00719 #define AIPS_PACRN_REG(base) ((base)->PACRN) 00720 #define AIPS_PACRO_REG(base) ((base)->PACRO) 00721 #define AIPS_PACRP_REG(base) ((base)->PACRP) 00722 #define AIPS_PACRU_REG(base) ((base)->PACRU) 00723 00724 /*! 00725 * @} 00726 */ /* end of group AIPS_Register_Accessor_Macros */ 00727 00728 00729 /* ---------------------------------------------------------------------------- 00730 -- AIPS Register Masks 00731 ---------------------------------------------------------------------------- */ 00732 00733 /*! 00734 * @addtogroup AIPS_Register_Masks AIPS Register Masks 00735 * @{ 00736 */ 00737 00738 /* MPRA Bit Fields */ 00739 #define AIPS_MPRA_MPL5_MASK 0x100u 00740 #define AIPS_MPRA_MPL5_SHIFT 8 00741 #define AIPS_MPRA_MTW5_MASK 0x200u 00742 #define AIPS_MPRA_MTW5_SHIFT 9 00743 #define AIPS_MPRA_MTR5_MASK 0x400u 00744 #define AIPS_MPRA_MTR5_SHIFT 10 00745 #define AIPS_MPRA_MPL4_MASK 0x1000u 00746 #define AIPS_MPRA_MPL4_SHIFT 12 00747 #define AIPS_MPRA_MTW4_MASK 0x2000u 00748 #define AIPS_MPRA_MTW4_SHIFT 13 00749 #define AIPS_MPRA_MTR4_MASK 0x4000u 00750 #define AIPS_MPRA_MTR4_SHIFT 14 00751 #define AIPS_MPRA_MPL3_MASK 0x10000u 00752 #define AIPS_MPRA_MPL3_SHIFT 16 00753 #define AIPS_MPRA_MTW3_MASK 0x20000u 00754 #define AIPS_MPRA_MTW3_SHIFT 17 00755 #define AIPS_MPRA_MTR3_MASK 0x40000u 00756 #define AIPS_MPRA_MTR3_SHIFT 18 00757 #define AIPS_MPRA_MPL2_MASK 0x100000u 00758 #define AIPS_MPRA_MPL2_SHIFT 20 00759 #define AIPS_MPRA_MTW2_MASK 0x200000u 00760 #define AIPS_MPRA_MTW2_SHIFT 21 00761 #define AIPS_MPRA_MTR2_MASK 0x400000u 00762 #define AIPS_MPRA_MTR2_SHIFT 22 00763 #define AIPS_MPRA_MPL1_MASK 0x1000000u 00764 #define AIPS_MPRA_MPL1_SHIFT 24 00765 #define AIPS_MPRA_MTW1_MASK 0x2000000u 00766 #define AIPS_MPRA_MTW1_SHIFT 25 00767 #define AIPS_MPRA_MTR1_MASK 0x4000000u 00768 #define AIPS_MPRA_MTR1_SHIFT 26 00769 #define AIPS_MPRA_MPL0_MASK 0x10000000u 00770 #define AIPS_MPRA_MPL0_SHIFT 28 00771 #define AIPS_MPRA_MTW0_MASK 0x20000000u 00772 #define AIPS_MPRA_MTW0_SHIFT 29 00773 #define AIPS_MPRA_MTR0_MASK 0x40000000u 00774 #define AIPS_MPRA_MTR0_SHIFT 30 00775 /* PACRA Bit Fields */ 00776 #define AIPS_PACRA_TP7_MASK 0x1u 00777 #define AIPS_PACRA_TP7_SHIFT 0 00778 #define AIPS_PACRA_WP7_MASK 0x2u 00779 #define AIPS_PACRA_WP7_SHIFT 1 00780 #define AIPS_PACRA_SP7_MASK 0x4u 00781 #define AIPS_PACRA_SP7_SHIFT 2 00782 #define AIPS_PACRA_TP6_MASK 0x10u 00783 #define AIPS_PACRA_TP6_SHIFT 4 00784 #define AIPS_PACRA_WP6_MASK 0x20u 00785 #define AIPS_PACRA_WP6_SHIFT 5 00786 #define AIPS_PACRA_SP6_MASK 0x40u 00787 #define AIPS_PACRA_SP6_SHIFT 6 00788 #define AIPS_PACRA_TP5_MASK 0x100u 00789 #define AIPS_PACRA_TP5_SHIFT 8 00790 #define AIPS_PACRA_WP5_MASK 0x200u 00791 #define AIPS_PACRA_WP5_SHIFT 9 00792 #define AIPS_PACRA_SP5_MASK 0x400u 00793 #define AIPS_PACRA_SP5_SHIFT 10 00794 #define AIPS_PACRA_TP4_MASK 0x1000u 00795 #define AIPS_PACRA_TP4_SHIFT 12 00796 #define AIPS_PACRA_WP4_MASK 0x2000u 00797 #define AIPS_PACRA_WP4_SHIFT 13 00798 #define AIPS_PACRA_SP4_MASK 0x4000u 00799 #define AIPS_PACRA_SP4_SHIFT 14 00800 #define AIPS_PACRA_TP3_MASK 0x10000u 00801 #define AIPS_PACRA_TP3_SHIFT 16 00802 #define AIPS_PACRA_WP3_MASK 0x20000u 00803 #define AIPS_PACRA_WP3_SHIFT 17 00804 #define AIPS_PACRA_SP3_MASK 0x40000u 00805 #define AIPS_PACRA_SP3_SHIFT 18 00806 #define AIPS_PACRA_TP2_MASK 0x100000u 00807 #define AIPS_PACRA_TP2_SHIFT 20 00808 #define AIPS_PACRA_WP2_MASK 0x200000u 00809 #define AIPS_PACRA_WP2_SHIFT 21 00810 #define AIPS_PACRA_SP2_MASK 0x400000u 00811 #define AIPS_PACRA_SP2_SHIFT 22 00812 #define AIPS_PACRA_TP1_MASK 0x1000000u 00813 #define AIPS_PACRA_TP1_SHIFT 24 00814 #define AIPS_PACRA_WP1_MASK 0x2000000u 00815 #define AIPS_PACRA_WP1_SHIFT 25 00816 #define AIPS_PACRA_SP1_MASK 0x4000000u 00817 #define AIPS_PACRA_SP1_SHIFT 26 00818 #define AIPS_PACRA_TP0_MASK 0x10000000u 00819 #define AIPS_PACRA_TP0_SHIFT 28 00820 #define AIPS_PACRA_WP0_MASK 0x20000000u 00821 #define AIPS_PACRA_WP0_SHIFT 29 00822 #define AIPS_PACRA_SP0_MASK 0x40000000u 00823 #define AIPS_PACRA_SP0_SHIFT 30 00824 /* PACRB Bit Fields */ 00825 #define AIPS_PACRB_TP7_MASK 0x1u 00826 #define AIPS_PACRB_TP7_SHIFT 0 00827 #define AIPS_PACRB_WP7_MASK 0x2u 00828 #define AIPS_PACRB_WP7_SHIFT 1 00829 #define AIPS_PACRB_SP7_MASK 0x4u 00830 #define AIPS_PACRB_SP7_SHIFT 2 00831 #define AIPS_PACRB_TP6_MASK 0x10u 00832 #define AIPS_PACRB_TP6_SHIFT 4 00833 #define AIPS_PACRB_WP6_MASK 0x20u 00834 #define AIPS_PACRB_WP6_SHIFT 5 00835 #define AIPS_PACRB_SP6_MASK 0x40u 00836 #define AIPS_PACRB_SP6_SHIFT 6 00837 #define AIPS_PACRB_TP5_MASK 0x100u 00838 #define AIPS_PACRB_TP5_SHIFT 8 00839 #define AIPS_PACRB_WP5_MASK 0x200u 00840 #define AIPS_PACRB_WP5_SHIFT 9 00841 #define AIPS_PACRB_SP5_MASK 0x400u 00842 #define AIPS_PACRB_SP5_SHIFT 10 00843 #define AIPS_PACRB_TP4_MASK 0x1000u 00844 #define AIPS_PACRB_TP4_SHIFT 12 00845 #define AIPS_PACRB_WP4_MASK 0x2000u 00846 #define AIPS_PACRB_WP4_SHIFT 13 00847 #define AIPS_PACRB_SP4_MASK 0x4000u 00848 #define AIPS_PACRB_SP4_SHIFT 14 00849 #define AIPS_PACRB_TP3_MASK 0x10000u 00850 #define AIPS_PACRB_TP3_SHIFT 16 00851 #define AIPS_PACRB_WP3_MASK 0x20000u 00852 #define AIPS_PACRB_WP3_SHIFT 17 00853 #define AIPS_PACRB_SP3_MASK 0x40000u 00854 #define AIPS_PACRB_SP3_SHIFT 18 00855 #define AIPS_PACRB_TP2_MASK 0x100000u 00856 #define AIPS_PACRB_TP2_SHIFT 20 00857 #define AIPS_PACRB_WP2_MASK 0x200000u 00858 #define AIPS_PACRB_WP2_SHIFT 21 00859 #define AIPS_PACRB_SP2_MASK 0x400000u 00860 #define AIPS_PACRB_SP2_SHIFT 22 00861 #define AIPS_PACRB_TP1_MASK 0x1000000u 00862 #define AIPS_PACRB_TP1_SHIFT 24 00863 #define AIPS_PACRB_WP1_MASK 0x2000000u 00864 #define AIPS_PACRB_WP1_SHIFT 25 00865 #define AIPS_PACRB_SP1_MASK 0x4000000u 00866 #define AIPS_PACRB_SP1_SHIFT 26 00867 #define AIPS_PACRB_TP0_MASK 0x10000000u 00868 #define AIPS_PACRB_TP0_SHIFT 28 00869 #define AIPS_PACRB_WP0_MASK 0x20000000u 00870 #define AIPS_PACRB_WP0_SHIFT 29 00871 #define AIPS_PACRB_SP0_MASK 0x40000000u 00872 #define AIPS_PACRB_SP0_SHIFT 30 00873 /* PACRC Bit Fields */ 00874 #define AIPS_PACRC_TP7_MASK 0x1u 00875 #define AIPS_PACRC_TP7_SHIFT 0 00876 #define AIPS_PACRC_WP7_MASK 0x2u 00877 #define AIPS_PACRC_WP7_SHIFT 1 00878 #define AIPS_PACRC_SP7_MASK 0x4u 00879 #define AIPS_PACRC_SP7_SHIFT 2 00880 #define AIPS_PACRC_TP6_MASK 0x10u 00881 #define AIPS_PACRC_TP6_SHIFT 4 00882 #define AIPS_PACRC_WP6_MASK 0x20u 00883 #define AIPS_PACRC_WP6_SHIFT 5 00884 #define AIPS_PACRC_SP6_MASK 0x40u 00885 #define AIPS_PACRC_SP6_SHIFT 6 00886 #define AIPS_PACRC_TP5_MASK 0x100u 00887 #define AIPS_PACRC_TP5_SHIFT 8 00888 #define AIPS_PACRC_WP5_MASK 0x200u 00889 #define AIPS_PACRC_WP5_SHIFT 9 00890 #define AIPS_PACRC_SP5_MASK 0x400u 00891 #define AIPS_PACRC_SP5_SHIFT 10 00892 #define AIPS_PACRC_TP4_MASK 0x1000u 00893 #define AIPS_PACRC_TP4_SHIFT 12 00894 #define AIPS_PACRC_WP4_MASK 0x2000u 00895 #define AIPS_PACRC_WP4_SHIFT 13 00896 #define AIPS_PACRC_SP4_MASK 0x4000u 00897 #define AIPS_PACRC_SP4_SHIFT 14 00898 #define AIPS_PACRC_TP3_MASK 0x10000u 00899 #define AIPS_PACRC_TP3_SHIFT 16 00900 #define AIPS_PACRC_WP3_MASK 0x20000u 00901 #define AIPS_PACRC_WP3_SHIFT 17 00902 #define AIPS_PACRC_SP3_MASK 0x40000u 00903 #define AIPS_PACRC_SP3_SHIFT 18 00904 #define AIPS_PACRC_TP2_MASK 0x100000u 00905 #define AIPS_PACRC_TP2_SHIFT 20 00906 #define AIPS_PACRC_WP2_MASK 0x200000u 00907 #define AIPS_PACRC_WP2_SHIFT 21 00908 #define AIPS_PACRC_SP2_MASK 0x400000u 00909 #define AIPS_PACRC_SP2_SHIFT 22 00910 #define AIPS_PACRC_TP1_MASK 0x1000000u 00911 #define AIPS_PACRC_TP1_SHIFT 24 00912 #define AIPS_PACRC_WP1_MASK 0x2000000u 00913 #define AIPS_PACRC_WP1_SHIFT 25 00914 #define AIPS_PACRC_SP1_MASK 0x4000000u 00915 #define AIPS_PACRC_SP1_SHIFT 26 00916 #define AIPS_PACRC_TP0_MASK 0x10000000u 00917 #define AIPS_PACRC_TP0_SHIFT 28 00918 #define AIPS_PACRC_WP0_MASK 0x20000000u 00919 #define AIPS_PACRC_WP0_SHIFT 29 00920 #define AIPS_PACRC_SP0_MASK 0x40000000u 00921 #define AIPS_PACRC_SP0_SHIFT 30 00922 /* PACRD Bit Fields */ 00923 #define AIPS_PACRD_TP7_MASK 0x1u 00924 #define AIPS_PACRD_TP7_SHIFT 0 00925 #define AIPS_PACRD_WP7_MASK 0x2u 00926 #define AIPS_PACRD_WP7_SHIFT 1 00927 #define AIPS_PACRD_SP7_MASK 0x4u 00928 #define AIPS_PACRD_SP7_SHIFT 2 00929 #define AIPS_PACRD_TP6_MASK 0x10u 00930 #define AIPS_PACRD_TP6_SHIFT 4 00931 #define AIPS_PACRD_WP6_MASK 0x20u 00932 #define AIPS_PACRD_WP6_SHIFT 5 00933 #define AIPS_PACRD_SP6_MASK 0x40u 00934 #define AIPS_PACRD_SP6_SHIFT 6 00935 #define AIPS_PACRD_TP5_MASK 0x100u 00936 #define AIPS_PACRD_TP5_SHIFT 8 00937 #define AIPS_PACRD_WP5_MASK 0x200u 00938 #define AIPS_PACRD_WP5_SHIFT 9 00939 #define AIPS_PACRD_SP5_MASK 0x400u 00940 #define AIPS_PACRD_SP5_SHIFT 10 00941 #define AIPS_PACRD_TP4_MASK 0x1000u 00942 #define AIPS_PACRD_TP4_SHIFT 12 00943 #define AIPS_PACRD_WP4_MASK 0x2000u 00944 #define AIPS_PACRD_WP4_SHIFT 13 00945 #define AIPS_PACRD_SP4_MASK 0x4000u 00946 #define AIPS_PACRD_SP4_SHIFT 14 00947 #define AIPS_PACRD_TP3_MASK 0x10000u 00948 #define AIPS_PACRD_TP3_SHIFT 16 00949 #define AIPS_PACRD_WP3_MASK 0x20000u 00950 #define AIPS_PACRD_WP3_SHIFT 17 00951 #define AIPS_PACRD_SP3_MASK 0x40000u 00952 #define AIPS_PACRD_SP3_SHIFT 18 00953 #define AIPS_PACRD_TP2_MASK 0x100000u 00954 #define AIPS_PACRD_TP2_SHIFT 20 00955 #define AIPS_PACRD_WP2_MASK 0x200000u 00956 #define AIPS_PACRD_WP2_SHIFT 21 00957 #define AIPS_PACRD_SP2_MASK 0x400000u 00958 #define AIPS_PACRD_SP2_SHIFT 22 00959 #define AIPS_PACRD_TP1_MASK 0x1000000u 00960 #define AIPS_PACRD_TP1_SHIFT 24 00961 #define AIPS_PACRD_WP1_MASK 0x2000000u 00962 #define AIPS_PACRD_WP1_SHIFT 25 00963 #define AIPS_PACRD_SP1_MASK 0x4000000u 00964 #define AIPS_PACRD_SP1_SHIFT 26 00965 #define AIPS_PACRD_TP0_MASK 0x10000000u 00966 #define AIPS_PACRD_TP0_SHIFT 28 00967 #define AIPS_PACRD_WP0_MASK 0x20000000u 00968 #define AIPS_PACRD_WP0_SHIFT 29 00969 #define AIPS_PACRD_SP0_MASK 0x40000000u 00970 #define AIPS_PACRD_SP0_SHIFT 30 00971 /* PACRE Bit Fields */ 00972 #define AIPS_PACRE_TP7_MASK 0x1u 00973 #define AIPS_PACRE_TP7_SHIFT 0 00974 #define AIPS_PACRE_WP7_MASK 0x2u 00975 #define AIPS_PACRE_WP7_SHIFT 1 00976 #define AIPS_PACRE_SP7_MASK 0x4u 00977 #define AIPS_PACRE_SP7_SHIFT 2 00978 #define AIPS_PACRE_TP6_MASK 0x10u 00979 #define AIPS_PACRE_TP6_SHIFT 4 00980 #define AIPS_PACRE_WP6_MASK 0x20u 00981 #define AIPS_PACRE_WP6_SHIFT 5 00982 #define AIPS_PACRE_SP6_MASK 0x40u 00983 #define AIPS_PACRE_SP6_SHIFT 6 00984 #define AIPS_PACRE_TP5_MASK 0x100u 00985 #define AIPS_PACRE_TP5_SHIFT 8 00986 #define AIPS_PACRE_WP5_MASK 0x200u 00987 #define AIPS_PACRE_WP5_SHIFT 9 00988 #define AIPS_PACRE_SP5_MASK 0x400u 00989 #define AIPS_PACRE_SP5_SHIFT 10 00990 #define AIPS_PACRE_TP4_MASK 0x1000u 00991 #define AIPS_PACRE_TP4_SHIFT 12 00992 #define AIPS_PACRE_WP4_MASK 0x2000u 00993 #define AIPS_PACRE_WP4_SHIFT 13 00994 #define AIPS_PACRE_SP4_MASK 0x4000u 00995 #define AIPS_PACRE_SP4_SHIFT 14 00996 #define AIPS_PACRE_TP3_MASK 0x10000u 00997 #define AIPS_PACRE_TP3_SHIFT 16 00998 #define AIPS_PACRE_WP3_MASK 0x20000u 00999 #define AIPS_PACRE_WP3_SHIFT 17 01000 #define AIPS_PACRE_SP3_MASK 0x40000u 01001 #define AIPS_PACRE_SP3_SHIFT 18 01002 #define AIPS_PACRE_TP2_MASK 0x100000u 01003 #define AIPS_PACRE_TP2_SHIFT 20 01004 #define AIPS_PACRE_WP2_MASK 0x200000u 01005 #define AIPS_PACRE_WP2_SHIFT 21 01006 #define AIPS_PACRE_SP2_MASK 0x400000u 01007 #define AIPS_PACRE_SP2_SHIFT 22 01008 #define AIPS_PACRE_TP1_MASK 0x1000000u 01009 #define AIPS_PACRE_TP1_SHIFT 24 01010 #define AIPS_PACRE_WP1_MASK 0x2000000u 01011 #define AIPS_PACRE_WP1_SHIFT 25 01012 #define AIPS_PACRE_SP1_MASK 0x4000000u 01013 #define AIPS_PACRE_SP1_SHIFT 26 01014 #define AIPS_PACRE_TP0_MASK 0x10000000u 01015 #define AIPS_PACRE_TP0_SHIFT 28 01016 #define AIPS_PACRE_WP0_MASK 0x20000000u 01017 #define AIPS_PACRE_WP0_SHIFT 29 01018 #define AIPS_PACRE_SP0_MASK 0x40000000u 01019 #define AIPS_PACRE_SP0_SHIFT 30 01020 /* PACRF Bit Fields */ 01021 #define AIPS_PACRF_TP7_MASK 0x1u 01022 #define AIPS_PACRF_TP7_SHIFT 0 01023 #define AIPS_PACRF_WP7_MASK 0x2u 01024 #define AIPS_PACRF_WP7_SHIFT 1 01025 #define AIPS_PACRF_SP7_MASK 0x4u 01026 #define AIPS_PACRF_SP7_SHIFT 2 01027 #define AIPS_PACRF_TP6_MASK 0x10u 01028 #define AIPS_PACRF_TP6_SHIFT 4 01029 #define AIPS_PACRF_WP6_MASK 0x20u 01030 #define AIPS_PACRF_WP6_SHIFT 5 01031 #define AIPS_PACRF_SP6_MASK 0x40u 01032 #define AIPS_PACRF_SP6_SHIFT 6 01033 #define AIPS_PACRF_TP5_MASK 0x100u 01034 #define AIPS_PACRF_TP5_SHIFT 8 01035 #define AIPS_PACRF_WP5_MASK 0x200u 01036 #define AIPS_PACRF_WP5_SHIFT 9 01037 #define AIPS_PACRF_SP5_MASK 0x400u 01038 #define AIPS_PACRF_SP5_SHIFT 10 01039 #define AIPS_PACRF_TP4_MASK 0x1000u 01040 #define AIPS_PACRF_TP4_SHIFT 12 01041 #define AIPS_PACRF_WP4_MASK 0x2000u 01042 #define AIPS_PACRF_WP4_SHIFT 13 01043 #define AIPS_PACRF_SP4_MASK 0x4000u 01044 #define AIPS_PACRF_SP4_SHIFT 14 01045 #define AIPS_PACRF_TP3_MASK 0x10000u 01046 #define AIPS_PACRF_TP3_SHIFT 16 01047 #define AIPS_PACRF_WP3_MASK 0x20000u 01048 #define AIPS_PACRF_WP3_SHIFT 17 01049 #define AIPS_PACRF_SP3_MASK 0x40000u 01050 #define AIPS_PACRF_SP3_SHIFT 18 01051 #define AIPS_PACRF_TP2_MASK 0x100000u 01052 #define AIPS_PACRF_TP2_SHIFT 20 01053 #define AIPS_PACRF_WP2_MASK 0x200000u 01054 #define AIPS_PACRF_WP2_SHIFT 21 01055 #define AIPS_PACRF_SP2_MASK 0x400000u 01056 #define AIPS_PACRF_SP2_SHIFT 22 01057 #define AIPS_PACRF_TP1_MASK 0x1000000u 01058 #define AIPS_PACRF_TP1_SHIFT 24 01059 #define AIPS_PACRF_WP1_MASK 0x2000000u 01060 #define AIPS_PACRF_WP1_SHIFT 25 01061 #define AIPS_PACRF_SP1_MASK 0x4000000u 01062 #define AIPS_PACRF_SP1_SHIFT 26 01063 #define AIPS_PACRF_TP0_MASK 0x10000000u 01064 #define AIPS_PACRF_TP0_SHIFT 28 01065 #define AIPS_PACRF_WP0_MASK 0x20000000u 01066 #define AIPS_PACRF_WP0_SHIFT 29 01067 #define AIPS_PACRF_SP0_MASK 0x40000000u 01068 #define AIPS_PACRF_SP0_SHIFT 30 01069 /* PACRG Bit Fields */ 01070 #define AIPS_PACRG_TP7_MASK 0x1u 01071 #define AIPS_PACRG_TP7_SHIFT 0 01072 #define AIPS_PACRG_WP7_MASK 0x2u 01073 #define AIPS_PACRG_WP7_SHIFT 1 01074 #define AIPS_PACRG_SP7_MASK 0x4u 01075 #define AIPS_PACRG_SP7_SHIFT 2 01076 #define AIPS_PACRG_TP6_MASK 0x10u 01077 #define AIPS_PACRG_TP6_SHIFT 4 01078 #define AIPS_PACRG_WP6_MASK 0x20u 01079 #define AIPS_PACRG_WP6_SHIFT 5 01080 #define AIPS_PACRG_SP6_MASK 0x40u 01081 #define AIPS_PACRG_SP6_SHIFT 6 01082 #define AIPS_PACRG_TP5_MASK 0x100u 01083 #define AIPS_PACRG_TP5_SHIFT 8 01084 #define AIPS_PACRG_WP5_MASK 0x200u 01085 #define AIPS_PACRG_WP5_SHIFT 9 01086 #define AIPS_PACRG_SP5_MASK 0x400u 01087 #define AIPS_PACRG_SP5_SHIFT 10 01088 #define AIPS_PACRG_TP4_MASK 0x1000u 01089 #define AIPS_PACRG_TP4_SHIFT 12 01090 #define AIPS_PACRG_WP4_MASK 0x2000u 01091 #define AIPS_PACRG_WP4_SHIFT 13 01092 #define AIPS_PACRG_SP4_MASK 0x4000u 01093 #define AIPS_PACRG_SP4_SHIFT 14 01094 #define AIPS_PACRG_TP3_MASK 0x10000u 01095 #define AIPS_PACRG_TP3_SHIFT 16 01096 #define AIPS_PACRG_WP3_MASK 0x20000u 01097 #define AIPS_PACRG_WP3_SHIFT 17 01098 #define AIPS_PACRG_SP3_MASK 0x40000u 01099 #define AIPS_PACRG_SP3_SHIFT 18 01100 #define AIPS_PACRG_TP2_MASK 0x100000u 01101 #define AIPS_PACRG_TP2_SHIFT 20 01102 #define AIPS_PACRG_WP2_MASK 0x200000u 01103 #define AIPS_PACRG_WP2_SHIFT 21 01104 #define AIPS_PACRG_SP2_MASK 0x400000u 01105 #define AIPS_PACRG_SP2_SHIFT 22 01106 #define AIPS_PACRG_TP1_MASK 0x1000000u 01107 #define AIPS_PACRG_TP1_SHIFT 24 01108 #define AIPS_PACRG_WP1_MASK 0x2000000u 01109 #define AIPS_PACRG_WP1_SHIFT 25 01110 #define AIPS_PACRG_SP1_MASK 0x4000000u 01111 #define AIPS_PACRG_SP1_SHIFT 26 01112 #define AIPS_PACRG_TP0_MASK 0x10000000u 01113 #define AIPS_PACRG_TP0_SHIFT 28 01114 #define AIPS_PACRG_WP0_MASK 0x20000000u 01115 #define AIPS_PACRG_WP0_SHIFT 29 01116 #define AIPS_PACRG_SP0_MASK 0x40000000u 01117 #define AIPS_PACRG_SP0_SHIFT 30 01118 /* PACRH Bit Fields */ 01119 #define AIPS_PACRH_TP7_MASK 0x1u 01120 #define AIPS_PACRH_TP7_SHIFT 0 01121 #define AIPS_PACRH_WP7_MASK 0x2u 01122 #define AIPS_PACRH_WP7_SHIFT 1 01123 #define AIPS_PACRH_SP7_MASK 0x4u 01124 #define AIPS_PACRH_SP7_SHIFT 2 01125 #define AIPS_PACRH_TP6_MASK 0x10u 01126 #define AIPS_PACRH_TP6_SHIFT 4 01127 #define AIPS_PACRH_WP6_MASK 0x20u 01128 #define AIPS_PACRH_WP6_SHIFT 5 01129 #define AIPS_PACRH_SP6_MASK 0x40u 01130 #define AIPS_PACRH_SP6_SHIFT 6 01131 #define AIPS_PACRH_TP5_MASK 0x100u 01132 #define AIPS_PACRH_TP5_SHIFT 8 01133 #define AIPS_PACRH_WP5_MASK 0x200u 01134 #define AIPS_PACRH_WP5_SHIFT 9 01135 #define AIPS_PACRH_SP5_MASK 0x400u 01136 #define AIPS_PACRH_SP5_SHIFT 10 01137 #define AIPS_PACRH_TP4_MASK 0x1000u 01138 #define AIPS_PACRH_TP4_SHIFT 12 01139 #define AIPS_PACRH_WP4_MASK 0x2000u 01140 #define AIPS_PACRH_WP4_SHIFT 13 01141 #define AIPS_PACRH_SP4_MASK 0x4000u 01142 #define AIPS_PACRH_SP4_SHIFT 14 01143 #define AIPS_PACRH_TP3_MASK 0x10000u 01144 #define AIPS_PACRH_TP3_SHIFT 16 01145 #define AIPS_PACRH_WP3_MASK 0x20000u 01146 #define AIPS_PACRH_WP3_SHIFT 17 01147 #define AIPS_PACRH_SP3_MASK 0x40000u 01148 #define AIPS_PACRH_SP3_SHIFT 18 01149 #define AIPS_PACRH_TP2_MASK 0x100000u 01150 #define AIPS_PACRH_TP2_SHIFT 20 01151 #define AIPS_PACRH_WP2_MASK 0x200000u 01152 #define AIPS_PACRH_WP2_SHIFT 21 01153 #define AIPS_PACRH_SP2_MASK 0x400000u 01154 #define AIPS_PACRH_SP2_SHIFT 22 01155 #define AIPS_PACRH_TP1_MASK 0x1000000u 01156 #define AIPS_PACRH_TP1_SHIFT 24 01157 #define AIPS_PACRH_WP1_MASK 0x2000000u 01158 #define AIPS_PACRH_WP1_SHIFT 25 01159 #define AIPS_PACRH_SP1_MASK 0x4000000u 01160 #define AIPS_PACRH_SP1_SHIFT 26 01161 #define AIPS_PACRH_TP0_MASK 0x10000000u 01162 #define AIPS_PACRH_TP0_SHIFT 28 01163 #define AIPS_PACRH_WP0_MASK 0x20000000u 01164 #define AIPS_PACRH_WP0_SHIFT 29 01165 #define AIPS_PACRH_SP0_MASK 0x40000000u 01166 #define AIPS_PACRH_SP0_SHIFT 30 01167 /* PACRI Bit Fields */ 01168 #define AIPS_PACRI_TP7_MASK 0x1u 01169 #define AIPS_PACRI_TP7_SHIFT 0 01170 #define AIPS_PACRI_WP7_MASK 0x2u 01171 #define AIPS_PACRI_WP7_SHIFT 1 01172 #define AIPS_PACRI_SP7_MASK 0x4u 01173 #define AIPS_PACRI_SP7_SHIFT 2 01174 #define AIPS_PACRI_TP6_MASK 0x10u 01175 #define AIPS_PACRI_TP6_SHIFT 4 01176 #define AIPS_PACRI_WP6_MASK 0x20u 01177 #define AIPS_PACRI_WP6_SHIFT 5 01178 #define AIPS_PACRI_SP6_MASK 0x40u 01179 #define AIPS_PACRI_SP6_SHIFT 6 01180 #define AIPS_PACRI_TP5_MASK 0x100u 01181 #define AIPS_PACRI_TP5_SHIFT 8 01182 #define AIPS_PACRI_WP5_MASK 0x200u 01183 #define AIPS_PACRI_WP5_SHIFT 9 01184 #define AIPS_PACRI_SP5_MASK 0x400u 01185 #define AIPS_PACRI_SP5_SHIFT 10 01186 #define AIPS_PACRI_TP4_MASK 0x1000u 01187 #define AIPS_PACRI_TP4_SHIFT 12 01188 #define AIPS_PACRI_WP4_MASK 0x2000u 01189 #define AIPS_PACRI_WP4_SHIFT 13 01190 #define AIPS_PACRI_SP4_MASK 0x4000u 01191 #define AIPS_PACRI_SP4_SHIFT 14 01192 #define AIPS_PACRI_TP3_MASK 0x10000u 01193 #define AIPS_PACRI_TP3_SHIFT 16 01194 #define AIPS_PACRI_WP3_MASK 0x20000u 01195 #define AIPS_PACRI_WP3_SHIFT 17 01196 #define AIPS_PACRI_SP3_MASK 0x40000u 01197 #define AIPS_PACRI_SP3_SHIFT 18 01198 #define AIPS_PACRI_TP2_MASK 0x100000u 01199 #define AIPS_PACRI_TP2_SHIFT 20 01200 #define AIPS_PACRI_WP2_MASK 0x200000u 01201 #define AIPS_PACRI_WP2_SHIFT 21 01202 #define AIPS_PACRI_SP2_MASK 0x400000u 01203 #define AIPS_PACRI_SP2_SHIFT 22 01204 #define AIPS_PACRI_TP1_MASK 0x1000000u 01205 #define AIPS_PACRI_TP1_SHIFT 24 01206 #define AIPS_PACRI_WP1_MASK 0x2000000u 01207 #define AIPS_PACRI_WP1_SHIFT 25 01208 #define AIPS_PACRI_SP1_MASK 0x4000000u 01209 #define AIPS_PACRI_SP1_SHIFT 26 01210 #define AIPS_PACRI_TP0_MASK 0x10000000u 01211 #define AIPS_PACRI_TP0_SHIFT 28 01212 #define AIPS_PACRI_WP0_MASK 0x20000000u 01213 #define AIPS_PACRI_WP0_SHIFT 29 01214 #define AIPS_PACRI_SP0_MASK 0x40000000u 01215 #define AIPS_PACRI_SP0_SHIFT 30 01216 /* PACRJ Bit Fields */ 01217 #define AIPS_PACRJ_TP7_MASK 0x1u 01218 #define AIPS_PACRJ_TP7_SHIFT 0 01219 #define AIPS_PACRJ_WP7_MASK 0x2u 01220 #define AIPS_PACRJ_WP7_SHIFT 1 01221 #define AIPS_PACRJ_SP7_MASK 0x4u 01222 #define AIPS_PACRJ_SP7_SHIFT 2 01223 #define AIPS_PACRJ_TP6_MASK 0x10u 01224 #define AIPS_PACRJ_TP6_SHIFT 4 01225 #define AIPS_PACRJ_WP6_MASK 0x20u 01226 #define AIPS_PACRJ_WP6_SHIFT 5 01227 #define AIPS_PACRJ_SP6_MASK 0x40u 01228 #define AIPS_PACRJ_SP6_SHIFT 6 01229 #define AIPS_PACRJ_TP5_MASK 0x100u 01230 #define AIPS_PACRJ_TP5_SHIFT 8 01231 #define AIPS_PACRJ_WP5_MASK 0x200u 01232 #define AIPS_PACRJ_WP5_SHIFT 9 01233 #define AIPS_PACRJ_SP5_MASK 0x400u 01234 #define AIPS_PACRJ_SP5_SHIFT 10 01235 #define AIPS_PACRJ_TP4_MASK 0x1000u 01236 #define AIPS_PACRJ_TP4_SHIFT 12 01237 #define AIPS_PACRJ_WP4_MASK 0x2000u 01238 #define AIPS_PACRJ_WP4_SHIFT 13 01239 #define AIPS_PACRJ_SP4_MASK 0x4000u 01240 #define AIPS_PACRJ_SP4_SHIFT 14 01241 #define AIPS_PACRJ_TP3_MASK 0x10000u 01242 #define AIPS_PACRJ_TP3_SHIFT 16 01243 #define AIPS_PACRJ_WP3_MASK 0x20000u 01244 #define AIPS_PACRJ_WP3_SHIFT 17 01245 #define AIPS_PACRJ_SP3_MASK 0x40000u 01246 #define AIPS_PACRJ_SP3_SHIFT 18 01247 #define AIPS_PACRJ_TP2_MASK 0x100000u 01248 #define AIPS_PACRJ_TP2_SHIFT 20 01249 #define AIPS_PACRJ_WP2_MASK 0x200000u 01250 #define AIPS_PACRJ_WP2_SHIFT 21 01251 #define AIPS_PACRJ_SP2_MASK 0x400000u 01252 #define AIPS_PACRJ_SP2_SHIFT 22 01253 #define AIPS_PACRJ_TP1_MASK 0x1000000u 01254 #define AIPS_PACRJ_TP1_SHIFT 24 01255 #define AIPS_PACRJ_WP1_MASK 0x2000000u 01256 #define AIPS_PACRJ_WP1_SHIFT 25 01257 #define AIPS_PACRJ_SP1_MASK 0x4000000u 01258 #define AIPS_PACRJ_SP1_SHIFT 26 01259 #define AIPS_PACRJ_TP0_MASK 0x10000000u 01260 #define AIPS_PACRJ_TP0_SHIFT 28 01261 #define AIPS_PACRJ_WP0_MASK 0x20000000u 01262 #define AIPS_PACRJ_WP0_SHIFT 29 01263 #define AIPS_PACRJ_SP0_MASK 0x40000000u 01264 #define AIPS_PACRJ_SP0_SHIFT 30 01265 /* PACRK Bit Fields */ 01266 #define AIPS_PACRK_TP7_MASK 0x1u 01267 #define AIPS_PACRK_TP7_SHIFT 0 01268 #define AIPS_PACRK_WP7_MASK 0x2u 01269 #define AIPS_PACRK_WP7_SHIFT 1 01270 #define AIPS_PACRK_SP7_MASK 0x4u 01271 #define AIPS_PACRK_SP7_SHIFT 2 01272 #define AIPS_PACRK_TP6_MASK 0x10u 01273 #define AIPS_PACRK_TP6_SHIFT 4 01274 #define AIPS_PACRK_WP6_MASK 0x20u 01275 #define AIPS_PACRK_WP6_SHIFT 5 01276 #define AIPS_PACRK_SP6_MASK 0x40u 01277 #define AIPS_PACRK_SP6_SHIFT 6 01278 #define AIPS_PACRK_TP5_MASK 0x100u 01279 #define AIPS_PACRK_TP5_SHIFT 8 01280 #define AIPS_PACRK_WP5_MASK 0x200u 01281 #define AIPS_PACRK_WP5_SHIFT 9 01282 #define AIPS_PACRK_SP5_MASK 0x400u 01283 #define AIPS_PACRK_SP5_SHIFT 10 01284 #define AIPS_PACRK_TP4_MASK 0x1000u 01285 #define AIPS_PACRK_TP4_SHIFT 12 01286 #define AIPS_PACRK_WP4_MASK 0x2000u 01287 #define AIPS_PACRK_WP4_SHIFT 13 01288 #define AIPS_PACRK_SP4_MASK 0x4000u 01289 #define AIPS_PACRK_SP4_SHIFT 14 01290 #define AIPS_PACRK_TP3_MASK 0x10000u 01291 #define AIPS_PACRK_TP3_SHIFT 16 01292 #define AIPS_PACRK_WP3_MASK 0x20000u 01293 #define AIPS_PACRK_WP3_SHIFT 17 01294 #define AIPS_PACRK_SP3_MASK 0x40000u 01295 #define AIPS_PACRK_SP3_SHIFT 18 01296 #define AIPS_PACRK_TP2_MASK 0x100000u 01297 #define AIPS_PACRK_TP2_SHIFT 20 01298 #define AIPS_PACRK_WP2_MASK 0x200000u 01299 #define AIPS_PACRK_WP2_SHIFT 21 01300 #define AIPS_PACRK_SP2_MASK 0x400000u 01301 #define AIPS_PACRK_SP2_SHIFT 22 01302 #define AIPS_PACRK_TP1_MASK 0x1000000u 01303 #define AIPS_PACRK_TP1_SHIFT 24 01304 #define AIPS_PACRK_WP1_MASK 0x2000000u 01305 #define AIPS_PACRK_WP1_SHIFT 25 01306 #define AIPS_PACRK_SP1_MASK 0x4000000u 01307 #define AIPS_PACRK_SP1_SHIFT 26 01308 #define AIPS_PACRK_TP0_MASK 0x10000000u 01309 #define AIPS_PACRK_TP0_SHIFT 28 01310 #define AIPS_PACRK_WP0_MASK 0x20000000u 01311 #define AIPS_PACRK_WP0_SHIFT 29 01312 #define AIPS_PACRK_SP0_MASK 0x40000000u 01313 #define AIPS_PACRK_SP0_SHIFT 30 01314 /* PACRL Bit Fields */ 01315 #define AIPS_PACRL_TP7_MASK 0x1u 01316 #define AIPS_PACRL_TP7_SHIFT 0 01317 #define AIPS_PACRL_WP7_MASK 0x2u 01318 #define AIPS_PACRL_WP7_SHIFT 1 01319 #define AIPS_PACRL_SP7_MASK 0x4u 01320 #define AIPS_PACRL_SP7_SHIFT 2 01321 #define AIPS_PACRL_TP6_MASK 0x10u 01322 #define AIPS_PACRL_TP6_SHIFT 4 01323 #define AIPS_PACRL_WP6_MASK 0x20u 01324 #define AIPS_PACRL_WP6_SHIFT 5 01325 #define AIPS_PACRL_SP6_MASK 0x40u 01326 #define AIPS_PACRL_SP6_SHIFT 6 01327 #define AIPS_PACRL_TP5_MASK 0x100u 01328 #define AIPS_PACRL_TP5_SHIFT 8 01329 #define AIPS_PACRL_WP5_MASK 0x200u 01330 #define AIPS_PACRL_WP5_SHIFT 9 01331 #define AIPS_PACRL_SP5_MASK 0x400u 01332 #define AIPS_PACRL_SP5_SHIFT 10 01333 #define AIPS_PACRL_TP4_MASK 0x1000u 01334 #define AIPS_PACRL_TP4_SHIFT 12 01335 #define AIPS_PACRL_WP4_MASK 0x2000u 01336 #define AIPS_PACRL_WP4_SHIFT 13 01337 #define AIPS_PACRL_SP4_MASK 0x4000u 01338 #define AIPS_PACRL_SP4_SHIFT 14 01339 #define AIPS_PACRL_TP3_MASK 0x10000u 01340 #define AIPS_PACRL_TP3_SHIFT 16 01341 #define AIPS_PACRL_WP3_MASK 0x20000u 01342 #define AIPS_PACRL_WP3_SHIFT 17 01343 #define AIPS_PACRL_SP3_MASK 0x40000u 01344 #define AIPS_PACRL_SP3_SHIFT 18 01345 #define AIPS_PACRL_TP2_MASK 0x100000u 01346 #define AIPS_PACRL_TP2_SHIFT 20 01347 #define AIPS_PACRL_WP2_MASK 0x200000u 01348 #define AIPS_PACRL_WP2_SHIFT 21 01349 #define AIPS_PACRL_SP2_MASK 0x400000u 01350 #define AIPS_PACRL_SP2_SHIFT 22 01351 #define AIPS_PACRL_TP1_MASK 0x1000000u 01352 #define AIPS_PACRL_TP1_SHIFT 24 01353 #define AIPS_PACRL_WP1_MASK 0x2000000u 01354 #define AIPS_PACRL_WP1_SHIFT 25 01355 #define AIPS_PACRL_SP1_MASK 0x4000000u 01356 #define AIPS_PACRL_SP1_SHIFT 26 01357 #define AIPS_PACRL_TP0_MASK 0x10000000u 01358 #define AIPS_PACRL_TP0_SHIFT 28 01359 #define AIPS_PACRL_WP0_MASK 0x20000000u 01360 #define AIPS_PACRL_WP0_SHIFT 29 01361 #define AIPS_PACRL_SP0_MASK 0x40000000u 01362 #define AIPS_PACRL_SP0_SHIFT 30 01363 /* PACRM Bit Fields */ 01364 #define AIPS_PACRM_TP7_MASK 0x1u 01365 #define AIPS_PACRM_TP7_SHIFT 0 01366 #define AIPS_PACRM_WP7_MASK 0x2u 01367 #define AIPS_PACRM_WP7_SHIFT 1 01368 #define AIPS_PACRM_SP7_MASK 0x4u 01369 #define AIPS_PACRM_SP7_SHIFT 2 01370 #define AIPS_PACRM_TP6_MASK 0x10u 01371 #define AIPS_PACRM_TP6_SHIFT 4 01372 #define AIPS_PACRM_WP6_MASK 0x20u 01373 #define AIPS_PACRM_WP6_SHIFT 5 01374 #define AIPS_PACRM_SP6_MASK 0x40u 01375 #define AIPS_PACRM_SP6_SHIFT 6 01376 #define AIPS_PACRM_TP5_MASK 0x100u 01377 #define AIPS_PACRM_TP5_SHIFT 8 01378 #define AIPS_PACRM_WP5_MASK 0x200u 01379 #define AIPS_PACRM_WP5_SHIFT 9 01380 #define AIPS_PACRM_SP5_MASK 0x400u 01381 #define AIPS_PACRM_SP5_SHIFT 10 01382 #define AIPS_PACRM_TP4_MASK 0x1000u 01383 #define AIPS_PACRM_TP4_SHIFT 12 01384 #define AIPS_PACRM_WP4_MASK 0x2000u 01385 #define AIPS_PACRM_WP4_SHIFT 13 01386 #define AIPS_PACRM_SP4_MASK 0x4000u 01387 #define AIPS_PACRM_SP4_SHIFT 14 01388 #define AIPS_PACRM_TP3_MASK 0x10000u 01389 #define AIPS_PACRM_TP3_SHIFT 16 01390 #define AIPS_PACRM_WP3_MASK 0x20000u 01391 #define AIPS_PACRM_WP3_SHIFT 17 01392 #define AIPS_PACRM_SP3_MASK 0x40000u 01393 #define AIPS_PACRM_SP3_SHIFT 18 01394 #define AIPS_PACRM_TP2_MASK 0x100000u 01395 #define AIPS_PACRM_TP2_SHIFT 20 01396 #define AIPS_PACRM_WP2_MASK 0x200000u 01397 #define AIPS_PACRM_WP2_SHIFT 21 01398 #define AIPS_PACRM_SP2_MASK 0x400000u 01399 #define AIPS_PACRM_SP2_SHIFT 22 01400 #define AIPS_PACRM_TP1_MASK 0x1000000u 01401 #define AIPS_PACRM_TP1_SHIFT 24 01402 #define AIPS_PACRM_WP1_MASK 0x2000000u 01403 #define AIPS_PACRM_WP1_SHIFT 25 01404 #define AIPS_PACRM_SP1_MASK 0x4000000u 01405 #define AIPS_PACRM_SP1_SHIFT 26 01406 #define AIPS_PACRM_TP0_MASK 0x10000000u 01407 #define AIPS_PACRM_TP0_SHIFT 28 01408 #define AIPS_PACRM_WP0_MASK 0x20000000u 01409 #define AIPS_PACRM_WP0_SHIFT 29 01410 #define AIPS_PACRM_SP0_MASK 0x40000000u 01411 #define AIPS_PACRM_SP0_SHIFT 30 01412 /* PACRN Bit Fields */ 01413 #define AIPS_PACRN_TP7_MASK 0x1u 01414 #define AIPS_PACRN_TP7_SHIFT 0 01415 #define AIPS_PACRN_WP7_MASK 0x2u 01416 #define AIPS_PACRN_WP7_SHIFT 1 01417 #define AIPS_PACRN_SP7_MASK 0x4u 01418 #define AIPS_PACRN_SP7_SHIFT 2 01419 #define AIPS_PACRN_TP6_MASK 0x10u 01420 #define AIPS_PACRN_TP6_SHIFT 4 01421 #define AIPS_PACRN_WP6_MASK 0x20u 01422 #define AIPS_PACRN_WP6_SHIFT 5 01423 #define AIPS_PACRN_SP6_MASK 0x40u 01424 #define AIPS_PACRN_SP6_SHIFT 6 01425 #define AIPS_PACRN_TP5_MASK 0x100u 01426 #define AIPS_PACRN_TP5_SHIFT 8 01427 #define AIPS_PACRN_WP5_MASK 0x200u 01428 #define AIPS_PACRN_WP5_SHIFT 9 01429 #define AIPS_PACRN_SP5_MASK 0x400u 01430 #define AIPS_PACRN_SP5_SHIFT 10 01431 #define AIPS_PACRN_TP4_MASK 0x1000u 01432 #define AIPS_PACRN_TP4_SHIFT 12 01433 #define AIPS_PACRN_WP4_MASK 0x2000u 01434 #define AIPS_PACRN_WP4_SHIFT 13 01435 #define AIPS_PACRN_SP4_MASK 0x4000u 01436 #define AIPS_PACRN_SP4_SHIFT 14 01437 #define AIPS_PACRN_TP3_MASK 0x10000u 01438 #define AIPS_PACRN_TP3_SHIFT 16 01439 #define AIPS_PACRN_WP3_MASK 0x20000u 01440 #define AIPS_PACRN_WP3_SHIFT 17 01441 #define AIPS_PACRN_SP3_MASK 0x40000u 01442 #define AIPS_PACRN_SP3_SHIFT 18 01443 #define AIPS_PACRN_TP2_MASK 0x100000u 01444 #define AIPS_PACRN_TP2_SHIFT 20 01445 #define AIPS_PACRN_WP2_MASK 0x200000u 01446 #define AIPS_PACRN_WP2_SHIFT 21 01447 #define AIPS_PACRN_SP2_MASK 0x400000u 01448 #define AIPS_PACRN_SP2_SHIFT 22 01449 #define AIPS_PACRN_TP1_MASK 0x1000000u 01450 #define AIPS_PACRN_TP1_SHIFT 24 01451 #define AIPS_PACRN_WP1_MASK 0x2000000u 01452 #define AIPS_PACRN_WP1_SHIFT 25 01453 #define AIPS_PACRN_SP1_MASK 0x4000000u 01454 #define AIPS_PACRN_SP1_SHIFT 26 01455 #define AIPS_PACRN_TP0_MASK 0x10000000u 01456 #define AIPS_PACRN_TP0_SHIFT 28 01457 #define AIPS_PACRN_WP0_MASK 0x20000000u 01458 #define AIPS_PACRN_WP0_SHIFT 29 01459 #define AIPS_PACRN_SP0_MASK 0x40000000u 01460 #define AIPS_PACRN_SP0_SHIFT 30 01461 /* PACRO Bit Fields */ 01462 #define AIPS_PACRO_TP7_MASK 0x1u 01463 #define AIPS_PACRO_TP7_SHIFT 0 01464 #define AIPS_PACRO_WP7_MASK 0x2u 01465 #define AIPS_PACRO_WP7_SHIFT 1 01466 #define AIPS_PACRO_SP7_MASK 0x4u 01467 #define AIPS_PACRO_SP7_SHIFT 2 01468 #define AIPS_PACRO_TP6_MASK 0x10u 01469 #define AIPS_PACRO_TP6_SHIFT 4 01470 #define AIPS_PACRO_WP6_MASK 0x20u 01471 #define AIPS_PACRO_WP6_SHIFT 5 01472 #define AIPS_PACRO_SP6_MASK 0x40u 01473 #define AIPS_PACRO_SP6_SHIFT 6 01474 #define AIPS_PACRO_TP5_MASK 0x100u 01475 #define AIPS_PACRO_TP5_SHIFT 8 01476 #define AIPS_PACRO_WP5_MASK 0x200u 01477 #define AIPS_PACRO_WP5_SHIFT 9 01478 #define AIPS_PACRO_SP5_MASK 0x400u 01479 #define AIPS_PACRO_SP5_SHIFT 10 01480 #define AIPS_PACRO_TP4_MASK 0x1000u 01481 #define AIPS_PACRO_TP4_SHIFT 12 01482 #define AIPS_PACRO_WP4_MASK 0x2000u 01483 #define AIPS_PACRO_WP4_SHIFT 13 01484 #define AIPS_PACRO_SP4_MASK 0x4000u 01485 #define AIPS_PACRO_SP4_SHIFT 14 01486 #define AIPS_PACRO_TP3_MASK 0x10000u 01487 #define AIPS_PACRO_TP3_SHIFT 16 01488 #define AIPS_PACRO_WP3_MASK 0x20000u 01489 #define AIPS_PACRO_WP3_SHIFT 17 01490 #define AIPS_PACRO_SP3_MASK 0x40000u 01491 #define AIPS_PACRO_SP3_SHIFT 18 01492 #define AIPS_PACRO_TP2_MASK 0x100000u 01493 #define AIPS_PACRO_TP2_SHIFT 20 01494 #define AIPS_PACRO_WP2_MASK 0x200000u 01495 #define AIPS_PACRO_WP2_SHIFT 21 01496 #define AIPS_PACRO_SP2_MASK 0x400000u 01497 #define AIPS_PACRO_SP2_SHIFT 22 01498 #define AIPS_PACRO_TP1_MASK 0x1000000u 01499 #define AIPS_PACRO_TP1_SHIFT 24 01500 #define AIPS_PACRO_WP1_MASK 0x2000000u 01501 #define AIPS_PACRO_WP1_SHIFT 25 01502 #define AIPS_PACRO_SP1_MASK 0x4000000u 01503 #define AIPS_PACRO_SP1_SHIFT 26 01504 #define AIPS_PACRO_TP0_MASK 0x10000000u 01505 #define AIPS_PACRO_TP0_SHIFT 28 01506 #define AIPS_PACRO_WP0_MASK 0x20000000u 01507 #define AIPS_PACRO_WP0_SHIFT 29 01508 #define AIPS_PACRO_SP0_MASK 0x40000000u 01509 #define AIPS_PACRO_SP0_SHIFT 30 01510 /* PACRP Bit Fields */ 01511 #define AIPS_PACRP_TP7_MASK 0x1u 01512 #define AIPS_PACRP_TP7_SHIFT 0 01513 #define AIPS_PACRP_WP7_MASK 0x2u 01514 #define AIPS_PACRP_WP7_SHIFT 1 01515 #define AIPS_PACRP_SP7_MASK 0x4u 01516 #define AIPS_PACRP_SP7_SHIFT 2 01517 #define AIPS_PACRP_TP6_MASK 0x10u 01518 #define AIPS_PACRP_TP6_SHIFT 4 01519 #define AIPS_PACRP_WP6_MASK 0x20u 01520 #define AIPS_PACRP_WP6_SHIFT 5 01521 #define AIPS_PACRP_SP6_MASK 0x40u 01522 #define AIPS_PACRP_SP6_SHIFT 6 01523 #define AIPS_PACRP_TP5_MASK 0x100u 01524 #define AIPS_PACRP_TP5_SHIFT 8 01525 #define AIPS_PACRP_WP5_MASK 0x200u 01526 #define AIPS_PACRP_WP5_SHIFT 9 01527 #define AIPS_PACRP_SP5_MASK 0x400u 01528 #define AIPS_PACRP_SP5_SHIFT 10 01529 #define AIPS_PACRP_TP4_MASK 0x1000u 01530 #define AIPS_PACRP_TP4_SHIFT 12 01531 #define AIPS_PACRP_WP4_MASK 0x2000u 01532 #define AIPS_PACRP_WP4_SHIFT 13 01533 #define AIPS_PACRP_SP4_MASK 0x4000u 01534 #define AIPS_PACRP_SP4_SHIFT 14 01535 #define AIPS_PACRP_TP3_MASK 0x10000u 01536 #define AIPS_PACRP_TP3_SHIFT 16 01537 #define AIPS_PACRP_WP3_MASK 0x20000u 01538 #define AIPS_PACRP_WP3_SHIFT 17 01539 #define AIPS_PACRP_SP3_MASK 0x40000u 01540 #define AIPS_PACRP_SP3_SHIFT 18 01541 #define AIPS_PACRP_TP2_MASK 0x100000u 01542 #define AIPS_PACRP_TP2_SHIFT 20 01543 #define AIPS_PACRP_WP2_MASK 0x200000u 01544 #define AIPS_PACRP_WP2_SHIFT 21 01545 #define AIPS_PACRP_SP2_MASK 0x400000u 01546 #define AIPS_PACRP_SP2_SHIFT 22 01547 #define AIPS_PACRP_TP1_MASK 0x1000000u 01548 #define AIPS_PACRP_TP1_SHIFT 24 01549 #define AIPS_PACRP_WP1_MASK 0x2000000u 01550 #define AIPS_PACRP_WP1_SHIFT 25 01551 #define AIPS_PACRP_SP1_MASK 0x4000000u 01552 #define AIPS_PACRP_SP1_SHIFT 26 01553 #define AIPS_PACRP_TP0_MASK 0x10000000u 01554 #define AIPS_PACRP_TP0_SHIFT 28 01555 #define AIPS_PACRP_WP0_MASK 0x20000000u 01556 #define AIPS_PACRP_WP0_SHIFT 29 01557 #define AIPS_PACRP_SP0_MASK 0x40000000u 01558 #define AIPS_PACRP_SP0_SHIFT 30 01559 /* PACRU Bit Fields */ 01560 #define AIPS_PACRU_TP1_MASK 0x1000000u 01561 #define AIPS_PACRU_TP1_SHIFT 24 01562 #define AIPS_PACRU_WP1_MASK 0x2000000u 01563 #define AIPS_PACRU_WP1_SHIFT 25 01564 #define AIPS_PACRU_SP1_MASK 0x4000000u 01565 #define AIPS_PACRU_SP1_SHIFT 26 01566 #define AIPS_PACRU_TP0_MASK 0x10000000u 01567 #define AIPS_PACRU_TP0_SHIFT 28 01568 #define AIPS_PACRU_WP0_MASK 0x20000000u 01569 #define AIPS_PACRU_WP0_SHIFT 29 01570 #define AIPS_PACRU_SP0_MASK 0x40000000u 01571 #define AIPS_PACRU_SP0_SHIFT 30 01572 01573 /*! 01574 * @} 01575 */ /* end of group AIPS_Register_Masks */ 01576 01577 01578 /* AIPS - Peripheral instance base addresses */ 01579 /** Peripheral AIPS0 base address */ 01580 #define AIPS0_BASE (0x40000000u) 01581 /** Peripheral AIPS0 base pointer */ 01582 #define AIPS0 ((AIPS_Type *)AIPS0_BASE) 01583 #define AIPS0_BASE_PTR (AIPS0) 01584 /** Peripheral AIPS1 base address */ 01585 #define AIPS1_BASE (0x40080000u) 01586 /** Peripheral AIPS1 base pointer */ 01587 #define AIPS1 ((AIPS_Type *)AIPS1_BASE) 01588 #define AIPS1_BASE_PTR (AIPS1) 01589 /** Array initializer of AIPS peripheral base addresses */ 01590 #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE } 01591 /** Array initializer of AIPS peripheral base pointers */ 01592 #define AIPS_BASE_PTRS { AIPS0, AIPS1 } 01593 01594 /* ---------------------------------------------------------------------------- 01595 -- AIPS - Register accessor macros 01596 ---------------------------------------------------------------------------- */ 01597 01598 /*! 01599 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros 01600 * @{ 01601 */ 01602 01603 01604 /* AIPS - Register instance definitions */ 01605 /* AIPS0 */ 01606 #define AIPS0_MPRA AIPS_MPRA_REG(AIPS0) 01607 #define AIPS0_PACRA AIPS_PACRA_REG(AIPS0) 01608 #define AIPS0_PACRB AIPS_PACRB_REG(AIPS0) 01609 #define AIPS0_PACRC AIPS_PACRC_REG(AIPS0) 01610 #define AIPS0_PACRD AIPS_PACRD_REG(AIPS0) 01611 #define AIPS0_PACRE AIPS_PACRE_REG(AIPS0) 01612 #define AIPS0_PACRF AIPS_PACRF_REG(AIPS0) 01613 #define AIPS0_PACRG AIPS_PACRG_REG(AIPS0) 01614 #define AIPS0_PACRH AIPS_PACRH_REG(AIPS0) 01615 #define AIPS0_PACRI AIPS_PACRI_REG(AIPS0) 01616 #define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0) 01617 #define AIPS0_PACRK AIPS_PACRK_REG(AIPS0) 01618 #define AIPS0_PACRL AIPS_PACRL_REG(AIPS0) 01619 #define AIPS0_PACRM AIPS_PACRM_REG(AIPS0) 01620 #define AIPS0_PACRN AIPS_PACRN_REG(AIPS0) 01621 #define AIPS0_PACRO AIPS_PACRO_REG(AIPS0) 01622 #define AIPS0_PACRP AIPS_PACRP_REG(AIPS0) 01623 #define AIPS0_PACRU AIPS_PACRU_REG(AIPS0) 01624 /* AIPS1 */ 01625 #define AIPS1_MPRA AIPS_MPRA_REG(AIPS1) 01626 #define AIPS1_PACRA AIPS_PACRA_REG(AIPS1) 01627 #define AIPS1_PACRB AIPS_PACRB_REG(AIPS1) 01628 #define AIPS1_PACRC AIPS_PACRC_REG(AIPS1) 01629 #define AIPS1_PACRD AIPS_PACRD_REG(AIPS1) 01630 #define AIPS1_PACRE AIPS_PACRE_REG(AIPS1) 01631 #define AIPS1_PACRF AIPS_PACRF_REG(AIPS1) 01632 #define AIPS1_PACRG AIPS_PACRG_REG(AIPS1) 01633 #define AIPS1_PACRH AIPS_PACRH_REG(AIPS1) 01634 #define AIPS1_PACRI AIPS_PACRI_REG(AIPS1) 01635 #define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1) 01636 #define AIPS1_PACRK AIPS_PACRK_REG(AIPS1) 01637 #define AIPS1_PACRL AIPS_PACRL_REG(AIPS1) 01638 #define AIPS1_PACRM AIPS_PACRM_REG(AIPS1) 01639 #define AIPS1_PACRN AIPS_PACRN_REG(AIPS1) 01640 #define AIPS1_PACRO AIPS_PACRO_REG(AIPS1) 01641 #define AIPS1_PACRP AIPS_PACRP_REG(AIPS1) 01642 #define AIPS1_PACRU AIPS_PACRU_REG(AIPS1) 01643 01644 /*! 01645 * @} 01646 */ /* end of group AIPS_Register_Accessor_Macros */ 01647 01648 01649 /*! 01650 * @} 01651 */ /* end of group AIPS_Peripheral_Access_Layer */ 01652 01653 01654 /* ---------------------------------------------------------------------------- 01655 -- AXBS Peripheral Access Layer 01656 ---------------------------------------------------------------------------- */ 01657 01658 /*! 01659 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer 01660 * @{ 01661 */ 01662 01663 /** AXBS - Register Layout Typedef */ 01664 typedef struct { 01665 struct { /* offset: 0x0, array step: 0x100 */ 01666 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */ 01667 uint8_t RESERVED_0[12]; 01668 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ 01669 uint8_t RESERVED_1[236]; 01670 } SLAVE[5]; 01671 uint8_t RESERVED_0[768]; 01672 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ 01673 uint8_t RESERVED_1[252]; 01674 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ 01675 uint8_t RESERVED_2[252]; 01676 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ 01677 uint8_t RESERVED_3[252]; 01678 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ 01679 uint8_t RESERVED_4[252]; 01680 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ 01681 uint8_t RESERVED_5[252]; 01682 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ 01683 } AXBS_Type, *AXBS_MemMapPtr; 01684 01685 /* ---------------------------------------------------------------------------- 01686 -- AXBS - Register accessor macros 01687 ---------------------------------------------------------------------------- */ 01688 01689 /*! 01690 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros 01691 * @{ 01692 */ 01693 01694 01695 /* AXBS - Register accessors */ 01696 #define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS) 01697 #define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS) 01698 #define AXBS_MGPCR0_REG(base) ((base)->MGPCR0) 01699 #define AXBS_MGPCR1_REG(base) ((base)->MGPCR1) 01700 #define AXBS_MGPCR2_REG(base) ((base)->MGPCR2) 01701 #define AXBS_MGPCR3_REG(base) ((base)->MGPCR3) 01702 #define AXBS_MGPCR4_REG(base) ((base)->MGPCR4) 01703 #define AXBS_MGPCR5_REG(base) ((base)->MGPCR5) 01704 01705 /*! 01706 * @} 01707 */ /* end of group AXBS_Register_Accessor_Macros */ 01708 01709 01710 /* ---------------------------------------------------------------------------- 01711 -- AXBS Register Masks 01712 ---------------------------------------------------------------------------- */ 01713 01714 /*! 01715 * @addtogroup AXBS_Register_Masks AXBS Register Masks 01716 * @{ 01717 */ 01718 01719 /* PRS Bit Fields */ 01720 #define AXBS_PRS_M0_MASK 0x7u 01721 #define AXBS_PRS_M0_SHIFT 0 01722 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK) 01723 #define AXBS_PRS_M1_MASK 0x70u 01724 #define AXBS_PRS_M1_SHIFT 4 01725 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK) 01726 #define AXBS_PRS_M2_MASK 0x700u 01727 #define AXBS_PRS_M2_SHIFT 8 01728 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK) 01729 #define AXBS_PRS_M3_MASK 0x7000u 01730 #define AXBS_PRS_M3_SHIFT 12 01731 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK) 01732 #define AXBS_PRS_M4_MASK 0x70000u 01733 #define AXBS_PRS_M4_SHIFT 16 01734 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK) 01735 #define AXBS_PRS_M5_MASK 0x700000u 01736 #define AXBS_PRS_M5_SHIFT 20 01737 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK) 01738 /* CRS Bit Fields */ 01739 #define AXBS_CRS_PARK_MASK 0x7u 01740 #define AXBS_CRS_PARK_SHIFT 0 01741 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK) 01742 #define AXBS_CRS_PCTL_MASK 0x30u 01743 #define AXBS_CRS_PCTL_SHIFT 4 01744 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK) 01745 #define AXBS_CRS_ARB_MASK 0x300u 01746 #define AXBS_CRS_ARB_SHIFT 8 01747 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK) 01748 #define AXBS_CRS_HLP_MASK 0x40000000u 01749 #define AXBS_CRS_HLP_SHIFT 30 01750 #define AXBS_CRS_RO_MASK 0x80000000u 01751 #define AXBS_CRS_RO_SHIFT 31 01752 /* MGPCR0 Bit Fields */ 01753 #define AXBS_MGPCR0_AULB_MASK 0x7u 01754 #define AXBS_MGPCR0_AULB_SHIFT 0 01755 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK) 01756 /* MGPCR1 Bit Fields */ 01757 #define AXBS_MGPCR1_AULB_MASK 0x7u 01758 #define AXBS_MGPCR1_AULB_SHIFT 0 01759 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK) 01760 /* MGPCR2 Bit Fields */ 01761 #define AXBS_MGPCR2_AULB_MASK 0x7u 01762 #define AXBS_MGPCR2_AULB_SHIFT 0 01763 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK) 01764 /* MGPCR3 Bit Fields */ 01765 #define AXBS_MGPCR3_AULB_MASK 0x7u 01766 #define AXBS_MGPCR3_AULB_SHIFT 0 01767 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK) 01768 /* MGPCR4 Bit Fields */ 01769 #define AXBS_MGPCR4_AULB_MASK 0x7u 01770 #define AXBS_MGPCR4_AULB_SHIFT 0 01771 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK) 01772 /* MGPCR5 Bit Fields */ 01773 #define AXBS_MGPCR5_AULB_MASK 0x7u 01774 #define AXBS_MGPCR5_AULB_SHIFT 0 01775 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK) 01776 01777 /*! 01778 * @} 01779 */ /* end of group AXBS_Register_Masks */ 01780 01781 01782 /* AXBS - Peripheral instance base addresses */ 01783 /** Peripheral AXBS base address */ 01784 #define AXBS_BASE (0x40004000u) 01785 /** Peripheral AXBS base pointer */ 01786 #define AXBS ((AXBS_Type *)AXBS_BASE) 01787 #define AXBS_BASE_PTR (AXBS) 01788 /** Array initializer of AXBS peripheral base addresses */ 01789 #define AXBS_BASE_ADDRS { AXBS_BASE } 01790 /** Array initializer of AXBS peripheral base pointers */ 01791 #define AXBS_BASE_PTRS { AXBS } 01792 01793 /* ---------------------------------------------------------------------------- 01794 -- AXBS - Register accessor macros 01795 ---------------------------------------------------------------------------- */ 01796 01797 /*! 01798 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros 01799 * @{ 01800 */ 01801 01802 01803 /* AXBS - Register instance definitions */ 01804 /* AXBS */ 01805 #define AXBS_PRS0 AXBS_PRS_REG(AXBS,0) 01806 #define AXBS_CRS0 AXBS_CRS_REG(AXBS,0) 01807 #define AXBS_PRS1 AXBS_PRS_REG(AXBS,1) 01808 #define AXBS_CRS1 AXBS_CRS_REG(AXBS,1) 01809 #define AXBS_PRS2 AXBS_PRS_REG(AXBS,2) 01810 #define AXBS_CRS2 AXBS_CRS_REG(AXBS,2) 01811 #define AXBS_PRS3 AXBS_PRS_REG(AXBS,3) 01812 #define AXBS_CRS3 AXBS_CRS_REG(AXBS,3) 01813 #define AXBS_PRS4 AXBS_PRS_REG(AXBS,4) 01814 #define AXBS_CRS4 AXBS_CRS_REG(AXBS,4) 01815 #define AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS) 01816 #define AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS) 01817 #define AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS) 01818 #define AXBS_MGPCR3 AXBS_MGPCR3_REG(AXBS) 01819 #define AXBS_MGPCR4 AXBS_MGPCR4_REG(AXBS) 01820 #define AXBS_MGPCR5 AXBS_MGPCR5_REG(AXBS) 01821 01822 /* AXBS - Register array accessors */ 01823 #define AXBS_PRS(index) AXBS_PRS_REG(AXBS,index) 01824 #define AXBS_CRS(index) AXBS_CRS_REG(AXBS,index) 01825 01826 /*! 01827 * @} 01828 */ /* end of group AXBS_Register_Accessor_Macros */ 01829 01830 01831 /*! 01832 * @} 01833 */ /* end of group AXBS_Peripheral_Access_Layer */ 01834 01835 01836 /* ---------------------------------------------------------------------------- 01837 -- CAN Peripheral Access Layer 01838 ---------------------------------------------------------------------------- */ 01839 01840 /*! 01841 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer 01842 * @{ 01843 */ 01844 01845 /** CAN - Register Layout Typedef */ 01846 typedef struct { 01847 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ 01848 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */ 01849 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ 01850 uint8_t RESERVED_0[4]; 01851 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ 01852 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */ 01853 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */ 01854 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ 01855 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */ 01856 uint8_t RESERVED_1[4]; 01857 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ 01858 uint8_t RESERVED_2[4]; 01859 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */ 01860 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */ 01861 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */ 01862 uint8_t RESERVED_3[8]; 01863 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ 01864 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */ 01865 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ 01866 uint8_t RESERVED_4[48]; 01867 struct { /* offset: 0x80, array step: 0x10 */ 01868 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */ 01869 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */ 01870 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */ 01871 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */ 01872 } MB[16]; 01873 uint8_t RESERVED_5[1792]; 01874 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ 01875 } CAN_Type, *CAN_MemMapPtr; 01876 01877 /* ---------------------------------------------------------------------------- 01878 -- CAN - Register accessor macros 01879 ---------------------------------------------------------------------------- */ 01880 01881 /*! 01882 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros 01883 * @{ 01884 */ 01885 01886 01887 /* CAN - Register accessors */ 01888 #define CAN_MCR_REG(base) ((base)->MCR) 01889 #define CAN_CTRL1_REG(base) ((base)->CTRL1) 01890 #define CAN_TIMER_REG(base) ((base)->TIMER) 01891 #define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) 01892 #define CAN_RX14MASK_REG(base) ((base)->RX14MASK) 01893 #define CAN_RX15MASK_REG(base) ((base)->RX15MASK) 01894 #define CAN_ECR_REG(base) ((base)->ECR) 01895 #define CAN_ESR1_REG(base) ((base)->ESR1) 01896 #define CAN_IMASK1_REG(base) ((base)->IMASK1) 01897 #define CAN_IFLAG1_REG(base) ((base)->IFLAG1) 01898 #define CAN_CTRL2_REG(base) ((base)->CTRL2) 01899 #define CAN_ESR2_REG(base) ((base)->ESR2) 01900 #define CAN_CRCR_REG(base) ((base)->CRCR) 01901 #define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) 01902 #define CAN_RXFIR_REG(base) ((base)->RXFIR) 01903 #define CAN_CS_REG(base,index) ((base)->MB[index].CS) 01904 #define CAN_ID_REG(base,index) ((base)->MB[index].ID) 01905 #define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) 01906 #define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) 01907 #define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) 01908 01909 /*! 01910 * @} 01911 */ /* end of group CAN_Register_Accessor_Macros */ 01912 01913 01914 /* ---------------------------------------------------------------------------- 01915 -- CAN Register Masks 01916 ---------------------------------------------------------------------------- */ 01917 01918 /*! 01919 * @addtogroup CAN_Register_Masks CAN Register Masks 01920 * @{ 01921 */ 01922 01923 /* MCR Bit Fields */ 01924 #define CAN_MCR_MAXMB_MASK 0x7Fu 01925 #define CAN_MCR_MAXMB_SHIFT 0 01926 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK) 01927 #define CAN_MCR_IDAM_MASK 0x300u 01928 #define CAN_MCR_IDAM_SHIFT 8 01929 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK) 01930 #define CAN_MCR_AEN_MASK 0x1000u 01931 #define CAN_MCR_AEN_SHIFT 12 01932 #define CAN_MCR_LPRIOEN_MASK 0x2000u 01933 #define CAN_MCR_LPRIOEN_SHIFT 13 01934 #define CAN_MCR_IRMQ_MASK 0x10000u 01935 #define CAN_MCR_IRMQ_SHIFT 16 01936 #define CAN_MCR_SRXDIS_MASK 0x20000u 01937 #define CAN_MCR_SRXDIS_SHIFT 17 01938 #define CAN_MCR_WAKSRC_MASK 0x80000u 01939 #define CAN_MCR_WAKSRC_SHIFT 19 01940 #define CAN_MCR_LPMACK_MASK 0x100000u 01941 #define CAN_MCR_LPMACK_SHIFT 20 01942 #define CAN_MCR_WRNEN_MASK 0x200000u 01943 #define CAN_MCR_WRNEN_SHIFT 21 01944 #define CAN_MCR_SLFWAK_MASK 0x400000u 01945 #define CAN_MCR_SLFWAK_SHIFT 22 01946 #define CAN_MCR_SUPV_MASK 0x800000u 01947 #define CAN_MCR_SUPV_SHIFT 23 01948 #define CAN_MCR_FRZACK_MASK 0x1000000u 01949 #define CAN_MCR_FRZACK_SHIFT 24 01950 #define CAN_MCR_SOFTRST_MASK 0x2000000u 01951 #define CAN_MCR_SOFTRST_SHIFT 25 01952 #define CAN_MCR_WAKMSK_MASK 0x4000000u 01953 #define CAN_MCR_WAKMSK_SHIFT 26 01954 #define CAN_MCR_NOTRDY_MASK 0x8000000u 01955 #define CAN_MCR_NOTRDY_SHIFT 27 01956 #define CAN_MCR_HALT_MASK 0x10000000u 01957 #define CAN_MCR_HALT_SHIFT 28 01958 #define CAN_MCR_RFEN_MASK 0x20000000u 01959 #define CAN_MCR_RFEN_SHIFT 29 01960 #define CAN_MCR_FRZ_MASK 0x40000000u 01961 #define CAN_MCR_FRZ_SHIFT 30 01962 #define CAN_MCR_MDIS_MASK 0x80000000u 01963 #define CAN_MCR_MDIS_SHIFT 31 01964 /* CTRL1 Bit Fields */ 01965 #define CAN_CTRL1_PROPSEG_MASK 0x7u 01966 #define CAN_CTRL1_PROPSEG_SHIFT 0 01967 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK) 01968 #define CAN_CTRL1_LOM_MASK 0x8u 01969 #define CAN_CTRL1_LOM_SHIFT 3 01970 #define CAN_CTRL1_LBUF_MASK 0x10u 01971 #define CAN_CTRL1_LBUF_SHIFT 4 01972 #define CAN_CTRL1_TSYN_MASK 0x20u 01973 #define CAN_CTRL1_TSYN_SHIFT 5 01974 #define CAN_CTRL1_BOFFREC_MASK 0x40u 01975 #define CAN_CTRL1_BOFFREC_SHIFT 6 01976 #define CAN_CTRL1_SMP_MASK 0x80u 01977 #define CAN_CTRL1_SMP_SHIFT 7 01978 #define CAN_CTRL1_RWRNMSK_MASK 0x400u 01979 #define CAN_CTRL1_RWRNMSK_SHIFT 10 01980 #define CAN_CTRL1_TWRNMSK_MASK 0x800u 01981 #define CAN_CTRL1_TWRNMSK_SHIFT 11 01982 #define CAN_CTRL1_LPB_MASK 0x1000u 01983 #define CAN_CTRL1_LPB_SHIFT 12 01984 #define CAN_CTRL1_CLKSRC_MASK 0x2000u 01985 #define CAN_CTRL1_CLKSRC_SHIFT 13 01986 #define CAN_CTRL1_ERRMSK_MASK 0x4000u 01987 #define CAN_CTRL1_ERRMSK_SHIFT 14 01988 #define CAN_CTRL1_BOFFMSK_MASK 0x8000u 01989 #define CAN_CTRL1_BOFFMSK_SHIFT 15 01990 #define CAN_CTRL1_PSEG2_MASK 0x70000u 01991 #define CAN_CTRL1_PSEG2_SHIFT 16 01992 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK) 01993 #define CAN_CTRL1_PSEG1_MASK 0x380000u 01994 #define CAN_CTRL1_PSEG1_SHIFT 19 01995 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK) 01996 #define CAN_CTRL1_RJW_MASK 0xC00000u 01997 #define CAN_CTRL1_RJW_SHIFT 22 01998 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK) 01999 #define CAN_CTRL1_PRESDIV_MASK 0xFF000000u 02000 #define CAN_CTRL1_PRESDIV_SHIFT 24 02001 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK) 02002 /* TIMER Bit Fields */ 02003 #define CAN_TIMER_TIMER_MASK 0xFFFFu 02004 #define CAN_TIMER_TIMER_SHIFT 0 02005 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK) 02006 /* RXMGMASK Bit Fields */ 02007 #define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu 02008 #define CAN_RXMGMASK_MG_SHIFT 0 02009 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK) 02010 /* RX14MASK Bit Fields */ 02011 #define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu 02012 #define CAN_RX14MASK_RX14M_SHIFT 0 02013 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK) 02014 /* RX15MASK Bit Fields */ 02015 #define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu 02016 #define CAN_RX15MASK_RX15M_SHIFT 0 02017 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK) 02018 /* ECR Bit Fields */ 02019 #define CAN_ECR_TXERRCNT_MASK 0xFFu 02020 #define CAN_ECR_TXERRCNT_SHIFT 0 02021 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK) 02022 #define CAN_ECR_RXERRCNT_MASK 0xFF00u 02023 #define CAN_ECR_RXERRCNT_SHIFT 8 02024 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK) 02025 /* ESR1 Bit Fields */ 02026 #define CAN_ESR1_WAKINT_MASK 0x1u 02027 #define CAN_ESR1_WAKINT_SHIFT 0 02028 #define CAN_ESR1_ERRINT_MASK 0x2u 02029 #define CAN_ESR1_ERRINT_SHIFT 1 02030 #define CAN_ESR1_BOFFINT_MASK 0x4u 02031 #define CAN_ESR1_BOFFINT_SHIFT 2 02032 #define CAN_ESR1_RX_MASK 0x8u 02033 #define CAN_ESR1_RX_SHIFT 3 02034 #define CAN_ESR1_FLTCONF_MASK 0x30u 02035 #define CAN_ESR1_FLTCONF_SHIFT 4 02036 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK) 02037 #define CAN_ESR1_TX_MASK 0x40u 02038 #define CAN_ESR1_TX_SHIFT 6 02039 #define CAN_ESR1_IDLE_MASK 0x80u 02040 #define CAN_ESR1_IDLE_SHIFT 7 02041 #define CAN_ESR1_RXWRN_MASK 0x100u 02042 #define CAN_ESR1_RXWRN_SHIFT 8 02043 #define CAN_ESR1_TXWRN_MASK 0x200u 02044 #define CAN_ESR1_TXWRN_SHIFT 9 02045 #define CAN_ESR1_STFERR_MASK 0x400u 02046 #define CAN_ESR1_STFERR_SHIFT 10 02047 #define CAN_ESR1_FRMERR_MASK 0x800u 02048 #define CAN_ESR1_FRMERR_SHIFT 11 02049 #define CAN_ESR1_CRCERR_MASK 0x1000u 02050 #define CAN_ESR1_CRCERR_SHIFT 12 02051 #define CAN_ESR1_ACKERR_MASK 0x2000u 02052 #define CAN_ESR1_ACKERR_SHIFT 13 02053 #define CAN_ESR1_BIT0ERR_MASK 0x4000u 02054 #define CAN_ESR1_BIT0ERR_SHIFT 14 02055 #define CAN_ESR1_BIT1ERR_MASK 0x8000u 02056 #define CAN_ESR1_BIT1ERR_SHIFT 15 02057 #define CAN_ESR1_RWRNINT_MASK 0x10000u 02058 #define CAN_ESR1_RWRNINT_SHIFT 16 02059 #define CAN_ESR1_TWRNINT_MASK 0x20000u 02060 #define CAN_ESR1_TWRNINT_SHIFT 17 02061 #define CAN_ESR1_SYNCH_MASK 0x40000u 02062 #define CAN_ESR1_SYNCH_SHIFT 18 02063 /* IMASK1 Bit Fields */ 02064 #define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu 02065 #define CAN_IMASK1_BUFLM_SHIFT 0 02066 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK) 02067 /* IFLAG1 Bit Fields */ 02068 #define CAN_IFLAG1_BUF0I_MASK 0x1u 02069 #define CAN_IFLAG1_BUF0I_SHIFT 0 02070 #define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu 02071 #define CAN_IFLAG1_BUF4TO1I_SHIFT 1 02072 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK) 02073 #define CAN_IFLAG1_BUF5I_MASK 0x20u 02074 #define CAN_IFLAG1_BUF5I_SHIFT 5 02075 #define CAN_IFLAG1_BUF6I_MASK 0x40u 02076 #define CAN_IFLAG1_BUF6I_SHIFT 6 02077 #define CAN_IFLAG1_BUF7I_MASK 0x80u 02078 #define CAN_IFLAG1_BUF7I_SHIFT 7 02079 #define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u 02080 #define CAN_IFLAG1_BUF31TO8I_SHIFT 8 02081 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK) 02082 /* CTRL2 Bit Fields */ 02083 #define CAN_CTRL2_EACEN_MASK 0x10000u 02084 #define CAN_CTRL2_EACEN_SHIFT 16 02085 #define CAN_CTRL2_RRS_MASK 0x20000u 02086 #define CAN_CTRL2_RRS_SHIFT 17 02087 #define CAN_CTRL2_MRP_MASK 0x40000u 02088 #define CAN_CTRL2_MRP_SHIFT 18 02089 #define CAN_CTRL2_TASD_MASK 0xF80000u 02090 #define CAN_CTRL2_TASD_SHIFT 19 02091 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK) 02092 #define CAN_CTRL2_RFFN_MASK 0xF000000u 02093 #define CAN_CTRL2_RFFN_SHIFT 24 02094 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK) 02095 #define CAN_CTRL2_WRMFRZ_MASK 0x10000000u 02096 #define CAN_CTRL2_WRMFRZ_SHIFT 28 02097 /* ESR2 Bit Fields */ 02098 #define CAN_ESR2_IMB_MASK 0x2000u 02099 #define CAN_ESR2_IMB_SHIFT 13 02100 #define CAN_ESR2_VPS_MASK 0x4000u 02101 #define CAN_ESR2_VPS_SHIFT 14 02102 #define CAN_ESR2_LPTM_MASK 0x7F0000u 02103 #define CAN_ESR2_LPTM_SHIFT 16 02104 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK) 02105 /* CRCR Bit Fields */ 02106 #define CAN_CRCR_TXCRC_MASK 0x7FFFu 02107 #define CAN_CRCR_TXCRC_SHIFT 0 02108 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK) 02109 #define CAN_CRCR_MBCRC_MASK 0x7F0000u 02110 #define CAN_CRCR_MBCRC_SHIFT 16 02111 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK) 02112 /* RXFGMASK Bit Fields */ 02113 #define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu 02114 #define CAN_RXFGMASK_FGM_SHIFT 0 02115 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK) 02116 /* RXFIR Bit Fields */ 02117 #define CAN_RXFIR_IDHIT_MASK 0x1FFu 02118 #define CAN_RXFIR_IDHIT_SHIFT 0 02119 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK) 02120 /* CS Bit Fields */ 02121 #define CAN_CS_TIME_STAMP_MASK 0xFFFFu 02122 #define CAN_CS_TIME_STAMP_SHIFT 0 02123 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK) 02124 #define CAN_CS_DLC_MASK 0xF0000u 02125 #define CAN_CS_DLC_SHIFT 16 02126 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK) 02127 #define CAN_CS_RTR_MASK 0x100000u 02128 #define CAN_CS_RTR_SHIFT 20 02129 #define CAN_CS_IDE_MASK 0x200000u 02130 #define CAN_CS_IDE_SHIFT 21 02131 #define CAN_CS_SRR_MASK 0x400000u 02132 #define CAN_CS_SRR_SHIFT 22 02133 #define CAN_CS_CODE_MASK 0xF000000u 02134 #define CAN_CS_CODE_SHIFT 24 02135 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK) 02136 /* ID Bit Fields */ 02137 #define CAN_ID_EXT_MASK 0x3FFFFu 02138 #define CAN_ID_EXT_SHIFT 0 02139 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK) 02140 #define CAN_ID_STD_MASK 0x1FFC0000u 02141 #define CAN_ID_STD_SHIFT 18 02142 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK) 02143 #define CAN_ID_PRIO_MASK 0xE0000000u 02144 #define CAN_ID_PRIO_SHIFT 29 02145 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK) 02146 /* WORD0 Bit Fields */ 02147 #define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu 02148 #define CAN_WORD0_DATA_BYTE_3_SHIFT 0 02149 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK) 02150 #define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u 02151 #define CAN_WORD0_DATA_BYTE_2_SHIFT 8 02152 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK) 02153 #define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u 02154 #define CAN_WORD0_DATA_BYTE_1_SHIFT 16 02155 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK) 02156 #define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u 02157 #define CAN_WORD0_DATA_BYTE_0_SHIFT 24 02158 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK) 02159 /* WORD1 Bit Fields */ 02160 #define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu 02161 #define CAN_WORD1_DATA_BYTE_7_SHIFT 0 02162 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK) 02163 #define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u 02164 #define CAN_WORD1_DATA_BYTE_6_SHIFT 8 02165 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK) 02166 #define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u 02167 #define CAN_WORD1_DATA_BYTE_5_SHIFT 16 02168 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK) 02169 #define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u 02170 #define CAN_WORD1_DATA_BYTE_4_SHIFT 24 02171 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK) 02172 /* RXIMR Bit Fields */ 02173 #define CAN_RXIMR_MI_MASK 0xFFFFFFFFu 02174 #define CAN_RXIMR_MI_SHIFT 0 02175 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK) 02176 02177 /*! 02178 * @} 02179 */ /* end of group CAN_Register_Masks */ 02180 02181 02182 /* CAN - Peripheral instance base addresses */ 02183 /** Peripheral CAN0 base address */ 02184 #define CAN0_BASE (0x40024000u) 02185 /** Peripheral CAN0 base pointer */ 02186 #define CAN0 ((CAN_Type *)CAN0_BASE) 02187 #define CAN0_BASE_PTR (CAN0) 02188 /** Array initializer of CAN peripheral base addresses */ 02189 #define CAN_BASE_ADDRS { CAN0_BASE } 02190 /** Array initializer of CAN peripheral base pointers */ 02191 #define CAN_BASE_PTRS { CAN0 } 02192 /** Interrupt vectors for the CAN peripheral type */ 02193 #define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn } 02194 #define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn } 02195 #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn } 02196 #define CAN_Error_IRQS { CAN0_Error_IRQn } 02197 #define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn } 02198 #define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn } 02199 02200 /* ---------------------------------------------------------------------------- 02201 -- CAN - Register accessor macros 02202 ---------------------------------------------------------------------------- */ 02203 02204 /*! 02205 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros 02206 * @{ 02207 */ 02208 02209 02210 /* CAN - Register instance definitions */ 02211 /* CAN0 */ 02212 #define CAN0_MCR CAN_MCR_REG(CAN0) 02213 #define CAN0_CTRL1 CAN_CTRL1_REG(CAN0) 02214 #define CAN0_TIMER CAN_TIMER_REG(CAN0) 02215 #define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0) 02216 #define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0) 02217 #define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0) 02218 #define CAN0_ECR CAN_ECR_REG(CAN0) 02219 #define CAN0_ESR1 CAN_ESR1_REG(CAN0) 02220 #define CAN0_IMASK1 CAN_IMASK1_REG(CAN0) 02221 #define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0) 02222 #define CAN0_CTRL2 CAN_CTRL2_REG(CAN0) 02223 #define CAN0_ESR2 CAN_ESR2_REG(CAN0) 02224 #define CAN0_CRCR CAN_CRCR_REG(CAN0) 02225 #define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0) 02226 #define CAN0_RXFIR CAN_RXFIR_REG(CAN0) 02227 #define CAN0_CS0 CAN_CS_REG(CAN0,0) 02228 #define CAN0_ID0 CAN_ID_REG(CAN0,0) 02229 #define CAN0_WORD00 CAN_WORD0_REG(CAN0,0) 02230 #define CAN0_WORD10 CAN_WORD1_REG(CAN0,0) 02231 #define CAN0_CS1 CAN_CS_REG(CAN0,1) 02232 #define CAN0_ID1 CAN_ID_REG(CAN0,1) 02233 #define CAN0_WORD01 CAN_WORD0_REG(CAN0,1) 02234 #define CAN0_WORD11 CAN_WORD1_REG(CAN0,1) 02235 #define CAN0_CS2 CAN_CS_REG(CAN0,2) 02236 #define CAN0_ID2 CAN_ID_REG(CAN0,2) 02237 #define CAN0_WORD02 CAN_WORD0_REG(CAN0,2) 02238 #define CAN0_WORD12 CAN_WORD1_REG(CAN0,2) 02239 #define CAN0_CS3 CAN_CS_REG(CAN0,3) 02240 #define CAN0_ID3 CAN_ID_REG(CAN0,3) 02241 #define CAN0_WORD03 CAN_WORD0_REG(CAN0,3) 02242 #define CAN0_WORD13 CAN_WORD1_REG(CAN0,3) 02243 #define CAN0_CS4 CAN_CS_REG(CAN0,4) 02244 #define CAN0_ID4 CAN_ID_REG(CAN0,4) 02245 #define CAN0_WORD04 CAN_WORD0_REG(CAN0,4) 02246 #define CAN0_WORD14 CAN_WORD1_REG(CAN0,4) 02247 #define CAN0_CS5 CAN_CS_REG(CAN0,5) 02248 #define CAN0_ID5 CAN_ID_REG(CAN0,5) 02249 #define CAN0_WORD05 CAN_WORD0_REG(CAN0,5) 02250 #define CAN0_WORD15 CAN_WORD1_REG(CAN0,5) 02251 #define CAN0_CS6 CAN_CS_REG(CAN0,6) 02252 #define CAN0_ID6 CAN_ID_REG(CAN0,6) 02253 #define CAN0_WORD06 CAN_WORD0_REG(CAN0,6) 02254 #define CAN0_WORD16 CAN_WORD1_REG(CAN0,6) 02255 #define CAN0_CS7 CAN_CS_REG(CAN0,7) 02256 #define CAN0_ID7 CAN_ID_REG(CAN0,7) 02257 #define CAN0_WORD07 CAN_WORD0_REG(CAN0,7) 02258 #define CAN0_WORD17 CAN_WORD1_REG(CAN0,7) 02259 #define CAN0_CS8 CAN_CS_REG(CAN0,8) 02260 #define CAN0_ID8 CAN_ID_REG(CAN0,8) 02261 #define CAN0_WORD08 CAN_WORD0_REG(CAN0,8) 02262 #define CAN0_WORD18 CAN_WORD1_REG(CAN0,8) 02263 #define CAN0_CS9 CAN_CS_REG(CAN0,9) 02264 #define CAN0_ID9 CAN_ID_REG(CAN0,9) 02265 #define CAN0_WORD09 CAN_WORD0_REG(CAN0,9) 02266 #define CAN0_WORD19 CAN_WORD1_REG(CAN0,9) 02267 #define CAN0_CS10 CAN_CS_REG(CAN0,10) 02268 #define CAN0_ID10 CAN_ID_REG(CAN0,10) 02269 #define CAN0_WORD010 CAN_WORD0_REG(CAN0,10) 02270 #define CAN0_WORD110 CAN_WORD1_REG(CAN0,10) 02271 #define CAN0_CS11 CAN_CS_REG(CAN0,11) 02272 #define CAN0_ID11 CAN_ID_REG(CAN0,11) 02273 #define CAN0_WORD011 CAN_WORD0_REG(CAN0,11) 02274 #define CAN0_WORD111 CAN_WORD1_REG(CAN0,11) 02275 #define CAN0_CS12 CAN_CS_REG(CAN0,12) 02276 #define CAN0_ID12 CAN_ID_REG(CAN0,12) 02277 #define CAN0_WORD012 CAN_WORD0_REG(CAN0,12) 02278 #define CAN0_WORD112 CAN_WORD1_REG(CAN0,12) 02279 #define CAN0_CS13 CAN_CS_REG(CAN0,13) 02280 #define CAN0_ID13 CAN_ID_REG(CAN0,13) 02281 #define CAN0_WORD013 CAN_WORD0_REG(CAN0,13) 02282 #define CAN0_WORD113 CAN_WORD1_REG(CAN0,13) 02283 #define CAN0_CS14 CAN_CS_REG(CAN0,14) 02284 #define CAN0_ID14 CAN_ID_REG(CAN0,14) 02285 #define CAN0_WORD014 CAN_WORD0_REG(CAN0,14) 02286 #define CAN0_WORD114 CAN_WORD1_REG(CAN0,14) 02287 #define CAN0_CS15 CAN_CS_REG(CAN0,15) 02288 #define CAN0_ID15 CAN_ID_REG(CAN0,15) 02289 #define CAN0_WORD015 CAN_WORD0_REG(CAN0,15) 02290 #define CAN0_WORD115 CAN_WORD1_REG(CAN0,15) 02291 #define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0,0) 02292 #define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0,1) 02293 #define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0,2) 02294 #define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0,3) 02295 #define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0,4) 02296 #define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0,5) 02297 #define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0,6) 02298 #define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0,7) 02299 #define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0,8) 02300 #define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0,9) 02301 #define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0,10) 02302 #define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0,11) 02303 #define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0,12) 02304 #define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0,13) 02305 #define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0,14) 02306 #define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0,15) 02307 02308 /* CAN - Register array accessors */ 02309 #define CAN0_CS(index) CAN_CS_REG(CAN0,index) 02310 #define CAN0_ID(index) CAN_ID_REG(CAN0,index) 02311 #define CAN0_WORD0(index) CAN_WORD0_REG(CAN0,index) 02312 #define CAN0_WORD1(index) CAN_WORD1_REG(CAN0,index) 02313 #define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0,index) 02314 02315 /*! 02316 * @} 02317 */ /* end of group CAN_Register_Accessor_Macros */ 02318 02319 02320 /*! 02321 * @} 02322 */ /* end of group CAN_Peripheral_Access_Layer */ 02323 02324 02325 /* ---------------------------------------------------------------------------- 02326 -- CAU Peripheral Access Layer 02327 ---------------------------------------------------------------------------- */ 02328 02329 /*! 02330 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer 02331 * @{ 02332 */ 02333 02334 /** CAU - Register Layout Typedef */ 02335 typedef struct { 02336 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */ 02337 uint8_t RESERVED_0[2048]; 02338 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */ 02339 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */ 02340 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */ 02341 uint8_t RESERVED_1[20]; 02342 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */ 02343 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */ 02344 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */ 02345 uint8_t RESERVED_2[20]; 02346 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */ 02347 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */ 02348 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */ 02349 uint8_t RESERVED_3[20]; 02350 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */ 02351 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */ 02352 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */ 02353 uint8_t RESERVED_4[84]; 02354 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */ 02355 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */ 02356 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */ 02357 uint8_t RESERVED_5[20]; 02358 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */ 02359 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */ 02360 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */ 02361 uint8_t RESERVED_6[276]; 02362 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */ 02363 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */ 02364 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */ 02365 uint8_t RESERVED_7[20]; 02366 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */ 02367 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */ 02368 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */ 02369 } CAU_Type, *CAU_MemMapPtr; 02370 02371 /* ---------------------------------------------------------------------------- 02372 -- CAU - Register accessor macros 02373 ---------------------------------------------------------------------------- */ 02374 02375 /*! 02376 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros 02377 * @{ 02378 */ 02379 02380 02381 /* CAU - Register accessors */ 02382 #define CAU_DIRECT_REG(base,index) ((base)->DIRECT[index]) 02383 #define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR) 02384 #define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA) 02385 #define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index]) 02386 #define CAU_STR_CASR_REG(base) ((base)->STR_CASR) 02387 #define CAU_STR_CAA_REG(base) ((base)->STR_CAA) 02388 #define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index]) 02389 #define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR) 02390 #define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA) 02391 #define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index]) 02392 #define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR) 02393 #define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA) 02394 #define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index]) 02395 #define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR) 02396 #define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA) 02397 #define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index]) 02398 #define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR) 02399 #define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA) 02400 #define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index]) 02401 #define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR) 02402 #define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA) 02403 #define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index]) 02404 #define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR) 02405 #define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA) 02406 #define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index]) 02407 02408 /*! 02409 * @} 02410 */ /* end of group CAU_Register_Accessor_Macros */ 02411 02412 02413 /* ---------------------------------------------------------------------------- 02414 -- CAU Register Masks 02415 ---------------------------------------------------------------------------- */ 02416 02417 /*! 02418 * @addtogroup CAU_Register_Masks CAU Register Masks 02419 * @{ 02420 */ 02421 02422 /* DIRECT Bit Fields */ 02423 #define CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu 02424 #define CAU_DIRECT_CAU_DIRECT0_SHIFT 0 02425 #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK) 02426 #define CAU_DIRECT_CAU_DIRECT1_MASK 0xFFFFFFFFu 02427 #define CAU_DIRECT_CAU_DIRECT1_SHIFT 0 02428 #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK) 02429 #define CAU_DIRECT_CAU_DIRECT2_MASK 0xFFFFFFFFu 02430 #define CAU_DIRECT_CAU_DIRECT2_SHIFT 0 02431 #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK) 02432 #define CAU_DIRECT_CAU_DIRECT3_MASK 0xFFFFFFFFu 02433 #define CAU_DIRECT_CAU_DIRECT3_SHIFT 0 02434 #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK) 02435 #define CAU_DIRECT_CAU_DIRECT4_MASK 0xFFFFFFFFu 02436 #define CAU_DIRECT_CAU_DIRECT4_SHIFT 0 02437 #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK) 02438 #define CAU_DIRECT_CAU_DIRECT5_MASK 0xFFFFFFFFu 02439 #define CAU_DIRECT_CAU_DIRECT5_SHIFT 0 02440 #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK) 02441 #define CAU_DIRECT_CAU_DIRECT6_MASK 0xFFFFFFFFu 02442 #define CAU_DIRECT_CAU_DIRECT6_SHIFT 0 02443 #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK) 02444 #define CAU_DIRECT_CAU_DIRECT7_MASK 0xFFFFFFFFu 02445 #define CAU_DIRECT_CAU_DIRECT7_SHIFT 0 02446 #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK) 02447 #define CAU_DIRECT_CAU_DIRECT8_MASK 0xFFFFFFFFu 02448 #define CAU_DIRECT_CAU_DIRECT8_SHIFT 0 02449 #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK) 02450 #define CAU_DIRECT_CAU_DIRECT9_MASK 0xFFFFFFFFu 02451 #define CAU_DIRECT_CAU_DIRECT9_SHIFT 0 02452 #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK) 02453 #define CAU_DIRECT_CAU_DIRECT10_MASK 0xFFFFFFFFu 02454 #define CAU_DIRECT_CAU_DIRECT10_SHIFT 0 02455 #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK) 02456 #define CAU_DIRECT_CAU_DIRECT11_MASK 0xFFFFFFFFu 02457 #define CAU_DIRECT_CAU_DIRECT11_SHIFT 0 02458 #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK) 02459 #define CAU_DIRECT_CAU_DIRECT12_MASK 0xFFFFFFFFu 02460 #define CAU_DIRECT_CAU_DIRECT12_SHIFT 0 02461 #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK) 02462 #define CAU_DIRECT_CAU_DIRECT13_MASK 0xFFFFFFFFu 02463 #define CAU_DIRECT_CAU_DIRECT13_SHIFT 0 02464 #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK) 02465 #define CAU_DIRECT_CAU_DIRECT14_MASK 0xFFFFFFFFu 02466 #define CAU_DIRECT_CAU_DIRECT14_SHIFT 0 02467 #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK) 02468 #define CAU_DIRECT_CAU_DIRECT15_MASK 0xFFFFFFFFu 02469 #define CAU_DIRECT_CAU_DIRECT15_SHIFT 0 02470 #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK) 02471 /* LDR_CASR Bit Fields */ 02472 #define CAU_LDR_CASR_IC_MASK 0x1u 02473 #define CAU_LDR_CASR_IC_SHIFT 0 02474 #define CAU_LDR_CASR_DPE_MASK 0x2u 02475 #define CAU_LDR_CASR_DPE_SHIFT 1 02476 #define CAU_LDR_CASR_VER_MASK 0xF0000000u 02477 #define CAU_LDR_CASR_VER_SHIFT 28 02478 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK) 02479 /* LDR_CAA Bit Fields */ 02480 #define CAU_LDR_CAA_ACC_MASK 0xFFFFFFFFu 02481 #define CAU_LDR_CAA_ACC_SHIFT 0 02482 #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK) 02483 /* LDR_CA Bit Fields */ 02484 #define CAU_LDR_CA_CA0_MASK 0xFFFFFFFFu 02485 #define CAU_LDR_CA_CA0_SHIFT 0 02486 #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK) 02487 #define CAU_LDR_CA_CA1_MASK 0xFFFFFFFFu 02488 #define CAU_LDR_CA_CA1_SHIFT 0 02489 #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK) 02490 #define CAU_LDR_CA_CA2_MASK 0xFFFFFFFFu 02491 #define CAU_LDR_CA_CA2_SHIFT 0 02492 #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK) 02493 #define CAU_LDR_CA_CA3_MASK 0xFFFFFFFFu 02494 #define CAU_LDR_CA_CA3_SHIFT 0 02495 #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK) 02496 #define CAU_LDR_CA_CA4_MASK 0xFFFFFFFFu 02497 #define CAU_LDR_CA_CA4_SHIFT 0 02498 #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK) 02499 #define CAU_LDR_CA_CA5_MASK 0xFFFFFFFFu 02500 #define CAU_LDR_CA_CA5_SHIFT 0 02501 #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK) 02502 #define CAU_LDR_CA_CA6_MASK 0xFFFFFFFFu 02503 #define CAU_LDR_CA_CA6_SHIFT 0 02504 #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK) 02505 #define CAU_LDR_CA_CA7_MASK 0xFFFFFFFFu 02506 #define CAU_LDR_CA_CA7_SHIFT 0 02507 #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK) 02508 #define CAU_LDR_CA_CA8_MASK 0xFFFFFFFFu 02509 #define CAU_LDR_CA_CA8_SHIFT 0 02510 #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK) 02511 /* STR_CASR Bit Fields */ 02512 #define CAU_STR_CASR_IC_MASK 0x1u 02513 #define CAU_STR_CASR_IC_SHIFT 0 02514 #define CAU_STR_CASR_DPE_MASK 0x2u 02515 #define CAU_STR_CASR_DPE_SHIFT 1 02516 #define CAU_STR_CASR_VER_MASK 0xF0000000u 02517 #define CAU_STR_CASR_VER_SHIFT 28 02518 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK) 02519 /* STR_CAA Bit Fields */ 02520 #define CAU_STR_CAA_ACC_MASK 0xFFFFFFFFu 02521 #define CAU_STR_CAA_ACC_SHIFT 0 02522 #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK) 02523 /* STR_CA Bit Fields */ 02524 #define CAU_STR_CA_CA0_MASK 0xFFFFFFFFu 02525 #define CAU_STR_CA_CA0_SHIFT 0 02526 #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK) 02527 #define CAU_STR_CA_CA1_MASK 0xFFFFFFFFu 02528 #define CAU_STR_CA_CA1_SHIFT 0 02529 #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK) 02530 #define CAU_STR_CA_CA2_MASK 0xFFFFFFFFu 02531 #define CAU_STR_CA_CA2_SHIFT 0 02532 #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK) 02533 #define CAU_STR_CA_CA3_MASK 0xFFFFFFFFu 02534 #define CAU_STR_CA_CA3_SHIFT 0 02535 #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK) 02536 #define CAU_STR_CA_CA4_MASK 0xFFFFFFFFu 02537 #define CAU_STR_CA_CA4_SHIFT 0 02538 #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK) 02539 #define CAU_STR_CA_CA5_MASK 0xFFFFFFFFu 02540 #define CAU_STR_CA_CA5_SHIFT 0 02541 #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK) 02542 #define CAU_STR_CA_CA6_MASK 0xFFFFFFFFu 02543 #define CAU_STR_CA_CA6_SHIFT 0 02544 #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK) 02545 #define CAU_STR_CA_CA7_MASK 0xFFFFFFFFu 02546 #define CAU_STR_CA_CA7_SHIFT 0 02547 #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK) 02548 #define CAU_STR_CA_CA8_MASK 0xFFFFFFFFu 02549 #define CAU_STR_CA_CA8_SHIFT 0 02550 #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK) 02551 /* ADR_CASR Bit Fields */ 02552 #define CAU_ADR_CASR_IC_MASK 0x1u 02553 #define CAU_ADR_CASR_IC_SHIFT 0 02554 #define CAU_ADR_CASR_DPE_MASK 0x2u 02555 #define CAU_ADR_CASR_DPE_SHIFT 1 02556 #define CAU_ADR_CASR_VER_MASK 0xF0000000u 02557 #define CAU_ADR_CASR_VER_SHIFT 28 02558 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK) 02559 /* ADR_CAA Bit Fields */ 02560 #define CAU_ADR_CAA_ACC_MASK 0xFFFFFFFFu 02561 #define CAU_ADR_CAA_ACC_SHIFT 0 02562 #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK) 02563 /* ADR_CA Bit Fields */ 02564 #define CAU_ADR_CA_CA0_MASK 0xFFFFFFFFu 02565 #define CAU_ADR_CA_CA0_SHIFT 0 02566 #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK) 02567 #define CAU_ADR_CA_CA1_MASK 0xFFFFFFFFu 02568 #define CAU_ADR_CA_CA1_SHIFT 0 02569 #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK) 02570 #define CAU_ADR_CA_CA2_MASK 0xFFFFFFFFu 02571 #define CAU_ADR_CA_CA2_SHIFT 0 02572 #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK) 02573 #define CAU_ADR_CA_CA3_MASK 0xFFFFFFFFu 02574 #define CAU_ADR_CA_CA3_SHIFT 0 02575 #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK) 02576 #define CAU_ADR_CA_CA4_MASK 0xFFFFFFFFu 02577 #define CAU_ADR_CA_CA4_SHIFT 0 02578 #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK) 02579 #define CAU_ADR_CA_CA5_MASK 0xFFFFFFFFu 02580 #define CAU_ADR_CA_CA5_SHIFT 0 02581 #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK) 02582 #define CAU_ADR_CA_CA6_MASK 0xFFFFFFFFu 02583 #define CAU_ADR_CA_CA6_SHIFT 0 02584 #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK) 02585 #define CAU_ADR_CA_CA7_MASK 0xFFFFFFFFu 02586 #define CAU_ADR_CA_CA7_SHIFT 0 02587 #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK) 02588 #define CAU_ADR_CA_CA8_MASK 0xFFFFFFFFu 02589 #define CAU_ADR_CA_CA8_SHIFT 0 02590 #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK) 02591 /* RADR_CASR Bit Fields */ 02592 #define CAU_RADR_CASR_IC_MASK 0x1u 02593 #define CAU_RADR_CASR_IC_SHIFT 0 02594 #define CAU_RADR_CASR_DPE_MASK 0x2u 02595 #define CAU_RADR_CASR_DPE_SHIFT 1 02596 #define CAU_RADR_CASR_VER_MASK 0xF0000000u 02597 #define CAU_RADR_CASR_VER_SHIFT 28 02598 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK) 02599 /* RADR_CAA Bit Fields */ 02600 #define CAU_RADR_CAA_ACC_MASK 0xFFFFFFFFu 02601 #define CAU_RADR_CAA_ACC_SHIFT 0 02602 #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK) 02603 /* RADR_CA Bit Fields */ 02604 #define CAU_RADR_CA_CA0_MASK 0xFFFFFFFFu 02605 #define CAU_RADR_CA_CA0_SHIFT 0 02606 #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK) 02607 #define CAU_RADR_CA_CA1_MASK 0xFFFFFFFFu 02608 #define CAU_RADR_CA_CA1_SHIFT 0 02609 #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK) 02610 #define CAU_RADR_CA_CA2_MASK 0xFFFFFFFFu 02611 #define CAU_RADR_CA_CA2_SHIFT 0 02612 #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK) 02613 #define CAU_RADR_CA_CA3_MASK 0xFFFFFFFFu 02614 #define CAU_RADR_CA_CA3_SHIFT 0 02615 #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK) 02616 #define CAU_RADR_CA_CA4_MASK 0xFFFFFFFFu 02617 #define CAU_RADR_CA_CA4_SHIFT 0 02618 #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK) 02619 #define CAU_RADR_CA_CA5_MASK 0xFFFFFFFFu 02620 #define CAU_RADR_CA_CA5_SHIFT 0 02621 #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK) 02622 #define CAU_RADR_CA_CA6_MASK 0xFFFFFFFFu 02623 #define CAU_RADR_CA_CA6_SHIFT 0 02624 #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK) 02625 #define CAU_RADR_CA_CA7_MASK 0xFFFFFFFFu 02626 #define CAU_RADR_CA_CA7_SHIFT 0 02627 #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK) 02628 #define CAU_RADR_CA_CA8_MASK 0xFFFFFFFFu 02629 #define CAU_RADR_CA_CA8_SHIFT 0 02630 #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK) 02631 /* XOR_CASR Bit Fields */ 02632 #define CAU_XOR_CASR_IC_MASK 0x1u 02633 #define CAU_XOR_CASR_IC_SHIFT 0 02634 #define CAU_XOR_CASR_DPE_MASK 0x2u 02635 #define CAU_XOR_CASR_DPE_SHIFT 1 02636 #define CAU_XOR_CASR_VER_MASK 0xF0000000u 02637 #define CAU_XOR_CASR_VER_SHIFT 28 02638 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK) 02639 /* XOR_CAA Bit Fields */ 02640 #define CAU_XOR_CAA_ACC_MASK 0xFFFFFFFFu 02641 #define CAU_XOR_CAA_ACC_SHIFT 0 02642 #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK) 02643 /* XOR_CA Bit Fields */ 02644 #define CAU_XOR_CA_CA0_MASK 0xFFFFFFFFu 02645 #define CAU_XOR_CA_CA0_SHIFT 0 02646 #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK) 02647 #define CAU_XOR_CA_CA1_MASK 0xFFFFFFFFu 02648 #define CAU_XOR_CA_CA1_SHIFT 0 02649 #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK) 02650 #define CAU_XOR_CA_CA2_MASK 0xFFFFFFFFu 02651 #define CAU_XOR_CA_CA2_SHIFT 0 02652 #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK) 02653 #define CAU_XOR_CA_CA3_MASK 0xFFFFFFFFu 02654 #define CAU_XOR_CA_CA3_SHIFT 0 02655 #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK) 02656 #define CAU_XOR_CA_CA4_MASK 0xFFFFFFFFu 02657 #define CAU_XOR_CA_CA4_SHIFT 0 02658 #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK) 02659 #define CAU_XOR_CA_CA5_MASK 0xFFFFFFFFu 02660 #define CAU_XOR_CA_CA5_SHIFT 0 02661 #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK) 02662 #define CAU_XOR_CA_CA6_MASK 0xFFFFFFFFu 02663 #define CAU_XOR_CA_CA6_SHIFT 0 02664 #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK) 02665 #define CAU_XOR_CA_CA7_MASK 0xFFFFFFFFu 02666 #define CAU_XOR_CA_CA7_SHIFT 0 02667 #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK) 02668 #define CAU_XOR_CA_CA8_MASK 0xFFFFFFFFu 02669 #define CAU_XOR_CA_CA8_SHIFT 0 02670 #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK) 02671 /* ROTL_CASR Bit Fields */ 02672 #define CAU_ROTL_CASR_IC_MASK 0x1u 02673 #define CAU_ROTL_CASR_IC_SHIFT 0 02674 #define CAU_ROTL_CASR_DPE_MASK 0x2u 02675 #define CAU_ROTL_CASR_DPE_SHIFT 1 02676 #define CAU_ROTL_CASR_VER_MASK 0xF0000000u 02677 #define CAU_ROTL_CASR_VER_SHIFT 28 02678 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK) 02679 /* ROTL_CAA Bit Fields */ 02680 #define CAU_ROTL_CAA_ACC_MASK 0xFFFFFFFFu 02681 #define CAU_ROTL_CAA_ACC_SHIFT 0 02682 #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK) 02683 /* ROTL_CA Bit Fields */ 02684 #define CAU_ROTL_CA_CA0_MASK 0xFFFFFFFFu 02685 #define CAU_ROTL_CA_CA0_SHIFT 0 02686 #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK) 02687 #define CAU_ROTL_CA_CA1_MASK 0xFFFFFFFFu 02688 #define CAU_ROTL_CA_CA1_SHIFT 0 02689 #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK) 02690 #define CAU_ROTL_CA_CA2_MASK 0xFFFFFFFFu 02691 #define CAU_ROTL_CA_CA2_SHIFT 0 02692 #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK) 02693 #define CAU_ROTL_CA_CA3_MASK 0xFFFFFFFFu 02694 #define CAU_ROTL_CA_CA3_SHIFT 0 02695 #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK) 02696 #define CAU_ROTL_CA_CA4_MASK 0xFFFFFFFFu 02697 #define CAU_ROTL_CA_CA4_SHIFT 0 02698 #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK) 02699 #define CAU_ROTL_CA_CA5_MASK 0xFFFFFFFFu 02700 #define CAU_ROTL_CA_CA5_SHIFT 0 02701 #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK) 02702 #define CAU_ROTL_CA_CA6_MASK 0xFFFFFFFFu 02703 #define CAU_ROTL_CA_CA6_SHIFT 0 02704 #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK) 02705 #define CAU_ROTL_CA_CA7_MASK 0xFFFFFFFFu 02706 #define CAU_ROTL_CA_CA7_SHIFT 0 02707 #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK) 02708 #define CAU_ROTL_CA_CA8_MASK 0xFFFFFFFFu 02709 #define CAU_ROTL_CA_CA8_SHIFT 0 02710 #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK) 02711 /* AESC_CASR Bit Fields */ 02712 #define CAU_AESC_CASR_IC_MASK 0x1u 02713 #define CAU_AESC_CASR_IC_SHIFT 0 02714 #define CAU_AESC_CASR_DPE_MASK 0x2u 02715 #define CAU_AESC_CASR_DPE_SHIFT 1 02716 #define CAU_AESC_CASR_VER_MASK 0xF0000000u 02717 #define CAU_AESC_CASR_VER_SHIFT 28 02718 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK) 02719 /* AESC_CAA Bit Fields */ 02720 #define CAU_AESC_CAA_ACC_MASK 0xFFFFFFFFu 02721 #define CAU_AESC_CAA_ACC_SHIFT 0 02722 #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK) 02723 /* AESC_CA Bit Fields */ 02724 #define CAU_AESC_CA_CA0_MASK 0xFFFFFFFFu 02725 #define CAU_AESC_CA_CA0_SHIFT 0 02726 #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK) 02727 #define CAU_AESC_CA_CA1_MASK 0xFFFFFFFFu 02728 #define CAU_AESC_CA_CA1_SHIFT 0 02729 #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK) 02730 #define CAU_AESC_CA_CA2_MASK 0xFFFFFFFFu 02731 #define CAU_AESC_CA_CA2_SHIFT 0 02732 #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK) 02733 #define CAU_AESC_CA_CA3_MASK 0xFFFFFFFFu 02734 #define CAU_AESC_CA_CA3_SHIFT 0 02735 #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK) 02736 #define CAU_AESC_CA_CA4_MASK 0xFFFFFFFFu 02737 #define CAU_AESC_CA_CA4_SHIFT 0 02738 #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK) 02739 #define CAU_AESC_CA_CA5_MASK 0xFFFFFFFFu 02740 #define CAU_AESC_CA_CA5_SHIFT 0 02741 #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK) 02742 #define CAU_AESC_CA_CA6_MASK 0xFFFFFFFFu 02743 #define CAU_AESC_CA_CA6_SHIFT 0 02744 #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK) 02745 #define CAU_AESC_CA_CA7_MASK 0xFFFFFFFFu 02746 #define CAU_AESC_CA_CA7_SHIFT 0 02747 #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK) 02748 #define CAU_AESC_CA_CA8_MASK 0xFFFFFFFFu 02749 #define CAU_AESC_CA_CA8_SHIFT 0 02750 #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK) 02751 /* AESIC_CASR Bit Fields */ 02752 #define CAU_AESIC_CASR_IC_MASK 0x1u 02753 #define CAU_AESIC_CASR_IC_SHIFT 0 02754 #define CAU_AESIC_CASR_DPE_MASK 0x2u 02755 #define CAU_AESIC_CASR_DPE_SHIFT 1 02756 #define CAU_AESIC_CASR_VER_MASK 0xF0000000u 02757 #define CAU_AESIC_CASR_VER_SHIFT 28 02758 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK) 02759 /* AESIC_CAA Bit Fields */ 02760 #define CAU_AESIC_CAA_ACC_MASK 0xFFFFFFFFu 02761 #define CAU_AESIC_CAA_ACC_SHIFT 0 02762 #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK) 02763 /* AESIC_CA Bit Fields */ 02764 #define CAU_AESIC_CA_CA0_MASK 0xFFFFFFFFu 02765 #define CAU_AESIC_CA_CA0_SHIFT 0 02766 #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK) 02767 #define CAU_AESIC_CA_CA1_MASK 0xFFFFFFFFu 02768 #define CAU_AESIC_CA_CA1_SHIFT 0 02769 #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK) 02770 #define CAU_AESIC_CA_CA2_MASK 0xFFFFFFFFu 02771 #define CAU_AESIC_CA_CA2_SHIFT 0 02772 #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK) 02773 #define CAU_AESIC_CA_CA3_MASK 0xFFFFFFFFu 02774 #define CAU_AESIC_CA_CA3_SHIFT 0 02775 #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK) 02776 #define CAU_AESIC_CA_CA4_MASK 0xFFFFFFFFu 02777 #define CAU_AESIC_CA_CA4_SHIFT 0 02778 #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK) 02779 #define CAU_AESIC_CA_CA5_MASK 0xFFFFFFFFu 02780 #define CAU_AESIC_CA_CA5_SHIFT 0 02781 #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK) 02782 #define CAU_AESIC_CA_CA6_MASK 0xFFFFFFFFu 02783 #define CAU_AESIC_CA_CA6_SHIFT 0 02784 #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK) 02785 #define CAU_AESIC_CA_CA7_MASK 0xFFFFFFFFu 02786 #define CAU_AESIC_CA_CA7_SHIFT 0 02787 #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK) 02788 #define CAU_AESIC_CA_CA8_MASK 0xFFFFFFFFu 02789 #define CAU_AESIC_CA_CA8_SHIFT 0 02790 #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK) 02791 02792 /*! 02793 * @} 02794 */ /* end of group CAU_Register_Masks */ 02795 02796 02797 /* CAU - Peripheral instance base addresses */ 02798 /** Peripheral CAU base address */ 02799 #define CAU_BASE (0xE0081000u) 02800 /** Peripheral CAU base pointer */ 02801 #define CAU ((CAU_Type *)CAU_BASE) 02802 #define CAU_BASE_PTR (CAU) 02803 /** Array initializer of CAU peripheral base addresses */ 02804 #define CAU_BASE_ADDRS { CAU_BASE } 02805 /** Array initializer of CAU peripheral base pointers */ 02806 #define CAU_BASE_PTRS { CAU } 02807 02808 /* ---------------------------------------------------------------------------- 02809 -- CAU - Register accessor macros 02810 ---------------------------------------------------------------------------- */ 02811 02812 /*! 02813 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros 02814 * @{ 02815 */ 02816 02817 02818 /* CAU - Register instance definitions */ 02819 /* CAU */ 02820 #define CAU_DIRECT0 CAU_DIRECT_REG(CAU,0) 02821 #define CAU_DIRECT1 CAU_DIRECT_REG(CAU,1) 02822 #define CAU_DIRECT2 CAU_DIRECT_REG(CAU,2) 02823 #define CAU_DIRECT3 CAU_DIRECT_REG(CAU,3) 02824 #define CAU_DIRECT4 CAU_DIRECT_REG(CAU,4) 02825 #define CAU_DIRECT5 CAU_DIRECT_REG(CAU,5) 02826 #define CAU_DIRECT6 CAU_DIRECT_REG(CAU,6) 02827 #define CAU_DIRECT7 CAU_DIRECT_REG(CAU,7) 02828 #define CAU_DIRECT8 CAU_DIRECT_REG(CAU,8) 02829 #define CAU_DIRECT9 CAU_DIRECT_REG(CAU,9) 02830 #define CAU_DIRECT10 CAU_DIRECT_REG(CAU,10) 02831 #define CAU_DIRECT11 CAU_DIRECT_REG(CAU,11) 02832 #define CAU_DIRECT12 CAU_DIRECT_REG(CAU,12) 02833 #define CAU_DIRECT13 CAU_DIRECT_REG(CAU,13) 02834 #define CAU_DIRECT14 CAU_DIRECT_REG(CAU,14) 02835 #define CAU_DIRECT15 CAU_DIRECT_REG(CAU,15) 02836 #define CAU_LDR_CASR CAU_LDR_CASR_REG(CAU) 02837 #define CAU_LDR_CAA CAU_LDR_CAA_REG(CAU) 02838 #define CAU_LDR_CA0 CAU_LDR_CA_REG(CAU,0) 02839 #define CAU_LDR_CA1 CAU_LDR_CA_REG(CAU,1) 02840 #define CAU_LDR_CA2 CAU_LDR_CA_REG(CAU,2) 02841 #define CAU_LDR_CA3 CAU_LDR_CA_REG(CAU,3) 02842 #define CAU_LDR_CA4 CAU_LDR_CA_REG(CAU,4) 02843 #define CAU_LDR_CA5 CAU_LDR_CA_REG(CAU,5) 02844 #define CAU_LDR_CA6 CAU_LDR_CA_REG(CAU,6) 02845 #define CAU_LDR_CA7 CAU_LDR_CA_REG(CAU,7) 02846 #define CAU_LDR_CA8 CAU_LDR_CA_REG(CAU,8) 02847 #define CAU_STR_CASR CAU_STR_CASR_REG(CAU) 02848 #define CAU_STR_CAA CAU_STR_CAA_REG(CAU) 02849 #define CAU_STR_CA0 CAU_STR_CA_REG(CAU,0) 02850 #define CAU_STR_CA1 CAU_STR_CA_REG(CAU,1) 02851 #define CAU_STR_CA2 CAU_STR_CA_REG(CAU,2) 02852 #define CAU_STR_CA3 CAU_STR_CA_REG(CAU,3) 02853 #define CAU_STR_CA4 CAU_STR_CA_REG(CAU,4) 02854 #define CAU_STR_CA5 CAU_STR_CA_REG(CAU,5) 02855 #define CAU_STR_CA6 CAU_STR_CA_REG(CAU,6) 02856 #define CAU_STR_CA7 CAU_STR_CA_REG(CAU,7) 02857 #define CAU_STR_CA8 CAU_STR_CA_REG(CAU,8) 02858 #define CAU_ADR_CASR CAU_ADR_CASR_REG(CAU) 02859 #define CAU_ADR_CAA CAU_ADR_CAA_REG(CAU) 02860 #define CAU_ADR_CA0 CAU_ADR_CA_REG(CAU,0) 02861 #define CAU_ADR_CA1 CAU_ADR_CA_REG(CAU,1) 02862 #define CAU_ADR_CA2 CAU_ADR_CA_REG(CAU,2) 02863 #define CAU_ADR_CA3 CAU_ADR_CA_REG(CAU,3) 02864 #define CAU_ADR_CA4 CAU_ADR_CA_REG(CAU,4) 02865 #define CAU_ADR_CA5 CAU_ADR_CA_REG(CAU,5) 02866 #define CAU_ADR_CA6 CAU_ADR_CA_REG(CAU,6) 02867 #define CAU_ADR_CA7 CAU_ADR_CA_REG(CAU,7) 02868 #define CAU_ADR_CA8 CAU_ADR_CA_REG(CAU,8) 02869 #define CAU_RADR_CASR CAU_RADR_CASR_REG(CAU) 02870 #define CAU_RADR_CAA CAU_RADR_CAA_REG(CAU) 02871 #define CAU_RADR_CA0 CAU_RADR_CA_REG(CAU,0) 02872 #define CAU_RADR_CA1 CAU_RADR_CA_REG(CAU,1) 02873 #define CAU_RADR_CA2 CAU_RADR_CA_REG(CAU,2) 02874 #define CAU_RADR_CA3 CAU_RADR_CA_REG(CAU,3) 02875 #define CAU_RADR_CA4 CAU_RADR_CA_REG(CAU,4) 02876 #define CAU_RADR_CA5 CAU_RADR_CA_REG(CAU,5) 02877 #define CAU_RADR_CA6 CAU_RADR_CA_REG(CAU,6) 02878 #define CAU_RADR_CA7 CAU_RADR_CA_REG(CAU,7) 02879 #define CAU_RADR_CA8 CAU_RADR_CA_REG(CAU,8) 02880 #define CAU_XOR_CASR CAU_XOR_CASR_REG(CAU) 02881 #define CAU_XOR_CAA CAU_XOR_CAA_REG(CAU) 02882 #define CAU_XOR_CA0 CAU_XOR_CA_REG(CAU,0) 02883 #define CAU_XOR_CA1 CAU_XOR_CA_REG(CAU,1) 02884 #define CAU_XOR_CA2 CAU_XOR_CA_REG(CAU,2) 02885 #define CAU_XOR_CA3 CAU_XOR_CA_REG(CAU,3) 02886 #define CAU_XOR_CA4 CAU_XOR_CA_REG(CAU,4) 02887 #define CAU_XOR_CA5 CAU_XOR_CA_REG(CAU,5) 02888 #define CAU_XOR_CA6 CAU_XOR_CA_REG(CAU,6) 02889 #define CAU_XOR_CA7 CAU_XOR_CA_REG(CAU,7) 02890 #define CAU_XOR_CA8 CAU_XOR_CA_REG(CAU,8) 02891 #define CAU_ROTL_CASR CAU_ROTL_CASR_REG(CAU) 02892 #define CAU_ROTL_CAA CAU_ROTL_CAA_REG(CAU) 02893 #define CAU_ROTL_CA0 CAU_ROTL_CA_REG(CAU,0) 02894 #define CAU_ROTL_CA1 CAU_ROTL_CA_REG(CAU,1) 02895 #define CAU_ROTL_CA2 CAU_ROTL_CA_REG(CAU,2) 02896 #define CAU_ROTL_CA3 CAU_ROTL_CA_REG(CAU,3) 02897 #define CAU_ROTL_CA4 CAU_ROTL_CA_REG(CAU,4) 02898 #define CAU_ROTL_CA5 CAU_ROTL_CA_REG(CAU,5) 02899 #define CAU_ROTL_CA6 CAU_ROTL_CA_REG(CAU,6) 02900 #define CAU_ROTL_CA7 CAU_ROTL_CA_REG(CAU,7) 02901 #define CAU_ROTL_CA8 CAU_ROTL_CA_REG(CAU,8) 02902 #define CAU_AESC_CASR CAU_AESC_CASR_REG(CAU) 02903 #define CAU_AESC_CAA CAU_AESC_CAA_REG(CAU) 02904 #define CAU_AESC_CA0 CAU_AESC_CA_REG(CAU,0) 02905 #define CAU_AESC_CA1 CAU_AESC_CA_REG(CAU,1) 02906 #define CAU_AESC_CA2 CAU_AESC_CA_REG(CAU,2) 02907 #define CAU_AESC_CA3 CAU_AESC_CA_REG(CAU,3) 02908 #define CAU_AESC_CA4 CAU_AESC_CA_REG(CAU,4) 02909 #define CAU_AESC_CA5 CAU_AESC_CA_REG(CAU,5) 02910 #define CAU_AESC_CA6 CAU_AESC_CA_REG(CAU,6) 02911 #define CAU_AESC_CA7 CAU_AESC_CA_REG(CAU,7) 02912 #define CAU_AESC_CA8 CAU_AESC_CA_REG(CAU,8) 02913 #define CAU_AESIC_CASR CAU_AESIC_CASR_REG(CAU) 02914 #define CAU_AESIC_CAA CAU_AESIC_CAA_REG(CAU) 02915 #define CAU_AESIC_CA0 CAU_AESIC_CA_REG(CAU,0) 02916 #define CAU_AESIC_CA1 CAU_AESIC_CA_REG(CAU,1) 02917 #define CAU_AESIC_CA2 CAU_AESIC_CA_REG(CAU,2) 02918 #define CAU_AESIC_CA3 CAU_AESIC_CA_REG(CAU,3) 02919 #define CAU_AESIC_CA4 CAU_AESIC_CA_REG(CAU,4) 02920 #define CAU_AESIC_CA5 CAU_AESIC_CA_REG(CAU,5) 02921 #define CAU_AESIC_CA6 CAU_AESIC_CA_REG(CAU,6) 02922 #define CAU_AESIC_CA7 CAU_AESIC_CA_REG(CAU,7) 02923 #define CAU_AESIC_CA8 CAU_AESIC_CA_REG(CAU,8) 02924 02925 /* CAU - Register array accessors */ 02926 #define CAU_DIRECT(index) CAU_DIRECT_REG(CAU,index) 02927 #define CAU_LDR_CA(index) CAU_LDR_CA_REG(CAU,index) 02928 #define CAU_STR_CA(index) CAU_STR_CA_REG(CAU,index) 02929 #define CAU_ADR_CA(index) CAU_ADR_CA_REG(CAU,index) 02930 #define CAU_RADR_CA(index) CAU_RADR_CA_REG(CAU,index) 02931 #define CAU_XOR_CA(index) CAU_XOR_CA_REG(CAU,index) 02932 #define CAU_ROTL_CA(index) CAU_ROTL_CA_REG(CAU,index) 02933 #define CAU_AESC_CA(index) CAU_AESC_CA_REG(CAU,index) 02934 #define CAU_AESIC_CA(index) CAU_AESIC_CA_REG(CAU,index) 02935 02936 /*! 02937 * @} 02938 */ /* end of group CAU_Register_Accessor_Macros */ 02939 02940 02941 /*! 02942 * @} 02943 */ /* end of group CAU_Peripheral_Access_Layer */ 02944 02945 02946 /* ---------------------------------------------------------------------------- 02947 -- CMP Peripheral Access Layer 02948 ---------------------------------------------------------------------------- */ 02949 02950 /*! 02951 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer 02952 * @{ 02953 */ 02954 02955 /** CMP - Register Layout Typedef */ 02956 typedef struct { 02957 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ 02958 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ 02959 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ 02960 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ 02961 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ 02962 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ 02963 } CMP_Type, *CMP_MemMapPtr; 02964 02965 /* ---------------------------------------------------------------------------- 02966 -- CMP - Register accessor macros 02967 ---------------------------------------------------------------------------- */ 02968 02969 /*! 02970 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros 02971 * @{ 02972 */ 02973 02974 02975 /* CMP - Register accessors */ 02976 #define CMP_CR0_REG(base) ((base)->CR0) 02977 #define CMP_CR1_REG(base) ((base)->CR1) 02978 #define CMP_FPR_REG(base) ((base)->FPR) 02979 #define CMP_SCR_REG(base) ((base)->SCR) 02980 #define CMP_DACCR_REG(base) ((base)->DACCR) 02981 #define CMP_MUXCR_REG(base) ((base)->MUXCR) 02982 02983 /*! 02984 * @} 02985 */ /* end of group CMP_Register_Accessor_Macros */ 02986 02987 02988 /* ---------------------------------------------------------------------------- 02989 -- CMP Register Masks 02990 ---------------------------------------------------------------------------- */ 02991 02992 /*! 02993 * @addtogroup CMP_Register_Masks CMP Register Masks 02994 * @{ 02995 */ 02996 02997 /* CR0 Bit Fields */ 02998 #define CMP_CR0_HYSTCTR_MASK 0x3u 02999 #define CMP_CR0_HYSTCTR_SHIFT 0 03000 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK) 03001 #define CMP_CR0_FILTER_CNT_MASK 0x70u 03002 #define CMP_CR0_FILTER_CNT_SHIFT 4 03003 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK) 03004 /* CR1 Bit Fields */ 03005 #define CMP_CR1_EN_MASK 0x1u 03006 #define CMP_CR1_EN_SHIFT 0 03007 #define CMP_CR1_OPE_MASK 0x2u 03008 #define CMP_CR1_OPE_SHIFT 1 03009 #define CMP_CR1_COS_MASK 0x4u 03010 #define CMP_CR1_COS_SHIFT 2 03011 #define CMP_CR1_INV_MASK 0x8u 03012 #define CMP_CR1_INV_SHIFT 3 03013 #define CMP_CR1_PMODE_MASK 0x10u 03014 #define CMP_CR1_PMODE_SHIFT 4 03015 #define CMP_CR1_WE_MASK 0x40u 03016 #define CMP_CR1_WE_SHIFT 6 03017 #define CMP_CR1_SE_MASK 0x80u 03018 #define CMP_CR1_SE_SHIFT 7 03019 /* FPR Bit Fields */ 03020 #define CMP_FPR_FILT_PER_MASK 0xFFu 03021 #define CMP_FPR_FILT_PER_SHIFT 0 03022 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK) 03023 /* SCR Bit Fields */ 03024 #define CMP_SCR_COUT_MASK 0x1u 03025 #define CMP_SCR_COUT_SHIFT 0 03026 #define CMP_SCR_CFF_MASK 0x2u 03027 #define CMP_SCR_CFF_SHIFT 1 03028 #define CMP_SCR_CFR_MASK 0x4u 03029 #define CMP_SCR_CFR_SHIFT 2 03030 #define CMP_SCR_IEF_MASK 0x8u 03031 #define CMP_SCR_IEF_SHIFT 3 03032 #define CMP_SCR_IER_MASK 0x10u 03033 #define CMP_SCR_IER_SHIFT 4 03034 #define CMP_SCR_DMAEN_MASK 0x40u 03035 #define CMP_SCR_DMAEN_SHIFT 6 03036 /* DACCR Bit Fields */ 03037 #define CMP_DACCR_VOSEL_MASK 0x3Fu 03038 #define CMP_DACCR_VOSEL_SHIFT 0 03039 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK) 03040 #define CMP_DACCR_VRSEL_MASK 0x40u 03041 #define CMP_DACCR_VRSEL_SHIFT 6 03042 #define CMP_DACCR_DACEN_MASK 0x80u 03043 #define CMP_DACCR_DACEN_SHIFT 7 03044 /* MUXCR Bit Fields */ 03045 #define CMP_MUXCR_MSEL_MASK 0x7u 03046 #define CMP_MUXCR_MSEL_SHIFT 0 03047 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK) 03048 #define CMP_MUXCR_PSEL_MASK 0x38u 03049 #define CMP_MUXCR_PSEL_SHIFT 3 03050 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK) 03051 #define CMP_MUXCR_PSTM_MASK 0x80u 03052 #define CMP_MUXCR_PSTM_SHIFT 7 03053 03054 /*! 03055 * @} 03056 */ /* end of group CMP_Register_Masks */ 03057 03058 03059 /* CMP - Peripheral instance base addresses */ 03060 /** Peripheral CMP0 base address */ 03061 #define CMP0_BASE (0x40073000u) 03062 /** Peripheral CMP0 base pointer */ 03063 #define CMP0 ((CMP_Type *)CMP0_BASE) 03064 #define CMP0_BASE_PTR (CMP0) 03065 /** Peripheral CMP1 base address */ 03066 #define CMP1_BASE (0x40073008u) 03067 /** Peripheral CMP1 base pointer */ 03068 #define CMP1 ((CMP_Type *)CMP1_BASE) 03069 #define CMP1_BASE_PTR (CMP1) 03070 /** Peripheral CMP2 base address */ 03071 #define CMP2_BASE (0x40073010u) 03072 /** Peripheral CMP2 base pointer */ 03073 #define CMP2 ((CMP_Type *)CMP2_BASE) 03074 #define CMP2_BASE_PTR (CMP2) 03075 /** Array initializer of CMP peripheral base addresses */ 03076 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } 03077 /** Array initializer of CMP peripheral base pointers */ 03078 #define CMP_BASE_PTRS { CMP0, CMP1, CMP2 } 03079 /** Interrupt vectors for the CMP peripheral type */ 03080 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn } 03081 03082 /* ---------------------------------------------------------------------------- 03083 -- CMP - Register accessor macros 03084 ---------------------------------------------------------------------------- */ 03085 03086 /*! 03087 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros 03088 * @{ 03089 */ 03090 03091 03092 /* CMP - Register instance definitions */ 03093 /* CMP0 */ 03094 #define CMP0_CR0 CMP_CR0_REG(CMP0) 03095 #define CMP0_CR1 CMP_CR1_REG(CMP0) 03096 #define CMP0_FPR CMP_FPR_REG(CMP0) 03097 #define CMP0_SCR CMP_SCR_REG(CMP0) 03098 #define CMP0_DACCR CMP_DACCR_REG(CMP0) 03099 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0) 03100 /* CMP1 */ 03101 #define CMP1_CR0 CMP_CR0_REG(CMP1) 03102 #define CMP1_CR1 CMP_CR1_REG(CMP1) 03103 #define CMP1_FPR CMP_FPR_REG(CMP1) 03104 #define CMP1_SCR CMP_SCR_REG(CMP1) 03105 #define CMP1_DACCR CMP_DACCR_REG(CMP1) 03106 #define CMP1_MUXCR CMP_MUXCR_REG(CMP1) 03107 /* CMP2 */ 03108 #define CMP2_CR0 CMP_CR0_REG(CMP2) 03109 #define CMP2_CR1 CMP_CR1_REG(CMP2) 03110 #define CMP2_FPR CMP_FPR_REG(CMP2) 03111 #define CMP2_SCR CMP_SCR_REG(CMP2) 03112 #define CMP2_DACCR CMP_DACCR_REG(CMP2) 03113 #define CMP2_MUXCR CMP_MUXCR_REG(CMP2) 03114 03115 /*! 03116 * @} 03117 */ /* end of group CMP_Register_Accessor_Macros */ 03118 03119 03120 /*! 03121 * @} 03122 */ /* end of group CMP_Peripheral_Access_Layer */ 03123 03124 03125 /* ---------------------------------------------------------------------------- 03126 -- CMT Peripheral Access Layer 03127 ---------------------------------------------------------------------------- */ 03128 03129 /*! 03130 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer 03131 * @{ 03132 */ 03133 03134 /** CMT - Register Layout Typedef */ 03135 typedef struct { 03136 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */ 03137 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */ 03138 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */ 03139 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */ 03140 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */ 03141 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */ 03142 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */ 03143 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */ 03144 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */ 03145 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */ 03146 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */ 03147 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */ 03148 } CMT_Type, *CMT_MemMapPtr; 03149 03150 /* ---------------------------------------------------------------------------- 03151 -- CMT - Register accessor macros 03152 ---------------------------------------------------------------------------- */ 03153 03154 /*! 03155 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros 03156 * @{ 03157 */ 03158 03159 03160 /* CMT - Register accessors */ 03161 #define CMT_CGH1_REG(base) ((base)->CGH1) 03162 #define CMT_CGL1_REG(base) ((base)->CGL1) 03163 #define CMT_CGH2_REG(base) ((base)->CGH2) 03164 #define CMT_CGL2_REG(base) ((base)->CGL2) 03165 #define CMT_OC_REG(base) ((base)->OC) 03166 #define CMT_MSC_REG(base) ((base)->MSC) 03167 #define CMT_CMD1_REG(base) ((base)->CMD1) 03168 #define CMT_CMD2_REG(base) ((base)->CMD2) 03169 #define CMT_CMD3_REG(base) ((base)->CMD3) 03170 #define CMT_CMD4_REG(base) ((base)->CMD4) 03171 #define CMT_PPS_REG(base) ((base)->PPS) 03172 #define CMT_DMA_REG(base) ((base)->DMA) 03173 03174 /*! 03175 * @} 03176 */ /* end of group CMT_Register_Accessor_Macros */ 03177 03178 03179 /* ---------------------------------------------------------------------------- 03180 -- CMT Register Masks 03181 ---------------------------------------------------------------------------- */ 03182 03183 /*! 03184 * @addtogroup CMT_Register_Masks CMT Register Masks 03185 * @{ 03186 */ 03187 03188 /* CGH1 Bit Fields */ 03189 #define CMT_CGH1_PH_MASK 0xFFu 03190 #define CMT_CGH1_PH_SHIFT 0 03191 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK) 03192 /* CGL1 Bit Fields */ 03193 #define CMT_CGL1_PL_MASK 0xFFu 03194 #define CMT_CGL1_PL_SHIFT 0 03195 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK) 03196 /* CGH2 Bit Fields */ 03197 #define CMT_CGH2_SH_MASK 0xFFu 03198 #define CMT_CGH2_SH_SHIFT 0 03199 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK) 03200 /* CGL2 Bit Fields */ 03201 #define CMT_CGL2_SL_MASK 0xFFu 03202 #define CMT_CGL2_SL_SHIFT 0 03203 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK) 03204 /* OC Bit Fields */ 03205 #define CMT_OC_IROPEN_MASK 0x20u 03206 #define CMT_OC_IROPEN_SHIFT 5 03207 #define CMT_OC_CMTPOL_MASK 0x40u 03208 #define CMT_OC_CMTPOL_SHIFT 6 03209 #define CMT_OC_IROL_MASK 0x80u 03210 #define CMT_OC_IROL_SHIFT 7 03211 /* MSC Bit Fields */ 03212 #define CMT_MSC_MCGEN_MASK 0x1u 03213 #define CMT_MSC_MCGEN_SHIFT 0 03214 #define CMT_MSC_EOCIE_MASK 0x2u 03215 #define CMT_MSC_EOCIE_SHIFT 1 03216 #define CMT_MSC_FSK_MASK 0x4u 03217 #define CMT_MSC_FSK_SHIFT 2 03218 #define CMT_MSC_BASE_MASK 0x8u 03219 #define CMT_MSC_BASE_SHIFT 3 03220 #define CMT_MSC_EXSPC_MASK 0x10u 03221 #define CMT_MSC_EXSPC_SHIFT 4 03222 #define CMT_MSC_CMTDIV_MASK 0x60u 03223 #define CMT_MSC_CMTDIV_SHIFT 5 03224 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK) 03225 #define CMT_MSC_EOCF_MASK 0x80u 03226 #define CMT_MSC_EOCF_SHIFT 7 03227 /* CMD1 Bit Fields */ 03228 #define CMT_CMD1_MB_MASK 0xFFu 03229 #define CMT_CMD1_MB_SHIFT 0 03230 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK) 03231 /* CMD2 Bit Fields */ 03232 #define CMT_CMD2_MB_MASK 0xFFu 03233 #define CMT_CMD2_MB_SHIFT 0 03234 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK) 03235 /* CMD3 Bit Fields */ 03236 #define CMT_CMD3_SB_MASK 0xFFu 03237 #define CMT_CMD3_SB_SHIFT 0 03238 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK) 03239 /* CMD4 Bit Fields */ 03240 #define CMT_CMD4_SB_MASK 0xFFu 03241 #define CMT_CMD4_SB_SHIFT 0 03242 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK) 03243 /* PPS Bit Fields */ 03244 #define CMT_PPS_PPSDIV_MASK 0xFu 03245 #define CMT_PPS_PPSDIV_SHIFT 0 03246 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK) 03247 /* DMA Bit Fields */ 03248 #define CMT_DMA_DMA_MASK 0x1u 03249 #define CMT_DMA_DMA_SHIFT 0 03250 03251 /*! 03252 * @} 03253 */ /* end of group CMT_Register_Masks */ 03254 03255 03256 /* CMT - Peripheral instance base addresses */ 03257 /** Peripheral CMT base address */ 03258 #define CMT_BASE (0x40062000u) 03259 /** Peripheral CMT base pointer */ 03260 #define CMT ((CMT_Type *)CMT_BASE) 03261 #define CMT_BASE_PTR (CMT) 03262 /** Array initializer of CMT peripheral base addresses */ 03263 #define CMT_BASE_ADDRS { CMT_BASE } 03264 /** Array initializer of CMT peripheral base pointers */ 03265 #define CMT_BASE_PTRS { CMT } 03266 /** Interrupt vectors for the CMT peripheral type */ 03267 #define CMT_IRQS { CMT_IRQn } 03268 03269 /* ---------------------------------------------------------------------------- 03270 -- CMT - Register accessor macros 03271 ---------------------------------------------------------------------------- */ 03272 03273 /*! 03274 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros 03275 * @{ 03276 */ 03277 03278 03279 /* CMT - Register instance definitions */ 03280 /* CMT */ 03281 #define CMT_CGH1 CMT_CGH1_REG(CMT) 03282 #define CMT_CGL1 CMT_CGL1_REG(CMT) 03283 #define CMT_CGH2 CMT_CGH2_REG(CMT) 03284 #define CMT_CGL2 CMT_CGL2_REG(CMT) 03285 #define CMT_OC CMT_OC_REG(CMT) 03286 #define CMT_MSC CMT_MSC_REG(CMT) 03287 #define CMT_CMD1 CMT_CMD1_REG(CMT) 03288 #define CMT_CMD2 CMT_CMD2_REG(CMT) 03289 #define CMT_CMD3 CMT_CMD3_REG(CMT) 03290 #define CMT_CMD4 CMT_CMD4_REG(CMT) 03291 #define CMT_PPS CMT_PPS_REG(CMT) 03292 #define CMT_DMA CMT_DMA_REG(CMT) 03293 03294 /*! 03295 * @} 03296 */ /* end of group CMT_Register_Accessor_Macros */ 03297 03298 03299 /*! 03300 * @} 03301 */ /* end of group CMT_Peripheral_Access_Layer */ 03302 03303 03304 /* ---------------------------------------------------------------------------- 03305 -- CRC Peripheral Access Layer 03306 ---------------------------------------------------------------------------- */ 03307 03308 /*! 03309 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer 03310 * @{ 03311 */ 03312 03313 /** CRC - Register Layout Typedef */ 03314 typedef struct { 03315 union { /* offset: 0x0 */ 03316 struct { /* offset: 0x0 */ 03317 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ 03318 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ 03319 } ACCESS16BIT; 03320 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ 03321 struct { /* offset: 0x0 */ 03322 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ 03323 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ 03324 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ 03325 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ 03326 } ACCESS8BIT; 03327 }; 03328 union { /* offset: 0x4 */ 03329 struct { /* offset: 0x4 */ 03330 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ 03331 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ 03332 } GPOLY_ACCESS16BIT; 03333 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ 03334 struct { /* offset: 0x4 */ 03335 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ 03336 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ 03337 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ 03338 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ 03339 } GPOLY_ACCESS8BIT; 03340 }; 03341 union { /* offset: 0x8 */ 03342 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ 03343 struct { /* offset: 0x8 */ 03344 uint8_t RESERVED_0[3]; 03345 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ 03346 } CTRL_ACCESS8BIT; 03347 }; 03348 } CRC_Type, *CRC_MemMapPtr; 03349 03350 /* ---------------------------------------------------------------------------- 03351 -- CRC - Register accessor macros 03352 ---------------------------------------------------------------------------- */ 03353 03354 /*! 03355 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros 03356 * @{ 03357 */ 03358 03359 03360 /* CRC - Register accessors */ 03361 #define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL) 03362 #define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH) 03363 #define CRC_DATA_REG(base) ((base)->DATA) 03364 #define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL) 03365 #define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU) 03366 #define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL) 03367 #define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU) 03368 #define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) 03369 #define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) 03370 #define CRC_GPOLY_REG(base) ((base)->GPOLY) 03371 #define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) 03372 #define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) 03373 #define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) 03374 #define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) 03375 #define CRC_CTRL_REG(base) ((base)->CTRL) 03376 #define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) 03377 03378 /*! 03379 * @} 03380 */ /* end of group CRC_Register_Accessor_Macros */ 03381 03382 03383 /* ---------------------------------------------------------------------------- 03384 -- CRC Register Masks 03385 ---------------------------------------------------------------------------- */ 03386 03387 /*! 03388 * @addtogroup CRC_Register_Masks CRC Register Masks 03389 * @{ 03390 */ 03391 03392 /* DATAL Bit Fields */ 03393 #define CRC_DATAL_DATAL_MASK 0xFFFFu 03394 #define CRC_DATAL_DATAL_SHIFT 0 03395 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK) 03396 /* DATAH Bit Fields */ 03397 #define CRC_DATAH_DATAH_MASK 0xFFFFu 03398 #define CRC_DATAH_DATAH_SHIFT 0 03399 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK) 03400 /* DATA Bit Fields */ 03401 #define CRC_DATA_LL_MASK 0xFFu 03402 #define CRC_DATA_LL_SHIFT 0 03403 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK) 03404 #define CRC_DATA_LU_MASK 0xFF00u 03405 #define CRC_DATA_LU_SHIFT 8 03406 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK) 03407 #define CRC_DATA_HL_MASK 0xFF0000u 03408 #define CRC_DATA_HL_SHIFT 16 03409 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK) 03410 #define CRC_DATA_HU_MASK 0xFF000000u 03411 #define CRC_DATA_HU_SHIFT 24 03412 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK) 03413 /* DATALL Bit Fields */ 03414 #define CRC_DATALL_DATALL_MASK 0xFFu 03415 #define CRC_DATALL_DATALL_SHIFT 0 03416 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK) 03417 /* DATALU Bit Fields */ 03418 #define CRC_DATALU_DATALU_MASK 0xFFu 03419 #define CRC_DATALU_DATALU_SHIFT 0 03420 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK) 03421 /* DATAHL Bit Fields */ 03422 #define CRC_DATAHL_DATAHL_MASK 0xFFu 03423 #define CRC_DATAHL_DATAHL_SHIFT 0 03424 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK) 03425 /* DATAHU Bit Fields */ 03426 #define CRC_DATAHU_DATAHU_MASK 0xFFu 03427 #define CRC_DATAHU_DATAHU_SHIFT 0 03428 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK) 03429 /* GPOLYL Bit Fields */ 03430 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu 03431 #define CRC_GPOLYL_GPOLYL_SHIFT 0 03432 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK) 03433 /* GPOLYH Bit Fields */ 03434 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu 03435 #define CRC_GPOLYH_GPOLYH_SHIFT 0 03436 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK) 03437 /* GPOLY Bit Fields */ 03438 #define CRC_GPOLY_LOW_MASK 0xFFFFu 03439 #define CRC_GPOLY_LOW_SHIFT 0 03440 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK) 03441 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u 03442 #define CRC_GPOLY_HIGH_SHIFT 16 03443 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK) 03444 /* GPOLYLL Bit Fields */ 03445 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu 03446 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0 03447 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK) 03448 /* GPOLYLU Bit Fields */ 03449 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu 03450 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0 03451 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK) 03452 /* GPOLYHL Bit Fields */ 03453 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu 03454 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0 03455 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK) 03456 /* GPOLYHU Bit Fields */ 03457 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu 03458 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0 03459 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK) 03460 /* CTRL Bit Fields */ 03461 #define CRC_CTRL_TCRC_MASK 0x1000000u 03462 #define CRC_CTRL_TCRC_SHIFT 24 03463 #define CRC_CTRL_WAS_MASK 0x2000000u 03464 #define CRC_CTRL_WAS_SHIFT 25 03465 #define CRC_CTRL_FXOR_MASK 0x4000000u 03466 #define CRC_CTRL_FXOR_SHIFT 26 03467 #define CRC_CTRL_TOTR_MASK 0x30000000u 03468 #define CRC_CTRL_TOTR_SHIFT 28 03469 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK) 03470 #define CRC_CTRL_TOT_MASK 0xC0000000u 03471 #define CRC_CTRL_TOT_SHIFT 30 03472 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK) 03473 /* CTRLHU Bit Fields */ 03474 #define CRC_CTRLHU_TCRC_MASK 0x1u 03475 #define CRC_CTRLHU_TCRC_SHIFT 0 03476 #define CRC_CTRLHU_WAS_MASK 0x2u 03477 #define CRC_CTRLHU_WAS_SHIFT 1 03478 #define CRC_CTRLHU_FXOR_MASK 0x4u 03479 #define CRC_CTRLHU_FXOR_SHIFT 2 03480 #define CRC_CTRLHU_TOTR_MASK 0x30u 03481 #define CRC_CTRLHU_TOTR_SHIFT 4 03482 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK) 03483 #define CRC_CTRLHU_TOT_MASK 0xC0u 03484 #define CRC_CTRLHU_TOT_SHIFT 6 03485 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK) 03486 03487 /*! 03488 * @} 03489 */ /* end of group CRC_Register_Masks */ 03490 03491 03492 /* CRC - Peripheral instance base addresses */ 03493 /** Peripheral CRC base address */ 03494 #define CRC_BASE (0x40032000u) 03495 /** Peripheral CRC base pointer */ 03496 #define CRC0 ((CRC_Type *)CRC_BASE) 03497 #define CRC_BASE_PTR (CRC0) 03498 /** Array initializer of CRC peripheral base addresses */ 03499 #define CRC_BASE_ADDRS { CRC_BASE } 03500 /** Array initializer of CRC peripheral base pointers */ 03501 #define CRC_BASE_PTRS { CRC0 } 03502 03503 /* ---------------------------------------------------------------------------- 03504 -- CRC - Register accessor macros 03505 ---------------------------------------------------------------------------- */ 03506 03507 /*! 03508 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros 03509 * @{ 03510 */ 03511 03512 03513 /* CRC - Register instance definitions */ 03514 /* CRC */ 03515 #define CRC_DATA CRC_DATA_REG(CRC0) 03516 #define CRC_DATAL CRC_DATAL_REG(CRC0) 03517 #define CRC_DATALL CRC_DATALL_REG(CRC0) 03518 #define CRC_DATALU CRC_DATALU_REG(CRC0) 03519 #define CRC_DATAH CRC_DATAH_REG(CRC0) 03520 #define CRC_DATAHL CRC_DATAHL_REG(CRC0) 03521 #define CRC_DATAHU CRC_DATAHU_REG(CRC0) 03522 #define CRC_GPOLY CRC_GPOLY_REG(CRC0) 03523 #define CRC_GPOLYL CRC_GPOLYL_REG(CRC0) 03524 #define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0) 03525 #define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0) 03526 #define CRC_GPOLYH CRC_GPOLYH_REG(CRC0) 03527 #define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0) 03528 #define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0) 03529 #define CRC_CTRL CRC_CTRL_REG(CRC0) 03530 #define CRC_CTRLHU CRC_CTRLHU_REG(CRC0) 03531 03532 /*! 03533 * @} 03534 */ /* end of group CRC_Register_Accessor_Macros */ 03535 03536 03537 /*! 03538 * @} 03539 */ /* end of group CRC_Peripheral_Access_Layer */ 03540 03541 03542 /* ---------------------------------------------------------------------------- 03543 -- DAC Peripheral Access Layer 03544 ---------------------------------------------------------------------------- */ 03545 03546 /*! 03547 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer 03548 * @{ 03549 */ 03550 03551 /** DAC - Register Layout Typedef */ 03552 typedef struct { 03553 struct { /* offset: 0x0, array step: 0x2 */ 03554 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ 03555 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ 03556 } DAT[16]; 03557 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ 03558 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ 03559 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ 03560 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ 03561 } DAC_Type, *DAC_MemMapPtr; 03562 03563 /* ---------------------------------------------------------------------------- 03564 -- DAC - Register accessor macros 03565 ---------------------------------------------------------------------------- */ 03566 03567 /*! 03568 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros 03569 * @{ 03570 */ 03571 03572 03573 /* DAC - Register accessors */ 03574 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL) 03575 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) 03576 #define DAC_SR_REG(base) ((base)->SR) 03577 #define DAC_C0_REG(base) ((base)->C0) 03578 #define DAC_C1_REG(base) ((base)->C1) 03579 #define DAC_C2_REG(base) ((base)->C2) 03580 03581 /*! 03582 * @} 03583 */ /* end of group DAC_Register_Accessor_Macros */ 03584 03585 03586 /* ---------------------------------------------------------------------------- 03587 -- DAC Register Masks 03588 ---------------------------------------------------------------------------- */ 03589 03590 /*! 03591 * @addtogroup DAC_Register_Masks DAC Register Masks 03592 * @{ 03593 */ 03594 03595 /* DATL Bit Fields */ 03596 #define DAC_DATL_DATA0_MASK 0xFFu 03597 #define DAC_DATL_DATA0_SHIFT 0 03598 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK) 03599 /* DATH Bit Fields */ 03600 #define DAC_DATH_DATA1_MASK 0xFu 03601 #define DAC_DATH_DATA1_SHIFT 0 03602 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK) 03603 /* SR Bit Fields */ 03604 #define DAC_SR_DACBFRPBF_MASK 0x1u 03605 #define DAC_SR_DACBFRPBF_SHIFT 0 03606 #define DAC_SR_DACBFRPTF_MASK 0x2u 03607 #define DAC_SR_DACBFRPTF_SHIFT 1 03608 #define DAC_SR_DACBFWMF_MASK 0x4u 03609 #define DAC_SR_DACBFWMF_SHIFT 2 03610 /* C0 Bit Fields */ 03611 #define DAC_C0_DACBBIEN_MASK 0x1u 03612 #define DAC_C0_DACBBIEN_SHIFT 0 03613 #define DAC_C0_DACBTIEN_MASK 0x2u 03614 #define DAC_C0_DACBTIEN_SHIFT 1 03615 #define DAC_C0_DACBWIEN_MASK 0x4u 03616 #define DAC_C0_DACBWIEN_SHIFT 2 03617 #define DAC_C0_LPEN_MASK 0x8u 03618 #define DAC_C0_LPEN_SHIFT 3 03619 #define DAC_C0_DACSWTRG_MASK 0x10u 03620 #define DAC_C0_DACSWTRG_SHIFT 4 03621 #define DAC_C0_DACTRGSEL_MASK 0x20u 03622 #define DAC_C0_DACTRGSEL_SHIFT 5 03623 #define DAC_C0_DACRFS_MASK 0x40u 03624 #define DAC_C0_DACRFS_SHIFT 6 03625 #define DAC_C0_DACEN_MASK 0x80u 03626 #define DAC_C0_DACEN_SHIFT 7 03627 /* C1 Bit Fields */ 03628 #define DAC_C1_DACBFEN_MASK 0x1u 03629 #define DAC_C1_DACBFEN_SHIFT 0 03630 #define DAC_C1_DACBFMD_MASK 0x6u 03631 #define DAC_C1_DACBFMD_SHIFT 1 03632 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK) 03633 #define DAC_C1_DACBFWM_MASK 0x18u 03634 #define DAC_C1_DACBFWM_SHIFT 3 03635 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK) 03636 #define DAC_C1_DMAEN_MASK 0x80u 03637 #define DAC_C1_DMAEN_SHIFT 7 03638 /* C2 Bit Fields */ 03639 #define DAC_C2_DACBFUP_MASK 0xFu 03640 #define DAC_C2_DACBFUP_SHIFT 0 03641 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK) 03642 #define DAC_C2_DACBFRP_MASK 0xF0u 03643 #define DAC_C2_DACBFRP_SHIFT 4 03644 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK) 03645 03646 /*! 03647 * @} 03648 */ /* end of group DAC_Register_Masks */ 03649 03650 03651 /* DAC - Peripheral instance base addresses */ 03652 /** Peripheral DAC0 base address */ 03653 #define DAC0_BASE (0x400CC000u) 03654 /** Peripheral DAC0 base pointer */ 03655 #define DAC0 ((DAC_Type *)DAC0_BASE) 03656 #define DAC0_BASE_PTR (DAC0) 03657 /** Peripheral DAC1 base address */ 03658 #define DAC1_BASE (0x400CD000u) 03659 /** Peripheral DAC1 base pointer */ 03660 #define DAC1 ((DAC_Type *)DAC1_BASE) 03661 #define DAC1_BASE_PTR (DAC1) 03662 /** Array initializer of DAC peripheral base addresses */ 03663 #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } 03664 /** Array initializer of DAC peripheral base pointers */ 03665 #define DAC_BASE_PTRS { DAC0, DAC1 } 03666 /** Interrupt vectors for the DAC peripheral type */ 03667 #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn } 03668 03669 /* ---------------------------------------------------------------------------- 03670 -- DAC - Register accessor macros 03671 ---------------------------------------------------------------------------- */ 03672 03673 /*! 03674 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros 03675 * @{ 03676 */ 03677 03678 03679 /* DAC - Register instance definitions */ 03680 /* DAC0 */ 03681 #define DAC0_DAT0L DAC_DATL_REG(DAC0,0) 03682 #define DAC0_DAT0H DAC_DATH_REG(DAC0,0) 03683 #define DAC0_DAT1L DAC_DATL_REG(DAC0,1) 03684 #define DAC0_DAT1H DAC_DATH_REG(DAC0,1) 03685 #define DAC0_DAT2L DAC_DATL_REG(DAC0,2) 03686 #define DAC0_DAT2H DAC_DATH_REG(DAC0,2) 03687 #define DAC0_DAT3L DAC_DATL_REG(DAC0,3) 03688 #define DAC0_DAT3H DAC_DATH_REG(DAC0,3) 03689 #define DAC0_DAT4L DAC_DATL_REG(DAC0,4) 03690 #define DAC0_DAT4H DAC_DATH_REG(DAC0,4) 03691 #define DAC0_DAT5L DAC_DATL_REG(DAC0,5) 03692 #define DAC0_DAT5H DAC_DATH_REG(DAC0,5) 03693 #define DAC0_DAT6L DAC_DATL_REG(DAC0,6) 03694 #define DAC0_DAT6H DAC_DATH_REG(DAC0,6) 03695 #define DAC0_DAT7L DAC_DATL_REG(DAC0,7) 03696 #define DAC0_DAT7H DAC_DATH_REG(DAC0,7) 03697 #define DAC0_DAT8L DAC_DATL_REG(DAC0,8) 03698 #define DAC0_DAT8H DAC_DATH_REG(DAC0,8) 03699 #define DAC0_DAT9L DAC_DATL_REG(DAC0,9) 03700 #define DAC0_DAT9H DAC_DATH_REG(DAC0,9) 03701 #define DAC0_DAT10L DAC_DATL_REG(DAC0,10) 03702 #define DAC0_DAT10H DAC_DATH_REG(DAC0,10) 03703 #define DAC0_DAT11L DAC_DATL_REG(DAC0,11) 03704 #define DAC0_DAT11H DAC_DATH_REG(DAC0,11) 03705 #define DAC0_DAT12L DAC_DATL_REG(DAC0,12) 03706 #define DAC0_DAT12H DAC_DATH_REG(DAC0,12) 03707 #define DAC0_DAT13L DAC_DATL_REG(DAC0,13) 03708 #define DAC0_DAT13H DAC_DATH_REG(DAC0,13) 03709 #define DAC0_DAT14L DAC_DATL_REG(DAC0,14) 03710 #define DAC0_DAT14H DAC_DATH_REG(DAC0,14) 03711 #define DAC0_DAT15L DAC_DATL_REG(DAC0,15) 03712 #define DAC0_DAT15H DAC_DATH_REG(DAC0,15) 03713 #define DAC0_SR DAC_SR_REG(DAC0) 03714 #define DAC0_C0 DAC_C0_REG(DAC0) 03715 #define DAC0_C1 DAC_C1_REG(DAC0) 03716 #define DAC0_C2 DAC_C2_REG(DAC0) 03717 /* DAC1 */ 03718 #define DAC1_DAT0L DAC_DATL_REG(DAC1,0) 03719 #define DAC1_DAT0H DAC_DATH_REG(DAC1,0) 03720 #define DAC1_DAT1L DAC_DATL_REG(DAC1,1) 03721 #define DAC1_DAT1H DAC_DATH_REG(DAC1,1) 03722 #define DAC1_DAT2L DAC_DATL_REG(DAC1,2) 03723 #define DAC1_DAT2H DAC_DATH_REG(DAC1,2) 03724 #define DAC1_DAT3L DAC_DATL_REG(DAC1,3) 03725 #define DAC1_DAT3H DAC_DATH_REG(DAC1,3) 03726 #define DAC1_DAT4L DAC_DATL_REG(DAC1,4) 03727 #define DAC1_DAT4H DAC_DATH_REG(DAC1,4) 03728 #define DAC1_DAT5L DAC_DATL_REG(DAC1,5) 03729 #define DAC1_DAT5H DAC_DATH_REG(DAC1,5) 03730 #define DAC1_DAT6L DAC_DATL_REG(DAC1,6) 03731 #define DAC1_DAT6H DAC_DATH_REG(DAC1,6) 03732 #define DAC1_DAT7L DAC_DATL_REG(DAC1,7) 03733 #define DAC1_DAT7H DAC_DATH_REG(DAC1,7) 03734 #define DAC1_DAT8L DAC_DATL_REG(DAC1,8) 03735 #define DAC1_DAT8H DAC_DATH_REG(DAC1,8) 03736 #define DAC1_DAT9L DAC_DATL_REG(DAC1,9) 03737 #define DAC1_DAT9H DAC_DATH_REG(DAC1,9) 03738 #define DAC1_DAT10L DAC_DATL_REG(DAC1,10) 03739 #define DAC1_DAT10H DAC_DATH_REG(DAC1,10) 03740 #define DAC1_DAT11L DAC_DATL_REG(DAC1,11) 03741 #define DAC1_DAT11H DAC_DATH_REG(DAC1,11) 03742 #define DAC1_DAT12L DAC_DATL_REG(DAC1,12) 03743 #define DAC1_DAT12H DAC_DATH_REG(DAC1,12) 03744 #define DAC1_DAT13L DAC_DATL_REG(DAC1,13) 03745 #define DAC1_DAT13H DAC_DATH_REG(DAC1,13) 03746 #define DAC1_DAT14L DAC_DATL_REG(DAC1,14) 03747 #define DAC1_DAT14H DAC_DATH_REG(DAC1,14) 03748 #define DAC1_DAT15L DAC_DATL_REG(DAC1,15) 03749 #define DAC1_DAT15H DAC_DATH_REG(DAC1,15) 03750 #define DAC1_SR DAC_SR_REG(DAC1) 03751 #define DAC1_C0 DAC_C0_REG(DAC1) 03752 #define DAC1_C1 DAC_C1_REG(DAC1) 03753 #define DAC1_C2 DAC_C2_REG(DAC1) 03754 03755 /* DAC - Register array accessors */ 03756 #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index) 03757 #define DAC1_DATL(index) DAC_DATL_REG(DAC1,index) 03758 #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index) 03759 #define DAC1_DATH(index) DAC_DATH_REG(DAC1,index) 03760 03761 /*! 03762 * @} 03763 */ /* end of group DAC_Register_Accessor_Macros */ 03764 03765 03766 /*! 03767 * @} 03768 */ /* end of group DAC_Peripheral_Access_Layer */ 03769 03770 03771 /* ---------------------------------------------------------------------------- 03772 -- DMA Peripheral Access Layer 03773 ---------------------------------------------------------------------------- */ 03774 03775 /*! 03776 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer 03777 * @{ 03778 */ 03779 03780 /** DMA - Register Layout Typedef */ 03781 typedef struct { 03782 __IO uint32_t CR; /**< Control Register, offset: 0x0 */ 03783 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ 03784 uint8_t RESERVED_0[4]; 03785 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ 03786 uint8_t RESERVED_1[4]; 03787 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ 03788 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ 03789 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ 03790 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ 03791 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ 03792 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ 03793 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ 03794 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ 03795 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ 03796 uint8_t RESERVED_2[4]; 03797 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ 03798 uint8_t RESERVED_3[4]; 03799 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ 03800 uint8_t RESERVED_4[4]; 03801 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ 03802 uint8_t RESERVED_5[200]; 03803 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ 03804 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ 03805 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ 03806 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ 03807 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ 03808 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ 03809 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ 03810 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ 03811 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ 03812 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ 03813 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ 03814 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ 03815 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ 03816 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ 03817 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ 03818 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ 03819 uint8_t RESERVED_6[3824]; 03820 struct { /* offset: 0x1000, array step: 0x20 */ 03821 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ 03822 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ 03823 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ 03824 union { /* offset: 0x1008, array step: 0x20 */ 03825 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */ 03826 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ 03827 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */ 03828 }; 03829 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ 03830 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ 03831 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ 03832 union { /* offset: 0x1016, array step: 0x20 */ 03833 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ 03834 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ 03835 }; 03836 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ 03837 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ 03838 union { /* offset: 0x101E, array step: 0x20 */ 03839 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ 03840 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ 03841 }; 03842 } TCD[16]; 03843 } DMA_Type, *DMA_MemMapPtr; 03844 03845 /* ---------------------------------------------------------------------------- 03846 -- DMA - Register accessor macros 03847 ---------------------------------------------------------------------------- */ 03848 03849 /*! 03850 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros 03851 * @{ 03852 */ 03853 03854 03855 /* DMA - Register accessors */ 03856 #define DMA_CR_REG(base) ((base)->CR) 03857 #define DMA_ES_REG(base) ((base)->ES) 03858 #define DMA_ERQ_REG(base) ((base)->ERQ) 03859 #define DMA_EEI_REG(base) ((base)->EEI) 03860 #define DMA_CEEI_REG(base) ((base)->CEEI) 03861 #define DMA_SEEI_REG(base) ((base)->SEEI) 03862 #define DMA_CERQ_REG(base) ((base)->CERQ) 03863 #define DMA_SERQ_REG(base) ((base)->SERQ) 03864 #define DMA_CDNE_REG(base) ((base)->CDNE) 03865 #define DMA_SSRT_REG(base) ((base)->SSRT) 03866 #define DMA_CERR_REG(base) ((base)->CERR) 03867 #define DMA_CINT_REG(base) ((base)->CINT) 03868 #define DMA_INT_REG(base) ((base)->INT) 03869 #define DMA_ERR_REG(base) ((base)->ERR) 03870 #define DMA_HRS_REG(base) ((base)->HRS) 03871 #define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) 03872 #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) 03873 #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) 03874 #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) 03875 #define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) 03876 #define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) 03877 #define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) 03878 #define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) 03879 #define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) 03880 #define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) 03881 #define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) 03882 #define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) 03883 #define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) 03884 #define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) 03885 #define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) 03886 #define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) 03887 #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) 03888 #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) 03889 #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) 03890 #define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) 03891 #define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) 03892 #define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) 03893 #define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) 03894 #define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) 03895 #define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) 03896 #define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) 03897 #define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) 03898 #define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) 03899 #define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) 03900 #define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) 03901 #define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) 03902 03903 /*! 03904 * @} 03905 */ /* end of group DMA_Register_Accessor_Macros */ 03906 03907 03908 /* ---------------------------------------------------------------------------- 03909 -- DMA Register Masks 03910 ---------------------------------------------------------------------------- */ 03911 03912 /*! 03913 * @addtogroup DMA_Register_Masks DMA Register Masks 03914 * @{ 03915 */ 03916 03917 /* CR Bit Fields */ 03918 #define DMA_CR_EDBG_MASK 0x2u 03919 #define DMA_CR_EDBG_SHIFT 1 03920 #define DMA_CR_ERCA_MASK 0x4u 03921 #define DMA_CR_ERCA_SHIFT 2 03922 #define DMA_CR_HOE_MASK 0x10u 03923 #define DMA_CR_HOE_SHIFT 4 03924 #define DMA_CR_HALT_MASK 0x20u 03925 #define DMA_CR_HALT_SHIFT 5 03926 #define DMA_CR_CLM_MASK 0x40u 03927 #define DMA_CR_CLM_SHIFT 6 03928 #define DMA_CR_EMLM_MASK 0x80u 03929 #define DMA_CR_EMLM_SHIFT 7 03930 #define DMA_CR_ECX_MASK 0x10000u 03931 #define DMA_CR_ECX_SHIFT 16 03932 #define DMA_CR_CX_MASK 0x20000u 03933 #define DMA_CR_CX_SHIFT 17 03934 /* ES Bit Fields */ 03935 #define DMA_ES_DBE_MASK 0x1u 03936 #define DMA_ES_DBE_SHIFT 0 03937 #define DMA_ES_SBE_MASK 0x2u 03938 #define DMA_ES_SBE_SHIFT 1 03939 #define DMA_ES_SGE_MASK 0x4u 03940 #define DMA_ES_SGE_SHIFT 2 03941 #define DMA_ES_NCE_MASK 0x8u 03942 #define DMA_ES_NCE_SHIFT 3 03943 #define DMA_ES_DOE_MASK 0x10u 03944 #define DMA_ES_DOE_SHIFT 4 03945 #define DMA_ES_DAE_MASK 0x20u 03946 #define DMA_ES_DAE_SHIFT 5 03947 #define DMA_ES_SOE_MASK 0x40u 03948 #define DMA_ES_SOE_SHIFT 6 03949 #define DMA_ES_SAE_MASK 0x80u 03950 #define DMA_ES_SAE_SHIFT 7 03951 #define DMA_ES_ERRCHN_MASK 0xF00u 03952 #define DMA_ES_ERRCHN_SHIFT 8 03953 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK) 03954 #define DMA_ES_CPE_MASK 0x4000u 03955 #define DMA_ES_CPE_SHIFT 14 03956 #define DMA_ES_ECX_MASK 0x10000u 03957 #define DMA_ES_ECX_SHIFT 16 03958 #define DMA_ES_VLD_MASK 0x80000000u 03959 #define DMA_ES_VLD_SHIFT 31 03960 /* ERQ Bit Fields */ 03961 #define DMA_ERQ_ERQ0_MASK 0x1u 03962 #define DMA_ERQ_ERQ0_SHIFT 0 03963 #define DMA_ERQ_ERQ1_MASK 0x2u 03964 #define DMA_ERQ_ERQ1_SHIFT 1 03965 #define DMA_ERQ_ERQ2_MASK 0x4u 03966 #define DMA_ERQ_ERQ2_SHIFT 2 03967 #define DMA_ERQ_ERQ3_MASK 0x8u 03968 #define DMA_ERQ_ERQ3_SHIFT 3 03969 #define DMA_ERQ_ERQ4_MASK 0x10u 03970 #define DMA_ERQ_ERQ4_SHIFT 4 03971 #define DMA_ERQ_ERQ5_MASK 0x20u 03972 #define DMA_ERQ_ERQ5_SHIFT 5 03973 #define DMA_ERQ_ERQ6_MASK 0x40u 03974 #define DMA_ERQ_ERQ6_SHIFT 6 03975 #define DMA_ERQ_ERQ7_MASK 0x80u 03976 #define DMA_ERQ_ERQ7_SHIFT 7 03977 #define DMA_ERQ_ERQ8_MASK 0x100u 03978 #define DMA_ERQ_ERQ8_SHIFT 8 03979 #define DMA_ERQ_ERQ9_MASK 0x200u 03980 #define DMA_ERQ_ERQ9_SHIFT 9 03981 #define DMA_ERQ_ERQ10_MASK 0x400u 03982 #define DMA_ERQ_ERQ10_SHIFT 10 03983 #define DMA_ERQ_ERQ11_MASK 0x800u 03984 #define DMA_ERQ_ERQ11_SHIFT 11 03985 #define DMA_ERQ_ERQ12_MASK 0x1000u 03986 #define DMA_ERQ_ERQ12_SHIFT 12 03987 #define DMA_ERQ_ERQ13_MASK 0x2000u 03988 #define DMA_ERQ_ERQ13_SHIFT 13 03989 #define DMA_ERQ_ERQ14_MASK 0x4000u 03990 #define DMA_ERQ_ERQ14_SHIFT 14 03991 #define DMA_ERQ_ERQ15_MASK 0x8000u 03992 #define DMA_ERQ_ERQ15_SHIFT 15 03993 /* EEI Bit Fields */ 03994 #define DMA_EEI_EEI0_MASK 0x1u 03995 #define DMA_EEI_EEI0_SHIFT 0 03996 #define DMA_EEI_EEI1_MASK 0x2u 03997 #define DMA_EEI_EEI1_SHIFT 1 03998 #define DMA_EEI_EEI2_MASK 0x4u 03999 #define DMA_EEI_EEI2_SHIFT 2 04000 #define DMA_EEI_EEI3_MASK 0x8u 04001 #define DMA_EEI_EEI3_SHIFT 3 04002 #define DMA_EEI_EEI4_MASK 0x10u 04003 #define DMA_EEI_EEI4_SHIFT 4 04004 #define DMA_EEI_EEI5_MASK 0x20u 04005 #define DMA_EEI_EEI5_SHIFT 5 04006 #define DMA_EEI_EEI6_MASK 0x40u 04007 #define DMA_EEI_EEI6_SHIFT 6 04008 #define DMA_EEI_EEI7_MASK 0x80u 04009 #define DMA_EEI_EEI7_SHIFT 7 04010 #define DMA_EEI_EEI8_MASK 0x100u 04011 #define DMA_EEI_EEI8_SHIFT 8 04012 #define DMA_EEI_EEI9_MASK 0x200u 04013 #define DMA_EEI_EEI9_SHIFT 9 04014 #define DMA_EEI_EEI10_MASK 0x400u 04015 #define DMA_EEI_EEI10_SHIFT 10 04016 #define DMA_EEI_EEI11_MASK 0x800u 04017 #define DMA_EEI_EEI11_SHIFT 11 04018 #define DMA_EEI_EEI12_MASK 0x1000u 04019 #define DMA_EEI_EEI12_SHIFT 12 04020 #define DMA_EEI_EEI13_MASK 0x2000u 04021 #define DMA_EEI_EEI13_SHIFT 13 04022 #define DMA_EEI_EEI14_MASK 0x4000u 04023 #define DMA_EEI_EEI14_SHIFT 14 04024 #define DMA_EEI_EEI15_MASK 0x8000u 04025 #define DMA_EEI_EEI15_SHIFT 15 04026 /* CEEI Bit Fields */ 04027 #define DMA_CEEI_CEEI_MASK 0xFu 04028 #define DMA_CEEI_CEEI_SHIFT 0 04029 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK) 04030 #define DMA_CEEI_CAEE_MASK 0x40u 04031 #define DMA_CEEI_CAEE_SHIFT 6 04032 #define DMA_CEEI_NOP_MASK 0x80u 04033 #define DMA_CEEI_NOP_SHIFT 7 04034 /* SEEI Bit Fields */ 04035 #define DMA_SEEI_SEEI_MASK 0xFu 04036 #define DMA_SEEI_SEEI_SHIFT 0 04037 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK) 04038 #define DMA_SEEI_SAEE_MASK 0x40u 04039 #define DMA_SEEI_SAEE_SHIFT 6 04040 #define DMA_SEEI_NOP_MASK 0x80u 04041 #define DMA_SEEI_NOP_SHIFT 7 04042 /* CERQ Bit Fields */ 04043 #define DMA_CERQ_CERQ_MASK 0xFu 04044 #define DMA_CERQ_CERQ_SHIFT 0 04045 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK) 04046 #define DMA_CERQ_CAER_MASK 0x40u 04047 #define DMA_CERQ_CAER_SHIFT 6 04048 #define DMA_CERQ_NOP_MASK 0x80u 04049 #define DMA_CERQ_NOP_SHIFT 7 04050 /* SERQ Bit Fields */ 04051 #define DMA_SERQ_SERQ_MASK 0xFu 04052 #define DMA_SERQ_SERQ_SHIFT 0 04053 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK) 04054 #define DMA_SERQ_SAER_MASK 0x40u 04055 #define DMA_SERQ_SAER_SHIFT 6 04056 #define DMA_SERQ_NOP_MASK 0x80u 04057 #define DMA_SERQ_NOP_SHIFT 7 04058 /* CDNE Bit Fields */ 04059 #define DMA_CDNE_CDNE_MASK 0xFu 04060 #define DMA_CDNE_CDNE_SHIFT 0 04061 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK) 04062 #define DMA_CDNE_CADN_MASK 0x40u 04063 #define DMA_CDNE_CADN_SHIFT 6 04064 #define DMA_CDNE_NOP_MASK 0x80u 04065 #define DMA_CDNE_NOP_SHIFT 7 04066 /* SSRT Bit Fields */ 04067 #define DMA_SSRT_SSRT_MASK 0xFu 04068 #define DMA_SSRT_SSRT_SHIFT 0 04069 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK) 04070 #define DMA_SSRT_SAST_MASK 0x40u 04071 #define DMA_SSRT_SAST_SHIFT 6 04072 #define DMA_SSRT_NOP_MASK 0x80u 04073 #define DMA_SSRT_NOP_SHIFT 7 04074 /* CERR Bit Fields */ 04075 #define DMA_CERR_CERR_MASK 0xFu 04076 #define DMA_CERR_CERR_SHIFT 0 04077 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK) 04078 #define DMA_CERR_CAEI_MASK 0x40u 04079 #define DMA_CERR_CAEI_SHIFT 6 04080 #define DMA_CERR_NOP_MASK 0x80u 04081 #define DMA_CERR_NOP_SHIFT 7 04082 /* CINT Bit Fields */ 04083 #define DMA_CINT_CINT_MASK 0xFu 04084 #define DMA_CINT_CINT_SHIFT 0 04085 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK) 04086 #define DMA_CINT_CAIR_MASK 0x40u 04087 #define DMA_CINT_CAIR_SHIFT 6 04088 #define DMA_CINT_NOP_MASK 0x80u 04089 #define DMA_CINT_NOP_SHIFT 7 04090 /* INT Bit Fields */ 04091 #define DMA_INT_INT0_MASK 0x1u 04092 #define DMA_INT_INT0_SHIFT 0 04093 #define DMA_INT_INT1_MASK 0x2u 04094 #define DMA_INT_INT1_SHIFT 1 04095 #define DMA_INT_INT2_MASK 0x4u 04096 #define DMA_INT_INT2_SHIFT 2 04097 #define DMA_INT_INT3_MASK 0x8u 04098 #define DMA_INT_INT3_SHIFT 3 04099 #define DMA_INT_INT4_MASK 0x10u 04100 #define DMA_INT_INT4_SHIFT 4 04101 #define DMA_INT_INT5_MASK 0x20u 04102 #define DMA_INT_INT5_SHIFT 5 04103 #define DMA_INT_INT6_MASK 0x40u 04104 #define DMA_INT_INT6_SHIFT 6 04105 #define DMA_INT_INT7_MASK 0x80u 04106 #define DMA_INT_INT7_SHIFT 7 04107 #define DMA_INT_INT8_MASK 0x100u 04108 #define DMA_INT_INT8_SHIFT 8 04109 #define DMA_INT_INT9_MASK 0x200u 04110 #define DMA_INT_INT9_SHIFT 9 04111 #define DMA_INT_INT10_MASK 0x400u 04112 #define DMA_INT_INT10_SHIFT 10 04113 #define DMA_INT_INT11_MASK 0x800u 04114 #define DMA_INT_INT11_SHIFT 11 04115 #define DMA_INT_INT12_MASK 0x1000u 04116 #define DMA_INT_INT12_SHIFT 12 04117 #define DMA_INT_INT13_MASK 0x2000u 04118 #define DMA_INT_INT13_SHIFT 13 04119 #define DMA_INT_INT14_MASK 0x4000u 04120 #define DMA_INT_INT14_SHIFT 14 04121 #define DMA_INT_INT15_MASK 0x8000u 04122 #define DMA_INT_INT15_SHIFT 15 04123 /* ERR Bit Fields */ 04124 #define DMA_ERR_ERR0_MASK 0x1u 04125 #define DMA_ERR_ERR0_SHIFT 0 04126 #define DMA_ERR_ERR1_MASK 0x2u 04127 #define DMA_ERR_ERR1_SHIFT 1 04128 #define DMA_ERR_ERR2_MASK 0x4u 04129 #define DMA_ERR_ERR2_SHIFT 2 04130 #define DMA_ERR_ERR3_MASK 0x8u 04131 #define DMA_ERR_ERR3_SHIFT 3 04132 #define DMA_ERR_ERR4_MASK 0x10u 04133 #define DMA_ERR_ERR4_SHIFT 4 04134 #define DMA_ERR_ERR5_MASK 0x20u 04135 #define DMA_ERR_ERR5_SHIFT 5 04136 #define DMA_ERR_ERR6_MASK 0x40u 04137 #define DMA_ERR_ERR6_SHIFT 6 04138 #define DMA_ERR_ERR7_MASK 0x80u 04139 #define DMA_ERR_ERR7_SHIFT 7 04140 #define DMA_ERR_ERR8_MASK 0x100u 04141 #define DMA_ERR_ERR8_SHIFT 8 04142 #define DMA_ERR_ERR9_MASK 0x200u 04143 #define DMA_ERR_ERR9_SHIFT 9 04144 #define DMA_ERR_ERR10_MASK 0x400u 04145 #define DMA_ERR_ERR10_SHIFT 10 04146 #define DMA_ERR_ERR11_MASK 0x800u 04147 #define DMA_ERR_ERR11_SHIFT 11 04148 #define DMA_ERR_ERR12_MASK 0x1000u 04149 #define DMA_ERR_ERR12_SHIFT 12 04150 #define DMA_ERR_ERR13_MASK 0x2000u 04151 #define DMA_ERR_ERR13_SHIFT 13 04152 #define DMA_ERR_ERR14_MASK 0x4000u 04153 #define DMA_ERR_ERR14_SHIFT 14 04154 #define DMA_ERR_ERR15_MASK 0x8000u 04155 #define DMA_ERR_ERR15_SHIFT 15 04156 /* HRS Bit Fields */ 04157 #define DMA_HRS_HRS0_MASK 0x1u 04158 #define DMA_HRS_HRS0_SHIFT 0 04159 #define DMA_HRS_HRS1_MASK 0x2u 04160 #define DMA_HRS_HRS1_SHIFT 1 04161 #define DMA_HRS_HRS2_MASK 0x4u 04162 #define DMA_HRS_HRS2_SHIFT 2 04163 #define DMA_HRS_HRS3_MASK 0x8u 04164 #define DMA_HRS_HRS3_SHIFT 3 04165 #define DMA_HRS_HRS4_MASK 0x10u 04166 #define DMA_HRS_HRS4_SHIFT 4 04167 #define DMA_HRS_HRS5_MASK 0x20u 04168 #define DMA_HRS_HRS5_SHIFT 5 04169 #define DMA_HRS_HRS6_MASK 0x40u 04170 #define DMA_HRS_HRS6_SHIFT 6 04171 #define DMA_HRS_HRS7_MASK 0x80u 04172 #define DMA_HRS_HRS7_SHIFT 7 04173 #define DMA_HRS_HRS8_MASK 0x100u 04174 #define DMA_HRS_HRS8_SHIFT 8 04175 #define DMA_HRS_HRS9_MASK 0x200u 04176 #define DMA_HRS_HRS9_SHIFT 9 04177 #define DMA_HRS_HRS10_MASK 0x400u 04178 #define DMA_HRS_HRS10_SHIFT 10 04179 #define DMA_HRS_HRS11_MASK 0x800u 04180 #define DMA_HRS_HRS11_SHIFT 11 04181 #define DMA_HRS_HRS12_MASK 0x1000u 04182 #define DMA_HRS_HRS12_SHIFT 12 04183 #define DMA_HRS_HRS13_MASK 0x2000u 04184 #define DMA_HRS_HRS13_SHIFT 13 04185 #define DMA_HRS_HRS14_MASK 0x4000u 04186 #define DMA_HRS_HRS14_SHIFT 14 04187 #define DMA_HRS_HRS15_MASK 0x8000u 04188 #define DMA_HRS_HRS15_SHIFT 15 04189 /* DCHPRI3 Bit Fields */ 04190 #define DMA_DCHPRI3_CHPRI_MASK 0xFu 04191 #define DMA_DCHPRI3_CHPRI_SHIFT 0 04192 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK) 04193 #define DMA_DCHPRI3_DPA_MASK 0x40u 04194 #define DMA_DCHPRI3_DPA_SHIFT 6 04195 #define DMA_DCHPRI3_ECP_MASK 0x80u 04196 #define DMA_DCHPRI3_ECP_SHIFT 7 04197 /* DCHPRI2 Bit Fields */ 04198 #define DMA_DCHPRI2_CHPRI_MASK 0xFu 04199 #define DMA_DCHPRI2_CHPRI_SHIFT 0 04200 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK) 04201 #define DMA_DCHPRI2_DPA_MASK 0x40u 04202 #define DMA_DCHPRI2_DPA_SHIFT 6 04203 #define DMA_DCHPRI2_ECP_MASK 0x80u 04204 #define DMA_DCHPRI2_ECP_SHIFT 7 04205 /* DCHPRI1 Bit Fields */ 04206 #define DMA_DCHPRI1_CHPRI_MASK 0xFu 04207 #define DMA_DCHPRI1_CHPRI_SHIFT 0 04208 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK) 04209 #define DMA_DCHPRI1_DPA_MASK 0x40u 04210 #define DMA_DCHPRI1_DPA_SHIFT 6 04211 #define DMA_DCHPRI1_ECP_MASK 0x80u 04212 #define DMA_DCHPRI1_ECP_SHIFT 7 04213 /* DCHPRI0 Bit Fields */ 04214 #define DMA_DCHPRI0_CHPRI_MASK 0xFu 04215 #define DMA_DCHPRI0_CHPRI_SHIFT 0 04216 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK) 04217 #define DMA_DCHPRI0_DPA_MASK 0x40u 04218 #define DMA_DCHPRI0_DPA_SHIFT 6 04219 #define DMA_DCHPRI0_ECP_MASK 0x80u 04220 #define DMA_DCHPRI0_ECP_SHIFT 7 04221 /* DCHPRI7 Bit Fields */ 04222 #define DMA_DCHPRI7_CHPRI_MASK 0xFu 04223 #define DMA_DCHPRI7_CHPRI_SHIFT 0 04224 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK) 04225 #define DMA_DCHPRI7_DPA_MASK 0x40u 04226 #define DMA_DCHPRI7_DPA_SHIFT 6 04227 #define DMA_DCHPRI7_ECP_MASK 0x80u 04228 #define DMA_DCHPRI7_ECP_SHIFT 7 04229 /* DCHPRI6 Bit Fields */ 04230 #define DMA_DCHPRI6_CHPRI_MASK 0xFu 04231 #define DMA_DCHPRI6_CHPRI_SHIFT 0 04232 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK) 04233 #define DMA_DCHPRI6_DPA_MASK 0x40u 04234 #define DMA_DCHPRI6_DPA_SHIFT 6 04235 #define DMA_DCHPRI6_ECP_MASK 0x80u 04236 #define DMA_DCHPRI6_ECP_SHIFT 7 04237 /* DCHPRI5 Bit Fields */ 04238 #define DMA_DCHPRI5_CHPRI_MASK 0xFu 04239 #define DMA_DCHPRI5_CHPRI_SHIFT 0 04240 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK) 04241 #define DMA_DCHPRI5_DPA_MASK 0x40u 04242 #define DMA_DCHPRI5_DPA_SHIFT 6 04243 #define DMA_DCHPRI5_ECP_MASK 0x80u 04244 #define DMA_DCHPRI5_ECP_SHIFT 7 04245 /* DCHPRI4 Bit Fields */ 04246 #define DMA_DCHPRI4_CHPRI_MASK 0xFu 04247 #define DMA_DCHPRI4_CHPRI_SHIFT 0 04248 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK) 04249 #define DMA_DCHPRI4_DPA_MASK 0x40u 04250 #define DMA_DCHPRI4_DPA_SHIFT 6 04251 #define DMA_DCHPRI4_ECP_MASK 0x80u 04252 #define DMA_DCHPRI4_ECP_SHIFT 7 04253 /* DCHPRI11 Bit Fields */ 04254 #define DMA_DCHPRI11_CHPRI_MASK 0xFu 04255 #define DMA_DCHPRI11_CHPRI_SHIFT 0 04256 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK) 04257 #define DMA_DCHPRI11_DPA_MASK 0x40u 04258 #define DMA_DCHPRI11_DPA_SHIFT 6 04259 #define DMA_DCHPRI11_ECP_MASK 0x80u 04260 #define DMA_DCHPRI11_ECP_SHIFT 7 04261 /* DCHPRI10 Bit Fields */ 04262 #define DMA_DCHPRI10_CHPRI_MASK 0xFu 04263 #define DMA_DCHPRI10_CHPRI_SHIFT 0 04264 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK) 04265 #define DMA_DCHPRI10_DPA_MASK 0x40u 04266 #define DMA_DCHPRI10_DPA_SHIFT 6 04267 #define DMA_DCHPRI10_ECP_MASK 0x80u 04268 #define DMA_DCHPRI10_ECP_SHIFT 7 04269 /* DCHPRI9 Bit Fields */ 04270 #define DMA_DCHPRI9_CHPRI_MASK 0xFu 04271 #define DMA_DCHPRI9_CHPRI_SHIFT 0 04272 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK) 04273 #define DMA_DCHPRI9_DPA_MASK 0x40u 04274 #define DMA_DCHPRI9_DPA_SHIFT 6 04275 #define DMA_DCHPRI9_ECP_MASK 0x80u 04276 #define DMA_DCHPRI9_ECP_SHIFT 7 04277 /* DCHPRI8 Bit Fields */ 04278 #define DMA_DCHPRI8_CHPRI_MASK 0xFu 04279 #define DMA_DCHPRI8_CHPRI_SHIFT 0 04280 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK) 04281 #define DMA_DCHPRI8_DPA_MASK 0x40u 04282 #define DMA_DCHPRI8_DPA_SHIFT 6 04283 #define DMA_DCHPRI8_ECP_MASK 0x80u 04284 #define DMA_DCHPRI8_ECP_SHIFT 7 04285 /* DCHPRI15 Bit Fields */ 04286 #define DMA_DCHPRI15_CHPRI_MASK 0xFu 04287 #define DMA_DCHPRI15_CHPRI_SHIFT 0 04288 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK) 04289 #define DMA_DCHPRI15_DPA_MASK 0x40u 04290 #define DMA_DCHPRI15_DPA_SHIFT 6 04291 #define DMA_DCHPRI15_ECP_MASK 0x80u 04292 #define DMA_DCHPRI15_ECP_SHIFT 7 04293 /* DCHPRI14 Bit Fields */ 04294 #define DMA_DCHPRI14_CHPRI_MASK 0xFu 04295 #define DMA_DCHPRI14_CHPRI_SHIFT 0 04296 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK) 04297 #define DMA_DCHPRI14_DPA_MASK 0x40u 04298 #define DMA_DCHPRI14_DPA_SHIFT 6 04299 #define DMA_DCHPRI14_ECP_MASK 0x80u 04300 #define DMA_DCHPRI14_ECP_SHIFT 7 04301 /* DCHPRI13 Bit Fields */ 04302 #define DMA_DCHPRI13_CHPRI_MASK 0xFu 04303 #define DMA_DCHPRI13_CHPRI_SHIFT 0 04304 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK) 04305 #define DMA_DCHPRI13_DPA_MASK 0x40u 04306 #define DMA_DCHPRI13_DPA_SHIFT 6 04307 #define DMA_DCHPRI13_ECP_MASK 0x80u 04308 #define DMA_DCHPRI13_ECP_SHIFT 7 04309 /* DCHPRI12 Bit Fields */ 04310 #define DMA_DCHPRI12_CHPRI_MASK 0xFu 04311 #define DMA_DCHPRI12_CHPRI_SHIFT 0 04312 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK) 04313 #define DMA_DCHPRI12_DPA_MASK 0x40u 04314 #define DMA_DCHPRI12_DPA_SHIFT 6 04315 #define DMA_DCHPRI12_ECP_MASK 0x80u 04316 #define DMA_DCHPRI12_ECP_SHIFT 7 04317 /* SADDR Bit Fields */ 04318 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu 04319 #define DMA_SADDR_SADDR_SHIFT 0 04320 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK) 04321 /* SOFF Bit Fields */ 04322 #define DMA_SOFF_SOFF_MASK 0xFFFFu 04323 #define DMA_SOFF_SOFF_SHIFT 0 04324 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK) 04325 /* ATTR Bit Fields */ 04326 #define DMA_ATTR_DSIZE_MASK 0x7u 04327 #define DMA_ATTR_DSIZE_SHIFT 0 04328 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK) 04329 #define DMA_ATTR_DMOD_MASK 0xF8u 04330 #define DMA_ATTR_DMOD_SHIFT 3 04331 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK) 04332 #define DMA_ATTR_SSIZE_MASK 0x700u 04333 #define DMA_ATTR_SSIZE_SHIFT 8 04334 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK) 04335 #define DMA_ATTR_SMOD_MASK 0xF800u 04336 #define DMA_ATTR_SMOD_SHIFT 11 04337 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK) 04338 /* NBYTES_MLNO Bit Fields */ 04339 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu 04340 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0 04341 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK) 04342 /* NBYTES_MLOFFNO Bit Fields */ 04343 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu 04344 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0 04345 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK) 04346 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u 04347 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30 04348 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u 04349 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31 04350 /* NBYTES_MLOFFYES Bit Fields */ 04351 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu 04352 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0 04353 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK) 04354 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u 04355 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10 04356 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK) 04357 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u 04358 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30 04359 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u 04360 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31 04361 /* SLAST Bit Fields */ 04362 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu 04363 #define DMA_SLAST_SLAST_SHIFT 0 04364 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK) 04365 /* DADDR Bit Fields */ 04366 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu 04367 #define DMA_DADDR_DADDR_SHIFT 0 04368 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK) 04369 /* DOFF Bit Fields */ 04370 #define DMA_DOFF_DOFF_MASK 0xFFFFu 04371 #define DMA_DOFF_DOFF_SHIFT 0 04372 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK) 04373 /* CITER_ELINKNO Bit Fields */ 04374 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu 04375 #define DMA_CITER_ELINKNO_CITER_SHIFT 0 04376 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK) 04377 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u 04378 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15 04379 /* CITER_ELINKYES Bit Fields */ 04380 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu 04381 #define DMA_CITER_ELINKYES_CITER_SHIFT 0 04382 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK) 04383 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u 04384 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9 04385 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK) 04386 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u 04387 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15 04388 /* DLAST_SGA Bit Fields */ 04389 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu 04390 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0 04391 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK) 04392 /* CSR Bit Fields */ 04393 #define DMA_CSR_START_MASK 0x1u 04394 #define DMA_CSR_START_SHIFT 0 04395 #define DMA_CSR_INTMAJOR_MASK 0x2u 04396 #define DMA_CSR_INTMAJOR_SHIFT 1 04397 #define DMA_CSR_INTHALF_MASK 0x4u 04398 #define DMA_CSR_INTHALF_SHIFT 2 04399 #define DMA_CSR_DREQ_MASK 0x8u 04400 #define DMA_CSR_DREQ_SHIFT 3 04401 #define DMA_CSR_ESG_MASK 0x10u 04402 #define DMA_CSR_ESG_SHIFT 4 04403 #define DMA_CSR_MAJORELINK_MASK 0x20u 04404 #define DMA_CSR_MAJORELINK_SHIFT 5 04405 #define DMA_CSR_ACTIVE_MASK 0x40u 04406 #define DMA_CSR_ACTIVE_SHIFT 6 04407 #define DMA_CSR_DONE_MASK 0x80u 04408 #define DMA_CSR_DONE_SHIFT 7 04409 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u 04410 #define DMA_CSR_MAJORLINKCH_SHIFT 8 04411 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK) 04412 #define DMA_CSR_BWC_MASK 0xC000u 04413 #define DMA_CSR_BWC_SHIFT 14 04414 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK) 04415 /* BITER_ELINKNO Bit Fields */ 04416 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu 04417 #define DMA_BITER_ELINKNO_BITER_SHIFT 0 04418 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK) 04419 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u 04420 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15 04421 /* BITER_ELINKYES Bit Fields */ 04422 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu 04423 #define DMA_BITER_ELINKYES_BITER_SHIFT 0 04424 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK) 04425 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u 04426 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9 04427 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK) 04428 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u 04429 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15 04430 04431 /*! 04432 * @} 04433 */ /* end of group DMA_Register_Masks */ 04434 04435 04436 /* DMA - Peripheral instance base addresses */ 04437 /** Peripheral DMA base address */ 04438 #define DMA_BASE (0x40008000u) 04439 /** Peripheral DMA base pointer */ 04440 #define DMA0 ((DMA_Type *)DMA_BASE) 04441 #define DMA_BASE_PTR (DMA0) 04442 /** Array initializer of DMA peripheral base addresses */ 04443 #define DMA_BASE_ADDRS { DMA_BASE } 04444 /** Array initializer of DMA peripheral base pointers */ 04445 #define DMA_BASE_PTRS { DMA0 } 04446 /** Interrupt vectors for the DMA peripheral type */ 04447 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } 04448 #define DMA_ERROR_IRQS { DMA_Error_IRQn } 04449 04450 /* ---------------------------------------------------------------------------- 04451 -- DMA - Register accessor macros 04452 ---------------------------------------------------------------------------- */ 04453 04454 /*! 04455 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros 04456 * @{ 04457 */ 04458 04459 04460 /* DMA - Register instance definitions */ 04461 /* DMA */ 04462 #define DMA_CR DMA_CR_REG(DMA0) 04463 #define DMA_ES DMA_ES_REG(DMA0) 04464 #define DMA_ERQ DMA_ERQ_REG(DMA0) 04465 #define DMA_EEI DMA_EEI_REG(DMA0) 04466 #define DMA_CEEI DMA_CEEI_REG(DMA0) 04467 #define DMA_SEEI DMA_SEEI_REG(DMA0) 04468 #define DMA_CERQ DMA_CERQ_REG(DMA0) 04469 #define DMA_SERQ DMA_SERQ_REG(DMA0) 04470 #define DMA_CDNE DMA_CDNE_REG(DMA0) 04471 #define DMA_SSRT DMA_SSRT_REG(DMA0) 04472 #define DMA_CERR DMA_CERR_REG(DMA0) 04473 #define DMA_CINT DMA_CINT_REG(DMA0) 04474 #define DMA_INT DMA_INT_REG(DMA0) 04475 #define DMA_ERR DMA_ERR_REG(DMA0) 04476 #define DMA_HRS DMA_HRS_REG(DMA0) 04477 #define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0) 04478 #define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0) 04479 #define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0) 04480 #define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0) 04481 #define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0) 04482 #define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0) 04483 #define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0) 04484 #define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0) 04485 #define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0) 04486 #define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0) 04487 #define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0) 04488 #define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0) 04489 #define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0) 04490 #define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0) 04491 #define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0) 04492 #define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0) 04493 #define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0) 04494 #define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0) 04495 #define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0) 04496 #define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0) 04497 #define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0) 04498 #define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0) 04499 #define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0) 04500 #define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0) 04501 #define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0) 04502 #define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0) 04503 #define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0) 04504 #define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0) 04505 #define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0) 04506 #define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0) 04507 #define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0) 04508 #define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1) 04509 #define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1) 04510 #define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1) 04511 #define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1) 04512 #define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1) 04513 #define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1) 04514 #define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1) 04515 #define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1) 04516 #define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1) 04517 #define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1) 04518 #define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1) 04519 #define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1) 04520 #define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1) 04521 #define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1) 04522 #define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1) 04523 #define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2) 04524 #define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2) 04525 #define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2) 04526 #define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2) 04527 #define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2) 04528 #define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2) 04529 #define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2) 04530 #define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2) 04531 #define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2) 04532 #define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2) 04533 #define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2) 04534 #define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2) 04535 #define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2) 04536 #define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2) 04537 #define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2) 04538 #define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3) 04539 #define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3) 04540 #define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3) 04541 #define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3) 04542 #define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3) 04543 #define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3) 04544 #define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3) 04545 #define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3) 04546 #define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3) 04547 #define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3) 04548 #define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3) 04549 #define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3) 04550 #define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3) 04551 #define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3) 04552 #define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3) 04553 #define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4) 04554 #define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4) 04555 #define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4) 04556 #define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4) 04557 #define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4) 04558 #define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4) 04559 #define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4) 04560 #define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4) 04561 #define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4) 04562 #define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4) 04563 #define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4) 04564 #define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4) 04565 #define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4) 04566 #define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4) 04567 #define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4) 04568 #define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5) 04569 #define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5) 04570 #define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5) 04571 #define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5) 04572 #define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5) 04573 #define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5) 04574 #define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5) 04575 #define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5) 04576 #define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5) 04577 #define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5) 04578 #define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5) 04579 #define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5) 04580 #define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5) 04581 #define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5) 04582 #define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5) 04583 #define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6) 04584 #define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6) 04585 #define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6) 04586 #define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6) 04587 #define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6) 04588 #define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6) 04589 #define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6) 04590 #define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6) 04591 #define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6) 04592 #define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6) 04593 #define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6) 04594 #define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6) 04595 #define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6) 04596 #define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6) 04597 #define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6) 04598 #define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7) 04599 #define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7) 04600 #define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7) 04601 #define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7) 04602 #define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7) 04603 #define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7) 04604 #define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7) 04605 #define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7) 04606 #define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7) 04607 #define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7) 04608 #define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7) 04609 #define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7) 04610 #define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7) 04611 #define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7) 04612 #define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7) 04613 #define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8) 04614 #define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8) 04615 #define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8) 04616 #define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8) 04617 #define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8) 04618 #define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8) 04619 #define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8) 04620 #define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8) 04621 #define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8) 04622 #define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8) 04623 #define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8) 04624 #define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8) 04625 #define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8) 04626 #define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8) 04627 #define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8) 04628 #define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9) 04629 #define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9) 04630 #define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9) 04631 #define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9) 04632 #define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9) 04633 #define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9) 04634 #define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9) 04635 #define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9) 04636 #define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9) 04637 #define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9) 04638 #define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9) 04639 #define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9) 04640 #define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9) 04641 #define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9) 04642 #define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9) 04643 #define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10) 04644 #define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10) 04645 #define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10) 04646 #define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10) 04647 #define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10) 04648 #define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10) 04649 #define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10) 04650 #define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10) 04651 #define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10) 04652 #define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10) 04653 #define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10) 04654 #define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10) 04655 #define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10) 04656 #define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10) 04657 #define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10) 04658 #define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11) 04659 #define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11) 04660 #define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11) 04661 #define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11) 04662 #define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11) 04663 #define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11) 04664 #define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11) 04665 #define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11) 04666 #define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11) 04667 #define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11) 04668 #define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11) 04669 #define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11) 04670 #define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11) 04671 #define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11) 04672 #define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11) 04673 #define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12) 04674 #define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12) 04675 #define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12) 04676 #define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12) 04677 #define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12) 04678 #define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12) 04679 #define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12) 04680 #define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12) 04681 #define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12) 04682 #define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12) 04683 #define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12) 04684 #define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12) 04685 #define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12) 04686 #define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12) 04687 #define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12) 04688 #define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13) 04689 #define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13) 04690 #define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13) 04691 #define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13) 04692 #define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13) 04693 #define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13) 04694 #define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13) 04695 #define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13) 04696 #define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13) 04697 #define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13) 04698 #define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13) 04699 #define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13) 04700 #define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13) 04701 #define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13) 04702 #define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13) 04703 #define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14) 04704 #define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14) 04705 #define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14) 04706 #define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14) 04707 #define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14) 04708 #define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14) 04709 #define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14) 04710 #define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14) 04711 #define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14) 04712 #define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14) 04713 #define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14) 04714 #define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14) 04715 #define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14) 04716 #define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14) 04717 #define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14) 04718 #define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15) 04719 #define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15) 04720 #define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15) 04721 #define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15) 04722 #define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15) 04723 #define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15) 04724 #define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15) 04725 #define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15) 04726 #define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15) 04727 #define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15) 04728 #define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15) 04729 #define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15) 04730 #define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15) 04731 #define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15) 04732 #define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15) 04733 04734 /* DMA - Register array accessors */ 04735 #define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index) 04736 #define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index) 04737 #define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index) 04738 #define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index) 04739 #define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index) 04740 #define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index) 04741 #define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index) 04742 #define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index) 04743 #define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index) 04744 #define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index) 04745 #define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index) 04746 #define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index) 04747 #define DMA_CSR(index) DMA_CSR_REG(DMA0,index) 04748 #define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index) 04749 #define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index) 04750 04751 /*! 04752 * @} 04753 */ /* end of group DMA_Register_Accessor_Macros */ 04754 04755 04756 /*! 04757 * @} 04758 */ /* end of group DMA_Peripheral_Access_Layer */ 04759 04760 04761 /* ---------------------------------------------------------------------------- 04762 -- DMAMUX Peripheral Access Layer 04763 ---------------------------------------------------------------------------- */ 04764 04765 /*! 04766 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer 04767 * @{ 04768 */ 04769 04770 /** DMAMUX - Register Layout Typedef */ 04771 typedef struct { 04772 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ 04773 } DMAMUX_Type, *DMAMUX_MemMapPtr; 04774 04775 /* ---------------------------------------------------------------------------- 04776 -- DMAMUX - Register accessor macros 04777 ---------------------------------------------------------------------------- */ 04778 04779 /*! 04780 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros 04781 * @{ 04782 */ 04783 04784 04785 /* DMAMUX - Register accessors */ 04786 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index]) 04787 04788 /*! 04789 * @} 04790 */ /* end of group DMAMUX_Register_Accessor_Macros */ 04791 04792 04793 /* ---------------------------------------------------------------------------- 04794 -- DMAMUX Register Masks 04795 ---------------------------------------------------------------------------- */ 04796 04797 /*! 04798 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks 04799 * @{ 04800 */ 04801 04802 /* CHCFG Bit Fields */ 04803 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu 04804 #define DMAMUX_CHCFG_SOURCE_SHIFT 0 04805 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK) 04806 #define DMAMUX_CHCFG_TRIG_MASK 0x40u 04807 #define DMAMUX_CHCFG_TRIG_SHIFT 6 04808 #define DMAMUX_CHCFG_ENBL_MASK 0x80u 04809 #define DMAMUX_CHCFG_ENBL_SHIFT 7 04810 04811 /*! 04812 * @} 04813 */ /* end of group DMAMUX_Register_Masks */ 04814 04815 04816 /* DMAMUX - Peripheral instance base addresses */ 04817 /** Peripheral DMAMUX base address */ 04818 #define DMAMUX_BASE (0x40021000u) 04819 /** Peripheral DMAMUX base pointer */ 04820 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) 04821 #define DMAMUX_BASE_PTR (DMAMUX) 04822 /** Array initializer of DMAMUX peripheral base addresses */ 04823 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE } 04824 /** Array initializer of DMAMUX peripheral base pointers */ 04825 #define DMAMUX_BASE_PTRS { DMAMUX } 04826 04827 /* ---------------------------------------------------------------------------- 04828 -- DMAMUX - Register accessor macros 04829 ---------------------------------------------------------------------------- */ 04830 04831 /*! 04832 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros 04833 * @{ 04834 */ 04835 04836 04837 /* DMAMUX - Register instance definitions */ 04838 /* DMAMUX */ 04839 #define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0) 04840 #define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1) 04841 #define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2) 04842 #define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3) 04843 #define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4) 04844 #define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5) 04845 #define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6) 04846 #define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7) 04847 #define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8) 04848 #define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9) 04849 #define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10) 04850 #define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11) 04851 #define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12) 04852 #define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13) 04853 #define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14) 04854 #define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15) 04855 04856 /* DMAMUX - Register array accessors */ 04857 #define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index) 04858 04859 /*! 04860 * @} 04861 */ /* end of group DMAMUX_Register_Accessor_Macros */ 04862 04863 04864 /*! 04865 * @} 04866 */ /* end of group DMAMUX_Peripheral_Access_Layer */ 04867 04868 04869 /* ---------------------------------------------------------------------------- 04870 -- ENET Peripheral Access Layer 04871 ---------------------------------------------------------------------------- */ 04872 04873 /*! 04874 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer 04875 * @{ 04876 */ 04877 04878 /** ENET - Register Layout Typedef */ 04879 typedef struct { 04880 uint8_t RESERVED_0[4]; 04881 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ 04882 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ 04883 uint8_t RESERVED_1[4]; 04884 __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ 04885 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ 04886 uint8_t RESERVED_2[12]; 04887 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ 04888 uint8_t RESERVED_3[24]; 04889 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ 04890 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ 04891 uint8_t RESERVED_4[28]; 04892 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ 04893 uint8_t RESERVED_5[28]; 04894 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ 04895 uint8_t RESERVED_6[60]; 04896 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ 04897 uint8_t RESERVED_7[28]; 04898 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ 04899 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ 04900 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ 04901 uint8_t RESERVED_8[40]; 04902 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ 04903 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ 04904 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ 04905 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ 04906 uint8_t RESERVED_9[28]; 04907 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ 04908 uint8_t RESERVED_10[56]; 04909 __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */ 04910 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */ 04911 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ 04912 uint8_t RESERVED_11[4]; 04913 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ 04914 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ 04915 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ 04916 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ 04917 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ 04918 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ 04919 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ 04920 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ 04921 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ 04922 uint8_t RESERVED_12[12]; 04923 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ 04924 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ 04925 uint8_t RESERVED_13[60]; 04926 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ 04927 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ 04928 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ 04929 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ 04930 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ 04931 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ 04932 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ 04933 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ 04934 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ 04935 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ 04936 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ 04937 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ 04938 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ 04939 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ 04940 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ 04941 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ 04942 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ 04943 uint8_t RESERVED_14[4]; 04944 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ 04945 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ 04946 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ 04947 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ 04948 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ 04949 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ 04950 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ 04951 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ 04952 uint8_t RESERVED_15[4]; 04953 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ 04954 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ 04955 uint8_t RESERVED_16[12]; 04956 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ 04957 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ 04958 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ 04959 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ 04960 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ 04961 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ 04962 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ 04963 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ 04964 uint8_t RESERVED_17[4]; 04965 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ 04966 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ 04967 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ 04968 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ 04969 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ 04970 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ 04971 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ 04972 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ 04973 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ 04974 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ 04975 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ 04976 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ 04977 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ 04978 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ 04979 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ 04980 uint8_t RESERVED_18[284]; 04981 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ 04982 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ 04983 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ 04984 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ 04985 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ 04986 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ 04987 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ 04988 uint8_t RESERVED_19[488]; 04989 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ 04990 struct { /* offset: 0x608, array step: 0x8 */ 04991 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ 04992 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ 04993 } CHANNEL[4]; 04994 } ENET_Type, *ENET_MemMapPtr; 04995 04996 /* ---------------------------------------------------------------------------- 04997 -- ENET - Register accessor macros 04998 ---------------------------------------------------------------------------- */ 04999 05000 /*! 05001 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros 05002 * @{ 05003 */ 05004 05005 05006 /* ENET - Register accessors */ 05007 #define ENET_EIR_REG(base) ((base)->EIR) 05008 #define ENET_EIMR_REG(base) ((base)->EIMR) 05009 #define ENET_RDAR_REG(base) ((base)->RDAR) 05010 #define ENET_TDAR_REG(base) ((base)->TDAR) 05011 #define ENET_ECR_REG(base) ((base)->ECR) 05012 #define ENET_MMFR_REG(base) ((base)->MMFR) 05013 #define ENET_MSCR_REG(base) ((base)->MSCR) 05014 #define ENET_MIBC_REG(base) ((base)->MIBC) 05015 #define ENET_RCR_REG(base) ((base)->RCR) 05016 #define ENET_TCR_REG(base) ((base)->TCR) 05017 #define ENET_PALR_REG(base) ((base)->PALR) 05018 #define ENET_PAUR_REG(base) ((base)->PAUR) 05019 #define ENET_OPD_REG(base) ((base)->OPD) 05020 #define ENET_IAUR_REG(base) ((base)->IAUR) 05021 #define ENET_IALR_REG(base) ((base)->IALR) 05022 #define ENET_GAUR_REG(base) ((base)->GAUR) 05023 #define ENET_GALR_REG(base) ((base)->GALR) 05024 #define ENET_TFWR_REG(base) ((base)->TFWR) 05025 #define ENET_RDSR_REG(base) ((base)->RDSR) 05026 #define ENET_TDSR_REG(base) ((base)->TDSR) 05027 #define ENET_MRBR_REG(base) ((base)->MRBR) 05028 #define ENET_RSFL_REG(base) ((base)->RSFL) 05029 #define ENET_RSEM_REG(base) ((base)->RSEM) 05030 #define ENET_RAEM_REG(base) ((base)->RAEM) 05031 #define ENET_RAFL_REG(base) ((base)->RAFL) 05032 #define ENET_TSEM_REG(base) ((base)->TSEM) 05033 #define ENET_TAEM_REG(base) ((base)->TAEM) 05034 #define ENET_TAFL_REG(base) ((base)->TAFL) 05035 #define ENET_TIPG_REG(base) ((base)->TIPG) 05036 #define ENET_FTRL_REG(base) ((base)->FTRL) 05037 #define ENET_TACC_REG(base) ((base)->TACC) 05038 #define ENET_RACC_REG(base) ((base)->RACC) 05039 #define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS) 05040 #define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT) 05041 #define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT) 05042 #define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN) 05043 #define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE) 05044 #define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE) 05045 #define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG) 05046 #define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB) 05047 #define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL) 05048 #define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64) 05049 #define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127) 05050 #define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255) 05051 #define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511) 05052 #define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023) 05053 #define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047) 05054 #define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048) 05055 #define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS) 05056 #define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK) 05057 #define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL) 05058 #define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL) 05059 #define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF) 05060 #define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL) 05061 #define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL) 05062 #define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR) 05063 #define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR) 05064 #define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC) 05065 #define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK) 05066 #define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS) 05067 #define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT) 05068 #define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT) 05069 #define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN) 05070 #define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE) 05071 #define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE) 05072 #define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG) 05073 #define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB) 05074 #define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64) 05075 #define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127) 05076 #define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255) 05077 #define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511) 05078 #define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023) 05079 #define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047) 05080 #define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048) 05081 #define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS) 05082 #define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP) 05083 #define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK) 05084 #define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC) 05085 #define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN) 05086 #define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR) 05087 #define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC) 05088 #define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK) 05089 #define ENET_ATCR_REG(base) ((base)->ATCR) 05090 #define ENET_ATVR_REG(base) ((base)->ATVR) 05091 #define ENET_ATOFF_REG(base) ((base)->ATOFF) 05092 #define ENET_ATPER_REG(base) ((base)->ATPER) 05093 #define ENET_ATCOR_REG(base) ((base)->ATCOR) 05094 #define ENET_ATINC_REG(base) ((base)->ATINC) 05095 #define ENET_ATSTMP_REG(base) ((base)->ATSTMP) 05096 #define ENET_TGSR_REG(base) ((base)->TGSR) 05097 #define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR) 05098 #define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR) 05099 05100 /*! 05101 * @} 05102 */ /* end of group ENET_Register_Accessor_Macros */ 05103 05104 05105 /* ---------------------------------------------------------------------------- 05106 -- ENET Register Masks 05107 ---------------------------------------------------------------------------- */ 05108 05109 /*! 05110 * @addtogroup ENET_Register_Masks ENET Register Masks 05111 * @{ 05112 */ 05113 05114 /* EIR Bit Fields */ 05115 #define ENET_EIR_TS_TIMER_MASK 0x8000u 05116 #define ENET_EIR_TS_TIMER_SHIFT 15 05117 #define ENET_EIR_TS_AVAIL_MASK 0x10000u 05118 #define ENET_EIR_TS_AVAIL_SHIFT 16 05119 #define ENET_EIR_WAKEUP_MASK 0x20000u 05120 #define ENET_EIR_WAKEUP_SHIFT 17 05121 #define ENET_EIR_PLR_MASK 0x40000u 05122 #define ENET_EIR_PLR_SHIFT 18 05123 #define ENET_EIR_UN_MASK 0x80000u 05124 #define ENET_EIR_UN_SHIFT 19 05125 #define ENET_EIR_RL_MASK 0x100000u 05126 #define ENET_EIR_RL_SHIFT 20 05127 #define ENET_EIR_LC_MASK 0x200000u 05128 #define ENET_EIR_LC_SHIFT 21 05129 #define ENET_EIR_EBERR_MASK 0x400000u 05130 #define ENET_EIR_EBERR_SHIFT 22 05131 #define ENET_EIR_MII_MASK 0x800000u 05132 #define ENET_EIR_MII_SHIFT 23 05133 #define ENET_EIR_RXB_MASK 0x1000000u 05134 #define ENET_EIR_RXB_SHIFT 24 05135 #define ENET_EIR_RXF_MASK 0x2000000u 05136 #define ENET_EIR_RXF_SHIFT 25 05137 #define ENET_EIR_TXB_MASK 0x4000000u 05138 #define ENET_EIR_TXB_SHIFT 26 05139 #define ENET_EIR_TXF_MASK 0x8000000u 05140 #define ENET_EIR_TXF_SHIFT 27 05141 #define ENET_EIR_GRA_MASK 0x10000000u 05142 #define ENET_EIR_GRA_SHIFT 28 05143 #define ENET_EIR_BABT_MASK 0x20000000u 05144 #define ENET_EIR_BABT_SHIFT 29 05145 #define ENET_EIR_BABR_MASK 0x40000000u 05146 #define ENET_EIR_BABR_SHIFT 30 05147 /* EIMR Bit Fields */ 05148 #define ENET_EIMR_TS_TIMER_MASK 0x8000u 05149 #define ENET_EIMR_TS_TIMER_SHIFT 15 05150 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u 05151 #define ENET_EIMR_TS_AVAIL_SHIFT 16 05152 #define ENET_EIMR_WAKEUP_MASK 0x20000u 05153 #define ENET_EIMR_WAKEUP_SHIFT 17 05154 #define ENET_EIMR_PLR_MASK 0x40000u 05155 #define ENET_EIMR_PLR_SHIFT 18 05156 #define ENET_EIMR_UN_MASK 0x80000u 05157 #define ENET_EIMR_UN_SHIFT 19 05158 #define ENET_EIMR_RL_MASK 0x100000u 05159 #define ENET_EIMR_RL_SHIFT 20 05160 #define ENET_EIMR_LC_MASK 0x200000u 05161 #define ENET_EIMR_LC_SHIFT 21 05162 #define ENET_EIMR_EBERR_MASK 0x400000u 05163 #define ENET_EIMR_EBERR_SHIFT 22 05164 #define ENET_EIMR_MII_MASK 0x800000u 05165 #define ENET_EIMR_MII_SHIFT 23 05166 #define ENET_EIMR_RXB_MASK 0x1000000u 05167 #define ENET_EIMR_RXB_SHIFT 24 05168 #define ENET_EIMR_RXF_MASK 0x2000000u 05169 #define ENET_EIMR_RXF_SHIFT 25 05170 #define ENET_EIMR_TXB_MASK 0x4000000u 05171 #define ENET_EIMR_TXB_SHIFT 26 05172 #define ENET_EIMR_TXF_MASK 0x8000000u 05173 #define ENET_EIMR_TXF_SHIFT 27 05174 #define ENET_EIMR_GRA_MASK 0x10000000u 05175 #define ENET_EIMR_GRA_SHIFT 28 05176 #define ENET_EIMR_BABT_MASK 0x20000000u 05177 #define ENET_EIMR_BABT_SHIFT 29 05178 #define ENET_EIMR_BABR_MASK 0x40000000u 05179 #define ENET_EIMR_BABR_SHIFT 30 05180 /* RDAR Bit Fields */ 05181 #define ENET_RDAR_RDAR_MASK 0x1000000u 05182 #define ENET_RDAR_RDAR_SHIFT 24 05183 /* TDAR Bit Fields */ 05184 #define ENET_TDAR_TDAR_MASK 0x1000000u 05185 #define ENET_TDAR_TDAR_SHIFT 24 05186 /* ECR Bit Fields */ 05187 #define ENET_ECR_RESET_MASK 0x1u 05188 #define ENET_ECR_RESET_SHIFT 0 05189 #define ENET_ECR_ETHEREN_MASK 0x2u 05190 #define ENET_ECR_ETHEREN_SHIFT 1 05191 #define ENET_ECR_MAGICEN_MASK 0x4u 05192 #define ENET_ECR_MAGICEN_SHIFT 2 05193 #define ENET_ECR_SLEEP_MASK 0x8u 05194 #define ENET_ECR_SLEEP_SHIFT 3 05195 #define ENET_ECR_EN1588_MASK 0x10u 05196 #define ENET_ECR_EN1588_SHIFT 4 05197 #define ENET_ECR_DBGEN_MASK 0x40u 05198 #define ENET_ECR_DBGEN_SHIFT 6 05199 #define ENET_ECR_STOPEN_MASK 0x80u 05200 #define ENET_ECR_STOPEN_SHIFT 7 05201 #define ENET_ECR_DBSWP_MASK 0x100u 05202 #define ENET_ECR_DBSWP_SHIFT 8 05203 /* MMFR Bit Fields */ 05204 #define ENET_MMFR_DATA_MASK 0xFFFFu 05205 #define ENET_MMFR_DATA_SHIFT 0 05206 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK) 05207 #define ENET_MMFR_TA_MASK 0x30000u 05208 #define ENET_MMFR_TA_SHIFT 16 05209 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK) 05210 #define ENET_MMFR_RA_MASK 0x7C0000u 05211 #define ENET_MMFR_RA_SHIFT 18 05212 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK) 05213 #define ENET_MMFR_PA_MASK 0xF800000u 05214 #define ENET_MMFR_PA_SHIFT 23 05215 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK) 05216 #define ENET_MMFR_OP_MASK 0x30000000u 05217 #define ENET_MMFR_OP_SHIFT 28 05218 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK) 05219 #define ENET_MMFR_ST_MASK 0xC0000000u 05220 #define ENET_MMFR_ST_SHIFT 30 05221 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK) 05222 /* MSCR Bit Fields */ 05223 #define ENET_MSCR_MII_SPEED_MASK 0x7Eu 05224 #define ENET_MSCR_MII_SPEED_SHIFT 1 05225 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK) 05226 #define ENET_MSCR_DIS_PRE_MASK 0x80u 05227 #define ENET_MSCR_DIS_PRE_SHIFT 7 05228 #define ENET_MSCR_HOLDTIME_MASK 0x700u 05229 #define ENET_MSCR_HOLDTIME_SHIFT 8 05230 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK) 05231 /* MIBC Bit Fields */ 05232 #define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u 05233 #define ENET_MIBC_MIB_CLEAR_SHIFT 29 05234 #define ENET_MIBC_MIB_IDLE_MASK 0x40000000u 05235 #define ENET_MIBC_MIB_IDLE_SHIFT 30 05236 #define ENET_MIBC_MIB_DIS_MASK 0x80000000u 05237 #define ENET_MIBC_MIB_DIS_SHIFT 31 05238 /* RCR Bit Fields */ 05239 #define ENET_RCR_LOOP_MASK 0x1u 05240 #define ENET_RCR_LOOP_SHIFT 0 05241 #define ENET_RCR_DRT_MASK 0x2u 05242 #define ENET_RCR_DRT_SHIFT 1 05243 #define ENET_RCR_MII_MODE_MASK 0x4u 05244 #define ENET_RCR_MII_MODE_SHIFT 2 05245 #define ENET_RCR_PROM_MASK 0x8u 05246 #define ENET_RCR_PROM_SHIFT 3 05247 #define ENET_RCR_BC_REJ_MASK 0x10u 05248 #define ENET_RCR_BC_REJ_SHIFT 4 05249 #define ENET_RCR_FCE_MASK 0x20u 05250 #define ENET_RCR_FCE_SHIFT 5 05251 #define ENET_RCR_RMII_MODE_MASK 0x100u 05252 #define ENET_RCR_RMII_MODE_SHIFT 8 05253 #define ENET_RCR_RMII_10T_MASK 0x200u 05254 #define ENET_RCR_RMII_10T_SHIFT 9 05255 #define ENET_RCR_PADEN_MASK 0x1000u 05256 #define ENET_RCR_PADEN_SHIFT 12 05257 #define ENET_RCR_PAUFWD_MASK 0x2000u 05258 #define ENET_RCR_PAUFWD_SHIFT 13 05259 #define ENET_RCR_CRCFWD_MASK 0x4000u 05260 #define ENET_RCR_CRCFWD_SHIFT 14 05261 #define ENET_RCR_CFEN_MASK 0x8000u 05262 #define ENET_RCR_CFEN_SHIFT 15 05263 #define ENET_RCR_MAX_FL_MASK 0x3FFF0000u 05264 #define ENET_RCR_MAX_FL_SHIFT 16 05265 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK) 05266 #define ENET_RCR_NLC_MASK 0x40000000u 05267 #define ENET_RCR_NLC_SHIFT 30 05268 #define ENET_RCR_GRS_MASK 0x80000000u 05269 #define ENET_RCR_GRS_SHIFT 31 05270 /* TCR Bit Fields */ 05271 #define ENET_TCR_GTS_MASK 0x1u 05272 #define ENET_TCR_GTS_SHIFT 0 05273 #define ENET_TCR_FDEN_MASK 0x4u 05274 #define ENET_TCR_FDEN_SHIFT 2 05275 #define ENET_TCR_TFC_PAUSE_MASK 0x8u 05276 #define ENET_TCR_TFC_PAUSE_SHIFT 3 05277 #define ENET_TCR_RFC_PAUSE_MASK 0x10u 05278 #define ENET_TCR_RFC_PAUSE_SHIFT 4 05279 #define ENET_TCR_ADDSEL_MASK 0xE0u 05280 #define ENET_TCR_ADDSEL_SHIFT 5 05281 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK) 05282 #define ENET_TCR_ADDINS_MASK 0x100u 05283 #define ENET_TCR_ADDINS_SHIFT 8 05284 #define ENET_TCR_CRCFWD_MASK 0x200u 05285 #define ENET_TCR_CRCFWD_SHIFT 9 05286 /* PALR Bit Fields */ 05287 #define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu 05288 #define ENET_PALR_PADDR1_SHIFT 0 05289 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK) 05290 /* PAUR Bit Fields */ 05291 #define ENET_PAUR_TYPE_MASK 0xFFFFu 05292 #define ENET_PAUR_TYPE_SHIFT 0 05293 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK) 05294 #define ENET_PAUR_PADDR2_MASK 0xFFFF0000u 05295 #define ENET_PAUR_PADDR2_SHIFT 16 05296 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK) 05297 /* OPD Bit Fields */ 05298 #define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu 05299 #define ENET_OPD_PAUSE_DUR_SHIFT 0 05300 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK) 05301 #define ENET_OPD_OPCODE_MASK 0xFFFF0000u 05302 #define ENET_OPD_OPCODE_SHIFT 16 05303 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK) 05304 /* IAUR Bit Fields */ 05305 #define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu 05306 #define ENET_IAUR_IADDR1_SHIFT 0 05307 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK) 05308 /* IALR Bit Fields */ 05309 #define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu 05310 #define ENET_IALR_IADDR2_SHIFT 0 05311 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK) 05312 /* GAUR Bit Fields */ 05313 #define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu 05314 #define ENET_GAUR_GADDR1_SHIFT 0 05315 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK) 05316 /* GALR Bit Fields */ 05317 #define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu 05318 #define ENET_GALR_GADDR2_SHIFT 0 05319 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK) 05320 /* TFWR Bit Fields */ 05321 #define ENET_TFWR_TFWR_MASK 0x3Fu 05322 #define ENET_TFWR_TFWR_SHIFT 0 05323 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK) 05324 #define ENET_TFWR_STRFWD_MASK 0x100u 05325 #define ENET_TFWR_STRFWD_SHIFT 8 05326 /* RDSR Bit Fields */ 05327 #define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u 05328 #define ENET_RDSR_R_DES_START_SHIFT 3 05329 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK) 05330 /* TDSR Bit Fields */ 05331 #define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u 05332 #define ENET_TDSR_X_DES_START_SHIFT 3 05333 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK) 05334 /* MRBR Bit Fields */ 05335 #define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u 05336 #define ENET_MRBR_R_BUF_SIZE_SHIFT 4 05337 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK) 05338 /* RSFL Bit Fields */ 05339 #define ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu 05340 #define ENET_RSFL_RX_SECTION_FULL_SHIFT 0 05341 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK) 05342 /* RSEM Bit Fields */ 05343 #define ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu 05344 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0 05345 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK) 05346 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK 0x1F0000u 05347 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT 16 05348 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK) 05349 /* RAEM Bit Fields */ 05350 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu 05351 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0 05352 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK) 05353 /* RAFL Bit Fields */ 05354 #define ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu 05355 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0 05356 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK) 05357 /* TSEM Bit Fields */ 05358 #define ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu 05359 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0 05360 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK) 05361 /* TAEM Bit Fields */ 05362 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu 05363 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0 05364 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK) 05365 /* TAFL Bit Fields */ 05366 #define ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu 05367 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0 05368 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK) 05369 /* TIPG Bit Fields */ 05370 #define ENET_TIPG_IPG_MASK 0x1Fu 05371 #define ENET_TIPG_IPG_SHIFT 0 05372 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK) 05373 /* FTRL Bit Fields */ 05374 #define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu 05375 #define ENET_FTRL_TRUNC_FL_SHIFT 0 05376 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK) 05377 /* TACC Bit Fields */ 05378 #define ENET_TACC_SHIFT16_MASK 0x1u 05379 #define ENET_TACC_SHIFT16_SHIFT 0 05380 #define ENET_TACC_IPCHK_MASK 0x8u 05381 #define ENET_TACC_IPCHK_SHIFT 3 05382 #define ENET_TACC_PROCHK_MASK 0x10u 05383 #define ENET_TACC_PROCHK_SHIFT 4 05384 /* RACC Bit Fields */ 05385 #define ENET_RACC_PADREM_MASK 0x1u 05386 #define ENET_RACC_PADREM_SHIFT 0 05387 #define ENET_RACC_IPDIS_MASK 0x2u 05388 #define ENET_RACC_IPDIS_SHIFT 1 05389 #define ENET_RACC_PRODIS_MASK 0x4u 05390 #define ENET_RACC_PRODIS_SHIFT 2 05391 #define ENET_RACC_LINEDIS_MASK 0x40u 05392 #define ENET_RACC_LINEDIS_SHIFT 6 05393 #define ENET_RACC_SHIFT16_MASK 0x80u 05394 #define ENET_RACC_SHIFT16_SHIFT 7 05395 /* RMON_T_PACKETS Bit Fields */ 05396 #define ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu 05397 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0 05398 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK) 05399 /* RMON_T_BC_PKT Bit Fields */ 05400 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK 0xFFFFu 05401 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT 0 05402 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK) 05403 /* RMON_T_MC_PKT Bit Fields */ 05404 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK 0xFFFFu 05405 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT 0 05406 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK) 05407 /* RMON_T_CRC_ALIGN Bit Fields */ 05408 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK 0xFFFFu 05409 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT 0 05410 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) 05411 /* RMON_T_UNDERSIZE Bit Fields */ 05412 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK 0xFFFFu 05413 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT 0 05414 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) 05415 /* RMON_T_OVERSIZE Bit Fields */ 05416 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK 0xFFFFu 05417 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT 0 05418 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK) 05419 /* RMON_T_FRAG Bit Fields */ 05420 #define ENET_RMON_T_FRAG_TXPKTS_MASK 0xFFFFu 05421 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT 0 05422 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK) 05423 /* RMON_T_JAB Bit Fields */ 05424 #define ENET_RMON_T_JAB_TXPKTS_MASK 0xFFFFu 05425 #define ENET_RMON_T_JAB_TXPKTS_SHIFT 0 05426 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK) 05427 /* RMON_T_COL Bit Fields */ 05428 #define ENET_RMON_T_COL_TXPKTS_MASK 0xFFFFu 05429 #define ENET_RMON_T_COL_TXPKTS_SHIFT 0 05430 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK) 05431 /* RMON_T_P64 Bit Fields */ 05432 #define ENET_RMON_T_P64_TXPKTS_MASK 0xFFFFu 05433 #define ENET_RMON_T_P64_TXPKTS_SHIFT 0 05434 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK) 05435 /* RMON_T_P65TO127 Bit Fields */ 05436 #define ENET_RMON_T_P65TO127_TXPKTS_MASK 0xFFFFu 05437 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT 0 05438 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK) 05439 /* RMON_T_P128TO255 Bit Fields */ 05440 #define ENET_RMON_T_P128TO255_TXPKTS_MASK 0xFFFFu 05441 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT 0 05442 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK) 05443 /* RMON_T_P256TO511 Bit Fields */ 05444 #define ENET_RMON_T_P256TO511_TXPKTS_MASK 0xFFFFu 05445 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT 0 05446 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK) 05447 /* RMON_T_P512TO1023 Bit Fields */ 05448 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK 0xFFFFu 05449 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT 0 05450 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK) 05451 /* RMON_T_P1024TO2047 Bit Fields */ 05452 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK 0xFFFFu 05453 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT 0 05454 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK) 05455 /* RMON_T_P_GTE2048 Bit Fields */ 05456 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK 0xFFFFu 05457 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT 0 05458 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK) 05459 /* RMON_T_OCTETS Bit Fields */ 05460 #define ENET_RMON_T_OCTETS_TXOCTS_MASK 0xFFFFFFFFu 05461 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0 05462 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK) 05463 /* IEEE_T_FRAME_OK Bit Fields */ 05464 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu 05465 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0 05466 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK) 05467 /* IEEE_T_1COL Bit Fields */ 05468 #define ENET_IEEE_T_1COL_COUNT_MASK 0xFFFFu 05469 #define ENET_IEEE_T_1COL_COUNT_SHIFT 0 05470 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK) 05471 /* IEEE_T_MCOL Bit Fields */ 05472 #define ENET_IEEE_T_MCOL_COUNT_MASK 0xFFFFu 05473 #define ENET_IEEE_T_MCOL_COUNT_SHIFT 0 05474 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK) 05475 /* IEEE_T_DEF Bit Fields */ 05476 #define ENET_IEEE_T_DEF_COUNT_MASK 0xFFFFu 05477 #define ENET_IEEE_T_DEF_COUNT_SHIFT 0 05478 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK) 05479 /* IEEE_T_LCOL Bit Fields */ 05480 #define ENET_IEEE_T_LCOL_COUNT_MASK 0xFFFFu 05481 #define ENET_IEEE_T_LCOL_COUNT_SHIFT 0 05482 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK) 05483 /* IEEE_T_EXCOL Bit Fields */ 05484 #define ENET_IEEE_T_EXCOL_COUNT_MASK 0xFFFFu 05485 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT 0 05486 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK) 05487 /* IEEE_T_MACERR Bit Fields */ 05488 #define ENET_IEEE_T_MACERR_COUNT_MASK 0xFFFFu 05489 #define ENET_IEEE_T_MACERR_COUNT_SHIFT 0 05490 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK) 05491 /* IEEE_T_CSERR Bit Fields */ 05492 #define ENET_IEEE_T_CSERR_COUNT_MASK 0xFFFFu 05493 #define ENET_IEEE_T_CSERR_COUNT_SHIFT 0 05494 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK) 05495 /* IEEE_T_FDXFC Bit Fields */ 05496 #define ENET_IEEE_T_FDXFC_COUNT_MASK 0xFFFFu 05497 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT 0 05498 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK) 05499 /* IEEE_T_OCTETS_OK Bit Fields */ 05500 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu 05501 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT 0 05502 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK) 05503 /* RMON_R_PACKETS Bit Fields */ 05504 #define ENET_RMON_R_PACKETS_COUNT_MASK 0xFFFFu 05505 #define ENET_RMON_R_PACKETS_COUNT_SHIFT 0 05506 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK) 05507 /* RMON_R_BC_PKT Bit Fields */ 05508 #define ENET_RMON_R_BC_PKT_COUNT_MASK 0xFFFFu 05509 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT 0 05510 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK) 05511 /* RMON_R_MC_PKT Bit Fields */ 05512 #define ENET_RMON_R_MC_PKT_COUNT_MASK 0xFFFFu 05513 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT 0 05514 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK) 05515 /* RMON_R_CRC_ALIGN Bit Fields */ 05516 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK 0xFFFFu 05517 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT 0 05518 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK) 05519 /* RMON_R_UNDERSIZE Bit Fields */ 05520 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK 0xFFFFu 05521 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT 0 05522 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK) 05523 /* RMON_R_OVERSIZE Bit Fields */ 05524 #define ENET_RMON_R_OVERSIZE_COUNT_MASK 0xFFFFu 05525 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT 0 05526 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK) 05527 /* RMON_R_FRAG Bit Fields */ 05528 #define ENET_RMON_R_FRAG_COUNT_MASK 0xFFFFu 05529 #define ENET_RMON_R_FRAG_COUNT_SHIFT 0 05530 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK) 05531 /* RMON_R_JAB Bit Fields */ 05532 #define ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu 05533 #define ENET_RMON_R_JAB_COUNT_SHIFT 0 05534 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK) 05535 /* RMON_R_P64 Bit Fields */ 05536 #define ENET_RMON_R_P64_COUNT_MASK 0xFFFFu 05537 #define ENET_RMON_R_P64_COUNT_SHIFT 0 05538 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK) 05539 /* RMON_R_P65TO127 Bit Fields */ 05540 #define ENET_RMON_R_P65TO127_COUNT_MASK 0xFFFFu 05541 #define ENET_RMON_R_P65TO127_COUNT_SHIFT 0 05542 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK) 05543 /* RMON_R_P128TO255 Bit Fields */ 05544 #define ENET_RMON_R_P128TO255_COUNT_MASK 0xFFFFu 05545 #define ENET_RMON_R_P128TO255_COUNT_SHIFT 0 05546 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK) 05547 /* RMON_R_P256TO511 Bit Fields */ 05548 #define ENET_RMON_R_P256TO511_COUNT_MASK 0xFFFFu 05549 #define ENET_RMON_R_P256TO511_COUNT_SHIFT 0 05550 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK) 05551 /* RMON_R_P512TO1023 Bit Fields */ 05552 #define ENET_RMON_R_P512TO1023_COUNT_MASK 0xFFFFu 05553 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT 0 05554 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK) 05555 /* RMON_R_P1024TO2047 Bit Fields */ 05556 #define ENET_RMON_R_P1024TO2047_COUNT_MASK 0xFFFFu 05557 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT 0 05558 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK) 05559 /* RMON_R_P_GTE2048 Bit Fields */ 05560 #define ENET_RMON_R_P_GTE2048_COUNT_MASK 0xFFFFu 05561 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT 0 05562 #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK) 05563 /* RMON_R_OCTETS Bit Fields */ 05564 #define ENET_RMON_R_OCTETS_COUNT_MASK 0xFFFFFFFFu 05565 #define ENET_RMON_R_OCTETS_COUNT_SHIFT 0 05566 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK) 05567 /* IEEE_R_DROP Bit Fields */ 05568 #define ENET_IEEE_R_DROP_COUNT_MASK 0xFFFFu 05569 #define ENET_IEEE_R_DROP_COUNT_SHIFT 0 05570 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK) 05571 /* IEEE_R_FRAME_OK Bit Fields */ 05572 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK 0xFFFFu 05573 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT 0 05574 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK) 05575 /* IEEE_R_CRC Bit Fields */ 05576 #define ENET_IEEE_R_CRC_COUNT_MASK 0xFFFFu 05577 #define ENET_IEEE_R_CRC_COUNT_SHIFT 0 05578 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK) 05579 /* IEEE_R_ALIGN Bit Fields */ 05580 #define ENET_IEEE_R_ALIGN_COUNT_MASK 0xFFFFu 05581 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT 0 05582 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK) 05583 /* IEEE_R_MACERR Bit Fields */ 05584 #define ENET_IEEE_R_MACERR_COUNT_MASK 0xFFFFu 05585 #define ENET_IEEE_R_MACERR_COUNT_SHIFT 0 05586 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK) 05587 /* IEEE_R_FDXFC Bit Fields */ 05588 #define ENET_IEEE_R_FDXFC_COUNT_MASK 0xFFFFu 05589 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT 0 05590 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK) 05591 /* IEEE_R_OCTETS_OK Bit Fields */ 05592 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu 05593 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT 0 05594 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK) 05595 /* ATCR Bit Fields */ 05596 #define ENET_ATCR_EN_MASK 0x1u 05597 #define ENET_ATCR_EN_SHIFT 0 05598 #define ENET_ATCR_OFFEN_MASK 0x4u 05599 #define ENET_ATCR_OFFEN_SHIFT 2 05600 #define ENET_ATCR_OFFRST_MASK 0x8u 05601 #define ENET_ATCR_OFFRST_SHIFT 3 05602 #define ENET_ATCR_PEREN_MASK 0x10u 05603 #define ENET_ATCR_PEREN_SHIFT 4 05604 #define ENET_ATCR_PINPER_MASK 0x80u 05605 #define ENET_ATCR_PINPER_SHIFT 7 05606 #define ENET_ATCR_RESTART_MASK 0x200u 05607 #define ENET_ATCR_RESTART_SHIFT 9 05608 #define ENET_ATCR_CAPTURE_MASK 0x800u 05609 #define ENET_ATCR_CAPTURE_SHIFT 11 05610 #define ENET_ATCR_SLAVE_MASK 0x2000u 05611 #define ENET_ATCR_SLAVE_SHIFT 13 05612 /* ATVR Bit Fields */ 05613 #define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu 05614 #define ENET_ATVR_ATIME_SHIFT 0 05615 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK) 05616 /* ATOFF Bit Fields */ 05617 #define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu 05618 #define ENET_ATOFF_OFFSET_SHIFT 0 05619 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK) 05620 /* ATPER Bit Fields */ 05621 #define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu 05622 #define ENET_ATPER_PERIOD_SHIFT 0 05623 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK) 05624 /* ATCOR Bit Fields */ 05625 #define ENET_ATCOR_COR_MASK 0x7FFFFFFFu 05626 #define ENET_ATCOR_COR_SHIFT 0 05627 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK) 05628 /* ATINC Bit Fields */ 05629 #define ENET_ATINC_INC_MASK 0x7Fu 05630 #define ENET_ATINC_INC_SHIFT 0 05631 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK) 05632 #define ENET_ATINC_INC_CORR_MASK 0x7F00u 05633 #define ENET_ATINC_INC_CORR_SHIFT 8 05634 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK) 05635 /* ATSTMP Bit Fields */ 05636 #define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu 05637 #define ENET_ATSTMP_TIMESTAMP_SHIFT 0 05638 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK) 05639 /* TGSR Bit Fields */ 05640 #define ENET_TGSR_TF0_MASK 0x1u 05641 #define ENET_TGSR_TF0_SHIFT 0 05642 #define ENET_TGSR_TF1_MASK 0x2u 05643 #define ENET_TGSR_TF1_SHIFT 1 05644 #define ENET_TGSR_TF2_MASK 0x4u 05645 #define ENET_TGSR_TF2_SHIFT 2 05646 #define ENET_TGSR_TF3_MASK 0x8u 05647 #define ENET_TGSR_TF3_SHIFT 3 05648 /* TCSR Bit Fields */ 05649 #define ENET_TCSR_TDRE_MASK 0x1u 05650 #define ENET_TCSR_TDRE_SHIFT 0 05651 #define ENET_TCSR_TMODE_MASK 0x3Cu 05652 #define ENET_TCSR_TMODE_SHIFT 2 05653 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK) 05654 #define ENET_TCSR_TIE_MASK 0x40u 05655 #define ENET_TCSR_TIE_SHIFT 6 05656 #define ENET_TCSR_TF_MASK 0x80u 05657 #define ENET_TCSR_TF_SHIFT 7 05658 /* TCCR Bit Fields */ 05659 #define ENET_TCCR_TCC_MASK 0xFFFFFFFFu 05660 #define ENET_TCCR_TCC_SHIFT 0 05661 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK) 05662 05663 /*! 05664 * @} 05665 */ /* end of group ENET_Register_Masks */ 05666 05667 05668 /* ENET - Peripheral instance base addresses */ 05669 /** Peripheral ENET base address */ 05670 #define ENET_BASE (0x400C0000u) 05671 /** Peripheral ENET base pointer */ 05672 #define ENET ((ENET_Type *)ENET_BASE) 05673 #define ENET_BASE_PTR (ENET) 05674 /** Array initializer of ENET peripheral base addresses */ 05675 #define ENET_BASE_ADDRS { ENET_BASE } 05676 /** Array initializer of ENET peripheral base pointers */ 05677 #define ENET_BASE_PTRS { ENET } 05678 /** Interrupt vectors for the ENET peripheral type */ 05679 #define ENET_Transmit_IRQS { ENET_Transmit_IRQn } 05680 #define ENET_Receive_IRQS { ENET_Receive_IRQn } 05681 #define ENET_Error_IRQS { ENET_Error_IRQn } 05682 #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn } 05683 05684 /* ---------------------------------------------------------------------------- 05685 -- ENET - Register accessor macros 05686 ---------------------------------------------------------------------------- */ 05687 05688 /*! 05689 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros 05690 * @{ 05691 */ 05692 05693 05694 /* ENET - Register instance definitions */ 05695 /* ENET */ 05696 #define ENET_EIR ENET_EIR_REG(ENET) 05697 #define ENET_EIMR ENET_EIMR_REG(ENET) 05698 #define ENET_RDAR ENET_RDAR_REG(ENET) 05699 #define ENET_TDAR ENET_TDAR_REG(ENET) 05700 #define ENET_ECR ENET_ECR_REG(ENET) 05701 #define ENET_MMFR ENET_MMFR_REG(ENET) 05702 #define ENET_MSCR ENET_MSCR_REG(ENET) 05703 #define ENET_MIBC ENET_MIBC_REG(ENET) 05704 #define ENET_RCR ENET_RCR_REG(ENET) 05705 #define ENET_TCR ENET_TCR_REG(ENET) 05706 #define ENET_PALR ENET_PALR_REG(ENET) 05707 #define ENET_PAUR ENET_PAUR_REG(ENET) 05708 #define ENET_OPD ENET_OPD_REG(ENET) 05709 #define ENET_IAUR ENET_IAUR_REG(ENET) 05710 #define ENET_IALR ENET_IALR_REG(ENET) 05711 #define ENET_GAUR ENET_GAUR_REG(ENET) 05712 #define ENET_GALR ENET_GALR_REG(ENET) 05713 #define ENET_TFWR ENET_TFWR_REG(ENET) 05714 #define ENET_RDSR ENET_RDSR_REG(ENET) 05715 #define ENET_TDSR ENET_TDSR_REG(ENET) 05716 #define ENET_MRBR ENET_MRBR_REG(ENET) 05717 #define ENET_RSFL ENET_RSFL_REG(ENET) 05718 #define ENET_RSEM ENET_RSEM_REG(ENET) 05719 #define ENET_RAEM ENET_RAEM_REG(ENET) 05720 #define ENET_RAFL ENET_RAFL_REG(ENET) 05721 #define ENET_TSEM ENET_TSEM_REG(ENET) 05722 #define ENET_TAEM ENET_TAEM_REG(ENET) 05723 #define ENET_TAFL ENET_TAFL_REG(ENET) 05724 #define ENET_TIPG ENET_TIPG_REG(ENET) 05725 #define ENET_FTRL ENET_FTRL_REG(ENET) 05726 #define ENET_TACC ENET_TACC_REG(ENET) 05727 #define ENET_RACC ENET_RACC_REG(ENET) 05728 #define ENET_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET) 05729 #define ENET_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET) 05730 #define ENET_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET) 05731 #define ENET_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET) 05732 #define ENET_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET) 05733 #define ENET_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET) 05734 #define ENET_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET) 05735 #define ENET_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET) 05736 #define ENET_RMON_T_COL ENET_RMON_T_COL_REG(ENET) 05737 #define ENET_RMON_T_P64 ENET_RMON_T_P64_REG(ENET) 05738 #define ENET_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET) 05739 #define ENET_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET) 05740 #define ENET_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET) 05741 #define ENET_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET) 05742 #define ENET_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET) 05743 #define ENET_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET) 05744 #define ENET_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET) 05745 #define ENET_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET) 05746 #define ENET_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET) 05747 #define ENET_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET) 05748 #define ENET_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET) 05749 #define ENET_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET) 05750 #define ENET_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET) 05751 #define ENET_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET) 05752 #define ENET_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET) 05753 #define ENET_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET) 05754 #define ENET_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET) 05755 #define ENET_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET) 05756 #define ENET_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET) 05757 #define ENET_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET) 05758 #define ENET_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET) 05759 #define ENET_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET) 05760 #define ENET_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET) 05761 #define ENET_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET) 05762 #define ENET_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET) 05763 #define ENET_RMON_R_P64 ENET_RMON_R_P64_REG(ENET) 05764 #define ENET_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET) 05765 #define ENET_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET) 05766 #define ENET_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET) 05767 #define ENET_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET) 05768 #define ENET_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET) 05769 #define ENET_RMON_R_P_GTE2048 ENET_RMON_R_P_GTE2048_REG(ENET) 05770 #define ENET_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET) 05771 #define ENET_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET) 05772 #define ENET_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET) 05773 #define ENET_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET) 05774 #define ENET_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET) 05775 #define ENET_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET) 05776 #define ENET_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET) 05777 #define ENET_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET) 05778 #define ENET_ATCR ENET_ATCR_REG(ENET) 05779 #define ENET_ATVR ENET_ATVR_REG(ENET) 05780 #define ENET_ATOFF ENET_ATOFF_REG(ENET) 05781 #define ENET_ATPER ENET_ATPER_REG(ENET) 05782 #define ENET_ATCOR ENET_ATCOR_REG(ENET) 05783 #define ENET_ATINC ENET_ATINC_REG(ENET) 05784 #define ENET_ATSTMP ENET_ATSTMP_REG(ENET) 05785 #define ENET_TGSR ENET_TGSR_REG(ENET) 05786 #define ENET_TCSR0 ENET_TCSR_REG(ENET,0) 05787 #define ENET_TCCR0 ENET_TCCR_REG(ENET,0) 05788 #define ENET_TCSR1 ENET_TCSR_REG(ENET,1) 05789 #define ENET_TCCR1 ENET_TCCR_REG(ENET,1) 05790 #define ENET_TCSR2 ENET_TCSR_REG(ENET,2) 05791 #define ENET_TCCR2 ENET_TCCR_REG(ENET,2) 05792 #define ENET_TCSR3 ENET_TCSR_REG(ENET,3) 05793 #define ENET_TCCR3 ENET_TCCR_REG(ENET,3) 05794 05795 /* ENET - Register array accessors */ 05796 #define ENET_TCSR(index) ENET_TCSR_REG(ENET,index) 05797 #define ENET_TCCR(index) ENET_TCCR_REG(ENET,index) 05798 05799 /*! 05800 * @} 05801 */ /* end of group ENET_Register_Accessor_Macros */ 05802 05803 05804 /*! 05805 * @} 05806 */ /* end of group ENET_Peripheral_Access_Layer */ 05807 05808 05809 /* ---------------------------------------------------------------------------- 05810 -- EWM Peripheral Access Layer 05811 ---------------------------------------------------------------------------- */ 05812 05813 /*! 05814 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer 05815 * @{ 05816 */ 05817 05818 /** EWM - Register Layout Typedef */ 05819 typedef struct { 05820 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ 05821 __O uint8_t SERV; /**< Service Register, offset: 0x1 */ 05822 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ 05823 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ 05824 } EWM_Type, *EWM_MemMapPtr; 05825 05826 /* ---------------------------------------------------------------------------- 05827 -- EWM - Register accessor macros 05828 ---------------------------------------------------------------------------- */ 05829 05830 /*! 05831 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros 05832 * @{ 05833 */ 05834 05835 05836 /* EWM - Register accessors */ 05837 #define EWM_CTRL_REG(base) ((base)->CTRL) 05838 #define EWM_SERV_REG(base) ((base)->SERV) 05839 #define EWM_CMPL_REG(base) ((base)->CMPL) 05840 #define EWM_CMPH_REG(base) ((base)->CMPH) 05841 05842 /*! 05843 * @} 05844 */ /* end of group EWM_Register_Accessor_Macros */ 05845 05846 05847 /* ---------------------------------------------------------------------------- 05848 -- EWM Register Masks 05849 ---------------------------------------------------------------------------- */ 05850 05851 /*! 05852 * @addtogroup EWM_Register_Masks EWM Register Masks 05853 * @{ 05854 */ 05855 05856 /* CTRL Bit Fields */ 05857 #define EWM_CTRL_EWMEN_MASK 0x1u 05858 #define EWM_CTRL_EWMEN_SHIFT 0 05859 #define EWM_CTRL_ASSIN_MASK 0x2u 05860 #define EWM_CTRL_ASSIN_SHIFT 1 05861 #define EWM_CTRL_INEN_MASK 0x4u 05862 #define EWM_CTRL_INEN_SHIFT 2 05863 #define EWM_CTRL_INTEN_MASK 0x8u 05864 #define EWM_CTRL_INTEN_SHIFT 3 05865 /* SERV Bit Fields */ 05866 #define EWM_SERV_SERVICE_MASK 0xFFu 05867 #define EWM_SERV_SERVICE_SHIFT 0 05868 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK) 05869 /* CMPL Bit Fields */ 05870 #define EWM_CMPL_COMPAREL_MASK 0xFFu 05871 #define EWM_CMPL_COMPAREL_SHIFT 0 05872 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK) 05873 /* CMPH Bit Fields */ 05874 #define EWM_CMPH_COMPAREH_MASK 0xFFu 05875 #define EWM_CMPH_COMPAREH_SHIFT 0 05876 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK) 05877 05878 /*! 05879 * @} 05880 */ /* end of group EWM_Register_Masks */ 05881 05882 05883 /* EWM - Peripheral instance base addresses */ 05884 /** Peripheral EWM base address */ 05885 #define EWM_BASE (0x40061000u) 05886 /** Peripheral EWM base pointer */ 05887 #define EWM ((EWM_Type *)EWM_BASE) 05888 #define EWM_BASE_PTR (EWM) 05889 /** Array initializer of EWM peripheral base addresses */ 05890 #define EWM_BASE_ADDRS { EWM_BASE } 05891 /** Array initializer of EWM peripheral base pointers */ 05892 #define EWM_BASE_PTRS { EWM } 05893 /** Interrupt vectors for the EWM peripheral type */ 05894 #define EWM_IRQS { Watchdog_IRQn } 05895 05896 /* ---------------------------------------------------------------------------- 05897 -- EWM - Register accessor macros 05898 ---------------------------------------------------------------------------- */ 05899 05900 /*! 05901 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros 05902 * @{ 05903 */ 05904 05905 05906 /* EWM - Register instance definitions */ 05907 /* EWM */ 05908 #define EWM_CTRL EWM_CTRL_REG(EWM) 05909 #define EWM_SERV EWM_SERV_REG(EWM) 05910 #define EWM_CMPL EWM_CMPL_REG(EWM) 05911 #define EWM_CMPH EWM_CMPH_REG(EWM) 05912 05913 /*! 05914 * @} 05915 */ /* end of group EWM_Register_Accessor_Macros */ 05916 05917 05918 /*! 05919 * @} 05920 */ /* end of group EWM_Peripheral_Access_Layer */ 05921 05922 05923 /* ---------------------------------------------------------------------------- 05924 -- FB Peripheral Access Layer 05925 ---------------------------------------------------------------------------- */ 05926 05927 /*! 05928 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer 05929 * @{ 05930 */ 05931 05932 /** FB - Register Layout Typedef */ 05933 typedef struct { 05934 struct { /* offset: 0x0, array step: 0xC */ 05935 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */ 05936 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */ 05937 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */ 05938 } CS[6]; 05939 uint8_t RESERVED_0[24]; 05940 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */ 05941 } FB_Type, *FB_MemMapPtr; 05942 05943 /* ---------------------------------------------------------------------------- 05944 -- FB - Register accessor macros 05945 ---------------------------------------------------------------------------- */ 05946 05947 /*! 05948 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros 05949 * @{ 05950 */ 05951 05952 05953 /* FB - Register accessors */ 05954 #define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR) 05955 #define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR) 05956 #define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR) 05957 #define FB_CSPMCR_REG(base) ((base)->CSPMCR) 05958 05959 /*! 05960 * @} 05961 */ /* end of group FB_Register_Accessor_Macros */ 05962 05963 05964 /* ---------------------------------------------------------------------------- 05965 -- FB Register Masks 05966 ---------------------------------------------------------------------------- */ 05967 05968 /*! 05969 * @addtogroup FB_Register_Masks FB Register Masks 05970 * @{ 05971 */ 05972 05973 /* CSAR Bit Fields */ 05974 #define FB_CSAR_BA_MASK 0xFFFF0000u 05975 #define FB_CSAR_BA_SHIFT 16 05976 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK) 05977 /* CSMR Bit Fields */ 05978 #define FB_CSMR_V_MASK 0x1u 05979 #define FB_CSMR_V_SHIFT 0 05980 #define FB_CSMR_WP_MASK 0x100u 05981 #define FB_CSMR_WP_SHIFT 8 05982 #define FB_CSMR_BAM_MASK 0xFFFF0000u 05983 #define FB_CSMR_BAM_SHIFT 16 05984 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK) 05985 /* CSCR Bit Fields */ 05986 #define FB_CSCR_BSTW_MASK 0x8u 05987 #define FB_CSCR_BSTW_SHIFT 3 05988 #define FB_CSCR_BSTR_MASK 0x10u 05989 #define FB_CSCR_BSTR_SHIFT 4 05990 #define FB_CSCR_BEM_MASK 0x20u 05991 #define FB_CSCR_BEM_SHIFT 5 05992 #define FB_CSCR_PS_MASK 0xC0u 05993 #define FB_CSCR_PS_SHIFT 6 05994 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK) 05995 #define FB_CSCR_AA_MASK 0x100u 05996 #define FB_CSCR_AA_SHIFT 8 05997 #define FB_CSCR_BLS_MASK 0x200u 05998 #define FB_CSCR_BLS_SHIFT 9 05999 #define FB_CSCR_WS_MASK 0xFC00u 06000 #define FB_CSCR_WS_SHIFT 10 06001 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK) 06002 #define FB_CSCR_WRAH_MASK 0x30000u 06003 #define FB_CSCR_WRAH_SHIFT 16 06004 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK) 06005 #define FB_CSCR_RDAH_MASK 0xC0000u 06006 #define FB_CSCR_RDAH_SHIFT 18 06007 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK) 06008 #define FB_CSCR_ASET_MASK 0x300000u 06009 #define FB_CSCR_ASET_SHIFT 20 06010 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK) 06011 #define FB_CSCR_EXTS_MASK 0x400000u 06012 #define FB_CSCR_EXTS_SHIFT 22 06013 #define FB_CSCR_SWSEN_MASK 0x800000u 06014 #define FB_CSCR_SWSEN_SHIFT 23 06015 #define FB_CSCR_SWS_MASK 0xFC000000u 06016 #define FB_CSCR_SWS_SHIFT 26 06017 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK) 06018 /* CSPMCR Bit Fields */ 06019 #define FB_CSPMCR_GROUP5_MASK 0xF000u 06020 #define FB_CSPMCR_GROUP5_SHIFT 12 06021 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK) 06022 #define FB_CSPMCR_GROUP4_MASK 0xF0000u 06023 #define FB_CSPMCR_GROUP4_SHIFT 16 06024 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK) 06025 #define FB_CSPMCR_GROUP3_MASK 0xF00000u 06026 #define FB_CSPMCR_GROUP3_SHIFT 20 06027 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK) 06028 #define FB_CSPMCR_GROUP2_MASK 0xF000000u 06029 #define FB_CSPMCR_GROUP2_SHIFT 24 06030 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK) 06031 #define FB_CSPMCR_GROUP1_MASK 0xF0000000u 06032 #define FB_CSPMCR_GROUP1_SHIFT 28 06033 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK) 06034 06035 /*! 06036 * @} 06037 */ /* end of group FB_Register_Masks */ 06038 06039 06040 /* FB - Peripheral instance base addresses */ 06041 /** Peripheral FB base address */ 06042 #define FB_BASE (0x4000C000u) 06043 /** Peripheral FB base pointer */ 06044 #define FB ((FB_Type *)FB_BASE) 06045 #define FB_BASE_PTR (FB) 06046 /** Array initializer of FB peripheral base addresses */ 06047 #define FB_BASE_ADDRS { FB_BASE } 06048 /** Array initializer of FB peripheral base pointers */ 06049 #define FB_BASE_PTRS { FB } 06050 06051 /* ---------------------------------------------------------------------------- 06052 -- FB - Register accessor macros 06053 ---------------------------------------------------------------------------- */ 06054 06055 /*! 06056 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros 06057 * @{ 06058 */ 06059 06060 06061 /* FB - Register instance definitions */ 06062 /* FB */ 06063 #define FB_CSAR0 FB_CSAR_REG(FB,0) 06064 #define FB_CSMR0 FB_CSMR_REG(FB,0) 06065 #define FB_CSCR0 FB_CSCR_REG(FB,0) 06066 #define FB_CSAR1 FB_CSAR_REG(FB,1) 06067 #define FB_CSMR1 FB_CSMR_REG(FB,1) 06068 #define FB_CSCR1 FB_CSCR_REG(FB,1) 06069 #define FB_CSAR2 FB_CSAR_REG(FB,2) 06070 #define FB_CSMR2 FB_CSMR_REG(FB,2) 06071 #define FB_CSCR2 FB_CSCR_REG(FB,2) 06072 #define FB_CSAR3 FB_CSAR_REG(FB,3) 06073 #define FB_CSMR3 FB_CSMR_REG(FB,3) 06074 #define FB_CSCR3 FB_CSCR_REG(FB,3) 06075 #define FB_CSAR4 FB_CSAR_REG(FB,4) 06076 #define FB_CSMR4 FB_CSMR_REG(FB,4) 06077 #define FB_CSCR4 FB_CSCR_REG(FB,4) 06078 #define FB_CSAR5 FB_CSAR_REG(FB,5) 06079 #define FB_CSMR5 FB_CSMR_REG(FB,5) 06080 #define FB_CSCR5 FB_CSCR_REG(FB,5) 06081 #define FB_CSPMCR FB_CSPMCR_REG(FB) 06082 06083 /* FB - Register array accessors */ 06084 #define FB_CSAR(index) FB_CSAR_REG(FB,index) 06085 #define FB_CSMR(index) FB_CSMR_REG(FB,index) 06086 #define FB_CSCR(index) FB_CSCR_REG(FB,index) 06087 06088 /*! 06089 * @} 06090 */ /* end of group FB_Register_Accessor_Macros */ 06091 06092 06093 /*! 06094 * @} 06095 */ /* end of group FB_Peripheral_Access_Layer */ 06096 06097 06098 /* ---------------------------------------------------------------------------- 06099 -- FMC Peripheral Access Layer 06100 ---------------------------------------------------------------------------- */ 06101 06102 /*! 06103 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer 06104 * @{ 06105 */ 06106 06107 /** FMC - Register Layout Typedef */ 06108 typedef struct { 06109 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */ 06110 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */ 06111 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */ 06112 uint8_t RESERVED_0[244]; 06113 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */ 06114 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */ 06115 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */ 06116 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */ 06117 uint8_t RESERVED_1[192]; 06118 struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */ 06119 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */ 06120 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */ 06121 } SET[4][4]; 06122 } FMC_Type, *FMC_MemMapPtr; 06123 06124 /* ---------------------------------------------------------------------------- 06125 -- FMC - Register accessor macros 06126 ---------------------------------------------------------------------------- */ 06127 06128 /*! 06129 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros 06130 * @{ 06131 */ 06132 06133 06134 /* FMC - Register accessors */ 06135 #define FMC_PFAPR_REG(base) ((base)->PFAPR) 06136 #define FMC_PFB0CR_REG(base) ((base)->PFB0CR) 06137 #define FMC_PFB1CR_REG(base) ((base)->PFB1CR) 06138 #define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index]) 06139 #define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index]) 06140 #define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index]) 06141 #define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index]) 06142 #define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U) 06143 #define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L) 06144 06145 /*! 06146 * @} 06147 */ /* end of group FMC_Register_Accessor_Macros */ 06148 06149 06150 /* ---------------------------------------------------------------------------- 06151 -- FMC Register Masks 06152 ---------------------------------------------------------------------------- */ 06153 06154 /*! 06155 * @addtogroup FMC_Register_Masks FMC Register Masks 06156 * @{ 06157 */ 06158 06159 /* PFAPR Bit Fields */ 06160 #define FMC_PFAPR_M0AP_MASK 0x3u 06161 #define FMC_PFAPR_M0AP_SHIFT 0 06162 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK) 06163 #define FMC_PFAPR_M1AP_MASK 0xCu 06164 #define FMC_PFAPR_M1AP_SHIFT 2 06165 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK) 06166 #define FMC_PFAPR_M2AP_MASK 0x30u 06167 #define FMC_PFAPR_M2AP_SHIFT 4 06168 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK) 06169 #define FMC_PFAPR_M3AP_MASK 0xC0u 06170 #define FMC_PFAPR_M3AP_SHIFT 6 06171 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK) 06172 #define FMC_PFAPR_M4AP_MASK 0x300u 06173 #define FMC_PFAPR_M4AP_SHIFT 8 06174 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK) 06175 #define FMC_PFAPR_M5AP_MASK 0xC00u 06176 #define FMC_PFAPR_M5AP_SHIFT 10 06177 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK) 06178 #define FMC_PFAPR_M6AP_MASK 0x3000u 06179 #define FMC_PFAPR_M6AP_SHIFT 12 06180 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK) 06181 #define FMC_PFAPR_M7AP_MASK 0xC000u 06182 #define FMC_PFAPR_M7AP_SHIFT 14 06183 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK) 06184 #define FMC_PFAPR_M0PFD_MASK 0x10000u 06185 #define FMC_PFAPR_M0PFD_SHIFT 16 06186 #define FMC_PFAPR_M1PFD_MASK 0x20000u 06187 #define FMC_PFAPR_M1PFD_SHIFT 17 06188 #define FMC_PFAPR_M2PFD_MASK 0x40000u 06189 #define FMC_PFAPR_M2PFD_SHIFT 18 06190 #define FMC_PFAPR_M3PFD_MASK 0x80000u 06191 #define FMC_PFAPR_M3PFD_SHIFT 19 06192 #define FMC_PFAPR_M4PFD_MASK 0x100000u 06193 #define FMC_PFAPR_M4PFD_SHIFT 20 06194 #define FMC_PFAPR_M5PFD_MASK 0x200000u 06195 #define FMC_PFAPR_M5PFD_SHIFT 21 06196 #define FMC_PFAPR_M6PFD_MASK 0x400000u 06197 #define FMC_PFAPR_M6PFD_SHIFT 22 06198 #define FMC_PFAPR_M7PFD_MASK 0x800000u 06199 #define FMC_PFAPR_M7PFD_SHIFT 23 06200 /* PFB0CR Bit Fields */ 06201 #define FMC_PFB0CR_B0SEBE_MASK 0x1u 06202 #define FMC_PFB0CR_B0SEBE_SHIFT 0 06203 #define FMC_PFB0CR_B0IPE_MASK 0x2u 06204 #define FMC_PFB0CR_B0IPE_SHIFT 1 06205 #define FMC_PFB0CR_B0DPE_MASK 0x4u 06206 #define FMC_PFB0CR_B0DPE_SHIFT 2 06207 #define FMC_PFB0CR_B0ICE_MASK 0x8u 06208 #define FMC_PFB0CR_B0ICE_SHIFT 3 06209 #define FMC_PFB0CR_B0DCE_MASK 0x10u 06210 #define FMC_PFB0CR_B0DCE_SHIFT 4 06211 #define FMC_PFB0CR_CRC_MASK 0xE0u 06212 #define FMC_PFB0CR_CRC_SHIFT 5 06213 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK) 06214 #define FMC_PFB0CR_B0MW_MASK 0x60000u 06215 #define FMC_PFB0CR_B0MW_SHIFT 17 06216 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK) 06217 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u 06218 #define FMC_PFB0CR_S_B_INV_SHIFT 19 06219 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u 06220 #define FMC_PFB0CR_CINV_WAY_SHIFT 20 06221 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK) 06222 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u 06223 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24 06224 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK) 06225 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u 06226 #define FMC_PFB0CR_B0RWSC_SHIFT 28 06227 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK) 06228 /* PFB1CR Bit Fields */ 06229 #define FMC_PFB1CR_B1SEBE_MASK 0x1u 06230 #define FMC_PFB1CR_B1SEBE_SHIFT 0 06231 #define FMC_PFB1CR_B1IPE_MASK 0x2u 06232 #define FMC_PFB1CR_B1IPE_SHIFT 1 06233 #define FMC_PFB1CR_B1DPE_MASK 0x4u 06234 #define FMC_PFB1CR_B1DPE_SHIFT 2 06235 #define FMC_PFB1CR_B1ICE_MASK 0x8u 06236 #define FMC_PFB1CR_B1ICE_SHIFT 3 06237 #define FMC_PFB1CR_B1DCE_MASK 0x10u 06238 #define FMC_PFB1CR_B1DCE_SHIFT 4 06239 #define FMC_PFB1CR_B1MW_MASK 0x60000u 06240 #define FMC_PFB1CR_B1MW_SHIFT 17 06241 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK) 06242 #define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u 06243 #define FMC_PFB1CR_B1RWSC_SHIFT 28 06244 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK) 06245 /* TAGVDW0S Bit Fields */ 06246 #define FMC_TAGVDW0S_valid_MASK 0x1u 06247 #define FMC_TAGVDW0S_valid_SHIFT 0 06248 #define FMC_TAGVDW0S_tag_MASK 0x7FFE0u 06249 #define FMC_TAGVDW0S_tag_SHIFT 5 06250 #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK) 06251 /* TAGVDW1S Bit Fields */ 06252 #define FMC_TAGVDW1S_valid_MASK 0x1u 06253 #define FMC_TAGVDW1S_valid_SHIFT 0 06254 #define FMC_TAGVDW1S_tag_MASK 0x7FFE0u 06255 #define FMC_TAGVDW1S_tag_SHIFT 5 06256 #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK) 06257 /* TAGVDW2S Bit Fields */ 06258 #define FMC_TAGVDW2S_valid_MASK 0x1u 06259 #define FMC_TAGVDW2S_valid_SHIFT 0 06260 #define FMC_TAGVDW2S_tag_MASK 0x7FFE0u 06261 #define FMC_TAGVDW2S_tag_SHIFT 5 06262 #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK) 06263 /* TAGVDW3S Bit Fields */ 06264 #define FMC_TAGVDW3S_valid_MASK 0x1u 06265 #define FMC_TAGVDW3S_valid_SHIFT 0 06266 #define FMC_TAGVDW3S_tag_MASK 0x7FFE0u 06267 #define FMC_TAGVDW3S_tag_SHIFT 5 06268 #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK) 06269 /* DATA_U Bit Fields */ 06270 #define FMC_DATA_U_data_MASK 0xFFFFFFFFu 06271 #define FMC_DATA_U_data_SHIFT 0 06272 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK) 06273 /* DATA_L Bit Fields */ 06274 #define FMC_DATA_L_data_MASK 0xFFFFFFFFu 06275 #define FMC_DATA_L_data_SHIFT 0 06276 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK) 06277 06278 /*! 06279 * @} 06280 */ /* end of group FMC_Register_Masks */ 06281 06282 06283 /* FMC - Peripheral instance base addresses */ 06284 /** Peripheral FMC base address */ 06285 #define FMC_BASE (0x4001F000u) 06286 /** Peripheral FMC base pointer */ 06287 #define FMC ((FMC_Type *)FMC_BASE) 06288 #define FMC_BASE_PTR (FMC) 06289 /** Array initializer of FMC peripheral base addresses */ 06290 #define FMC_BASE_ADDRS { FMC_BASE } 06291 /** Array initializer of FMC peripheral base pointers */ 06292 #define FMC_BASE_PTRS { FMC } 06293 06294 /* ---------------------------------------------------------------------------- 06295 -- FMC - Register accessor macros 06296 ---------------------------------------------------------------------------- */ 06297 06298 /*! 06299 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros 06300 * @{ 06301 */ 06302 06303 06304 /* FMC - Register instance definitions */ 06305 /* FMC */ 06306 #define FMC_PFAPR FMC_PFAPR_REG(FMC) 06307 #define FMC_PFB0CR FMC_PFB0CR_REG(FMC) 06308 #define FMC_PFB1CR FMC_PFB1CR_REG(FMC) 06309 #define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0) 06310 #define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1) 06311 #define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2) 06312 #define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3) 06313 #define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0) 06314 #define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1) 06315 #define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2) 06316 #define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3) 06317 #define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0) 06318 #define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1) 06319 #define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2) 06320 #define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3) 06321 #define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0) 06322 #define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1) 06323 #define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2) 06324 #define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3) 06325 #define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0) 06326 #define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0) 06327 #define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1) 06328 #define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1) 06329 #define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2) 06330 #define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2) 06331 #define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3) 06332 #define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3) 06333 #define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0) 06334 #define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0) 06335 #define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1) 06336 #define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1) 06337 #define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2) 06338 #define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2) 06339 #define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3) 06340 #define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3) 06341 #define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0) 06342 #define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0) 06343 #define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1) 06344 #define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1) 06345 #define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2) 06346 #define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2) 06347 #define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3) 06348 #define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3) 06349 #define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0) 06350 #define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0) 06351 #define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1) 06352 #define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1) 06353 #define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2) 06354 #define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2) 06355 #define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3) 06356 #define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3) 06357 06358 /* FMC - Register array accessors */ 06359 #define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index) 06360 #define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index) 06361 #define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index) 06362 #define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index) 06363 #define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2) 06364 #define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2) 06365 06366 /*! 06367 * @} 06368 */ /* end of group FMC_Register_Accessor_Macros */ 06369 06370 06371 /*! 06372 * @} 06373 */ /* end of group FMC_Peripheral_Access_Layer */ 06374 06375 06376 /* ---------------------------------------------------------------------------- 06377 -- FTFE Peripheral Access Layer 06378 ---------------------------------------------------------------------------- */ 06379 06380 /*! 06381 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer 06382 * @{ 06383 */ 06384 06385 /** FTFE - Register Layout Typedef */ 06386 typedef struct { 06387 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ 06388 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ 06389 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ 06390 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ 06391 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ 06392 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ 06393 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ 06394 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ 06395 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ 06396 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ 06397 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ 06398 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ 06399 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ 06400 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ 06401 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ 06402 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ 06403 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ 06404 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ 06405 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ 06406 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ 06407 uint8_t RESERVED_0[2]; 06408 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */ 06409 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */ 06410 } FTFE_Type, *FTFE_MemMapPtr; 06411 06412 /* ---------------------------------------------------------------------------- 06413 -- FTFE - Register accessor macros 06414 ---------------------------------------------------------------------------- */ 06415 06416 /*! 06417 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros 06418 * @{ 06419 */ 06420 06421 06422 /* FTFE - Register accessors */ 06423 #define FTFE_FSTAT_REG(base) ((base)->FSTAT) 06424 #define FTFE_FCNFG_REG(base) ((base)->FCNFG) 06425 #define FTFE_FSEC_REG(base) ((base)->FSEC) 06426 #define FTFE_FOPT_REG(base) ((base)->FOPT) 06427 #define FTFE_FCCOB3_REG(base) ((base)->FCCOB3) 06428 #define FTFE_FCCOB2_REG(base) ((base)->FCCOB2) 06429 #define FTFE_FCCOB1_REG(base) ((base)->FCCOB1) 06430 #define FTFE_FCCOB0_REG(base) ((base)->FCCOB0) 06431 #define FTFE_FCCOB7_REG(base) ((base)->FCCOB7) 06432 #define FTFE_FCCOB6_REG(base) ((base)->FCCOB6) 06433 #define FTFE_FCCOB5_REG(base) ((base)->FCCOB5) 06434 #define FTFE_FCCOB4_REG(base) ((base)->FCCOB4) 06435 #define FTFE_FCCOBB_REG(base) ((base)->FCCOBB) 06436 #define FTFE_FCCOBA_REG(base) ((base)->FCCOBA) 06437 #define FTFE_FCCOB9_REG(base) ((base)->FCCOB9) 06438 #define FTFE_FCCOB8_REG(base) ((base)->FCCOB8) 06439 #define FTFE_FPROT3_REG(base) ((base)->FPROT3) 06440 #define FTFE_FPROT2_REG(base) ((base)->FPROT2) 06441 #define FTFE_FPROT1_REG(base) ((base)->FPROT1) 06442 #define FTFE_FPROT0_REG(base) ((base)->FPROT0) 06443 #define FTFE_FEPROT_REG(base) ((base)->FEPROT) 06444 #define FTFE_FDPROT_REG(base) ((base)->FDPROT) 06445 06446 /*! 06447 * @} 06448 */ /* end of group FTFE_Register_Accessor_Macros */ 06449 06450 06451 /* ---------------------------------------------------------------------------- 06452 -- FTFE Register Masks 06453 ---------------------------------------------------------------------------- */ 06454 06455 /*! 06456 * @addtogroup FTFE_Register_Masks FTFE Register Masks 06457 * @{ 06458 */ 06459 06460 /* FSTAT Bit Fields */ 06461 #define FTFE_FSTAT_MGSTAT0_MASK 0x1u 06462 #define FTFE_FSTAT_MGSTAT0_SHIFT 0 06463 #define FTFE_FSTAT_FPVIOL_MASK 0x10u 06464 #define FTFE_FSTAT_FPVIOL_SHIFT 4 06465 #define FTFE_FSTAT_ACCERR_MASK 0x20u 06466 #define FTFE_FSTAT_ACCERR_SHIFT 5 06467 #define FTFE_FSTAT_RDCOLERR_MASK 0x40u 06468 #define FTFE_FSTAT_RDCOLERR_SHIFT 6 06469 #define FTFE_FSTAT_CCIF_MASK 0x80u 06470 #define FTFE_FSTAT_CCIF_SHIFT 7 06471 /* FCNFG Bit Fields */ 06472 #define FTFE_FCNFG_EEERDY_MASK 0x1u 06473 #define FTFE_FCNFG_EEERDY_SHIFT 0 06474 #define FTFE_FCNFG_RAMRDY_MASK 0x2u 06475 #define FTFE_FCNFG_RAMRDY_SHIFT 1 06476 #define FTFE_FCNFG_PFLSH_MASK 0x4u 06477 #define FTFE_FCNFG_PFLSH_SHIFT 2 06478 #define FTFE_FCNFG_SWAP_MASK 0x8u 06479 #define FTFE_FCNFG_SWAP_SHIFT 3 06480 #define FTFE_FCNFG_ERSSUSP_MASK 0x10u 06481 #define FTFE_FCNFG_ERSSUSP_SHIFT 4 06482 #define FTFE_FCNFG_ERSAREQ_MASK 0x20u 06483 #define FTFE_FCNFG_ERSAREQ_SHIFT 5 06484 #define FTFE_FCNFG_RDCOLLIE_MASK 0x40u 06485 #define FTFE_FCNFG_RDCOLLIE_SHIFT 6 06486 #define FTFE_FCNFG_CCIE_MASK 0x80u 06487 #define FTFE_FCNFG_CCIE_SHIFT 7 06488 /* FSEC Bit Fields */ 06489 #define FTFE_FSEC_SEC_MASK 0x3u 06490 #define FTFE_FSEC_SEC_SHIFT 0 06491 #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK) 06492 #define FTFE_FSEC_FSLACC_MASK 0xCu 06493 #define FTFE_FSEC_FSLACC_SHIFT 2 06494 #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK) 06495 #define FTFE_FSEC_MEEN_MASK 0x30u 06496 #define FTFE_FSEC_MEEN_SHIFT 4 06497 #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK) 06498 #define FTFE_FSEC_KEYEN_MASK 0xC0u 06499 #define FTFE_FSEC_KEYEN_SHIFT 6 06500 #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK) 06501 /* FOPT Bit Fields */ 06502 #define FTFE_FOPT_OPT_MASK 0xFFu 06503 #define FTFE_FOPT_OPT_SHIFT 0 06504 #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK) 06505 /* FCCOB3 Bit Fields */ 06506 #define FTFE_FCCOB3_CCOBn_MASK 0xFFu 06507 #define FTFE_FCCOB3_CCOBn_SHIFT 0 06508 #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK) 06509 /* FCCOB2 Bit Fields */ 06510 #define FTFE_FCCOB2_CCOBn_MASK 0xFFu 06511 #define FTFE_FCCOB2_CCOBn_SHIFT 0 06512 #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK) 06513 /* FCCOB1 Bit Fields */ 06514 #define FTFE_FCCOB1_CCOBn_MASK 0xFFu 06515 #define FTFE_FCCOB1_CCOBn_SHIFT 0 06516 #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK) 06517 /* FCCOB0 Bit Fields */ 06518 #define FTFE_FCCOB0_CCOBn_MASK 0xFFu 06519 #define FTFE_FCCOB0_CCOBn_SHIFT 0 06520 #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK) 06521 /* FCCOB7 Bit Fields */ 06522 #define FTFE_FCCOB7_CCOBn_MASK 0xFFu 06523 #define FTFE_FCCOB7_CCOBn_SHIFT 0 06524 #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK) 06525 /* FCCOB6 Bit Fields */ 06526 #define FTFE_FCCOB6_CCOBn_MASK 0xFFu 06527 #define FTFE_FCCOB6_CCOBn_SHIFT 0 06528 #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK) 06529 /* FCCOB5 Bit Fields */ 06530 #define FTFE_FCCOB5_CCOBn_MASK 0xFFu 06531 #define FTFE_FCCOB5_CCOBn_SHIFT 0 06532 #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK) 06533 /* FCCOB4 Bit Fields */ 06534 #define FTFE_FCCOB4_CCOBn_MASK 0xFFu 06535 #define FTFE_FCCOB4_CCOBn_SHIFT 0 06536 #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK) 06537 /* FCCOBB Bit Fields */ 06538 #define FTFE_FCCOBB_CCOBn_MASK 0xFFu 06539 #define FTFE_FCCOBB_CCOBn_SHIFT 0 06540 #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK) 06541 /* FCCOBA Bit Fields */ 06542 #define FTFE_FCCOBA_CCOBn_MASK 0xFFu 06543 #define FTFE_FCCOBA_CCOBn_SHIFT 0 06544 #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK) 06545 /* FCCOB9 Bit Fields */ 06546 #define FTFE_FCCOB9_CCOBn_MASK 0xFFu 06547 #define FTFE_FCCOB9_CCOBn_SHIFT 0 06548 #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK) 06549 /* FCCOB8 Bit Fields */ 06550 #define FTFE_FCCOB8_CCOBn_MASK 0xFFu 06551 #define FTFE_FCCOB8_CCOBn_SHIFT 0 06552 #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK) 06553 /* FPROT3 Bit Fields */ 06554 #define FTFE_FPROT3_PROT_MASK 0xFFu 06555 #define FTFE_FPROT3_PROT_SHIFT 0 06556 #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK) 06557 /* FPROT2 Bit Fields */ 06558 #define FTFE_FPROT2_PROT_MASK 0xFFu 06559 #define FTFE_FPROT2_PROT_SHIFT 0 06560 #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK) 06561 /* FPROT1 Bit Fields */ 06562 #define FTFE_FPROT1_PROT_MASK 0xFFu 06563 #define FTFE_FPROT1_PROT_SHIFT 0 06564 #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK) 06565 /* FPROT0 Bit Fields */ 06566 #define FTFE_FPROT0_PROT_MASK 0xFFu 06567 #define FTFE_FPROT0_PROT_SHIFT 0 06568 #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK) 06569 /* FEPROT Bit Fields */ 06570 #define FTFE_FEPROT_EPROT_MASK 0xFFu 06571 #define FTFE_FEPROT_EPROT_SHIFT 0 06572 #define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK) 06573 /* FDPROT Bit Fields */ 06574 #define FTFE_FDPROT_DPROT_MASK 0xFFu 06575 #define FTFE_FDPROT_DPROT_SHIFT 0 06576 #define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK) 06577 06578 /*! 06579 * @} 06580 */ /* end of group FTFE_Register_Masks */ 06581 06582 06583 /* FTFE - Peripheral instance base addresses */ 06584 /** Peripheral FTFE base address */ 06585 #define FTFE_BASE (0x40020000u) 06586 /** Peripheral FTFE base pointer */ 06587 #define FTFE ((FTFE_Type *)FTFE_BASE) 06588 #define FTFE_BASE_PTR (FTFE) 06589 /** Array initializer of FTFE peripheral base addresses */ 06590 #define FTFE_BASE_ADDRS { FTFE_BASE } 06591 /** Array initializer of FTFE peripheral base pointers */ 06592 #define FTFE_BASE_PTRS { FTFE } 06593 /** Interrupt vectors for the FTFE peripheral type */ 06594 #define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn } 06595 #define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn } 06596 06597 /* ---------------------------------------------------------------------------- 06598 -- FTFE - Register accessor macros 06599 ---------------------------------------------------------------------------- */ 06600 06601 /*! 06602 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros 06603 * @{ 06604 */ 06605 06606 06607 /* FTFE - Register instance definitions */ 06608 /* FTFE */ 06609 #define FTFE_FSTAT FTFE_FSTAT_REG(FTFE) 06610 #define FTFE_FCNFG FTFE_FCNFG_REG(FTFE) 06611 #define FTFE_FSEC FTFE_FSEC_REG(FTFE) 06612 #define FTFE_FOPT FTFE_FOPT_REG(FTFE) 06613 #define FTFE_FCCOB3 FTFE_FCCOB3_REG(FTFE) 06614 #define FTFE_FCCOB2 FTFE_FCCOB2_REG(FTFE) 06615 #define FTFE_FCCOB1 FTFE_FCCOB1_REG(FTFE) 06616 #define FTFE_FCCOB0 FTFE_FCCOB0_REG(FTFE) 06617 #define FTFE_FCCOB7 FTFE_FCCOB7_REG(FTFE) 06618 #define FTFE_FCCOB6 FTFE_FCCOB6_REG(FTFE) 06619 #define FTFE_FCCOB5 FTFE_FCCOB5_REG(FTFE) 06620 #define FTFE_FCCOB4 FTFE_FCCOB4_REG(FTFE) 06621 #define FTFE_FCCOBB FTFE_FCCOBB_REG(FTFE) 06622 #define FTFE_FCCOBA FTFE_FCCOBA_REG(FTFE) 06623 #define FTFE_FCCOB9 FTFE_FCCOB9_REG(FTFE) 06624 #define FTFE_FCCOB8 FTFE_FCCOB8_REG(FTFE) 06625 #define FTFE_FPROT3 FTFE_FPROT3_REG(FTFE) 06626 #define FTFE_FPROT2 FTFE_FPROT2_REG(FTFE) 06627 #define FTFE_FPROT1 FTFE_FPROT1_REG(FTFE) 06628 #define FTFE_FPROT0 FTFE_FPROT0_REG(FTFE) 06629 #define FTFE_FEPROT FTFE_FEPROT_REG(FTFE) 06630 #define FTFE_FDPROT FTFE_FDPROT_REG(FTFE) 06631 06632 /*! 06633 * @} 06634 */ /* end of group FTFE_Register_Accessor_Macros */ 06635 06636 06637 /*! 06638 * @} 06639 */ /* end of group FTFE_Peripheral_Access_Layer */ 06640 06641 06642 /* ---------------------------------------------------------------------------- 06643 -- FTM Peripheral Access Layer 06644 ---------------------------------------------------------------------------- */ 06645 06646 /*! 06647 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer 06648 * @{ 06649 */ 06650 06651 /** FTM - Register Layout Typedef */ 06652 typedef struct { 06653 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ 06654 __IO uint32_t CNT; /**< Counter, offset: 0x4 */ 06655 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ 06656 struct { /* offset: 0xC, array step: 0x8 */ 06657 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ 06658 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ 06659 } CONTROLS[8]; 06660 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ 06661 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ 06662 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ 06663 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ 06664 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ 06665 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ 06666 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ 06667 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ 06668 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ 06669 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ 06670 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ 06671 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ 06672 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ 06673 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */ 06674 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ 06675 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ 06676 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ 06677 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ 06678 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ 06679 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ 06680 } FTM_Type, *FTM_MemMapPtr; 06681 06682 /* ---------------------------------------------------------------------------- 06683 -- FTM - Register accessor macros 06684 ---------------------------------------------------------------------------- */ 06685 06686 /*! 06687 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros 06688 * @{ 06689 */ 06690 06691 06692 /* FTM - Register accessors */ 06693 #define FTM_SC_REG(base) ((base)->SC) 06694 #define FTM_CNT_REG(base) ((base)->CNT) 06695 #define FTM_MOD_REG(base) ((base)->MOD) 06696 #define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) 06697 #define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) 06698 #define FTM_CNTIN_REG(base) ((base)->CNTIN) 06699 #define FTM_STATUS_REG(base) ((base)->STATUS) 06700 #define FTM_MODE_REG(base) ((base)->MODE) 06701 #define FTM_SYNC_REG(base) ((base)->SYNC) 06702 #define FTM_OUTINIT_REG(base) ((base)->OUTINIT) 06703 #define FTM_OUTMASK_REG(base) ((base)->OUTMASK) 06704 #define FTM_COMBINE_REG(base) ((base)->COMBINE) 06705 #define FTM_DEADTIME_REG(base) ((base)->DEADTIME) 06706 #define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) 06707 #define FTM_POL_REG(base) ((base)->POL) 06708 #define FTM_FMS_REG(base) ((base)->FMS) 06709 #define FTM_FILTER_REG(base) ((base)->FILTER) 06710 #define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) 06711 #define FTM_QDCTRL_REG(base) ((base)->QDCTRL) 06712 #define FTM_CONF_REG(base) ((base)->CONF) 06713 #define FTM_FLTPOL_REG(base) ((base)->FLTPOL) 06714 #define FTM_SYNCONF_REG(base) ((base)->SYNCONF) 06715 #define FTM_INVCTRL_REG(base) ((base)->INVCTRL) 06716 #define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) 06717 #define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) 06718 06719 /*! 06720 * @} 06721 */ /* end of group FTM_Register_Accessor_Macros */ 06722 06723 06724 /* ---------------------------------------------------------------------------- 06725 -- FTM Register Masks 06726 ---------------------------------------------------------------------------- */ 06727 06728 /*! 06729 * @addtogroup FTM_Register_Masks FTM Register Masks 06730 * @{ 06731 */ 06732 06733 /* SC Bit Fields */ 06734 #define FTM_SC_PS_MASK 0x7u 06735 #define FTM_SC_PS_SHIFT 0 06736 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK) 06737 #define FTM_SC_CLKS_MASK 0x18u 06738 #define FTM_SC_CLKS_SHIFT 3 06739 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK) 06740 #define FTM_SC_CPWMS_MASK 0x20u 06741 #define FTM_SC_CPWMS_SHIFT 5 06742 #define FTM_SC_TOIE_MASK 0x40u 06743 #define FTM_SC_TOIE_SHIFT 6 06744 #define FTM_SC_TOF_MASK 0x80u 06745 #define FTM_SC_TOF_SHIFT 7 06746 /* CNT Bit Fields */ 06747 #define FTM_CNT_COUNT_MASK 0xFFFFu 06748 #define FTM_CNT_COUNT_SHIFT 0 06749 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK) 06750 /* MOD Bit Fields */ 06751 #define FTM_MOD_MOD_MASK 0xFFFFu 06752 #define FTM_MOD_MOD_SHIFT 0 06753 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK) 06754 /* CnSC Bit Fields */ 06755 #define FTM_CnSC_DMA_MASK 0x1u 06756 #define FTM_CnSC_DMA_SHIFT 0 06757 #define FTM_CnSC_ELSA_MASK 0x4u 06758 #define FTM_CnSC_ELSA_SHIFT 2 06759 #define FTM_CnSC_ELSB_MASK 0x8u 06760 #define FTM_CnSC_ELSB_SHIFT 3 06761 #define FTM_CnSC_MSA_MASK 0x10u 06762 #define FTM_CnSC_MSA_SHIFT 4 06763 #define FTM_CnSC_MSB_MASK 0x20u 06764 #define FTM_CnSC_MSB_SHIFT 5 06765 #define FTM_CnSC_CHIE_MASK 0x40u 06766 #define FTM_CnSC_CHIE_SHIFT 6 06767 #define FTM_CnSC_CHF_MASK 0x80u 06768 #define FTM_CnSC_CHF_SHIFT 7 06769 /* CnV Bit Fields */ 06770 #define FTM_CnV_VAL_MASK 0xFFFFu 06771 #define FTM_CnV_VAL_SHIFT 0 06772 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK) 06773 /* CNTIN Bit Fields */ 06774 #define FTM_CNTIN_INIT_MASK 0xFFFFu 06775 #define FTM_CNTIN_INIT_SHIFT 0 06776 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK) 06777 /* STATUS Bit Fields */ 06778 #define FTM_STATUS_CH0F_MASK 0x1u 06779 #define FTM_STATUS_CH0F_SHIFT 0 06780 #define FTM_STATUS_CH1F_MASK 0x2u 06781 #define FTM_STATUS_CH1F_SHIFT 1 06782 #define FTM_STATUS_CH2F_MASK 0x4u 06783 #define FTM_STATUS_CH2F_SHIFT 2 06784 #define FTM_STATUS_CH3F_MASK 0x8u 06785 #define FTM_STATUS_CH3F_SHIFT 3 06786 #define FTM_STATUS_CH4F_MASK 0x10u 06787 #define FTM_STATUS_CH4F_SHIFT 4 06788 #define FTM_STATUS_CH5F_MASK 0x20u 06789 #define FTM_STATUS_CH5F_SHIFT 5 06790 #define FTM_STATUS_CH6F_MASK 0x40u 06791 #define FTM_STATUS_CH6F_SHIFT 6 06792 #define FTM_STATUS_CH7F_MASK 0x80u 06793 #define FTM_STATUS_CH7F_SHIFT 7 06794 /* MODE Bit Fields */ 06795 #define FTM_MODE_FTMEN_MASK 0x1u 06796 #define FTM_MODE_FTMEN_SHIFT 0 06797 #define FTM_MODE_INIT_MASK 0x2u 06798 #define FTM_MODE_INIT_SHIFT 1 06799 #define FTM_MODE_WPDIS_MASK 0x4u 06800 #define FTM_MODE_WPDIS_SHIFT 2 06801 #define FTM_MODE_PWMSYNC_MASK 0x8u 06802 #define FTM_MODE_PWMSYNC_SHIFT 3 06803 #define FTM_MODE_CAPTEST_MASK 0x10u 06804 #define FTM_MODE_CAPTEST_SHIFT 4 06805 #define FTM_MODE_FAULTM_MASK 0x60u 06806 #define FTM_MODE_FAULTM_SHIFT 5 06807 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK) 06808 #define FTM_MODE_FAULTIE_MASK 0x80u 06809 #define FTM_MODE_FAULTIE_SHIFT 7 06810 /* SYNC Bit Fields */ 06811 #define FTM_SYNC_CNTMIN_MASK 0x1u 06812 #define FTM_SYNC_CNTMIN_SHIFT 0 06813 #define FTM_SYNC_CNTMAX_MASK 0x2u 06814 #define FTM_SYNC_CNTMAX_SHIFT 1 06815 #define FTM_SYNC_REINIT_MASK 0x4u 06816 #define FTM_SYNC_REINIT_SHIFT 2 06817 #define FTM_SYNC_SYNCHOM_MASK 0x8u 06818 #define FTM_SYNC_SYNCHOM_SHIFT 3 06819 #define FTM_SYNC_TRIG0_MASK 0x10u 06820 #define FTM_SYNC_TRIG0_SHIFT 4 06821 #define FTM_SYNC_TRIG1_MASK 0x20u 06822 #define FTM_SYNC_TRIG1_SHIFT 5 06823 #define FTM_SYNC_TRIG2_MASK 0x40u 06824 #define FTM_SYNC_TRIG2_SHIFT 6 06825 #define FTM_SYNC_SWSYNC_MASK 0x80u 06826 #define FTM_SYNC_SWSYNC_SHIFT 7 06827 /* OUTINIT Bit Fields */ 06828 #define FTM_OUTINIT_CH0OI_MASK 0x1u 06829 #define FTM_OUTINIT_CH0OI_SHIFT 0 06830 #define FTM_OUTINIT_CH1OI_MASK 0x2u 06831 #define FTM_OUTINIT_CH1OI_SHIFT 1 06832 #define FTM_OUTINIT_CH2OI_MASK 0x4u 06833 #define FTM_OUTINIT_CH2OI_SHIFT 2 06834 #define FTM_OUTINIT_CH3OI_MASK 0x8u 06835 #define FTM_OUTINIT_CH3OI_SHIFT 3 06836 #define FTM_OUTINIT_CH4OI_MASK 0x10u 06837 #define FTM_OUTINIT_CH4OI_SHIFT 4 06838 #define FTM_OUTINIT_CH5OI_MASK 0x20u 06839 #define FTM_OUTINIT_CH5OI_SHIFT 5 06840 #define FTM_OUTINIT_CH6OI_MASK 0x40u 06841 #define FTM_OUTINIT_CH6OI_SHIFT 6 06842 #define FTM_OUTINIT_CH7OI_MASK 0x80u 06843 #define FTM_OUTINIT_CH7OI_SHIFT 7 06844 /* OUTMASK Bit Fields */ 06845 #define FTM_OUTMASK_CH0OM_MASK 0x1u 06846 #define FTM_OUTMASK_CH0OM_SHIFT 0 06847 #define FTM_OUTMASK_CH1OM_MASK 0x2u 06848 #define FTM_OUTMASK_CH1OM_SHIFT 1 06849 #define FTM_OUTMASK_CH2OM_MASK 0x4u 06850 #define FTM_OUTMASK_CH2OM_SHIFT 2 06851 #define FTM_OUTMASK_CH3OM_MASK 0x8u 06852 #define FTM_OUTMASK_CH3OM_SHIFT 3 06853 #define FTM_OUTMASK_CH4OM_MASK 0x10u 06854 #define FTM_OUTMASK_CH4OM_SHIFT 4 06855 #define FTM_OUTMASK_CH5OM_MASK 0x20u 06856 #define FTM_OUTMASK_CH5OM_SHIFT 5 06857 #define FTM_OUTMASK_CH6OM_MASK 0x40u 06858 #define FTM_OUTMASK_CH6OM_SHIFT 6 06859 #define FTM_OUTMASK_CH7OM_MASK 0x80u 06860 #define FTM_OUTMASK_CH7OM_SHIFT 7 06861 /* COMBINE Bit Fields */ 06862 #define FTM_COMBINE_COMBINE0_MASK 0x1u 06863 #define FTM_COMBINE_COMBINE0_SHIFT 0 06864 #define FTM_COMBINE_COMP0_MASK 0x2u 06865 #define FTM_COMBINE_COMP0_SHIFT 1 06866 #define FTM_COMBINE_DECAPEN0_MASK 0x4u 06867 #define FTM_COMBINE_DECAPEN0_SHIFT 2 06868 #define FTM_COMBINE_DECAP0_MASK 0x8u 06869 #define FTM_COMBINE_DECAP0_SHIFT 3 06870 #define FTM_COMBINE_DTEN0_MASK 0x10u 06871 #define FTM_COMBINE_DTEN0_SHIFT 4 06872 #define FTM_COMBINE_SYNCEN0_MASK 0x20u 06873 #define FTM_COMBINE_SYNCEN0_SHIFT 5 06874 #define FTM_COMBINE_FAULTEN0_MASK 0x40u 06875 #define FTM_COMBINE_FAULTEN0_SHIFT 6 06876 #define FTM_COMBINE_COMBINE1_MASK 0x100u 06877 #define FTM_COMBINE_COMBINE1_SHIFT 8 06878 #define FTM_COMBINE_COMP1_MASK 0x200u 06879 #define FTM_COMBINE_COMP1_SHIFT 9 06880 #define FTM_COMBINE_DECAPEN1_MASK 0x400u 06881 #define FTM_COMBINE_DECAPEN1_SHIFT 10 06882 #define FTM_COMBINE_DECAP1_MASK 0x800u 06883 #define FTM_COMBINE_DECAP1_SHIFT 11 06884 #define FTM_COMBINE_DTEN1_MASK 0x1000u 06885 #define FTM_COMBINE_DTEN1_SHIFT 12 06886 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u 06887 #define FTM_COMBINE_SYNCEN1_SHIFT 13 06888 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u 06889 #define FTM_COMBINE_FAULTEN1_SHIFT 14 06890 #define FTM_COMBINE_COMBINE2_MASK 0x10000u 06891 #define FTM_COMBINE_COMBINE2_SHIFT 16 06892 #define FTM_COMBINE_COMP2_MASK 0x20000u 06893 #define FTM_COMBINE_COMP2_SHIFT 17 06894 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u 06895 #define FTM_COMBINE_DECAPEN2_SHIFT 18 06896 #define FTM_COMBINE_DECAP2_MASK 0x80000u 06897 #define FTM_COMBINE_DECAP2_SHIFT 19 06898 #define FTM_COMBINE_DTEN2_MASK 0x100000u 06899 #define FTM_COMBINE_DTEN2_SHIFT 20 06900 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u 06901 #define FTM_COMBINE_SYNCEN2_SHIFT 21 06902 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u 06903 #define FTM_COMBINE_FAULTEN2_SHIFT 22 06904 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u 06905 #define FTM_COMBINE_COMBINE3_SHIFT 24 06906 #define FTM_COMBINE_COMP3_MASK 0x2000000u 06907 #define FTM_COMBINE_COMP3_SHIFT 25 06908 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u 06909 #define FTM_COMBINE_DECAPEN3_SHIFT 26 06910 #define FTM_COMBINE_DECAP3_MASK 0x8000000u 06911 #define FTM_COMBINE_DECAP3_SHIFT 27 06912 #define FTM_COMBINE_DTEN3_MASK 0x10000000u 06913 #define FTM_COMBINE_DTEN3_SHIFT 28 06914 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u 06915 #define FTM_COMBINE_SYNCEN3_SHIFT 29 06916 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u 06917 #define FTM_COMBINE_FAULTEN3_SHIFT 30 06918 /* DEADTIME Bit Fields */ 06919 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu 06920 #define FTM_DEADTIME_DTVAL_SHIFT 0 06921 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK) 06922 #define FTM_DEADTIME_DTPS_MASK 0xC0u 06923 #define FTM_DEADTIME_DTPS_SHIFT 6 06924 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK) 06925 /* EXTTRIG Bit Fields */ 06926 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u 06927 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0 06928 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u 06929 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1 06930 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u 06931 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2 06932 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u 06933 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3 06934 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u 06935 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4 06936 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u 06937 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5 06938 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u 06939 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6 06940 #define FTM_EXTTRIG_TRIGF_MASK 0x80u 06941 #define FTM_EXTTRIG_TRIGF_SHIFT 7 06942 /* POL Bit Fields */ 06943 #define FTM_POL_POL0_MASK 0x1u 06944 #define FTM_POL_POL0_SHIFT 0 06945 #define FTM_POL_POL1_MASK 0x2u 06946 #define FTM_POL_POL1_SHIFT 1 06947 #define FTM_POL_POL2_MASK 0x4u 06948 #define FTM_POL_POL2_SHIFT 2 06949 #define FTM_POL_POL3_MASK 0x8u 06950 #define FTM_POL_POL3_SHIFT 3 06951 #define FTM_POL_POL4_MASK 0x10u 06952 #define FTM_POL_POL4_SHIFT 4 06953 #define FTM_POL_POL5_MASK 0x20u 06954 #define FTM_POL_POL5_SHIFT 5 06955 #define FTM_POL_POL6_MASK 0x40u 06956 #define FTM_POL_POL6_SHIFT 6 06957 #define FTM_POL_POL7_MASK 0x80u 06958 #define FTM_POL_POL7_SHIFT 7 06959 /* FMS Bit Fields */ 06960 #define FTM_FMS_FAULTF0_MASK 0x1u 06961 #define FTM_FMS_FAULTF0_SHIFT 0 06962 #define FTM_FMS_FAULTF1_MASK 0x2u 06963 #define FTM_FMS_FAULTF1_SHIFT 1 06964 #define FTM_FMS_FAULTF2_MASK 0x4u 06965 #define FTM_FMS_FAULTF2_SHIFT 2 06966 #define FTM_FMS_FAULTF3_MASK 0x8u 06967 #define FTM_FMS_FAULTF3_SHIFT 3 06968 #define FTM_FMS_FAULTIN_MASK 0x20u 06969 #define FTM_FMS_FAULTIN_SHIFT 5 06970 #define FTM_FMS_WPEN_MASK 0x40u 06971 #define FTM_FMS_WPEN_SHIFT 6 06972 #define FTM_FMS_FAULTF_MASK 0x80u 06973 #define FTM_FMS_FAULTF_SHIFT 7 06974 /* FILTER Bit Fields */ 06975 #define FTM_FILTER_CH0FVAL_MASK 0xFu 06976 #define FTM_FILTER_CH0FVAL_SHIFT 0 06977 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK) 06978 #define FTM_FILTER_CH1FVAL_MASK 0xF0u 06979 #define FTM_FILTER_CH1FVAL_SHIFT 4 06980 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK) 06981 #define FTM_FILTER_CH2FVAL_MASK 0xF00u 06982 #define FTM_FILTER_CH2FVAL_SHIFT 8 06983 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK) 06984 #define FTM_FILTER_CH3FVAL_MASK 0xF000u 06985 #define FTM_FILTER_CH3FVAL_SHIFT 12 06986 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK) 06987 /* FLTCTRL Bit Fields */ 06988 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u 06989 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0 06990 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u 06991 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1 06992 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u 06993 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2 06994 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u 06995 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3 06996 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u 06997 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4 06998 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u 06999 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5 07000 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u 07001 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6 07002 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u 07003 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7 07004 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u 07005 #define FTM_FLTCTRL_FFVAL_SHIFT 8 07006 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK) 07007 /* QDCTRL Bit Fields */ 07008 #define FTM_QDCTRL_QUADEN_MASK 0x1u 07009 #define FTM_QDCTRL_QUADEN_SHIFT 0 07010 #define FTM_QDCTRL_TOFDIR_MASK 0x2u 07011 #define FTM_QDCTRL_TOFDIR_SHIFT 1 07012 #define FTM_QDCTRL_QUADIR_MASK 0x4u 07013 #define FTM_QDCTRL_QUADIR_SHIFT 2 07014 #define FTM_QDCTRL_QUADMODE_MASK 0x8u 07015 #define FTM_QDCTRL_QUADMODE_SHIFT 3 07016 #define FTM_QDCTRL_PHBPOL_MASK 0x10u 07017 #define FTM_QDCTRL_PHBPOL_SHIFT 4 07018 #define FTM_QDCTRL_PHAPOL_MASK 0x20u 07019 #define FTM_QDCTRL_PHAPOL_SHIFT 5 07020 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u 07021 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6 07022 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u 07023 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7 07024 /* CONF Bit Fields */ 07025 #define FTM_CONF_NUMTOF_MASK 0x1Fu 07026 #define FTM_CONF_NUMTOF_SHIFT 0 07027 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK) 07028 #define FTM_CONF_BDMMODE_MASK 0xC0u 07029 #define FTM_CONF_BDMMODE_SHIFT 6 07030 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK) 07031 #define FTM_CONF_GTBEEN_MASK 0x200u 07032 #define FTM_CONF_GTBEEN_SHIFT 9 07033 #define FTM_CONF_GTBEOUT_MASK 0x400u 07034 #define FTM_CONF_GTBEOUT_SHIFT 10 07035 /* FLTPOL Bit Fields */ 07036 #define FTM_FLTPOL_FLT0POL_MASK 0x1u 07037 #define FTM_FLTPOL_FLT0POL_SHIFT 0 07038 #define FTM_FLTPOL_FLT1POL_MASK 0x2u 07039 #define FTM_FLTPOL_FLT1POL_SHIFT 1 07040 #define FTM_FLTPOL_FLT2POL_MASK 0x4u 07041 #define FTM_FLTPOL_FLT2POL_SHIFT 2 07042 #define FTM_FLTPOL_FLT3POL_MASK 0x8u 07043 #define FTM_FLTPOL_FLT3POL_SHIFT 3 07044 /* SYNCONF Bit Fields */ 07045 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u 07046 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0 07047 #define FTM_SYNCONF_CNTINC_MASK 0x4u 07048 #define FTM_SYNCONF_CNTINC_SHIFT 2 07049 #define FTM_SYNCONF_INVC_MASK 0x10u 07050 #define FTM_SYNCONF_INVC_SHIFT 4 07051 #define FTM_SYNCONF_SWOC_MASK 0x20u 07052 #define FTM_SYNCONF_SWOC_SHIFT 5 07053 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u 07054 #define FTM_SYNCONF_SYNCMODE_SHIFT 7 07055 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u 07056 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8 07057 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u 07058 #define FTM_SYNCONF_SWWRBUF_SHIFT 9 07059 #define FTM_SYNCONF_SWOM_MASK 0x400u 07060 #define FTM_SYNCONF_SWOM_SHIFT 10 07061 #define FTM_SYNCONF_SWINVC_MASK 0x800u 07062 #define FTM_SYNCONF_SWINVC_SHIFT 11 07063 #define FTM_SYNCONF_SWSOC_MASK 0x1000u 07064 #define FTM_SYNCONF_SWSOC_SHIFT 12 07065 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u 07066 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16 07067 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u 07068 #define FTM_SYNCONF_HWWRBUF_SHIFT 17 07069 #define FTM_SYNCONF_HWOM_MASK 0x40000u 07070 #define FTM_SYNCONF_HWOM_SHIFT 18 07071 #define FTM_SYNCONF_HWINVC_MASK 0x80000u 07072 #define FTM_SYNCONF_HWINVC_SHIFT 19 07073 #define FTM_SYNCONF_HWSOC_MASK 0x100000u 07074 #define FTM_SYNCONF_HWSOC_SHIFT 20 07075 /* INVCTRL Bit Fields */ 07076 #define FTM_INVCTRL_INV0EN_MASK 0x1u 07077 #define FTM_INVCTRL_INV0EN_SHIFT 0 07078 #define FTM_INVCTRL_INV1EN_MASK 0x2u 07079 #define FTM_INVCTRL_INV1EN_SHIFT 1 07080 #define FTM_INVCTRL_INV2EN_MASK 0x4u 07081 #define FTM_INVCTRL_INV2EN_SHIFT 2 07082 #define FTM_INVCTRL_INV3EN_MASK 0x8u 07083 #define FTM_INVCTRL_INV3EN_SHIFT 3 07084 /* SWOCTRL Bit Fields */ 07085 #define FTM_SWOCTRL_CH0OC_MASK 0x1u 07086 #define FTM_SWOCTRL_CH0OC_SHIFT 0 07087 #define FTM_SWOCTRL_CH1OC_MASK 0x2u 07088 #define FTM_SWOCTRL_CH1OC_SHIFT 1 07089 #define FTM_SWOCTRL_CH2OC_MASK 0x4u 07090 #define FTM_SWOCTRL_CH2OC_SHIFT 2 07091 #define FTM_SWOCTRL_CH3OC_MASK 0x8u 07092 #define FTM_SWOCTRL_CH3OC_SHIFT 3 07093 #define FTM_SWOCTRL_CH4OC_MASK 0x10u 07094 #define FTM_SWOCTRL_CH4OC_SHIFT 4 07095 #define FTM_SWOCTRL_CH5OC_MASK 0x20u 07096 #define FTM_SWOCTRL_CH5OC_SHIFT 5 07097 #define FTM_SWOCTRL_CH6OC_MASK 0x40u 07098 #define FTM_SWOCTRL_CH6OC_SHIFT 6 07099 #define FTM_SWOCTRL_CH7OC_MASK 0x80u 07100 #define FTM_SWOCTRL_CH7OC_SHIFT 7 07101 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u 07102 #define FTM_SWOCTRL_CH0OCV_SHIFT 8 07103 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u 07104 #define FTM_SWOCTRL_CH1OCV_SHIFT 9 07105 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u 07106 #define FTM_SWOCTRL_CH2OCV_SHIFT 10 07107 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u 07108 #define FTM_SWOCTRL_CH3OCV_SHIFT 11 07109 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u 07110 #define FTM_SWOCTRL_CH4OCV_SHIFT 12 07111 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u 07112 #define FTM_SWOCTRL_CH5OCV_SHIFT 13 07113 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u 07114 #define FTM_SWOCTRL_CH6OCV_SHIFT 14 07115 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u 07116 #define FTM_SWOCTRL_CH7OCV_SHIFT 15 07117 /* PWMLOAD Bit Fields */ 07118 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u 07119 #define FTM_PWMLOAD_CH0SEL_SHIFT 0 07120 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u 07121 #define FTM_PWMLOAD_CH1SEL_SHIFT 1 07122 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u 07123 #define FTM_PWMLOAD_CH2SEL_SHIFT 2 07124 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u 07125 #define FTM_PWMLOAD_CH3SEL_SHIFT 3 07126 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u 07127 #define FTM_PWMLOAD_CH4SEL_SHIFT 4 07128 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u 07129 #define FTM_PWMLOAD_CH5SEL_SHIFT 5 07130 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u 07131 #define FTM_PWMLOAD_CH6SEL_SHIFT 6 07132 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u 07133 #define FTM_PWMLOAD_CH7SEL_SHIFT 7 07134 #define FTM_PWMLOAD_LDOK_MASK 0x200u 07135 #define FTM_PWMLOAD_LDOK_SHIFT 9 07136 07137 /*! 07138 * @} 07139 */ /* end of group FTM_Register_Masks */ 07140 07141 07142 /* FTM - Peripheral instance base addresses */ 07143 /** Peripheral FTM0 base address */ 07144 #define FTM0_BASE (0x40038000u) 07145 /** Peripheral FTM0 base pointer */ 07146 #define FTM0 ((FTM_Type *)FTM0_BASE) 07147 #define FTM0_BASE_PTR (FTM0) 07148 /** Peripheral FTM1 base address */ 07149 #define FTM1_BASE (0x40039000u) 07150 /** Peripheral FTM1 base pointer */ 07151 #define FTM1 ((FTM_Type *)FTM1_BASE) 07152 #define FTM1_BASE_PTR (FTM1) 07153 /** Peripheral FTM2 base address */ 07154 #define FTM2_BASE (0x4003A000u) 07155 /** Peripheral FTM2 base pointer */ 07156 #define FTM2 ((FTM_Type *)FTM2_BASE) 07157 #define FTM2_BASE_PTR (FTM2) 07158 /** Peripheral FTM3 base address */ 07159 #define FTM3_BASE (0x400B9000u) 07160 /** Peripheral FTM3 base pointer */ 07161 #define FTM3 ((FTM_Type *)FTM3_BASE) 07162 #define FTM3_BASE_PTR (FTM3) 07163 /** Array initializer of FTM peripheral base addresses */ 07164 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE } 07165 /** Array initializer of FTM peripheral base pointers */ 07166 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 } 07167 /** Interrupt vectors for the FTM peripheral type */ 07168 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn } 07169 07170 /* ---------------------------------------------------------------------------- 07171 -- FTM - Register accessor macros 07172 ---------------------------------------------------------------------------- */ 07173 07174 /*! 07175 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros 07176 * @{ 07177 */ 07178 07179 07180 /* FTM - Register instance definitions */ 07181 /* FTM0 */ 07182 #define FTM0_SC FTM_SC_REG(FTM0) 07183 #define FTM0_CNT FTM_CNT_REG(FTM0) 07184 #define FTM0_MOD FTM_MOD_REG(FTM0) 07185 #define FTM0_C0SC FTM_CnSC_REG(FTM0,0) 07186 #define FTM0_C0V FTM_CnV_REG(FTM0,0) 07187 #define FTM0_C1SC FTM_CnSC_REG(FTM0,1) 07188 #define FTM0_C1V FTM_CnV_REG(FTM0,1) 07189 #define FTM0_C2SC FTM_CnSC_REG(FTM0,2) 07190 #define FTM0_C2V FTM_CnV_REG(FTM0,2) 07191 #define FTM0_C3SC FTM_CnSC_REG(FTM0,3) 07192 #define FTM0_C3V FTM_CnV_REG(FTM0,3) 07193 #define FTM0_C4SC FTM_CnSC_REG(FTM0,4) 07194 #define FTM0_C4V FTM_CnV_REG(FTM0,4) 07195 #define FTM0_C5SC FTM_CnSC_REG(FTM0,5) 07196 #define FTM0_C5V FTM_CnV_REG(FTM0,5) 07197 #define FTM0_C6SC FTM_CnSC_REG(FTM0,6) 07198 #define FTM0_C6V FTM_CnV_REG(FTM0,6) 07199 #define FTM0_C7SC FTM_CnSC_REG(FTM0,7) 07200 #define FTM0_C7V FTM_CnV_REG(FTM0,7) 07201 #define FTM0_CNTIN FTM_CNTIN_REG(FTM0) 07202 #define FTM0_STATUS FTM_STATUS_REG(FTM0) 07203 #define FTM0_MODE FTM_MODE_REG(FTM0) 07204 #define FTM0_SYNC FTM_SYNC_REG(FTM0) 07205 #define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0) 07206 #define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0) 07207 #define FTM0_COMBINE FTM_COMBINE_REG(FTM0) 07208 #define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0) 07209 #define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0) 07210 #define FTM0_POL FTM_POL_REG(FTM0) 07211 #define FTM0_FMS FTM_FMS_REG(FTM0) 07212 #define FTM0_FILTER FTM_FILTER_REG(FTM0) 07213 #define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0) 07214 #define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0) 07215 #define FTM0_CONF FTM_CONF_REG(FTM0) 07216 #define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0) 07217 #define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0) 07218 #define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0) 07219 #define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0) 07220 #define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0) 07221 /* FTM1 */ 07222 #define FTM1_SC FTM_SC_REG(FTM1) 07223 #define FTM1_CNT FTM_CNT_REG(FTM1) 07224 #define FTM1_MOD FTM_MOD_REG(FTM1) 07225 #define FTM1_C0SC FTM_CnSC_REG(FTM1,0) 07226 #define FTM1_C0V FTM_CnV_REG(FTM1,0) 07227 #define FTM1_C1SC FTM_CnSC_REG(FTM1,1) 07228 #define FTM1_C1V FTM_CnV_REG(FTM1,1) 07229 #define FTM1_CNTIN FTM_CNTIN_REG(FTM1) 07230 #define FTM1_STATUS FTM_STATUS_REG(FTM1) 07231 #define FTM1_MODE FTM_MODE_REG(FTM1) 07232 #define FTM1_SYNC FTM_SYNC_REG(FTM1) 07233 #define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1) 07234 #define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1) 07235 #define FTM1_COMBINE FTM_COMBINE_REG(FTM1) 07236 #define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1) 07237 #define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1) 07238 #define FTM1_POL FTM_POL_REG(FTM1) 07239 #define FTM1_FMS FTM_FMS_REG(FTM1) 07240 #define FTM1_FILTER FTM_FILTER_REG(FTM1) 07241 #define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1) 07242 #define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1) 07243 #define FTM1_CONF FTM_CONF_REG(FTM1) 07244 #define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1) 07245 #define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1) 07246 #define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1) 07247 #define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1) 07248 #define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1) 07249 /* FTM2 */ 07250 #define FTM2_SC FTM_SC_REG(FTM2) 07251 #define FTM2_CNT FTM_CNT_REG(FTM2) 07252 #define FTM2_MOD FTM_MOD_REG(FTM2) 07253 #define FTM2_C0SC FTM_CnSC_REG(FTM2,0) 07254 #define FTM2_C0V FTM_CnV_REG(FTM2,0) 07255 #define FTM2_C1SC FTM_CnSC_REG(FTM2,1) 07256 #define FTM2_C1V FTM_CnV_REG(FTM2,1) 07257 #define FTM2_CNTIN FTM_CNTIN_REG(FTM2) 07258 #define FTM2_STATUS FTM_STATUS_REG(FTM2) 07259 #define FTM2_MODE FTM_MODE_REG(FTM2) 07260 #define FTM2_SYNC FTM_SYNC_REG(FTM2) 07261 #define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2) 07262 #define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2) 07263 #define FTM2_COMBINE FTM_COMBINE_REG(FTM2) 07264 #define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2) 07265 #define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2) 07266 #define FTM2_POL FTM_POL_REG(FTM2) 07267 #define FTM2_FMS FTM_FMS_REG(FTM2) 07268 #define FTM2_FILTER FTM_FILTER_REG(FTM2) 07269 #define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2) 07270 #define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2) 07271 #define FTM2_CONF FTM_CONF_REG(FTM2) 07272 #define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2) 07273 #define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2) 07274 #define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2) 07275 #define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2) 07276 #define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2) 07277 /* FTM3 */ 07278 #define FTM3_SC FTM_SC_REG(FTM3) 07279 #define FTM3_CNT FTM_CNT_REG(FTM3) 07280 #define FTM3_MOD FTM_MOD_REG(FTM3) 07281 #define FTM3_C0SC FTM_CnSC_REG(FTM3,0) 07282 #define FTM3_C0V FTM_CnV_REG(FTM3,0) 07283 #define FTM3_C1SC FTM_CnSC_REG(FTM3,1) 07284 #define FTM3_C1V FTM_CnV_REG(FTM3,1) 07285 #define FTM3_C2SC FTM_CnSC_REG(FTM3,2) 07286 #define FTM3_C2V FTM_CnV_REG(FTM3,2) 07287 #define FTM3_C3SC FTM_CnSC_REG(FTM3,3) 07288 #define FTM3_C3V FTM_CnV_REG(FTM3,3) 07289 #define FTM3_C4SC FTM_CnSC_REG(FTM3,4) 07290 #define FTM3_C4V FTM_CnV_REG(FTM3,4) 07291 #define FTM3_C5SC FTM_CnSC_REG(FTM3,5) 07292 #define FTM3_C5V FTM_CnV_REG(FTM3,5) 07293 #define FTM3_C6SC FTM_CnSC_REG(FTM3,6) 07294 #define FTM3_C6V FTM_CnV_REG(FTM3,6) 07295 #define FTM3_C7SC FTM_CnSC_REG(FTM3,7) 07296 #define FTM3_C7V FTM_CnV_REG(FTM3,7) 07297 #define FTM3_CNTIN FTM_CNTIN_REG(FTM3) 07298 #define FTM3_STATUS FTM_STATUS_REG(FTM3) 07299 #define FTM3_MODE FTM_MODE_REG(FTM3) 07300 #define FTM3_SYNC FTM_SYNC_REG(FTM3) 07301 #define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3) 07302 #define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3) 07303 #define FTM3_COMBINE FTM_COMBINE_REG(FTM3) 07304 #define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3) 07305 #define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3) 07306 #define FTM3_POL FTM_POL_REG(FTM3) 07307 #define FTM3_FMS FTM_FMS_REG(FTM3) 07308 #define FTM3_FILTER FTM_FILTER_REG(FTM3) 07309 #define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3) 07310 #define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3) 07311 #define FTM3_CONF FTM_CONF_REG(FTM3) 07312 #define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3) 07313 #define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3) 07314 #define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3) 07315 #define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3) 07316 #define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3) 07317 07318 /* FTM - Register array accessors */ 07319 #define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index) 07320 #define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index) 07321 #define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index) 07322 #define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index) 07323 #define FTM0_CnV(index) FTM_CnV_REG(FTM0,index) 07324 #define FTM1_CnV(index) FTM_CnV_REG(FTM1,index) 07325 #define FTM2_CnV(index) FTM_CnV_REG(FTM2,index) 07326 #define FTM3_CnV(index) FTM_CnV_REG(FTM3,index) 07327 07328 /*! 07329 * @} 07330 */ /* end of group FTM_Register_Accessor_Macros */ 07331 07332 07333 /*! 07334 * @} 07335 */ /* end of group FTM_Peripheral_Access_Layer */ 07336 07337 07338 /* ---------------------------------------------------------------------------- 07339 -- GPIO Peripheral Access Layer 07340 ---------------------------------------------------------------------------- */ 07341 07342 /*! 07343 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 07344 * @{ 07345 */ 07346 07347 /** GPIO - Register Layout Typedef */ 07348 typedef struct { 07349 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 07350 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 07351 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 07352 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 07353 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 07354 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 07355 } GPIO_Type, *GPIO_MemMapPtr; 07356 07357 /* ---------------------------------------------------------------------------- 07358 -- GPIO - Register accessor macros 07359 ---------------------------------------------------------------------------- */ 07360 07361 /*! 07362 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros 07363 * @{ 07364 */ 07365 07366 07367 /* GPIO - Register accessors */ 07368 #define GPIO_PDOR_REG(base) ((base)->PDOR) 07369 #define GPIO_PSOR_REG(base) ((base)->PSOR) 07370 #define GPIO_PCOR_REG(base) ((base)->PCOR) 07371 #define GPIO_PTOR_REG(base) ((base)->PTOR) 07372 #define GPIO_PDIR_REG(base) ((base)->PDIR) 07373 #define GPIO_PDDR_REG(base) ((base)->PDDR) 07374 07375 /*! 07376 * @} 07377 */ /* end of group GPIO_Register_Accessor_Macros */ 07378 07379 07380 /* ---------------------------------------------------------------------------- 07381 -- GPIO Register Masks 07382 ---------------------------------------------------------------------------- */ 07383 07384 /*! 07385 * @addtogroup GPIO_Register_Masks GPIO Register Masks 07386 * @{ 07387 */ 07388 07389 /* PDOR Bit Fields */ 07390 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu 07391 #define GPIO_PDOR_PDO_SHIFT 0 07392 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK) 07393 /* PSOR Bit Fields */ 07394 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu 07395 #define GPIO_PSOR_PTSO_SHIFT 0 07396 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK) 07397 /* PCOR Bit Fields */ 07398 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu 07399 #define GPIO_PCOR_PTCO_SHIFT 0 07400 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK) 07401 /* PTOR Bit Fields */ 07402 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu 07403 #define GPIO_PTOR_PTTO_SHIFT 0 07404 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK) 07405 /* PDIR Bit Fields */ 07406 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu 07407 #define GPIO_PDIR_PDI_SHIFT 0 07408 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK) 07409 /* PDDR Bit Fields */ 07410 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu 07411 #define GPIO_PDDR_PDD_SHIFT 0 07412 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK) 07413 07414 /*! 07415 * @} 07416 */ /* end of group GPIO_Register_Masks */ 07417 07418 07419 /* GPIO - Peripheral instance base addresses */ 07420 /** Peripheral PTA base address */ 07421 #define PTA_BASE (0x400FF000u) 07422 /** Peripheral PTA base pointer */ 07423 #define PTA ((GPIO_Type *)PTA_BASE) 07424 #define PTA_BASE_PTR (PTA) 07425 /** Peripheral PTB base address */ 07426 #define PTB_BASE (0x400FF040u) 07427 /** Peripheral PTB base pointer */ 07428 #define PTB ((GPIO_Type *)PTB_BASE) 07429 #define PTB_BASE_PTR (PTB) 07430 /** Peripheral PTC base address */ 07431 #define PTC_BASE (0x400FF080u) 07432 /** Peripheral PTC base pointer */ 07433 #define PTC ((GPIO_Type *)PTC_BASE) 07434 #define PTC_BASE_PTR (PTC) 07435 /** Peripheral PTD base address */ 07436 #define PTD_BASE (0x400FF0C0u) 07437 /** Peripheral PTD base pointer */ 07438 #define PTD ((GPIO_Type *)PTD_BASE) 07439 #define PTD_BASE_PTR (PTD) 07440 /** Peripheral PTE base address */ 07441 #define PTE_BASE (0x400FF100u) 07442 /** Peripheral PTE base pointer */ 07443 #define PTE ((GPIO_Type *)PTE_BASE) 07444 #define PTE_BASE_PTR (PTE) 07445 /** Array initializer of GPIO peripheral base addresses */ 07446 #define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE } 07447 /** Array initializer of GPIO peripheral base pointers */ 07448 #define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE } 07449 07450 /* ---------------------------------------------------------------------------- 07451 -- GPIO - Register accessor macros 07452 ---------------------------------------------------------------------------- */ 07453 07454 /*! 07455 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros 07456 * @{ 07457 */ 07458 07459 07460 /* GPIO - Register instance definitions */ 07461 /* PTA */ 07462 #define GPIOA_PDOR GPIO_PDOR_REG(PTA) 07463 #define GPIOA_PSOR GPIO_PSOR_REG(PTA) 07464 #define GPIOA_PCOR GPIO_PCOR_REG(PTA) 07465 #define GPIOA_PTOR GPIO_PTOR_REG(PTA) 07466 #define GPIOA_PDIR GPIO_PDIR_REG(PTA) 07467 #define GPIOA_PDDR GPIO_PDDR_REG(PTA) 07468 /* PTB */ 07469 #define GPIOB_PDOR GPIO_PDOR_REG(PTB) 07470 #define GPIOB_PSOR GPIO_PSOR_REG(PTB) 07471 #define GPIOB_PCOR GPIO_PCOR_REG(PTB) 07472 #define GPIOB_PTOR GPIO_PTOR_REG(PTB) 07473 #define GPIOB_PDIR GPIO_PDIR_REG(PTB) 07474 #define GPIOB_PDDR GPIO_PDDR_REG(PTB) 07475 /* PTC */ 07476 #define GPIOC_PDOR GPIO_PDOR_REG(PTC) 07477 #define GPIOC_PSOR GPIO_PSOR_REG(PTC) 07478 #define GPIOC_PCOR GPIO_PCOR_REG(PTC) 07479 #define GPIOC_PTOR GPIO_PTOR_REG(PTC) 07480 #define GPIOC_PDIR GPIO_PDIR_REG(PTC) 07481 #define GPIOC_PDDR GPIO_PDDR_REG(PTC) 07482 /* PTD */ 07483 #define GPIOD_PDOR GPIO_PDOR_REG(PTD) 07484 #define GPIOD_PSOR GPIO_PSOR_REG(PTD) 07485 #define GPIOD_PCOR GPIO_PCOR_REG(PTD) 07486 #define GPIOD_PTOR GPIO_PTOR_REG(PTD) 07487 #define GPIOD_PDIR GPIO_PDIR_REG(PTD) 07488 #define GPIOD_PDDR GPIO_PDDR_REG(PTD) 07489 /* PTE */ 07490 #define GPIOE_PDOR GPIO_PDOR_REG(PTE) 07491 #define GPIOE_PSOR GPIO_PSOR_REG(PTE) 07492 #define GPIOE_PCOR GPIO_PCOR_REG(PTE) 07493 #define GPIOE_PTOR GPIO_PTOR_REG(PTE) 07494 #define GPIOE_PDIR GPIO_PDIR_REG(PTE) 07495 #define GPIOE_PDDR GPIO_PDDR_REG(PTE) 07496 07497 /*! 07498 * @} 07499 */ /* end of group GPIO_Register_Accessor_Macros */ 07500 07501 07502 /*! 07503 * @} 07504 */ /* end of group GPIO_Peripheral_Access_Layer */ 07505 07506 07507 /* ---------------------------------------------------------------------------- 07508 -- I2C Peripheral Access Layer 07509 ---------------------------------------------------------------------------- */ 07510 07511 /*! 07512 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 07513 * @{ 07514 */ 07515 07516 /** I2C - Register Layout Typedef */ 07517 typedef struct { 07518 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ 07519 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ 07520 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ 07521 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ 07522 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ 07523 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ 07524 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ 07525 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ 07526 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ 07527 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ 07528 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ 07529 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ 07530 } I2C_Type, *I2C_MemMapPtr; 07531 07532 /* ---------------------------------------------------------------------------- 07533 -- I2C - Register accessor macros 07534 ---------------------------------------------------------------------------- */ 07535 07536 /*! 07537 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros 07538 * @{ 07539 */ 07540 07541 07542 /* I2C - Register accessors */ 07543 #define I2C_A1_REG(base) ((base)->A1) 07544 #define I2C_F_REG(base) ((base)->F) 07545 #define I2C_C1_REG(base) ((base)->C1) 07546 #define I2C_S_REG(base) ((base)->S) 07547 #define I2C_D_REG(base) ((base)->D) 07548 #define I2C_C2_REG(base) ((base)->C2) 07549 #define I2C_FLT_REG(base) ((base)->FLT) 07550 #define I2C_RA_REG(base) ((base)->RA) 07551 #define I2C_SMB_REG(base) ((base)->SMB) 07552 #define I2C_A2_REG(base) ((base)->A2) 07553 #define I2C_SLTH_REG(base) ((base)->SLTH) 07554 #define I2C_SLTL_REG(base) ((base)->SLTL) 07555 07556 /*! 07557 * @} 07558 */ /* end of group I2C_Register_Accessor_Macros */ 07559 07560 07561 /* ---------------------------------------------------------------------------- 07562 -- I2C Register Masks 07563 ---------------------------------------------------------------------------- */ 07564 07565 /*! 07566 * @addtogroup I2C_Register_Masks I2C Register Masks 07567 * @{ 07568 */ 07569 07570 /* A1 Bit Fields */ 07571 #define I2C_A1_AD_MASK 0xFEu 07572 #define I2C_A1_AD_SHIFT 1 07573 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK) 07574 /* F Bit Fields */ 07575 #define I2C_F_ICR_MASK 0x3Fu 07576 #define I2C_F_ICR_SHIFT 0 07577 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK) 07578 #define I2C_F_MULT_MASK 0xC0u 07579 #define I2C_F_MULT_SHIFT 6 07580 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK) 07581 /* C1 Bit Fields */ 07582 #define I2C_C1_DMAEN_MASK 0x1u 07583 #define I2C_C1_DMAEN_SHIFT 0 07584 #define I2C_C1_WUEN_MASK 0x2u 07585 #define I2C_C1_WUEN_SHIFT 1 07586 #define I2C_C1_RSTA_MASK 0x4u 07587 #define I2C_C1_RSTA_SHIFT 2 07588 #define I2C_C1_TXAK_MASK 0x8u 07589 #define I2C_C1_TXAK_SHIFT 3 07590 #define I2C_C1_TX_MASK 0x10u 07591 #define I2C_C1_TX_SHIFT 4 07592 #define I2C_C1_MST_MASK 0x20u 07593 #define I2C_C1_MST_SHIFT 5 07594 #define I2C_C1_IICIE_MASK 0x40u 07595 #define I2C_C1_IICIE_SHIFT 6 07596 #define I2C_C1_IICEN_MASK 0x80u 07597 #define I2C_C1_IICEN_SHIFT 7 07598 /* S Bit Fields */ 07599 #define I2C_S_RXAK_MASK 0x1u 07600 #define I2C_S_RXAK_SHIFT 0 07601 #define I2C_S_IICIF_MASK 0x2u 07602 #define I2C_S_IICIF_SHIFT 1 07603 #define I2C_S_SRW_MASK 0x4u 07604 #define I2C_S_SRW_SHIFT 2 07605 #define I2C_S_RAM_MASK 0x8u 07606 #define I2C_S_RAM_SHIFT 3 07607 #define I2C_S_ARBL_MASK 0x10u 07608 #define I2C_S_ARBL_SHIFT 4 07609 #define I2C_S_BUSY_MASK 0x20u 07610 #define I2C_S_BUSY_SHIFT 5 07611 #define I2C_S_IAAS_MASK 0x40u 07612 #define I2C_S_IAAS_SHIFT 6 07613 #define I2C_S_TCF_MASK 0x80u 07614 #define I2C_S_TCF_SHIFT 7 07615 /* D Bit Fields */ 07616 #define I2C_D_DATA_MASK 0xFFu 07617 #define I2C_D_DATA_SHIFT 0 07618 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK) 07619 /* C2 Bit Fields */ 07620 #define I2C_C2_AD_MASK 0x7u 07621 #define I2C_C2_AD_SHIFT 0 07622 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK) 07623 #define I2C_C2_RMEN_MASK 0x8u 07624 #define I2C_C2_RMEN_SHIFT 3 07625 #define I2C_C2_SBRC_MASK 0x10u 07626 #define I2C_C2_SBRC_SHIFT 4 07627 #define I2C_C2_HDRS_MASK 0x20u 07628 #define I2C_C2_HDRS_SHIFT 5 07629 #define I2C_C2_ADEXT_MASK 0x40u 07630 #define I2C_C2_ADEXT_SHIFT 6 07631 #define I2C_C2_GCAEN_MASK 0x80u 07632 #define I2C_C2_GCAEN_SHIFT 7 07633 /* FLT Bit Fields */ 07634 #define I2C_FLT_FLT_MASK 0xFu 07635 #define I2C_FLT_FLT_SHIFT 0 07636 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK) 07637 #define I2C_FLT_STARTF_MASK 0x10u 07638 #define I2C_FLT_STARTF_SHIFT 4 07639 #define I2C_FLT_SSIE_MASK 0x20u 07640 #define I2C_FLT_SSIE_SHIFT 5 07641 #define I2C_FLT_STOPF_MASK 0x40u 07642 #define I2C_FLT_STOPF_SHIFT 6 07643 #define I2C_FLT_SHEN_MASK 0x80u 07644 #define I2C_FLT_SHEN_SHIFT 7 07645 /* RA Bit Fields */ 07646 #define I2C_RA_RAD_MASK 0xFEu 07647 #define I2C_RA_RAD_SHIFT 1 07648 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK) 07649 /* SMB Bit Fields */ 07650 #define I2C_SMB_SHTF2IE_MASK 0x1u 07651 #define I2C_SMB_SHTF2IE_SHIFT 0 07652 #define I2C_SMB_SHTF2_MASK 0x2u 07653 #define I2C_SMB_SHTF2_SHIFT 1 07654 #define I2C_SMB_SHTF1_MASK 0x4u 07655 #define I2C_SMB_SHTF1_SHIFT 2 07656 #define I2C_SMB_SLTF_MASK 0x8u 07657 #define I2C_SMB_SLTF_SHIFT 3 07658 #define I2C_SMB_TCKSEL_MASK 0x10u 07659 #define I2C_SMB_TCKSEL_SHIFT 4 07660 #define I2C_SMB_SIICAEN_MASK 0x20u 07661 #define I2C_SMB_SIICAEN_SHIFT 5 07662 #define I2C_SMB_ALERTEN_MASK 0x40u 07663 #define I2C_SMB_ALERTEN_SHIFT 6 07664 #define I2C_SMB_FACK_MASK 0x80u 07665 #define I2C_SMB_FACK_SHIFT 7 07666 /* A2 Bit Fields */ 07667 #define I2C_A2_SAD_MASK 0xFEu 07668 #define I2C_A2_SAD_SHIFT 1 07669 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK) 07670 /* SLTH Bit Fields */ 07671 #define I2C_SLTH_SSLT_MASK 0xFFu 07672 #define I2C_SLTH_SSLT_SHIFT 0 07673 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK) 07674 /* SLTL Bit Fields */ 07675 #define I2C_SLTL_SSLT_MASK 0xFFu 07676 #define I2C_SLTL_SSLT_SHIFT 0 07677 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK) 07678 07679 /*! 07680 * @} 07681 */ /* end of group I2C_Register_Masks */ 07682 07683 07684 /* I2C - Peripheral instance base addresses */ 07685 /** Peripheral I2C0 base address */ 07686 #define I2C0_BASE (0x40066000u) 07687 /** Peripheral I2C0 base pointer */ 07688 #define I2C0 ((I2C_Type *)I2C0_BASE) 07689 #define I2C0_BASE_PTR (I2C0) 07690 /** Peripheral I2C1 base address */ 07691 #define I2C1_BASE (0x40067000u) 07692 /** Peripheral I2C1 base pointer */ 07693 #define I2C1 ((I2C_Type *)I2C1_BASE) 07694 #define I2C1_BASE_PTR (I2C1) 07695 /** Peripheral I2C2 base address */ 07696 #define I2C2_BASE (0x400E6000u) 07697 /** Peripheral I2C2 base pointer */ 07698 #define I2C2 ((I2C_Type *)I2C2_BASE) 07699 #define I2C2_BASE_PTR (I2C2) 07700 /** Array initializer of I2C peripheral base addresses */ 07701 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE } 07702 /** Array initializer of I2C peripheral base pointers */ 07703 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2 } 07704 /** Interrupt vectors for the I2C peripheral type */ 07705 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn } 07706 07707 /* ---------------------------------------------------------------------------- 07708 -- I2C - Register accessor macros 07709 ---------------------------------------------------------------------------- */ 07710 07711 /*! 07712 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros 07713 * @{ 07714 */ 07715 07716 07717 /* I2C - Register instance definitions */ 07718 /* I2C0 */ 07719 #define I2C0_A1 I2C_A1_REG(I2C0) 07720 #define I2C0_F I2C_F_REG(I2C0) 07721 #define I2C0_C1 I2C_C1_REG(I2C0) 07722 #define I2C0_S I2C_S_REG(I2C0) 07723 #define I2C0_D I2C_D_REG(I2C0) 07724 #define I2C0_C2 I2C_C2_REG(I2C0) 07725 #define I2C0_FLT I2C_FLT_REG(I2C0) 07726 #define I2C0_RA I2C_RA_REG(I2C0) 07727 #define I2C0_SMB I2C_SMB_REG(I2C0) 07728 #define I2C0_A2 I2C_A2_REG(I2C0) 07729 #define I2C0_SLTH I2C_SLTH_REG(I2C0) 07730 #define I2C0_SLTL I2C_SLTL_REG(I2C0) 07731 /* I2C1 */ 07732 #define I2C1_A1 I2C_A1_REG(I2C1) 07733 #define I2C1_F I2C_F_REG(I2C1) 07734 #define I2C1_C1 I2C_C1_REG(I2C1) 07735 #define I2C1_S I2C_S_REG(I2C1) 07736 #define I2C1_D I2C_D_REG(I2C1) 07737 #define I2C1_C2 I2C_C2_REG(I2C1) 07738 #define I2C1_FLT I2C_FLT_REG(I2C1) 07739 #define I2C1_RA I2C_RA_REG(I2C1) 07740 #define I2C1_SMB I2C_SMB_REG(I2C1) 07741 #define I2C1_A2 I2C_A2_REG(I2C1) 07742 #define I2C1_SLTH I2C_SLTH_REG(I2C1) 07743 #define I2C1_SLTL I2C_SLTL_REG(I2C1) 07744 /* I2C2 */ 07745 #define I2C2_A1 I2C_A1_REG(I2C2) 07746 #define I2C2_F I2C_F_REG(I2C2) 07747 #define I2C2_C1 I2C_C1_REG(I2C2) 07748 #define I2C2_S I2C_S_REG(I2C2) 07749 #define I2C2_D I2C_D_REG(I2C2) 07750 #define I2C2_C2 I2C_C2_REG(I2C2) 07751 #define I2C2_FLT I2C_FLT_REG(I2C2) 07752 #define I2C2_RA I2C_RA_REG(I2C2) 07753 #define I2C2_SMB I2C_SMB_REG(I2C2) 07754 #define I2C2_A2 I2C_A2_REG(I2C2) 07755 #define I2C2_SLTH I2C_SLTH_REG(I2C2) 07756 #define I2C2_SLTL I2C_SLTL_REG(I2C2) 07757 07758 /*! 07759 * @} 07760 */ /* end of group I2C_Register_Accessor_Macros */ 07761 07762 07763 /*! 07764 * @} 07765 */ /* end of group I2C_Peripheral_Access_Layer */ 07766 07767 07768 /* ---------------------------------------------------------------------------- 07769 -- I2S Peripheral Access Layer 07770 ---------------------------------------------------------------------------- */ 07771 07772 /*! 07773 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer 07774 * @{ 07775 */ 07776 07777 /** I2S - Register Layout Typedef */ 07778 typedef struct { 07779 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ 07780 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ 07781 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ 07782 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ 07783 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ 07784 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ 07785 uint8_t RESERVED_0[8]; 07786 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ 07787 uint8_t RESERVED_1[24]; 07788 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ 07789 uint8_t RESERVED_2[24]; 07790 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ 07791 uint8_t RESERVED_3[28]; 07792 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ 07793 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ 07794 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ 07795 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ 07796 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ 07797 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ 07798 uint8_t RESERVED_4[8]; 07799 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ 07800 uint8_t RESERVED_5[24]; 07801 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ 07802 uint8_t RESERVED_6[24]; 07803 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ 07804 uint8_t RESERVED_7[28]; 07805 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */ 07806 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */ 07807 } I2S_Type, *I2S_MemMapPtr; 07808 07809 /* ---------------------------------------------------------------------------- 07810 -- I2S - Register accessor macros 07811 ---------------------------------------------------------------------------- */ 07812 07813 /*! 07814 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros 07815 * @{ 07816 */ 07817 07818 07819 /* I2S - Register accessors */ 07820 #define I2S_TCSR_REG(base) ((base)->TCSR) 07821 #define I2S_TCR1_REG(base) ((base)->TCR1) 07822 #define I2S_TCR2_REG(base) ((base)->TCR2) 07823 #define I2S_TCR3_REG(base) ((base)->TCR3) 07824 #define I2S_TCR4_REG(base) ((base)->TCR4) 07825 #define I2S_TCR5_REG(base) ((base)->TCR5) 07826 #define I2S_TDR_REG(base,index) ((base)->TDR[index]) 07827 #define I2S_TFR_REG(base,index) ((base)->TFR[index]) 07828 #define I2S_TMR_REG(base) ((base)->TMR) 07829 #define I2S_RCSR_REG(base) ((base)->RCSR) 07830 #define I2S_RCR1_REG(base) ((base)->RCR1) 07831 #define I2S_RCR2_REG(base) ((base)->RCR2) 07832 #define I2S_RCR3_REG(base) ((base)->RCR3) 07833 #define I2S_RCR4_REG(base) ((base)->RCR4) 07834 #define I2S_RCR5_REG(base) ((base)->RCR5) 07835 #define I2S_RDR_REG(base,index) ((base)->RDR[index]) 07836 #define I2S_RFR_REG(base,index) ((base)->RFR[index]) 07837 #define I2S_RMR_REG(base) ((base)->RMR) 07838 #define I2S_MCR_REG(base) ((base)->MCR) 07839 #define I2S_MDR_REG(base) ((base)->MDR) 07840 07841 /*! 07842 * @} 07843 */ /* end of group I2S_Register_Accessor_Macros */ 07844 07845 07846 /* ---------------------------------------------------------------------------- 07847 -- I2S Register Masks 07848 ---------------------------------------------------------------------------- */ 07849 07850 /*! 07851 * @addtogroup I2S_Register_Masks I2S Register Masks 07852 * @{ 07853 */ 07854 07855 /* TCSR Bit Fields */ 07856 #define I2S_TCSR_FRDE_MASK 0x1u 07857 #define I2S_TCSR_FRDE_SHIFT 0 07858 #define I2S_TCSR_FWDE_MASK 0x2u 07859 #define I2S_TCSR_FWDE_SHIFT 1 07860 #define I2S_TCSR_FRIE_MASK 0x100u 07861 #define I2S_TCSR_FRIE_SHIFT 8 07862 #define I2S_TCSR_FWIE_MASK 0x200u 07863 #define I2S_TCSR_FWIE_SHIFT 9 07864 #define I2S_TCSR_FEIE_MASK 0x400u 07865 #define I2S_TCSR_FEIE_SHIFT 10 07866 #define I2S_TCSR_SEIE_MASK 0x800u 07867 #define I2S_TCSR_SEIE_SHIFT 11 07868 #define I2S_TCSR_WSIE_MASK 0x1000u 07869 #define I2S_TCSR_WSIE_SHIFT 12 07870 #define I2S_TCSR_FRF_MASK 0x10000u 07871 #define I2S_TCSR_FRF_SHIFT 16 07872 #define I2S_TCSR_FWF_MASK 0x20000u 07873 #define I2S_TCSR_FWF_SHIFT 17 07874 #define I2S_TCSR_FEF_MASK 0x40000u 07875 #define I2S_TCSR_FEF_SHIFT 18 07876 #define I2S_TCSR_SEF_MASK 0x80000u 07877 #define I2S_TCSR_SEF_SHIFT 19 07878 #define I2S_TCSR_WSF_MASK 0x100000u 07879 #define I2S_TCSR_WSF_SHIFT 20 07880 #define I2S_TCSR_SR_MASK 0x1000000u 07881 #define I2S_TCSR_SR_SHIFT 24 07882 #define I2S_TCSR_FR_MASK 0x2000000u 07883 #define I2S_TCSR_FR_SHIFT 25 07884 #define I2S_TCSR_BCE_MASK 0x10000000u 07885 #define I2S_TCSR_BCE_SHIFT 28 07886 #define I2S_TCSR_DBGE_MASK 0x20000000u 07887 #define I2S_TCSR_DBGE_SHIFT 29 07888 #define I2S_TCSR_STOPE_MASK 0x40000000u 07889 #define I2S_TCSR_STOPE_SHIFT 30 07890 #define I2S_TCSR_TE_MASK 0x80000000u 07891 #define I2S_TCSR_TE_SHIFT 31 07892 /* TCR1 Bit Fields */ 07893 #define I2S_TCR1_TFW_MASK 0x7u 07894 #define I2S_TCR1_TFW_SHIFT 0 07895 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK) 07896 /* TCR2 Bit Fields */ 07897 #define I2S_TCR2_DIV_MASK 0xFFu 07898 #define I2S_TCR2_DIV_SHIFT 0 07899 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK) 07900 #define I2S_TCR2_BCD_MASK 0x1000000u 07901 #define I2S_TCR2_BCD_SHIFT 24 07902 #define I2S_TCR2_BCP_MASK 0x2000000u 07903 #define I2S_TCR2_BCP_SHIFT 25 07904 #define I2S_TCR2_MSEL_MASK 0xC000000u 07905 #define I2S_TCR2_MSEL_SHIFT 26 07906 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK) 07907 #define I2S_TCR2_BCI_MASK 0x10000000u 07908 #define I2S_TCR2_BCI_SHIFT 28 07909 #define I2S_TCR2_BCS_MASK 0x20000000u 07910 #define I2S_TCR2_BCS_SHIFT 29 07911 #define I2S_TCR2_SYNC_MASK 0xC0000000u 07912 #define I2S_TCR2_SYNC_SHIFT 30 07913 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK) 07914 /* TCR3 Bit Fields */ 07915 #define I2S_TCR3_WDFL_MASK 0x1Fu 07916 #define I2S_TCR3_WDFL_SHIFT 0 07917 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK) 07918 #define I2S_TCR3_TCE_MASK 0x30000u 07919 #define I2S_TCR3_TCE_SHIFT 16 07920 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK) 07921 /* TCR4 Bit Fields */ 07922 #define I2S_TCR4_FSD_MASK 0x1u 07923 #define I2S_TCR4_FSD_SHIFT 0 07924 #define I2S_TCR4_FSP_MASK 0x2u 07925 #define I2S_TCR4_FSP_SHIFT 1 07926 #define I2S_TCR4_FSE_MASK 0x8u 07927 #define I2S_TCR4_FSE_SHIFT 3 07928 #define I2S_TCR4_MF_MASK 0x10u 07929 #define I2S_TCR4_MF_SHIFT 4 07930 #define I2S_TCR4_SYWD_MASK 0x1F00u 07931 #define I2S_TCR4_SYWD_SHIFT 8 07932 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK) 07933 #define I2S_TCR4_FRSZ_MASK 0x1F0000u 07934 #define I2S_TCR4_FRSZ_SHIFT 16 07935 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK) 07936 /* TCR5 Bit Fields */ 07937 #define I2S_TCR5_FBT_MASK 0x1F00u 07938 #define I2S_TCR5_FBT_SHIFT 8 07939 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK) 07940 #define I2S_TCR5_W0W_MASK 0x1F0000u 07941 #define I2S_TCR5_W0W_SHIFT 16 07942 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK) 07943 #define I2S_TCR5_WNW_MASK 0x1F000000u 07944 #define I2S_TCR5_WNW_SHIFT 24 07945 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK) 07946 /* TDR Bit Fields */ 07947 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu 07948 #define I2S_TDR_TDR_SHIFT 0 07949 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK) 07950 /* TFR Bit Fields */ 07951 #define I2S_TFR_RFP_MASK 0xFu 07952 #define I2S_TFR_RFP_SHIFT 0 07953 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK) 07954 #define I2S_TFR_WFP_MASK 0xF0000u 07955 #define I2S_TFR_WFP_SHIFT 16 07956 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK) 07957 /* TMR Bit Fields */ 07958 #define I2S_TMR_TWM_MASK 0xFFFFFFFFu 07959 #define I2S_TMR_TWM_SHIFT 0 07960 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK) 07961 /* RCSR Bit Fields */ 07962 #define I2S_RCSR_FRDE_MASK 0x1u 07963 #define I2S_RCSR_FRDE_SHIFT 0 07964 #define I2S_RCSR_FWDE_MASK 0x2u 07965 #define I2S_RCSR_FWDE_SHIFT 1 07966 #define I2S_RCSR_FRIE_MASK 0x100u 07967 #define I2S_RCSR_FRIE_SHIFT 8 07968 #define I2S_RCSR_FWIE_MASK 0x200u 07969 #define I2S_RCSR_FWIE_SHIFT 9 07970 #define I2S_RCSR_FEIE_MASK 0x400u 07971 #define I2S_RCSR_FEIE_SHIFT 10 07972 #define I2S_RCSR_SEIE_MASK 0x800u 07973 #define I2S_RCSR_SEIE_SHIFT 11 07974 #define I2S_RCSR_WSIE_MASK 0x1000u 07975 #define I2S_RCSR_WSIE_SHIFT 12 07976 #define I2S_RCSR_FRF_MASK 0x10000u 07977 #define I2S_RCSR_FRF_SHIFT 16 07978 #define I2S_RCSR_FWF_MASK 0x20000u 07979 #define I2S_RCSR_FWF_SHIFT 17 07980 #define I2S_RCSR_FEF_MASK 0x40000u 07981 #define I2S_RCSR_FEF_SHIFT 18 07982 #define I2S_RCSR_SEF_MASK 0x80000u 07983 #define I2S_RCSR_SEF_SHIFT 19 07984 #define I2S_RCSR_WSF_MASK 0x100000u 07985 #define I2S_RCSR_WSF_SHIFT 20 07986 #define I2S_RCSR_SR_MASK 0x1000000u 07987 #define I2S_RCSR_SR_SHIFT 24 07988 #define I2S_RCSR_FR_MASK 0x2000000u 07989 #define I2S_RCSR_FR_SHIFT 25 07990 #define I2S_RCSR_BCE_MASK 0x10000000u 07991 #define I2S_RCSR_BCE_SHIFT 28 07992 #define I2S_RCSR_DBGE_MASK 0x20000000u 07993 #define I2S_RCSR_DBGE_SHIFT 29 07994 #define I2S_RCSR_STOPE_MASK 0x40000000u 07995 #define I2S_RCSR_STOPE_SHIFT 30 07996 #define I2S_RCSR_RE_MASK 0x80000000u 07997 #define I2S_RCSR_RE_SHIFT 31 07998 /* RCR1 Bit Fields */ 07999 #define I2S_RCR1_RFW_MASK 0x7u 08000 #define I2S_RCR1_RFW_SHIFT 0 08001 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK) 08002 /* RCR2 Bit Fields */ 08003 #define I2S_RCR2_DIV_MASK 0xFFu 08004 #define I2S_RCR2_DIV_SHIFT 0 08005 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK) 08006 #define I2S_RCR2_BCD_MASK 0x1000000u 08007 #define I2S_RCR2_BCD_SHIFT 24 08008 #define I2S_RCR2_BCP_MASK 0x2000000u 08009 #define I2S_RCR2_BCP_SHIFT 25 08010 #define I2S_RCR2_MSEL_MASK 0xC000000u 08011 #define I2S_RCR2_MSEL_SHIFT 26 08012 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK) 08013 #define I2S_RCR2_BCI_MASK 0x10000000u 08014 #define I2S_RCR2_BCI_SHIFT 28 08015 #define I2S_RCR2_BCS_MASK 0x20000000u 08016 #define I2S_RCR2_BCS_SHIFT 29 08017 #define I2S_RCR2_SYNC_MASK 0xC0000000u 08018 #define I2S_RCR2_SYNC_SHIFT 30 08019 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK) 08020 /* RCR3 Bit Fields */ 08021 #define I2S_RCR3_WDFL_MASK 0x1Fu 08022 #define I2S_RCR3_WDFL_SHIFT 0 08023 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK) 08024 #define I2S_RCR3_RCE_MASK 0x30000u 08025 #define I2S_RCR3_RCE_SHIFT 16 08026 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK) 08027 /* RCR4 Bit Fields */ 08028 #define I2S_RCR4_FSD_MASK 0x1u 08029 #define I2S_RCR4_FSD_SHIFT 0 08030 #define I2S_RCR4_FSP_MASK 0x2u 08031 #define I2S_RCR4_FSP_SHIFT 1 08032 #define I2S_RCR4_FSE_MASK 0x8u 08033 #define I2S_RCR4_FSE_SHIFT 3 08034 #define I2S_RCR4_MF_MASK 0x10u 08035 #define I2S_RCR4_MF_SHIFT 4 08036 #define I2S_RCR4_SYWD_MASK 0x1F00u 08037 #define I2S_RCR4_SYWD_SHIFT 8 08038 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK) 08039 #define I2S_RCR4_FRSZ_MASK 0x1F0000u 08040 #define I2S_RCR4_FRSZ_SHIFT 16 08041 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK) 08042 /* RCR5 Bit Fields */ 08043 #define I2S_RCR5_FBT_MASK 0x1F00u 08044 #define I2S_RCR5_FBT_SHIFT 8 08045 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK) 08046 #define I2S_RCR5_W0W_MASK 0x1F0000u 08047 #define I2S_RCR5_W0W_SHIFT 16 08048 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK) 08049 #define I2S_RCR5_WNW_MASK 0x1F000000u 08050 #define I2S_RCR5_WNW_SHIFT 24 08051 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK) 08052 /* RDR Bit Fields */ 08053 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu 08054 #define I2S_RDR_RDR_SHIFT 0 08055 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK) 08056 /* RFR Bit Fields */ 08057 #define I2S_RFR_RFP_MASK 0xFu 08058 #define I2S_RFR_RFP_SHIFT 0 08059 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK) 08060 #define I2S_RFR_WFP_MASK 0xF0000u 08061 #define I2S_RFR_WFP_SHIFT 16 08062 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK) 08063 /* RMR Bit Fields */ 08064 #define I2S_RMR_RWM_MASK 0xFFFFFFFFu 08065 #define I2S_RMR_RWM_SHIFT 0 08066 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK) 08067 /* MCR Bit Fields */ 08068 #define I2S_MCR_MICS_MASK 0x3000000u 08069 #define I2S_MCR_MICS_SHIFT 24 08070 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK) 08071 #define I2S_MCR_MOE_MASK 0x40000000u 08072 #define I2S_MCR_MOE_SHIFT 30 08073 #define I2S_MCR_DUF_MASK 0x80000000u 08074 #define I2S_MCR_DUF_SHIFT 31 08075 /* MDR Bit Fields */ 08076 #define I2S_MDR_DIVIDE_MASK 0xFFFu 08077 #define I2S_MDR_DIVIDE_SHIFT 0 08078 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK) 08079 #define I2S_MDR_FRACT_MASK 0xFF000u 08080 #define I2S_MDR_FRACT_SHIFT 12 08081 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK) 08082 08083 /*! 08084 * @} 08085 */ /* end of group I2S_Register_Masks */ 08086 08087 08088 /* I2S - Peripheral instance base addresses */ 08089 /** Peripheral I2S0 base address */ 08090 #define I2S0_BASE (0x4002F000u) 08091 /** Peripheral I2S0 base pointer */ 08092 #define I2S0 ((I2S_Type *)I2S0_BASE) 08093 #define I2S0_BASE_PTR (I2S0) 08094 /** Array initializer of I2S peripheral base addresses */ 08095 #define I2S_BASE_ADDRS { I2S0_BASE } 08096 /** Array initializer of I2S peripheral base pointers */ 08097 #define I2S_BASE_PTRS { I2S0 } 08098 /** Interrupt vectors for the I2S peripheral type */ 08099 #define I2S_RX_IRQS { I2S0_Rx_IRQn } 08100 #define I2S_TX_IRQS { I2S0_Tx_IRQn } 08101 08102 /* ---------------------------------------------------------------------------- 08103 -- I2S - Register accessor macros 08104 ---------------------------------------------------------------------------- */ 08105 08106 /*! 08107 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros 08108 * @{ 08109 */ 08110 08111 08112 /* I2S - Register instance definitions */ 08113 /* I2S0 */ 08114 #define I2S0_TCSR I2S_TCSR_REG(I2S0) 08115 #define I2S0_TCR1 I2S_TCR1_REG(I2S0) 08116 #define I2S0_TCR2 I2S_TCR2_REG(I2S0) 08117 #define I2S0_TCR3 I2S_TCR3_REG(I2S0) 08118 #define I2S0_TCR4 I2S_TCR4_REG(I2S0) 08119 #define I2S0_TCR5 I2S_TCR5_REG(I2S0) 08120 #define I2S0_TDR0 I2S_TDR_REG(I2S0,0) 08121 #define I2S0_TDR1 I2S_TDR_REG(I2S0,1) 08122 #define I2S0_TFR0 I2S_TFR_REG(I2S0,0) 08123 #define I2S0_TFR1 I2S_TFR_REG(I2S0,1) 08124 #define I2S0_TMR I2S_TMR_REG(I2S0) 08125 #define I2S0_RCSR I2S_RCSR_REG(I2S0) 08126 #define I2S0_RCR1 I2S_RCR1_REG(I2S0) 08127 #define I2S0_RCR2 I2S_RCR2_REG(I2S0) 08128 #define I2S0_RCR3 I2S_RCR3_REG(I2S0) 08129 #define I2S0_RCR4 I2S_RCR4_REG(I2S0) 08130 #define I2S0_RCR5 I2S_RCR5_REG(I2S0) 08131 #define I2S0_RDR0 I2S_RDR_REG(I2S0,0) 08132 #define I2S0_RDR1 I2S_RDR_REG(I2S0,1) 08133 #define I2S0_RFR0 I2S_RFR_REG(I2S0,0) 08134 #define I2S0_RFR1 I2S_RFR_REG(I2S0,1) 08135 #define I2S0_RMR I2S_RMR_REG(I2S0) 08136 #define I2S0_MCR I2S_MCR_REG(I2S0) 08137 #define I2S0_MDR I2S_MDR_REG(I2S0) 08138 08139 /* I2S - Register array accessors */ 08140 #define I2S0_TDR(index) I2S_TDR_REG(I2S0,index) 08141 #define I2S0_TFR(index) I2S_TFR_REG(I2S0,index) 08142 #define I2S0_RDR(index) I2S_RDR_REG(I2S0,index) 08143 #define I2S0_RFR(index) I2S_RFR_REG(I2S0,index) 08144 08145 /*! 08146 * @} 08147 */ /* end of group I2S_Register_Accessor_Macros */ 08148 08149 08150 /*! 08151 * @} 08152 */ /* end of group I2S_Peripheral_Access_Layer */ 08153 08154 08155 /* ---------------------------------------------------------------------------- 08156 -- LLWU Peripheral Access Layer 08157 ---------------------------------------------------------------------------- */ 08158 08159 /*! 08160 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer 08161 * @{ 08162 */ 08163 08164 /** LLWU - Register Layout Typedef */ 08165 typedef struct { 08166 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ 08167 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ 08168 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ 08169 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ 08170 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ 08171 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ 08172 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ 08173 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ 08174 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ 08175 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ 08176 __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */ 08177 } LLWU_Type, *LLWU_MemMapPtr; 08178 08179 /* ---------------------------------------------------------------------------- 08180 -- LLWU - Register accessor macros 08181 ---------------------------------------------------------------------------- */ 08182 08183 /*! 08184 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros 08185 * @{ 08186 */ 08187 08188 08189 /* LLWU - Register accessors */ 08190 #define LLWU_PE1_REG(base) ((base)->PE1) 08191 #define LLWU_PE2_REG(base) ((base)->PE2) 08192 #define LLWU_PE3_REG(base) ((base)->PE3) 08193 #define LLWU_PE4_REG(base) ((base)->PE4) 08194 #define LLWU_ME_REG(base) ((base)->ME) 08195 #define LLWU_F1_REG(base) ((base)->F1) 08196 #define LLWU_F2_REG(base) ((base)->F2) 08197 #define LLWU_F3_REG(base) ((base)->F3) 08198 #define LLWU_FILT1_REG(base) ((base)->FILT1) 08199 #define LLWU_FILT2_REG(base) ((base)->FILT2) 08200 #define LLWU_RST_REG(base) ((base)->RST) 08201 08202 /*! 08203 * @} 08204 */ /* end of group LLWU_Register_Accessor_Macros */ 08205 08206 08207 /* ---------------------------------------------------------------------------- 08208 -- LLWU Register Masks 08209 ---------------------------------------------------------------------------- */ 08210 08211 /*! 08212 * @addtogroup LLWU_Register_Masks LLWU Register Masks 08213 * @{ 08214 */ 08215 08216 /* PE1 Bit Fields */ 08217 #define LLWU_PE1_WUPE0_MASK 0x3u 08218 #define LLWU_PE1_WUPE0_SHIFT 0 08219 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK) 08220 #define LLWU_PE1_WUPE1_MASK 0xCu 08221 #define LLWU_PE1_WUPE1_SHIFT 2 08222 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK) 08223 #define LLWU_PE1_WUPE2_MASK 0x30u 08224 #define LLWU_PE1_WUPE2_SHIFT 4 08225 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK) 08226 #define LLWU_PE1_WUPE3_MASK 0xC0u 08227 #define LLWU_PE1_WUPE3_SHIFT 6 08228 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK) 08229 /* PE2 Bit Fields */ 08230 #define LLWU_PE2_WUPE4_MASK 0x3u 08231 #define LLWU_PE2_WUPE4_SHIFT 0 08232 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK) 08233 #define LLWU_PE2_WUPE5_MASK 0xCu 08234 #define LLWU_PE2_WUPE5_SHIFT 2 08235 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK) 08236 #define LLWU_PE2_WUPE6_MASK 0x30u 08237 #define LLWU_PE2_WUPE6_SHIFT 4 08238 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK) 08239 #define LLWU_PE2_WUPE7_MASK 0xC0u 08240 #define LLWU_PE2_WUPE7_SHIFT 6 08241 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK) 08242 /* PE3 Bit Fields */ 08243 #define LLWU_PE3_WUPE8_MASK 0x3u 08244 #define LLWU_PE3_WUPE8_SHIFT 0 08245 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK) 08246 #define LLWU_PE3_WUPE9_MASK 0xCu 08247 #define LLWU_PE3_WUPE9_SHIFT 2 08248 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK) 08249 #define LLWU_PE3_WUPE10_MASK 0x30u 08250 #define LLWU_PE3_WUPE10_SHIFT 4 08251 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK) 08252 #define LLWU_PE3_WUPE11_MASK 0xC0u 08253 #define LLWU_PE3_WUPE11_SHIFT 6 08254 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK) 08255 /* PE4 Bit Fields */ 08256 #define LLWU_PE4_WUPE12_MASK 0x3u 08257 #define LLWU_PE4_WUPE12_SHIFT 0 08258 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK) 08259 #define LLWU_PE4_WUPE13_MASK 0xCu 08260 #define LLWU_PE4_WUPE13_SHIFT 2 08261 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK) 08262 #define LLWU_PE4_WUPE14_MASK 0x30u 08263 #define LLWU_PE4_WUPE14_SHIFT 4 08264 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK) 08265 #define LLWU_PE4_WUPE15_MASK 0xC0u 08266 #define LLWU_PE4_WUPE15_SHIFT 6 08267 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK) 08268 /* ME Bit Fields */ 08269 #define LLWU_ME_WUME0_MASK 0x1u 08270 #define LLWU_ME_WUME0_SHIFT 0 08271 #define LLWU_ME_WUME1_MASK 0x2u 08272 #define LLWU_ME_WUME1_SHIFT 1 08273 #define LLWU_ME_WUME2_MASK 0x4u 08274 #define LLWU_ME_WUME2_SHIFT 2 08275 #define LLWU_ME_WUME3_MASK 0x8u 08276 #define LLWU_ME_WUME3_SHIFT 3 08277 #define LLWU_ME_WUME4_MASK 0x10u 08278 #define LLWU_ME_WUME4_SHIFT 4 08279 #define LLWU_ME_WUME5_MASK 0x20u 08280 #define LLWU_ME_WUME5_SHIFT 5 08281 #define LLWU_ME_WUME6_MASK 0x40u 08282 #define LLWU_ME_WUME6_SHIFT 6 08283 #define LLWU_ME_WUME7_MASK 0x80u 08284 #define LLWU_ME_WUME7_SHIFT 7 08285 /* F1 Bit Fields */ 08286 #define LLWU_F1_WUF0_MASK 0x1u 08287 #define LLWU_F1_WUF0_SHIFT 0 08288 #define LLWU_F1_WUF1_MASK 0x2u 08289 #define LLWU_F1_WUF1_SHIFT 1 08290 #define LLWU_F1_WUF2_MASK 0x4u 08291 #define LLWU_F1_WUF2_SHIFT 2 08292 #define LLWU_F1_WUF3_MASK 0x8u 08293 #define LLWU_F1_WUF3_SHIFT 3 08294 #define LLWU_F1_WUF4_MASK 0x10u 08295 #define LLWU_F1_WUF4_SHIFT 4 08296 #define LLWU_F1_WUF5_MASK 0x20u 08297 #define LLWU_F1_WUF5_SHIFT 5 08298 #define LLWU_F1_WUF6_MASK 0x40u 08299 #define LLWU_F1_WUF6_SHIFT 6 08300 #define LLWU_F1_WUF7_MASK 0x80u 08301 #define LLWU_F1_WUF7_SHIFT 7 08302 /* F2 Bit Fields */ 08303 #define LLWU_F2_WUF8_MASK 0x1u 08304 #define LLWU_F2_WUF8_SHIFT 0 08305 #define LLWU_F2_WUF9_MASK 0x2u 08306 #define LLWU_F2_WUF9_SHIFT 1 08307 #define LLWU_F2_WUF10_MASK 0x4u 08308 #define LLWU_F2_WUF10_SHIFT 2 08309 #define LLWU_F2_WUF11_MASK 0x8u 08310 #define LLWU_F2_WUF11_SHIFT 3 08311 #define LLWU_F2_WUF12_MASK 0x10u 08312 #define LLWU_F2_WUF12_SHIFT 4 08313 #define LLWU_F2_WUF13_MASK 0x20u 08314 #define LLWU_F2_WUF13_SHIFT 5 08315 #define LLWU_F2_WUF14_MASK 0x40u 08316 #define LLWU_F2_WUF14_SHIFT 6 08317 #define LLWU_F2_WUF15_MASK 0x80u 08318 #define LLWU_F2_WUF15_SHIFT 7 08319 /* F3 Bit Fields */ 08320 #define LLWU_F3_MWUF0_MASK 0x1u 08321 #define LLWU_F3_MWUF0_SHIFT 0 08322 #define LLWU_F3_MWUF1_MASK 0x2u 08323 #define LLWU_F3_MWUF1_SHIFT 1 08324 #define LLWU_F3_MWUF2_MASK 0x4u 08325 #define LLWU_F3_MWUF2_SHIFT 2 08326 #define LLWU_F3_MWUF3_MASK 0x8u 08327 #define LLWU_F3_MWUF3_SHIFT 3 08328 #define LLWU_F3_MWUF4_MASK 0x10u 08329 #define LLWU_F3_MWUF4_SHIFT 4 08330 #define LLWU_F3_MWUF5_MASK 0x20u 08331 #define LLWU_F3_MWUF5_SHIFT 5 08332 #define LLWU_F3_MWUF6_MASK 0x40u 08333 #define LLWU_F3_MWUF6_SHIFT 6 08334 #define LLWU_F3_MWUF7_MASK 0x80u 08335 #define LLWU_F3_MWUF7_SHIFT 7 08336 /* FILT1 Bit Fields */ 08337 #define LLWU_FILT1_FILTSEL_MASK 0xFu 08338 #define LLWU_FILT1_FILTSEL_SHIFT 0 08339 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK) 08340 #define LLWU_FILT1_FILTE_MASK 0x60u 08341 #define LLWU_FILT1_FILTE_SHIFT 5 08342 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK) 08343 #define LLWU_FILT1_FILTF_MASK 0x80u 08344 #define LLWU_FILT1_FILTF_SHIFT 7 08345 /* FILT2 Bit Fields */ 08346 #define LLWU_FILT2_FILTSEL_MASK 0xFu 08347 #define LLWU_FILT2_FILTSEL_SHIFT 0 08348 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK) 08349 #define LLWU_FILT2_FILTE_MASK 0x60u 08350 #define LLWU_FILT2_FILTE_SHIFT 5 08351 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK) 08352 #define LLWU_FILT2_FILTF_MASK 0x80u 08353 #define LLWU_FILT2_FILTF_SHIFT 7 08354 /* RST Bit Fields */ 08355 #define LLWU_RST_RSTFILT_MASK 0x1u 08356 #define LLWU_RST_RSTFILT_SHIFT 0 08357 #define LLWU_RST_LLRSTE_MASK 0x2u 08358 #define LLWU_RST_LLRSTE_SHIFT 1 08359 08360 /*! 08361 * @} 08362 */ /* end of group LLWU_Register_Masks */ 08363 08364 08365 /* LLWU - Peripheral instance base addresses */ 08366 /** Peripheral LLWU base address */ 08367 #define LLWU_BASE (0x4007C000u) 08368 /** Peripheral LLWU base pointer */ 08369 #define LLWU ((LLWU_Type *)LLWU_BASE) 08370 #define LLWU_BASE_PTR (LLWU) 08371 /** Array initializer of LLWU peripheral base addresses */ 08372 #define LLWU_BASE_ADDRS { LLWU_BASE } 08373 /** Array initializer of LLWU peripheral base pointers */ 08374 #define LLWU_BASE_PTRS { LLWU } 08375 /** Interrupt vectors for the LLWU peripheral type */ 08376 #define LLWU_IRQS { LLW_IRQn } 08377 08378 /* ---------------------------------------------------------------------------- 08379 -- LLWU - Register accessor macros 08380 ---------------------------------------------------------------------------- */ 08381 08382 /*! 08383 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros 08384 * @{ 08385 */ 08386 08387 08388 /* LLWU - Register instance definitions */ 08389 /* LLWU */ 08390 #define LLWU_PE1 LLWU_PE1_REG(LLWU) 08391 #define LLWU_PE2 LLWU_PE2_REG(LLWU) 08392 #define LLWU_PE3 LLWU_PE3_REG(LLWU) 08393 #define LLWU_PE4 LLWU_PE4_REG(LLWU) 08394 #define LLWU_ME LLWU_ME_REG(LLWU) 08395 #define LLWU_F1 LLWU_F1_REG(LLWU) 08396 #define LLWU_F2 LLWU_F2_REG(LLWU) 08397 #define LLWU_F3 LLWU_F3_REG(LLWU) 08398 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU) 08399 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU) 08400 #define LLWU_RST LLWU_RST_REG(LLWU) 08401 08402 /*! 08403 * @} 08404 */ /* end of group LLWU_Register_Accessor_Macros */ 08405 08406 08407 /*! 08408 * @} 08409 */ /* end of group LLWU_Peripheral_Access_Layer */ 08410 08411 08412 /* ---------------------------------------------------------------------------- 08413 -- LPTMR Peripheral Access Layer 08414 ---------------------------------------------------------------------------- */ 08415 08416 /*! 08417 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer 08418 * @{ 08419 */ 08420 08421 /** LPTMR - Register Layout Typedef */ 08422 typedef struct { 08423 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ 08424 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ 08425 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ 08426 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ 08427 } LPTMR_Type, *LPTMR_MemMapPtr; 08428 08429 /* ---------------------------------------------------------------------------- 08430 -- LPTMR - Register accessor macros 08431 ---------------------------------------------------------------------------- */ 08432 08433 /*! 08434 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros 08435 * @{ 08436 */ 08437 08438 08439 /* LPTMR - Register accessors */ 08440 #define LPTMR_CSR_REG(base) ((base)->CSR) 08441 #define LPTMR_PSR_REG(base) ((base)->PSR) 08442 #define LPTMR_CMR_REG(base) ((base)->CMR) 08443 #define LPTMR_CNR_REG(base) ((base)->CNR) 08444 08445 /*! 08446 * @} 08447 */ /* end of group LPTMR_Register_Accessor_Macros */ 08448 08449 08450 /* ---------------------------------------------------------------------------- 08451 -- LPTMR Register Masks 08452 ---------------------------------------------------------------------------- */ 08453 08454 /*! 08455 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks 08456 * @{ 08457 */ 08458 08459 /* CSR Bit Fields */ 08460 #define LPTMR_CSR_TEN_MASK 0x1u 08461 #define LPTMR_CSR_TEN_SHIFT 0 08462 #define LPTMR_CSR_TMS_MASK 0x2u 08463 #define LPTMR_CSR_TMS_SHIFT 1 08464 #define LPTMR_CSR_TFC_MASK 0x4u 08465 #define LPTMR_CSR_TFC_SHIFT 2 08466 #define LPTMR_CSR_TPP_MASK 0x8u 08467 #define LPTMR_CSR_TPP_SHIFT 3 08468 #define LPTMR_CSR_TPS_MASK 0x30u 08469 #define LPTMR_CSR_TPS_SHIFT 4 08470 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK) 08471 #define LPTMR_CSR_TIE_MASK 0x40u 08472 #define LPTMR_CSR_TIE_SHIFT 6 08473 #define LPTMR_CSR_TCF_MASK 0x80u 08474 #define LPTMR_CSR_TCF_SHIFT 7 08475 /* PSR Bit Fields */ 08476 #define LPTMR_PSR_PCS_MASK 0x3u 08477 #define LPTMR_PSR_PCS_SHIFT 0 08478 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK) 08479 #define LPTMR_PSR_PBYP_MASK 0x4u 08480 #define LPTMR_PSR_PBYP_SHIFT 2 08481 #define LPTMR_PSR_PRESCALE_MASK 0x78u 08482 #define LPTMR_PSR_PRESCALE_SHIFT 3 08483 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK) 08484 /* CMR Bit Fields */ 08485 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu 08486 #define LPTMR_CMR_COMPARE_SHIFT 0 08487 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK) 08488 /* CNR Bit Fields */ 08489 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu 08490 #define LPTMR_CNR_COUNTER_SHIFT 0 08491 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK) 08492 08493 /*! 08494 * @} 08495 */ /* end of group LPTMR_Register_Masks */ 08496 08497 08498 /* LPTMR - Peripheral instance base addresses */ 08499 /** Peripheral LPTMR0 base address */ 08500 #define LPTMR0_BASE (0x40040000u) 08501 /** Peripheral LPTMR0 base pointer */ 08502 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 08503 #define LPTMR0_BASE_PTR (LPTMR0) 08504 /** Array initializer of LPTMR peripheral base addresses */ 08505 #define LPTMR_BASE_ADDRS { LPTMR0_BASE } 08506 /** Array initializer of LPTMR peripheral base pointers */ 08507 #define LPTMR_BASE_PTRS { LPTMR0 } 08508 /** Interrupt vectors for the LPTMR peripheral type */ 08509 #define LPTMR_IRQS { LPTimer_IRQn } 08510 08511 /* ---------------------------------------------------------------------------- 08512 -- LPTMR - Register accessor macros 08513 ---------------------------------------------------------------------------- */ 08514 08515 /*! 08516 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros 08517 * @{ 08518 */ 08519 08520 08521 /* LPTMR - Register instance definitions */ 08522 /* LPTMR0 */ 08523 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0) 08524 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0) 08525 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0) 08526 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0) 08527 08528 /*! 08529 * @} 08530 */ /* end of group LPTMR_Register_Accessor_Macros */ 08531 08532 08533 /*! 08534 * @} 08535 */ /* end of group LPTMR_Peripheral_Access_Layer */ 08536 08537 08538 /* ---------------------------------------------------------------------------- 08539 -- MCG Peripheral Access Layer 08540 ---------------------------------------------------------------------------- */ 08541 08542 /*! 08543 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer 08544 * @{ 08545 */ 08546 08547 /** MCG - Register Layout Typedef */ 08548 typedef struct { 08549 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ 08550 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ 08551 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ 08552 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ 08553 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ 08554 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ 08555 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */ 08556 uint8_t RESERVED_0[1]; 08557 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ 08558 uint8_t RESERVED_1[1]; 08559 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ 08560 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ 08561 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ 08562 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ 08563 } MCG_Type, *MCG_MemMapPtr; 08564 08565 /* ---------------------------------------------------------------------------- 08566 -- MCG - Register accessor macros 08567 ---------------------------------------------------------------------------- */ 08568 08569 /*! 08570 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros 08571 * @{ 08572 */ 08573 08574 08575 /* MCG - Register accessors */ 08576 #define MCG_C1_REG(base) ((base)->C1) 08577 #define MCG_C2_REG(base) ((base)->C2) 08578 #define MCG_C3_REG(base) ((base)->C3) 08579 #define MCG_C4_REG(base) ((base)->C4) 08580 #define MCG_C5_REG(base) ((base)->C5) 08581 #define MCG_C6_REG(base) ((base)->C6) 08582 #define MCG_S_REG(base) ((base)->S) 08583 #define MCG_SC_REG(base) ((base)->SC) 08584 #define MCG_ATCVH_REG(base) ((base)->ATCVH) 08585 #define MCG_ATCVL_REG(base) ((base)->ATCVL) 08586 #define MCG_C7_REG(base) ((base)->C7) 08587 #define MCG_C8_REG(base) ((base)->C8) 08588 08589 /*! 08590 * @} 08591 */ /* end of group MCG_Register_Accessor_Macros */ 08592 08593 08594 /* ---------------------------------------------------------------------------- 08595 -- MCG Register Masks 08596 ---------------------------------------------------------------------------- */ 08597 08598 /*! 08599 * @addtogroup MCG_Register_Masks MCG Register Masks 08600 * @{ 08601 */ 08602 08603 /* C1 Bit Fields */ 08604 #define MCG_C1_IREFSTEN_MASK 0x1u 08605 #define MCG_C1_IREFSTEN_SHIFT 0 08606 #define MCG_C1_IRCLKEN_MASK 0x2u 08607 #define MCG_C1_IRCLKEN_SHIFT 1 08608 #define MCG_C1_IREFS_MASK 0x4u 08609 #define MCG_C1_IREFS_SHIFT 2 08610 #define MCG_C1_FRDIV_MASK 0x38u 08611 #define MCG_C1_FRDIV_SHIFT 3 08612 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK) 08613 #define MCG_C1_CLKS_MASK 0xC0u 08614 #define MCG_C1_CLKS_SHIFT 6 08615 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK) 08616 /* C2 Bit Fields */ 08617 #define MCG_C2_IRCS_MASK 0x1u 08618 #define MCG_C2_IRCS_SHIFT 0 08619 #define MCG_C2_LP_MASK 0x2u 08620 #define MCG_C2_LP_SHIFT 1 08621 #define MCG_C2_EREFS_MASK 0x4u 08622 #define MCG_C2_EREFS_SHIFT 2 08623 #define MCG_C2_HGO_MASK 0x8u 08624 #define MCG_C2_HGO_SHIFT 3 08625 #define MCG_C2_RANGE_MASK 0x30u 08626 #define MCG_C2_RANGE_SHIFT 4 08627 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK) 08628 #define MCG_C2_FCFTRIM_MASK 0x40u 08629 #define MCG_C2_FCFTRIM_SHIFT 6 08630 #define MCG_C2_LOCRE0_MASK 0x80u 08631 #define MCG_C2_LOCRE0_SHIFT 7 08632 /* C3 Bit Fields */ 08633 #define MCG_C3_SCTRIM_MASK 0xFFu 08634 #define MCG_C3_SCTRIM_SHIFT 0 08635 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK) 08636 /* C4 Bit Fields */ 08637 #define MCG_C4_SCFTRIM_MASK 0x1u 08638 #define MCG_C4_SCFTRIM_SHIFT 0 08639 #define MCG_C4_FCTRIM_MASK 0x1Eu 08640 #define MCG_C4_FCTRIM_SHIFT 1 08641 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK) 08642 #define MCG_C4_DRST_DRS_MASK 0x60u 08643 #define MCG_C4_DRST_DRS_SHIFT 5 08644 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK) 08645 #define MCG_C4_DMX32_MASK 0x80u 08646 #define MCG_C4_DMX32_SHIFT 7 08647 /* C5 Bit Fields */ 08648 #define MCG_C5_PRDIV0_MASK 0x1Fu 08649 #define MCG_C5_PRDIV0_SHIFT 0 08650 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK) 08651 #define MCG_C5_PLLSTEN0_MASK 0x20u 08652 #define MCG_C5_PLLSTEN0_SHIFT 5 08653 #define MCG_C5_PLLCLKEN0_MASK 0x40u 08654 #define MCG_C5_PLLCLKEN0_SHIFT 6 08655 /* C6 Bit Fields */ 08656 #define MCG_C6_VDIV0_MASK 0x1Fu 08657 #define MCG_C6_VDIV0_SHIFT 0 08658 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK) 08659 #define MCG_C6_CME0_MASK 0x20u 08660 #define MCG_C6_CME0_SHIFT 5 08661 #define MCG_C6_PLLS_MASK 0x40u 08662 #define MCG_C6_PLLS_SHIFT 6 08663 #define MCG_C6_LOLIE0_MASK 0x80u 08664 #define MCG_C6_LOLIE0_SHIFT 7 08665 /* S Bit Fields */ 08666 #define MCG_S_IRCST_MASK 0x1u 08667 #define MCG_S_IRCST_SHIFT 0 08668 #define MCG_S_OSCINIT0_MASK 0x2u 08669 #define MCG_S_OSCINIT0_SHIFT 1 08670 #define MCG_S_CLKST_MASK 0xCu 08671 #define MCG_S_CLKST_SHIFT 2 08672 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK) 08673 #define MCG_S_IREFST_MASK 0x10u 08674 #define MCG_S_IREFST_SHIFT 4 08675 #define MCG_S_PLLST_MASK 0x20u 08676 #define MCG_S_PLLST_SHIFT 5 08677 #define MCG_S_LOCK0_MASK 0x40u 08678 #define MCG_S_LOCK0_SHIFT 6 08679 #define MCG_S_LOLS0_MASK 0x80u 08680 #define MCG_S_LOLS0_SHIFT 7 08681 /* SC Bit Fields */ 08682 #define MCG_SC_LOCS0_MASK 0x1u 08683 #define MCG_SC_LOCS0_SHIFT 0 08684 #define MCG_SC_FCRDIV_MASK 0xEu 08685 #define MCG_SC_FCRDIV_SHIFT 1 08686 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK) 08687 #define MCG_SC_FLTPRSRV_MASK 0x10u 08688 #define MCG_SC_FLTPRSRV_SHIFT 4 08689 #define MCG_SC_ATMF_MASK 0x20u 08690 #define MCG_SC_ATMF_SHIFT 5 08691 #define MCG_SC_ATMS_MASK 0x40u 08692 #define MCG_SC_ATMS_SHIFT 6 08693 #define MCG_SC_ATME_MASK 0x80u 08694 #define MCG_SC_ATME_SHIFT 7 08695 /* ATCVH Bit Fields */ 08696 #define MCG_ATCVH_ATCVH_MASK 0xFFu 08697 #define MCG_ATCVH_ATCVH_SHIFT 0 08698 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK) 08699 /* ATCVL Bit Fields */ 08700 #define MCG_ATCVL_ATCVL_MASK 0xFFu 08701 #define MCG_ATCVL_ATCVL_SHIFT 0 08702 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK) 08703 /* C7 Bit Fields */ 08704 #define MCG_C7_OSCSEL_MASK 0x3u 08705 #define MCG_C7_OSCSEL_SHIFT 0 08706 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK) 08707 /* C8 Bit Fields */ 08708 #define MCG_C8_LOCS1_MASK 0x1u 08709 #define MCG_C8_LOCS1_SHIFT 0 08710 #define MCG_C8_CME1_MASK 0x20u 08711 #define MCG_C8_CME1_SHIFT 5 08712 #define MCG_C8_LOLRE_MASK 0x40u 08713 #define MCG_C8_LOLRE_SHIFT 6 08714 #define MCG_C8_LOCRE1_MASK 0x80u 08715 #define MCG_C8_LOCRE1_SHIFT 7 08716 08717 /*! 08718 * @} 08719 */ /* end of group MCG_Register_Masks */ 08720 08721 08722 /* MCG - Peripheral instance base addresses */ 08723 /** Peripheral MCG base address */ 08724 #define MCG_BASE (0x40064000u) 08725 /** Peripheral MCG base pointer */ 08726 #define MCG ((MCG_Type *)MCG_BASE) 08727 #define MCG_BASE_PTR (MCG) 08728 /** Array initializer of MCG peripheral base addresses */ 08729 #define MCG_BASE_ADDRS { MCG_BASE } 08730 /** Array initializer of MCG peripheral base pointers */ 08731 #define MCG_BASE_PTRS { MCG } 08732 08733 /* ---------------------------------------------------------------------------- 08734 -- MCG - Register accessor macros 08735 ---------------------------------------------------------------------------- */ 08736 08737 /*! 08738 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros 08739 * @{ 08740 */ 08741 08742 08743 /* MCG - Register instance definitions */ 08744 /* MCG */ 08745 #define MCG_C1 MCG_C1_REG(MCG) 08746 #define MCG_C2 MCG_C2_REG(MCG) 08747 #define MCG_C3 MCG_C3_REG(MCG) 08748 #define MCG_C4 MCG_C4_REG(MCG) 08749 #define MCG_C5 MCG_C5_REG(MCG) 08750 #define MCG_C6 MCG_C6_REG(MCG) 08751 #define MCG_S MCG_S_REG(MCG) 08752 #define MCG_SC MCG_SC_REG(MCG) 08753 #define MCG_ATCVH MCG_ATCVH_REG(MCG) 08754 #define MCG_ATCVL MCG_ATCVL_REG(MCG) 08755 #define MCG_C7 MCG_C7_REG(MCG) 08756 #define MCG_C8 MCG_C8_REG(MCG) 08757 08758 /*! 08759 * @} 08760 */ /* end of group MCG_Register_Accessor_Macros */ 08761 08762 08763 /*! 08764 * @} 08765 */ /* end of group MCG_Peripheral_Access_Layer */ 08766 08767 08768 /* ---------------------------------------------------------------------------- 08769 -- MCM Peripheral Access Layer 08770 ---------------------------------------------------------------------------- */ 08771 08772 /*! 08773 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer 08774 * @{ 08775 */ 08776 08777 /** MCM - Register Layout Typedef */ 08778 typedef struct { 08779 uint8_t RESERVED_0[8]; 08780 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 08781 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ 08782 __IO uint32_t CR; /**< Control Register, offset: 0xC */ 08783 __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */ 08784 __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */ 08785 __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */ 08786 __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */ 08787 uint8_t RESERVED_1[16]; 08788 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */ 08789 } MCM_Type, *MCM_MemMapPtr; 08790 08791 /* ---------------------------------------------------------------------------- 08792 -- MCM - Register accessor macros 08793 ---------------------------------------------------------------------------- */ 08794 08795 /*! 08796 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros 08797 * @{ 08798 */ 08799 08800 08801 /* MCM - Register accessors */ 08802 #define MCM_PLASC_REG(base) ((base)->PLASC) 08803 #define MCM_PLAMC_REG(base) ((base)->PLAMC) 08804 #define MCM_CR_REG(base) ((base)->CR) 08805 #define MCM_ISCR_REG(base) ((base)->ISCR) 08806 #define MCM_ETBCC_REG(base) ((base)->ETBCC) 08807 #define MCM_ETBRL_REG(base) ((base)->ETBRL) 08808 #define MCM_ETBCNT_REG(base) ((base)->ETBCNT) 08809 #define MCM_PID_REG(base) ((base)->PID) 08810 08811 /*! 08812 * @} 08813 */ /* end of group MCM_Register_Accessor_Macros */ 08814 08815 08816 /* ---------------------------------------------------------------------------- 08817 -- MCM Register Masks 08818 ---------------------------------------------------------------------------- */ 08819 08820 /*! 08821 * @addtogroup MCM_Register_Masks MCM Register Masks 08822 * @{ 08823 */ 08824 08825 /* PLASC Bit Fields */ 08826 #define MCM_PLASC_ASC_MASK 0xFFu 08827 #define MCM_PLASC_ASC_SHIFT 0 08828 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK) 08829 /* PLAMC Bit Fields */ 08830 #define MCM_PLAMC_AMC_MASK 0xFFu 08831 #define MCM_PLAMC_AMC_SHIFT 0 08832 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK) 08833 /* CR Bit Fields */ 08834 #define MCM_CR_SRAMUAP_MASK 0x3000000u 08835 #define MCM_CR_SRAMUAP_SHIFT 24 08836 #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK) 08837 #define MCM_CR_SRAMUWP_MASK 0x4000000u 08838 #define MCM_CR_SRAMUWP_SHIFT 26 08839 #define MCM_CR_SRAMLAP_MASK 0x30000000u 08840 #define MCM_CR_SRAMLAP_SHIFT 28 08841 #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK) 08842 #define MCM_CR_SRAMLWP_MASK 0x40000000u 08843 #define MCM_CR_SRAMLWP_SHIFT 30 08844 /* ISCR Bit Fields */ 08845 #define MCM_ISCR_IRQ_MASK 0x2u 08846 #define MCM_ISCR_IRQ_SHIFT 1 08847 #define MCM_ISCR_NMI_MASK 0x4u 08848 #define MCM_ISCR_NMI_SHIFT 2 08849 #define MCM_ISCR_DHREQ_MASK 0x8u 08850 #define MCM_ISCR_DHREQ_SHIFT 3 08851 #define MCM_ISCR_FIOC_MASK 0x100u 08852 #define MCM_ISCR_FIOC_SHIFT 8 08853 #define MCM_ISCR_FDZC_MASK 0x200u 08854 #define MCM_ISCR_FDZC_SHIFT 9 08855 #define MCM_ISCR_FOFC_MASK 0x400u 08856 #define MCM_ISCR_FOFC_SHIFT 10 08857 #define MCM_ISCR_FUFC_MASK 0x800u 08858 #define MCM_ISCR_FUFC_SHIFT 11 08859 #define MCM_ISCR_FIXC_MASK 0x1000u 08860 #define MCM_ISCR_FIXC_SHIFT 12 08861 #define MCM_ISCR_FIDC_MASK 0x8000u 08862 #define MCM_ISCR_FIDC_SHIFT 15 08863 #define MCM_ISCR_FIOCE_MASK 0x1000000u 08864 #define MCM_ISCR_FIOCE_SHIFT 24 08865 #define MCM_ISCR_FDZCE_MASK 0x2000000u 08866 #define MCM_ISCR_FDZCE_SHIFT 25 08867 #define MCM_ISCR_FOFCE_MASK 0x4000000u 08868 #define MCM_ISCR_FOFCE_SHIFT 26 08869 #define MCM_ISCR_FUFCE_MASK 0x8000000u 08870 #define MCM_ISCR_FUFCE_SHIFT 27 08871 #define MCM_ISCR_FIXCE_MASK 0x10000000u 08872 #define MCM_ISCR_FIXCE_SHIFT 28 08873 #define MCM_ISCR_FIDCE_MASK 0x80000000u 08874 #define MCM_ISCR_FIDCE_SHIFT 31 08875 /* ETBCC Bit Fields */ 08876 #define MCM_ETBCC_CNTEN_MASK 0x1u 08877 #define MCM_ETBCC_CNTEN_SHIFT 0 08878 #define MCM_ETBCC_RSPT_MASK 0x6u 08879 #define MCM_ETBCC_RSPT_SHIFT 1 08880 #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK) 08881 #define MCM_ETBCC_RLRQ_MASK 0x8u 08882 #define MCM_ETBCC_RLRQ_SHIFT 3 08883 #define MCM_ETBCC_ETDIS_MASK 0x10u 08884 #define MCM_ETBCC_ETDIS_SHIFT 4 08885 #define MCM_ETBCC_ITDIS_MASK 0x20u 08886 #define MCM_ETBCC_ITDIS_SHIFT 5 08887 /* ETBRL Bit Fields */ 08888 #define MCM_ETBRL_RELOAD_MASK 0x7FFu 08889 #define MCM_ETBRL_RELOAD_SHIFT 0 08890 #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK) 08891 /* ETBCNT Bit Fields */ 08892 #define MCM_ETBCNT_COUNTER_MASK 0x7FFu 08893 #define MCM_ETBCNT_COUNTER_SHIFT 0 08894 #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK) 08895 /* PID Bit Fields */ 08896 #define MCM_PID_PID_MASK 0xFFu 08897 #define MCM_PID_PID_SHIFT 0 08898 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK) 08899 08900 /*! 08901 * @} 08902 */ /* end of group MCM_Register_Masks */ 08903 08904 08905 /* MCM - Peripheral instance base addresses */ 08906 /** Peripheral MCM base address */ 08907 #define MCM_BASE (0xE0080000u) 08908 /** Peripheral MCM base pointer */ 08909 #define MCM ((MCM_Type *)MCM_BASE) 08910 #define MCM_BASE_PTR (MCM) 08911 /** Array initializer of MCM peripheral base addresses */ 08912 #define MCM_BASE_ADDRS { MCM_BASE } 08913 /** Array initializer of MCM peripheral base pointers */ 08914 #define MCM_BASE_PTRS { MCM } 08915 08916 /* ---------------------------------------------------------------------------- 08917 -- MCM - Register accessor macros 08918 ---------------------------------------------------------------------------- */ 08919 08920 /*! 08921 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros 08922 * @{ 08923 */ 08924 08925 08926 /* MCM - Register instance definitions */ 08927 /* MCM */ 08928 #define MCM_PLASC MCM_PLASC_REG(MCM) 08929 #define MCM_PLAMC MCM_PLAMC_REG(MCM) 08930 #define MCM_CR MCM_CR_REG(MCM) 08931 #define MCM_ISCR MCM_ISCR_REG(MCM) 08932 #define MCM_ETBCC MCM_ETBCC_REG(MCM) 08933 #define MCM_ETBRL MCM_ETBRL_REG(MCM) 08934 #define MCM_ETBCNT MCM_ETBCNT_REG(MCM) 08935 #define MCM_PID MCM_PID_REG(MCM) 08936 08937 /*! 08938 * @} 08939 */ /* end of group MCM_Register_Accessor_Macros */ 08940 08941 08942 /*! 08943 * @} 08944 */ /* end of group MCM_Peripheral_Access_Layer */ 08945 08946 08947 /* ---------------------------------------------------------------------------- 08948 -- MPU Peripheral Access Layer 08949 ---------------------------------------------------------------------------- */ 08950 08951 /*! 08952 * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer 08953 * @{ 08954 */ 08955 08956 /** MPU - Register Layout Typedef */ 08957 typedef struct { 08958 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */ 08959 uint8_t RESERVED_0[12]; 08960 struct { /* offset: 0x10, array step: 0x8 */ 08961 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */ 08962 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */ 08963 } SP[5]; 08964 uint8_t RESERVED_1[968]; 08965 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */ 08966 uint8_t RESERVED_2[832]; 08967 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */ 08968 } MPU_Type, *MPU_MemMapPtr; 08969 08970 /* ---------------------------------------------------------------------------- 08971 -- MPU - Register accessor macros 08972 ---------------------------------------------------------------------------- */ 08973 08974 /*! 08975 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros 08976 * @{ 08977 */ 08978 08979 08980 /* MPU - Register accessors */ 08981 #define MPU_CESR_REG(base) ((base)->CESR) 08982 #define MPU_EAR_REG(base,index) ((base)->SP[index].EAR) 08983 #define MPU_EDR_REG(base,index) ((base)->SP[index].EDR) 08984 #define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2]) 08985 #define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index]) 08986 08987 /*! 08988 * @} 08989 */ /* end of group MPU_Register_Accessor_Macros */ 08990 08991 08992 /* ---------------------------------------------------------------------------- 08993 -- MPU Register Masks 08994 ---------------------------------------------------------------------------- */ 08995 08996 /*! 08997 * @addtogroup MPU_Register_Masks MPU Register Masks 08998 * @{ 08999 */ 09000 09001 /* CESR Bit Fields */ 09002 #define MPU_CESR_VLD_MASK 0x1u 09003 #define MPU_CESR_VLD_SHIFT 0 09004 #define MPU_CESR_NRGD_MASK 0xF00u 09005 #define MPU_CESR_NRGD_SHIFT 8 09006 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK) 09007 #define MPU_CESR_NSP_MASK 0xF000u 09008 #define MPU_CESR_NSP_SHIFT 12 09009 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK) 09010 #define MPU_CESR_HRL_MASK 0xF0000u 09011 #define MPU_CESR_HRL_SHIFT 16 09012 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK) 09013 #define MPU_CESR_SPERR_MASK 0xF8000000u 09014 #define MPU_CESR_SPERR_SHIFT 27 09015 #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK) 09016 /* EAR Bit Fields */ 09017 #define MPU_EAR_EADDR_MASK 0xFFFFFFFFu 09018 #define MPU_EAR_EADDR_SHIFT 0 09019 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK) 09020 /* EDR Bit Fields */ 09021 #define MPU_EDR_ERW_MASK 0x1u 09022 #define MPU_EDR_ERW_SHIFT 0 09023 #define MPU_EDR_EATTR_MASK 0xEu 09024 #define MPU_EDR_EATTR_SHIFT 1 09025 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK) 09026 #define MPU_EDR_EMN_MASK 0xF0u 09027 #define MPU_EDR_EMN_SHIFT 4 09028 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK) 09029 #define MPU_EDR_EPID_MASK 0xFF00u 09030 #define MPU_EDR_EPID_SHIFT 8 09031 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK) 09032 #define MPU_EDR_EACD_MASK 0xFFFF0000u 09033 #define MPU_EDR_EACD_SHIFT 16 09034 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK) 09035 /* WORD Bit Fields */ 09036 #define MPU_WORD_VLD_MASK 0x1u 09037 #define MPU_WORD_VLD_SHIFT 0 09038 #define MPU_WORD_M0UM_MASK 0x7u 09039 #define MPU_WORD_M0UM_SHIFT 0 09040 #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK) 09041 #define MPU_WORD_M0SM_MASK 0x18u 09042 #define MPU_WORD_M0SM_SHIFT 3 09043 #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK) 09044 #define MPU_WORD_M0PE_MASK 0x20u 09045 #define MPU_WORD_M0PE_SHIFT 5 09046 #define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u 09047 #define MPU_WORD_ENDADDR_SHIFT 5 09048 #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK) 09049 #define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u 09050 #define MPU_WORD_SRTADDR_SHIFT 5 09051 #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK) 09052 #define MPU_WORD_M1UM_MASK 0x1C0u 09053 #define MPU_WORD_M1UM_SHIFT 6 09054 #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK) 09055 #define MPU_WORD_M1SM_MASK 0x600u 09056 #define MPU_WORD_M1SM_SHIFT 9 09057 #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK) 09058 #define MPU_WORD_M1PE_MASK 0x800u 09059 #define MPU_WORD_M1PE_SHIFT 11 09060 #define MPU_WORD_M2UM_MASK 0x7000u 09061 #define MPU_WORD_M2UM_SHIFT 12 09062 #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK) 09063 #define MPU_WORD_M2SM_MASK 0x18000u 09064 #define MPU_WORD_M2SM_SHIFT 15 09065 #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK) 09066 #define MPU_WORD_PIDMASK_MASK 0xFF0000u 09067 #define MPU_WORD_PIDMASK_SHIFT 16 09068 #define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK) 09069 #define MPU_WORD_M2PE_MASK 0x20000u 09070 #define MPU_WORD_M2PE_SHIFT 17 09071 #define MPU_WORD_M3UM_MASK 0x1C0000u 09072 #define MPU_WORD_M3UM_SHIFT 18 09073 #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK) 09074 #define MPU_WORD_M3SM_MASK 0x600000u 09075 #define MPU_WORD_M3SM_SHIFT 21 09076 #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK) 09077 #define MPU_WORD_M3PE_MASK 0x800000u 09078 #define MPU_WORD_M3PE_SHIFT 23 09079 #define MPU_WORD_PID_MASK 0xFF000000u 09080 #define MPU_WORD_PID_SHIFT 24 09081 #define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK) 09082 #define MPU_WORD_M4WE_MASK 0x1000000u 09083 #define MPU_WORD_M4WE_SHIFT 24 09084 #define MPU_WORD_M4RE_MASK 0x2000000u 09085 #define MPU_WORD_M4RE_SHIFT 25 09086 #define MPU_WORD_M5WE_MASK 0x4000000u 09087 #define MPU_WORD_M5WE_SHIFT 26 09088 #define MPU_WORD_M5RE_MASK 0x8000000u 09089 #define MPU_WORD_M5RE_SHIFT 27 09090 #define MPU_WORD_M6WE_MASK 0x10000000u 09091 #define MPU_WORD_M6WE_SHIFT 28 09092 #define MPU_WORD_M6RE_MASK 0x20000000u 09093 #define MPU_WORD_M6RE_SHIFT 29 09094 #define MPU_WORD_M7WE_MASK 0x40000000u 09095 #define MPU_WORD_M7WE_SHIFT 30 09096 #define MPU_WORD_M7RE_MASK 0x80000000u 09097 #define MPU_WORD_M7RE_SHIFT 31 09098 /* RGDAAC Bit Fields */ 09099 #define MPU_RGDAAC_M0UM_MASK 0x7u 09100 #define MPU_RGDAAC_M0UM_SHIFT 0 09101 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK) 09102 #define MPU_RGDAAC_M0SM_MASK 0x18u 09103 #define MPU_RGDAAC_M0SM_SHIFT 3 09104 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK) 09105 #define MPU_RGDAAC_M0PE_MASK 0x20u 09106 #define MPU_RGDAAC_M0PE_SHIFT 5 09107 #define MPU_RGDAAC_M1UM_MASK 0x1C0u 09108 #define MPU_RGDAAC_M1UM_SHIFT 6 09109 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK) 09110 #define MPU_RGDAAC_M1SM_MASK 0x600u 09111 #define MPU_RGDAAC_M1SM_SHIFT 9 09112 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK) 09113 #define MPU_RGDAAC_M1PE_MASK 0x800u 09114 #define MPU_RGDAAC_M1PE_SHIFT 11 09115 #define MPU_RGDAAC_M2UM_MASK 0x7000u 09116 #define MPU_RGDAAC_M2UM_SHIFT 12 09117 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK) 09118 #define MPU_RGDAAC_M2SM_MASK 0x18000u 09119 #define MPU_RGDAAC_M2SM_SHIFT 15 09120 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK) 09121 #define MPU_RGDAAC_M2PE_MASK 0x20000u 09122 #define MPU_RGDAAC_M2PE_SHIFT 17 09123 #define MPU_RGDAAC_M3UM_MASK 0x1C0000u 09124 #define MPU_RGDAAC_M3UM_SHIFT 18 09125 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK) 09126 #define MPU_RGDAAC_M3SM_MASK 0x600000u 09127 #define MPU_RGDAAC_M3SM_SHIFT 21 09128 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK) 09129 #define MPU_RGDAAC_M3PE_MASK 0x800000u 09130 #define MPU_RGDAAC_M3PE_SHIFT 23 09131 #define MPU_RGDAAC_M4WE_MASK 0x1000000u 09132 #define MPU_RGDAAC_M4WE_SHIFT 24 09133 #define MPU_RGDAAC_M4RE_MASK 0x2000000u 09134 #define MPU_RGDAAC_M4RE_SHIFT 25 09135 #define MPU_RGDAAC_M5WE_MASK 0x4000000u 09136 #define MPU_RGDAAC_M5WE_SHIFT 26 09137 #define MPU_RGDAAC_M5RE_MASK 0x8000000u 09138 #define MPU_RGDAAC_M5RE_SHIFT 27 09139 #define MPU_RGDAAC_M6WE_MASK 0x10000000u 09140 #define MPU_RGDAAC_M6WE_SHIFT 28 09141 #define MPU_RGDAAC_M6RE_MASK 0x20000000u 09142 #define MPU_RGDAAC_M6RE_SHIFT 29 09143 #define MPU_RGDAAC_M7WE_MASK 0x40000000u 09144 #define MPU_RGDAAC_M7WE_SHIFT 30 09145 #define MPU_RGDAAC_M7RE_MASK 0x80000000u 09146 #define MPU_RGDAAC_M7RE_SHIFT 31 09147 09148 /*! 09149 * @} 09150 */ /* end of group MPU_Register_Masks */ 09151 09152 09153 /* MPU - Peripheral instance base addresses */ 09154 /** Peripheral MPU base address */ 09155 #define MPU_BASE (0x4000D000u) 09156 /** Peripheral MPU base pointer */ 09157 #define MPU ((MPU_Type *)MPU_BASE) 09158 #define MPU_BASE_PTR (MPU) 09159 /** Array initializer of MPU peripheral base addresses */ 09160 #define MPU_BASE_ADDRS { MPU_BASE } 09161 /** Array initializer of MPU peripheral base pointers */ 09162 #define MPU_BASE_PTRS { MPU } 09163 09164 /* ---------------------------------------------------------------------------- 09165 -- MPU - Register accessor macros 09166 ---------------------------------------------------------------------------- */ 09167 09168 /*! 09169 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros 09170 * @{ 09171 */ 09172 09173 09174 /* MPU - Register instance definitions */ 09175 /* MPU */ 09176 #define MPU_CESR MPU_CESR_REG(MPU) 09177 #define MPU_EAR0 MPU_EAR_REG(MPU,0) 09178 #define MPU_EDR0 MPU_EDR_REG(MPU,0) 09179 #define MPU_EAR1 MPU_EAR_REG(MPU,1) 09180 #define MPU_EDR1 MPU_EDR_REG(MPU,1) 09181 #define MPU_EAR2 MPU_EAR_REG(MPU,2) 09182 #define MPU_EDR2 MPU_EDR_REG(MPU,2) 09183 #define MPU_EAR3 MPU_EAR_REG(MPU,3) 09184 #define MPU_EDR3 MPU_EDR_REG(MPU,3) 09185 #define MPU_EAR4 MPU_EAR_REG(MPU,4) 09186 #define MPU_EDR4 MPU_EDR_REG(MPU,4) 09187 #define MPU_RGD0_WORD0 MPU_WORD_REG(MPU,0,0) 09188 #define MPU_RGD0_WORD1 MPU_WORD_REG(MPU,0,1) 09189 #define MPU_RGD0_WORD2 MPU_WORD_REG(MPU,0,2) 09190 #define MPU_RGD0_WORD3 MPU_WORD_REG(MPU,0,3) 09191 #define MPU_RGD1_WORD0 MPU_WORD_REG(MPU,1,0) 09192 #define MPU_RGD1_WORD1 MPU_WORD_REG(MPU,1,1) 09193 #define MPU_RGD1_WORD2 MPU_WORD_REG(MPU,1,2) 09194 #define MPU_RGD1_WORD3 MPU_WORD_REG(MPU,1,3) 09195 #define MPU_RGD2_WORD0 MPU_WORD_REG(MPU,2,0) 09196 #define MPU_RGD2_WORD1 MPU_WORD_REG(MPU,2,1) 09197 #define MPU_RGD2_WORD2 MPU_WORD_REG(MPU,2,2) 09198 #define MPU_RGD2_WORD3 MPU_WORD_REG(MPU,2,3) 09199 #define MPU_RGD3_WORD0 MPU_WORD_REG(MPU,3,0) 09200 #define MPU_RGD3_WORD1 MPU_WORD_REG(MPU,3,1) 09201 #define MPU_RGD3_WORD2 MPU_WORD_REG(MPU,3,2) 09202 #define MPU_RGD3_WORD3 MPU_WORD_REG(MPU,3,3) 09203 #define MPU_RGD4_WORD0 MPU_WORD_REG(MPU,4,0) 09204 #define MPU_RGD4_WORD1 MPU_WORD_REG(MPU,4,1) 09205 #define MPU_RGD4_WORD2 MPU_WORD_REG(MPU,4,2) 09206 #define MPU_RGD4_WORD3 MPU_WORD_REG(MPU,4,3) 09207 #define MPU_RGD5_WORD0 MPU_WORD_REG(MPU,5,0) 09208 #define MPU_RGD5_WORD1 MPU_WORD_REG(MPU,5,1) 09209 #define MPU_RGD5_WORD2 MPU_WORD_REG(MPU,5,2) 09210 #define MPU_RGD5_WORD3 MPU_WORD_REG(MPU,5,3) 09211 #define MPU_RGD6_WORD0 MPU_WORD_REG(MPU,6,0) 09212 #define MPU_RGD6_WORD1 MPU_WORD_REG(MPU,6,1) 09213 #define MPU_RGD6_WORD2 MPU_WORD_REG(MPU,6,2) 09214 #define MPU_RGD6_WORD3 MPU_WORD_REG(MPU,6,3) 09215 #define MPU_RGD7_WORD0 MPU_WORD_REG(MPU,7,0) 09216 #define MPU_RGD7_WORD1 MPU_WORD_REG(MPU,7,1) 09217 #define MPU_RGD7_WORD2 MPU_WORD_REG(MPU,7,2) 09218 #define MPU_RGD7_WORD3 MPU_WORD_REG(MPU,7,3) 09219 #define MPU_RGD8_WORD0 MPU_WORD_REG(MPU,8,0) 09220 #define MPU_RGD8_WORD1 MPU_WORD_REG(MPU,8,1) 09221 #define MPU_RGD8_WORD2 MPU_WORD_REG(MPU,8,2) 09222 #define MPU_RGD8_WORD3 MPU_WORD_REG(MPU,8,3) 09223 #define MPU_RGD9_WORD0 MPU_WORD_REG(MPU,9,0) 09224 #define MPU_RGD9_WORD1 MPU_WORD_REG(MPU,9,1) 09225 #define MPU_RGD9_WORD2 MPU_WORD_REG(MPU,9,2) 09226 #define MPU_RGD9_WORD3 MPU_WORD_REG(MPU,9,3) 09227 #define MPU_RGD10_WORD0 MPU_WORD_REG(MPU,10,0) 09228 #define MPU_RGD10_WORD1 MPU_WORD_REG(MPU,10,1) 09229 #define MPU_RGD10_WORD2 MPU_WORD_REG(MPU,10,2) 09230 #define MPU_RGD10_WORD3 MPU_WORD_REG(MPU,10,3) 09231 #define MPU_RGD11_WORD0 MPU_WORD_REG(MPU,11,0) 09232 #define MPU_RGD11_WORD1 MPU_WORD_REG(MPU,11,1) 09233 #define MPU_RGD11_WORD2 MPU_WORD_REG(MPU,11,2) 09234 #define MPU_RGD11_WORD3 MPU_WORD_REG(MPU,11,3) 09235 #define MPU_RGDAAC0 MPU_RGDAAC_REG(MPU,0) 09236 #define MPU_RGDAAC1 MPU_RGDAAC_REG(MPU,1) 09237 #define MPU_RGDAAC2 MPU_RGDAAC_REG(MPU,2) 09238 #define MPU_RGDAAC3 MPU_RGDAAC_REG(MPU,3) 09239 #define MPU_RGDAAC4 MPU_RGDAAC_REG(MPU,4) 09240 #define MPU_RGDAAC5 MPU_RGDAAC_REG(MPU,5) 09241 #define MPU_RGDAAC6 MPU_RGDAAC_REG(MPU,6) 09242 #define MPU_RGDAAC7 MPU_RGDAAC_REG(MPU,7) 09243 #define MPU_RGDAAC8 MPU_RGDAAC_REG(MPU,8) 09244 #define MPU_RGDAAC9 MPU_RGDAAC_REG(MPU,9) 09245 #define MPU_RGDAAC10 MPU_RGDAAC_REG(MPU,10) 09246 #define MPU_RGDAAC11 MPU_RGDAAC_REG(MPU,11) 09247 09248 /* MPU - Register array accessors */ 09249 #define MPU_EAR(index) MPU_EAR_REG(MPU,index) 09250 #define MPU_EDR(index) MPU_EDR_REG(MPU,index) 09251 #define MPU_WORD(index,index2) MPU_WORD_REG(MPU,index,index2) 09252 #define MPU_RGDAAC(index) MPU_RGDAAC_REG(MPU,index) 09253 09254 /*! 09255 * @} 09256 */ /* end of group MPU_Register_Accessor_Macros */ 09257 09258 09259 /*! 09260 * @} 09261 */ /* end of group MPU_Peripheral_Access_Layer */ 09262 09263 09264 /* ---------------------------------------------------------------------------- 09265 -- NV Peripheral Access Layer 09266 ---------------------------------------------------------------------------- */ 09267 09268 /*! 09269 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer 09270 * @{ 09271 */ 09272 09273 /** NV - Register Layout Typedef */ 09274 typedef struct { 09275 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ 09276 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ 09277 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ 09278 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ 09279 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ 09280 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ 09281 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ 09282 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ 09283 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ 09284 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ 09285 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ 09286 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ 09287 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ 09288 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ 09289 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */ 09290 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */ 09291 } NV_Type, *NV_MemMapPtr; 09292 09293 /* ---------------------------------------------------------------------------- 09294 -- NV - Register accessor macros 09295 ---------------------------------------------------------------------------- */ 09296 09297 /*! 09298 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros 09299 * @{ 09300 */ 09301 09302 09303 /* NV - Register accessors */ 09304 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3) 09305 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) 09306 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) 09307 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) 09308 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) 09309 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) 09310 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) 09311 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) 09312 #define NV_FPROT3_REG(base) ((base)->FPROT3) 09313 #define NV_FPROT2_REG(base) ((base)->FPROT2) 09314 #define NV_FPROT1_REG(base) ((base)->FPROT1) 09315 #define NV_FPROT0_REG(base) ((base)->FPROT0) 09316 #define NV_FSEC_REG(base) ((base)->FSEC) 09317 #define NV_FOPT_REG(base) ((base)->FOPT) 09318 #define NV_FEPROT_REG(base) ((base)->FEPROT) 09319 #define NV_FDPROT_REG(base) ((base)->FDPROT) 09320 09321 /*! 09322 * @} 09323 */ /* end of group NV_Register_Accessor_Macros */ 09324 09325 09326 /* ---------------------------------------------------------------------------- 09327 -- NV Register Masks 09328 ---------------------------------------------------------------------------- */ 09329 09330 /*! 09331 * @addtogroup NV_Register_Masks NV Register Masks 09332 * @{ 09333 */ 09334 09335 /* BACKKEY3 Bit Fields */ 09336 #define NV_BACKKEY3_KEY_MASK 0xFFu 09337 #define NV_BACKKEY3_KEY_SHIFT 0 09338 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK) 09339 /* BACKKEY2 Bit Fields */ 09340 #define NV_BACKKEY2_KEY_MASK 0xFFu 09341 #define NV_BACKKEY2_KEY_SHIFT 0 09342 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK) 09343 /* BACKKEY1 Bit Fields */ 09344 #define NV_BACKKEY1_KEY_MASK 0xFFu 09345 #define NV_BACKKEY1_KEY_SHIFT 0 09346 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK) 09347 /* BACKKEY0 Bit Fields */ 09348 #define NV_BACKKEY0_KEY_MASK 0xFFu 09349 #define NV_BACKKEY0_KEY_SHIFT 0 09350 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK) 09351 /* BACKKEY7 Bit Fields */ 09352 #define NV_BACKKEY7_KEY_MASK 0xFFu 09353 #define NV_BACKKEY7_KEY_SHIFT 0 09354 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK) 09355 /* BACKKEY6 Bit Fields */ 09356 #define NV_BACKKEY6_KEY_MASK 0xFFu 09357 #define NV_BACKKEY6_KEY_SHIFT 0 09358 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK) 09359 /* BACKKEY5 Bit Fields */ 09360 #define NV_BACKKEY5_KEY_MASK 0xFFu 09361 #define NV_BACKKEY5_KEY_SHIFT 0 09362 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK) 09363 /* BACKKEY4 Bit Fields */ 09364 #define NV_BACKKEY4_KEY_MASK 0xFFu 09365 #define NV_BACKKEY4_KEY_SHIFT 0 09366 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK) 09367 /* FPROT3 Bit Fields */ 09368 #define NV_FPROT3_PROT_MASK 0xFFu 09369 #define NV_FPROT3_PROT_SHIFT 0 09370 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK) 09371 /* FPROT2 Bit Fields */ 09372 #define NV_FPROT2_PROT_MASK 0xFFu 09373 #define NV_FPROT2_PROT_SHIFT 0 09374 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK) 09375 /* FPROT1 Bit Fields */ 09376 #define NV_FPROT1_PROT_MASK 0xFFu 09377 #define NV_FPROT1_PROT_SHIFT 0 09378 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK) 09379 /* FPROT0 Bit Fields */ 09380 #define NV_FPROT0_PROT_MASK 0xFFu 09381 #define NV_FPROT0_PROT_SHIFT 0 09382 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK) 09383 /* FSEC Bit Fields */ 09384 #define NV_FSEC_SEC_MASK 0x3u 09385 #define NV_FSEC_SEC_SHIFT 0 09386 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK) 09387 #define NV_FSEC_FSLACC_MASK 0xCu 09388 #define NV_FSEC_FSLACC_SHIFT 2 09389 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK) 09390 #define NV_FSEC_MEEN_MASK 0x30u 09391 #define NV_FSEC_MEEN_SHIFT 4 09392 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK) 09393 #define NV_FSEC_KEYEN_MASK 0xC0u 09394 #define NV_FSEC_KEYEN_SHIFT 6 09395 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK) 09396 /* FOPT Bit Fields */ 09397 #define NV_FOPT_LPBOOT_MASK 0x1u 09398 #define NV_FOPT_LPBOOT_SHIFT 0 09399 #define NV_FOPT_EZPORT_DIS_MASK 0x2u 09400 #define NV_FOPT_EZPORT_DIS_SHIFT 1 09401 /* FEPROT Bit Fields */ 09402 #define NV_FEPROT_EPROT_MASK 0xFFu 09403 #define NV_FEPROT_EPROT_SHIFT 0 09404 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK) 09405 /* FDPROT Bit Fields */ 09406 #define NV_FDPROT_DPROT_MASK 0xFFu 09407 #define NV_FDPROT_DPROT_SHIFT 0 09408 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK) 09409 09410 /*! 09411 * @} 09412 */ /* end of group NV_Register_Masks */ 09413 09414 09415 /* NV - Peripheral instance base addresses */ 09416 /** Peripheral FTFE_FlashConfig base address */ 09417 #define FTFE_FlashConfig_BASE (0x400u) 09418 /** Peripheral FTFE_FlashConfig base pointer */ 09419 #define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE) 09420 #define FTFE_FlashConfig_BASE_PTR (FTFE_FlashConfig) 09421 /** Array initializer of NV peripheral base addresses */ 09422 #define NV_BASE_ADDRS { FTFE_FlashConfig_BASE } 09423 /** Array initializer of NV peripheral base pointers */ 09424 #define NV_BASE_PTRS { FTFE_FlashConfig } 09425 09426 /* ---------------------------------------------------------------------------- 09427 -- NV - Register accessor macros 09428 ---------------------------------------------------------------------------- */ 09429 09430 /*! 09431 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros 09432 * @{ 09433 */ 09434 09435 09436 /* NV - Register instance definitions */ 09437 /* FTFE_FlashConfig */ 09438 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFE_FlashConfig) 09439 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFE_FlashConfig) 09440 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFE_FlashConfig) 09441 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFE_FlashConfig) 09442 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFE_FlashConfig) 09443 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFE_FlashConfig) 09444 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFE_FlashConfig) 09445 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFE_FlashConfig) 09446 #define NV_FPROT3 NV_FPROT3_REG(FTFE_FlashConfig) 09447 #define NV_FPROT2 NV_FPROT2_REG(FTFE_FlashConfig) 09448 #define NV_FPROT1 NV_FPROT1_REG(FTFE_FlashConfig) 09449 #define NV_FPROT0 NV_FPROT0_REG(FTFE_FlashConfig) 09450 #define NV_FSEC NV_FSEC_REG(FTFE_FlashConfig) 09451 #define NV_FOPT NV_FOPT_REG(FTFE_FlashConfig) 09452 #define NV_FEPROT NV_FEPROT_REG(FTFE_FlashConfig) 09453 #define NV_FDPROT NV_FDPROT_REG(FTFE_FlashConfig) 09454 09455 /*! 09456 * @} 09457 */ /* end of group NV_Register_Accessor_Macros */ 09458 09459 09460 /*! 09461 * @} 09462 */ /* end of group NV_Peripheral_Access_Layer */ 09463 09464 09465 /* ---------------------------------------------------------------------------- 09466 -- OSC Peripheral Access Layer 09467 ---------------------------------------------------------------------------- */ 09468 09469 /*! 09470 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer 09471 * @{ 09472 */ 09473 09474 /** OSC - Register Layout Typedef */ 09475 typedef struct { 09476 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ 09477 } OSC_Type, *OSC_MemMapPtr; 09478 09479 /* ---------------------------------------------------------------------------- 09480 -- OSC - Register accessor macros 09481 ---------------------------------------------------------------------------- */ 09482 09483 /*! 09484 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros 09485 * @{ 09486 */ 09487 09488 09489 /* OSC - Register accessors */ 09490 #define OSC_CR_REG(base) ((base)->CR) 09491 09492 /*! 09493 * @} 09494 */ /* end of group OSC_Register_Accessor_Macros */ 09495 09496 09497 /* ---------------------------------------------------------------------------- 09498 -- OSC Register Masks 09499 ---------------------------------------------------------------------------- */ 09500 09501 /*! 09502 * @addtogroup OSC_Register_Masks OSC Register Masks 09503 * @{ 09504 */ 09505 09506 /* CR Bit Fields */ 09507 #define OSC_CR_SC16P_MASK 0x1u 09508 #define OSC_CR_SC16P_SHIFT 0 09509 #define OSC_CR_SC8P_MASK 0x2u 09510 #define OSC_CR_SC8P_SHIFT 1 09511 #define OSC_CR_SC4P_MASK 0x4u 09512 #define OSC_CR_SC4P_SHIFT 2 09513 #define OSC_CR_SC2P_MASK 0x8u 09514 #define OSC_CR_SC2P_SHIFT 3 09515 #define OSC_CR_EREFSTEN_MASK 0x20u 09516 #define OSC_CR_EREFSTEN_SHIFT 5 09517 #define OSC_CR_ERCLKEN_MASK 0x80u 09518 #define OSC_CR_ERCLKEN_SHIFT 7 09519 09520 /*! 09521 * @} 09522 */ /* end of group OSC_Register_Masks */ 09523 09524 09525 /* OSC - Peripheral instance base addresses */ 09526 /** Peripheral OSC base address */ 09527 #define OSC_BASE (0x40065000u) 09528 /** Peripheral OSC base pointer */ 09529 #define OSC ((OSC_Type *)OSC_BASE) 09530 #define OSC_BASE_PTR (OSC) 09531 /** Array initializer of OSC peripheral base addresses */ 09532 #define OSC_BASE_ADDRS { OSC_BASE } 09533 /** Array initializer of OSC peripheral base pointers */ 09534 #define OSC_BASE_PTRS { OSC } 09535 09536 /* ---------------------------------------------------------------------------- 09537 -- OSC - Register accessor macros 09538 ---------------------------------------------------------------------------- */ 09539 09540 /*! 09541 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros 09542 * @{ 09543 */ 09544 09545 09546 /* OSC - Register instance definitions */ 09547 /* OSC */ 09548 #define OSC_CR OSC_CR_REG(OSC) 09549 09550 /*! 09551 * @} 09552 */ /* end of group OSC_Register_Accessor_Macros */ 09553 09554 09555 /*! 09556 * @} 09557 */ /* end of group OSC_Peripheral_Access_Layer */ 09558 09559 09560 /* ---------------------------------------------------------------------------- 09561 -- PDB Peripheral Access Layer 09562 ---------------------------------------------------------------------------- */ 09563 09564 /*! 09565 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer 09566 * @{ 09567 */ 09568 09569 /** PDB - Register Layout Typedef */ 09570 typedef struct { 09571 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */ 09572 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */ 09573 __I uint32_t CNT; /**< Counter register, offset: 0x8 */ 09574 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */ 09575 struct { /* offset: 0x10, array step: 0x28 */ 09576 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */ 09577 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */ 09578 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */ 09579 uint8_t RESERVED_0[24]; 09580 } CH[2]; 09581 uint8_t RESERVED_0[240]; 09582 struct { /* offset: 0x150, array step: 0x8 */ 09583 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */ 09584 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */ 09585 } DAC[2]; 09586 uint8_t RESERVED_1[48]; 09587 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */ 09588 __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */ 09589 } PDB_Type, *PDB_MemMapPtr; 09590 09591 /* ---------------------------------------------------------------------------- 09592 -- PDB - Register accessor macros 09593 ---------------------------------------------------------------------------- */ 09594 09595 /*! 09596 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros 09597 * @{ 09598 */ 09599 09600 09601 /* PDB - Register accessors */ 09602 #define PDB_SC_REG(base) ((base)->SC) 09603 #define PDB_MOD_REG(base) ((base)->MOD) 09604 #define PDB_CNT_REG(base) ((base)->CNT) 09605 #define PDB_IDLY_REG(base) ((base)->IDLY) 09606 #define PDB_C1_REG(base,index) ((base)->CH[index].C1) 09607 #define PDB_S_REG(base,index) ((base)->CH[index].S) 09608 #define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) 09609 #define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) 09610 #define PDB_INT_REG(base,index) ((base)->DAC[index].INT) 09611 #define PDB_POEN_REG(base) ((base)->POEN) 09612 #define PDB_PODLY_REG(base,index) ((base)->PODLY[index]) 09613 09614 /*! 09615 * @} 09616 */ /* end of group PDB_Register_Accessor_Macros */ 09617 09618 09619 /* ---------------------------------------------------------------------------- 09620 -- PDB Register Masks 09621 ---------------------------------------------------------------------------- */ 09622 09623 /*! 09624 * @addtogroup PDB_Register_Masks PDB Register Masks 09625 * @{ 09626 */ 09627 09628 /* SC Bit Fields */ 09629 #define PDB_SC_LDOK_MASK 0x1u 09630 #define PDB_SC_LDOK_SHIFT 0 09631 #define PDB_SC_CONT_MASK 0x2u 09632 #define PDB_SC_CONT_SHIFT 1 09633 #define PDB_SC_MULT_MASK 0xCu 09634 #define PDB_SC_MULT_SHIFT 2 09635 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK) 09636 #define PDB_SC_PDBIE_MASK 0x20u 09637 #define PDB_SC_PDBIE_SHIFT 5 09638 #define PDB_SC_PDBIF_MASK 0x40u 09639 #define PDB_SC_PDBIF_SHIFT 6 09640 #define PDB_SC_PDBEN_MASK 0x80u 09641 #define PDB_SC_PDBEN_SHIFT 7 09642 #define PDB_SC_TRGSEL_MASK 0xF00u 09643 #define PDB_SC_TRGSEL_SHIFT 8 09644 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK) 09645 #define PDB_SC_PRESCALER_MASK 0x7000u 09646 #define PDB_SC_PRESCALER_SHIFT 12 09647 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK) 09648 #define PDB_SC_DMAEN_MASK 0x8000u 09649 #define PDB_SC_DMAEN_SHIFT 15 09650 #define PDB_SC_SWTRIG_MASK 0x10000u 09651 #define PDB_SC_SWTRIG_SHIFT 16 09652 #define PDB_SC_PDBEIE_MASK 0x20000u 09653 #define PDB_SC_PDBEIE_SHIFT 17 09654 #define PDB_SC_LDMOD_MASK 0xC0000u 09655 #define PDB_SC_LDMOD_SHIFT 18 09656 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK) 09657 /* MOD Bit Fields */ 09658 #define PDB_MOD_MOD_MASK 0xFFFFu 09659 #define PDB_MOD_MOD_SHIFT 0 09660 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK) 09661 /* CNT Bit Fields */ 09662 #define PDB_CNT_CNT_MASK 0xFFFFu 09663 #define PDB_CNT_CNT_SHIFT 0 09664 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK) 09665 /* IDLY Bit Fields */ 09666 #define PDB_IDLY_IDLY_MASK 0xFFFFu 09667 #define PDB_IDLY_IDLY_SHIFT 0 09668 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK) 09669 /* C1 Bit Fields */ 09670 #define PDB_C1_EN_MASK 0xFFu 09671 #define PDB_C1_EN_SHIFT 0 09672 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK) 09673 #define PDB_C1_TOS_MASK 0xFF00u 09674 #define PDB_C1_TOS_SHIFT 8 09675 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK) 09676 #define PDB_C1_BB_MASK 0xFF0000u 09677 #define PDB_C1_BB_SHIFT 16 09678 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK) 09679 /* S Bit Fields */ 09680 #define PDB_S_ERR_MASK 0xFFu 09681 #define PDB_S_ERR_SHIFT 0 09682 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK) 09683 #define PDB_S_CF_MASK 0xFF0000u 09684 #define PDB_S_CF_SHIFT 16 09685 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK) 09686 /* DLY Bit Fields */ 09687 #define PDB_DLY_DLY_MASK 0xFFFFu 09688 #define PDB_DLY_DLY_SHIFT 0 09689 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK) 09690 /* INTC Bit Fields */ 09691 #define PDB_INTC_TOE_MASK 0x1u 09692 #define PDB_INTC_TOE_SHIFT 0 09693 #define PDB_INTC_EXT_MASK 0x2u 09694 #define PDB_INTC_EXT_SHIFT 1 09695 /* INT Bit Fields */ 09696 #define PDB_INT_INT_MASK 0xFFFFu 09697 #define PDB_INT_INT_SHIFT 0 09698 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK) 09699 /* POEN Bit Fields */ 09700 #define PDB_POEN_POEN_MASK 0xFFu 09701 #define PDB_POEN_POEN_SHIFT 0 09702 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK) 09703 /* PODLY Bit Fields */ 09704 #define PDB_PODLY_DLY2_MASK 0xFFFFu 09705 #define PDB_PODLY_DLY2_SHIFT 0 09706 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK) 09707 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u 09708 #define PDB_PODLY_DLY1_SHIFT 16 09709 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK) 09710 09711 /*! 09712 * @} 09713 */ /* end of group PDB_Register_Masks */ 09714 09715 09716 /* PDB - Peripheral instance base addresses */ 09717 /** Peripheral PDB0 base address */ 09718 #define PDB0_BASE (0x40036000u) 09719 /** Peripheral PDB0 base pointer */ 09720 #define PDB0 ((PDB_Type *)PDB0_BASE) 09721 #define PDB0_BASE_PTR (PDB0) 09722 /** Array initializer of PDB peripheral base addresses */ 09723 #define PDB_BASE_ADDRS { PDB0_BASE } 09724 /** Array initializer of PDB peripheral base pointers */ 09725 #define PDB_BASE_PTRS { PDB0 } 09726 /** Interrupt vectors for the PDB peripheral type */ 09727 #define PDB_IRQS { PDB0_IRQn } 09728 09729 /* ---------------------------------------------------------------------------- 09730 -- PDB - Register accessor macros 09731 ---------------------------------------------------------------------------- */ 09732 09733 /*! 09734 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros 09735 * @{ 09736 */ 09737 09738 09739 /* PDB - Register instance definitions */ 09740 /* PDB0 */ 09741 #define PDB0_SC PDB_SC_REG(PDB0) 09742 #define PDB0_MOD PDB_MOD_REG(PDB0) 09743 #define PDB0_CNT PDB_CNT_REG(PDB0) 09744 #define PDB0_IDLY PDB_IDLY_REG(PDB0) 09745 #define PDB0_CH0C1 PDB_C1_REG(PDB0,0) 09746 #define PDB0_CH0S PDB_S_REG(PDB0,0) 09747 #define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0) 09748 #define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1) 09749 #define PDB0_CH1C1 PDB_C1_REG(PDB0,1) 09750 #define PDB0_CH1S PDB_S_REG(PDB0,1) 09751 #define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0) 09752 #define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1) 09753 #define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0) 09754 #define PDB0_DACINT0 PDB_INT_REG(PDB0,0) 09755 #define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1) 09756 #define PDB0_DACINT1 PDB_INT_REG(PDB0,1) 09757 #define PDB0_POEN PDB_POEN_REG(PDB0) 09758 #define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0) 09759 #define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1) 09760 #define PDB0_PO2DLY PDB_PODLY_REG(PDB0,2) 09761 09762 /* PDB - Register array accessors */ 09763 #define PDB0_C1(index) PDB_C1_REG(PDB0,index) 09764 #define PDB0_S(index) PDB_S_REG(PDB0,index) 09765 #define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2) 09766 #define PDB0_INTC(index) PDB_INTC_REG(PDB0,index) 09767 #define PDB0_INT(index) PDB_INT_REG(PDB0,index) 09768 #define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index) 09769 09770 /*! 09771 * @} 09772 */ /* end of group PDB_Register_Accessor_Macros */ 09773 09774 09775 /*! 09776 * @} 09777 */ /* end of group PDB_Peripheral_Access_Layer */ 09778 09779 09780 /* ---------------------------------------------------------------------------- 09781 -- PIT Peripheral Access Layer 09782 ---------------------------------------------------------------------------- */ 09783 09784 /*! 09785 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer 09786 * @{ 09787 */ 09788 09789 /** PIT - Register Layout Typedef */ 09790 typedef struct { 09791 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ 09792 uint8_t RESERVED_0[252]; 09793 struct { /* offset: 0x100, array step: 0x10 */ 09794 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ 09795 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ 09796 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ 09797 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ 09798 } CHANNEL[4]; 09799 } PIT_Type, *PIT_MemMapPtr; 09800 09801 /* ---------------------------------------------------------------------------- 09802 -- PIT - Register accessor macros 09803 ---------------------------------------------------------------------------- */ 09804 09805 /*! 09806 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros 09807 * @{ 09808 */ 09809 09810 09811 /* PIT - Register accessors */ 09812 #define PIT_MCR_REG(base) ((base)->MCR) 09813 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) 09814 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) 09815 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) 09816 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) 09817 09818 /*! 09819 * @} 09820 */ /* end of group PIT_Register_Accessor_Macros */ 09821 09822 09823 /* ---------------------------------------------------------------------------- 09824 -- PIT Register Masks 09825 ---------------------------------------------------------------------------- */ 09826 09827 /*! 09828 * @addtogroup PIT_Register_Masks PIT Register Masks 09829 * @{ 09830 */ 09831 09832 /* MCR Bit Fields */ 09833 #define PIT_MCR_FRZ_MASK 0x1u 09834 #define PIT_MCR_FRZ_SHIFT 0 09835 #define PIT_MCR_MDIS_MASK 0x2u 09836 #define PIT_MCR_MDIS_SHIFT 1 09837 /* LDVAL Bit Fields */ 09838 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu 09839 #define PIT_LDVAL_TSV_SHIFT 0 09840 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK) 09841 /* CVAL Bit Fields */ 09842 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu 09843 #define PIT_CVAL_TVL_SHIFT 0 09844 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK) 09845 /* TCTRL Bit Fields */ 09846 #define PIT_TCTRL_TEN_MASK 0x1u 09847 #define PIT_TCTRL_TEN_SHIFT 0 09848 #define PIT_TCTRL_TIE_MASK 0x2u 09849 #define PIT_TCTRL_TIE_SHIFT 1 09850 #define PIT_TCTRL_CHN_MASK 0x4u 09851 #define PIT_TCTRL_CHN_SHIFT 2 09852 /* TFLG Bit Fields */ 09853 #define PIT_TFLG_TIF_MASK 0x1u 09854 #define PIT_TFLG_TIF_SHIFT 0 09855 09856 /*! 09857 * @} 09858 */ /* end of group PIT_Register_Masks */ 09859 09860 09861 /* PIT - Peripheral instance base addresses */ 09862 /** Peripheral PIT base address */ 09863 #define PIT_BASE (0x40037000u) 09864 /** Peripheral PIT base pointer */ 09865 #define PIT ((PIT_Type *)PIT_BASE) 09866 #define PIT_BASE_PTR (PIT) 09867 /** Array initializer of PIT peripheral base addresses */ 09868 #define PIT_BASE_ADDRS { PIT_BASE } 09869 /** Array initializer of PIT peripheral base pointers */ 09870 #define PIT_BASE_PTRS { PIT } 09871 /** Interrupt vectors for the PIT peripheral type */ 09872 #define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } 09873 09874 /* ---------------------------------------------------------------------------- 09875 -- PIT - Register accessor macros 09876 ---------------------------------------------------------------------------- */ 09877 09878 /*! 09879 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros 09880 * @{ 09881 */ 09882 09883 09884 /* PIT - Register instance definitions */ 09885 /* PIT */ 09886 #define PIT_MCR PIT_MCR_REG(PIT) 09887 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0) 09888 #define PIT_CVAL0 PIT_CVAL_REG(PIT,0) 09889 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0) 09890 #define PIT_TFLG0 PIT_TFLG_REG(PIT,0) 09891 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1) 09892 #define PIT_CVAL1 PIT_CVAL_REG(PIT,1) 09893 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1) 09894 #define PIT_TFLG1 PIT_TFLG_REG(PIT,1) 09895 #define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2) 09896 #define PIT_CVAL2 PIT_CVAL_REG(PIT,2) 09897 #define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2) 09898 #define PIT_TFLG2 PIT_TFLG_REG(PIT,2) 09899 #define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3) 09900 #define PIT_CVAL3 PIT_CVAL_REG(PIT,3) 09901 #define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3) 09902 #define PIT_TFLG3 PIT_TFLG_REG(PIT,3) 09903 09904 /* PIT - Register array accessors */ 09905 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index) 09906 #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index) 09907 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index) 09908 #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index) 09909 09910 /*! 09911 * @} 09912 */ /* end of group PIT_Register_Accessor_Macros */ 09913 09914 09915 /*! 09916 * @} 09917 */ /* end of group PIT_Peripheral_Access_Layer */ 09918 09919 09920 /* ---------------------------------------------------------------------------- 09921 -- PMC Peripheral Access Layer 09922 ---------------------------------------------------------------------------- */ 09923 09924 /*! 09925 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer 09926 * @{ 09927 */ 09928 09929 /** PMC - Register Layout Typedef */ 09930 typedef struct { 09931 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ 09932 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ 09933 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ 09934 } PMC_Type, *PMC_MemMapPtr; 09935 09936 /* ---------------------------------------------------------------------------- 09937 -- PMC - Register accessor macros 09938 ---------------------------------------------------------------------------- */ 09939 09940 /*! 09941 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros 09942 * @{ 09943 */ 09944 09945 09946 /* PMC - Register accessors */ 09947 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1) 09948 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2) 09949 #define PMC_REGSC_REG(base) ((base)->REGSC) 09950 09951 /*! 09952 * @} 09953 */ /* end of group PMC_Register_Accessor_Macros */ 09954 09955 09956 /* ---------------------------------------------------------------------------- 09957 -- PMC Register Masks 09958 ---------------------------------------------------------------------------- */ 09959 09960 /*! 09961 * @addtogroup PMC_Register_Masks PMC Register Masks 09962 * @{ 09963 */ 09964 09965 /* LVDSC1 Bit Fields */ 09966 #define PMC_LVDSC1_LVDV_MASK 0x3u 09967 #define PMC_LVDSC1_LVDV_SHIFT 0 09968 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) 09969 #define PMC_LVDSC1_LVDRE_MASK 0x10u 09970 #define PMC_LVDSC1_LVDRE_SHIFT 4 09971 #define PMC_LVDSC1_LVDIE_MASK 0x20u 09972 #define PMC_LVDSC1_LVDIE_SHIFT 5 09973 #define PMC_LVDSC1_LVDACK_MASK 0x40u 09974 #define PMC_LVDSC1_LVDACK_SHIFT 6 09975 #define PMC_LVDSC1_LVDF_MASK 0x80u 09976 #define PMC_LVDSC1_LVDF_SHIFT 7 09977 /* LVDSC2 Bit Fields */ 09978 #define PMC_LVDSC2_LVWV_MASK 0x3u 09979 #define PMC_LVDSC2_LVWV_SHIFT 0 09980 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) 09981 #define PMC_LVDSC2_LVWIE_MASK 0x20u 09982 #define PMC_LVDSC2_LVWIE_SHIFT 5 09983 #define PMC_LVDSC2_LVWACK_MASK 0x40u 09984 #define PMC_LVDSC2_LVWACK_SHIFT 6 09985 #define PMC_LVDSC2_LVWF_MASK 0x80u 09986 #define PMC_LVDSC2_LVWF_SHIFT 7 09987 /* REGSC Bit Fields */ 09988 #define PMC_REGSC_BGBE_MASK 0x1u 09989 #define PMC_REGSC_BGBE_SHIFT 0 09990 #define PMC_REGSC_REGONS_MASK 0x4u 09991 #define PMC_REGSC_REGONS_SHIFT 2 09992 #define PMC_REGSC_ACKISO_MASK 0x8u 09993 #define PMC_REGSC_ACKISO_SHIFT 3 09994 #define PMC_REGSC_BGEN_MASK 0x10u 09995 #define PMC_REGSC_BGEN_SHIFT 4 09996 09997 /*! 09998 * @} 09999 */ /* end of group PMC_Register_Masks */ 10000 10001 10002 /* PMC - Peripheral instance base addresses */ 10003 /** Peripheral PMC base address */ 10004 #define PMC_BASE (0x4007D000u) 10005 /** Peripheral PMC base pointer */ 10006 #define PMC ((PMC_Type *)PMC_BASE) 10007 #define PMC_BASE_PTR (PMC) 10008 /** Array initializer of PMC peripheral base addresses */ 10009 #define PMC_BASE_ADDRS { PMC_BASE } 10010 /** Array initializer of PMC peripheral base pointers */ 10011 #define PMC_BASE_PTRS { PMC } 10012 /** Interrupt vectors for the PMC peripheral type */ 10013 #define PMC_IRQS { LVD_LVW_IRQn } 10014 10015 /* ---------------------------------------------------------------------------- 10016 -- PMC - Register accessor macros 10017 ---------------------------------------------------------------------------- */ 10018 10019 /*! 10020 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros 10021 * @{ 10022 */ 10023 10024 10025 /* PMC - Register instance definitions */ 10026 /* PMC */ 10027 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC) 10028 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC) 10029 #define PMC_REGSC PMC_REGSC_REG(PMC) 10030 10031 /*! 10032 * @} 10033 */ /* end of group PMC_Register_Accessor_Macros */ 10034 10035 10036 /*! 10037 * @} 10038 */ /* end of group PMC_Peripheral_Access_Layer */ 10039 10040 10041 /* ---------------------------------------------------------------------------- 10042 -- PORT Peripheral Access Layer 10043 ---------------------------------------------------------------------------- */ 10044 10045 /*! 10046 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer 10047 * @{ 10048 */ 10049 10050 /** PORT - Register Layout Typedef */ 10051 typedef struct { 10052 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ 10053 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ 10054 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ 10055 uint8_t RESERVED_0[24]; 10056 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ 10057 uint8_t RESERVED_1[28]; 10058 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ 10059 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ 10060 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ 10061 } PORT_Type, *PORT_MemMapPtr; 10062 10063 /* ---------------------------------------------------------------------------- 10064 -- PORT - Register accessor macros 10065 ---------------------------------------------------------------------------- */ 10066 10067 /*! 10068 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros 10069 * @{ 10070 */ 10071 10072 10073 /* PORT - Register accessors */ 10074 #define PORT_PCR_REG(base,index) ((base)->PCR[index]) 10075 #define PORT_GPCLR_REG(base) ((base)->GPCLR) 10076 #define PORT_GPCHR_REG(base) ((base)->GPCHR) 10077 #define PORT_ISFR_REG(base) ((base)->ISFR) 10078 #define PORT_DFER_REG(base) ((base)->DFER) 10079 #define PORT_DFCR_REG(base) ((base)->DFCR) 10080 #define PORT_DFWR_REG(base) ((base)->DFWR) 10081 10082 /*! 10083 * @} 10084 */ /* end of group PORT_Register_Accessor_Macros */ 10085 10086 10087 /* ---------------------------------------------------------------------------- 10088 -- PORT Register Masks 10089 ---------------------------------------------------------------------------- */ 10090 10091 /*! 10092 * @addtogroup PORT_Register_Masks PORT Register Masks 10093 * @{ 10094 */ 10095 10096 /* PCR Bit Fields */ 10097 #define PORT_PCR_PS_MASK 0x1u 10098 #define PORT_PCR_PS_SHIFT 0 10099 #define PORT_PCR_PE_MASK 0x2u 10100 #define PORT_PCR_PE_SHIFT 1 10101 #define PORT_PCR_SRE_MASK 0x4u 10102 #define PORT_PCR_SRE_SHIFT 2 10103 #define PORT_PCR_PFE_MASK 0x10u 10104 #define PORT_PCR_PFE_SHIFT 4 10105 #define PORT_PCR_ODE_MASK 0x20u 10106 #define PORT_PCR_ODE_SHIFT 5 10107 #define PORT_PCR_DSE_MASK 0x40u 10108 #define PORT_PCR_DSE_SHIFT 6 10109 #define PORT_PCR_MUX_MASK 0x700u 10110 #define PORT_PCR_MUX_SHIFT 8 10111 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK) 10112 #define PORT_PCR_LK_MASK 0x8000u 10113 #define PORT_PCR_LK_SHIFT 15 10114 #define PORT_PCR_IRQC_MASK 0xF0000u 10115 #define PORT_PCR_IRQC_SHIFT 16 10116 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK) 10117 #define PORT_PCR_ISF_MASK 0x1000000u 10118 #define PORT_PCR_ISF_SHIFT 24 10119 /* GPCLR Bit Fields */ 10120 #define PORT_GPCLR_GPWD_MASK 0xFFFFu 10121 #define PORT_GPCLR_GPWD_SHIFT 0 10122 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK) 10123 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u 10124 #define PORT_GPCLR_GPWE_SHIFT 16 10125 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK) 10126 /* GPCHR Bit Fields */ 10127 #define PORT_GPCHR_GPWD_MASK 0xFFFFu 10128 #define PORT_GPCHR_GPWD_SHIFT 0 10129 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK) 10130 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u 10131 #define PORT_GPCHR_GPWE_SHIFT 16 10132 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK) 10133 /* ISFR Bit Fields */ 10134 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu 10135 #define PORT_ISFR_ISF_SHIFT 0 10136 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK) 10137 /* DFER Bit Fields */ 10138 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu 10139 #define PORT_DFER_DFE_SHIFT 0 10140 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK) 10141 /* DFCR Bit Fields */ 10142 #define PORT_DFCR_CS_MASK 0x1u 10143 #define PORT_DFCR_CS_SHIFT 0 10144 /* DFWR Bit Fields */ 10145 #define PORT_DFWR_FILT_MASK 0x1Fu 10146 #define PORT_DFWR_FILT_SHIFT 0 10147 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK) 10148 10149 /*! 10150 * @} 10151 */ /* end of group PORT_Register_Masks */ 10152 10153 10154 /* PORT - Peripheral instance base addresses */ 10155 /** Peripheral PORTA base address */ 10156 #define PORTA_BASE (0x40049000u) 10157 /** Peripheral PORTA base pointer */ 10158 #define PORTA ((PORT_Type *)PORTA_BASE) 10159 #define PORTA_BASE_PTR (PORTA) 10160 /** Peripheral PORTB base address */ 10161 #define PORTB_BASE (0x4004A000u) 10162 /** Peripheral PORTB base pointer */ 10163 #define PORTB ((PORT_Type *)PORTB_BASE) 10164 #define PORTB_BASE_PTR (PORTB) 10165 /** Peripheral PORTC base address */ 10166 #define PORTC_BASE (0x4004B000u) 10167 /** Peripheral PORTC base pointer */ 10168 #define PORTC ((PORT_Type *)PORTC_BASE) 10169 #define PORTC_BASE_PTR (PORTC) 10170 /** Peripheral PORTD base address */ 10171 #define PORTD_BASE (0x4004C000u) 10172 /** Peripheral PORTD base pointer */ 10173 #define PORTD ((PORT_Type *)PORTD_BASE) 10174 #define PORTD_BASE_PTR (PORTD) 10175 /** Peripheral PORTE base address */ 10176 #define PORTE_BASE (0x4004D000u) 10177 /** Peripheral PORTE base pointer */ 10178 #define PORTE ((PORT_Type *)PORTE_BASE) 10179 #define PORTE_BASE_PTR (PORTE) 10180 /** Array initializer of PORT peripheral base addresses */ 10181 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } 10182 /** Array initializer of PORT peripheral base pointers */ 10183 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } 10184 /** Interrupt vectors for the PORT peripheral type */ 10185 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn } 10186 10187 /* ---------------------------------------------------------------------------- 10188 -- PORT - Register accessor macros 10189 ---------------------------------------------------------------------------- */ 10190 10191 /*! 10192 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros 10193 * @{ 10194 */ 10195 10196 10197 /* PORT - Register instance definitions */ 10198 /* PORTA */ 10199 #define PORTA_PCR0 PORT_PCR_REG(PORTA,0) 10200 #define PORTA_PCR1 PORT_PCR_REG(PORTA,1) 10201 #define PORTA_PCR2 PORT_PCR_REG(PORTA,2) 10202 #define PORTA_PCR3 PORT_PCR_REG(PORTA,3) 10203 #define PORTA_PCR4 PORT_PCR_REG(PORTA,4) 10204 #define PORTA_PCR5 PORT_PCR_REG(PORTA,5) 10205 #define PORTA_PCR6 PORT_PCR_REG(PORTA,6) 10206 #define PORTA_PCR7 PORT_PCR_REG(PORTA,7) 10207 #define PORTA_PCR8 PORT_PCR_REG(PORTA,8) 10208 #define PORTA_PCR9 PORT_PCR_REG(PORTA,9) 10209 #define PORTA_PCR10 PORT_PCR_REG(PORTA,10) 10210 #define PORTA_PCR11 PORT_PCR_REG(PORTA,11) 10211 #define PORTA_PCR12 PORT_PCR_REG(PORTA,12) 10212 #define PORTA_PCR13 PORT_PCR_REG(PORTA,13) 10213 #define PORTA_PCR14 PORT_PCR_REG(PORTA,14) 10214 #define PORTA_PCR15 PORT_PCR_REG(PORTA,15) 10215 #define PORTA_PCR16 PORT_PCR_REG(PORTA,16) 10216 #define PORTA_PCR17 PORT_PCR_REG(PORTA,17) 10217 #define PORTA_PCR18 PORT_PCR_REG(PORTA,18) 10218 #define PORTA_PCR19 PORT_PCR_REG(PORTA,19) 10219 #define PORTA_PCR20 PORT_PCR_REG(PORTA,20) 10220 #define PORTA_PCR21 PORT_PCR_REG(PORTA,21) 10221 #define PORTA_PCR22 PORT_PCR_REG(PORTA,22) 10222 #define PORTA_PCR23 PORT_PCR_REG(PORTA,23) 10223 #define PORTA_PCR24 PORT_PCR_REG(PORTA,24) 10224 #define PORTA_PCR25 PORT_PCR_REG(PORTA,25) 10225 #define PORTA_PCR26 PORT_PCR_REG(PORTA,26) 10226 #define PORTA_PCR27 PORT_PCR_REG(PORTA,27) 10227 #define PORTA_PCR28 PORT_PCR_REG(PORTA,28) 10228 #define PORTA_PCR29 PORT_PCR_REG(PORTA,29) 10229 #define PORTA_PCR30 PORT_PCR_REG(PORTA,30) 10230 #define PORTA_PCR31 PORT_PCR_REG(PORTA,31) 10231 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA) 10232 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA) 10233 #define PORTA_ISFR PORT_ISFR_REG(PORTA) 10234 /* PORTB */ 10235 #define PORTB_PCR0 PORT_PCR_REG(PORTB,0) 10236 #define PORTB_PCR1 PORT_PCR_REG(PORTB,1) 10237 #define PORTB_PCR2 PORT_PCR_REG(PORTB,2) 10238 #define PORTB_PCR3 PORT_PCR_REG(PORTB,3) 10239 #define PORTB_PCR4 PORT_PCR_REG(PORTB,4) 10240 #define PORTB_PCR5 PORT_PCR_REG(PORTB,5) 10241 #define PORTB_PCR6 PORT_PCR_REG(PORTB,6) 10242 #define PORTB_PCR7 PORT_PCR_REG(PORTB,7) 10243 #define PORTB_PCR8 PORT_PCR_REG(PORTB,8) 10244 #define PORTB_PCR9 PORT_PCR_REG(PORTB,9) 10245 #define PORTB_PCR10 PORT_PCR_REG(PORTB,10) 10246 #define PORTB_PCR11 PORT_PCR_REG(PORTB,11) 10247 #define PORTB_PCR12 PORT_PCR_REG(PORTB,12) 10248 #define PORTB_PCR13 PORT_PCR_REG(PORTB,13) 10249 #define PORTB_PCR14 PORT_PCR_REG(PORTB,14) 10250 #define PORTB_PCR15 PORT_PCR_REG(PORTB,15) 10251 #define PORTB_PCR16 PORT_PCR_REG(PORTB,16) 10252 #define PORTB_PCR17 PORT_PCR_REG(PORTB,17) 10253 #define PORTB_PCR18 PORT_PCR_REG(PORTB,18) 10254 #define PORTB_PCR19 PORT_PCR_REG(PORTB,19) 10255 #define PORTB_PCR20 PORT_PCR_REG(PORTB,20) 10256 #define PORTB_PCR21 PORT_PCR_REG(PORTB,21) 10257 #define PORTB_PCR22 PORT_PCR_REG(PORTB,22) 10258 #define PORTB_PCR23 PORT_PCR_REG(PORTB,23) 10259 #define PORTB_PCR24 PORT_PCR_REG(PORTB,24) 10260 #define PORTB_PCR25 PORT_PCR_REG(PORTB,25) 10261 #define PORTB_PCR26 PORT_PCR_REG(PORTB,26) 10262 #define PORTB_PCR27 PORT_PCR_REG(PORTB,27) 10263 #define PORTB_PCR28 PORT_PCR_REG(PORTB,28) 10264 #define PORTB_PCR29 PORT_PCR_REG(PORTB,29) 10265 #define PORTB_PCR30 PORT_PCR_REG(PORTB,30) 10266 #define PORTB_PCR31 PORT_PCR_REG(PORTB,31) 10267 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB) 10268 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB) 10269 #define PORTB_ISFR PORT_ISFR_REG(PORTB) 10270 /* PORTC */ 10271 #define PORTC_PCR0 PORT_PCR_REG(PORTC,0) 10272 #define PORTC_PCR1 PORT_PCR_REG(PORTC,1) 10273 #define PORTC_PCR2 PORT_PCR_REG(PORTC,2) 10274 #define PORTC_PCR3 PORT_PCR_REG(PORTC,3) 10275 #define PORTC_PCR4 PORT_PCR_REG(PORTC,4) 10276 #define PORTC_PCR5 PORT_PCR_REG(PORTC,5) 10277 #define PORTC_PCR6 PORT_PCR_REG(PORTC,6) 10278 #define PORTC_PCR7 PORT_PCR_REG(PORTC,7) 10279 #define PORTC_PCR8 PORT_PCR_REG(PORTC,8) 10280 #define PORTC_PCR9 PORT_PCR_REG(PORTC,9) 10281 #define PORTC_PCR10 PORT_PCR_REG(PORTC,10) 10282 #define PORTC_PCR11 PORT_PCR_REG(PORTC,11) 10283 #define PORTC_PCR12 PORT_PCR_REG(PORTC,12) 10284 #define PORTC_PCR13 PORT_PCR_REG(PORTC,13) 10285 #define PORTC_PCR14 PORT_PCR_REG(PORTC,14) 10286 #define PORTC_PCR15 PORT_PCR_REG(PORTC,15) 10287 #define PORTC_PCR16 PORT_PCR_REG(PORTC,16) 10288 #define PORTC_PCR17 PORT_PCR_REG(PORTC,17) 10289 #define PORTC_PCR18 PORT_PCR_REG(PORTC,18) 10290 #define PORTC_PCR19 PORT_PCR_REG(PORTC,19) 10291 #define PORTC_PCR20 PORT_PCR_REG(PORTC,20) 10292 #define PORTC_PCR21 PORT_PCR_REG(PORTC,21) 10293 #define PORTC_PCR22 PORT_PCR_REG(PORTC,22) 10294 #define PORTC_PCR23 PORT_PCR_REG(PORTC,23) 10295 #define PORTC_PCR24 PORT_PCR_REG(PORTC,24) 10296 #define PORTC_PCR25 PORT_PCR_REG(PORTC,25) 10297 #define PORTC_PCR26 PORT_PCR_REG(PORTC,26) 10298 #define PORTC_PCR27 PORT_PCR_REG(PORTC,27) 10299 #define PORTC_PCR28 PORT_PCR_REG(PORTC,28) 10300 #define PORTC_PCR29 PORT_PCR_REG(PORTC,29) 10301 #define PORTC_PCR30 PORT_PCR_REG(PORTC,30) 10302 #define PORTC_PCR31 PORT_PCR_REG(PORTC,31) 10303 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC) 10304 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC) 10305 #define PORTC_ISFR PORT_ISFR_REG(PORTC) 10306 /* PORTD */ 10307 #define PORTD_PCR0 PORT_PCR_REG(PORTD,0) 10308 #define PORTD_PCR1 PORT_PCR_REG(PORTD,1) 10309 #define PORTD_PCR2 PORT_PCR_REG(PORTD,2) 10310 #define PORTD_PCR3 PORT_PCR_REG(PORTD,3) 10311 #define PORTD_PCR4 PORT_PCR_REG(PORTD,4) 10312 #define PORTD_PCR5 PORT_PCR_REG(PORTD,5) 10313 #define PORTD_PCR6 PORT_PCR_REG(PORTD,6) 10314 #define PORTD_PCR7 PORT_PCR_REG(PORTD,7) 10315 #define PORTD_PCR8 PORT_PCR_REG(PORTD,8) 10316 #define PORTD_PCR9 PORT_PCR_REG(PORTD,9) 10317 #define PORTD_PCR10 PORT_PCR_REG(PORTD,10) 10318 #define PORTD_PCR11 PORT_PCR_REG(PORTD,11) 10319 #define PORTD_PCR12 PORT_PCR_REG(PORTD,12) 10320 #define PORTD_PCR13 PORT_PCR_REG(PORTD,13) 10321 #define PORTD_PCR14 PORT_PCR_REG(PORTD,14) 10322 #define PORTD_PCR15 PORT_PCR_REG(PORTD,15) 10323 #define PORTD_PCR16 PORT_PCR_REG(PORTD,16) 10324 #define PORTD_PCR17 PORT_PCR_REG(PORTD,17) 10325 #define PORTD_PCR18 PORT_PCR_REG(PORTD,18) 10326 #define PORTD_PCR19 PORT_PCR_REG(PORTD,19) 10327 #define PORTD_PCR20 PORT_PCR_REG(PORTD,20) 10328 #define PORTD_PCR21 PORT_PCR_REG(PORTD,21) 10329 #define PORTD_PCR22 PORT_PCR_REG(PORTD,22) 10330 #define PORTD_PCR23 PORT_PCR_REG(PORTD,23) 10331 #define PORTD_PCR24 PORT_PCR_REG(PORTD,24) 10332 #define PORTD_PCR25 PORT_PCR_REG(PORTD,25) 10333 #define PORTD_PCR26 PORT_PCR_REG(PORTD,26) 10334 #define PORTD_PCR27 PORT_PCR_REG(PORTD,27) 10335 #define PORTD_PCR28 PORT_PCR_REG(PORTD,28) 10336 #define PORTD_PCR29 PORT_PCR_REG(PORTD,29) 10337 #define PORTD_PCR30 PORT_PCR_REG(PORTD,30) 10338 #define PORTD_PCR31 PORT_PCR_REG(PORTD,31) 10339 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD) 10340 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD) 10341 #define PORTD_ISFR PORT_ISFR_REG(PORTD) 10342 #define PORTD_DFER PORT_DFER_REG(PORTD) 10343 #define PORTD_DFCR PORT_DFCR_REG(PORTD) 10344 #define PORTD_DFWR PORT_DFWR_REG(PORTD) 10345 /* PORTE */ 10346 #define PORTE_PCR0 PORT_PCR_REG(PORTE,0) 10347 #define PORTE_PCR1 PORT_PCR_REG(PORTE,1) 10348 #define PORTE_PCR2 PORT_PCR_REG(PORTE,2) 10349 #define PORTE_PCR3 PORT_PCR_REG(PORTE,3) 10350 #define PORTE_PCR4 PORT_PCR_REG(PORTE,4) 10351 #define PORTE_PCR5 PORT_PCR_REG(PORTE,5) 10352 #define PORTE_PCR6 PORT_PCR_REG(PORTE,6) 10353 #define PORTE_PCR7 PORT_PCR_REG(PORTE,7) 10354 #define PORTE_PCR8 PORT_PCR_REG(PORTE,8) 10355 #define PORTE_PCR9 PORT_PCR_REG(PORTE,9) 10356 #define PORTE_PCR10 PORT_PCR_REG(PORTE,10) 10357 #define PORTE_PCR11 PORT_PCR_REG(PORTE,11) 10358 #define PORTE_PCR12 PORT_PCR_REG(PORTE,12) 10359 #define PORTE_PCR13 PORT_PCR_REG(PORTE,13) 10360 #define PORTE_PCR14 PORT_PCR_REG(PORTE,14) 10361 #define PORTE_PCR15 PORT_PCR_REG(PORTE,15) 10362 #define PORTE_PCR16 PORT_PCR_REG(PORTE,16) 10363 #define PORTE_PCR17 PORT_PCR_REG(PORTE,17) 10364 #define PORTE_PCR18 PORT_PCR_REG(PORTE,18) 10365 #define PORTE_PCR19 PORT_PCR_REG(PORTE,19) 10366 #define PORTE_PCR20 PORT_PCR_REG(PORTE,20) 10367 #define PORTE_PCR21 PORT_PCR_REG(PORTE,21) 10368 #define PORTE_PCR22 PORT_PCR_REG(PORTE,22) 10369 #define PORTE_PCR23 PORT_PCR_REG(PORTE,23) 10370 #define PORTE_PCR24 PORT_PCR_REG(PORTE,24) 10371 #define PORTE_PCR25 PORT_PCR_REG(PORTE,25) 10372 #define PORTE_PCR26 PORT_PCR_REG(PORTE,26) 10373 #define PORTE_PCR27 PORT_PCR_REG(PORTE,27) 10374 #define PORTE_PCR28 PORT_PCR_REG(PORTE,28) 10375 #define PORTE_PCR29 PORT_PCR_REG(PORTE,29) 10376 #define PORTE_PCR30 PORT_PCR_REG(PORTE,30) 10377 #define PORTE_PCR31 PORT_PCR_REG(PORTE,31) 10378 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE) 10379 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE) 10380 #define PORTE_ISFR PORT_ISFR_REG(PORTE) 10381 10382 /* PORT - Register array accessors */ 10383 #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index) 10384 #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index) 10385 #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index) 10386 #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index) 10387 #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index) 10388 10389 /*! 10390 * @} 10391 */ /* end of group PORT_Register_Accessor_Macros */ 10392 10393 10394 /*! 10395 * @} 10396 */ /* end of group PORT_Peripheral_Access_Layer */ 10397 10398 10399 /* ---------------------------------------------------------------------------- 10400 -- RCM Peripheral Access Layer 10401 ---------------------------------------------------------------------------- */ 10402 10403 /*! 10404 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer 10405 * @{ 10406 */ 10407 10408 /** RCM - Register Layout Typedef */ 10409 typedef struct { 10410 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ 10411 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ 10412 uint8_t RESERVED_0[2]; 10413 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ 10414 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ 10415 uint8_t RESERVED_1[1]; 10416 __I uint8_t MR; /**< Mode Register, offset: 0x7 */ 10417 } RCM_Type, *RCM_MemMapPtr; 10418 10419 /* ---------------------------------------------------------------------------- 10420 -- RCM - Register accessor macros 10421 ---------------------------------------------------------------------------- */ 10422 10423 /*! 10424 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros 10425 * @{ 10426 */ 10427 10428 10429 /* RCM - Register accessors */ 10430 #define RCM_SRS0_REG(base) ((base)->SRS0) 10431 #define RCM_SRS1_REG(base) ((base)->SRS1) 10432 #define RCM_RPFC_REG(base) ((base)->RPFC) 10433 #define RCM_RPFW_REG(base) ((base)->RPFW) 10434 #define RCM_MR_REG(base) ((base)->MR) 10435 10436 /*! 10437 * @} 10438 */ /* end of group RCM_Register_Accessor_Macros */ 10439 10440 10441 /* ---------------------------------------------------------------------------- 10442 -- RCM Register Masks 10443 ---------------------------------------------------------------------------- */ 10444 10445 /*! 10446 * @addtogroup RCM_Register_Masks RCM Register Masks 10447 * @{ 10448 */ 10449 10450 /* SRS0 Bit Fields */ 10451 #define RCM_SRS0_WAKEUP_MASK 0x1u 10452 #define RCM_SRS0_WAKEUP_SHIFT 0 10453 #define RCM_SRS0_LVD_MASK 0x2u 10454 #define RCM_SRS0_LVD_SHIFT 1 10455 #define RCM_SRS0_LOC_MASK 0x4u 10456 #define RCM_SRS0_LOC_SHIFT 2 10457 #define RCM_SRS0_LOL_MASK 0x8u 10458 #define RCM_SRS0_LOL_SHIFT 3 10459 #define RCM_SRS0_WDOG_MASK 0x20u 10460 #define RCM_SRS0_WDOG_SHIFT 5 10461 #define RCM_SRS0_PIN_MASK 0x40u 10462 #define RCM_SRS0_PIN_SHIFT 6 10463 #define RCM_SRS0_POR_MASK 0x80u 10464 #define RCM_SRS0_POR_SHIFT 7 10465 /* SRS1 Bit Fields */ 10466 #define RCM_SRS1_JTAG_MASK 0x1u 10467 #define RCM_SRS1_JTAG_SHIFT 0 10468 #define RCM_SRS1_LOCKUP_MASK 0x2u 10469 #define RCM_SRS1_LOCKUP_SHIFT 1 10470 #define RCM_SRS1_SW_MASK 0x4u 10471 #define RCM_SRS1_SW_SHIFT 2 10472 #define RCM_SRS1_MDM_AP_MASK 0x8u 10473 #define RCM_SRS1_MDM_AP_SHIFT 3 10474 #define RCM_SRS1_EZPT_MASK 0x10u 10475 #define RCM_SRS1_EZPT_SHIFT 4 10476 #define RCM_SRS1_SACKERR_MASK 0x20u 10477 #define RCM_SRS1_SACKERR_SHIFT 5 10478 /* RPFC Bit Fields */ 10479 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u 10480 #define RCM_RPFC_RSTFLTSRW_SHIFT 0 10481 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK) 10482 #define RCM_RPFC_RSTFLTSS_MASK 0x4u 10483 #define RCM_RPFC_RSTFLTSS_SHIFT 2 10484 /* RPFW Bit Fields */ 10485 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu 10486 #define RCM_RPFW_RSTFLTSEL_SHIFT 0 10487 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK) 10488 /* MR Bit Fields */ 10489 #define RCM_MR_EZP_MS_MASK 0x2u 10490 #define RCM_MR_EZP_MS_SHIFT 1 10491 10492 /*! 10493 * @} 10494 */ /* end of group RCM_Register_Masks */ 10495 10496 10497 /* RCM - Peripheral instance base addresses */ 10498 /** Peripheral RCM base address */ 10499 #define RCM_BASE (0x4007F000u) 10500 /** Peripheral RCM base pointer */ 10501 #define RCM ((RCM_Type *)RCM_BASE) 10502 #define RCM_BASE_PTR (RCM) 10503 /** Array initializer of RCM peripheral base addresses */ 10504 #define RCM_BASE_ADDRS { RCM_BASE } 10505 /** Array initializer of RCM peripheral base pointers */ 10506 #define RCM_BASE_PTRS { RCM } 10507 10508 /* ---------------------------------------------------------------------------- 10509 -- RCM - Register accessor macros 10510 ---------------------------------------------------------------------------- */ 10511 10512 /*! 10513 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros 10514 * @{ 10515 */ 10516 10517 10518 /* RCM - Register instance definitions */ 10519 /* RCM */ 10520 #define RCM_SRS0 RCM_SRS0_REG(RCM) 10521 #define RCM_SRS1 RCM_SRS1_REG(RCM) 10522 #define RCM_RPFC RCM_RPFC_REG(RCM) 10523 #define RCM_RPFW RCM_RPFW_REG(RCM) 10524 #define RCM_MR RCM_MR_REG(RCM) 10525 10526 /*! 10527 * @} 10528 */ /* end of group RCM_Register_Accessor_Macros */ 10529 10530 10531 /*! 10532 * @} 10533 */ /* end of group RCM_Peripheral_Access_Layer */ 10534 10535 10536 /* ---------------------------------------------------------------------------- 10537 -- RFSYS Peripheral Access Layer 10538 ---------------------------------------------------------------------------- */ 10539 10540 /*! 10541 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer 10542 * @{ 10543 */ 10544 10545 /** RFSYS - Register Layout Typedef */ 10546 typedef struct { 10547 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ 10548 } RFSYS_Type, *RFSYS_MemMapPtr; 10549 10550 /* ---------------------------------------------------------------------------- 10551 -- RFSYS - Register accessor macros 10552 ---------------------------------------------------------------------------- */ 10553 10554 /*! 10555 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros 10556 * @{ 10557 */ 10558 10559 10560 /* RFSYS - Register accessors */ 10561 #define RFSYS_REG_REG(base,index) ((base)->REG[index]) 10562 10563 /*! 10564 * @} 10565 */ /* end of group RFSYS_Register_Accessor_Macros */ 10566 10567 10568 /* ---------------------------------------------------------------------------- 10569 -- RFSYS Register Masks 10570 ---------------------------------------------------------------------------- */ 10571 10572 /*! 10573 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks 10574 * @{ 10575 */ 10576 10577 /* REG Bit Fields */ 10578 #define RFSYS_REG_LL_MASK 0xFFu 10579 #define RFSYS_REG_LL_SHIFT 0 10580 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK) 10581 #define RFSYS_REG_LH_MASK 0xFF00u 10582 #define RFSYS_REG_LH_SHIFT 8 10583 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK) 10584 #define RFSYS_REG_HL_MASK 0xFF0000u 10585 #define RFSYS_REG_HL_SHIFT 16 10586 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK) 10587 #define RFSYS_REG_HH_MASK 0xFF000000u 10588 #define RFSYS_REG_HH_SHIFT 24 10589 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK) 10590 10591 /*! 10592 * @} 10593 */ /* end of group RFSYS_Register_Masks */ 10594 10595 10596 /* RFSYS - Peripheral instance base addresses */ 10597 /** Peripheral RFSYS base address */ 10598 #define RFSYS_BASE (0x40041000u) 10599 /** Peripheral RFSYS base pointer */ 10600 #define RFSYS ((RFSYS_Type *)RFSYS_BASE) 10601 #define RFSYS_BASE_PTR (RFSYS) 10602 /** Array initializer of RFSYS peripheral base addresses */ 10603 #define RFSYS_BASE_ADDRS { RFSYS_BASE } 10604 /** Array initializer of RFSYS peripheral base pointers */ 10605 #define RFSYS_BASE_PTRS { RFSYS } 10606 10607 /* ---------------------------------------------------------------------------- 10608 -- RFSYS - Register accessor macros 10609 ---------------------------------------------------------------------------- */ 10610 10611 /*! 10612 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros 10613 * @{ 10614 */ 10615 10616 10617 /* RFSYS - Register instance definitions */ 10618 /* RFSYS */ 10619 #define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0) 10620 #define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1) 10621 #define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2) 10622 #define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3) 10623 #define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4) 10624 #define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5) 10625 #define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6) 10626 #define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7) 10627 10628 /* RFSYS - Register array accessors */ 10629 #define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index) 10630 10631 /*! 10632 * @} 10633 */ /* end of group RFSYS_Register_Accessor_Macros */ 10634 10635 10636 /*! 10637 * @} 10638 */ /* end of group RFSYS_Peripheral_Access_Layer */ 10639 10640 10641 /* ---------------------------------------------------------------------------- 10642 -- RFVBAT Peripheral Access Layer 10643 ---------------------------------------------------------------------------- */ 10644 10645 /*! 10646 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer 10647 * @{ 10648 */ 10649 10650 /** RFVBAT - Register Layout Typedef */ 10651 typedef struct { 10652 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */ 10653 } RFVBAT_Type, *RFVBAT_MemMapPtr; 10654 10655 /* ---------------------------------------------------------------------------- 10656 -- RFVBAT - Register accessor macros 10657 ---------------------------------------------------------------------------- */ 10658 10659 /*! 10660 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros 10661 * @{ 10662 */ 10663 10664 10665 /* RFVBAT - Register accessors */ 10666 #define RFVBAT_REG_REG(base,index) ((base)->REG[index]) 10667 10668 /*! 10669 * @} 10670 */ /* end of group RFVBAT_Register_Accessor_Macros */ 10671 10672 10673 /* ---------------------------------------------------------------------------- 10674 -- RFVBAT Register Masks 10675 ---------------------------------------------------------------------------- */ 10676 10677 /*! 10678 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks 10679 * @{ 10680 */ 10681 10682 /* REG Bit Fields */ 10683 #define RFVBAT_REG_LL_MASK 0xFFu 10684 #define RFVBAT_REG_LL_SHIFT 0 10685 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK) 10686 #define RFVBAT_REG_LH_MASK 0xFF00u 10687 #define RFVBAT_REG_LH_SHIFT 8 10688 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK) 10689 #define RFVBAT_REG_HL_MASK 0xFF0000u 10690 #define RFVBAT_REG_HL_SHIFT 16 10691 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK) 10692 #define RFVBAT_REG_HH_MASK 0xFF000000u 10693 #define RFVBAT_REG_HH_SHIFT 24 10694 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK) 10695 10696 /*! 10697 * @} 10698 */ /* end of group RFVBAT_Register_Masks */ 10699 10700 10701 /* RFVBAT - Peripheral instance base addresses */ 10702 /** Peripheral RFVBAT base address */ 10703 #define RFVBAT_BASE (0x4003E000u) 10704 /** Peripheral RFVBAT base pointer */ 10705 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE) 10706 #define RFVBAT_BASE_PTR (RFVBAT) 10707 /** Array initializer of RFVBAT peripheral base addresses */ 10708 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE } 10709 /** Array initializer of RFVBAT peripheral base pointers */ 10710 #define RFVBAT_BASE_PTRS { RFVBAT } 10711 10712 /* ---------------------------------------------------------------------------- 10713 -- RFVBAT - Register accessor macros 10714 ---------------------------------------------------------------------------- */ 10715 10716 /*! 10717 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros 10718 * @{ 10719 */ 10720 10721 10722 /* RFVBAT - Register instance definitions */ 10723 /* RFVBAT */ 10724 #define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0) 10725 #define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1) 10726 #define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2) 10727 #define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3) 10728 #define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4) 10729 #define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5) 10730 #define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6) 10731 #define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7) 10732 10733 /* RFVBAT - Register array accessors */ 10734 #define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index) 10735 10736 /*! 10737 * @} 10738 */ /* end of group RFVBAT_Register_Accessor_Macros */ 10739 10740 10741 /*! 10742 * @} 10743 */ /* end of group RFVBAT_Peripheral_Access_Layer */ 10744 10745 10746 /* ---------------------------------------------------------------------------- 10747 -- RNG Peripheral Access Layer 10748 ---------------------------------------------------------------------------- */ 10749 10750 /*! 10751 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer 10752 * @{ 10753 */ 10754 10755 /** RNG - Register Layout Typedef */ 10756 typedef struct { 10757 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */ 10758 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */ 10759 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */ 10760 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */ 10761 } RNG_Type, *RNG_MemMapPtr; 10762 10763 /* ---------------------------------------------------------------------------- 10764 -- RNG - Register accessor macros 10765 ---------------------------------------------------------------------------- */ 10766 10767 /*! 10768 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros 10769 * @{ 10770 */ 10771 10772 10773 /* RNG - Register accessors */ 10774 #define RNG_CR_REG(base) ((base)->CR) 10775 #define RNG_SR_REG(base) ((base)->SR) 10776 #define RNG_ER_REG(base) ((base)->ER) 10777 #define RNG_OR_REG(base) ((base)->OR) 10778 10779 /*! 10780 * @} 10781 */ /* end of group RNG_Register_Accessor_Macros */ 10782 10783 10784 /* ---------------------------------------------------------------------------- 10785 -- RNG Register Masks 10786 ---------------------------------------------------------------------------- */ 10787 10788 /*! 10789 * @addtogroup RNG_Register_Masks RNG Register Masks 10790 * @{ 10791 */ 10792 10793 /* CR Bit Fields */ 10794 #define RNG_CR_GO_MASK 0x1u 10795 #define RNG_CR_GO_SHIFT 0 10796 #define RNG_CR_HA_MASK 0x2u 10797 #define RNG_CR_HA_SHIFT 1 10798 #define RNG_CR_INTM_MASK 0x4u 10799 #define RNG_CR_INTM_SHIFT 2 10800 #define RNG_CR_CLRI_MASK 0x8u 10801 #define RNG_CR_CLRI_SHIFT 3 10802 #define RNG_CR_SLP_MASK 0x10u 10803 #define RNG_CR_SLP_SHIFT 4 10804 /* SR Bit Fields */ 10805 #define RNG_SR_SECV_MASK 0x1u 10806 #define RNG_SR_SECV_SHIFT 0 10807 #define RNG_SR_LRS_MASK 0x2u 10808 #define RNG_SR_LRS_SHIFT 1 10809 #define RNG_SR_ORU_MASK 0x4u 10810 #define RNG_SR_ORU_SHIFT 2 10811 #define RNG_SR_ERRI_MASK 0x8u 10812 #define RNG_SR_ERRI_SHIFT 3 10813 #define RNG_SR_SLP_MASK 0x10u 10814 #define RNG_SR_SLP_SHIFT 4 10815 #define RNG_SR_OREG_LVL_MASK 0xFF00u 10816 #define RNG_SR_OREG_LVL_SHIFT 8 10817 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK) 10818 #define RNG_SR_OREG_SIZE_MASK 0xFF0000u 10819 #define RNG_SR_OREG_SIZE_SHIFT 16 10820 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK) 10821 /* ER Bit Fields */ 10822 #define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu 10823 #define RNG_ER_EXT_ENT_SHIFT 0 10824 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK) 10825 /* OR Bit Fields */ 10826 #define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu 10827 #define RNG_OR_RANDOUT_SHIFT 0 10828 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK) 10829 10830 /*! 10831 * @} 10832 */ /* end of group RNG_Register_Masks */ 10833 10834 10835 /* RNG - Peripheral instance base addresses */ 10836 /** Peripheral RNG base address */ 10837 #define RNG_BASE (0x40029000u) 10838 /** Peripheral RNG base pointer */ 10839 #define RNG ((RNG_Type *)RNG_BASE) 10840 #define RNG_BASE_PTR (RNG) 10841 /** Array initializer of RNG peripheral base addresses */ 10842 #define RNG_BASE_ADDRS { RNG_BASE } 10843 /** Array initializer of RNG peripheral base pointers */ 10844 #define RNG_BASE_PTRS { RNG } 10845 /** Interrupt vectors for the RNG peripheral type */ 10846 #define RNG_IRQS { RNG_IRQn } 10847 10848 /* ---------------------------------------------------------------------------- 10849 -- RNG - Register accessor macros 10850 ---------------------------------------------------------------------------- */ 10851 10852 /*! 10853 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros 10854 * @{ 10855 */ 10856 10857 10858 /* RNG - Register instance definitions */ 10859 /* RNG */ 10860 #define RNG_CR RNG_CR_REG(RNG) 10861 #define RNG_SR RNG_SR_REG(RNG) 10862 #define RNG_ER RNG_ER_REG(RNG) 10863 #define RNG_OR RNG_OR_REG(RNG) 10864 10865 /*! 10866 * @} 10867 */ /* end of group RNG_Register_Accessor_Macros */ 10868 10869 10870 /*! 10871 * @} 10872 */ /* end of group RNG_Peripheral_Access_Layer */ 10873 10874 10875 /* ---------------------------------------------------------------------------- 10876 -- RTC Peripheral Access Layer 10877 ---------------------------------------------------------------------------- */ 10878 10879 /*! 10880 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer 10881 * @{ 10882 */ 10883 10884 /** RTC - Register Layout Typedef */ 10885 typedef struct { 10886 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ 10887 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ 10888 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ 10889 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ 10890 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ 10891 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ 10892 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ 10893 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ 10894 uint8_t RESERVED_0[2016]; 10895 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ 10896 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ 10897 } RTC_Type, *RTC_MemMapPtr; 10898 10899 /* ---------------------------------------------------------------------------- 10900 -- RTC - Register accessor macros 10901 ---------------------------------------------------------------------------- */ 10902 10903 /*! 10904 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros 10905 * @{ 10906 */ 10907 10908 10909 /* RTC - Register accessors */ 10910 #define RTC_TSR_REG(base) ((base)->TSR) 10911 #define RTC_TPR_REG(base) ((base)->TPR) 10912 #define RTC_TAR_REG(base) ((base)->TAR) 10913 #define RTC_TCR_REG(base) ((base)->TCR) 10914 #define RTC_CR_REG(base) ((base)->CR) 10915 #define RTC_SR_REG(base) ((base)->SR) 10916 #define RTC_LR_REG(base) ((base)->LR) 10917 #define RTC_IER_REG(base) ((base)->IER) 10918 #define RTC_WAR_REG(base) ((base)->WAR) 10919 #define RTC_RAR_REG(base) ((base)->RAR) 10920 10921 /*! 10922 * @} 10923 */ /* end of group RTC_Register_Accessor_Macros */ 10924 10925 10926 /* ---------------------------------------------------------------------------- 10927 -- RTC Register Masks 10928 ---------------------------------------------------------------------------- */ 10929 10930 /*! 10931 * @addtogroup RTC_Register_Masks RTC Register Masks 10932 * @{ 10933 */ 10934 10935 /* TSR Bit Fields */ 10936 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu 10937 #define RTC_TSR_TSR_SHIFT 0 10938 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK) 10939 /* TPR Bit Fields */ 10940 #define RTC_TPR_TPR_MASK 0xFFFFu 10941 #define RTC_TPR_TPR_SHIFT 0 10942 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK) 10943 /* TAR Bit Fields */ 10944 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu 10945 #define RTC_TAR_TAR_SHIFT 0 10946 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK) 10947 /* TCR Bit Fields */ 10948 #define RTC_TCR_TCR_MASK 0xFFu 10949 #define RTC_TCR_TCR_SHIFT 0 10950 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK) 10951 #define RTC_TCR_CIR_MASK 0xFF00u 10952 #define RTC_TCR_CIR_SHIFT 8 10953 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK) 10954 #define RTC_TCR_TCV_MASK 0xFF0000u 10955 #define RTC_TCR_TCV_SHIFT 16 10956 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK) 10957 #define RTC_TCR_CIC_MASK 0xFF000000u 10958 #define RTC_TCR_CIC_SHIFT 24 10959 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK) 10960 /* CR Bit Fields */ 10961 #define RTC_CR_SWR_MASK 0x1u 10962 #define RTC_CR_SWR_SHIFT 0 10963 #define RTC_CR_WPE_MASK 0x2u 10964 #define RTC_CR_WPE_SHIFT 1 10965 #define RTC_CR_SUP_MASK 0x4u 10966 #define RTC_CR_SUP_SHIFT 2 10967 #define RTC_CR_UM_MASK 0x8u 10968 #define RTC_CR_UM_SHIFT 3 10969 #define RTC_CR_WPS_MASK 0x10u 10970 #define RTC_CR_WPS_SHIFT 4 10971 #define RTC_CR_OSCE_MASK 0x100u 10972 #define RTC_CR_OSCE_SHIFT 8 10973 #define RTC_CR_CLKO_MASK 0x200u 10974 #define RTC_CR_CLKO_SHIFT 9 10975 #define RTC_CR_SC16P_MASK 0x400u 10976 #define RTC_CR_SC16P_SHIFT 10 10977 #define RTC_CR_SC8P_MASK 0x800u 10978 #define RTC_CR_SC8P_SHIFT 11 10979 #define RTC_CR_SC4P_MASK 0x1000u 10980 #define RTC_CR_SC4P_SHIFT 12 10981 #define RTC_CR_SC2P_MASK 0x2000u 10982 #define RTC_CR_SC2P_SHIFT 13 10983 /* SR Bit Fields */ 10984 #define RTC_SR_TIF_MASK 0x1u 10985 #define RTC_SR_TIF_SHIFT 0 10986 #define RTC_SR_TOF_MASK 0x2u 10987 #define RTC_SR_TOF_SHIFT 1 10988 #define RTC_SR_TAF_MASK 0x4u 10989 #define RTC_SR_TAF_SHIFT 2 10990 #define RTC_SR_TCE_MASK 0x10u 10991 #define RTC_SR_TCE_SHIFT 4 10992 /* LR Bit Fields */ 10993 #define RTC_LR_TCL_MASK 0x8u 10994 #define RTC_LR_TCL_SHIFT 3 10995 #define RTC_LR_CRL_MASK 0x10u 10996 #define RTC_LR_CRL_SHIFT 4 10997 #define RTC_LR_SRL_MASK 0x20u 10998 #define RTC_LR_SRL_SHIFT 5 10999 #define RTC_LR_LRL_MASK 0x40u 11000 #define RTC_LR_LRL_SHIFT 6 11001 /* IER Bit Fields */ 11002 #define RTC_IER_TIIE_MASK 0x1u 11003 #define RTC_IER_TIIE_SHIFT 0 11004 #define RTC_IER_TOIE_MASK 0x2u 11005 #define RTC_IER_TOIE_SHIFT 1 11006 #define RTC_IER_TAIE_MASK 0x4u 11007 #define RTC_IER_TAIE_SHIFT 2 11008 #define RTC_IER_TSIE_MASK 0x10u 11009 #define RTC_IER_TSIE_SHIFT 4 11010 #define RTC_IER_WPON_MASK 0x80u 11011 #define RTC_IER_WPON_SHIFT 7 11012 /* WAR Bit Fields */ 11013 #define RTC_WAR_TSRW_MASK 0x1u 11014 #define RTC_WAR_TSRW_SHIFT 0 11015 #define RTC_WAR_TPRW_MASK 0x2u 11016 #define RTC_WAR_TPRW_SHIFT 1 11017 #define RTC_WAR_TARW_MASK 0x4u 11018 #define RTC_WAR_TARW_SHIFT 2 11019 #define RTC_WAR_TCRW_MASK 0x8u 11020 #define RTC_WAR_TCRW_SHIFT 3 11021 #define RTC_WAR_CRW_MASK 0x10u 11022 #define RTC_WAR_CRW_SHIFT 4 11023 #define RTC_WAR_SRW_MASK 0x20u 11024 #define RTC_WAR_SRW_SHIFT 5 11025 #define RTC_WAR_LRW_MASK 0x40u 11026 #define RTC_WAR_LRW_SHIFT 6 11027 #define RTC_WAR_IERW_MASK 0x80u 11028 #define RTC_WAR_IERW_SHIFT 7 11029 /* RAR Bit Fields */ 11030 #define RTC_RAR_TSRR_MASK 0x1u 11031 #define RTC_RAR_TSRR_SHIFT 0 11032 #define RTC_RAR_TPRR_MASK 0x2u 11033 #define RTC_RAR_TPRR_SHIFT 1 11034 #define RTC_RAR_TARR_MASK 0x4u 11035 #define RTC_RAR_TARR_SHIFT 2 11036 #define RTC_RAR_TCRR_MASK 0x8u 11037 #define RTC_RAR_TCRR_SHIFT 3 11038 #define RTC_RAR_CRR_MASK 0x10u 11039 #define RTC_RAR_CRR_SHIFT 4 11040 #define RTC_RAR_SRR_MASK 0x20u 11041 #define RTC_RAR_SRR_SHIFT 5 11042 #define RTC_RAR_LRR_MASK 0x40u 11043 #define RTC_RAR_LRR_SHIFT 6 11044 #define RTC_RAR_IERR_MASK 0x80u 11045 #define RTC_RAR_IERR_SHIFT 7 11046 11047 /*! 11048 * @} 11049 */ /* end of group RTC_Register_Masks */ 11050 11051 11052 /* RTC - Peripheral instance base addresses */ 11053 /** Peripheral RTC base address */ 11054 #define RTC_BASE (0x4003D000u) 11055 /** Peripheral RTC base pointer */ 11056 #define RTC ((RTC_Type *)RTC_BASE) 11057 #define RTC_BASE_PTR (RTC) 11058 /** Array initializer of RTC peripheral base addresses */ 11059 #define RTC_BASE_ADDRS { RTC_BASE } 11060 /** Array initializer of RTC peripheral base pointers */ 11061 #define RTC_BASE_PTRS { RTC } 11062 /** Interrupt vectors for the RTC peripheral type */ 11063 #define RTC_IRQS { RTC_IRQn } 11064 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } 11065 11066 /* ---------------------------------------------------------------------------- 11067 -- RTC - Register accessor macros 11068 ---------------------------------------------------------------------------- */ 11069 11070 /*! 11071 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros 11072 * @{ 11073 */ 11074 11075 11076 /* RTC - Register instance definitions */ 11077 /* RTC */ 11078 #define RTC_TSR RTC_TSR_REG(RTC) 11079 #define RTC_TPR RTC_TPR_REG(RTC) 11080 #define RTC_TAR RTC_TAR_REG(RTC) 11081 #define RTC_TCR RTC_TCR_REG(RTC) 11082 #define RTC_CR RTC_CR_REG(RTC) 11083 #define RTC_SR RTC_SR_REG(RTC) 11084 #define RTC_LR RTC_LR_REG(RTC) 11085 #define RTC_IER RTC_IER_REG(RTC) 11086 #define RTC_WAR RTC_WAR_REG(RTC) 11087 #define RTC_RAR RTC_RAR_REG(RTC) 11088 11089 /*! 11090 * @} 11091 */ /* end of group RTC_Register_Accessor_Macros */ 11092 11093 11094 /*! 11095 * @} 11096 */ /* end of group RTC_Peripheral_Access_Layer */ 11097 11098 11099 /* ---------------------------------------------------------------------------- 11100 -- SDHC Peripheral Access Layer 11101 ---------------------------------------------------------------------------- */ 11102 11103 /*! 11104 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer 11105 * @{ 11106 */ 11107 11108 /** SDHC - Register Layout Typedef */ 11109 typedef struct { 11110 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */ 11111 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */ 11112 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */ 11113 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */ 11114 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */ 11115 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */ 11116 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */ 11117 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */ 11118 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */ 11119 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */ 11120 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */ 11121 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */ 11122 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */ 11123 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */ 11124 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */ 11125 uint8_t RESERVED_0[8]; 11126 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */ 11127 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */ 11128 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */ 11129 uint8_t RESERVED_1[100]; 11130 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */ 11131 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */ 11132 uint8_t RESERVED_2[52]; 11133 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */ 11134 } SDHC_Type, *SDHC_MemMapPtr; 11135 11136 /* ---------------------------------------------------------------------------- 11137 -- SDHC - Register accessor macros 11138 ---------------------------------------------------------------------------- */ 11139 11140 /*! 11141 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros 11142 * @{ 11143 */ 11144 11145 11146 /* SDHC - Register accessors */ 11147 #define SDHC_DSADDR_REG(base) ((base)->DSADDR) 11148 #define SDHC_BLKATTR_REG(base) ((base)->BLKATTR) 11149 #define SDHC_CMDARG_REG(base) ((base)->CMDARG) 11150 #define SDHC_XFERTYP_REG(base) ((base)->XFERTYP) 11151 #define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index]) 11152 #define SDHC_DATPORT_REG(base) ((base)->DATPORT) 11153 #define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT) 11154 #define SDHC_PROCTL_REG(base) ((base)->PROCTL) 11155 #define SDHC_SYSCTL_REG(base) ((base)->SYSCTL) 11156 #define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT) 11157 #define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN) 11158 #define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN) 11159 #define SDHC_AC12ERR_REG(base) ((base)->AC12ERR) 11160 #define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT) 11161 #define SDHC_WML_REG(base) ((base)->WML) 11162 #define SDHC_FEVT_REG(base) ((base)->FEVT) 11163 #define SDHC_ADMAES_REG(base) ((base)->ADMAES) 11164 #define SDHC_ADSADDR_REG(base) ((base)->ADSADDR) 11165 #define SDHC_VENDOR_REG(base) ((base)->VENDOR) 11166 #define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT) 11167 #define SDHC_HOSTVER_REG(base) ((base)->HOSTVER) 11168 11169 /*! 11170 * @} 11171 */ /* end of group SDHC_Register_Accessor_Macros */ 11172 11173 11174 /* ---------------------------------------------------------------------------- 11175 -- SDHC Register Masks 11176 ---------------------------------------------------------------------------- */ 11177 11178 /*! 11179 * @addtogroup SDHC_Register_Masks SDHC Register Masks 11180 * @{ 11181 */ 11182 11183 /* DSADDR Bit Fields */ 11184 #define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu 11185 #define SDHC_DSADDR_DSADDR_SHIFT 2 11186 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK) 11187 /* BLKATTR Bit Fields */ 11188 #define SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu 11189 #define SDHC_BLKATTR_BLKSIZE_SHIFT 0 11190 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK) 11191 #define SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u 11192 #define SDHC_BLKATTR_BLKCNT_SHIFT 16 11193 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK) 11194 /* CMDARG Bit Fields */ 11195 #define SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu 11196 #define SDHC_CMDARG_CMDARG_SHIFT 0 11197 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK) 11198 /* XFERTYP Bit Fields */ 11199 #define SDHC_XFERTYP_DMAEN_MASK 0x1u 11200 #define SDHC_XFERTYP_DMAEN_SHIFT 0 11201 #define SDHC_XFERTYP_BCEN_MASK 0x2u 11202 #define SDHC_XFERTYP_BCEN_SHIFT 1 11203 #define SDHC_XFERTYP_AC12EN_MASK 0x4u 11204 #define SDHC_XFERTYP_AC12EN_SHIFT 2 11205 #define SDHC_XFERTYP_DTDSEL_MASK 0x10u 11206 #define SDHC_XFERTYP_DTDSEL_SHIFT 4 11207 #define SDHC_XFERTYP_MSBSEL_MASK 0x20u 11208 #define SDHC_XFERTYP_MSBSEL_SHIFT 5 11209 #define SDHC_XFERTYP_RSPTYP_MASK 0x30000u 11210 #define SDHC_XFERTYP_RSPTYP_SHIFT 16 11211 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK) 11212 #define SDHC_XFERTYP_CCCEN_MASK 0x80000u 11213 #define SDHC_XFERTYP_CCCEN_SHIFT 19 11214 #define SDHC_XFERTYP_CICEN_MASK 0x100000u 11215 #define SDHC_XFERTYP_CICEN_SHIFT 20 11216 #define SDHC_XFERTYP_DPSEL_MASK 0x200000u 11217 #define SDHC_XFERTYP_DPSEL_SHIFT 21 11218 #define SDHC_XFERTYP_CMDTYP_MASK 0xC00000u 11219 #define SDHC_XFERTYP_CMDTYP_SHIFT 22 11220 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK) 11221 #define SDHC_XFERTYP_CMDINX_MASK 0x3F000000u 11222 #define SDHC_XFERTYP_CMDINX_SHIFT 24 11223 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK) 11224 /* CMDRSP Bit Fields */ 11225 #define SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu 11226 #define SDHC_CMDRSP_CMDRSP0_SHIFT 0 11227 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK) 11228 #define SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu 11229 #define SDHC_CMDRSP_CMDRSP1_SHIFT 0 11230 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK) 11231 #define SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu 11232 #define SDHC_CMDRSP_CMDRSP2_SHIFT 0 11233 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK) 11234 #define SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu 11235 #define SDHC_CMDRSP_CMDRSP3_SHIFT 0 11236 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK) 11237 /* DATPORT Bit Fields */ 11238 #define SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu 11239 #define SDHC_DATPORT_DATCONT_SHIFT 0 11240 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK) 11241 /* PRSSTAT Bit Fields */ 11242 #define SDHC_PRSSTAT_CIHB_MASK 0x1u 11243 #define SDHC_PRSSTAT_CIHB_SHIFT 0 11244 #define SDHC_PRSSTAT_CDIHB_MASK 0x2u 11245 #define SDHC_PRSSTAT_CDIHB_SHIFT 1 11246 #define SDHC_PRSSTAT_DLA_MASK 0x4u 11247 #define SDHC_PRSSTAT_DLA_SHIFT 2 11248 #define SDHC_PRSSTAT_SDSTB_MASK 0x8u 11249 #define SDHC_PRSSTAT_SDSTB_SHIFT 3 11250 #define SDHC_PRSSTAT_IPGOFF_MASK 0x10u 11251 #define SDHC_PRSSTAT_IPGOFF_SHIFT 4 11252 #define SDHC_PRSSTAT_HCKOFF_MASK 0x20u 11253 #define SDHC_PRSSTAT_HCKOFF_SHIFT 5 11254 #define SDHC_PRSSTAT_PEROFF_MASK 0x40u 11255 #define SDHC_PRSSTAT_PEROFF_SHIFT 6 11256 #define SDHC_PRSSTAT_SDOFF_MASK 0x80u 11257 #define SDHC_PRSSTAT_SDOFF_SHIFT 7 11258 #define SDHC_PRSSTAT_WTA_MASK 0x100u 11259 #define SDHC_PRSSTAT_WTA_SHIFT 8 11260 #define SDHC_PRSSTAT_RTA_MASK 0x200u 11261 #define SDHC_PRSSTAT_RTA_SHIFT 9 11262 #define SDHC_PRSSTAT_BWEN_MASK 0x400u 11263 #define SDHC_PRSSTAT_BWEN_SHIFT 10 11264 #define SDHC_PRSSTAT_BREN_MASK 0x800u 11265 #define SDHC_PRSSTAT_BREN_SHIFT 11 11266 #define SDHC_PRSSTAT_CINS_MASK 0x10000u 11267 #define SDHC_PRSSTAT_CINS_SHIFT 16 11268 #define SDHC_PRSSTAT_CLSL_MASK 0x800000u 11269 #define SDHC_PRSSTAT_CLSL_SHIFT 23 11270 #define SDHC_PRSSTAT_DLSL_MASK 0xFF000000u 11271 #define SDHC_PRSSTAT_DLSL_SHIFT 24 11272 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK) 11273 /* PROCTL Bit Fields */ 11274 #define SDHC_PROCTL_LCTL_MASK 0x1u 11275 #define SDHC_PROCTL_LCTL_SHIFT 0 11276 #define SDHC_PROCTL_DTW_MASK 0x6u 11277 #define SDHC_PROCTL_DTW_SHIFT 1 11278 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK) 11279 #define SDHC_PROCTL_D3CD_MASK 0x8u 11280 #define SDHC_PROCTL_D3CD_SHIFT 3 11281 #define SDHC_PROCTL_EMODE_MASK 0x30u 11282 #define SDHC_PROCTL_EMODE_SHIFT 4 11283 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK) 11284 #define SDHC_PROCTL_CDTL_MASK 0x40u 11285 #define SDHC_PROCTL_CDTL_SHIFT 6 11286 #define SDHC_PROCTL_CDSS_MASK 0x80u 11287 #define SDHC_PROCTL_CDSS_SHIFT 7 11288 #define SDHC_PROCTL_DMAS_MASK 0x300u 11289 #define SDHC_PROCTL_DMAS_SHIFT 8 11290 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK) 11291 #define SDHC_PROCTL_SABGREQ_MASK 0x10000u 11292 #define SDHC_PROCTL_SABGREQ_SHIFT 16 11293 #define SDHC_PROCTL_CREQ_MASK 0x20000u 11294 #define SDHC_PROCTL_CREQ_SHIFT 17 11295 #define SDHC_PROCTL_RWCTL_MASK 0x40000u 11296 #define SDHC_PROCTL_RWCTL_SHIFT 18 11297 #define SDHC_PROCTL_IABG_MASK 0x80000u 11298 #define SDHC_PROCTL_IABG_SHIFT 19 11299 #define SDHC_PROCTL_WECINT_MASK 0x1000000u 11300 #define SDHC_PROCTL_WECINT_SHIFT 24 11301 #define SDHC_PROCTL_WECINS_MASK 0x2000000u 11302 #define SDHC_PROCTL_WECINS_SHIFT 25 11303 #define SDHC_PROCTL_WECRM_MASK 0x4000000u 11304 #define SDHC_PROCTL_WECRM_SHIFT 26 11305 /* SYSCTL Bit Fields */ 11306 #define SDHC_SYSCTL_IPGEN_MASK 0x1u 11307 #define SDHC_SYSCTL_IPGEN_SHIFT 0 11308 #define SDHC_SYSCTL_HCKEN_MASK 0x2u 11309 #define SDHC_SYSCTL_HCKEN_SHIFT 1 11310 #define SDHC_SYSCTL_PEREN_MASK 0x4u 11311 #define SDHC_SYSCTL_PEREN_SHIFT 2 11312 #define SDHC_SYSCTL_SDCLKEN_MASK 0x8u 11313 #define SDHC_SYSCTL_SDCLKEN_SHIFT 3 11314 #define SDHC_SYSCTL_DVS_MASK 0xF0u 11315 #define SDHC_SYSCTL_DVS_SHIFT 4 11316 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK) 11317 #define SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u 11318 #define SDHC_SYSCTL_SDCLKFS_SHIFT 8 11319 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK) 11320 #define SDHC_SYSCTL_DTOCV_MASK 0xF0000u 11321 #define SDHC_SYSCTL_DTOCV_SHIFT 16 11322 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK) 11323 #define SDHC_SYSCTL_RSTA_MASK 0x1000000u 11324 #define SDHC_SYSCTL_RSTA_SHIFT 24 11325 #define SDHC_SYSCTL_RSTC_MASK 0x2000000u 11326 #define SDHC_SYSCTL_RSTC_SHIFT 25 11327 #define SDHC_SYSCTL_RSTD_MASK 0x4000000u 11328 #define SDHC_SYSCTL_RSTD_SHIFT 26 11329 #define SDHC_SYSCTL_INITA_MASK 0x8000000u 11330 #define SDHC_SYSCTL_INITA_SHIFT 27 11331 /* IRQSTAT Bit Fields */ 11332 #define SDHC_IRQSTAT_CC_MASK 0x1u 11333 #define SDHC_IRQSTAT_CC_SHIFT 0 11334 #define SDHC_IRQSTAT_TC_MASK 0x2u 11335 #define SDHC_IRQSTAT_TC_SHIFT 1 11336 #define SDHC_IRQSTAT_BGE_MASK 0x4u 11337 #define SDHC_IRQSTAT_BGE_SHIFT 2 11338 #define SDHC_IRQSTAT_DINT_MASK 0x8u 11339 #define SDHC_IRQSTAT_DINT_SHIFT 3 11340 #define SDHC_IRQSTAT_BWR_MASK 0x10u 11341 #define SDHC_IRQSTAT_BWR_SHIFT 4 11342 #define SDHC_IRQSTAT_BRR_MASK 0x20u 11343 #define SDHC_IRQSTAT_BRR_SHIFT 5 11344 #define SDHC_IRQSTAT_CINS_MASK 0x40u 11345 #define SDHC_IRQSTAT_CINS_SHIFT 6 11346 #define SDHC_IRQSTAT_CRM_MASK 0x80u 11347 #define SDHC_IRQSTAT_CRM_SHIFT 7 11348 #define SDHC_IRQSTAT_CINT_MASK 0x100u 11349 #define SDHC_IRQSTAT_CINT_SHIFT 8 11350 #define SDHC_IRQSTAT_CTOE_MASK 0x10000u 11351 #define SDHC_IRQSTAT_CTOE_SHIFT 16 11352 #define SDHC_IRQSTAT_CCE_MASK 0x20000u 11353 #define SDHC_IRQSTAT_CCE_SHIFT 17 11354 #define SDHC_IRQSTAT_CEBE_MASK 0x40000u 11355 #define SDHC_IRQSTAT_CEBE_SHIFT 18 11356 #define SDHC_IRQSTAT_CIE_MASK 0x80000u 11357 #define SDHC_IRQSTAT_CIE_SHIFT 19 11358 #define SDHC_IRQSTAT_DTOE_MASK 0x100000u 11359 #define SDHC_IRQSTAT_DTOE_SHIFT 20 11360 #define SDHC_IRQSTAT_DCE_MASK 0x200000u 11361 #define SDHC_IRQSTAT_DCE_SHIFT 21 11362 #define SDHC_IRQSTAT_DEBE_MASK 0x400000u 11363 #define SDHC_IRQSTAT_DEBE_SHIFT 22 11364 #define SDHC_IRQSTAT_AC12E_MASK 0x1000000u 11365 #define SDHC_IRQSTAT_AC12E_SHIFT 24 11366 #define SDHC_IRQSTAT_DMAE_MASK 0x10000000u 11367 #define SDHC_IRQSTAT_DMAE_SHIFT 28 11368 /* IRQSTATEN Bit Fields */ 11369 #define SDHC_IRQSTATEN_CCSEN_MASK 0x1u 11370 #define SDHC_IRQSTATEN_CCSEN_SHIFT 0 11371 #define SDHC_IRQSTATEN_TCSEN_MASK 0x2u 11372 #define SDHC_IRQSTATEN_TCSEN_SHIFT 1 11373 #define SDHC_IRQSTATEN_BGESEN_MASK 0x4u 11374 #define SDHC_IRQSTATEN_BGESEN_SHIFT 2 11375 #define SDHC_IRQSTATEN_DINTSEN_MASK 0x8u 11376 #define SDHC_IRQSTATEN_DINTSEN_SHIFT 3 11377 #define SDHC_IRQSTATEN_BWRSEN_MASK 0x10u 11378 #define SDHC_IRQSTATEN_BWRSEN_SHIFT 4 11379 #define SDHC_IRQSTATEN_BRRSEN_MASK 0x20u 11380 #define SDHC_IRQSTATEN_BRRSEN_SHIFT 5 11381 #define SDHC_IRQSTATEN_CINSEN_MASK 0x40u 11382 #define SDHC_IRQSTATEN_CINSEN_SHIFT 6 11383 #define SDHC_IRQSTATEN_CRMSEN_MASK 0x80u 11384 #define SDHC_IRQSTATEN_CRMSEN_SHIFT 7 11385 #define SDHC_IRQSTATEN_CINTSEN_MASK 0x100u 11386 #define SDHC_IRQSTATEN_CINTSEN_SHIFT 8 11387 #define SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u 11388 #define SDHC_IRQSTATEN_CTOESEN_SHIFT 16 11389 #define SDHC_IRQSTATEN_CCESEN_MASK 0x20000u 11390 #define SDHC_IRQSTATEN_CCESEN_SHIFT 17 11391 #define SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u 11392 #define SDHC_IRQSTATEN_CEBESEN_SHIFT 18 11393 #define SDHC_IRQSTATEN_CIESEN_MASK 0x80000u 11394 #define SDHC_IRQSTATEN_CIESEN_SHIFT 19 11395 #define SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u 11396 #define SDHC_IRQSTATEN_DTOESEN_SHIFT 20 11397 #define SDHC_IRQSTATEN_DCESEN_MASK 0x200000u 11398 #define SDHC_IRQSTATEN_DCESEN_SHIFT 21 11399 #define SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u 11400 #define SDHC_IRQSTATEN_DEBESEN_SHIFT 22 11401 #define SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u 11402 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT 24 11403 #define SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u 11404 #define SDHC_IRQSTATEN_DMAESEN_SHIFT 28 11405 /* IRQSIGEN Bit Fields */ 11406 #define SDHC_IRQSIGEN_CCIEN_MASK 0x1u 11407 #define SDHC_IRQSIGEN_CCIEN_SHIFT 0 11408 #define SDHC_IRQSIGEN_TCIEN_MASK 0x2u 11409 #define SDHC_IRQSIGEN_TCIEN_SHIFT 1 11410 #define SDHC_IRQSIGEN_BGEIEN_MASK 0x4u 11411 #define SDHC_IRQSIGEN_BGEIEN_SHIFT 2 11412 #define SDHC_IRQSIGEN_DINTIEN_MASK 0x8u 11413 #define SDHC_IRQSIGEN_DINTIEN_SHIFT 3 11414 #define SDHC_IRQSIGEN_BWRIEN_MASK 0x10u 11415 #define SDHC_IRQSIGEN_BWRIEN_SHIFT 4 11416 #define SDHC_IRQSIGEN_BRRIEN_MASK 0x20u 11417 #define SDHC_IRQSIGEN_BRRIEN_SHIFT 5 11418 #define SDHC_IRQSIGEN_CINSIEN_MASK 0x40u 11419 #define SDHC_IRQSIGEN_CINSIEN_SHIFT 6 11420 #define SDHC_IRQSIGEN_CRMIEN_MASK 0x80u 11421 #define SDHC_IRQSIGEN_CRMIEN_SHIFT 7 11422 #define SDHC_IRQSIGEN_CINTIEN_MASK 0x100u 11423 #define SDHC_IRQSIGEN_CINTIEN_SHIFT 8 11424 #define SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u 11425 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT 16 11426 #define SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u 11427 #define SDHC_IRQSIGEN_CCEIEN_SHIFT 17 11428 #define SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u 11429 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT 18 11430 #define SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u 11431 #define SDHC_IRQSIGEN_CIEIEN_SHIFT 19 11432 #define SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u 11433 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT 20 11434 #define SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u 11435 #define SDHC_IRQSIGEN_DCEIEN_SHIFT 21 11436 #define SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u 11437 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT 22 11438 #define SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u 11439 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT 24 11440 #define SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u 11441 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT 28 11442 /* AC12ERR Bit Fields */ 11443 #define SDHC_AC12ERR_AC12NE_MASK 0x1u 11444 #define SDHC_AC12ERR_AC12NE_SHIFT 0 11445 #define SDHC_AC12ERR_AC12TOE_MASK 0x2u 11446 #define SDHC_AC12ERR_AC12TOE_SHIFT 1 11447 #define SDHC_AC12ERR_AC12EBE_MASK 0x4u 11448 #define SDHC_AC12ERR_AC12EBE_SHIFT 2 11449 #define SDHC_AC12ERR_AC12CE_MASK 0x8u 11450 #define SDHC_AC12ERR_AC12CE_SHIFT 3 11451 #define SDHC_AC12ERR_AC12IE_MASK 0x10u 11452 #define SDHC_AC12ERR_AC12IE_SHIFT 4 11453 #define SDHC_AC12ERR_CNIBAC12E_MASK 0x80u 11454 #define SDHC_AC12ERR_CNIBAC12E_SHIFT 7 11455 /* HTCAPBLT Bit Fields */ 11456 #define SDHC_HTCAPBLT_MBL_MASK 0x70000u 11457 #define SDHC_HTCAPBLT_MBL_SHIFT 16 11458 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK) 11459 #define SDHC_HTCAPBLT_ADMAS_MASK 0x100000u 11460 #define SDHC_HTCAPBLT_ADMAS_SHIFT 20 11461 #define SDHC_HTCAPBLT_HSS_MASK 0x200000u 11462 #define SDHC_HTCAPBLT_HSS_SHIFT 21 11463 #define SDHC_HTCAPBLT_DMAS_MASK 0x400000u 11464 #define SDHC_HTCAPBLT_DMAS_SHIFT 22 11465 #define SDHC_HTCAPBLT_SRS_MASK 0x800000u 11466 #define SDHC_HTCAPBLT_SRS_SHIFT 23 11467 #define SDHC_HTCAPBLT_VS33_MASK 0x1000000u 11468 #define SDHC_HTCAPBLT_VS33_SHIFT 24 11469 /* WML Bit Fields */ 11470 #define SDHC_WML_RDWML_MASK 0xFFu 11471 #define SDHC_WML_RDWML_SHIFT 0 11472 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK) 11473 #define SDHC_WML_WRWML_MASK 0xFF0000u 11474 #define SDHC_WML_WRWML_SHIFT 16 11475 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK) 11476 /* FEVT Bit Fields */ 11477 #define SDHC_FEVT_AC12NE_MASK 0x1u 11478 #define SDHC_FEVT_AC12NE_SHIFT 0 11479 #define SDHC_FEVT_AC12TOE_MASK 0x2u 11480 #define SDHC_FEVT_AC12TOE_SHIFT 1 11481 #define SDHC_FEVT_AC12CE_MASK 0x4u 11482 #define SDHC_FEVT_AC12CE_SHIFT 2 11483 #define SDHC_FEVT_AC12EBE_MASK 0x8u 11484 #define SDHC_FEVT_AC12EBE_SHIFT 3 11485 #define SDHC_FEVT_AC12IE_MASK 0x10u 11486 #define SDHC_FEVT_AC12IE_SHIFT 4 11487 #define SDHC_FEVT_CNIBAC12E_MASK 0x80u 11488 #define SDHC_FEVT_CNIBAC12E_SHIFT 7 11489 #define SDHC_FEVT_CTOE_MASK 0x10000u 11490 #define SDHC_FEVT_CTOE_SHIFT 16 11491 #define SDHC_FEVT_CCE_MASK 0x20000u 11492 #define SDHC_FEVT_CCE_SHIFT 17 11493 #define SDHC_FEVT_CEBE_MASK 0x40000u 11494 #define SDHC_FEVT_CEBE_SHIFT 18 11495 #define SDHC_FEVT_CIE_MASK 0x80000u 11496 #define SDHC_FEVT_CIE_SHIFT 19 11497 #define SDHC_FEVT_DTOE_MASK 0x100000u 11498 #define SDHC_FEVT_DTOE_SHIFT 20 11499 #define SDHC_FEVT_DCE_MASK 0x200000u 11500 #define SDHC_FEVT_DCE_SHIFT 21 11501 #define SDHC_FEVT_DEBE_MASK 0x400000u 11502 #define SDHC_FEVT_DEBE_SHIFT 22 11503 #define SDHC_FEVT_AC12E_MASK 0x1000000u 11504 #define SDHC_FEVT_AC12E_SHIFT 24 11505 #define SDHC_FEVT_DMAE_MASK 0x10000000u 11506 #define SDHC_FEVT_DMAE_SHIFT 28 11507 #define SDHC_FEVT_CINT_MASK 0x80000000u 11508 #define SDHC_FEVT_CINT_SHIFT 31 11509 /* ADMAES Bit Fields */ 11510 #define SDHC_ADMAES_ADMAES_MASK 0x3u 11511 #define SDHC_ADMAES_ADMAES_SHIFT 0 11512 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK) 11513 #define SDHC_ADMAES_ADMALME_MASK 0x4u 11514 #define SDHC_ADMAES_ADMALME_SHIFT 2 11515 #define SDHC_ADMAES_ADMADCE_MASK 0x8u 11516 #define SDHC_ADMAES_ADMADCE_SHIFT 3 11517 /* ADSADDR Bit Fields */ 11518 #define SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu 11519 #define SDHC_ADSADDR_ADSADDR_SHIFT 2 11520 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK) 11521 /* VENDOR Bit Fields */ 11522 #define SDHC_VENDOR_EXTDMAEN_MASK 0x1u 11523 #define SDHC_VENDOR_EXTDMAEN_SHIFT 0 11524 #define SDHC_VENDOR_EXBLKNU_MASK 0x2u 11525 #define SDHC_VENDOR_EXBLKNU_SHIFT 1 11526 #define SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u 11527 #define SDHC_VENDOR_INTSTVAL_SHIFT 16 11528 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK) 11529 /* MMCBOOT Bit Fields */ 11530 #define SDHC_MMCBOOT_DTOCVACK_MASK 0xFu 11531 #define SDHC_MMCBOOT_DTOCVACK_SHIFT 0 11532 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK) 11533 #define SDHC_MMCBOOT_BOOTACK_MASK 0x10u 11534 #define SDHC_MMCBOOT_BOOTACK_SHIFT 4 11535 #define SDHC_MMCBOOT_BOOTMODE_MASK 0x20u 11536 #define SDHC_MMCBOOT_BOOTMODE_SHIFT 5 11537 #define SDHC_MMCBOOT_BOOTEN_MASK 0x40u 11538 #define SDHC_MMCBOOT_BOOTEN_SHIFT 6 11539 #define SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u 11540 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7 11541 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u 11542 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16 11543 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK) 11544 /* HOSTVER Bit Fields */ 11545 #define SDHC_HOSTVER_SVN_MASK 0xFFu 11546 #define SDHC_HOSTVER_SVN_SHIFT 0 11547 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK) 11548 #define SDHC_HOSTVER_VVN_MASK 0xFF00u 11549 #define SDHC_HOSTVER_VVN_SHIFT 8 11550 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK) 11551 11552 /*! 11553 * @} 11554 */ /* end of group SDHC_Register_Masks */ 11555 11556 11557 /* SDHC - Peripheral instance base addresses */ 11558 /** Peripheral SDHC base address */ 11559 #define SDHC_BASE (0x400B1000u) 11560 /** Peripheral SDHC base pointer */ 11561 #define SDHC ((SDHC_Type *)SDHC_BASE) 11562 #define SDHC_BASE_PTR (SDHC) 11563 /** Array initializer of SDHC peripheral base addresses */ 11564 #define SDHC_BASE_ADDRS { SDHC_BASE } 11565 /** Array initializer of SDHC peripheral base pointers */ 11566 #define SDHC_BASE_PTRS { SDHC } 11567 /** Interrupt vectors for the SDHC peripheral type */ 11568 #define SDHC_IRQS { SDHC_IRQn } 11569 11570 /* ---------------------------------------------------------------------------- 11571 -- SDHC - Register accessor macros 11572 ---------------------------------------------------------------------------- */ 11573 11574 /*! 11575 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros 11576 * @{ 11577 */ 11578 11579 11580 /* SDHC - Register instance definitions */ 11581 /* SDHC */ 11582 #define SDHC_DSADDR SDHC_DSADDR_REG(SDHC) 11583 #define SDHC_BLKATTR SDHC_BLKATTR_REG(SDHC) 11584 #define SDHC_CMDARG SDHC_CMDARG_REG(SDHC) 11585 #define SDHC_XFERTYP SDHC_XFERTYP_REG(SDHC) 11586 #define SDHC_CMDRSP0 SDHC_CMDRSP_REG(SDHC,0) 11587 #define SDHC_CMDRSP1 SDHC_CMDRSP_REG(SDHC,1) 11588 #define SDHC_CMDRSP2 SDHC_CMDRSP_REG(SDHC,2) 11589 #define SDHC_CMDRSP3 SDHC_CMDRSP_REG(SDHC,3) 11590 #define SDHC_DATPORT SDHC_DATPORT_REG(SDHC) 11591 #define SDHC_PRSSTAT SDHC_PRSSTAT_REG(SDHC) 11592 #define SDHC_PROCTL SDHC_PROCTL_REG(SDHC) 11593 #define SDHC_SYSCTL SDHC_SYSCTL_REG(SDHC) 11594 #define SDHC_IRQSTAT SDHC_IRQSTAT_REG(SDHC) 11595 #define SDHC_IRQSTATEN SDHC_IRQSTATEN_REG(SDHC) 11596 #define SDHC_IRQSIGEN SDHC_IRQSIGEN_REG(SDHC) 11597 #define SDHC_AC12ERR SDHC_AC12ERR_REG(SDHC) 11598 #define SDHC_HTCAPBLT SDHC_HTCAPBLT_REG(SDHC) 11599 #define SDHC_WML SDHC_WML_REG(SDHC) 11600 #define SDHC_FEVT SDHC_FEVT_REG(SDHC) 11601 #define SDHC_ADMAES SDHC_ADMAES_REG(SDHC) 11602 #define SDHC_ADSADDR SDHC_ADSADDR_REG(SDHC) 11603 #define SDHC_VENDOR SDHC_VENDOR_REG(SDHC) 11604 #define SDHC_MMCBOOT SDHC_MMCBOOT_REG(SDHC) 11605 #define SDHC_HOSTVER SDHC_HOSTVER_REG(SDHC) 11606 11607 /* SDHC - Register array accessors */ 11608 #define SDHC_CMDRSP(index) SDHC_CMDRSP_REG(SDHC,index) 11609 11610 /*! 11611 * @} 11612 */ /* end of group SDHC_Register_Accessor_Macros */ 11613 11614 11615 /*! 11616 * @} 11617 */ /* end of group SDHC_Peripheral_Access_Layer */ 11618 11619 11620 /* ---------------------------------------------------------------------------- 11621 -- SIM Peripheral Access Layer 11622 ---------------------------------------------------------------------------- */ 11623 11624 /*! 11625 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer 11626 * @{ 11627 */ 11628 11629 /** SIM - Register Layout Typedef */ 11630 typedef struct { 11631 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ 11632 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ 11633 uint8_t RESERVED_0[4092]; 11634 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ 11635 uint8_t RESERVED_1[4]; 11636 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ 11637 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ 11638 uint8_t RESERVED_2[4]; 11639 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ 11640 uint8_t RESERVED_3[8]; 11641 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ 11642 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */ 11643 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */ 11644 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */ 11645 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ 11646 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ 11647 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ 11648 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ 11649 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ 11650 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */ 11651 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ 11652 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ 11653 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */ 11654 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ 11655 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ 11656 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ 11657 } SIM_Type, *SIM_MemMapPtr; 11658 11659 /* ---------------------------------------------------------------------------- 11660 -- SIM - Register accessor macros 11661 ---------------------------------------------------------------------------- */ 11662 11663 /*! 11664 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros 11665 * @{ 11666 */ 11667 11668 11669 /* SIM - Register accessors */ 11670 #define SIM_SOPT1_REG(base) ((base)->SOPT1) 11671 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) 11672 #define SIM_SOPT2_REG(base) ((base)->SOPT2) 11673 #define SIM_SOPT4_REG(base) ((base)->SOPT4) 11674 #define SIM_SOPT5_REG(base) ((base)->SOPT5) 11675 #define SIM_SOPT7_REG(base) ((base)->SOPT7) 11676 #define SIM_SDID_REG(base) ((base)->SDID) 11677 #define SIM_SCGC1_REG(base) ((base)->SCGC1) 11678 #define SIM_SCGC2_REG(base) ((base)->SCGC2) 11679 #define SIM_SCGC3_REG(base) ((base)->SCGC3) 11680 #define SIM_SCGC4_REG(base) ((base)->SCGC4) 11681 #define SIM_SCGC5_REG(base) ((base)->SCGC5) 11682 #define SIM_SCGC6_REG(base) ((base)->SCGC6) 11683 #define SIM_SCGC7_REG(base) ((base)->SCGC7) 11684 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) 11685 #define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2) 11686 #define SIM_FCFG1_REG(base) ((base)->FCFG1) 11687 #define SIM_FCFG2_REG(base) ((base)->FCFG2) 11688 #define SIM_UIDH_REG(base) ((base)->UIDH) 11689 #define SIM_UIDMH_REG(base) ((base)->UIDMH) 11690 #define SIM_UIDML_REG(base) ((base)->UIDML) 11691 #define SIM_UIDL_REG(base) ((base)->UIDL) 11692 11693 /*! 11694 * @} 11695 */ /* end of group SIM_Register_Accessor_Macros */ 11696 11697 11698 /* ---------------------------------------------------------------------------- 11699 -- SIM Register Masks 11700 ---------------------------------------------------------------------------- */ 11701 11702 /*! 11703 * @addtogroup SIM_Register_Masks SIM Register Masks 11704 * @{ 11705 */ 11706 11707 /* SOPT1 Bit Fields */ 11708 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u 11709 #define SIM_SOPT1_RAMSIZE_SHIFT 12 11710 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK) 11711 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u 11712 #define SIM_SOPT1_OSC32KSEL_SHIFT 18 11713 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK) 11714 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u 11715 #define SIM_SOPT1_USBVSTBY_SHIFT 29 11716 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u 11717 #define SIM_SOPT1_USBSSTBY_SHIFT 30 11718 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u 11719 #define SIM_SOPT1_USBREGEN_SHIFT 31 11720 /* SOPT1CFG Bit Fields */ 11721 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u 11722 #define SIM_SOPT1CFG_URWE_SHIFT 24 11723 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u 11724 #define SIM_SOPT1CFG_UVSWE_SHIFT 25 11725 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u 11726 #define SIM_SOPT1CFG_USSWE_SHIFT 26 11727 /* SOPT2 Bit Fields */ 11728 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u 11729 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4 11730 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u 11731 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5 11732 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK) 11733 #define SIM_SOPT2_FBSL_MASK 0x300u 11734 #define SIM_SOPT2_FBSL_SHIFT 8 11735 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK) 11736 #define SIM_SOPT2_PTD7PAD_MASK 0x800u 11737 #define SIM_SOPT2_PTD7PAD_SHIFT 11 11738 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u 11739 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12 11740 #define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u 11741 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16 11742 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK) 11743 #define SIM_SOPT2_USBSRC_MASK 0x40000u 11744 #define SIM_SOPT2_USBSRC_SHIFT 18 11745 #define SIM_SOPT2_RMIISRC_MASK 0x80000u 11746 #define SIM_SOPT2_RMIISRC_SHIFT 19 11747 #define SIM_SOPT2_TIMESRC_MASK 0x300000u 11748 #define SIM_SOPT2_TIMESRC_SHIFT 20 11749 #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK) 11750 #define SIM_SOPT2_SDHCSRC_MASK 0x30000000u 11751 #define SIM_SOPT2_SDHCSRC_SHIFT 28 11752 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK) 11753 /* SOPT4 Bit Fields */ 11754 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u 11755 #define SIM_SOPT4_FTM0FLT0_SHIFT 0 11756 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u 11757 #define SIM_SOPT4_FTM0FLT1_SHIFT 1 11758 #define SIM_SOPT4_FTM0FLT2_MASK 0x4u 11759 #define SIM_SOPT4_FTM0FLT2_SHIFT 2 11760 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u 11761 #define SIM_SOPT4_FTM1FLT0_SHIFT 4 11762 #define SIM_SOPT4_FTM2FLT0_MASK 0x100u 11763 #define SIM_SOPT4_FTM2FLT0_SHIFT 8 11764 #define SIM_SOPT4_FTM3FLT0_MASK 0x1000u 11765 #define SIM_SOPT4_FTM3FLT0_SHIFT 12 11766 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u 11767 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18 11768 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK) 11769 #define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u 11770 #define SIM_SOPT4_FTM2CH0SRC_SHIFT 20 11771 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK) 11772 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u 11773 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24 11774 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u 11775 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25 11776 #define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u 11777 #define SIM_SOPT4_FTM2CLKSEL_SHIFT 26 11778 #define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u 11779 #define SIM_SOPT4_FTM3CLKSEL_SHIFT 27 11780 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u 11781 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28 11782 #define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u 11783 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29 11784 #define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u 11785 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30 11786 #define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u 11787 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31 11788 /* SOPT5 Bit Fields */ 11789 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u 11790 #define SIM_SOPT5_UART0TXSRC_SHIFT 0 11791 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK) 11792 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu 11793 #define SIM_SOPT5_UART0RXSRC_SHIFT 2 11794 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK) 11795 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u 11796 #define SIM_SOPT5_UART1TXSRC_SHIFT 4 11797 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK) 11798 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u 11799 #define SIM_SOPT5_UART1RXSRC_SHIFT 6 11800 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK) 11801 /* SOPT7 Bit Fields */ 11802 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu 11803 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 11804 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK) 11805 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u 11806 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4 11807 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u 11808 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7 11809 #define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u 11810 #define SIM_SOPT7_ADC1TRGSEL_SHIFT 8 11811 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK) 11812 #define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u 11813 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12 11814 #define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u 11815 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15 11816 /* SDID Bit Fields */ 11817 #define SIM_SDID_PINID_MASK 0xFu 11818 #define SIM_SDID_PINID_SHIFT 0 11819 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK) 11820 #define SIM_SDID_FAMID_MASK 0x70u 11821 #define SIM_SDID_FAMID_SHIFT 4 11822 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK) 11823 #define SIM_SDID_DIEID_MASK 0xF80u 11824 #define SIM_SDID_DIEID_SHIFT 7 11825 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK) 11826 #define SIM_SDID_REVID_MASK 0xF000u 11827 #define SIM_SDID_REVID_SHIFT 12 11828 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK) 11829 #define SIM_SDID_SERIESID_MASK 0xF00000u 11830 #define SIM_SDID_SERIESID_SHIFT 20 11831 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK) 11832 #define SIM_SDID_SUBFAMID_MASK 0xF000000u 11833 #define SIM_SDID_SUBFAMID_SHIFT 24 11834 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK) 11835 #define SIM_SDID_FAMILYID_MASK 0xF0000000u 11836 #define SIM_SDID_FAMILYID_SHIFT 28 11837 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK) 11838 /* SCGC1 Bit Fields */ 11839 #define SIM_SCGC1_I2C2_MASK 0x40u 11840 #define SIM_SCGC1_I2C2_SHIFT 6 11841 #define SIM_SCGC1_UART4_MASK 0x400u 11842 #define SIM_SCGC1_UART4_SHIFT 10 11843 #define SIM_SCGC1_UART5_MASK 0x800u 11844 #define SIM_SCGC1_UART5_SHIFT 11 11845 /* SCGC2 Bit Fields */ 11846 #define SIM_SCGC2_ENET_MASK 0x1u 11847 #define SIM_SCGC2_ENET_SHIFT 0 11848 #define SIM_SCGC2_DAC0_MASK 0x1000u 11849 #define SIM_SCGC2_DAC0_SHIFT 12 11850 #define SIM_SCGC2_DAC1_MASK 0x2000u 11851 #define SIM_SCGC2_DAC1_SHIFT 13 11852 /* SCGC3 Bit Fields */ 11853 #define SIM_SCGC3_RNGA_MASK 0x1u 11854 #define SIM_SCGC3_RNGA_SHIFT 0 11855 #define SIM_SCGC3_SPI2_MASK 0x1000u 11856 #define SIM_SCGC3_SPI2_SHIFT 12 11857 #define SIM_SCGC3_SDHC_MASK 0x20000u 11858 #define SIM_SCGC3_SDHC_SHIFT 17 11859 #define SIM_SCGC3_FTM2_MASK 0x1000000u 11860 #define SIM_SCGC3_FTM2_SHIFT 24 11861 #define SIM_SCGC3_FTM3_MASK 0x2000000u 11862 #define SIM_SCGC3_FTM3_SHIFT 25 11863 #define SIM_SCGC3_ADC1_MASK 0x8000000u 11864 #define SIM_SCGC3_ADC1_SHIFT 27 11865 /* SCGC4 Bit Fields */ 11866 #define SIM_SCGC4_EWM_MASK 0x2u 11867 #define SIM_SCGC4_EWM_SHIFT 1 11868 #define SIM_SCGC4_CMT_MASK 0x4u 11869 #define SIM_SCGC4_CMT_SHIFT 2 11870 #define SIM_SCGC4_I2C0_MASK 0x40u 11871 #define SIM_SCGC4_I2C0_SHIFT 6 11872 #define SIM_SCGC4_I2C1_MASK 0x80u 11873 #define SIM_SCGC4_I2C1_SHIFT 7 11874 #define SIM_SCGC4_UART0_MASK 0x400u 11875 #define SIM_SCGC4_UART0_SHIFT 10 11876 #define SIM_SCGC4_UART1_MASK 0x800u 11877 #define SIM_SCGC4_UART1_SHIFT 11 11878 #define SIM_SCGC4_UART2_MASK 0x1000u 11879 #define SIM_SCGC4_UART2_SHIFT 12 11880 #define SIM_SCGC4_UART3_MASK 0x2000u 11881 #define SIM_SCGC4_UART3_SHIFT 13 11882 #define SIM_SCGC4_USBOTG_MASK 0x40000u 11883 #define SIM_SCGC4_USBOTG_SHIFT 18 11884 #define SIM_SCGC4_CMP_MASK 0x80000u 11885 #define SIM_SCGC4_CMP_SHIFT 19 11886 #define SIM_SCGC4_VREF_MASK 0x100000u 11887 #define SIM_SCGC4_VREF_SHIFT 20 11888 /* SCGC5 Bit Fields */ 11889 #define SIM_SCGC5_LPTMR_MASK 0x1u 11890 #define SIM_SCGC5_LPTMR_SHIFT 0 11891 #define SIM_SCGC5_PORTA_MASK 0x200u 11892 #define SIM_SCGC5_PORTA_SHIFT 9 11893 #define SIM_SCGC5_PORTB_MASK 0x400u 11894 #define SIM_SCGC5_PORTB_SHIFT 10 11895 #define SIM_SCGC5_PORTC_MASK 0x800u 11896 #define SIM_SCGC5_PORTC_SHIFT 11 11897 #define SIM_SCGC5_PORTD_MASK 0x1000u 11898 #define SIM_SCGC5_PORTD_SHIFT 12 11899 #define SIM_SCGC5_PORTE_MASK 0x2000u 11900 #define SIM_SCGC5_PORTE_SHIFT 13 11901 /* SCGC6 Bit Fields */ 11902 #define SIM_SCGC6_FTF_MASK 0x1u 11903 #define SIM_SCGC6_FTF_SHIFT 0 11904 #define SIM_SCGC6_DMAMUX_MASK 0x2u 11905 #define SIM_SCGC6_DMAMUX_SHIFT 1 11906 #define SIM_SCGC6_FLEXCAN0_MASK 0x10u 11907 #define SIM_SCGC6_FLEXCAN0_SHIFT 4 11908 #define SIM_SCGC6_RNGA_MASK 0x200u 11909 #define SIM_SCGC6_RNGA_SHIFT 9 11910 #define SIM_SCGC6_SPI0_MASK 0x1000u 11911 #define SIM_SCGC6_SPI0_SHIFT 12 11912 #define SIM_SCGC6_SPI1_MASK 0x2000u 11913 #define SIM_SCGC6_SPI1_SHIFT 13 11914 #define SIM_SCGC6_I2S_MASK 0x8000u 11915 #define SIM_SCGC6_I2S_SHIFT 15 11916 #define SIM_SCGC6_CRC_MASK 0x40000u 11917 #define SIM_SCGC6_CRC_SHIFT 18 11918 #define SIM_SCGC6_USBDCD_MASK 0x200000u 11919 #define SIM_SCGC6_USBDCD_SHIFT 21 11920 #define SIM_SCGC6_PDB_MASK 0x400000u 11921 #define SIM_SCGC6_PDB_SHIFT 22 11922 #define SIM_SCGC6_PIT_MASK 0x800000u 11923 #define SIM_SCGC6_PIT_SHIFT 23 11924 #define SIM_SCGC6_FTM0_MASK 0x1000000u 11925 #define SIM_SCGC6_FTM0_SHIFT 24 11926 #define SIM_SCGC6_FTM1_MASK 0x2000000u 11927 #define SIM_SCGC6_FTM1_SHIFT 25 11928 #define SIM_SCGC6_FTM2_MASK 0x4000000u 11929 #define SIM_SCGC6_FTM2_SHIFT 26 11930 #define SIM_SCGC6_ADC0_MASK 0x8000000u 11931 #define SIM_SCGC6_ADC0_SHIFT 27 11932 #define SIM_SCGC6_RTC_MASK 0x20000000u 11933 #define SIM_SCGC6_RTC_SHIFT 29 11934 #define SIM_SCGC6_DAC0_MASK 0x80000000u 11935 #define SIM_SCGC6_DAC0_SHIFT 31 11936 /* SCGC7 Bit Fields */ 11937 #define SIM_SCGC7_FLEXBUS_MASK 0x1u 11938 #define SIM_SCGC7_FLEXBUS_SHIFT 0 11939 #define SIM_SCGC7_DMA_MASK 0x2u 11940 #define SIM_SCGC7_DMA_SHIFT 1 11941 #define SIM_SCGC7_MPU_MASK 0x4u 11942 #define SIM_SCGC7_MPU_SHIFT 2 11943 /* CLKDIV1 Bit Fields */ 11944 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u 11945 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16 11946 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK) 11947 #define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u 11948 #define SIM_CLKDIV1_OUTDIV3_SHIFT 20 11949 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK) 11950 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u 11951 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24 11952 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK) 11953 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u 11954 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28 11955 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK) 11956 /* CLKDIV2 Bit Fields */ 11957 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u 11958 #define SIM_CLKDIV2_USBFRAC_SHIFT 0 11959 #define SIM_CLKDIV2_USBDIV_MASK 0xEu 11960 #define SIM_CLKDIV2_USBDIV_SHIFT 1 11961 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK) 11962 /* FCFG1 Bit Fields */ 11963 #define SIM_FCFG1_FLASHDIS_MASK 0x1u 11964 #define SIM_FCFG1_FLASHDIS_SHIFT 0 11965 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u 11966 #define SIM_FCFG1_FLASHDOZE_SHIFT 1 11967 #define SIM_FCFG1_DEPART_MASK 0xF00u 11968 #define SIM_FCFG1_DEPART_SHIFT 8 11969 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK) 11970 #define SIM_FCFG1_EESIZE_MASK 0xF0000u 11971 #define SIM_FCFG1_EESIZE_SHIFT 16 11972 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK) 11973 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u 11974 #define SIM_FCFG1_PFSIZE_SHIFT 24 11975 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK) 11976 #define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u 11977 #define SIM_FCFG1_NVMSIZE_SHIFT 28 11978 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK) 11979 /* FCFG2 Bit Fields */ 11980 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u 11981 #define SIM_FCFG2_MAXADDR1_SHIFT 16 11982 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK) 11983 #define SIM_FCFG2_PFLSH_MASK 0x800000u 11984 #define SIM_FCFG2_PFLSH_SHIFT 23 11985 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u 11986 #define SIM_FCFG2_MAXADDR0_SHIFT 24 11987 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK) 11988 /* UIDH Bit Fields */ 11989 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu 11990 #define SIM_UIDH_UID_SHIFT 0 11991 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK) 11992 /* UIDMH Bit Fields */ 11993 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu 11994 #define SIM_UIDMH_UID_SHIFT 0 11995 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK) 11996 /* UIDML Bit Fields */ 11997 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu 11998 #define SIM_UIDML_UID_SHIFT 0 11999 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK) 12000 /* UIDL Bit Fields */ 12001 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu 12002 #define SIM_UIDL_UID_SHIFT 0 12003 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK) 12004 12005 /*! 12006 * @} 12007 */ /* end of group SIM_Register_Masks */ 12008 12009 12010 /* SIM - Peripheral instance base addresses */ 12011 /** Peripheral SIM base address */ 12012 #define SIM_BASE (0x40047000u) 12013 /** Peripheral SIM base pointer */ 12014 #define SIM ((SIM_Type *)SIM_BASE) 12015 #define SIM_BASE_PTR (SIM) 12016 /** Array initializer of SIM peripheral base addresses */ 12017 #define SIM_BASE_ADDRS { SIM_BASE } 12018 /** Array initializer of SIM peripheral base pointers */ 12019 #define SIM_BASE_PTRS { SIM } 12020 12021 /* ---------------------------------------------------------------------------- 12022 -- SIM - Register accessor macros 12023 ---------------------------------------------------------------------------- */ 12024 12025 /*! 12026 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros 12027 * @{ 12028 */ 12029 12030 12031 /* SIM - Register instance definitions */ 12032 /* SIM */ 12033 #define SIM_SOPT1 SIM_SOPT1_REG(SIM) 12034 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM) 12035 #define SIM_SOPT2 SIM_SOPT2_REG(SIM) 12036 #define SIM_SOPT4 SIM_SOPT4_REG(SIM) 12037 #define SIM_SOPT5 SIM_SOPT5_REG(SIM) 12038 #define SIM_SOPT7 SIM_SOPT7_REG(SIM) 12039 #define SIM_SDID SIM_SDID_REG(SIM) 12040 #define SIM_SCGC1 SIM_SCGC1_REG(SIM) 12041 #define SIM_SCGC2 SIM_SCGC2_REG(SIM) 12042 #define SIM_SCGC3 SIM_SCGC3_REG(SIM) 12043 #define SIM_SCGC4 SIM_SCGC4_REG(SIM) 12044 #define SIM_SCGC5 SIM_SCGC5_REG(SIM) 12045 #define SIM_SCGC6 SIM_SCGC6_REG(SIM) 12046 #define SIM_SCGC7 SIM_SCGC7_REG(SIM) 12047 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM) 12048 #define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM) 12049 #define SIM_FCFG1 SIM_FCFG1_REG(SIM) 12050 #define SIM_FCFG2 SIM_FCFG2_REG(SIM) 12051 #define SIM_UIDH SIM_UIDH_REG(SIM) 12052 #define SIM_UIDMH SIM_UIDMH_REG(SIM) 12053 #define SIM_UIDML SIM_UIDML_REG(SIM) 12054 #define SIM_UIDL SIM_UIDL_REG(SIM) 12055 12056 /*! 12057 * @} 12058 */ /* end of group SIM_Register_Accessor_Macros */ 12059 12060 12061 /*! 12062 * @} 12063 */ /* end of group SIM_Peripheral_Access_Layer */ 12064 12065 12066 /* ---------------------------------------------------------------------------- 12067 -- SMC Peripheral Access Layer 12068 ---------------------------------------------------------------------------- */ 12069 12070 /*! 12071 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer 12072 * @{ 12073 */ 12074 12075 /** SMC - Register Layout Typedef */ 12076 typedef struct { 12077 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ 12078 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ 12079 __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */ 12080 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ 12081 } SMC_Type, *SMC_MemMapPtr; 12082 12083 /* ---------------------------------------------------------------------------- 12084 -- SMC - Register accessor macros 12085 ---------------------------------------------------------------------------- */ 12086 12087 /*! 12088 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros 12089 * @{ 12090 */ 12091 12092 12093 /* SMC - Register accessors */ 12094 #define SMC_PMPROT_REG(base) ((base)->PMPROT) 12095 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL) 12096 #define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL) 12097 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT) 12098 12099 /*! 12100 * @} 12101 */ /* end of group SMC_Register_Accessor_Macros */ 12102 12103 12104 /* ---------------------------------------------------------------------------- 12105 -- SMC Register Masks 12106 ---------------------------------------------------------------------------- */ 12107 12108 /*! 12109 * @addtogroup SMC_Register_Masks SMC Register Masks 12110 * @{ 12111 */ 12112 12113 /* PMPROT Bit Fields */ 12114 #define SMC_PMPROT_AVLLS_MASK 0x2u 12115 #define SMC_PMPROT_AVLLS_SHIFT 1 12116 #define SMC_PMPROT_ALLS_MASK 0x8u 12117 #define SMC_PMPROT_ALLS_SHIFT 3 12118 #define SMC_PMPROT_AVLP_MASK 0x20u 12119 #define SMC_PMPROT_AVLP_SHIFT 5 12120 /* PMCTRL Bit Fields */ 12121 #define SMC_PMCTRL_STOPM_MASK 0x7u 12122 #define SMC_PMCTRL_STOPM_SHIFT 0 12123 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK) 12124 #define SMC_PMCTRL_STOPA_MASK 0x8u 12125 #define SMC_PMCTRL_STOPA_SHIFT 3 12126 #define SMC_PMCTRL_RUNM_MASK 0x60u 12127 #define SMC_PMCTRL_RUNM_SHIFT 5 12128 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK) 12129 #define SMC_PMCTRL_LPWUI_MASK 0x80u 12130 #define SMC_PMCTRL_LPWUI_SHIFT 7 12131 /* VLLSCTRL Bit Fields */ 12132 #define SMC_VLLSCTRL_VLLSM_MASK 0x7u 12133 #define SMC_VLLSCTRL_VLLSM_SHIFT 0 12134 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK) 12135 #define SMC_VLLSCTRL_PORPO_MASK 0x20u 12136 #define SMC_VLLSCTRL_PORPO_SHIFT 5 12137 /* PMSTAT Bit Fields */ 12138 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu 12139 #define SMC_PMSTAT_PMSTAT_SHIFT 0 12140 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK) 12141 12142 /*! 12143 * @} 12144 */ /* end of group SMC_Register_Masks */ 12145 12146 12147 /* SMC - Peripheral instance base addresses */ 12148 /** Peripheral SMC base address */ 12149 #define SMC_BASE (0x4007E000u) 12150 /** Peripheral SMC base pointer */ 12151 #define SMC ((SMC_Type *)SMC_BASE) 12152 #define SMC_BASE_PTR (SMC) 12153 /** Array initializer of SMC peripheral base addresses */ 12154 #define SMC_BASE_ADDRS { SMC_BASE } 12155 /** Array initializer of SMC peripheral base pointers */ 12156 #define SMC_BASE_PTRS { SMC } 12157 12158 /* ---------------------------------------------------------------------------- 12159 -- SMC - Register accessor macros 12160 ---------------------------------------------------------------------------- */ 12161 12162 /*! 12163 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros 12164 * @{ 12165 */ 12166 12167 12168 /* SMC - Register instance definitions */ 12169 /* SMC */ 12170 #define SMC_PMPROT SMC_PMPROT_REG(SMC) 12171 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC) 12172 #define SMC_VLLSCTRL SMC_VLLSCTRL_REG(SMC) 12173 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC) 12174 12175 /*! 12176 * @} 12177 */ /* end of group SMC_Register_Accessor_Macros */ 12178 12179 12180 /*! 12181 * @} 12182 */ /* end of group SMC_Peripheral_Access_Layer */ 12183 12184 12185 /* ---------------------------------------------------------------------------- 12186 -- SPI Peripheral Access Layer 12187 ---------------------------------------------------------------------------- */ 12188 12189 /*! 12190 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 12191 * @{ 12192 */ 12193 12194 /** SPI - Register Layout Typedef */ 12195 typedef struct { 12196 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ 12197 uint8_t RESERVED_0[4]; 12198 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */ 12199 union { /* offset: 0xC */ 12200 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ 12201 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ 12202 }; 12203 uint8_t RESERVED_1[24]; 12204 __IO uint32_t SR; /**< Status Register, offset: 0x2C */ 12205 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ 12206 union { /* offset: 0x34 */ 12207 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */ 12208 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ 12209 }; 12210 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */ 12211 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */ 12212 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */ 12213 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */ 12214 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */ 12215 uint8_t RESERVED_2[48]; 12216 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */ 12217 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */ 12218 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */ 12219 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ 12220 } SPI_Type, *SPI_MemMapPtr; 12221 12222 /* ---------------------------------------------------------------------------- 12223 -- SPI - Register accessor macros 12224 ---------------------------------------------------------------------------- */ 12225 12226 /*! 12227 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros 12228 * @{ 12229 */ 12230 12231 12232 /* SPI - Register accessors */ 12233 #define SPI_MCR_REG(base) ((base)->MCR) 12234 #define SPI_TCR_REG(base) ((base)->TCR) 12235 #define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) 12236 #define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) 12237 #define SPI_SR_REG(base) ((base)->SR) 12238 #define SPI_RSER_REG(base) ((base)->RSER) 12239 #define SPI_PUSHR_REG(base) ((base)->PUSHR) 12240 #define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) 12241 #define SPI_POPR_REG(base) ((base)->POPR) 12242 #define SPI_TXFR0_REG(base) ((base)->TXFR0) 12243 #define SPI_TXFR1_REG(base) ((base)->TXFR1) 12244 #define SPI_TXFR2_REG(base) ((base)->TXFR2) 12245 #define SPI_TXFR3_REG(base) ((base)->TXFR3) 12246 #define SPI_RXFR0_REG(base) ((base)->RXFR0) 12247 #define SPI_RXFR1_REG(base) ((base)->RXFR1) 12248 #define SPI_RXFR2_REG(base) ((base)->RXFR2) 12249 #define SPI_RXFR3_REG(base) ((base)->RXFR3) 12250 12251 /*! 12252 * @} 12253 */ /* end of group SPI_Register_Accessor_Macros */ 12254 12255 12256 /* ---------------------------------------------------------------------------- 12257 -- SPI Register Masks 12258 ---------------------------------------------------------------------------- */ 12259 12260 /*! 12261 * @addtogroup SPI_Register_Masks SPI Register Masks 12262 * @{ 12263 */ 12264 12265 /* MCR Bit Fields */ 12266 #define SPI_MCR_HALT_MASK 0x1u 12267 #define SPI_MCR_HALT_SHIFT 0 12268 #define SPI_MCR_SMPL_PT_MASK 0x300u 12269 #define SPI_MCR_SMPL_PT_SHIFT 8 12270 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK) 12271 #define SPI_MCR_CLR_RXF_MASK 0x400u 12272 #define SPI_MCR_CLR_RXF_SHIFT 10 12273 #define SPI_MCR_CLR_TXF_MASK 0x800u 12274 #define SPI_MCR_CLR_TXF_SHIFT 11 12275 #define SPI_MCR_DIS_RXF_MASK 0x1000u 12276 #define SPI_MCR_DIS_RXF_SHIFT 12 12277 #define SPI_MCR_DIS_TXF_MASK 0x2000u 12278 #define SPI_MCR_DIS_TXF_SHIFT 13 12279 #define SPI_MCR_MDIS_MASK 0x4000u 12280 #define SPI_MCR_MDIS_SHIFT 14 12281 #define SPI_MCR_DOZE_MASK 0x8000u 12282 #define SPI_MCR_DOZE_SHIFT 15 12283 #define SPI_MCR_PCSIS_MASK 0x3F0000u 12284 #define SPI_MCR_PCSIS_SHIFT 16 12285 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK) 12286 #define SPI_MCR_ROOE_MASK 0x1000000u 12287 #define SPI_MCR_ROOE_SHIFT 24 12288 #define SPI_MCR_PCSSE_MASK 0x2000000u 12289 #define SPI_MCR_PCSSE_SHIFT 25 12290 #define SPI_MCR_MTFE_MASK 0x4000000u 12291 #define SPI_MCR_MTFE_SHIFT 26 12292 #define SPI_MCR_FRZ_MASK 0x8000000u 12293 #define SPI_MCR_FRZ_SHIFT 27 12294 #define SPI_MCR_DCONF_MASK 0x30000000u 12295 #define SPI_MCR_DCONF_SHIFT 28 12296 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK) 12297 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u 12298 #define SPI_MCR_CONT_SCKE_SHIFT 30 12299 #define SPI_MCR_MSTR_MASK 0x80000000u 12300 #define SPI_MCR_MSTR_SHIFT 31 12301 /* TCR Bit Fields */ 12302 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u 12303 #define SPI_TCR_SPI_TCNT_SHIFT 16 12304 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK) 12305 /* CTAR Bit Fields */ 12306 #define SPI_CTAR_BR_MASK 0xFu 12307 #define SPI_CTAR_BR_SHIFT 0 12308 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK) 12309 #define SPI_CTAR_DT_MASK 0xF0u 12310 #define SPI_CTAR_DT_SHIFT 4 12311 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK) 12312 #define SPI_CTAR_ASC_MASK 0xF00u 12313 #define SPI_CTAR_ASC_SHIFT 8 12314 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK) 12315 #define SPI_CTAR_CSSCK_MASK 0xF000u 12316 #define SPI_CTAR_CSSCK_SHIFT 12 12317 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK) 12318 #define SPI_CTAR_PBR_MASK 0x30000u 12319 #define SPI_CTAR_PBR_SHIFT 16 12320 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK) 12321 #define SPI_CTAR_PDT_MASK 0xC0000u 12322 #define SPI_CTAR_PDT_SHIFT 18 12323 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK) 12324 #define SPI_CTAR_PASC_MASK 0x300000u 12325 #define SPI_CTAR_PASC_SHIFT 20 12326 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK) 12327 #define SPI_CTAR_PCSSCK_MASK 0xC00000u 12328 #define SPI_CTAR_PCSSCK_SHIFT 22 12329 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK) 12330 #define SPI_CTAR_LSBFE_MASK 0x1000000u 12331 #define SPI_CTAR_LSBFE_SHIFT 24 12332 #define SPI_CTAR_CPHA_MASK 0x2000000u 12333 #define SPI_CTAR_CPHA_SHIFT 25 12334 #define SPI_CTAR_CPOL_MASK 0x4000000u 12335 #define SPI_CTAR_CPOL_SHIFT 26 12336 #define SPI_CTAR_FMSZ_MASK 0x78000000u 12337 #define SPI_CTAR_FMSZ_SHIFT 27 12338 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK) 12339 #define SPI_CTAR_DBR_MASK 0x80000000u 12340 #define SPI_CTAR_DBR_SHIFT 31 12341 /* CTAR_SLAVE Bit Fields */ 12342 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u 12343 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25 12344 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u 12345 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26 12346 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u 12347 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27 12348 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK) 12349 /* SR Bit Fields */ 12350 #define SPI_SR_POPNXTPTR_MASK 0xFu 12351 #define SPI_SR_POPNXTPTR_SHIFT 0 12352 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK) 12353 #define SPI_SR_RXCTR_MASK 0xF0u 12354 #define SPI_SR_RXCTR_SHIFT 4 12355 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK) 12356 #define SPI_SR_TXNXTPTR_MASK 0xF00u 12357 #define SPI_SR_TXNXTPTR_SHIFT 8 12358 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK) 12359 #define SPI_SR_TXCTR_MASK 0xF000u 12360 #define SPI_SR_TXCTR_SHIFT 12 12361 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK) 12362 #define SPI_SR_RFDF_MASK 0x20000u 12363 #define SPI_SR_RFDF_SHIFT 17 12364 #define SPI_SR_RFOF_MASK 0x80000u 12365 #define SPI_SR_RFOF_SHIFT 19 12366 #define SPI_SR_TFFF_MASK 0x2000000u 12367 #define SPI_SR_TFFF_SHIFT 25 12368 #define SPI_SR_TFUF_MASK 0x8000000u 12369 #define SPI_SR_TFUF_SHIFT 27 12370 #define SPI_SR_EOQF_MASK 0x10000000u 12371 #define SPI_SR_EOQF_SHIFT 28 12372 #define SPI_SR_TXRXS_MASK 0x40000000u 12373 #define SPI_SR_TXRXS_SHIFT 30 12374 #define SPI_SR_TCF_MASK 0x80000000u 12375 #define SPI_SR_TCF_SHIFT 31 12376 /* RSER Bit Fields */ 12377 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u 12378 #define SPI_RSER_RFDF_DIRS_SHIFT 16 12379 #define SPI_RSER_RFDF_RE_MASK 0x20000u 12380 #define SPI_RSER_RFDF_RE_SHIFT 17 12381 #define SPI_RSER_RFOF_RE_MASK 0x80000u 12382 #define SPI_RSER_RFOF_RE_SHIFT 19 12383 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u 12384 #define SPI_RSER_TFFF_DIRS_SHIFT 24 12385 #define SPI_RSER_TFFF_RE_MASK 0x2000000u 12386 #define SPI_RSER_TFFF_RE_SHIFT 25 12387 #define SPI_RSER_TFUF_RE_MASK 0x8000000u 12388 #define SPI_RSER_TFUF_RE_SHIFT 27 12389 #define SPI_RSER_EOQF_RE_MASK 0x10000000u 12390 #define SPI_RSER_EOQF_RE_SHIFT 28 12391 #define SPI_RSER_TCF_RE_MASK 0x80000000u 12392 #define SPI_RSER_TCF_RE_SHIFT 31 12393 /* PUSHR Bit Fields */ 12394 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu 12395 #define SPI_PUSHR_TXDATA_SHIFT 0 12396 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK) 12397 #define SPI_PUSHR_PCS_MASK 0x3F0000u 12398 #define SPI_PUSHR_PCS_SHIFT 16 12399 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK) 12400 #define SPI_PUSHR_CTCNT_MASK 0x4000000u 12401 #define SPI_PUSHR_CTCNT_SHIFT 26 12402 #define SPI_PUSHR_EOQ_MASK 0x8000000u 12403 #define SPI_PUSHR_EOQ_SHIFT 27 12404 #define SPI_PUSHR_CTAS_MASK 0x70000000u 12405 #define SPI_PUSHR_CTAS_SHIFT 28 12406 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK) 12407 #define SPI_PUSHR_CONT_MASK 0x80000000u 12408 #define SPI_PUSHR_CONT_SHIFT 31 12409 /* PUSHR_SLAVE Bit Fields */ 12410 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu 12411 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0 12412 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK) 12413 /* POPR Bit Fields */ 12414 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu 12415 #define SPI_POPR_RXDATA_SHIFT 0 12416 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK) 12417 /* TXFR0 Bit Fields */ 12418 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu 12419 #define SPI_TXFR0_TXDATA_SHIFT 0 12420 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK) 12421 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u 12422 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16 12423 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK) 12424 /* TXFR1 Bit Fields */ 12425 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu 12426 #define SPI_TXFR1_TXDATA_SHIFT 0 12427 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK) 12428 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u 12429 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16 12430 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK) 12431 /* TXFR2 Bit Fields */ 12432 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu 12433 #define SPI_TXFR2_TXDATA_SHIFT 0 12434 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK) 12435 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u 12436 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16 12437 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK) 12438 /* TXFR3 Bit Fields */ 12439 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu 12440 #define SPI_TXFR3_TXDATA_SHIFT 0 12441 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK) 12442 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u 12443 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16 12444 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK) 12445 /* RXFR0 Bit Fields */ 12446 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu 12447 #define SPI_RXFR0_RXDATA_SHIFT 0 12448 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK) 12449 /* RXFR1 Bit Fields */ 12450 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu 12451 #define SPI_RXFR1_RXDATA_SHIFT 0 12452 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK) 12453 /* RXFR2 Bit Fields */ 12454 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu 12455 #define SPI_RXFR2_RXDATA_SHIFT 0 12456 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK) 12457 /* RXFR3 Bit Fields */ 12458 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu 12459 #define SPI_RXFR3_RXDATA_SHIFT 0 12460 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK) 12461 12462 /*! 12463 * @} 12464 */ /* end of group SPI_Register_Masks */ 12465 12466 12467 /* SPI - Peripheral instance base addresses */ 12468 /** Peripheral SPI0 base address */ 12469 #define SPI0_BASE (0x4002C000u) 12470 /** Peripheral SPI0 base pointer */ 12471 #define SPI0 ((SPI_Type *)SPI0_BASE) 12472 #define SPI0_BASE_PTR (SPI0) 12473 /** Peripheral SPI1 base address */ 12474 #define SPI1_BASE (0x4002D000u) 12475 /** Peripheral SPI1 base pointer */ 12476 #define SPI1 ((SPI_Type *)SPI1_BASE) 12477 #define SPI1_BASE_PTR (SPI1) 12478 /** Peripheral SPI2 base address */ 12479 #define SPI2_BASE (0x400AC000u) 12480 /** Peripheral SPI2 base pointer */ 12481 #define SPI2 ((SPI_Type *)SPI2_BASE) 12482 #define SPI2_BASE_PTR (SPI2) 12483 /** Array initializer of SPI peripheral base addresses */ 12484 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE } 12485 /** Array initializer of SPI peripheral base pointers */ 12486 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2 } 12487 /** Interrupt vectors for the SPI peripheral type */ 12488 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn } 12489 12490 /* ---------------------------------------------------------------------------- 12491 -- SPI - Register accessor macros 12492 ---------------------------------------------------------------------------- */ 12493 12494 /*! 12495 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros 12496 * @{ 12497 */ 12498 12499 12500 /* SPI - Register instance definitions */ 12501 /* SPI0 */ 12502 #define SPI0_MCR SPI_MCR_REG(SPI0) 12503 #define SPI0_TCR SPI_TCR_REG(SPI0) 12504 #define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0) 12505 #define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0) 12506 #define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1) 12507 #define SPI0_SR SPI_SR_REG(SPI0) 12508 #define SPI0_RSER SPI_RSER_REG(SPI0) 12509 #define SPI0_PUSHR SPI_PUSHR_REG(SPI0) 12510 #define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0) 12511 #define SPI0_POPR SPI_POPR_REG(SPI0) 12512 #define SPI0_TXFR0 SPI_TXFR0_REG(SPI0) 12513 #define SPI0_TXFR1 SPI_TXFR1_REG(SPI0) 12514 #define SPI0_TXFR2 SPI_TXFR2_REG(SPI0) 12515 #define SPI0_TXFR3 SPI_TXFR3_REG(SPI0) 12516 #define SPI0_RXFR0 SPI_RXFR0_REG(SPI0) 12517 #define SPI0_RXFR1 SPI_RXFR1_REG(SPI0) 12518 #define SPI0_RXFR2 SPI_RXFR2_REG(SPI0) 12519 #define SPI0_RXFR3 SPI_RXFR3_REG(SPI0) 12520 /* SPI1 */ 12521 #define SPI1_MCR SPI_MCR_REG(SPI1) 12522 #define SPI1_TCR SPI_TCR_REG(SPI1) 12523 #define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0) 12524 #define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0) 12525 #define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1) 12526 #define SPI1_SR SPI_SR_REG(SPI1) 12527 #define SPI1_RSER SPI_RSER_REG(SPI1) 12528 #define SPI1_PUSHR SPI_PUSHR_REG(SPI1) 12529 #define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1) 12530 #define SPI1_POPR SPI_POPR_REG(SPI1) 12531 #define SPI1_TXFR0 SPI_TXFR0_REG(SPI1) 12532 #define SPI1_TXFR1 SPI_TXFR1_REG(SPI1) 12533 #define SPI1_TXFR2 SPI_TXFR2_REG(SPI1) 12534 #define SPI1_TXFR3 SPI_TXFR3_REG(SPI1) 12535 #define SPI1_RXFR0 SPI_RXFR0_REG(SPI1) 12536 #define SPI1_RXFR1 SPI_RXFR1_REG(SPI1) 12537 #define SPI1_RXFR2 SPI_RXFR2_REG(SPI1) 12538 #define SPI1_RXFR3 SPI_RXFR3_REG(SPI1) 12539 /* SPI2 */ 12540 #define SPI2_MCR SPI_MCR_REG(SPI2) 12541 #define SPI2_TCR SPI_TCR_REG(SPI2) 12542 #define SPI2_CTAR0 SPI_CTAR_REG(SPI2,0) 12543 #define SPI2_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI2,0) 12544 #define SPI2_CTAR1 SPI_CTAR_REG(SPI2,1) 12545 #define SPI2_SR SPI_SR_REG(SPI2) 12546 #define SPI2_RSER SPI_RSER_REG(SPI2) 12547 #define SPI2_PUSHR SPI_PUSHR_REG(SPI2) 12548 #define SPI2_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI2) 12549 #define SPI2_POPR SPI_POPR_REG(SPI2) 12550 #define SPI2_TXFR0 SPI_TXFR0_REG(SPI2) 12551 #define SPI2_TXFR1 SPI_TXFR1_REG(SPI2) 12552 #define SPI2_TXFR2 SPI_TXFR2_REG(SPI2) 12553 #define SPI2_TXFR3 SPI_TXFR3_REG(SPI2) 12554 #define SPI2_RXFR0 SPI_RXFR0_REG(SPI2) 12555 #define SPI2_RXFR1 SPI_RXFR1_REG(SPI2) 12556 #define SPI2_RXFR2 SPI_RXFR2_REG(SPI2) 12557 #define SPI2_RXFR3 SPI_RXFR3_REG(SPI2) 12558 12559 /* SPI - Register array accessors */ 12560 #define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2) 12561 #define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2) 12562 #define SPI2_CTAR(index2) SPI_CTAR_REG(SPI2,index2) 12563 #define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2) 12564 #define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2) 12565 #define SPI2_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI2,index2) 12566 12567 /*! 12568 * @} 12569 */ /* end of group SPI_Register_Accessor_Macros */ 12570 12571 12572 /*! 12573 * @} 12574 */ /* end of group SPI_Peripheral_Access_Layer */ 12575 12576 12577 /* ---------------------------------------------------------------------------- 12578 -- UART Peripheral Access Layer 12579 ---------------------------------------------------------------------------- */ 12580 12581 /*! 12582 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer 12583 * @{ 12584 */ 12585 12586 /** UART - Register Layout Typedef */ 12587 typedef struct { 12588 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */ 12589 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ 12590 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 12591 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 12592 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 12593 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 12594 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 12595 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 12596 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ 12597 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ 12598 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ 12599 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ 12600 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */ 12601 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */ 12602 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */ 12603 uint8_t RESERVED_0[1]; 12604 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */ 12605 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */ 12606 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */ 12607 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */ 12608 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */ 12609 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */ 12610 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */ 12611 uint8_t RESERVED_1[1]; 12612 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ 12613 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ 12614 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ 12615 union { /* offset: 0x1B */ 12616 __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ 12617 __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ 12618 }; 12619 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ 12620 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ 12621 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ 12622 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ 12623 } UART_Type, *UART_MemMapPtr; 12624 12625 /* ---------------------------------------------------------------------------- 12626 -- UART - Register accessor macros 12627 ---------------------------------------------------------------------------- */ 12628 12629 /*! 12630 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros 12631 * @{ 12632 */ 12633 12634 12635 /* UART - Register accessors */ 12636 #define UART_BDH_REG(base) ((base)->BDH) 12637 #define UART_BDL_REG(base) ((base)->BDL) 12638 #define UART_C1_REG(base) ((base)->C1) 12639 #define UART_C2_REG(base) ((base)->C2) 12640 #define UART_S1_REG(base) ((base)->S1) 12641 #define UART_S2_REG(base) ((base)->S2) 12642 #define UART_C3_REG(base) ((base)->C3) 12643 #define UART_D_REG(base) ((base)->D) 12644 #define UART_MA1_REG(base) ((base)->MA1) 12645 #define UART_MA2_REG(base) ((base)->MA2) 12646 #define UART_C4_REG(base) ((base)->C4) 12647 #define UART_C5_REG(base) ((base)->C5) 12648 #define UART_ED_REG(base) ((base)->ED) 12649 #define UART_MODEM_REG(base) ((base)->MODEM) 12650 #define UART_IR_REG(base) ((base)->IR) 12651 #define UART_PFIFO_REG(base) ((base)->PFIFO) 12652 #define UART_CFIFO_REG(base) ((base)->CFIFO) 12653 #define UART_SFIFO_REG(base) ((base)->SFIFO) 12654 #define UART_TWFIFO_REG(base) ((base)->TWFIFO) 12655 #define UART_TCFIFO_REG(base) ((base)->TCFIFO) 12656 #define UART_RWFIFO_REG(base) ((base)->RWFIFO) 12657 #define UART_RCFIFO_REG(base) ((base)->RCFIFO) 12658 #define UART_C7816_REG(base) ((base)->C7816) 12659 #define UART_IE7816_REG(base) ((base)->IE7816) 12660 #define UART_IS7816_REG(base) ((base)->IS7816) 12661 #define UART_WP7816T0_REG(base) ((base)->WP7816T0) 12662 #define UART_WP7816T1_REG(base) ((base)->WP7816T1) 12663 #define UART_WN7816_REG(base) ((base)->WN7816) 12664 #define UART_WF7816_REG(base) ((base)->WF7816) 12665 #define UART_ET7816_REG(base) ((base)->ET7816) 12666 #define UART_TL7816_REG(base) ((base)->TL7816) 12667 12668 /*! 12669 * @} 12670 */ /* end of group UART_Register_Accessor_Macros */ 12671 12672 12673 /* ---------------------------------------------------------------------------- 12674 -- UART Register Masks 12675 ---------------------------------------------------------------------------- */ 12676 12677 /*! 12678 * @addtogroup UART_Register_Masks UART Register Masks 12679 * @{ 12680 */ 12681 12682 /* BDH Bit Fields */ 12683 #define UART_BDH_SBR_MASK 0x1Fu 12684 #define UART_BDH_SBR_SHIFT 0 12685 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK) 12686 #define UART_BDH_SBNS_MASK 0x20u 12687 #define UART_BDH_SBNS_SHIFT 5 12688 #define UART_BDH_RXEDGIE_MASK 0x40u 12689 #define UART_BDH_RXEDGIE_SHIFT 6 12690 #define UART_BDH_LBKDIE_MASK 0x80u 12691 #define UART_BDH_LBKDIE_SHIFT 7 12692 /* BDL Bit Fields */ 12693 #define UART_BDL_SBR_MASK 0xFFu 12694 #define UART_BDL_SBR_SHIFT 0 12695 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK) 12696 /* C1 Bit Fields */ 12697 #define UART_C1_PT_MASK 0x1u 12698 #define UART_C1_PT_SHIFT 0 12699 #define UART_C1_PE_MASK 0x2u 12700 #define UART_C1_PE_SHIFT 1 12701 #define UART_C1_ILT_MASK 0x4u 12702 #define UART_C1_ILT_SHIFT 2 12703 #define UART_C1_WAKE_MASK 0x8u 12704 #define UART_C1_WAKE_SHIFT 3 12705 #define UART_C1_M_MASK 0x10u 12706 #define UART_C1_M_SHIFT 4 12707 #define UART_C1_RSRC_MASK 0x20u 12708 #define UART_C1_RSRC_SHIFT 5 12709 #define UART_C1_UARTSWAI_MASK 0x40u 12710 #define UART_C1_UARTSWAI_SHIFT 6 12711 #define UART_C1_LOOPS_MASK 0x80u 12712 #define UART_C1_LOOPS_SHIFT 7 12713 /* C2 Bit Fields */ 12714 #define UART_C2_SBK_MASK 0x1u 12715 #define UART_C2_SBK_SHIFT 0 12716 #define UART_C2_RWU_MASK 0x2u 12717 #define UART_C2_RWU_SHIFT 1 12718 #define UART_C2_RE_MASK 0x4u 12719 #define UART_C2_RE_SHIFT 2 12720 #define UART_C2_TE_MASK 0x8u 12721 #define UART_C2_TE_SHIFT 3 12722 #define UART_C2_ILIE_MASK 0x10u 12723 #define UART_C2_ILIE_SHIFT 4 12724 #define UART_C2_RIE_MASK 0x20u 12725 #define UART_C2_RIE_SHIFT 5 12726 #define UART_C2_TCIE_MASK 0x40u 12727 #define UART_C2_TCIE_SHIFT 6 12728 #define UART_C2_TIE_MASK 0x80u 12729 #define UART_C2_TIE_SHIFT 7 12730 /* S1 Bit Fields */ 12731 #define UART_S1_PF_MASK 0x1u 12732 #define UART_S1_PF_SHIFT 0 12733 #define UART_S1_FE_MASK 0x2u 12734 #define UART_S1_FE_SHIFT 1 12735 #define UART_S1_NF_MASK 0x4u 12736 #define UART_S1_NF_SHIFT 2 12737 #define UART_S1_OR_MASK 0x8u 12738 #define UART_S1_OR_SHIFT 3 12739 #define UART_S1_IDLE_MASK 0x10u 12740 #define UART_S1_IDLE_SHIFT 4 12741 #define UART_S1_RDRF_MASK 0x20u 12742 #define UART_S1_RDRF_SHIFT 5 12743 #define UART_S1_TC_MASK 0x40u 12744 #define UART_S1_TC_SHIFT 6 12745 #define UART_S1_TDRE_MASK 0x80u 12746 #define UART_S1_TDRE_SHIFT 7 12747 /* S2 Bit Fields */ 12748 #define UART_S2_RAF_MASK 0x1u 12749 #define UART_S2_RAF_SHIFT 0 12750 #define UART_S2_LBKDE_MASK 0x2u 12751 #define UART_S2_LBKDE_SHIFT 1 12752 #define UART_S2_BRK13_MASK 0x4u 12753 #define UART_S2_BRK13_SHIFT 2 12754 #define UART_S2_RWUID_MASK 0x8u 12755 #define UART_S2_RWUID_SHIFT 3 12756 #define UART_S2_RXINV_MASK 0x10u 12757 #define UART_S2_RXINV_SHIFT 4 12758 #define UART_S2_MSBF_MASK 0x20u 12759 #define UART_S2_MSBF_SHIFT 5 12760 #define UART_S2_RXEDGIF_MASK 0x40u 12761 #define UART_S2_RXEDGIF_SHIFT 6 12762 #define UART_S2_LBKDIF_MASK 0x80u 12763 #define UART_S2_LBKDIF_SHIFT 7 12764 /* C3 Bit Fields */ 12765 #define UART_C3_PEIE_MASK 0x1u 12766 #define UART_C3_PEIE_SHIFT 0 12767 #define UART_C3_FEIE_MASK 0x2u 12768 #define UART_C3_FEIE_SHIFT 1 12769 #define UART_C3_NEIE_MASK 0x4u 12770 #define UART_C3_NEIE_SHIFT 2 12771 #define UART_C3_ORIE_MASK 0x8u 12772 #define UART_C3_ORIE_SHIFT 3 12773 #define UART_C3_TXINV_MASK 0x10u 12774 #define UART_C3_TXINV_SHIFT 4 12775 #define UART_C3_TXDIR_MASK 0x20u 12776 #define UART_C3_TXDIR_SHIFT 5 12777 #define UART_C3_T8_MASK 0x40u 12778 #define UART_C3_T8_SHIFT 6 12779 #define UART_C3_R8_MASK 0x80u 12780 #define UART_C3_R8_SHIFT 7 12781 /* D Bit Fields */ 12782 #define UART_D_RT_MASK 0xFFu 12783 #define UART_D_RT_SHIFT 0 12784 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK) 12785 /* MA1 Bit Fields */ 12786 #define UART_MA1_MA_MASK 0xFFu 12787 #define UART_MA1_MA_SHIFT 0 12788 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK) 12789 /* MA2 Bit Fields */ 12790 #define UART_MA2_MA_MASK 0xFFu 12791 #define UART_MA2_MA_SHIFT 0 12792 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK) 12793 /* C4 Bit Fields */ 12794 #define UART_C4_BRFA_MASK 0x1Fu 12795 #define UART_C4_BRFA_SHIFT 0 12796 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK) 12797 #define UART_C4_M10_MASK 0x20u 12798 #define UART_C4_M10_SHIFT 5 12799 #define UART_C4_MAEN2_MASK 0x40u 12800 #define UART_C4_MAEN2_SHIFT 6 12801 #define UART_C4_MAEN1_MASK 0x80u 12802 #define UART_C4_MAEN1_SHIFT 7 12803 /* C5 Bit Fields */ 12804 #define UART_C5_LBKDDMAS_MASK 0x8u 12805 #define UART_C5_LBKDDMAS_SHIFT 3 12806 #define UART_C5_ILDMAS_MASK 0x10u 12807 #define UART_C5_ILDMAS_SHIFT 4 12808 #define UART_C5_RDMAS_MASK 0x20u 12809 #define UART_C5_RDMAS_SHIFT 5 12810 #define UART_C5_TCDMAS_MASK 0x40u 12811 #define UART_C5_TCDMAS_SHIFT 6 12812 #define UART_C5_TDMAS_MASK 0x80u 12813 #define UART_C5_TDMAS_SHIFT 7 12814 /* ED Bit Fields */ 12815 #define UART_ED_PARITYE_MASK 0x40u 12816 #define UART_ED_PARITYE_SHIFT 6 12817 #define UART_ED_NOISY_MASK 0x80u 12818 #define UART_ED_NOISY_SHIFT 7 12819 /* MODEM Bit Fields */ 12820 #define UART_MODEM_TXCTSE_MASK 0x1u 12821 #define UART_MODEM_TXCTSE_SHIFT 0 12822 #define UART_MODEM_TXRTSE_MASK 0x2u 12823 #define UART_MODEM_TXRTSE_SHIFT 1 12824 #define UART_MODEM_TXRTSPOL_MASK 0x4u 12825 #define UART_MODEM_TXRTSPOL_SHIFT 2 12826 #define UART_MODEM_RXRTSE_MASK 0x8u 12827 #define UART_MODEM_RXRTSE_SHIFT 3 12828 /* IR Bit Fields */ 12829 #define UART_IR_TNP_MASK 0x3u 12830 #define UART_IR_TNP_SHIFT 0 12831 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK) 12832 #define UART_IR_IREN_MASK 0x4u 12833 #define UART_IR_IREN_SHIFT 2 12834 /* PFIFO Bit Fields */ 12835 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u 12836 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0 12837 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK) 12838 #define UART_PFIFO_RXFE_MASK 0x8u 12839 #define UART_PFIFO_RXFE_SHIFT 3 12840 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u 12841 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4 12842 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK) 12843 #define UART_PFIFO_TXFE_MASK 0x80u 12844 #define UART_PFIFO_TXFE_SHIFT 7 12845 /* CFIFO Bit Fields */ 12846 #define UART_CFIFO_RXUFE_MASK 0x1u 12847 #define UART_CFIFO_RXUFE_SHIFT 0 12848 #define UART_CFIFO_TXOFE_MASK 0x2u 12849 #define UART_CFIFO_TXOFE_SHIFT 1 12850 #define UART_CFIFO_RXOFE_MASK 0x4u 12851 #define UART_CFIFO_RXOFE_SHIFT 2 12852 #define UART_CFIFO_RXFLUSH_MASK 0x40u 12853 #define UART_CFIFO_RXFLUSH_SHIFT 6 12854 #define UART_CFIFO_TXFLUSH_MASK 0x80u 12855 #define UART_CFIFO_TXFLUSH_SHIFT 7 12856 /* SFIFO Bit Fields */ 12857 #define UART_SFIFO_RXUF_MASK 0x1u 12858 #define UART_SFIFO_RXUF_SHIFT 0 12859 #define UART_SFIFO_TXOF_MASK 0x2u 12860 #define UART_SFIFO_TXOF_SHIFT 1 12861 #define UART_SFIFO_RXOF_MASK 0x4u 12862 #define UART_SFIFO_RXOF_SHIFT 2 12863 #define UART_SFIFO_RXEMPT_MASK 0x40u 12864 #define UART_SFIFO_RXEMPT_SHIFT 6 12865 #define UART_SFIFO_TXEMPT_MASK 0x80u 12866 #define UART_SFIFO_TXEMPT_SHIFT 7 12867 /* TWFIFO Bit Fields */ 12868 #define UART_TWFIFO_TXWATER_MASK 0xFFu 12869 #define UART_TWFIFO_TXWATER_SHIFT 0 12870 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK) 12871 /* TCFIFO Bit Fields */ 12872 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu 12873 #define UART_TCFIFO_TXCOUNT_SHIFT 0 12874 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK) 12875 /* RWFIFO Bit Fields */ 12876 #define UART_RWFIFO_RXWATER_MASK 0xFFu 12877 #define UART_RWFIFO_RXWATER_SHIFT 0 12878 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK) 12879 /* RCFIFO Bit Fields */ 12880 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu 12881 #define UART_RCFIFO_RXCOUNT_SHIFT 0 12882 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK) 12883 /* C7816 Bit Fields */ 12884 #define UART_C7816_ISO_7816E_MASK 0x1u 12885 #define UART_C7816_ISO_7816E_SHIFT 0 12886 #define UART_C7816_TTYPE_MASK 0x2u 12887 #define UART_C7816_TTYPE_SHIFT 1 12888 #define UART_C7816_INIT_MASK 0x4u 12889 #define UART_C7816_INIT_SHIFT 2 12890 #define UART_C7816_ANACK_MASK 0x8u 12891 #define UART_C7816_ANACK_SHIFT 3 12892 #define UART_C7816_ONACK_MASK 0x10u 12893 #define UART_C7816_ONACK_SHIFT 4 12894 /* IE7816 Bit Fields */ 12895 #define UART_IE7816_RXTE_MASK 0x1u 12896 #define UART_IE7816_RXTE_SHIFT 0 12897 #define UART_IE7816_TXTE_MASK 0x2u 12898 #define UART_IE7816_TXTE_SHIFT 1 12899 #define UART_IE7816_GTVE_MASK 0x4u 12900 #define UART_IE7816_GTVE_SHIFT 2 12901 #define UART_IE7816_INITDE_MASK 0x10u 12902 #define UART_IE7816_INITDE_SHIFT 4 12903 #define UART_IE7816_BWTE_MASK 0x20u 12904 #define UART_IE7816_BWTE_SHIFT 5 12905 #define UART_IE7816_CWTE_MASK 0x40u 12906 #define UART_IE7816_CWTE_SHIFT 6 12907 #define UART_IE7816_WTE_MASK 0x80u 12908 #define UART_IE7816_WTE_SHIFT 7 12909 /* IS7816 Bit Fields */ 12910 #define UART_IS7816_RXT_MASK 0x1u 12911 #define UART_IS7816_RXT_SHIFT 0 12912 #define UART_IS7816_TXT_MASK 0x2u 12913 #define UART_IS7816_TXT_SHIFT 1 12914 #define UART_IS7816_GTV_MASK 0x4u 12915 #define UART_IS7816_GTV_SHIFT 2 12916 #define UART_IS7816_INITD_MASK 0x10u 12917 #define UART_IS7816_INITD_SHIFT 4 12918 #define UART_IS7816_BWT_MASK 0x20u 12919 #define UART_IS7816_BWT_SHIFT 5 12920 #define UART_IS7816_CWT_MASK 0x40u 12921 #define UART_IS7816_CWT_SHIFT 6 12922 #define UART_IS7816_WT_MASK 0x80u 12923 #define UART_IS7816_WT_SHIFT 7 12924 /* WP7816T0 Bit Fields */ 12925 #define UART_WP7816T0_WI_MASK 0xFFu 12926 #define UART_WP7816T0_WI_SHIFT 0 12927 #define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T0_WI_SHIFT))&UART_WP7816T0_WI_MASK) 12928 /* WP7816T1 Bit Fields */ 12929 #define UART_WP7816T1_BWI_MASK 0xFu 12930 #define UART_WP7816T1_BWI_SHIFT 0 12931 #define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_BWI_SHIFT))&UART_WP7816T1_BWI_MASK) 12932 #define UART_WP7816T1_CWI_MASK 0xF0u 12933 #define UART_WP7816T1_CWI_SHIFT 4 12934 #define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_CWI_SHIFT))&UART_WP7816T1_CWI_MASK) 12935 /* WN7816 Bit Fields */ 12936 #define UART_WN7816_GTN_MASK 0xFFu 12937 #define UART_WN7816_GTN_SHIFT 0 12938 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK) 12939 /* WF7816 Bit Fields */ 12940 #define UART_WF7816_GTFD_MASK 0xFFu 12941 #define UART_WF7816_GTFD_SHIFT 0 12942 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK) 12943 /* ET7816 Bit Fields */ 12944 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu 12945 #define UART_ET7816_RXTHRESHOLD_SHIFT 0 12946 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK) 12947 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u 12948 #define UART_ET7816_TXTHRESHOLD_SHIFT 4 12949 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK) 12950 /* TL7816 Bit Fields */ 12951 #define UART_TL7816_TLEN_MASK 0xFFu 12952 #define UART_TL7816_TLEN_SHIFT 0 12953 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK) 12954 12955 /*! 12956 * @} 12957 */ /* end of group UART_Register_Masks */ 12958 12959 12960 /* UART - Peripheral instance base addresses */ 12961 /** Peripheral UART0 base address */ 12962 #define UART0_BASE (0x4006A000u) 12963 /** Peripheral UART0 base pointer */ 12964 #define UART0 ((UART_Type *)UART0_BASE) 12965 #define UART0_BASE_PTR (UART0) 12966 /** Peripheral UART1 base address */ 12967 #define UART1_BASE (0x4006B000u) 12968 /** Peripheral UART1 base pointer */ 12969 #define UART1 ((UART_Type *)UART1_BASE) 12970 #define UART1_BASE_PTR (UART1) 12971 /** Peripheral UART2 base address */ 12972 #define UART2_BASE (0x4006C000u) 12973 /** Peripheral UART2 base pointer */ 12974 #define UART2 ((UART_Type *)UART2_BASE) 12975 #define UART2_BASE_PTR (UART2) 12976 /** Peripheral UART3 base address */ 12977 #define UART3_BASE (0x4006D000u) 12978 /** Peripheral UART3 base pointer */ 12979 #define UART3 ((UART_Type *)UART3_BASE) 12980 #define UART3_BASE_PTR (UART3) 12981 /** Peripheral UART4 base address */ 12982 #define UART4_BASE (0x400EA000u) 12983 /** Peripheral UART4 base pointer */ 12984 #define UART4 ((UART_Type *)UART4_BASE) 12985 #define UART4_BASE_PTR (UART4) 12986 /** Peripheral UART5 base address */ 12987 #define UART5_BASE (0x400EB000u) 12988 /** Peripheral UART5 base pointer */ 12989 #define UART5 ((UART_Type *)UART5_BASE) 12990 #define UART5_BASE_PTR (UART5) 12991 /** Array initializer of UART peripheral base addresses */ 12992 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE } 12993 /** Array initializer of UART peripheral base pointers */ 12994 #define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 } 12995 /** Interrupt vectors for the UART peripheral type */ 12996 #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn } 12997 #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn } 12998 #define UART_LON_IRQS { UART0_LON_IRQn, 0, 0, 0, 0, 0 } 12999 13000 /* ---------------------------------------------------------------------------- 13001 -- UART - Register accessor macros 13002 ---------------------------------------------------------------------------- */ 13003 13004 /*! 13005 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros 13006 * @{ 13007 */ 13008 13009 13010 /* UART - Register instance definitions */ 13011 /* UART0 */ 13012 #define UART0_BDH UART_BDH_REG(UART0) 13013 #define UART0_BDL UART_BDL_REG(UART0) 13014 #define UART0_C1 UART_C1_REG(UART0) 13015 #define UART0_C2 UART_C2_REG(UART0) 13016 #define UART0_S1 UART_S1_REG(UART0) 13017 #define UART0_S2 UART_S2_REG(UART0) 13018 #define UART0_C3 UART_C3_REG(UART0) 13019 #define UART0_D UART_D_REG(UART0) 13020 #define UART0_MA1 UART_MA1_REG(UART0) 13021 #define UART0_MA2 UART_MA2_REG(UART0) 13022 #define UART0_C4 UART_C4_REG(UART0) 13023 #define UART0_C5 UART_C5_REG(UART0) 13024 #define UART0_ED UART_ED_REG(UART0) 13025 #define UART0_MODEM UART_MODEM_REG(UART0) 13026 #define UART0_IR UART_IR_REG(UART0) 13027 #define UART0_PFIFO UART_PFIFO_REG(UART0) 13028 #define UART0_CFIFO UART_CFIFO_REG(UART0) 13029 #define UART0_SFIFO UART_SFIFO_REG(UART0) 13030 #define UART0_TWFIFO UART_TWFIFO_REG(UART0) 13031 #define UART0_TCFIFO UART_TCFIFO_REG(UART0) 13032 #define UART0_RWFIFO UART_RWFIFO_REG(UART0) 13033 #define UART0_RCFIFO UART_RCFIFO_REG(UART0) 13034 #define UART0_C7816 UART_C7816_REG(UART0) 13035 #define UART0_IE7816 UART_IE7816_REG(UART0) 13036 #define UART0_IS7816 UART_IS7816_REG(UART0) 13037 #define UART0_WP7816T0 UART_WP7816T0_REG(UART0) 13038 #define UART0_WP7816T1 UART_WP7816T1_REG(UART0) 13039 #define UART0_WN7816 UART_WN7816_REG(UART0) 13040 #define UART0_WF7816 UART_WF7816_REG(UART0) 13041 #define UART0_ET7816 UART_ET7816_REG(UART0) 13042 #define UART0_TL7816 UART_TL7816_REG(UART0) 13043 /* UART1 */ 13044 #define UART1_BDH UART_BDH_REG(UART1) 13045 #define UART1_BDL UART_BDL_REG(UART1) 13046 #define UART1_C1 UART_C1_REG(UART1) 13047 #define UART1_C2 UART_C2_REG(UART1) 13048 #define UART1_S1 UART_S1_REG(UART1) 13049 #define UART1_S2 UART_S2_REG(UART1) 13050 #define UART1_C3 UART_C3_REG(UART1) 13051 #define UART1_D UART_D_REG(UART1) 13052 #define UART1_MA1 UART_MA1_REG(UART1) 13053 #define UART1_MA2 UART_MA2_REG(UART1) 13054 #define UART1_C4 UART_C4_REG(UART1) 13055 #define UART1_C5 UART_C5_REG(UART1) 13056 #define UART1_ED UART_ED_REG(UART1) 13057 #define UART1_MODEM UART_MODEM_REG(UART1) 13058 #define UART1_IR UART_IR_REG(UART1) 13059 #define UART1_PFIFO UART_PFIFO_REG(UART1) 13060 #define UART1_CFIFO UART_CFIFO_REG(UART1) 13061 #define UART1_SFIFO UART_SFIFO_REG(UART1) 13062 #define UART1_TWFIFO UART_TWFIFO_REG(UART1) 13063 #define UART1_TCFIFO UART_TCFIFO_REG(UART1) 13064 #define UART1_RWFIFO UART_RWFIFO_REG(UART1) 13065 #define UART1_RCFIFO UART_RCFIFO_REG(UART1) 13066 /* UART2 */ 13067 #define UART2_BDH UART_BDH_REG(UART2) 13068 #define UART2_BDL UART_BDL_REG(UART2) 13069 #define UART2_C1 UART_C1_REG(UART2) 13070 #define UART2_C2 UART_C2_REG(UART2) 13071 #define UART2_S1 UART_S1_REG(UART2) 13072 #define UART2_S2 UART_S2_REG(UART2) 13073 #define UART2_C3 UART_C3_REG(UART2) 13074 #define UART2_D UART_D_REG(UART2) 13075 #define UART2_MA1 UART_MA1_REG(UART2) 13076 #define UART2_MA2 UART_MA2_REG(UART2) 13077 #define UART2_C4 UART_C4_REG(UART2) 13078 #define UART2_C5 UART_C5_REG(UART2) 13079 #define UART2_ED UART_ED_REG(UART2) 13080 #define UART2_MODEM UART_MODEM_REG(UART2) 13081 #define UART2_IR UART_IR_REG(UART2) 13082 #define UART2_PFIFO UART_PFIFO_REG(UART2) 13083 #define UART2_CFIFO UART_CFIFO_REG(UART2) 13084 #define UART2_SFIFO UART_SFIFO_REG(UART2) 13085 #define UART2_TWFIFO UART_TWFIFO_REG(UART2) 13086 #define UART2_TCFIFO UART_TCFIFO_REG(UART2) 13087 #define UART2_RWFIFO UART_RWFIFO_REG(UART2) 13088 #define UART2_RCFIFO UART_RCFIFO_REG(UART2) 13089 /* UART3 */ 13090 #define UART3_BDH UART_BDH_REG(UART3) 13091 #define UART3_BDL UART_BDL_REG(UART3) 13092 #define UART3_C1 UART_C1_REG(UART3) 13093 #define UART3_C2 UART_C2_REG(UART3) 13094 #define UART3_S1 UART_S1_REG(UART3) 13095 #define UART3_S2 UART_S2_REG(UART3) 13096 #define UART3_C3 UART_C3_REG(UART3) 13097 #define UART3_D UART_D_REG(UART3) 13098 #define UART3_MA1 UART_MA1_REG(UART3) 13099 #define UART3_MA2 UART_MA2_REG(UART3) 13100 #define UART3_C4 UART_C4_REG(UART3) 13101 #define UART3_C5 UART_C5_REG(UART3) 13102 #define UART3_ED UART_ED_REG(UART3) 13103 #define UART3_MODEM UART_MODEM_REG(UART3) 13104 #define UART3_IR UART_IR_REG(UART3) 13105 #define UART3_PFIFO UART_PFIFO_REG(UART3) 13106 #define UART3_CFIFO UART_CFIFO_REG(UART3) 13107 #define UART3_SFIFO UART_SFIFO_REG(UART3) 13108 #define UART3_TWFIFO UART_TWFIFO_REG(UART3) 13109 #define UART3_TCFIFO UART_TCFIFO_REG(UART3) 13110 #define UART3_RWFIFO UART_RWFIFO_REG(UART3) 13111 #define UART3_RCFIFO UART_RCFIFO_REG(UART3) 13112 /* UART4 */ 13113 #define UART4_BDH UART_BDH_REG(UART4) 13114 #define UART4_BDL UART_BDL_REG(UART4) 13115 #define UART4_C1 UART_C1_REG(UART4) 13116 #define UART4_C2 UART_C2_REG(UART4) 13117 #define UART4_S1 UART_S1_REG(UART4) 13118 #define UART4_S2 UART_S2_REG(UART4) 13119 #define UART4_C3 UART_C3_REG(UART4) 13120 #define UART4_D UART_D_REG(UART4) 13121 #define UART4_MA1 UART_MA1_REG(UART4) 13122 #define UART4_MA2 UART_MA2_REG(UART4) 13123 #define UART4_C4 UART_C4_REG(UART4) 13124 #define UART4_C5 UART_C5_REG(UART4) 13125 #define UART4_ED UART_ED_REG(UART4) 13126 #define UART4_MODEM UART_MODEM_REG(UART4) 13127 #define UART4_IR UART_IR_REG(UART4) 13128 #define UART4_PFIFO UART_PFIFO_REG(UART4) 13129 #define UART4_CFIFO UART_CFIFO_REG(UART4) 13130 #define UART4_SFIFO UART_SFIFO_REG(UART4) 13131 #define UART4_TWFIFO UART_TWFIFO_REG(UART4) 13132 #define UART4_TCFIFO UART_TCFIFO_REG(UART4) 13133 #define UART4_RWFIFO UART_RWFIFO_REG(UART4) 13134 #define UART4_RCFIFO UART_RCFIFO_REG(UART4) 13135 /* UART5 */ 13136 #define UART5_BDH UART_BDH_REG(UART5) 13137 #define UART5_BDL UART_BDL_REG(UART5) 13138 #define UART5_C1 UART_C1_REG(UART5) 13139 #define UART5_C2 UART_C2_REG(UART5) 13140 #define UART5_S1 UART_S1_REG(UART5) 13141 #define UART5_S2 UART_S2_REG(UART5) 13142 #define UART5_C3 UART_C3_REG(UART5) 13143 #define UART5_D UART_D_REG(UART5) 13144 #define UART5_MA1 UART_MA1_REG(UART5) 13145 #define UART5_MA2 UART_MA2_REG(UART5) 13146 #define UART5_C4 UART_C4_REG(UART5) 13147 #define UART5_C5 UART_C5_REG(UART5) 13148 #define UART5_ED UART_ED_REG(UART5) 13149 #define UART5_MODEM UART_MODEM_REG(UART5) 13150 #define UART5_IR UART_IR_REG(UART5) 13151 #define UART5_PFIFO UART_PFIFO_REG(UART5) 13152 #define UART5_CFIFO UART_CFIFO_REG(UART5) 13153 #define UART5_SFIFO UART_SFIFO_REG(UART5) 13154 #define UART5_TWFIFO UART_TWFIFO_REG(UART5) 13155 #define UART5_TCFIFO UART_TCFIFO_REG(UART5) 13156 #define UART5_RWFIFO UART_RWFIFO_REG(UART5) 13157 #define UART5_RCFIFO UART_RCFIFO_REG(UART5) 13158 13159 /*! 13160 * @} 13161 */ /* end of group UART_Register_Accessor_Macros */ 13162 13163 13164 /*! 13165 * @} 13166 */ /* end of group UART_Peripheral_Access_Layer */ 13167 13168 13169 /* ---------------------------------------------------------------------------- 13170 -- USB Peripheral Access Layer 13171 ---------------------------------------------------------------------------- */ 13172 13173 /*! 13174 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer 13175 * @{ 13176 */ 13177 13178 /** USB - Register Layout Typedef */ 13179 typedef struct { 13180 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ 13181 uint8_t RESERVED_0[3]; 13182 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ 13183 uint8_t RESERVED_1[3]; 13184 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ 13185 uint8_t RESERVED_2[3]; 13186 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ 13187 uint8_t RESERVED_3[3]; 13188 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */ 13189 uint8_t RESERVED_4[3]; 13190 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */ 13191 uint8_t RESERVED_5[3]; 13192 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */ 13193 uint8_t RESERVED_6[3]; 13194 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ 13195 uint8_t RESERVED_7[99]; 13196 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ 13197 uint8_t RESERVED_8[3]; 13198 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ 13199 uint8_t RESERVED_9[3]; 13200 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ 13201 uint8_t RESERVED_10[3]; 13202 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ 13203 uint8_t RESERVED_11[3]; 13204 __I uint8_t STAT; /**< Status register, offset: 0x90 */ 13205 uint8_t RESERVED_12[3]; 13206 __IO uint8_t CTL; /**< Control register, offset: 0x94 */ 13207 uint8_t RESERVED_13[3]; 13208 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ 13209 uint8_t RESERVED_14[3]; 13210 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */ 13211 uint8_t RESERVED_15[3]; 13212 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */ 13213 uint8_t RESERVED_16[3]; 13214 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */ 13215 uint8_t RESERVED_17[3]; 13216 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */ 13217 uint8_t RESERVED_18[3]; 13218 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */ 13219 uint8_t RESERVED_19[3]; 13220 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ 13221 uint8_t RESERVED_20[3]; 13222 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ 13223 uint8_t RESERVED_21[11]; 13224 struct { /* offset: 0xC0, array step: 0x4 */ 13225 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ 13226 uint8_t RESERVED_0[3]; 13227 } ENDPOINT[16]; 13228 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ 13229 uint8_t RESERVED_22[3]; 13230 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ 13231 uint8_t RESERVED_23[3]; 13232 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ 13233 uint8_t RESERVED_24[3]; 13234 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */ 13235 uint8_t RESERVED_25[7]; 13236 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ 13237 uint8_t RESERVED_26[43]; 13238 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */ 13239 uint8_t RESERVED_27[3]; 13240 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */ 13241 uint8_t RESERVED_28[23]; 13242 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */ 13243 } USB_Type, *USB_MemMapPtr; 13244 13245 /* ---------------------------------------------------------------------------- 13246 -- USB - Register accessor macros 13247 ---------------------------------------------------------------------------- */ 13248 13249 /*! 13250 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros 13251 * @{ 13252 */ 13253 13254 13255 /* USB - Register accessors */ 13256 #define USB_PERID_REG(base) ((base)->PERID) 13257 #define USB_IDCOMP_REG(base) ((base)->IDCOMP) 13258 #define USB_REV_REG(base) ((base)->REV) 13259 #define USB_ADDINFO_REG(base) ((base)->ADDINFO) 13260 #define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) 13261 #define USB_OTGICR_REG(base) ((base)->OTGICR) 13262 #define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) 13263 #define USB_OTGCTL_REG(base) ((base)->OTGCTL) 13264 #define USB_ISTAT_REG(base) ((base)->ISTAT) 13265 #define USB_INTEN_REG(base) ((base)->INTEN) 13266 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) 13267 #define USB_ERREN_REG(base) ((base)->ERREN) 13268 #define USB_STAT_REG(base) ((base)->STAT) 13269 #define USB_CTL_REG(base) ((base)->CTL) 13270 #define USB_ADDR_REG(base) ((base)->ADDR) 13271 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) 13272 #define USB_FRMNUML_REG(base) ((base)->FRMNUML) 13273 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) 13274 #define USB_TOKEN_REG(base) ((base)->TOKEN) 13275 #define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) 13276 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) 13277 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) 13278 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) 13279 #define USB_USBCTRL_REG(base) ((base)->USBCTRL) 13280 #define USB_OBSERVE_REG(base) ((base)->OBSERVE) 13281 #define USB_CONTROL_REG(base) ((base)->CONTROL) 13282 #define USB_USBTRC0_REG(base) ((base)->USBTRC0) 13283 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) 13284 #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL) 13285 #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN) 13286 #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS) 13287 13288 /*! 13289 * @} 13290 */ /* end of group USB_Register_Accessor_Macros */ 13291 13292 13293 /* ---------------------------------------------------------------------------- 13294 -- USB Register Masks 13295 ---------------------------------------------------------------------------- */ 13296 13297 /*! 13298 * @addtogroup USB_Register_Masks USB Register Masks 13299 * @{ 13300 */ 13301 13302 /* PERID Bit Fields */ 13303 #define USB_PERID_ID_MASK 0x3Fu 13304 #define USB_PERID_ID_SHIFT 0 13305 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK) 13306 /* IDCOMP Bit Fields */ 13307 #define USB_IDCOMP_NID_MASK 0x3Fu 13308 #define USB_IDCOMP_NID_SHIFT 0 13309 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK) 13310 /* REV Bit Fields */ 13311 #define USB_REV_REV_MASK 0xFFu 13312 #define USB_REV_REV_SHIFT 0 13313 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK) 13314 /* ADDINFO Bit Fields */ 13315 #define USB_ADDINFO_IEHOST_MASK 0x1u 13316 #define USB_ADDINFO_IEHOST_SHIFT 0 13317 #define USB_ADDINFO_IRQNUM_MASK 0xF8u 13318 #define USB_ADDINFO_IRQNUM_SHIFT 3 13319 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK) 13320 /* OTGISTAT Bit Fields */ 13321 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u 13322 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0 13323 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u 13324 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2 13325 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u 13326 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3 13327 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u 13328 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5 13329 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u 13330 #define USB_OTGISTAT_ONEMSEC_SHIFT 6 13331 #define USB_OTGISTAT_IDCHG_MASK 0x80u 13332 #define USB_OTGISTAT_IDCHG_SHIFT 7 13333 /* OTGICR Bit Fields */ 13334 #define USB_OTGICR_AVBUSEN_MASK 0x1u 13335 #define USB_OTGICR_AVBUSEN_SHIFT 0 13336 #define USB_OTGICR_BSESSEN_MASK 0x4u 13337 #define USB_OTGICR_BSESSEN_SHIFT 2 13338 #define USB_OTGICR_SESSVLDEN_MASK 0x8u 13339 #define USB_OTGICR_SESSVLDEN_SHIFT 3 13340 #define USB_OTGICR_LINESTATEEN_MASK 0x20u 13341 #define USB_OTGICR_LINESTATEEN_SHIFT 5 13342 #define USB_OTGICR_ONEMSECEN_MASK 0x40u 13343 #define USB_OTGICR_ONEMSECEN_SHIFT 6 13344 #define USB_OTGICR_IDEN_MASK 0x80u 13345 #define USB_OTGICR_IDEN_SHIFT 7 13346 /* OTGSTAT Bit Fields */ 13347 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u 13348 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0 13349 #define USB_OTGSTAT_BSESSEND_MASK 0x4u 13350 #define USB_OTGSTAT_BSESSEND_SHIFT 2 13351 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u 13352 #define USB_OTGSTAT_SESS_VLD_SHIFT 3 13353 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u 13354 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5 13355 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u 13356 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6 13357 #define USB_OTGSTAT_ID_MASK 0x80u 13358 #define USB_OTGSTAT_ID_SHIFT 7 13359 /* OTGCTL Bit Fields */ 13360 #define USB_OTGCTL_OTGEN_MASK 0x4u 13361 #define USB_OTGCTL_OTGEN_SHIFT 2 13362 #define USB_OTGCTL_DMLOW_MASK 0x10u 13363 #define USB_OTGCTL_DMLOW_SHIFT 4 13364 #define USB_OTGCTL_DPLOW_MASK 0x20u 13365 #define USB_OTGCTL_DPLOW_SHIFT 5 13366 #define USB_OTGCTL_DPHIGH_MASK 0x80u 13367 #define USB_OTGCTL_DPHIGH_SHIFT 7 13368 /* ISTAT Bit Fields */ 13369 #define USB_ISTAT_USBRST_MASK 0x1u 13370 #define USB_ISTAT_USBRST_SHIFT 0 13371 #define USB_ISTAT_ERROR_MASK 0x2u 13372 #define USB_ISTAT_ERROR_SHIFT 1 13373 #define USB_ISTAT_SOFTOK_MASK 0x4u 13374 #define USB_ISTAT_SOFTOK_SHIFT 2 13375 #define USB_ISTAT_TOKDNE_MASK 0x8u 13376 #define USB_ISTAT_TOKDNE_SHIFT 3 13377 #define USB_ISTAT_SLEEP_MASK 0x10u 13378 #define USB_ISTAT_SLEEP_SHIFT 4 13379 #define USB_ISTAT_RESUME_MASK 0x20u 13380 #define USB_ISTAT_RESUME_SHIFT 5 13381 #define USB_ISTAT_ATTACH_MASK 0x40u 13382 #define USB_ISTAT_ATTACH_SHIFT 6 13383 #define USB_ISTAT_STALL_MASK 0x80u 13384 #define USB_ISTAT_STALL_SHIFT 7 13385 /* INTEN Bit Fields */ 13386 #define USB_INTEN_USBRSTEN_MASK 0x1u 13387 #define USB_INTEN_USBRSTEN_SHIFT 0 13388 #define USB_INTEN_ERROREN_MASK 0x2u 13389 #define USB_INTEN_ERROREN_SHIFT 1 13390 #define USB_INTEN_SOFTOKEN_MASK 0x4u 13391 #define USB_INTEN_SOFTOKEN_SHIFT 2 13392 #define USB_INTEN_TOKDNEEN_MASK 0x8u 13393 #define USB_INTEN_TOKDNEEN_SHIFT 3 13394 #define USB_INTEN_SLEEPEN_MASK 0x10u 13395 #define USB_INTEN_SLEEPEN_SHIFT 4 13396 #define USB_INTEN_RESUMEEN_MASK 0x20u 13397 #define USB_INTEN_RESUMEEN_SHIFT 5 13398 #define USB_INTEN_ATTACHEN_MASK 0x40u 13399 #define USB_INTEN_ATTACHEN_SHIFT 6 13400 #define USB_INTEN_STALLEN_MASK 0x80u 13401 #define USB_INTEN_STALLEN_SHIFT 7 13402 /* ERRSTAT Bit Fields */ 13403 #define USB_ERRSTAT_PIDERR_MASK 0x1u 13404 #define USB_ERRSTAT_PIDERR_SHIFT 0 13405 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u 13406 #define USB_ERRSTAT_CRC5EOF_SHIFT 1 13407 #define USB_ERRSTAT_CRC16_MASK 0x4u 13408 #define USB_ERRSTAT_CRC16_SHIFT 2 13409 #define USB_ERRSTAT_DFN8_MASK 0x8u 13410 #define USB_ERRSTAT_DFN8_SHIFT 3 13411 #define USB_ERRSTAT_BTOERR_MASK 0x10u 13412 #define USB_ERRSTAT_BTOERR_SHIFT 4 13413 #define USB_ERRSTAT_DMAERR_MASK 0x20u 13414 #define USB_ERRSTAT_DMAERR_SHIFT 5 13415 #define USB_ERRSTAT_BTSERR_MASK 0x80u 13416 #define USB_ERRSTAT_BTSERR_SHIFT 7 13417 /* ERREN Bit Fields */ 13418 #define USB_ERREN_PIDERREN_MASK 0x1u 13419 #define USB_ERREN_PIDERREN_SHIFT 0 13420 #define USB_ERREN_CRC5EOFEN_MASK 0x2u 13421 #define USB_ERREN_CRC5EOFEN_SHIFT 1 13422 #define USB_ERREN_CRC16EN_MASK 0x4u 13423 #define USB_ERREN_CRC16EN_SHIFT 2 13424 #define USB_ERREN_DFN8EN_MASK 0x8u 13425 #define USB_ERREN_DFN8EN_SHIFT 3 13426 #define USB_ERREN_BTOERREN_MASK 0x10u 13427 #define USB_ERREN_BTOERREN_SHIFT 4 13428 #define USB_ERREN_DMAERREN_MASK 0x20u 13429 #define USB_ERREN_DMAERREN_SHIFT 5 13430 #define USB_ERREN_BTSERREN_MASK 0x80u 13431 #define USB_ERREN_BTSERREN_SHIFT 7 13432 /* STAT Bit Fields */ 13433 #define USB_STAT_ODD_MASK 0x4u 13434 #define USB_STAT_ODD_SHIFT 2 13435 #define USB_STAT_TX_MASK 0x8u 13436 #define USB_STAT_TX_SHIFT 3 13437 #define USB_STAT_ENDP_MASK 0xF0u 13438 #define USB_STAT_ENDP_SHIFT 4 13439 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK) 13440 /* CTL Bit Fields */ 13441 #define USB_CTL_USBENSOFEN_MASK 0x1u 13442 #define USB_CTL_USBENSOFEN_SHIFT 0 13443 #define USB_CTL_ODDRST_MASK 0x2u 13444 #define USB_CTL_ODDRST_SHIFT 1 13445 #define USB_CTL_RESUME_MASK 0x4u 13446 #define USB_CTL_RESUME_SHIFT 2 13447 #define USB_CTL_HOSTMODEEN_MASK 0x8u 13448 #define USB_CTL_HOSTMODEEN_SHIFT 3 13449 #define USB_CTL_RESET_MASK 0x10u 13450 #define USB_CTL_RESET_SHIFT 4 13451 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u 13452 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5 13453 #define USB_CTL_SE0_MASK 0x40u 13454 #define USB_CTL_SE0_SHIFT 6 13455 #define USB_CTL_JSTATE_MASK 0x80u 13456 #define USB_CTL_JSTATE_SHIFT 7 13457 /* ADDR Bit Fields */ 13458 #define USB_ADDR_ADDR_MASK 0x7Fu 13459 #define USB_ADDR_ADDR_SHIFT 0 13460 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK) 13461 #define USB_ADDR_LSEN_MASK 0x80u 13462 #define USB_ADDR_LSEN_SHIFT 7 13463 /* BDTPAGE1 Bit Fields */ 13464 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu 13465 #define USB_BDTPAGE1_BDTBA_SHIFT 1 13466 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK) 13467 /* FRMNUML Bit Fields */ 13468 #define USB_FRMNUML_FRM_MASK 0xFFu 13469 #define USB_FRMNUML_FRM_SHIFT 0 13470 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK) 13471 /* FRMNUMH Bit Fields */ 13472 #define USB_FRMNUMH_FRM_MASK 0x7u 13473 #define USB_FRMNUMH_FRM_SHIFT 0 13474 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK) 13475 /* TOKEN Bit Fields */ 13476 #define USB_TOKEN_TOKENENDPT_MASK 0xFu 13477 #define USB_TOKEN_TOKENENDPT_SHIFT 0 13478 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK) 13479 #define USB_TOKEN_TOKENPID_MASK 0xF0u 13480 #define USB_TOKEN_TOKENPID_SHIFT 4 13481 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK) 13482 /* SOFTHLD Bit Fields */ 13483 #define USB_SOFTHLD_CNT_MASK 0xFFu 13484 #define USB_SOFTHLD_CNT_SHIFT 0 13485 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK) 13486 /* BDTPAGE2 Bit Fields */ 13487 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu 13488 #define USB_BDTPAGE2_BDTBA_SHIFT 0 13489 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK) 13490 /* BDTPAGE3 Bit Fields */ 13491 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu 13492 #define USB_BDTPAGE3_BDTBA_SHIFT 0 13493 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK) 13494 /* ENDPT Bit Fields */ 13495 #define USB_ENDPT_EPHSHK_MASK 0x1u 13496 #define USB_ENDPT_EPHSHK_SHIFT 0 13497 #define USB_ENDPT_EPSTALL_MASK 0x2u 13498 #define USB_ENDPT_EPSTALL_SHIFT 1 13499 #define USB_ENDPT_EPTXEN_MASK 0x4u 13500 #define USB_ENDPT_EPTXEN_SHIFT 2 13501 #define USB_ENDPT_EPRXEN_MASK 0x8u 13502 #define USB_ENDPT_EPRXEN_SHIFT 3 13503 #define USB_ENDPT_EPCTLDIS_MASK 0x10u 13504 #define USB_ENDPT_EPCTLDIS_SHIFT 4 13505 #define USB_ENDPT_RETRYDIS_MASK 0x40u 13506 #define USB_ENDPT_RETRYDIS_SHIFT 6 13507 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u 13508 #define USB_ENDPT_HOSTWOHUB_SHIFT 7 13509 /* USBCTRL Bit Fields */ 13510 #define USB_USBCTRL_PDE_MASK 0x40u 13511 #define USB_USBCTRL_PDE_SHIFT 6 13512 #define USB_USBCTRL_SUSP_MASK 0x80u 13513 #define USB_USBCTRL_SUSP_SHIFT 7 13514 /* OBSERVE Bit Fields */ 13515 #define USB_OBSERVE_DMPD_MASK 0x10u 13516 #define USB_OBSERVE_DMPD_SHIFT 4 13517 #define USB_OBSERVE_DPPD_MASK 0x40u 13518 #define USB_OBSERVE_DPPD_SHIFT 6 13519 #define USB_OBSERVE_DPPU_MASK 0x80u 13520 #define USB_OBSERVE_DPPU_SHIFT 7 13521 /* CONTROL Bit Fields */ 13522 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u 13523 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4 13524 /* USBTRC0 Bit Fields */ 13525 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u 13526 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0 13527 #define USB_USBTRC0_SYNC_DET_MASK 0x2u 13528 #define USB_USBTRC0_SYNC_DET_SHIFT 1 13529 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u 13530 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2 13531 #define USB_USBTRC0_USBRESMEN_MASK 0x20u 13532 #define USB_USBTRC0_USBRESMEN_SHIFT 5 13533 #define USB_USBTRC0_USBRESET_MASK 0x80u 13534 #define USB_USBTRC0_USBRESET_SHIFT 7 13535 /* USBFRMADJUST Bit Fields */ 13536 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu 13537 #define USB_USBFRMADJUST_ADJ_SHIFT 0 13538 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK) 13539 /* CLK_RECOVER_CTRL Bit Fields */ 13540 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u 13541 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5 13542 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u 13543 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6 13544 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u 13545 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7 13546 /* CLK_RECOVER_IRC_EN Bit Fields */ 13547 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u 13548 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0 13549 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u 13550 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1 13551 /* CLK_RECOVER_INT_STATUS Bit Fields */ 13552 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u 13553 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4 13554 13555 /*! 13556 * @} 13557 */ /* end of group USB_Register_Masks */ 13558 13559 13560 /* USB - Peripheral instance base addresses */ 13561 /** Peripheral USB0 base address */ 13562 #define USB0_BASE (0x40072000u) 13563 /** Peripheral USB0 base pointer */ 13564 #define USB0 ((USB_Type *)USB0_BASE) 13565 #define USB0_BASE_PTR (USB0) 13566 /** Array initializer of USB peripheral base addresses */ 13567 #define USB_BASE_ADDRS { USB0_BASE } 13568 /** Array initializer of USB peripheral base pointers */ 13569 #define USB_BASE_PTRS { USB0 } 13570 /** Interrupt vectors for the USB peripheral type */ 13571 #define USB_IRQS { USB0_IRQn } 13572 13573 /* ---------------------------------------------------------------------------- 13574 -- USB - Register accessor macros 13575 ---------------------------------------------------------------------------- */ 13576 13577 /*! 13578 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros 13579 * @{ 13580 */ 13581 13582 13583 /* USB - Register instance definitions */ 13584 /* USB0 */ 13585 #define USB0_PERID USB_PERID_REG(USB0) 13586 #define USB0_IDCOMP USB_IDCOMP_REG(USB0) 13587 #define USB0_REV USB_REV_REG(USB0) 13588 #define USB0_ADDINFO USB_ADDINFO_REG(USB0) 13589 #define USB0_OTGISTAT USB_OTGISTAT_REG(USB0) 13590 #define USB0_OTGICR USB_OTGICR_REG(USB0) 13591 #define USB0_OTGSTAT USB_OTGSTAT_REG(USB0) 13592 #define USB0_OTGCTL USB_OTGCTL_REG(USB0) 13593 #define USB0_ISTAT USB_ISTAT_REG(USB0) 13594 #define USB0_INTEN USB_INTEN_REG(USB0) 13595 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0) 13596 #define USB0_ERREN USB_ERREN_REG(USB0) 13597 #define USB0_STAT USB_STAT_REG(USB0) 13598 #define USB0_CTL USB_CTL_REG(USB0) 13599 #define USB0_ADDR USB_ADDR_REG(USB0) 13600 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0) 13601 #define USB0_FRMNUML USB_FRMNUML_REG(USB0) 13602 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0) 13603 #define USB0_TOKEN USB_TOKEN_REG(USB0) 13604 #define USB0_SOFTHLD USB_SOFTHLD_REG(USB0) 13605 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0) 13606 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0) 13607 #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0) 13608 #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1) 13609 #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2) 13610 #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3) 13611 #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4) 13612 #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5) 13613 #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6) 13614 #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7) 13615 #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8) 13616 #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9) 13617 #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10) 13618 #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11) 13619 #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12) 13620 #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13) 13621 #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14) 13622 #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15) 13623 #define USB0_USBCTRL USB_USBCTRL_REG(USB0) 13624 #define USB0_OBSERVE USB_OBSERVE_REG(USB0) 13625 #define USB0_CONTROL USB_CONTROL_REG(USB0) 13626 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0) 13627 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0) 13628 #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0) 13629 #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0) 13630 #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0) 13631 13632 /* USB - Register array accessors */ 13633 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index) 13634 13635 /*! 13636 * @} 13637 */ /* end of group USB_Register_Accessor_Macros */ 13638 13639 13640 /*! 13641 * @} 13642 */ /* end of group USB_Peripheral_Access_Layer */ 13643 13644 13645 /* ---------------------------------------------------------------------------- 13646 -- USBDCD Peripheral Access Layer 13647 ---------------------------------------------------------------------------- */ 13648 13649 /*! 13650 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer 13651 * @{ 13652 */ 13653 13654 /** USBDCD - Register Layout Typedef */ 13655 typedef struct { 13656 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */ 13657 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */ 13658 __I uint32_t STATUS; /**< Status register, offset: 0x8 */ 13659 uint8_t RESERVED_0[4]; 13660 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */ 13661 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */ 13662 union { /* offset: 0x18 */ 13663 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */ 13664 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */ 13665 }; 13666 } USBDCD_Type, *USBDCD_MemMapPtr; 13667 13668 /* ---------------------------------------------------------------------------- 13669 -- USBDCD - Register accessor macros 13670 ---------------------------------------------------------------------------- */ 13671 13672 /*! 13673 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros 13674 * @{ 13675 */ 13676 13677 13678 /* USBDCD - Register accessors */ 13679 #define USBDCD_CONTROL_REG(base) ((base)->CONTROL) 13680 #define USBDCD_CLOCK_REG(base) ((base)->CLOCK) 13681 #define USBDCD_STATUS_REG(base) ((base)->STATUS) 13682 #define USBDCD_TIMER0_REG(base) ((base)->TIMER0) 13683 #define USBDCD_TIMER1_REG(base) ((base)->TIMER1) 13684 #define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11) 13685 #define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12) 13686 13687 /*! 13688 * @} 13689 */ /* end of group USBDCD_Register_Accessor_Macros */ 13690 13691 13692 /* ---------------------------------------------------------------------------- 13693 -- USBDCD Register Masks 13694 ---------------------------------------------------------------------------- */ 13695 13696 /*! 13697 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks 13698 * @{ 13699 */ 13700 13701 /* CONTROL Bit Fields */ 13702 #define USBDCD_CONTROL_IACK_MASK 0x1u 13703 #define USBDCD_CONTROL_IACK_SHIFT 0 13704 #define USBDCD_CONTROL_IF_MASK 0x100u 13705 #define USBDCD_CONTROL_IF_SHIFT 8 13706 #define USBDCD_CONTROL_IE_MASK 0x10000u 13707 #define USBDCD_CONTROL_IE_SHIFT 16 13708 #define USBDCD_CONTROL_BC12_MASK 0x20000u 13709 #define USBDCD_CONTROL_BC12_SHIFT 17 13710 #define USBDCD_CONTROL_START_MASK 0x1000000u 13711 #define USBDCD_CONTROL_START_SHIFT 24 13712 #define USBDCD_CONTROL_SR_MASK 0x2000000u 13713 #define USBDCD_CONTROL_SR_SHIFT 25 13714 /* CLOCK Bit Fields */ 13715 #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u 13716 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0 13717 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu 13718 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2 13719 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK) 13720 /* STATUS Bit Fields */ 13721 #define USBDCD_STATUS_SEQ_RES_MASK 0x30000u 13722 #define USBDCD_STATUS_SEQ_RES_SHIFT 16 13723 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK) 13724 #define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u 13725 #define USBDCD_STATUS_SEQ_STAT_SHIFT 18 13726 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK) 13727 #define USBDCD_STATUS_ERR_MASK 0x100000u 13728 #define USBDCD_STATUS_ERR_SHIFT 20 13729 #define USBDCD_STATUS_TO_MASK 0x200000u 13730 #define USBDCD_STATUS_TO_SHIFT 21 13731 #define USBDCD_STATUS_ACTIVE_MASK 0x400000u 13732 #define USBDCD_STATUS_ACTIVE_SHIFT 22 13733 /* TIMER0 Bit Fields */ 13734 #define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu 13735 #define USBDCD_TIMER0_TUNITCON_SHIFT 0 13736 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK) 13737 #define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u 13738 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16 13739 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK) 13740 /* TIMER1 Bit Fields */ 13741 #define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu 13742 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0 13743 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK) 13744 #define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u 13745 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16 13746 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK) 13747 /* TIMER2_BC11 Bit Fields */ 13748 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK 0xFu 13749 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT 0 13750 #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK) 13751 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK 0x3FF0000u 13752 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT 16 13753 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK) 13754 /* TIMER2_BC12 Bit Fields */ 13755 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK 0x3FFu 13756 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT 0 13757 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK) 13758 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK 0x3FF0000u 13759 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16 13760 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) 13761 13762 /*! 13763 * @} 13764 */ /* end of group USBDCD_Register_Masks */ 13765 13766 13767 /* USBDCD - Peripheral instance base addresses */ 13768 /** Peripheral USBDCD base address */ 13769 #define USBDCD_BASE (0x40035000u) 13770 /** Peripheral USBDCD base pointer */ 13771 #define USBDCD ((USBDCD_Type *)USBDCD_BASE) 13772 #define USBDCD_BASE_PTR (USBDCD) 13773 /** Array initializer of USBDCD peripheral base addresses */ 13774 #define USBDCD_BASE_ADDRS { USBDCD_BASE } 13775 /** Array initializer of USBDCD peripheral base pointers */ 13776 #define USBDCD_BASE_PTRS { USBDCD } 13777 /** Interrupt vectors for the USBDCD peripheral type */ 13778 #define USBDCD_IRQS { USBDCD_IRQn } 13779 13780 /* ---------------------------------------------------------------------------- 13781 -- USBDCD - Register accessor macros 13782 ---------------------------------------------------------------------------- */ 13783 13784 /*! 13785 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros 13786 * @{ 13787 */ 13788 13789 13790 /* USBDCD - Register instance definitions */ 13791 /* USBDCD */ 13792 #define USBDCD_CONTROL USBDCD_CONTROL_REG(USBDCD) 13793 #define USBDCD_CLOCK USBDCD_CLOCK_REG(USBDCD) 13794 #define USBDCD_STATUS USBDCD_STATUS_REG(USBDCD) 13795 #define USBDCD_TIMER0 USBDCD_TIMER0_REG(USBDCD) 13796 #define USBDCD_TIMER1 USBDCD_TIMER1_REG(USBDCD) 13797 #define USBDCD_TIMER2_BC11 USBDCD_TIMER2_BC11_REG(USBDCD) 13798 #define USBDCD_TIMER2_BC12 USBDCD_TIMER2_BC12_REG(USBDCD) 13799 13800 /*! 13801 * @} 13802 */ /* end of group USBDCD_Register_Accessor_Macros */ 13803 13804 13805 /*! 13806 * @} 13807 */ /* end of group USBDCD_Peripheral_Access_Layer */ 13808 13809 13810 /* ---------------------------------------------------------------------------- 13811 -- VREF Peripheral Access Layer 13812 ---------------------------------------------------------------------------- */ 13813 13814 /*! 13815 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer 13816 * @{ 13817 */ 13818 13819 /** VREF - Register Layout Typedef */ 13820 typedef struct { 13821 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ 13822 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ 13823 } VREF_Type, *VREF_MemMapPtr; 13824 13825 /* ---------------------------------------------------------------------------- 13826 -- VREF - Register accessor macros 13827 ---------------------------------------------------------------------------- */ 13828 13829 /*! 13830 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros 13831 * @{ 13832 */ 13833 13834 13835 /* VREF - Register accessors */ 13836 #define VREF_TRM_REG(base) ((base)->TRM) 13837 #define VREF_SC_REG(base) ((base)->SC) 13838 13839 /*! 13840 * @} 13841 */ /* end of group VREF_Register_Accessor_Macros */ 13842 13843 13844 /* ---------------------------------------------------------------------------- 13845 -- VREF Register Masks 13846 ---------------------------------------------------------------------------- */ 13847 13848 /*! 13849 * @addtogroup VREF_Register_Masks VREF Register Masks 13850 * @{ 13851 */ 13852 13853 /* TRM Bit Fields */ 13854 #define VREF_TRM_TRIM_MASK 0x3Fu 13855 #define VREF_TRM_TRIM_SHIFT 0 13856 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK) 13857 #define VREF_TRM_CHOPEN_MASK 0x40u 13858 #define VREF_TRM_CHOPEN_SHIFT 6 13859 /* SC Bit Fields */ 13860 #define VREF_SC_MODE_LV_MASK 0x3u 13861 #define VREF_SC_MODE_LV_SHIFT 0 13862 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK) 13863 #define VREF_SC_VREFST_MASK 0x4u 13864 #define VREF_SC_VREFST_SHIFT 2 13865 #define VREF_SC_ICOMPEN_MASK 0x20u 13866 #define VREF_SC_ICOMPEN_SHIFT 5 13867 #define VREF_SC_REGEN_MASK 0x40u 13868 #define VREF_SC_REGEN_SHIFT 6 13869 #define VREF_SC_VREFEN_MASK 0x80u 13870 #define VREF_SC_VREFEN_SHIFT 7 13871 13872 /*! 13873 * @} 13874 */ /* end of group VREF_Register_Masks */ 13875 13876 13877 /* VREF - Peripheral instance base addresses */ 13878 /** Peripheral VREF base address */ 13879 #define VREF_BASE (0x40074000u) 13880 /** Peripheral VREF base pointer */ 13881 #define VREF ((VREF_Type *)VREF_BASE) 13882 #define VREF_BASE_PTR (VREF) 13883 /** Array initializer of VREF peripheral base addresses */ 13884 #define VREF_BASE_ADDRS { VREF_BASE } 13885 /** Array initializer of VREF peripheral base pointers */ 13886 #define VREF_BASE_PTRS { VREF } 13887 13888 /* ---------------------------------------------------------------------------- 13889 -- VREF - Register accessor macros 13890 ---------------------------------------------------------------------------- */ 13891 13892 /*! 13893 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros 13894 * @{ 13895 */ 13896 13897 13898 /* VREF - Register instance definitions */ 13899 /* VREF */ 13900 #define VREF_TRM VREF_TRM_REG(VREF) 13901 #define VREF_SC VREF_SC_REG(VREF) 13902 13903 /*! 13904 * @} 13905 */ /* end of group VREF_Register_Accessor_Macros */ 13906 13907 13908 /*! 13909 * @} 13910 */ /* end of group VREF_Peripheral_Access_Layer */ 13911 13912 13913 /* ---------------------------------------------------------------------------- 13914 -- WDOG Peripheral Access Layer 13915 ---------------------------------------------------------------------------- */ 13916 13917 /*! 13918 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer 13919 * @{ 13920 */ 13921 13922 /** WDOG - Register Layout Typedef */ 13923 typedef struct { 13924 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */ 13925 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */ 13926 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */ 13927 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */ 13928 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */ 13929 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */ 13930 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */ 13931 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */ 13932 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */ 13933 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */ 13934 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */ 13935 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */ 13936 } WDOG_Type, *WDOG_MemMapPtr; 13937 13938 /* ---------------------------------------------------------------------------- 13939 -- WDOG - Register accessor macros 13940 ---------------------------------------------------------------------------- */ 13941 13942 /*! 13943 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros 13944 * @{ 13945 */ 13946 13947 13948 /* WDOG - Register accessors */ 13949 #define WDOG_STCTRLH_REG(base) ((base)->STCTRLH) 13950 #define WDOG_STCTRLL_REG(base) ((base)->STCTRLL) 13951 #define WDOG_TOVALH_REG(base) ((base)->TOVALH) 13952 #define WDOG_TOVALL_REG(base) ((base)->TOVALL) 13953 #define WDOG_WINH_REG(base) ((base)->WINH) 13954 #define WDOG_WINL_REG(base) ((base)->WINL) 13955 #define WDOG_REFRESH_REG(base) ((base)->REFRESH) 13956 #define WDOG_UNLOCK_REG(base) ((base)->UNLOCK) 13957 #define WDOG_TMROUTH_REG(base) ((base)->TMROUTH) 13958 #define WDOG_TMROUTL_REG(base) ((base)->TMROUTL) 13959 #define WDOG_RSTCNT_REG(base) ((base)->RSTCNT) 13960 #define WDOG_PRESC_REG(base) ((base)->PRESC) 13961 13962 /*! 13963 * @} 13964 */ /* end of group WDOG_Register_Accessor_Macros */ 13965 13966 13967 /* ---------------------------------------------------------------------------- 13968 -- WDOG Register Masks 13969 ---------------------------------------------------------------------------- */ 13970 13971 /*! 13972 * @addtogroup WDOG_Register_Masks WDOG Register Masks 13973 * @{ 13974 */ 13975 13976 /* STCTRLH Bit Fields */ 13977 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u 13978 #define WDOG_STCTRLH_WDOGEN_SHIFT 0 13979 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u 13980 #define WDOG_STCTRLH_CLKSRC_SHIFT 1 13981 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u 13982 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2 13983 #define WDOG_STCTRLH_WINEN_MASK 0x8u 13984 #define WDOG_STCTRLH_WINEN_SHIFT 3 13985 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u 13986 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4 13987 #define WDOG_STCTRLH_DBGEN_MASK 0x20u 13988 #define WDOG_STCTRLH_DBGEN_SHIFT 5 13989 #define WDOG_STCTRLH_STOPEN_MASK 0x40u 13990 #define WDOG_STCTRLH_STOPEN_SHIFT 6 13991 #define WDOG_STCTRLH_WAITEN_MASK 0x80u 13992 #define WDOG_STCTRLH_WAITEN_SHIFT 7 13993 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u 13994 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10 13995 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u 13996 #define WDOG_STCTRLH_TESTSEL_SHIFT 11 13997 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u 13998 #define WDOG_STCTRLH_BYTESEL_SHIFT 12 13999 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK) 14000 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u 14001 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14 14002 /* STCTRLL Bit Fields */ 14003 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u 14004 #define WDOG_STCTRLL_INTFLG_SHIFT 15 14005 /* TOVALH Bit Fields */ 14006 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu 14007 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0 14008 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK) 14009 /* TOVALL Bit Fields */ 14010 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu 14011 #define WDOG_TOVALL_TOVALLOW_SHIFT 0 14012 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK) 14013 /* WINH Bit Fields */ 14014 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu 14015 #define WDOG_WINH_WINHIGH_SHIFT 0 14016 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK) 14017 /* WINL Bit Fields */ 14018 #define WDOG_WINL_WINLOW_MASK 0xFFFFu 14019 #define WDOG_WINL_WINLOW_SHIFT 0 14020 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK) 14021 /* REFRESH Bit Fields */ 14022 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu 14023 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0 14024 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK) 14025 /* UNLOCK Bit Fields */ 14026 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu 14027 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0 14028 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK) 14029 /* TMROUTH Bit Fields */ 14030 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu 14031 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0 14032 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK) 14033 /* TMROUTL Bit Fields */ 14034 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu 14035 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0 14036 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK) 14037 /* RSTCNT Bit Fields */ 14038 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu 14039 #define WDOG_RSTCNT_RSTCNT_SHIFT 0 14040 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK) 14041 /* PRESC Bit Fields */ 14042 #define WDOG_PRESC_PRESCVAL_MASK 0x700u 14043 #define WDOG_PRESC_PRESCVAL_SHIFT 8 14044 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK) 14045 14046 /*! 14047 * @} 14048 */ /* end of group WDOG_Register_Masks */ 14049 14050 14051 /* WDOG - Peripheral instance base addresses */ 14052 /** Peripheral WDOG base address */ 14053 #define WDOG_BASE (0x40052000u) 14054 /** Peripheral WDOG base pointer */ 14055 #define WDOG ((WDOG_Type *)WDOG_BASE) 14056 #define WDOG_BASE_PTR (WDOG) 14057 /** Array initializer of WDOG peripheral base addresses */ 14058 #define WDOG_BASE_ADDRS { WDOG_BASE } 14059 /** Array initializer of WDOG peripheral base pointers */ 14060 #define WDOG_BASE_PTRS { WDOG } 14061 /** Interrupt vectors for the WDOG peripheral type */ 14062 #define WDOG_IRQS { Watchdog_IRQn } 14063 14064 /* ---------------------------------------------------------------------------- 14065 -- WDOG - Register accessor macros 14066 ---------------------------------------------------------------------------- */ 14067 14068 /*! 14069 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros 14070 * @{ 14071 */ 14072 14073 14074 /* WDOG - Register instance definitions */ 14075 /* WDOG */ 14076 #define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG) 14077 #define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG) 14078 #define WDOG_TOVALH WDOG_TOVALH_REG(WDOG) 14079 #define WDOG_TOVALL WDOG_TOVALL_REG(WDOG) 14080 #define WDOG_WINH WDOG_WINH_REG(WDOG) 14081 #define WDOG_WINL WDOG_WINL_REG(WDOG) 14082 #define WDOG_REFRESH WDOG_REFRESH_REG(WDOG) 14083 #define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG) 14084 #define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG) 14085 #define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG) 14086 #define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG) 14087 #define WDOG_PRESC WDOG_PRESC_REG(WDOG) 14088 14089 /*! 14090 * @} 14091 */ /* end of group WDOG_Register_Accessor_Macros */ 14092 14093 14094 /*! 14095 * @} 14096 */ /* end of group WDOG_Peripheral_Access_Layer */ 14097 14098 14099 /* 14100 ** End of section using anonymous unions 14101 */ 14102 14103 #if defined(__ARMCC_VERSION) 14104 #pragma pop 14105 #elif defined(__CWCC__) 14106 #pragma pop 14107 #elif defined(__GNUC__) 14108 /* leave anonymous unions enabled */ 14109 #elif defined(__IAR_SYSTEMS_ICC__) 14110 #pragma language=default 14111 #else 14112 #error Not supported compiler type 14113 #endif 14114 14115 /*! 14116 * @} 14117 */ /* end of group Peripheral_access_layer */ 14118 14119 14120 /* ---------------------------------------------------------------------------- 14121 -- Backward Compatibility 14122 ---------------------------------------------------------------------------- */ 14123 14124 /*! 14125 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility 14126 * @{ 14127 */ 14128 14129 #define DMA_EARS_REG(base) This_symbol_has_been_deprecated 14130 #define DMA_EARS This_symbol_has_been_deprecated 14131 #define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated 14132 #define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated 14133 #define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated 14134 #define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated 14135 #define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated 14136 #define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated 14137 #define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated 14138 #define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated 14139 #define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated 14140 #define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated 14141 #define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated 14142 #define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated 14143 #define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated 14144 #define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated 14145 #define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated 14146 #define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated 14147 #define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated 14148 #define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated 14149 #define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated 14150 #define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated 14151 #define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated 14152 #define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated 14153 #define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated 14154 #define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated 14155 #define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated 14156 #define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated 14157 #define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated 14158 #define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated 14159 #define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated 14160 #define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated 14161 #define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated 14162 #define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated 14163 #define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated 14164 #define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated 14165 #define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated 14166 #define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated 14167 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base) 14168 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base) 14169 #define ENET_RMON_T_DROP This_symbol_has_been_deprecated 14170 #define ENET_IEEE_T_DROP This_symbol_has_been_deprecated 14171 #define ENET_IEEE_T_SQE This_symbol_has_been_deprecated 14172 #define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated 14173 #define MCG_C9_REG(base) This_symbol_has_been_deprecated 14174 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK 14175 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT 14176 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK 14177 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT 14178 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK 14179 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT 14180 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x) 14181 #define MCG_C9 This_symbol_has_been_deprecated 14182 #define MCM_PLACR_REG(base) This_symbol_has_been_deprecated 14183 #define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated 14184 #define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated 14185 #define MCM_PLACR This_symbol_has_been_deprecated 14186 #define ADC_BASES ADC_BASE_PTRS 14187 #define AIPS_BASES AIPS_BASE_PTRS 14188 #define AXBS_BASES AXBS_BASE_PTRS 14189 #define CAN_BASES CAN_BASE_PTRS 14190 #define CAU_BASES CAU_BASE_PTRS 14191 #define CMP_BASES CMP_BASE_PTRS 14192 #define CMT_BASES CMT_BASE_PTRS 14193 #define CRC_BASES CRC_BASE_PTRS 14194 #define DAC_BASES DAC_BASE_PTRS 14195 #define DMA_BASES DMA_BASE_PTRS 14196 #define DMAMUX_BASES DMAMUX_BASE_PTRS 14197 #define ENET_BASES ENET_BASE_PTRS 14198 #define EWM_BASES EWM_BASE_PTRS 14199 #define FB_BASES FB_BASE_PTRS 14200 #define FMC_BASES FMC_BASE_PTRS 14201 #define FTFE_BASES FTFE_BASE_PTRS 14202 #define FTM_BASES FTM_BASE_PTRS 14203 #define GPIO_BASES GPIO_BASE_PTRS 14204 #define I2C_BASES I2C_BASE_PTRS 14205 #define I2S_BASES I2S_BASE_PTRS 14206 #define LLWU_BASES LLWU_BASE_PTRS 14207 #define LPTMR_BASES LPTMR_BASE_PTRS 14208 #define MCG_BASES MCG_BASE_PTRS 14209 #define MCM_ISR_REG(base) MCM_ISCR_REG(base) 14210 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK 14211 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT 14212 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK 14213 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT 14214 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK 14215 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT 14216 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK 14217 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT 14218 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK 14219 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT 14220 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK 14221 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT 14222 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK 14223 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT 14224 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK 14225 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT 14226 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK 14227 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT 14228 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK 14229 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT 14230 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK 14231 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT 14232 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK 14233 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT 14234 #define MCM_BASES MCM_BASE_PTRS 14235 #define MPU_BASES MPU_BASE_PTRS 14236 #define NV_BASES NV_BASE_PTRS 14237 #define OSC_BASES OSC_BASE_PTRS 14238 #define PDB_BASES PDB_BASE_PTRS 14239 #define PIT_BASES PIT_BASE_PTRS 14240 #define PMC_BASES PMC_BASE_PTRS 14241 #define PORT_BASES PORT_BASE_PTRS 14242 #define RCM_BASES RCM_BASE_PTRS 14243 #define RFSYS_BASES RFSYS_BASE_PTRS 14244 #define RFVBAT_BASES RFVBAT_BASE_PTRS 14245 #define RNG_BASES RNG_BASE_PTRS 14246 #define RTC_BASES RTC_BASE_PTRS 14247 #define SDHC_BASES SDHC_BASE_PTRS 14248 #define SIM_BASES SIM_BASE_PTRS 14249 #define SMC_BASES SMC_BASE_PTRS 14250 #define SPI_BASES SPI_BASE_PTRS 14251 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base) 14252 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base) 14253 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK 14254 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT 14255 #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x) 14256 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK 14257 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT 14258 #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x) 14259 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK 14260 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT 14261 #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x) 14262 #define UART_BASES UART_BASE_PTRS 14263 #define USB_BASES USB_BASE_PTRS 14264 #define USBDCD_BASES USBDCD_BASE_PTRS 14265 #define VREF_BASES VREF_BASE_PTRS 14266 #define WDOG_BASES WDOG_BASE_PTRS 14267 #define DMA_EARS_REG(base) This_symbol_has_been_deprecated 14268 #define DMA_EARS This_symbol_has_been_deprecated 14269 #define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated 14270 #define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated 14271 #define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated 14272 #define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated 14273 #define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated 14274 #define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated 14275 #define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated 14276 #define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated 14277 #define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated 14278 #define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated 14279 #define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated 14280 #define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated 14281 #define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated 14282 #define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated 14283 #define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated 14284 #define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated 14285 #define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated 14286 #define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated 14287 #define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated 14288 #define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated 14289 #define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated 14290 #define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated 14291 #define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated 14292 #define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated 14293 #define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated 14294 #define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated 14295 #define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated 14296 #define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated 14297 #define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated 14298 #define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated 14299 #define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated 14300 #define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated 14301 #define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated 14302 #define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated 14303 #define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated 14304 #define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated 14305 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base) 14306 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base) 14307 #define ENET_RMON_T_DROP This_symbol_has_been_deprecated 14308 #define ENET_IEEE_T_DROP This_symbol_has_been_deprecated 14309 #define ENET_IEEE_T_SQE This_symbol_has_been_deprecated 14310 #define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated 14311 #define MCG_C9_REG(base) This_symbol_has_been_deprecated 14312 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK 14313 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT 14314 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK 14315 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT 14316 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK 14317 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT 14318 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x) 14319 #define MCG_C9 This_symbol_has_been_deprecated 14320 #define MCM_PLACR_REG(base) This_symbol_has_been_deprecated 14321 #define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated 14322 #define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated 14323 #define MCM_PLACR This_symbol_has_been_deprecated 14324 #define ADC_BASES ADC_BASE_PTRS 14325 #define AIPS_BASES AIPS_BASE_PTRS 14326 #define AXBS_BASES AXBS_BASE_PTRS 14327 #define CAN_BASES CAN_BASE_PTRS 14328 #define CAU_BASES CAU_BASE_PTRS 14329 #define CMP_BASES CMP_BASE_PTRS 14330 #define CMT_BASES CMT_BASE_PTRS 14331 #define CRC_BASES CRC_BASE_PTRS 14332 #define DAC_BASES DAC_BASE_PTRS 14333 #define DMA_BASES DMA_BASE_PTRS 14334 #define DMAMUX_BASES DMAMUX_BASE_PTRS 14335 #define ENET_BASES ENET_BASE_PTRS 14336 #define EWM_BASES EWM_BASE_PTRS 14337 #define FB_BASES FB_BASE_PTRS 14338 #define FMC_BASES FMC_BASE_PTRS 14339 #define FTFE_BASES FTFE_BASE_PTRS 14340 #define FTM_BASES FTM_BASE_PTRS 14341 #define GPIO_BASES GPIO_BASE_PTRS 14342 #define I2C_BASES I2C_BASE_PTRS 14343 #define I2S_BASES I2S_BASE_PTRS 14344 #define LLWU_BASES LLWU_BASE_PTRS 14345 #define LPTMR_BASES LPTMR_BASE_PTRS 14346 #define MCG_BASES MCG_BASE_PTRS 14347 #define MCM_ISR_REG(base) MCM_ISCR_REG(base) 14348 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK 14349 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT 14350 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK 14351 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT 14352 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK 14353 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT 14354 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK 14355 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT 14356 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK 14357 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT 14358 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK 14359 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT 14360 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK 14361 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT 14362 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK 14363 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT 14364 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK 14365 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT 14366 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK 14367 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT 14368 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK 14369 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT 14370 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK 14371 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT 14372 #define MCM_BASES MCM_BASE_PTRS 14373 #define MPU_BASES MPU_BASE_PTRS 14374 #define NV_BASES NV_BASE_PTRS 14375 #define OSC_BASES OSC_BASE_PTRS 14376 #define PDB_BASES PDB_BASE_PTRS 14377 #define PIT_BASES PIT_BASE_PTRS 14378 #define PMC_BASES PMC_BASE_PTRS 14379 #define PORT_BASES PORT_BASE_PTRS 14380 #define RCM_BASES RCM_BASE_PTRS 14381 #define RFSYS_BASES RFSYS_BASE_PTRS 14382 #define RFVBAT_BASES RFVBAT_BASE_PTRS 14383 #define RNG_BASES RNG_BASE_PTRS 14384 #define RTC_BASES RTC_BASE_PTRS 14385 #define SDHC_BASES SDHC_BASE_PTRS 14386 #define SIM_BASES SIM_BASE_PTRS 14387 #define SMC_BASES SMC_BASE_PTRS 14388 #define SPI_BASES SPI_BASE_PTRS 14389 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base) 14390 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base) 14391 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK 14392 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT 14393 #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x) 14394 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK 14395 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT 14396 #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x) 14397 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK 14398 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT 14399 #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x) 14400 #define UART_BASES UART_BASE_PTRS 14401 #define USB_BASES USB_BASE_PTRS 14402 #define USBDCD_BASES USBDCD_BASE_PTRS 14403 #define VREF_BASES VREF_BASE_PTRS 14404 #define WDOG_BASES WDOG_BASE_PTRS 14405 14406 /*! 14407 * @} 14408 */ /* end of group Backward_Compatibility_Symbols */ 14409 14410 14411 #else /* #if !defined(MK64F12_H_) */ 14412 /* There is already included the same memory map. Check if it is compatible (has the same major version) */ 14413 #if (MCU_MEM_MAP_VERSION != 0x0200u) 14414 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) 14415 #warning There are included two not compatible versions of memory maps. Please check possible differences. 14416 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */ 14417 #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */ 14418 #endif /* #if !defined(MK64F12_H_) */ 14419 14420 /* MK64F12.h, eof. */
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