Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Fork of
target-mcu-k64f
by 
Morpheus
ENET_Type Struct Reference
[ENET Peripheral Access Layer]
ENET - Register Layout Typedef. More...
#include <MK64F12.h>
Data Fields | |
| __IO uint32_t | EIR |
| Interrupt Event Register, offset: 0x4. | |
| __IO uint32_t | EIMR |
| Interrupt Mask Register, offset: 0x8. | |
| __IO uint32_t | RDAR |
| Receive Descriptor Active Register, offset: 0x10. | |
| __IO uint32_t | TDAR |
| Transmit Descriptor Active Register, offset: 0x14. | |
| __IO uint32_t | ECR |
| Ethernet Control Register, offset: 0x24. | |
| __IO uint32_t | MMFR |
| MII Management Frame Register, offset: 0x40. | |
| __IO uint32_t | MSCR |
| MII Speed Control Register, offset: 0x44. | |
| __IO uint32_t | MIBC |
| MIB Control Register, offset: 0x64. | |
| __IO uint32_t | RCR |
| Receive Control Register, offset: 0x84. | |
| __IO uint32_t | TCR |
| Transmit Control Register, offset: 0xC4. | |
| __IO uint32_t | PALR |
| Physical Address Lower Register, offset: 0xE4. | |
| __IO uint32_t | PAUR |
| Physical Address Upper Register, offset: 0xE8. | |
| __IO uint32_t | OPD |
| Opcode/Pause Duration Register, offset: 0xEC. | |
| __IO uint32_t | IAUR |
| Descriptor Individual Upper Address Register, offset: 0x118. | |
| __IO uint32_t | IALR |
| Descriptor Individual Lower Address Register, offset: 0x11C. | |
| __IO uint32_t | GAUR |
| Descriptor Group Upper Address Register, offset: 0x120. | |
| __IO uint32_t | GALR |
| Descriptor Group Lower Address Register, offset: 0x124. | |
| __IO uint32_t | TFWR |
| Transmit FIFO Watermark Register, offset: 0x144. | |
| __IO uint32_t | RDSR |
| Receive Descriptor Ring Start Register, offset: 0x180. | |
| __IO uint32_t | TDSR |
| Transmit Buffer Descriptor Ring Start Register, offset: 0x184. | |
| __IO uint32_t | MRBR |
| Maximum Receive Buffer Size Register, offset: 0x188. | |
| __IO uint32_t | RSFL |
| Receive FIFO Section Full Threshold, offset: 0x190. | |
| __IO uint32_t | RSEM |
| Receive FIFO Section Empty Threshold, offset: 0x194. | |
| __IO uint32_t | RAEM |
| Receive FIFO Almost Empty Threshold, offset: 0x198. | |
| __IO uint32_t | RAFL |
| Receive FIFO Almost Full Threshold, offset: 0x19C. | |
| __IO uint32_t | TSEM |
| Transmit FIFO Section Empty Threshold, offset: 0x1A0. | |
| __IO uint32_t | TAEM |
| Transmit FIFO Almost Empty Threshold, offset: 0x1A4. | |
| __IO uint32_t | TAFL |
| Transmit FIFO Almost Full Threshold, offset: 0x1A8. | |
| __IO uint32_t | TIPG |
| Transmit Inter-Packet Gap, offset: 0x1AC. | |
| __IO uint32_t | FTRL |
| Frame Truncation Length, offset: 0x1B0. | |
| __IO uint32_t | TACC |
| Transmit Accelerator Function Configuration, offset: 0x1C0. | |
| __IO uint32_t | RACC |
| Receive Accelerator Function Configuration, offset: 0x1C4. | |
| __I uint32_t | RMON_T_PACKETS |
| Tx Packet Count Statistic Register, offset: 0x204. | |
| __I uint32_t | RMON_T_BC_PKT |
| Tx Broadcast Packets Statistic Register, offset: 0x208. | |
| __I uint32_t | RMON_T_MC_PKT |
| Tx Multicast Packets Statistic Register, offset: 0x20C. | |
| __I uint32_t | RMON_T_CRC_ALIGN |
| Tx Packets with CRC/Align Error Statistic Register, offset: 0x210. | |
| __I uint32_t | RMON_T_UNDERSIZE |
| Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214. | |
| __I uint32_t | RMON_T_OVERSIZE |
| Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218. | |
| __I uint32_t | RMON_T_FRAG |
| Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C. | |
| __I uint32_t | RMON_T_JAB |
| Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220. | |
| __I uint32_t | RMON_T_COL |
| Tx Collision Count Statistic Register, offset: 0x224. | |
| __I uint32_t | RMON_T_P64 |
| Tx 64-Byte Packets Statistic Register, offset: 0x228. | |
| __I uint32_t | RMON_T_P65TO127 |
| Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C. | |
| __I uint32_t | RMON_T_P128TO255 |
| Tx 128- to 255-byte Packets Statistic Register, offset: 0x230. | |
| __I uint32_t | RMON_T_P256TO511 |
| Tx 256- to 511-byte Packets Statistic Register, offset: 0x234. | |
| __I uint32_t | RMON_T_P512TO1023 |
| Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238. | |
| __I uint32_t | RMON_T_P1024TO2047 |
| Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C. | |
| __I uint32_t | RMON_T_P_GTE2048 |
| Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240. | |
| __I uint32_t | RMON_T_OCTETS |
| Tx Octets Statistic Register, offset: 0x244. | |
| __I uint32_t | IEEE_T_FRAME_OK |
| Frames Transmitted OK Statistic Register, offset: 0x24C. | |
| __I uint32_t | IEEE_T_1COL |
| Frames Transmitted with Single Collision Statistic Register, offset: 0x250. | |
| __I uint32_t | IEEE_T_MCOL |
| Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254. | |
| __I uint32_t | IEEE_T_DEF |
| Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258. | |
| __I uint32_t | IEEE_T_LCOL |
| Frames Transmitted with Late Collision Statistic Register, offset: 0x25C. | |
| __I uint32_t | IEEE_T_EXCOL |
| Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260. | |
| __I uint32_t | IEEE_T_MACERR |
| Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264. | |
| __I uint32_t | IEEE_T_CSERR |
| Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268. | |
| __I uint32_t | IEEE_T_FDXFC |
| Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270. | |
| __I uint32_t | IEEE_T_OCTETS_OK |
| Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274. | |
| __I uint32_t | RMON_R_PACKETS |
| Rx Packet Count Statistic Register, offset: 0x284. | |
| __I uint32_t | RMON_R_BC_PKT |
| Rx Broadcast Packets Statistic Register, offset: 0x288. | |
| __I uint32_t | RMON_R_MC_PKT |
| Rx Multicast Packets Statistic Register, offset: 0x28C. | |
| __I uint32_t | RMON_R_CRC_ALIGN |
| Rx Packets with CRC/Align Error Statistic Register, offset: 0x290. | |
| __I uint32_t | RMON_R_UNDERSIZE |
| Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294. | |
| __I uint32_t | RMON_R_OVERSIZE |
| Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298. | |
| __I uint32_t | RMON_R_FRAG |
| Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C. | |
| __I uint32_t | RMON_R_JAB |
| Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0. | |
| __I uint32_t | RMON_R_P64 |
| Rx 64-Byte Packets Statistic Register, offset: 0x2A8. | |
| __I uint32_t | RMON_R_P65TO127 |
| Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC. | |
| __I uint32_t | RMON_R_P128TO255 |
| Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0. | |
| __I uint32_t | RMON_R_P256TO511 |
| Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4. | |
| __I uint32_t | RMON_R_P512TO1023 |
| Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8. | |
| __I uint32_t | RMON_R_P1024TO2047 |
| Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC. | |
| __I uint32_t | RMON_R_P_GTE2048 |
| Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0. | |
| __I uint32_t | RMON_R_OCTETS |
| Rx Octets Statistic Register, offset: 0x2C4. | |
| __I uint32_t | IEEE_R_DROP |
| Frames not Counted Correctly Statistic Register, offset: 0x2C8. | |
| __I uint32_t | IEEE_R_FRAME_OK |
| Frames Received OK Statistic Register, offset: 0x2CC. | |
| __I uint32_t | IEEE_R_CRC |
| Frames Received with CRC Error Statistic Register, offset: 0x2D0. | |
| __I uint32_t | IEEE_R_ALIGN |
| Frames Received with Alignment Error Statistic Register, offset: 0x2D4. | |
| __I uint32_t | IEEE_R_MACERR |
| Receive FIFO Overflow Count Statistic Register, offset: 0x2D8. | |
| __I uint32_t | IEEE_R_FDXFC |
| Flow Control Pause Frames Received Statistic Register, offset: 0x2DC. | |
| __I uint32_t | IEEE_R_OCTETS_OK |
| Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0. | |
| __IO uint32_t | ATCR |
| Adjustable Timer Control Register, offset: 0x400. | |
| __IO uint32_t | ATVR |
| Timer Value Register, offset: 0x404. | |
| __IO uint32_t | ATOFF |
| Timer Offset Register, offset: 0x408. | |
| __IO uint32_t | ATPER |
| Timer Period Register, offset: 0x40C. | |
| __IO uint32_t | ATCOR |
| Timer Correction Register, offset: 0x410. | |
| __IO uint32_t | ATINC |
| Time-Stamping Clock Period Register, offset: 0x414. | |
| __I uint32_t | ATSTMP |
| Timestamp of Last Transmitted Frame, offset: 0x418. | |
| __IO uint32_t | TGSR |
| Timer Global Status Register, offset: 0x604. | |
| __IO uint32_t | TCSR |
| Timer Control Status Register, array offset: 0x608, array step: 0x8. | |
| __IO uint32_t | TCCR |
| Timer Compare Capture Register, array offset: 0x60C, array step: 0x8. | |
Detailed Description
ENET - Register Layout Typedef.
Definition at line 4879 of file cmsis/MK64F12.h.
Field Documentation
| __IO uint32_t ATCOR |
Timer Correction Register, offset: 0x410.
Definition at line 4985 of file cmsis/MK64F12.h.
| __IO uint32_t ATCR |
Adjustable Timer Control Register, offset: 0x400.
Definition at line 4981 of file cmsis/MK64F12.h.
| __IO uint32_t ATINC |
Time-Stamping Clock Period Register, offset: 0x414.
Definition at line 4986 of file cmsis/MK64F12.h.
| __IO uint32_t ATOFF |
Timer Offset Register, offset: 0x408.
Definition at line 4983 of file cmsis/MK64F12.h.
| __IO uint32_t ATPER |
Timer Period Register, offset: 0x40C.
Definition at line 4984 of file cmsis/MK64F12.h.
| __I uint32_t ATSTMP |
Timestamp of Last Transmitted Frame, offset: 0x418.
Definition at line 4987 of file cmsis/MK64F12.h.
| __IO uint32_t ATVR |
Timer Value Register, offset: 0x404.
Definition at line 4982 of file cmsis/MK64F12.h.
| __IO uint32_t ECR |
Ethernet Control Register, offset: 0x24.
Definition at line 4887 of file cmsis/MK64F12.h.
| __IO uint32_t EIMR |
Interrupt Mask Register, offset: 0x8.
Definition at line 4882 of file cmsis/MK64F12.h.
| __IO uint32_t EIR |
Interrupt Event Register, offset: 0x4.
Definition at line 4881 of file cmsis/MK64F12.h.
| __IO uint32_t FTRL |
Frame Truncation Length, offset: 0x1B0.
Definition at line 4921 of file cmsis/MK64F12.h.
| __IO uint32_t GALR |
Descriptor Group Lower Address Register, offset: 0x124.
Definition at line 4905 of file cmsis/MK64F12.h.
| __IO uint32_t GAUR |
Descriptor Group Upper Address Register, offset: 0x120.
Definition at line 4904 of file cmsis/MK64F12.h.
| __IO uint32_t IALR |
Descriptor Individual Lower Address Register, offset: 0x11C.
Definition at line 4903 of file cmsis/MK64F12.h.
| __IO uint32_t IAUR |
Descriptor Individual Upper Address Register, offset: 0x118.
Definition at line 4902 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_R_ALIGN |
Frames Received with Alignment Error Statistic Register, offset: 0x2D4.
Definition at line 4976 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_R_CRC |
Frames Received with CRC Error Statistic Register, offset: 0x2D0.
Definition at line 4975 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_R_DROP |
Frames not Counted Correctly Statistic Register, offset: 0x2C8.
Definition at line 4973 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_R_FDXFC |
Flow Control Pause Frames Received Statistic Register, offset: 0x2DC.
Definition at line 4978 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_R_FRAME_OK |
Frames Received OK Statistic Register, offset: 0x2CC.
Definition at line 4974 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_R_MACERR |
Receive FIFO Overflow Count Statistic Register, offset: 0x2D8.
Definition at line 4977 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_R_OCTETS_OK |
Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0.
Definition at line 4979 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_T_1COL |
Frames Transmitted with Single Collision Statistic Register, offset: 0x250.
Definition at line 4945 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_T_CSERR |
Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268.
Definition at line 4951 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_T_DEF |
Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258.
Definition at line 4947 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_T_EXCOL |
Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260.
Definition at line 4949 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_T_FDXFC |
Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270.
Definition at line 4953 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_T_FRAME_OK |
Frames Transmitted OK Statistic Register, offset: 0x24C.
Definition at line 4944 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_T_LCOL |
Frames Transmitted with Late Collision Statistic Register, offset: 0x25C.
Definition at line 4948 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_T_MACERR |
Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264.
Definition at line 4950 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_T_MCOL |
Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254.
Definition at line 4946 of file cmsis/MK64F12.h.
| __I uint32_t IEEE_T_OCTETS_OK |
Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274.
Definition at line 4954 of file cmsis/MK64F12.h.
| __IO uint32_t MIBC |
MIB Control Register, offset: 0x64.
Definition at line 4892 of file cmsis/MK64F12.h.
| __IO uint32_t MMFR |
MII Management Frame Register, offset: 0x40.
Definition at line 4889 of file cmsis/MK64F12.h.
| __IO uint32_t MRBR |
Maximum Receive Buffer Size Register, offset: 0x188.
Definition at line 4911 of file cmsis/MK64F12.h.
| __IO uint32_t MSCR |
MII Speed Control Register, offset: 0x44.
Definition at line 4890 of file cmsis/MK64F12.h.
| __IO uint32_t OPD |
Opcode/Pause Duration Register, offset: 0xEC.
Definition at line 4900 of file cmsis/MK64F12.h.
| __IO uint32_t PALR |
Physical Address Lower Register, offset: 0xE4.
Definition at line 4898 of file cmsis/MK64F12.h.
| __IO uint32_t PAUR |
Physical Address Upper Register, offset: 0xE8.
Definition at line 4899 of file cmsis/MK64F12.h.
| __IO uint32_t RACC |
Receive Accelerator Function Configuration, offset: 0x1C4.
Definition at line 4924 of file cmsis/MK64F12.h.
| __IO uint32_t RAEM |
Receive FIFO Almost Empty Threshold, offset: 0x198.
Definition at line 4915 of file cmsis/MK64F12.h.
| __IO uint32_t RAFL |
Receive FIFO Almost Full Threshold, offset: 0x19C.
Definition at line 4916 of file cmsis/MK64F12.h.
| __IO uint32_t RCR |
Receive Control Register, offset: 0x84.
Definition at line 4894 of file cmsis/MK64F12.h.
| __IO uint32_t RDAR |
Receive Descriptor Active Register, offset: 0x10.
Definition at line 4884 of file cmsis/MK64F12.h.
| __IO uint32_t RDSR |
Receive Descriptor Ring Start Register, offset: 0x180.
Definition at line 4909 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_BC_PKT |
Rx Broadcast Packets Statistic Register, offset: 0x288.
Definition at line 4957 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_CRC_ALIGN |
Rx Packets with CRC/Align Error Statistic Register, offset: 0x290.
Definition at line 4959 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_FRAG |
Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C.
Definition at line 4962 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_JAB |
Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0.
Definition at line 4963 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_MC_PKT |
Rx Multicast Packets Statistic Register, offset: 0x28C.
Definition at line 4958 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_OCTETS |
Rx Octets Statistic Register, offset: 0x2C4.
Definition at line 4972 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_OVERSIZE |
Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298.
Definition at line 4961 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_P1024TO2047 |
Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC.
Definition at line 4970 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_P128TO255 |
Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0.
Definition at line 4967 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_P256TO511 |
Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4.
Definition at line 4968 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_P512TO1023 |
Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8.
Definition at line 4969 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_P64 |
Rx 64-Byte Packets Statistic Register, offset: 0x2A8.
Definition at line 4965 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_P65TO127 |
Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC.
Definition at line 4966 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_P_GTE2048 |
Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0.
Definition at line 4971 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_PACKETS |
Rx Packet Count Statistic Register, offset: 0x284.
Definition at line 4956 of file cmsis/MK64F12.h.
| __I uint32_t RMON_R_UNDERSIZE |
Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294.
Definition at line 4960 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_BC_PKT |
Tx Broadcast Packets Statistic Register, offset: 0x208.
Definition at line 4927 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_COL |
Tx Collision Count Statistic Register, offset: 0x224.
Definition at line 4934 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_CRC_ALIGN |
Tx Packets with CRC/Align Error Statistic Register, offset: 0x210.
Definition at line 4929 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_FRAG |
Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C.
Definition at line 4932 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_JAB |
Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220.
Definition at line 4933 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_MC_PKT |
Tx Multicast Packets Statistic Register, offset: 0x20C.
Definition at line 4928 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_OCTETS |
Tx Octets Statistic Register, offset: 0x244.
Definition at line 4942 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_OVERSIZE |
Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218.
Definition at line 4931 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_P1024TO2047 |
Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C.
Definition at line 4940 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_P128TO255 |
Tx 128- to 255-byte Packets Statistic Register, offset: 0x230.
Definition at line 4937 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_P256TO511 |
Tx 256- to 511-byte Packets Statistic Register, offset: 0x234.
Definition at line 4938 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_P512TO1023 |
Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238.
Definition at line 4939 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_P64 |
Tx 64-Byte Packets Statistic Register, offset: 0x228.
Definition at line 4935 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_P65TO127 |
Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C.
Definition at line 4936 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_P_GTE2048 |
Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240.
Definition at line 4941 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_PACKETS |
Tx Packet Count Statistic Register, offset: 0x204.
Definition at line 4926 of file cmsis/MK64F12.h.
| __I uint32_t RMON_T_UNDERSIZE |
Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214.
Definition at line 4930 of file cmsis/MK64F12.h.
| __IO uint32_t RSEM |
Receive FIFO Section Empty Threshold, offset: 0x194.
Definition at line 4914 of file cmsis/MK64F12.h.
| __IO uint32_t RSFL |
Receive FIFO Section Full Threshold, offset: 0x190.
Definition at line 4913 of file cmsis/MK64F12.h.
| __IO uint32_t TACC |
Transmit Accelerator Function Configuration, offset: 0x1C0.
Definition at line 4923 of file cmsis/MK64F12.h.
| __IO uint32_t TAEM |
Transmit FIFO Almost Empty Threshold, offset: 0x1A4.
Definition at line 4918 of file cmsis/MK64F12.h.
| __IO uint32_t TAFL |
Transmit FIFO Almost Full Threshold, offset: 0x1A8.
Definition at line 4919 of file cmsis/MK64F12.h.
| __IO uint32_t TCCR |
Timer Compare Capture Register, array offset: 0x60C, array step: 0x8.
Definition at line 4992 of file cmsis/MK64F12.h.
| __IO uint32_t TCR |
Transmit Control Register, offset: 0xC4.
Definition at line 4896 of file cmsis/MK64F12.h.
| __IO uint32_t TCSR |
Timer Control Status Register, array offset: 0x608, array step: 0x8.
Definition at line 4991 of file cmsis/MK64F12.h.
| __IO uint32_t TDAR |
Transmit Descriptor Active Register, offset: 0x14.
Definition at line 4885 of file cmsis/MK64F12.h.
| __IO uint32_t TDSR |
Transmit Buffer Descriptor Ring Start Register, offset: 0x184.
Definition at line 4910 of file cmsis/MK64F12.h.
| __IO uint32_t TFWR |
Transmit FIFO Watermark Register, offset: 0x144.
Definition at line 4907 of file cmsis/MK64F12.h.
| __IO uint32_t TGSR |
Timer Global Status Register, offset: 0x604.
Definition at line 4989 of file cmsis/MK64F12.h.
| __IO uint32_t TIPG |
Transmit Inter-Packet Gap, offset: 0x1AC.
Definition at line 4920 of file cmsis/MK64F12.h.
| __IO uint32_t TSEM |
Transmit FIFO Section Empty Threshold, offset: 0x1A0.
Definition at line 4917 of file cmsis/MK64F12.h.
Generated on Sat Aug 27 2022 17:09:03 by
1.7.2