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target-mcu-k64f
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Morpheus
I2S_Type Struct Reference
[I2S Peripheral Access Layer]
I2S - Register Layout Typedef. More...
#include <MK64F12.h>
Data Fields | |
| __IO uint32_t | TCSR |
| SAI Transmit Control Register, offset: 0x0. | |
| __IO uint32_t | TCR1 |
| SAI Transmit Configuration 1 Register, offset: 0x4. | |
| __IO uint32_t | TCR2 |
| SAI Transmit Configuration 2 Register, offset: 0x8. | |
| __IO uint32_t | TCR3 |
| SAI Transmit Configuration 3 Register, offset: 0xC. | |
| __IO uint32_t | TCR4 |
| SAI Transmit Configuration 4 Register, offset: 0x10. | |
| __IO uint32_t | TCR5 |
| SAI Transmit Configuration 5 Register, offset: 0x14. | |
| __O uint32_t | TDR [2] |
| SAI Transmit Data Register, array offset: 0x20, array step: 0x4. | |
| __I uint32_t | TFR [2] |
| SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4. | |
| __IO uint32_t | TMR |
| SAI Transmit Mask Register, offset: 0x60. | |
| __IO uint32_t | RCSR |
| SAI Receive Control Register, offset: 0x80. | |
| __IO uint32_t | RCR1 |
| SAI Receive Configuration 1 Register, offset: 0x84. | |
| __IO uint32_t | RCR2 |
| SAI Receive Configuration 2 Register, offset: 0x88. | |
| __IO uint32_t | RCR3 |
| SAI Receive Configuration 3 Register, offset: 0x8C. | |
| __IO uint32_t | RCR4 |
| SAI Receive Configuration 4 Register, offset: 0x90. | |
| __IO uint32_t | RCR5 |
| SAI Receive Configuration 5 Register, offset: 0x94. | |
| __I uint32_t | RDR [2] |
| SAI Receive Data Register, array offset: 0xA0, array step: 0x4. | |
| __I uint32_t | RFR [2] |
| SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4. | |
| __IO uint32_t | RMR |
| SAI Receive Mask Register, offset: 0xE0. | |
| __IO uint32_t | MCR |
| SAI MCLK Control Register, offset: 0x100. | |
| __IO uint32_t | MDR |
| SAI MCLK Divide Register, offset: 0x104. | |
Detailed Description
I2S - Register Layout Typedef.
Definition at line 7778 of file cmsis/MK64F12.h.
Field Documentation
| __IO uint32_t MCR |
SAI MCLK Control Register, offset: 0x100.
Definition at line 7805 of file cmsis/MK64F12.h.
| __IO uint32_t MDR |
SAI MCLK Divide Register, offset: 0x104.
Definition at line 7806 of file cmsis/MK64F12.h.
| __IO uint32_t RCR1 |
SAI Receive Configuration 1 Register, offset: 0x84.
Definition at line 7793 of file cmsis/MK64F12.h.
| __IO uint32_t RCR2 |
SAI Receive Configuration 2 Register, offset: 0x88.
Definition at line 7794 of file cmsis/MK64F12.h.
| __IO uint32_t RCR3 |
SAI Receive Configuration 3 Register, offset: 0x8C.
Definition at line 7795 of file cmsis/MK64F12.h.
| __IO uint32_t RCR4 |
SAI Receive Configuration 4 Register, offset: 0x90.
Definition at line 7796 of file cmsis/MK64F12.h.
| __IO uint32_t RCR5 |
SAI Receive Configuration 5 Register, offset: 0x94.
Definition at line 7797 of file cmsis/MK64F12.h.
| __IO uint32_t RCSR |
SAI Receive Control Register, offset: 0x80.
Definition at line 7792 of file cmsis/MK64F12.h.
| __I uint32_t RDR |
SAI Receive Data Register, array offset: 0xA0, array step: 0x4.
Definition at line 7799 of file cmsis/MK64F12.h.
| __I uint32_t RFR |
SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4.
Definition at line 7801 of file cmsis/MK64F12.h.
| __IO uint32_t RMR |
SAI Receive Mask Register, offset: 0xE0.
Definition at line 7803 of file cmsis/MK64F12.h.
| __IO uint32_t TCR1 |
SAI Transmit Configuration 1 Register, offset: 0x4.
Definition at line 7780 of file cmsis/MK64F12.h.
| __IO uint32_t TCR2 |
SAI Transmit Configuration 2 Register, offset: 0x8.
Definition at line 7781 of file cmsis/MK64F12.h.
| __IO uint32_t TCR3 |
SAI Transmit Configuration 3 Register, offset: 0xC.
Definition at line 7782 of file cmsis/MK64F12.h.
| __IO uint32_t TCR4 |
SAI Transmit Configuration 4 Register, offset: 0x10.
Definition at line 7783 of file cmsis/MK64F12.h.
| __IO uint32_t TCR5 |
SAI Transmit Configuration 5 Register, offset: 0x14.
Definition at line 7784 of file cmsis/MK64F12.h.
| __IO uint32_t TCSR |
SAI Transmit Control Register, offset: 0x0.
Definition at line 7779 of file cmsis/MK64F12.h.
| __O uint32_t TDR |
SAI Transmit Data Register, array offset: 0x20, array step: 0x4.
Definition at line 7786 of file cmsis/MK64F12.h.
| __I uint32_t TFR |
SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4.
Definition at line 7788 of file cmsis/MK64F12.h.
| __IO uint32_t TMR |
SAI Transmit Mask Register, offset: 0x60.
Definition at line 7790 of file cmsis/MK64F12.h.
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