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target-mcu-k64f
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Morpheus
PORT_Type Struct Reference
[PORT Peripheral Access Layer]
PORT - Register Layout Typedef. More...
#include <MK64F12.h>
Data Fields | |
| __IO uint32_t | PCR [32] |
| Pin Control Register n, array offset: 0x0, array step: 0x4. | |
| __O uint32_t | GPCLR |
| Global Pin Control Low Register, offset: 0x80. | |
| __O uint32_t | GPCHR |
| Global Pin Control High Register, offset: 0x84. | |
| __IO uint32_t | ISFR |
| Interrupt Status Flag Register, offset: 0xA0. | |
| __IO uint32_t | DFER |
| Digital Filter Enable Register, offset: 0xC0. | |
| __IO uint32_t | DFCR |
| Digital Filter Clock Register, offset: 0xC4. | |
| __IO uint32_t | DFWR |
| Digital Filter Width Register, offset: 0xC8. | |
Detailed Description
PORT - Register Layout Typedef.
Definition at line 10051 of file cmsis/MK64F12.h.
Field Documentation
| __IO uint32_t DFCR |
Digital Filter Clock Register, offset: 0xC4.
Definition at line 10059 of file cmsis/MK64F12.h.
| __IO uint32_t DFER |
Digital Filter Enable Register, offset: 0xC0.
Definition at line 10058 of file cmsis/MK64F12.h.
| __IO uint32_t DFWR |
Digital Filter Width Register, offset: 0xC8.
Definition at line 10060 of file cmsis/MK64F12.h.
| __O uint32_t GPCHR |
Global Pin Control High Register, offset: 0x84.
Definition at line 10054 of file cmsis/MK64F12.h.
| __O uint32_t GPCLR |
Global Pin Control Low Register, offset: 0x80.
Definition at line 10053 of file cmsis/MK64F12.h.
| __IO uint32_t ISFR |
Interrupt Status Flag Register, offset: 0xA0.
Definition at line 10056 of file cmsis/MK64F12.h.
| __IO uint32_t PCR |
Pin Control Register n, array offset: 0x0, array step: 0x4.
Definition at line 10052 of file cmsis/MK64F12.h.
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