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target-mcu-k64f
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Morpheus
ADC_Type Struct Reference
[ADC Peripheral Access Layer]
ADC - Register Layout Typedef. More...
#include <MK64F12.h>
Data Fields | |
| __IO uint32_t | SC1 [2] |
| ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4. | |
| __IO uint32_t | CFG1 |
| ADC Configuration Register 1, offset: 0x8. | |
| __IO uint32_t | CFG2 |
| ADC Configuration Register 2, offset: 0xC. | |
| __I uint32_t | R [2] |
| ADC Data Result Register, array offset: 0x10, array step: 0x4. | |
| __IO uint32_t | CV1 |
| Compare Value Registers, offset: 0x18. | |
| __IO uint32_t | CV2 |
| Compare Value Registers, offset: 0x1C. | |
| __IO uint32_t | SC2 |
| Status and Control Register 2, offset: 0x20. | |
| __IO uint32_t | SC3 |
| Status and Control Register 3, offset: 0x24. | |
| __IO uint32_t | OFS |
| ADC Offset Correction Register, offset: 0x28. | |
| __IO uint32_t | PG |
| ADC Plus-Side Gain Register, offset: 0x2C. | |
| __IO uint32_t | MG |
| ADC Minus-Side Gain Register, offset: 0x30. | |
| __IO uint32_t | CLPD |
| ADC Plus-Side General Calibration Value Register, offset: 0x34. | |
| __IO uint32_t | CLPS |
| ADC Plus-Side General Calibration Value Register, offset: 0x38. | |
| __IO uint32_t | CLP4 |
| ADC Plus-Side General Calibration Value Register, offset: 0x3C. | |
| __IO uint32_t | CLP3 |
| ADC Plus-Side General Calibration Value Register, offset: 0x40. | |
| __IO uint32_t | CLP2 |
| ADC Plus-Side General Calibration Value Register, offset: 0x44. | |
| __IO uint32_t | CLP1 |
| ADC Plus-Side General Calibration Value Register, offset: 0x48. | |
| __IO uint32_t | CLP0 |
| ADC Plus-Side General Calibration Value Register, offset: 0x4C. | |
| __IO uint32_t | CLMD |
| ADC Minus-Side General Calibration Value Register, offset: 0x54. | |
| __IO uint32_t | CLMS |
| ADC Minus-Side General Calibration Value Register, offset: 0x58. | |
| __IO uint32_t | CLM4 |
| ADC Minus-Side General Calibration Value Register, offset: 0x5C. | |
| __IO uint32_t | CLM3 |
| ADC Minus-Side General Calibration Value Register, offset: 0x60. | |
| __IO uint32_t | CLM2 |
| ADC Minus-Side General Calibration Value Register, offset: 0x64. | |
| __IO uint32_t | CLM1 |
| ADC Minus-Side General Calibration Value Register, offset: 0x68. | |
| __IO uint32_t | CLM0 |
| ADC Minus-Side General Calibration Value Register, offset: 0x6C. | |
Detailed Description
ADC - Register Layout Typedef.
Definition at line 330 of file cmsis/MK64F12.h.
Field Documentation
| __IO uint32_t CFG1 |
ADC Configuration Register 1, offset: 0x8.
Definition at line 332 of file cmsis/MK64F12.h.
| __IO uint32_t CFG2 |
ADC Configuration Register 2, offset: 0xC.
Definition at line 333 of file cmsis/MK64F12.h.
| __IO uint32_t CLM0 |
ADC Minus-Side General Calibration Value Register, offset: 0x6C.
Definition at line 356 of file cmsis/MK64F12.h.
| __IO uint32_t CLM1 |
ADC Minus-Side General Calibration Value Register, offset: 0x68.
Definition at line 355 of file cmsis/MK64F12.h.
| __IO uint32_t CLM2 |
ADC Minus-Side General Calibration Value Register, offset: 0x64.
Definition at line 354 of file cmsis/MK64F12.h.
| __IO uint32_t CLM3 |
ADC Minus-Side General Calibration Value Register, offset: 0x60.
Definition at line 353 of file cmsis/MK64F12.h.
| __IO uint32_t CLM4 |
ADC Minus-Side General Calibration Value Register, offset: 0x5C.
Definition at line 352 of file cmsis/MK64F12.h.
| __IO uint32_t CLMD |
ADC Minus-Side General Calibration Value Register, offset: 0x54.
Definition at line 350 of file cmsis/MK64F12.h.
| __IO uint32_t CLMS |
ADC Minus-Side General Calibration Value Register, offset: 0x58.
Definition at line 351 of file cmsis/MK64F12.h.
| __IO uint32_t CLP0 |
ADC Plus-Side General Calibration Value Register, offset: 0x4C.
Definition at line 348 of file cmsis/MK64F12.h.
| __IO uint32_t CLP1 |
ADC Plus-Side General Calibration Value Register, offset: 0x48.
Definition at line 347 of file cmsis/MK64F12.h.
| __IO uint32_t CLP2 |
ADC Plus-Side General Calibration Value Register, offset: 0x44.
Definition at line 346 of file cmsis/MK64F12.h.
| __IO uint32_t CLP3 |
ADC Plus-Side General Calibration Value Register, offset: 0x40.
Definition at line 345 of file cmsis/MK64F12.h.
| __IO uint32_t CLP4 |
ADC Plus-Side General Calibration Value Register, offset: 0x3C.
Definition at line 344 of file cmsis/MK64F12.h.
| __IO uint32_t CLPD |
ADC Plus-Side General Calibration Value Register, offset: 0x34.
Definition at line 342 of file cmsis/MK64F12.h.
| __IO uint32_t CLPS |
ADC Plus-Side General Calibration Value Register, offset: 0x38.
Definition at line 343 of file cmsis/MK64F12.h.
| __IO uint32_t CV1 |
Compare Value Registers, offset: 0x18.
Definition at line 335 of file cmsis/MK64F12.h.
| __IO uint32_t CV2 |
Compare Value Registers, offset: 0x1C.
Definition at line 336 of file cmsis/MK64F12.h.
| __IO uint32_t MG |
ADC Minus-Side Gain Register, offset: 0x30.
Definition at line 341 of file cmsis/MK64F12.h.
| __IO uint32_t OFS |
ADC Offset Correction Register, offset: 0x28.
Definition at line 339 of file cmsis/MK64F12.h.
| __IO uint32_t PG |
ADC Plus-Side Gain Register, offset: 0x2C.
Definition at line 340 of file cmsis/MK64F12.h.
| __I uint32_t R |
ADC Data Result Register, array offset: 0x10, array step: 0x4.
Definition at line 334 of file cmsis/MK64F12.h.
| __IO uint32_t SC1 |
ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4.
Definition at line 331 of file cmsis/MK64F12.h.
| __IO uint32_t SC2 |
Status and Control Register 2, offset: 0x20.
Definition at line 337 of file cmsis/MK64F12.h.
| __IO uint32_t SC3 |
Status and Control Register 3, offset: 0x24.
Definition at line 338 of file cmsis/MK64F12.h.
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