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target-mcu-k64f
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Morpheus
CMP_Type Struct Reference
[CMP Peripheral Access Layer]
CMP - Register Layout Typedef. More...
#include <MK64F12.h>
Data Fields | |
| __IO uint8_t | CR0 |
| CMP Control Register 0, offset: 0x0. | |
| __IO uint8_t | CR1 |
| CMP Control Register 1, offset: 0x1. | |
| __IO uint8_t | FPR |
| CMP Filter Period Register, offset: 0x2. | |
| __IO uint8_t | SCR |
| CMP Status and Control Register, offset: 0x3. | |
| __IO uint8_t | DACCR |
| DAC Control Register, offset: 0x4. | |
| __IO uint8_t | MUXCR |
| MUX Control Register, offset: 0x5. | |
Detailed Description
CMP - Register Layout Typedef.
Definition at line 2956 of file cmsis/MK64F12.h.
Field Documentation
| __IO uint8_t CR0 |
CMP Control Register 0, offset: 0x0.
Definition at line 2957 of file cmsis/MK64F12.h.
| __IO uint8_t CR1 |
CMP Control Register 1, offset: 0x1.
Definition at line 2958 of file cmsis/MK64F12.h.
| __IO uint8_t DACCR |
DAC Control Register, offset: 0x4.
Definition at line 2961 of file cmsis/MK64F12.h.
| __IO uint8_t FPR |
CMP Filter Period Register, offset: 0x2.
Definition at line 2959 of file cmsis/MK64F12.h.
| __IO uint8_t MUXCR |
MUX Control Register, offset: 0x5.
Definition at line 2962 of file cmsis/MK64F12.h.
| __IO uint8_t SCR |
CMP Status and Control Register, offset: 0x3.
Definition at line 2960 of file cmsis/MK64F12.h.
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