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target-mcu-k64f
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Morpheus
SPI_Type Struct Reference
[SPI Peripheral Access Layer]
SPI - Register Layout Typedef. More...
#include <MK64F12.h>
Data Fields | |
| __IO uint32_t | MCR |
| Module Configuration Register, offset: 0x0. | |
| __IO uint32_t | TCR |
| Transfer Count Register, offset: 0x8. | |
| __IO uint32_t | SR |
| Status Register, offset: 0x2C. | |
| __IO uint32_t | RSER |
| DMA/Interrupt Request Select and Enable Register, offset: 0x30. | |
| __I uint32_t | POPR |
| POP RX FIFO Register, offset: 0x38. | |
| __I uint32_t | TXFR0 |
| Transmit FIFO Registers, offset: 0x3C. | |
| __I uint32_t | TXFR1 |
| Transmit FIFO Registers, offset: 0x40. | |
| __I uint32_t | TXFR2 |
| Transmit FIFO Registers, offset: 0x44. | |
| __I uint32_t | TXFR3 |
| Transmit FIFO Registers, offset: 0x48. | |
| __I uint32_t | RXFR0 |
| Receive FIFO Registers, offset: 0x7C. | |
| __I uint32_t | RXFR1 |
| Receive FIFO Registers, offset: 0x80. | |
| __I uint32_t | RXFR2 |
| Receive FIFO Registers, offset: 0x84. | |
| __I uint32_t | RXFR3 |
| Receive FIFO Registers, offset: 0x88. | |
| __IO uint32_t | CTAR [2] |
| Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4. | |
| __IO uint32_t | CTAR_SLAVE [1] |
| Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4. | |
| __IO uint32_t | PUSHR |
| PUSH TX FIFO Register In Master Mode, offset: 0x34. | |
| __IO uint32_t | PUSHR_SLAVE |
| PUSH TX FIFO Register In Slave Mode, offset: 0x34. | |
Detailed Description
SPI - Register Layout Typedef.
Definition at line 12195 of file cmsis/MK64F12.h.
Field Documentation
| __IO uint32_t CTAR[2] |
Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4.
Definition at line 12200 of file cmsis/MK64F12.h.
| __IO uint32_t CTAR_SLAVE[1] |
Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4.
Definition at line 12201 of file cmsis/MK64F12.h.
| __IO uint32_t MCR |
Module Configuration Register, offset: 0x0.
Definition at line 12196 of file cmsis/MK64F12.h.
| __I uint32_t POPR |
POP RX FIFO Register, offset: 0x38.
Definition at line 12210 of file cmsis/MK64F12.h.
| __IO uint32_t PUSHR |
PUSH TX FIFO Register In Master Mode, offset: 0x34.
Definition at line 12207 of file cmsis/MK64F12.h.
| __IO uint32_t PUSHR_SLAVE |
PUSH TX FIFO Register In Slave Mode, offset: 0x34.
Definition at line 12208 of file cmsis/MK64F12.h.
| __IO uint32_t RSER |
DMA/Interrupt Request Select and Enable Register, offset: 0x30.
Definition at line 12205 of file cmsis/MK64F12.h.
| __I uint32_t RXFR0 |
Receive FIFO Registers, offset: 0x7C.
Definition at line 12216 of file cmsis/MK64F12.h.
| __I uint32_t RXFR1 |
Receive FIFO Registers, offset: 0x80.
Definition at line 12217 of file cmsis/MK64F12.h.
| __I uint32_t RXFR2 |
Receive FIFO Registers, offset: 0x84.
Definition at line 12218 of file cmsis/MK64F12.h.
| __I uint32_t RXFR3 |
Receive FIFO Registers, offset: 0x88.
Definition at line 12219 of file cmsis/MK64F12.h.
| __IO uint32_t SR |
Status Register, offset: 0x2C.
Definition at line 12204 of file cmsis/MK64F12.h.
| __IO uint32_t TCR |
Transfer Count Register, offset: 0x8.
Definition at line 12198 of file cmsis/MK64F12.h.
| __I uint32_t TXFR0 |
Transmit FIFO Registers, offset: 0x3C.
Definition at line 12211 of file cmsis/MK64F12.h.
| __I uint32_t TXFR1 |
Transmit FIFO Registers, offset: 0x40.
Definition at line 12212 of file cmsis/MK64F12.h.
| __I uint32_t TXFR2 |
Transmit FIFO Registers, offset: 0x44.
Definition at line 12213 of file cmsis/MK64F12.h.
| __I uint32_t TXFR3 |
Transmit FIFO Registers, offset: 0x48.
Definition at line 12214 of file cmsis/MK64F12.h.
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