Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Fork of
target-mcu-k64f
by 
Morpheus
DMA_Type Struct Reference
[DMA Peripheral Access Layer]
DMA - Register Layout Typedef. More...
#include <MK64F12.h>
Data Fields | |
| __IO uint32_t | CR |
| Control Register, offset: 0x0. | |
| __I uint32_t | ES |
| Error Status Register, offset: 0x4. | |
| __IO uint32_t | ERQ |
| Enable Request Register, offset: 0xC. | |
| __IO uint32_t | EEI |
| Enable Error Interrupt Register, offset: 0x14. | |
| __O uint8_t | CEEI |
| Clear Enable Error Interrupt Register, offset: 0x18. | |
| __O uint8_t | SEEI |
| Set Enable Error Interrupt Register, offset: 0x19. | |
| __O uint8_t | CERQ |
| Clear Enable Request Register, offset: 0x1A. | |
| __O uint8_t | SERQ |
| Set Enable Request Register, offset: 0x1B. | |
| __O uint8_t | CDNE |
| Clear DONE Status Bit Register, offset: 0x1C. | |
| __O uint8_t | SSRT |
| Set START Bit Register, offset: 0x1D. | |
| __O uint8_t | CERR |
| Clear Error Register, offset: 0x1E. | |
| __O uint8_t | CINT |
| Clear Interrupt Request Register, offset: 0x1F. | |
| __IO uint32_t | INT |
| Interrupt Request Register, offset: 0x24. | |
| __IO uint32_t | ERR |
| Error Register, offset: 0x2C. | |
| __I uint32_t | HRS |
| Hardware Request Status Register, offset: 0x34. | |
| __IO uint8_t | DCHPRI3 |
| Channel n Priority Register, offset: 0x100. | |
| __IO uint8_t | DCHPRI2 |
| Channel n Priority Register, offset: 0x101. | |
| __IO uint8_t | DCHPRI1 |
| Channel n Priority Register, offset: 0x102. | |
| __IO uint8_t | DCHPRI0 |
| Channel n Priority Register, offset: 0x103. | |
| __IO uint8_t | DCHPRI7 |
| Channel n Priority Register, offset: 0x104. | |
| __IO uint8_t | DCHPRI6 |
| Channel n Priority Register, offset: 0x105. | |
| __IO uint8_t | DCHPRI5 |
| Channel n Priority Register, offset: 0x106. | |
| __IO uint8_t | DCHPRI4 |
| Channel n Priority Register, offset: 0x107. | |
| __IO uint8_t | DCHPRI11 |
| Channel n Priority Register, offset: 0x108. | |
| __IO uint8_t | DCHPRI10 |
| Channel n Priority Register, offset: 0x109. | |
| __IO uint8_t | DCHPRI9 |
| Channel n Priority Register, offset: 0x10A. | |
| __IO uint8_t | DCHPRI8 |
| Channel n Priority Register, offset: 0x10B. | |
| __IO uint8_t | DCHPRI15 |
| Channel n Priority Register, offset: 0x10C. | |
| __IO uint8_t | DCHPRI14 |
| Channel n Priority Register, offset: 0x10D. | |
| __IO uint8_t | DCHPRI13 |
| Channel n Priority Register, offset: 0x10E. | |
| __IO uint8_t | DCHPRI12 |
| Channel n Priority Register, offset: 0x10F. | |
| __IO uint32_t | SADDR |
| TCD Source Address, array offset: 0x1000, array step: 0x20. | |
| __IO uint16_t | SOFF |
| TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20. | |
| __IO uint16_t | ATTR |
| TCD Transfer Attributes, array offset: 0x1006, array step: 0x20. | |
| __IO uint32_t | NBYTES_MLNO |
| TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20. | |
| __IO uint32_t | NBYTES_MLOFFNO |
| TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20. | |
| __IO uint32_t | NBYTES_MLOFFYES |
| TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20. | |
| __IO uint32_t | SLAST |
| TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20. | |
| __IO uint32_t | DADDR |
| TCD Destination Address, array offset: 0x1010, array step: 0x20. | |
| __IO uint16_t | DOFF |
| TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20. | |
| __IO uint16_t | CITER_ELINKNO |
| TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20. | |
| __IO uint16_t | CITER_ELINKYES |
| TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20. | |
| __IO uint32_t | DLAST_SGA |
| TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20. | |
| __IO uint16_t | CSR |
| TCD Control and Status, array offset: 0x101C, array step: 0x20. | |
| __IO uint16_t | BITER_ELINKNO |
| TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20. | |
| __IO uint16_t | BITER_ELINKYES |
| TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20. | |
Detailed Description
DMA - Register Layout Typedef.
Definition at line 3781 of file cmsis/MK64F12.h.
Field Documentation
| __IO uint16_t ATTR |
TCD Transfer Attributes, array offset: 0x1006, array step: 0x20.
Definition at line 3823 of file cmsis/MK64F12.h.
| __IO uint16_t BITER_ELINKNO |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20.
Definition at line 3839 of file cmsis/MK64F12.h.
| __IO uint16_t BITER_ELINKYES |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20.
Definition at line 3840 of file cmsis/MK64F12.h.
| __O uint8_t CDNE |
Clear DONE Status Bit Register, offset: 0x1C.
Definition at line 3792 of file cmsis/MK64F12.h.
| __O uint8_t CEEI |
Clear Enable Error Interrupt Register, offset: 0x18.
Definition at line 3788 of file cmsis/MK64F12.h.
| __O uint8_t CERQ |
Clear Enable Request Register, offset: 0x1A.
Definition at line 3790 of file cmsis/MK64F12.h.
| __O uint8_t CERR |
Clear Error Register, offset: 0x1E.
Definition at line 3794 of file cmsis/MK64F12.h.
| __O uint8_t CINT |
Clear Interrupt Request Register, offset: 0x1F.
Definition at line 3795 of file cmsis/MK64F12.h.
| __IO uint16_t CITER_ELINKNO |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20.
Definition at line 3833 of file cmsis/MK64F12.h.
| __IO uint16_t CITER_ELINKYES |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20.
Definition at line 3834 of file cmsis/MK64F12.h.
| __IO uint32_t CR |
Control Register, offset: 0x0.
Definition at line 3782 of file cmsis/MK64F12.h.
| __IO uint16_t CSR |
TCD Control and Status, array offset: 0x101C, array step: 0x20.
Definition at line 3837 of file cmsis/MK64F12.h.
| __IO uint32_t DADDR |
TCD Destination Address, array offset: 0x1010, array step: 0x20.
Definition at line 3830 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI0 |
Channel n Priority Register, offset: 0x103.
Definition at line 3806 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI1 |
Channel n Priority Register, offset: 0x102.
Definition at line 3805 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI10 |
Channel n Priority Register, offset: 0x109.
Definition at line 3812 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI11 |
Channel n Priority Register, offset: 0x108.
Definition at line 3811 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI12 |
Channel n Priority Register, offset: 0x10F.
Definition at line 3818 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI13 |
Channel n Priority Register, offset: 0x10E.
Definition at line 3817 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI14 |
Channel n Priority Register, offset: 0x10D.
Definition at line 3816 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI15 |
Channel n Priority Register, offset: 0x10C.
Definition at line 3815 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI2 |
Channel n Priority Register, offset: 0x101.
Definition at line 3804 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI3 |
Channel n Priority Register, offset: 0x100.
Definition at line 3803 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI4 |
Channel n Priority Register, offset: 0x107.
Definition at line 3810 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI5 |
Channel n Priority Register, offset: 0x106.
Definition at line 3809 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI6 |
Channel n Priority Register, offset: 0x105.
Definition at line 3808 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI7 |
Channel n Priority Register, offset: 0x104.
Definition at line 3807 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI8 |
Channel n Priority Register, offset: 0x10B.
Definition at line 3814 of file cmsis/MK64F12.h.
| __IO uint8_t DCHPRI9 |
Channel n Priority Register, offset: 0x10A.
Definition at line 3813 of file cmsis/MK64F12.h.
| __IO uint32_t DLAST_SGA |
TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20.
Definition at line 3836 of file cmsis/MK64F12.h.
| __IO uint16_t DOFF |
TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20.
Definition at line 3831 of file cmsis/MK64F12.h.
| __IO uint32_t EEI |
Enable Error Interrupt Register, offset: 0x14.
Definition at line 3787 of file cmsis/MK64F12.h.
| __IO uint32_t ERQ |
Enable Request Register, offset: 0xC.
Definition at line 3785 of file cmsis/MK64F12.h.
| __IO uint32_t ERR |
Error Register, offset: 0x2C.
Definition at line 3799 of file cmsis/MK64F12.h.
| __I uint32_t ES |
Error Status Register, offset: 0x4.
Definition at line 3783 of file cmsis/MK64F12.h.
| __I uint32_t HRS |
Hardware Request Status Register, offset: 0x34.
Definition at line 3801 of file cmsis/MK64F12.h.
| __IO uint32_t INT |
Interrupt Request Register, offset: 0x24.
Definition at line 3797 of file cmsis/MK64F12.h.
| __IO uint32_t NBYTES_MLNO |
TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20.
Definition at line 3825 of file cmsis/MK64F12.h.
| __IO uint32_t NBYTES_MLOFFNO |
TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20.
Definition at line 3826 of file cmsis/MK64F12.h.
| __IO uint32_t NBYTES_MLOFFYES |
TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20.
Definition at line 3827 of file cmsis/MK64F12.h.
| __IO uint32_t SADDR |
TCD Source Address, array offset: 0x1000, array step: 0x20.
Definition at line 3821 of file cmsis/MK64F12.h.
| __O uint8_t SEEI |
Set Enable Error Interrupt Register, offset: 0x19.
Definition at line 3789 of file cmsis/MK64F12.h.
| __O uint8_t SERQ |
Set Enable Request Register, offset: 0x1B.
Definition at line 3791 of file cmsis/MK64F12.h.
| __IO uint32_t SLAST |
TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20.
Definition at line 3829 of file cmsis/MK64F12.h.
| __IO uint16_t SOFF |
TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20.
Definition at line 3822 of file cmsis/MK64F12.h.
| __O uint8_t SSRT |
Set START Bit Register, offset: 0x1D.
Definition at line 3793 of file cmsis/MK64F12.h.
Generated on Sat Aug 27 2022 17:09:03 by
1.7.2