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MK20D5.h
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00001 /* 00002 ** ################################################################### 00003 ** Compilers: Keil ARM C/C++ Compiler 00004 ** Freescale C/C++ for Embedded ARM 00005 ** GNU C Compiler 00006 ** IAR ANSI C/C++ Compiler for ARM 00007 ** 00008 ** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011 00009 ** K20P32M50SF0RM Rev. 1, Oct 2011 00010 ** K20P48M50SF0RM Rev. 1, Oct 2011 00011 ** 00012 ** Version: rev. 3.4, 2013-10-29 00013 ** Build: b151120 00014 ** 00015 ** Abstract: 00016 ** CMSIS Peripheral Access Layer for MK20D5 00017 ** 00018 ** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. 00019 ** All rights reserved. 00020 ** 00021 ** Redistribution and use in source and binary forms, with or without modification, 00022 ** are permitted provided that the following conditions are met: 00023 ** 00024 ** o Redistributions of source code must retain the above copyright notice, this list 00025 ** of conditions and the following disclaimer. 00026 ** 00027 ** o Redistributions in binary form must reproduce the above copyright notice, this 00028 ** list of conditions and the following disclaimer in the documentation and/or 00029 ** other materials provided with the distribution. 00030 ** 00031 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its 00032 ** contributors may be used to endorse or promote products derived from this 00033 ** software without specific prior written permission. 00034 ** 00035 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00036 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00037 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00038 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00039 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00040 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00041 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00042 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00043 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00044 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00045 ** 00046 ** http: www.freescale.com 00047 ** mail: support@freescale.com 00048 ** 00049 ** Revisions: 00050 ** - rev. 2.0 (2011-11-07) 00051 ** Initial public version. 00052 ** - rev. 2.1 (2011-12-13) 00053 ** Removed registers for AIPS and AXBS modules. 00054 ** - rev. 3.0 (2012-03-19) 00055 ** PDB Peripheral register structure updated. 00056 ** DMA Registers and bits for unsupported DMA channels removed. 00057 ** - rev. 3.1 (2012-04-13) 00058 ** Added new #define symbol MCU_MEM_MAP_VERSION_MINOR. 00059 ** Added new #define symbols <peripheralType>_BASE_PTRS. 00060 ** - rev. 3.2 (2013-04-05) 00061 ** Changed start of doxygen comment. 00062 ** - rev. 3.3 (2013-06-24) 00063 ** NV_FOPT register - NMI_DIS bit added. 00064 ** - rev. 3.4 (2013-10-29) 00065 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. 00066 ** 00067 ** ################################################################### 00068 */ 00069 00070 /*! 00071 * @file MK20D5.h 00072 * @version 3.4 00073 * @date 2013-10-29 00074 * @brief CMSIS Peripheral Access Layer for MK20D5 00075 * 00076 * CMSIS Peripheral Access Layer for MK20D5 00077 */ 00078 00079 #ifndef _MK20D5_H_ 00080 #define _MK20D5_H_ /**< Symbol preventing repeated inclusion */ 00081 00082 /** Memory map major version (memory maps with equal major version number are 00083 * compatible) */ 00084 #define MCU_MEM_MAP_VERSION 0x0300U 00085 /** Memory map minor version */ 00086 #define MCU_MEM_MAP_VERSION_MINOR 0x0004U 00087 00088 /** 00089 * @brief Macro to calculate address of an aliased word in the peripheral 00090 * bitband area for a peripheral register and bit (bit band region 0x40000000 to 00091 * 0x400FFFFF). 00092 * @param Reg Register to access. 00093 * @param Bit Bit number to access. 00094 * @return Address of the aliased word in the peripheral bitband area. 00095 */ 00096 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) 00097 /** 00098 * @brief Macro to access a single bit of a peripheral register (bit band region 00099 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can 00100 * be used for peripherals with 32bit access allowed. 00101 * @param Reg Register to access. 00102 * @param Bit Bit number to access. 00103 * @return Value of the targeted bit in the bit band region. 00104 */ 00105 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) 00106 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit))) 00107 /** 00108 * @brief Macro to access a single bit of a peripheral register (bit band region 00109 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can 00110 * be used for peripherals with 16bit access allowed. 00111 * @param Reg Register to access. 00112 * @param Bit Bit number to access. 00113 * @return Value of the targeted bit in the bit band region. 00114 */ 00115 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) 00116 /** 00117 * @brief Macro to access a single bit of a peripheral register (bit band region 00118 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can 00119 * be used for peripherals with 8bit access allowed. 00120 * @param Reg Register to access. 00121 * @param Bit Bit number to access. 00122 * @return Value of the targeted bit in the bit band region. 00123 */ 00124 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) 00125 00126 /* ---------------------------------------------------------------------------- 00127 -- Interrupt vector numbers 00128 ---------------------------------------------------------------------------- */ 00129 00130 /*! 00131 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 00132 * @{ 00133 */ 00134 00135 /** Interrupt Number Definitions */ 00136 #define NUMBER_OF_INT_VECTORS 62 /**< Number of interrupts in the Vector table */ 00137 00138 typedef enum IRQn { 00139 /* Auxiliary constants */ 00140 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 00141 00142 /* Core interrupts */ 00143 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 00144 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ 00145 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ 00146 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ 00147 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ 00148 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ 00149 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ 00150 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ 00151 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ 00152 00153 /* Device specific interrupts */ 00154 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */ 00155 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */ 00156 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */ 00157 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */ 00158 DMA_Error_IRQn = 4, /**< DMA error interrupt */ 00159 Reserved21_IRQn = 5, /**< Reserved interrupt 21 */ 00160 FTFL_IRQn = 6, /**< FTFL interrupt */ 00161 Read_Collision_IRQn = 7, /**< Read collision interrupt */ 00162 LVD_LVW_IRQn = 8, /**< Low Voltage Detect, Low Voltage Warning */ 00163 LLW_IRQn = 9, /**< Low Leakage Wakeup */ 00164 Watchdog_IRQn = 10, /**< WDOG interrupt */ 00165 I2C0_IRQn = 11, /**< I2C0 interrupt */ 00166 SPI0_IRQn = 12, /**< SPI0 interrupt */ 00167 I2S0_Tx_IRQn = 13, /**< I2S0 transmit interrupt */ 00168 I2S0_Rx_IRQn = 14, /**< I2S0 receive interrupt */ 00169 UART0_LON_IRQn = 15, /**< UART0 LON interrupt */ 00170 UART0_RX_TX_IRQn = 16, /**< UART0 receive/transmit interrupt */ 00171 UART0_ERR_IRQn = 17, /**< UART0 error interrupt */ 00172 UART1_RX_TX_IRQn = 18, /**< UART1 receive/transmit interrupt */ 00173 UART1_ERR_IRQn = 19, /**< UART1 error interrupt */ 00174 UART2_RX_TX_IRQn = 20, /**< UART2 receive/transmit interrupt */ 00175 UART2_ERR_IRQn = 21, /**< UART2 error interrupt */ 00176 ADC0_IRQn = 22, /**< ADC0 interrupt */ 00177 CMP0_IRQn = 23, /**< CMP0 interrupt */ 00178 CMP1_IRQn = 24, /**< CMP1 interrupt */ 00179 FTM0_IRQn = 25, /**< FTM0 fault, overflow and channels interrupt */ 00180 FTM1_IRQn = 26, /**< FTM1 fault, overflow and channels interrupt */ 00181 CMT_IRQn = 27, /**< CMT interrupt */ 00182 RTC_IRQn = 28, /**< RTC interrupt */ 00183 RTC_Seconds_IRQn = 29, /**< RTC seconds interrupt */ 00184 PIT0_IRQn = 30, /**< PIT timer channel 0 interrupt */ 00185 PIT1_IRQn = 31, /**< PIT timer channel 1 interrupt */ 00186 PIT2_IRQn = 32, /**< PIT timer channel 2 interrupt */ 00187 PIT3_IRQn = 33, /**< PIT timer channel 3 interrupt */ 00188 PDB0_IRQn = 34, /**< PDB0 interrupt */ 00189 USB0_IRQn = 35, /**< USB0 interrupt */ 00190 USBDCD_IRQn = 36, /**< USBDCD interrupt */ 00191 TSI0_IRQn = 37, /**< TSI0 interrupt */ 00192 MCG_IRQn = 38, /**< MCG interrupt */ 00193 LPTimer_IRQn = 39, /**< LPTimer interrupt */ 00194 PORTA_IRQn = 40, /**< Port A interrupt */ 00195 PORTB_IRQn = 41, /**< Port B interrupt */ 00196 PORTC_IRQn = 42, /**< Port C interrupt */ 00197 PORTD_IRQn = 43, /**< Port D interrupt */ 00198 PORTE_IRQn = 44, /**< Port E interrupt */ 00199 SWI_IRQn = 45 /**< Software interrupt */ 00200 } IRQn_Type ; 00201 00202 /*! 00203 * @} 00204 */ /* end of group Interrupt_vector_numbers */ 00205 00206 00207 /* ---------------------------------------------------------------------------- 00208 -- Cortex M4 Core Configuration 00209 ---------------------------------------------------------------------------- */ 00210 00211 /*! 00212 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration 00213 * @{ 00214 */ 00215 00216 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 00217 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ 00218 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 00219 #define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ 00220 00221 #include "core_cm4.h" /* Core Peripheral Access Layer */ 00222 #include "system_MK20D5.h" /* Device specific configuration file */ 00223 00224 /*! 00225 * @} 00226 */ /* end of group Cortex_Core_Configuration */ 00227 00228 00229 /* ---------------------------------------------------------------------------- 00230 -- Mapping Information 00231 ---------------------------------------------------------------------------- */ 00232 00233 /*! 00234 * @addtogroup Mapping_Information Mapping Information 00235 * @{ 00236 */ 00237 00238 /** Mapping Information */ 00239 /*! 00240 * @addtogroup edma_request 00241 * @{ 00242 */ 00243 00244 /******************************************************************************* 00245 * Definitions 00246 ******************************************************************************/ 00247 00248 /*! 00249 * @brief Structure for the DMA hardware request 00250 * 00251 * Defines the structure for the DMA hardware request collections. The user can configure the 00252 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index 00253 * of the hardware request varies according to the to SoC. 00254 */ 00255 typedef enum _dma_request_source 00256 { 00257 #if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ 00258 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ 00259 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ 00260 defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ 00261 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ 00262 defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ 00263 defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ 00264 defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) 00265 kDmaRequestMux0SoftwareDMARequest = 0|0x100U, /**< Disable */ 00266 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ 00267 kDmaRequestMux0UART0ReceiveDMARequest = 2|0x100U, /**< UART0 Receive. */ 00268 kDmaRequestMux0UART0TransmitDMARequest = 3|0x100U, /**< UART0 Transmit. */ 00269 kDmaRequestMux0UART1ReceiveDMARequest = 4|0x100U, /**< UART1 Receive. */ 00270 kDmaRequestMux0UART1TransmitDMARequest = 5|0x100U, /**< UART1 Transmit. */ 00271 kDmaRequestMux0UART2ReceiveDMARequest = 6|0x100U, /**< UART2 Receive. */ 00272 kDmaRequestMux0UART2TransmitDMARequest = 7|0x100U, /**< UART2 Transmit. */ 00273 kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ 00274 kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ 00275 kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */ 00276 kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */ 00277 kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */ 00278 kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */ 00279 kDmaRequestMux0I2S0ReceiveDMARequest = 14|0x100U, /**< I2S0 Receive. */ 00280 kDmaRequestMux0I2S0TransmitDMARequest = 15|0x100U, /**< I2S0 Transmit. */ 00281 kDmaRequestMux0SPI0ReceiveDMARequest = 16|0x100U, /**< SPI0 Receive. */ 00282 kDmaRequestMux0SPI0TransmitDMARequest = 17|0x100U, /**< SPI0 Transmit. */ 00283 kDmaRequestMux0Reserved18 = 18|0x100U, /**< Reserved18 */ 00284 kDmaRequestMux0Reserved19 = 19|0x100U, /**< Reserved19 */ 00285 kDmaRequestMux0Reserved20 = 20|0x100U, /**< Reserved20 */ 00286 kDmaRequestMux0Reserved21 = 21|0x100U, /**< Reserved21 */ 00287 kDmaRequestMux0I2C0DMARequest = 22|0x100U, /**< I2C0. */ 00288 kDmaRequestMux0Reserved23 = 23|0x100U, /**< Reserved23 */ 00289 kDmaRequestMux0FTM0C0DMARequest = 24|0x100U, /**< FTM0 channel 0. */ 00290 kDmaRequestMux0FTM0C1DMARequest = 25|0x100U, /**< FTM0 channel 1. */ 00291 kDmaRequestMux0FTM0C2DMARequest = 26|0x100U, /**< FTM0 channel 2. */ 00292 kDmaRequestMux0FTM0C3DMARequest = 27|0x100U, /**< FTM0 channel 3. */ 00293 kDmaRequestMux0FTM0C4DMARequest = 28|0x100U, /**< FTM0 channel 4. */ 00294 kDmaRequestMux0FTM0C5DMARequest = 29|0x100U, /**< FTM0 channel 5. */ 00295 kDmaRequestMux0FTM0C6DMARequest = 30|0x100U, /**< FTM0 channel 6. */ 00296 kDmaRequestMux0FTM0C7DMARequest = 31|0x100U, /**< FTM0 channel 7. */ 00297 kDmaRequestMux0FTM1C0DMARequest = 32|0x100U, /**< FTM1 channel 0. */ 00298 kDmaRequestMux0FTM1C1DMARequest = 33|0x100U, /**< FTM1 channel 1. */ 00299 kDmaRequestMux0Reserved34 = 34|0x100U, /**< Reserved34 */ 00300 kDmaRequestMux0Reserved35 = 35|0x100U, /**< Reserved35 */ 00301 kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */ 00302 kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */ 00303 kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */ 00304 kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */ 00305 kDmaRequestMux0ADC0DMARequest = 40|0x100U, /**< ADC0. */ 00306 kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */ 00307 kDmaRequestMux0CMP0DMARequest = 42|0x100U, /**< CMP0. */ 00308 kDmaRequestMux0CMP1DMARequest = 43|0x100U, /**< CMP1. */ 00309 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ 00310 kDmaRequestMux0Reserved45 = 45|0x100U, /**< Reserved45 */ 00311 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ 00312 kDmaRequestMux0CMTDMARequest = 47|0x100U, /**< CMT. */ 00313 kDmaRequestMux0PDBDMARequest = 48|0x100U, /**< PDB. */ 00314 kDmaRequestMux0GPIOPortADMARequest = 49|0x100U, /**< GPIO Port A. */ 00315 kDmaRequestMux0GPIOPortBDMARequest = 50|0x100U, /**< GPIO Port B. */ 00316 kDmaRequestMux0GPIOPortCDMARequest = 51|0x100U, /**< GPIO Port C. */ 00317 kDmaRequestMux0GPIOPortDDMARequest = 52|0x100U, /**< GPIO Port D. */ 00318 kDmaRequestMux0GPIOPortEDMARequest = 53|0x100U, /**< GPIO Port E. */ 00319 kDmaRequestMux0AlwaysEnabledslot54DMARequest = 54|0x100U, /**< Always enabled. */ 00320 kDmaRequestMux0AlwaysEnabledslot55DMARequest = 55|0x100U, /**< Always enabled. */ 00321 kDmaRequestMux0AlwaysEnabledslot56DMARequest = 56|0x100U, /**< Always enabled. */ 00322 kDmaRequestMux0AlwaysEnabledslot57DMARequest = 57|0x100U, /**< Always enabled. */ 00323 kDmaRequestMux0AlwaysEnabledslot58DMARequest = 58|0x100U, /**< Always enabled. */ 00324 kDmaRequestMux0AlwaysEnabledslot59DMARequest = 59|0x100U, /**< Always enabled. */ 00325 kDmaRequestMux0AlwaysEnabledslot60DMARequest = 60|0x100U, /**< Always enabled. */ 00326 kDmaRequestMux0AlwaysEnabledslot61DMARequest = 61|0x100U, /**< Always enabled. */ 00327 kDmaRequestMux0AlwaysEnabledslot62DMARequest = 62|0x100U, /**< Always enabled. */ 00328 kDmaRequestMux0AlwaysEnabledslot63DMARequest = 63|0x100U, /**< Always enabled. */ 00329 #else 00330 #error "No valid CPU defined!" 00331 #endif 00332 } dma_request_source_t; 00333 00334 /* @} */ 00335 00336 00337 /*! 00338 * @} 00339 */ /* end of group Mapping_Information */ 00340 00341 00342 /* ---------------------------------------------------------------------------- 00343 -- Device Peripheral Access Layer 00344 ---------------------------------------------------------------------------- */ 00345 00346 /*! 00347 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 00348 * @{ 00349 */ 00350 00351 00352 /* 00353 ** Start of section using anonymous unions 00354 */ 00355 00356 #if defined(__ARMCC_VERSION) 00357 #pragma push 00358 #pragma anon_unions 00359 #elif defined(__CWCC__) 00360 #pragma push 00361 #pragma cpp_extensions on 00362 #elif defined(__GNUC__) 00363 /* anonymous unions are enabled by default */ 00364 #elif defined(__IAR_SYSTEMS_ICC__) 00365 #pragma language=extended 00366 #else 00367 #error Not supported compiler type 00368 #endif 00369 00370 /* ---------------------------------------------------------------------------- 00371 -- ADC Peripheral Access Layer 00372 ---------------------------------------------------------------------------- */ 00373 00374 /*! 00375 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 00376 * @{ 00377 */ 00378 00379 /** ADC - Register Layout Typedef */ 00380 typedef struct { 00381 __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */ 00382 __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */ 00383 __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */ 00384 __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */ 00385 __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */ 00386 __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */ 00387 __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */ 00388 __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */ 00389 __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */ 00390 __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */ 00391 __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */ 00392 __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */ 00393 __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */ 00394 __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */ 00395 __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */ 00396 __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */ 00397 __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */ 00398 __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */ 00399 uint8_t RESERVED_0[4]; 00400 __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */ 00401 __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */ 00402 __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */ 00403 __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */ 00404 __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */ 00405 __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */ 00406 __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */ 00407 } ADC_Type; 00408 00409 /* ---------------------------------------------------------------------------- 00410 -- ADC Register Masks 00411 ---------------------------------------------------------------------------- */ 00412 00413 /*! 00414 * @addtogroup ADC_Register_Masks ADC Register Masks 00415 * @{ 00416 */ 00417 00418 /*! @name SC1 - ADC status and control registers 1 */ 00419 #define ADC_SC1_ADCH_MASK (0x1FU) 00420 #define ADC_SC1_ADCH_SHIFT (0U) 00421 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) 00422 #define ADC_SC1_DIFF_MASK (0x20U) 00423 #define ADC_SC1_DIFF_SHIFT (5U) 00424 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) 00425 #define ADC_SC1_AIEN_MASK (0x40U) 00426 #define ADC_SC1_AIEN_SHIFT (6U) 00427 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) 00428 #define ADC_SC1_COCO_MASK (0x80U) 00429 #define ADC_SC1_COCO_SHIFT (7U) 00430 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) 00431 00432 /* The count of ADC_SC1 */ 00433 #define ADC_SC1_COUNT (2U) 00434 00435 /*! @name CFG1 - ADC configuration register 1 */ 00436 #define ADC_CFG1_ADICLK_MASK (0x3U) 00437 #define ADC_CFG1_ADICLK_SHIFT (0U) 00438 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) 00439 #define ADC_CFG1_MODE_MASK (0xCU) 00440 #define ADC_CFG1_MODE_SHIFT (2U) 00441 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) 00442 #define ADC_CFG1_ADLSMP_MASK (0x10U) 00443 #define ADC_CFG1_ADLSMP_SHIFT (4U) 00444 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) 00445 #define ADC_CFG1_ADIV_MASK (0x60U) 00446 #define ADC_CFG1_ADIV_SHIFT (5U) 00447 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) 00448 #define ADC_CFG1_ADLPC_MASK (0x80U) 00449 #define ADC_CFG1_ADLPC_SHIFT (7U) 00450 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) 00451 00452 /*! @name CFG2 - Configuration register 2 */ 00453 #define ADC_CFG2_ADLSTS_MASK (0x3U) 00454 #define ADC_CFG2_ADLSTS_SHIFT (0U) 00455 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) 00456 #define ADC_CFG2_ADHSC_MASK (0x4U) 00457 #define ADC_CFG2_ADHSC_SHIFT (2U) 00458 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) 00459 #define ADC_CFG2_ADACKEN_MASK (0x8U) 00460 #define ADC_CFG2_ADACKEN_SHIFT (3U) 00461 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) 00462 #define ADC_CFG2_MUXSEL_MASK (0x10U) 00463 #define ADC_CFG2_MUXSEL_SHIFT (4U) 00464 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) 00465 00466 /*! @name R - ADC data result register */ 00467 #define ADC_R_D_MASK (0xFFFFU) 00468 #define ADC_R_D_SHIFT (0U) 00469 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) 00470 00471 /* The count of ADC_R */ 00472 #define ADC_R_COUNT (2U) 00473 00474 /*! @name CV1 - Compare value registers */ 00475 #define ADC_CV1_CV_MASK (0xFFFFU) 00476 #define ADC_CV1_CV_SHIFT (0U) 00477 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) 00478 00479 /*! @name CV2 - Compare value registers */ 00480 #define ADC_CV2_CV_MASK (0xFFFFU) 00481 #define ADC_CV2_CV_SHIFT (0U) 00482 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) 00483 00484 /*! @name SC2 - Status and control register 2 */ 00485 #define ADC_SC2_REFSEL_MASK (0x3U) 00486 #define ADC_SC2_REFSEL_SHIFT (0U) 00487 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) 00488 #define ADC_SC2_DMAEN_MASK (0x4U) 00489 #define ADC_SC2_DMAEN_SHIFT (2U) 00490 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) 00491 #define ADC_SC2_ACREN_MASK (0x8U) 00492 #define ADC_SC2_ACREN_SHIFT (3U) 00493 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) 00494 #define ADC_SC2_ACFGT_MASK (0x10U) 00495 #define ADC_SC2_ACFGT_SHIFT (4U) 00496 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) 00497 #define ADC_SC2_ACFE_MASK (0x20U) 00498 #define ADC_SC2_ACFE_SHIFT (5U) 00499 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) 00500 #define ADC_SC2_ADTRG_MASK (0x40U) 00501 #define ADC_SC2_ADTRG_SHIFT (6U) 00502 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) 00503 #define ADC_SC2_ADACT_MASK (0x80U) 00504 #define ADC_SC2_ADACT_SHIFT (7U) 00505 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) 00506 00507 /*! @name SC3 - Status and control register 3 */ 00508 #define ADC_SC3_AVGS_MASK (0x3U) 00509 #define ADC_SC3_AVGS_SHIFT (0U) 00510 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) 00511 #define ADC_SC3_AVGE_MASK (0x4U) 00512 #define ADC_SC3_AVGE_SHIFT (2U) 00513 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) 00514 #define ADC_SC3_ADCO_MASK (0x8U) 00515 #define ADC_SC3_ADCO_SHIFT (3U) 00516 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) 00517 #define ADC_SC3_CALF_MASK (0x40U) 00518 #define ADC_SC3_CALF_SHIFT (6U) 00519 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) 00520 #define ADC_SC3_CAL_MASK (0x80U) 00521 #define ADC_SC3_CAL_SHIFT (7U) 00522 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) 00523 00524 /*! @name OFS - ADC offset correction register */ 00525 #define ADC_OFS_OFS_MASK (0xFFFFU) 00526 #define ADC_OFS_OFS_SHIFT (0U) 00527 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) 00528 00529 /*! @name PG - ADC plus-side gain register */ 00530 #define ADC_PG_PG_MASK (0xFFFFU) 00531 #define ADC_PG_PG_SHIFT (0U) 00532 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) 00533 00534 /*! @name MG - ADC minus-side gain register */ 00535 #define ADC_MG_MG_MASK (0xFFFFU) 00536 #define ADC_MG_MG_SHIFT (0U) 00537 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) 00538 00539 /*! @name CLPD - ADC plus-side general calibration value register */ 00540 #define ADC_CLPD_CLPD_MASK (0x3FU) 00541 #define ADC_CLPD_CLPD_SHIFT (0U) 00542 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) 00543 00544 /*! @name CLPS - ADC plus-side general calibration value register */ 00545 #define ADC_CLPS_CLPS_MASK (0x3FU) 00546 #define ADC_CLPS_CLPS_SHIFT (0U) 00547 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) 00548 00549 /*! @name CLP4 - ADC plus-side general calibration value register */ 00550 #define ADC_CLP4_CLP4_MASK (0x3FFU) 00551 #define ADC_CLP4_CLP4_SHIFT (0U) 00552 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) 00553 00554 /*! @name CLP3 - ADC plus-side general calibration value register */ 00555 #define ADC_CLP3_CLP3_MASK (0x1FFU) 00556 #define ADC_CLP3_CLP3_SHIFT (0U) 00557 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) 00558 00559 /*! @name CLP2 - ADC plus-side general calibration value register */ 00560 #define ADC_CLP2_CLP2_MASK (0xFFU) 00561 #define ADC_CLP2_CLP2_SHIFT (0U) 00562 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) 00563 00564 /*! @name CLP1 - ADC plus-side general calibration value register */ 00565 #define ADC_CLP1_CLP1_MASK (0x7FU) 00566 #define ADC_CLP1_CLP1_SHIFT (0U) 00567 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) 00568 00569 /*! @name CLP0 - ADC plus-side general calibration value register */ 00570 #define ADC_CLP0_CLP0_MASK (0x3FU) 00571 #define ADC_CLP0_CLP0_SHIFT (0U) 00572 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) 00573 00574 /*! @name CLMD - ADC minus-side general calibration value register */ 00575 #define ADC_CLMD_CLMD_MASK (0x3FU) 00576 #define ADC_CLMD_CLMD_SHIFT (0U) 00577 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) 00578 00579 /*! @name CLMS - ADC minus-side general calibration value register */ 00580 #define ADC_CLMS_CLMS_MASK (0x3FU) 00581 #define ADC_CLMS_CLMS_SHIFT (0U) 00582 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) 00583 00584 /*! @name CLM4 - ADC minus-side general calibration value register */ 00585 #define ADC_CLM4_CLM4_MASK (0x3FFU) 00586 #define ADC_CLM4_CLM4_SHIFT (0U) 00587 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) 00588 00589 /*! @name CLM3 - ADC minus-side general calibration value register */ 00590 #define ADC_CLM3_CLM3_MASK (0x1FFU) 00591 #define ADC_CLM3_CLM3_SHIFT (0U) 00592 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) 00593 00594 /*! @name CLM2 - ADC minus-side general calibration value register */ 00595 #define ADC_CLM2_CLM2_MASK (0xFFU) 00596 #define ADC_CLM2_CLM2_SHIFT (0U) 00597 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) 00598 00599 /*! @name CLM1 - ADC minus-side general calibration value register */ 00600 #define ADC_CLM1_CLM1_MASK (0x7FU) 00601 #define ADC_CLM1_CLM1_SHIFT (0U) 00602 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) 00603 00604 /*! @name CLM0 - ADC minus-side general calibration value register */ 00605 #define ADC_CLM0_CLM0_MASK (0x3FU) 00606 #define ADC_CLM0_CLM0_SHIFT (0U) 00607 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) 00608 00609 00610 /*! 00611 * @} 00612 */ /* end of group ADC_Register_Masks */ 00613 00614 00615 /* ADC - Peripheral instance base addresses */ 00616 /** Peripheral ADC0 base address */ 00617 #define ADC0_BASE (0x4003B000u) 00618 /** Peripheral ADC0 base pointer */ 00619 #define ADC0 ((ADC_Type *)ADC0_BASE) 00620 /** Array initializer of ADC peripheral base addresses */ 00621 #define ADC_BASE_ADDRS { ADC0_BASE } 00622 /** Array initializer of ADC peripheral base pointers */ 00623 #define ADC_BASE_PTRS { ADC0 } 00624 /** Interrupt vectors for the ADC peripheral type */ 00625 #define ADC_IRQS { ADC0_IRQn } 00626 00627 /*! 00628 * @} 00629 */ /* end of group ADC_Peripheral_Access_Layer */ 00630 00631 00632 /* ---------------------------------------------------------------------------- 00633 -- CMP Peripheral Access Layer 00634 ---------------------------------------------------------------------------- */ 00635 00636 /*! 00637 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer 00638 * @{ 00639 */ 00640 00641 /** CMP - Register Layout Typedef */ 00642 typedef struct { 00643 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ 00644 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ 00645 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ 00646 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ 00647 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ 00648 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ 00649 } CMP_Type; 00650 00651 /* ---------------------------------------------------------------------------- 00652 -- CMP Register Masks 00653 ---------------------------------------------------------------------------- */ 00654 00655 /*! 00656 * @addtogroup CMP_Register_Masks CMP Register Masks 00657 * @{ 00658 */ 00659 00660 /*! @name CR0 - CMP Control Register 0 */ 00661 #define CMP_CR0_HYSTCTR_MASK (0x3U) 00662 #define CMP_CR0_HYSTCTR_SHIFT (0U) 00663 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) 00664 #define CMP_CR0_FILTER_CNT_MASK (0x70U) 00665 #define CMP_CR0_FILTER_CNT_SHIFT (4U) 00666 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) 00667 00668 /*! @name CR1 - CMP Control Register 1 */ 00669 #define CMP_CR1_EN_MASK (0x1U) 00670 #define CMP_CR1_EN_SHIFT (0U) 00671 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) 00672 #define CMP_CR1_OPE_MASK (0x2U) 00673 #define CMP_CR1_OPE_SHIFT (1U) 00674 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) 00675 #define CMP_CR1_COS_MASK (0x4U) 00676 #define CMP_CR1_COS_SHIFT (2U) 00677 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) 00678 #define CMP_CR1_INV_MASK (0x8U) 00679 #define CMP_CR1_INV_SHIFT (3U) 00680 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) 00681 #define CMP_CR1_PMODE_MASK (0x10U) 00682 #define CMP_CR1_PMODE_SHIFT (4U) 00683 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) 00684 #define CMP_CR1_WE_MASK (0x40U) 00685 #define CMP_CR1_WE_SHIFT (6U) 00686 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) 00687 #define CMP_CR1_SE_MASK (0x80U) 00688 #define CMP_CR1_SE_SHIFT (7U) 00689 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) 00690 00691 /*! @name FPR - CMP Filter Period Register */ 00692 #define CMP_FPR_FILT_PER_MASK (0xFFU) 00693 #define CMP_FPR_FILT_PER_SHIFT (0U) 00694 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) 00695 00696 /*! @name SCR - CMP Status and Control Register */ 00697 #define CMP_SCR_COUT_MASK (0x1U) 00698 #define CMP_SCR_COUT_SHIFT (0U) 00699 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) 00700 #define CMP_SCR_CFF_MASK (0x2U) 00701 #define CMP_SCR_CFF_SHIFT (1U) 00702 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) 00703 #define CMP_SCR_CFR_MASK (0x4U) 00704 #define CMP_SCR_CFR_SHIFT (2U) 00705 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) 00706 #define CMP_SCR_IEF_MASK (0x8U) 00707 #define CMP_SCR_IEF_SHIFT (3U) 00708 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) 00709 #define CMP_SCR_IER_MASK (0x10U) 00710 #define CMP_SCR_IER_SHIFT (4U) 00711 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) 00712 #define CMP_SCR_DMAEN_MASK (0x40U) 00713 #define CMP_SCR_DMAEN_SHIFT (6U) 00714 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) 00715 00716 /*! @name DACCR - DAC Control Register */ 00717 #define CMP_DACCR_VOSEL_MASK (0x3FU) 00718 #define CMP_DACCR_VOSEL_SHIFT (0U) 00719 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) 00720 #define CMP_DACCR_VRSEL_MASK (0x40U) 00721 #define CMP_DACCR_VRSEL_SHIFT (6U) 00722 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) 00723 #define CMP_DACCR_DACEN_MASK (0x80U) 00724 #define CMP_DACCR_DACEN_SHIFT (7U) 00725 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) 00726 00727 /*! @name MUXCR - MUX Control Register */ 00728 #define CMP_MUXCR_MSEL_MASK (0x7U) 00729 #define CMP_MUXCR_MSEL_SHIFT (0U) 00730 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) 00731 #define CMP_MUXCR_PSEL_MASK (0x38U) 00732 #define CMP_MUXCR_PSEL_SHIFT (3U) 00733 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) 00734 00735 00736 /*! 00737 * @} 00738 */ /* end of group CMP_Register_Masks */ 00739 00740 00741 /* CMP - Peripheral instance base addresses */ 00742 /** Peripheral CMP0 base address */ 00743 #define CMP0_BASE (0x40073000u) 00744 /** Peripheral CMP0 base pointer */ 00745 #define CMP0 ((CMP_Type *)CMP0_BASE) 00746 /** Peripheral CMP1 base address */ 00747 #define CMP1_BASE (0x40073008u) 00748 /** Peripheral CMP1 base pointer */ 00749 #define CMP1 ((CMP_Type *)CMP1_BASE) 00750 /** Array initializer of CMP peripheral base addresses */ 00751 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } 00752 /** Array initializer of CMP peripheral base pointers */ 00753 #define CMP_BASE_PTRS { CMP0, CMP1 } 00754 /** Interrupt vectors for the CMP peripheral type */ 00755 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn } 00756 00757 /*! 00758 * @} 00759 */ /* end of group CMP_Peripheral_Access_Layer */ 00760 00761 00762 /* ---------------------------------------------------------------------------- 00763 -- CMT Peripheral Access Layer 00764 ---------------------------------------------------------------------------- */ 00765 00766 /*! 00767 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer 00768 * @{ 00769 */ 00770 00771 /** CMT - Register Layout Typedef */ 00772 typedef struct { 00773 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */ 00774 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */ 00775 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */ 00776 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */ 00777 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */ 00778 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */ 00779 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */ 00780 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */ 00781 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */ 00782 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */ 00783 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */ 00784 __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */ 00785 } CMT_Type; 00786 00787 /* ---------------------------------------------------------------------------- 00788 -- CMT Register Masks 00789 ---------------------------------------------------------------------------- */ 00790 00791 /*! 00792 * @addtogroup CMT_Register_Masks CMT Register Masks 00793 * @{ 00794 */ 00795 00796 /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */ 00797 #define CMT_CGH1_PH_MASK (0xFFU) 00798 #define CMT_CGH1_PH_SHIFT (0U) 00799 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK) 00800 00801 /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */ 00802 #define CMT_CGL1_PL_MASK (0xFFU) 00803 #define CMT_CGL1_PL_SHIFT (0U) 00804 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK) 00805 00806 /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */ 00807 #define CMT_CGH2_SH_MASK (0xFFU) 00808 #define CMT_CGH2_SH_SHIFT (0U) 00809 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK) 00810 00811 /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */ 00812 #define CMT_CGL2_SL_MASK (0xFFU) 00813 #define CMT_CGL2_SL_SHIFT (0U) 00814 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK) 00815 00816 /*! @name OC - CMT Output Control Register */ 00817 #define CMT_OC_IROPEN_MASK (0x20U) 00818 #define CMT_OC_IROPEN_SHIFT (5U) 00819 #define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK) 00820 #define CMT_OC_CMTPOL_MASK (0x40U) 00821 #define CMT_OC_CMTPOL_SHIFT (6U) 00822 #define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK) 00823 #define CMT_OC_IROL_MASK (0x80U) 00824 #define CMT_OC_IROL_SHIFT (7U) 00825 #define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK) 00826 00827 /*! @name MSC - CMT Modulator Status and Control Register */ 00828 #define CMT_MSC_MCGEN_MASK (0x1U) 00829 #define CMT_MSC_MCGEN_SHIFT (0U) 00830 #define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK) 00831 #define CMT_MSC_EOCIE_MASK (0x2U) 00832 #define CMT_MSC_EOCIE_SHIFT (1U) 00833 #define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK) 00834 #define CMT_MSC_FSK_MASK (0x4U) 00835 #define CMT_MSC_FSK_SHIFT (2U) 00836 #define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK) 00837 #define CMT_MSC_BASE_MASK (0x8U) 00838 #define CMT_MSC_BASE_SHIFT (3U) 00839 #define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK) 00840 #define CMT_MSC_EXSPC_MASK (0x10U) 00841 #define CMT_MSC_EXSPC_SHIFT (4U) 00842 #define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK) 00843 #define CMT_MSC_CMTDIV_MASK (0x60U) 00844 #define CMT_MSC_CMTDIV_SHIFT (5U) 00845 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK) 00846 #define CMT_MSC_EOCF_MASK (0x80U) 00847 #define CMT_MSC_EOCF_SHIFT (7U) 00848 #define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK) 00849 00850 /*! @name CMD1 - CMT Modulator Data Register Mark High */ 00851 #define CMT_CMD1_MB_MASK (0xFFU) 00852 #define CMT_CMD1_MB_SHIFT (0U) 00853 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK) 00854 00855 /*! @name CMD2 - CMT Modulator Data Register Mark Low */ 00856 #define CMT_CMD2_MB_MASK (0xFFU) 00857 #define CMT_CMD2_MB_SHIFT (0U) 00858 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK) 00859 00860 /*! @name CMD3 - CMT Modulator Data Register Space High */ 00861 #define CMT_CMD3_SB_MASK (0xFFU) 00862 #define CMT_CMD3_SB_SHIFT (0U) 00863 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK) 00864 00865 /*! @name CMD4 - CMT Modulator Data Register Space Low */ 00866 #define CMT_CMD4_SB_MASK (0xFFU) 00867 #define CMT_CMD4_SB_SHIFT (0U) 00868 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK) 00869 00870 /*! @name PPS - CMT Primary Prescaler Register */ 00871 #define CMT_PPS_PPSDIV_MASK (0xFU) 00872 #define CMT_PPS_PPSDIV_SHIFT (0U) 00873 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK) 00874 00875 /*! @name DMA - CMT Direct Memory Access */ 00876 #define CMT_DMA_DMA_MASK (0x1U) 00877 #define CMT_DMA_DMA_SHIFT (0U) 00878 #define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK) 00879 00880 00881 /*! 00882 * @} 00883 */ /* end of group CMT_Register_Masks */ 00884 00885 00886 /* CMT - Peripheral instance base addresses */ 00887 /** Peripheral CMT base address */ 00888 #define CMT_BASE (0x40062000u) 00889 /** Peripheral CMT base pointer */ 00890 #define CMT ((CMT_Type *)CMT_BASE) 00891 /** Array initializer of CMT peripheral base addresses */ 00892 #define CMT_BASE_ADDRS { CMT_BASE } 00893 /** Array initializer of CMT peripheral base pointers */ 00894 #define CMT_BASE_PTRS { CMT } 00895 /** Interrupt vectors for the CMT peripheral type */ 00896 #define CMT_IRQS { CMT_IRQn } 00897 00898 /*! 00899 * @} 00900 */ /* end of group CMT_Peripheral_Access_Layer */ 00901 00902 00903 /* ---------------------------------------------------------------------------- 00904 -- CRC Peripheral Access Layer 00905 ---------------------------------------------------------------------------- */ 00906 00907 /*! 00908 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer 00909 * @{ 00910 */ 00911 00912 /** CRC - Register Layout Typedef */ 00913 typedef struct { 00914 union { /* offset: 0x0 */ 00915 struct { /* offset: 0x0 */ 00916 __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */ 00917 __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */ 00918 } ACCESS16BIT; 00919 __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */ 00920 struct { /* offset: 0x0 */ 00921 __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */ 00922 __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */ 00923 __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */ 00924 __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */ 00925 } ACCESS8BIT; 00926 }; 00927 union { /* offset: 0x4 */ 00928 struct { /* offset: 0x4 */ 00929 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ 00930 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ 00931 } GPOLY_ACCESS16BIT; 00932 __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */ 00933 struct { /* offset: 0x4 */ 00934 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ 00935 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ 00936 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ 00937 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ 00938 } GPOLY_ACCESS8BIT; 00939 }; 00940 union { /* offset: 0x8 */ 00941 __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */ 00942 struct { /* offset: 0x8 */ 00943 uint8_t RESERVED_0[3]; 00944 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ 00945 } CTRL_ACCESS8BIT; 00946 }; 00947 } CRC_Type; 00948 00949 /* ---------------------------------------------------------------------------- 00950 -- CRC Register Masks 00951 ---------------------------------------------------------------------------- */ 00952 00953 /*! 00954 * @addtogroup CRC_Register_Masks CRC Register Masks 00955 * @{ 00956 */ 00957 00958 /*! @name CRCL - CRC_CRCL register. */ 00959 #define CRC_CRCL_CRCL_MASK (0xFFFFU) 00960 #define CRC_CRCL_CRCL_SHIFT (0U) 00961 #define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x)) << CRC_CRCL_CRCL_SHIFT)) & CRC_CRCL_CRCL_MASK) 00962 00963 /*! @name CRCH - CRC_CRCH register. */ 00964 #define CRC_CRCH_CRCH_MASK (0xFFFFU) 00965 #define CRC_CRCH_CRCH_SHIFT (0U) 00966 #define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x)) << CRC_CRCH_CRCH_SHIFT)) & CRC_CRCH_CRCH_MASK) 00967 00968 /*! @name CRC - CRC Data Register */ 00969 #define CRC_CRC_LL_MASK (0xFFU) 00970 #define CRC_CRC_LL_SHIFT (0U) 00971 #define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_LL_SHIFT)) & CRC_CRC_LL_MASK) 00972 #define CRC_CRC_LU_MASK (0xFF00U) 00973 #define CRC_CRC_LU_SHIFT (8U) 00974 #define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_LU_SHIFT)) & CRC_CRC_LU_MASK) 00975 #define CRC_CRC_HL_MASK (0xFF0000U) 00976 #define CRC_CRC_HL_SHIFT (16U) 00977 #define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_HL_SHIFT)) & CRC_CRC_HL_MASK) 00978 #define CRC_CRC_HU_MASK (0xFF000000U) 00979 #define CRC_CRC_HU_SHIFT (24U) 00980 #define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_HU_SHIFT)) & CRC_CRC_HU_MASK) 00981 00982 /*! @name CRCLL - CRC_CRCLL register. */ 00983 #define CRC_CRCLL_CRCLL_MASK (0xFFU) 00984 #define CRC_CRCLL_CRCLL_SHIFT (0U) 00985 #define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCLL_CRCLL_SHIFT)) & CRC_CRCLL_CRCLL_MASK) 00986 00987 /*! @name CRCLU - CRC_CRCLU register. */ 00988 #define CRC_CRCLU_CRCLU_MASK (0xFFU) 00989 #define CRC_CRCLU_CRCLU_SHIFT (0U) 00990 #define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCLU_CRCLU_SHIFT)) & CRC_CRCLU_CRCLU_MASK) 00991 00992 /*! @name CRCHL - CRC_CRCHL register. */ 00993 #define CRC_CRCHL_CRCHL_MASK (0xFFU) 00994 #define CRC_CRCHL_CRCHL_SHIFT (0U) 00995 #define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCHL_CRCHL_SHIFT)) & CRC_CRCHL_CRCHL_MASK) 00996 00997 /*! @name CRCHU - CRC_CRCHU register. */ 00998 #define CRC_CRCHU_CRCHU_MASK (0xFFU) 00999 #define CRC_CRCHU_CRCHU_SHIFT (0U) 01000 #define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCHU_CRCHU_SHIFT)) & CRC_CRCHU_CRCHU_MASK) 01001 01002 /*! @name GPOLYL - CRC_GPOLYL register. */ 01003 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) 01004 #define CRC_GPOLYL_GPOLYL_SHIFT (0U) 01005 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) 01006 01007 /*! @name GPOLYH - CRC_GPOLYH register. */ 01008 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) 01009 #define CRC_GPOLYH_GPOLYH_SHIFT (0U) 01010 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) 01011 01012 /*! @name GPOLY - CRC Polynomial Register */ 01013 #define CRC_GPOLY_LOW_MASK (0xFFFFU) 01014 #define CRC_GPOLY_LOW_SHIFT (0U) 01015 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) 01016 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) 01017 #define CRC_GPOLY_HIGH_SHIFT (16U) 01018 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) 01019 01020 /*! @name GPOLYLL - CRC_GPOLYLL register. */ 01021 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) 01022 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) 01023 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) 01024 01025 /*! @name GPOLYLU - CRC_GPOLYLU register. */ 01026 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) 01027 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) 01028 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) 01029 01030 /*! @name GPOLYHL - CRC_GPOLYHL register. */ 01031 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) 01032 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) 01033 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) 01034 01035 /*! @name GPOLYHU - CRC_GPOLYHU register. */ 01036 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) 01037 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) 01038 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) 01039 01040 /*! @name CTRL - CRC Control Register */ 01041 #define CRC_CTRL_TCRC_MASK (0x1000000U) 01042 #define CRC_CTRL_TCRC_SHIFT (24U) 01043 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) 01044 #define CRC_CTRL_WAS_MASK (0x2000000U) 01045 #define CRC_CTRL_WAS_SHIFT (25U) 01046 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) 01047 #define CRC_CTRL_FXOR_MASK (0x4000000U) 01048 #define CRC_CTRL_FXOR_SHIFT (26U) 01049 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) 01050 #define CRC_CTRL_TOTR_MASK (0x30000000U) 01051 #define CRC_CTRL_TOTR_SHIFT (28U) 01052 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) 01053 #define CRC_CTRL_TOT_MASK (0xC0000000U) 01054 #define CRC_CTRL_TOT_SHIFT (30U) 01055 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) 01056 01057 /*! @name CTRLHU - CRC_CTRLHU register. */ 01058 #define CRC_CTRLHU_TCRC_MASK (0x1U) 01059 #define CRC_CTRLHU_TCRC_SHIFT (0U) 01060 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) 01061 #define CRC_CTRLHU_WAS_MASK (0x2U) 01062 #define CRC_CTRLHU_WAS_SHIFT (1U) 01063 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) 01064 #define CRC_CTRLHU_FXOR_MASK (0x4U) 01065 #define CRC_CTRLHU_FXOR_SHIFT (2U) 01066 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) 01067 #define CRC_CTRLHU_TOTR_MASK (0x30U) 01068 #define CRC_CTRLHU_TOTR_SHIFT (4U) 01069 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) 01070 #define CRC_CTRLHU_TOT_MASK (0xC0U) 01071 #define CRC_CTRLHU_TOT_SHIFT (6U) 01072 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) 01073 01074 01075 /*! 01076 * @} 01077 */ /* end of group CRC_Register_Masks */ 01078 01079 01080 /* CRC - Peripheral instance base addresses */ 01081 /** Peripheral CRC base address */ 01082 #define CRC_BASE (0x40032000u) 01083 /** Peripheral CRC base pointer */ 01084 #define CRC0 ((CRC_Type *)CRC_BASE) 01085 /** Array initializer of CRC peripheral base addresses */ 01086 #define CRC_BASE_ADDRS { CRC_BASE } 01087 /** Array initializer of CRC peripheral base pointers */ 01088 #define CRC_BASE_PTRS { CRC0 } 01089 01090 /*! 01091 * @} 01092 */ /* end of group CRC_Peripheral_Access_Layer */ 01093 01094 01095 /* ---------------------------------------------------------------------------- 01096 -- DMA Peripheral Access Layer 01097 ---------------------------------------------------------------------------- */ 01098 01099 /*! 01100 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer 01101 * @{ 01102 */ 01103 01104 /** DMA - Register Layout Typedef */ 01105 typedef struct { 01106 __IO uint32_t CR; /**< Control Register, offset: 0x0 */ 01107 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ 01108 uint8_t RESERVED_0[4]; 01109 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ 01110 uint8_t RESERVED_1[4]; 01111 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ 01112 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ 01113 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ 01114 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ 01115 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ 01116 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ 01117 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ 01118 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ 01119 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ 01120 uint8_t RESERVED_2[4]; 01121 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ 01122 uint8_t RESERVED_3[4]; 01123 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ 01124 uint8_t RESERVED_4[4]; 01125 __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ 01126 uint8_t RESERVED_5[200]; 01127 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ 01128 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ 01129 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ 01130 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ 01131 uint8_t RESERVED_6[3836]; 01132 struct { /* offset: 0x1000, array step: 0x20 */ 01133 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ 01134 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ 01135 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ 01136 union { /* offset: 0x1008, array step: 0x20 */ 01137 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */ 01138 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ 01139 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */ 01140 }; 01141 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ 01142 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ 01143 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ 01144 union { /* offset: 0x1016, array step: 0x20 */ 01145 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ 01146 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ 01147 }; 01148 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ 01149 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ 01150 union { /* offset: 0x101E, array step: 0x20 */ 01151 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ 01152 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ 01153 }; 01154 } TCD[4]; 01155 } DMA_Type; 01156 01157 /* ---------------------------------------------------------------------------- 01158 -- DMA Register Masks 01159 ---------------------------------------------------------------------------- */ 01160 01161 /*! 01162 * @addtogroup DMA_Register_Masks DMA Register Masks 01163 * @{ 01164 */ 01165 01166 /*! @name CR - Control Register */ 01167 #define DMA_CR_EDBG_MASK (0x2U) 01168 #define DMA_CR_EDBG_SHIFT (1U) 01169 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) 01170 #define DMA_CR_ERCA_MASK (0x4U) 01171 #define DMA_CR_ERCA_SHIFT (2U) 01172 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) 01173 #define DMA_CR_HOE_MASK (0x10U) 01174 #define DMA_CR_HOE_SHIFT (4U) 01175 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) 01176 #define DMA_CR_HALT_MASK (0x20U) 01177 #define DMA_CR_HALT_SHIFT (5U) 01178 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) 01179 #define DMA_CR_CLM_MASK (0x40U) 01180 #define DMA_CR_CLM_SHIFT (6U) 01181 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) 01182 #define DMA_CR_EMLM_MASK (0x80U) 01183 #define DMA_CR_EMLM_SHIFT (7U) 01184 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) 01185 #define DMA_CR_ECX_MASK (0x10000U) 01186 #define DMA_CR_ECX_SHIFT (16U) 01187 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) 01188 #define DMA_CR_CX_MASK (0x20000U) 01189 #define DMA_CR_CX_SHIFT (17U) 01190 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) 01191 01192 /*! @name ES - Error Status Register */ 01193 #define DMA_ES_DBE_MASK (0x1U) 01194 #define DMA_ES_DBE_SHIFT (0U) 01195 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) 01196 #define DMA_ES_SBE_MASK (0x2U) 01197 #define DMA_ES_SBE_SHIFT (1U) 01198 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) 01199 #define DMA_ES_SGE_MASK (0x4U) 01200 #define DMA_ES_SGE_SHIFT (2U) 01201 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) 01202 #define DMA_ES_NCE_MASK (0x8U) 01203 #define DMA_ES_NCE_SHIFT (3U) 01204 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) 01205 #define DMA_ES_DOE_MASK (0x10U) 01206 #define DMA_ES_DOE_SHIFT (4U) 01207 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) 01208 #define DMA_ES_DAE_MASK (0x20U) 01209 #define DMA_ES_DAE_SHIFT (5U) 01210 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) 01211 #define DMA_ES_SOE_MASK (0x40U) 01212 #define DMA_ES_SOE_SHIFT (6U) 01213 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) 01214 #define DMA_ES_SAE_MASK (0x80U) 01215 #define DMA_ES_SAE_SHIFT (7U) 01216 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) 01217 #define DMA_ES_ERRCHN_MASK (0xF00U) 01218 #define DMA_ES_ERRCHN_SHIFT (8U) 01219 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) 01220 #define DMA_ES_CPE_MASK (0x4000U) 01221 #define DMA_ES_CPE_SHIFT (14U) 01222 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) 01223 #define DMA_ES_ECX_MASK (0x10000U) 01224 #define DMA_ES_ECX_SHIFT (16U) 01225 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) 01226 #define DMA_ES_VLD_MASK (0x80000000U) 01227 #define DMA_ES_VLD_SHIFT (31U) 01228 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) 01229 01230 /*! @name ERQ - Enable Request Register */ 01231 #define DMA_ERQ_ERQ0_MASK (0x1U) 01232 #define DMA_ERQ_ERQ0_SHIFT (0U) 01233 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) 01234 #define DMA_ERQ_ERQ1_MASK (0x2U) 01235 #define DMA_ERQ_ERQ1_SHIFT (1U) 01236 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) 01237 #define DMA_ERQ_ERQ2_MASK (0x4U) 01238 #define DMA_ERQ_ERQ2_SHIFT (2U) 01239 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) 01240 #define DMA_ERQ_ERQ3_MASK (0x8U) 01241 #define DMA_ERQ_ERQ3_SHIFT (3U) 01242 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) 01243 01244 /*! @name EEI - Enable Error Interrupt Register */ 01245 #define DMA_EEI_EEI0_MASK (0x1U) 01246 #define DMA_EEI_EEI0_SHIFT (0U) 01247 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) 01248 #define DMA_EEI_EEI1_MASK (0x2U) 01249 #define DMA_EEI_EEI1_SHIFT (1U) 01250 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) 01251 #define DMA_EEI_EEI2_MASK (0x4U) 01252 #define DMA_EEI_EEI2_SHIFT (2U) 01253 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) 01254 #define DMA_EEI_EEI3_MASK (0x8U) 01255 #define DMA_EEI_EEI3_SHIFT (3U) 01256 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) 01257 01258 /*! @name CEEI - Clear Enable Error Interrupt Register */ 01259 #define DMA_CEEI_CEEI_MASK (0xFU) 01260 #define DMA_CEEI_CEEI_SHIFT (0U) 01261 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) 01262 #define DMA_CEEI_CAEE_MASK (0x40U) 01263 #define DMA_CEEI_CAEE_SHIFT (6U) 01264 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) 01265 #define DMA_CEEI_NOP_MASK (0x80U) 01266 #define DMA_CEEI_NOP_SHIFT (7U) 01267 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) 01268 01269 /*! @name SEEI - Set Enable Error Interrupt Register */ 01270 #define DMA_SEEI_SEEI_MASK (0xFU) 01271 #define DMA_SEEI_SEEI_SHIFT (0U) 01272 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) 01273 #define DMA_SEEI_SAEE_MASK (0x40U) 01274 #define DMA_SEEI_SAEE_SHIFT (6U) 01275 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) 01276 #define DMA_SEEI_NOP_MASK (0x80U) 01277 #define DMA_SEEI_NOP_SHIFT (7U) 01278 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) 01279 01280 /*! @name CERQ - Clear Enable Request Register */ 01281 #define DMA_CERQ_CERQ_MASK (0xFU) 01282 #define DMA_CERQ_CERQ_SHIFT (0U) 01283 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) 01284 #define DMA_CERQ_CAER_MASK (0x40U) 01285 #define DMA_CERQ_CAER_SHIFT (6U) 01286 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) 01287 #define DMA_CERQ_NOP_MASK (0x80U) 01288 #define DMA_CERQ_NOP_SHIFT (7U) 01289 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) 01290 01291 /*! @name SERQ - Set Enable Request Register */ 01292 #define DMA_SERQ_SERQ_MASK (0xFU) 01293 #define DMA_SERQ_SERQ_SHIFT (0U) 01294 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) 01295 #define DMA_SERQ_SAER_MASK (0x40U) 01296 #define DMA_SERQ_SAER_SHIFT (6U) 01297 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) 01298 #define DMA_SERQ_NOP_MASK (0x80U) 01299 #define DMA_SERQ_NOP_SHIFT (7U) 01300 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) 01301 01302 /*! @name CDNE - Clear DONE Status Bit Register */ 01303 #define DMA_CDNE_CDNE_MASK (0xFU) 01304 #define DMA_CDNE_CDNE_SHIFT (0U) 01305 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) 01306 #define DMA_CDNE_CADN_MASK (0x40U) 01307 #define DMA_CDNE_CADN_SHIFT (6U) 01308 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) 01309 #define DMA_CDNE_NOP_MASK (0x80U) 01310 #define DMA_CDNE_NOP_SHIFT (7U) 01311 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) 01312 01313 /*! @name SSRT - Set START Bit Register */ 01314 #define DMA_SSRT_SSRT_MASK (0xFU) 01315 #define DMA_SSRT_SSRT_SHIFT (0U) 01316 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) 01317 #define DMA_SSRT_SAST_MASK (0x40U) 01318 #define DMA_SSRT_SAST_SHIFT (6U) 01319 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) 01320 #define DMA_SSRT_NOP_MASK (0x80U) 01321 #define DMA_SSRT_NOP_SHIFT (7U) 01322 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) 01323 01324 /*! @name CERR - Clear Error Register */ 01325 #define DMA_CERR_CERR_MASK (0xFU) 01326 #define DMA_CERR_CERR_SHIFT (0U) 01327 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) 01328 #define DMA_CERR_CAEI_MASK (0x40U) 01329 #define DMA_CERR_CAEI_SHIFT (6U) 01330 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) 01331 #define DMA_CERR_NOP_MASK (0x80U) 01332 #define DMA_CERR_NOP_SHIFT (7U) 01333 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) 01334 01335 /*! @name CINT - Clear Interrupt Request Register */ 01336 #define DMA_CINT_CINT_MASK (0xFU) 01337 #define DMA_CINT_CINT_SHIFT (0U) 01338 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) 01339 #define DMA_CINT_CAIR_MASK (0x40U) 01340 #define DMA_CINT_CAIR_SHIFT (6U) 01341 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) 01342 #define DMA_CINT_NOP_MASK (0x80U) 01343 #define DMA_CINT_NOP_SHIFT (7U) 01344 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) 01345 01346 /*! @name INT - Interrupt Request Register */ 01347 #define DMA_INT_INT0_MASK (0x1U) 01348 #define DMA_INT_INT0_SHIFT (0U) 01349 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) 01350 #define DMA_INT_INT1_MASK (0x2U) 01351 #define DMA_INT_INT1_SHIFT (1U) 01352 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) 01353 #define DMA_INT_INT2_MASK (0x4U) 01354 #define DMA_INT_INT2_SHIFT (2U) 01355 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) 01356 #define DMA_INT_INT3_MASK (0x8U) 01357 #define DMA_INT_INT3_SHIFT (3U) 01358 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) 01359 01360 /*! @name ERR - Error Register */ 01361 #define DMA_ERR_ERR0_MASK (0x1U) 01362 #define DMA_ERR_ERR0_SHIFT (0U) 01363 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) 01364 #define DMA_ERR_ERR1_MASK (0x2U) 01365 #define DMA_ERR_ERR1_SHIFT (1U) 01366 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) 01367 #define DMA_ERR_ERR2_MASK (0x4U) 01368 #define DMA_ERR_ERR2_SHIFT (2U) 01369 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) 01370 #define DMA_ERR_ERR3_MASK (0x8U) 01371 #define DMA_ERR_ERR3_SHIFT (3U) 01372 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) 01373 01374 /*! @name HRS - Hardware Request Status Register */ 01375 #define DMA_HRS_HRS0_MASK (0x1U) 01376 #define DMA_HRS_HRS0_SHIFT (0U) 01377 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) 01378 #define DMA_HRS_HRS1_MASK (0x2U) 01379 #define DMA_HRS_HRS1_SHIFT (1U) 01380 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) 01381 #define DMA_HRS_HRS2_MASK (0x4U) 01382 #define DMA_HRS_HRS2_SHIFT (2U) 01383 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) 01384 #define DMA_HRS_HRS3_MASK (0x8U) 01385 #define DMA_HRS_HRS3_SHIFT (3U) 01386 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) 01387 01388 /*! @name DCHPRI3 - Channel n Priority Register */ 01389 #define DMA_DCHPRI3_CHPRI_MASK (0xFU) 01390 #define DMA_DCHPRI3_CHPRI_SHIFT (0U) 01391 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) 01392 #define DMA_DCHPRI3_DPA_MASK (0x40U) 01393 #define DMA_DCHPRI3_DPA_SHIFT (6U) 01394 #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) 01395 #define DMA_DCHPRI3_ECP_MASK (0x80U) 01396 #define DMA_DCHPRI3_ECP_SHIFT (7U) 01397 #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) 01398 01399 /*! @name DCHPRI2 - Channel n Priority Register */ 01400 #define DMA_DCHPRI2_CHPRI_MASK (0xFU) 01401 #define DMA_DCHPRI2_CHPRI_SHIFT (0U) 01402 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) 01403 #define DMA_DCHPRI2_DPA_MASK (0x40U) 01404 #define DMA_DCHPRI2_DPA_SHIFT (6U) 01405 #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) 01406 #define DMA_DCHPRI2_ECP_MASK (0x80U) 01407 #define DMA_DCHPRI2_ECP_SHIFT (7U) 01408 #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) 01409 01410 /*! @name DCHPRI1 - Channel n Priority Register */ 01411 #define DMA_DCHPRI1_CHPRI_MASK (0xFU) 01412 #define DMA_DCHPRI1_CHPRI_SHIFT (0U) 01413 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) 01414 #define DMA_DCHPRI1_DPA_MASK (0x40U) 01415 #define DMA_DCHPRI1_DPA_SHIFT (6U) 01416 #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) 01417 #define DMA_DCHPRI1_ECP_MASK (0x80U) 01418 #define DMA_DCHPRI1_ECP_SHIFT (7U) 01419 #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) 01420 01421 /*! @name DCHPRI0 - Channel n Priority Register */ 01422 #define DMA_DCHPRI0_CHPRI_MASK (0xFU) 01423 #define DMA_DCHPRI0_CHPRI_SHIFT (0U) 01424 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) 01425 #define DMA_DCHPRI0_DPA_MASK (0x40U) 01426 #define DMA_DCHPRI0_DPA_SHIFT (6U) 01427 #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) 01428 #define DMA_DCHPRI0_ECP_MASK (0x80U) 01429 #define DMA_DCHPRI0_ECP_SHIFT (7U) 01430 #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) 01431 01432 /*! @name SADDR - TCD Source Address */ 01433 #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) 01434 #define DMA_SADDR_SADDR_SHIFT (0U) 01435 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) 01436 01437 /* The count of DMA_SADDR */ 01438 #define DMA_SADDR_COUNT (4U) 01439 01440 /*! @name SOFF - TCD Signed Source Address Offset */ 01441 #define DMA_SOFF_SOFF_MASK (0xFFFFU) 01442 #define DMA_SOFF_SOFF_SHIFT (0U) 01443 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) 01444 01445 /* The count of DMA_SOFF */ 01446 #define DMA_SOFF_COUNT (4U) 01447 01448 /*! @name ATTR - TCD Transfer Attributes */ 01449 #define DMA_ATTR_DSIZE_MASK (0x7U) 01450 #define DMA_ATTR_DSIZE_SHIFT (0U) 01451 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) 01452 #define DMA_ATTR_DMOD_MASK (0xF8U) 01453 #define DMA_ATTR_DMOD_SHIFT (3U) 01454 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) 01455 #define DMA_ATTR_SSIZE_MASK (0x700U) 01456 #define DMA_ATTR_SSIZE_SHIFT (8U) 01457 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) 01458 #define DMA_ATTR_SMOD_MASK (0xF800U) 01459 #define DMA_ATTR_SMOD_SHIFT (11U) 01460 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) 01461 01462 /* The count of DMA_ATTR */ 01463 #define DMA_ATTR_COUNT (4U) 01464 01465 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */ 01466 #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) 01467 #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) 01468 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) 01469 01470 /* The count of DMA_NBYTES_MLNO */ 01471 #define DMA_NBYTES_MLNO_COUNT (4U) 01472 01473 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */ 01474 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 01475 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 01476 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) 01477 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 01478 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 01479 #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) 01480 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 01481 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 01482 #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) 01483 01484 /* The count of DMA_NBYTES_MLOFFNO */ 01485 #define DMA_NBYTES_MLOFFNO_COUNT (4U) 01486 01487 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */ 01488 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 01489 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 01490 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) 01491 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 01492 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 01493 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) 01494 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 01495 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 01496 #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) 01497 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 01498 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 01499 #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) 01500 01501 /* The count of DMA_NBYTES_MLOFFYES */ 01502 #define DMA_NBYTES_MLOFFYES_COUNT (4U) 01503 01504 /*! @name SLAST - TCD Last Source Address Adjustment */ 01505 #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) 01506 #define DMA_SLAST_SLAST_SHIFT (0U) 01507 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) 01508 01509 /* The count of DMA_SLAST */ 01510 #define DMA_SLAST_COUNT (4U) 01511 01512 /*! @name DADDR - TCD Destination Address */ 01513 #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) 01514 #define DMA_DADDR_DADDR_SHIFT (0U) 01515 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) 01516 01517 /* The count of DMA_DADDR */ 01518 #define DMA_DADDR_COUNT (4U) 01519 01520 /*! @name DOFF - TCD Signed Destination Address Offset */ 01521 #define DMA_DOFF_DOFF_MASK (0xFFFFU) 01522 #define DMA_DOFF_DOFF_SHIFT (0U) 01523 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) 01524 01525 /* The count of DMA_DOFF */ 01526 #define DMA_DOFF_COUNT (4U) 01527 01528 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ 01529 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) 01530 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U) 01531 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) 01532 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) 01533 #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) 01534 #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) 01535 01536 /* The count of DMA_CITER_ELINKNO */ 01537 #define DMA_CITER_ELINKNO_COUNT (4U) 01538 01539 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ 01540 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) 01541 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U) 01542 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) 01543 #define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U) 01544 #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) 01545 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) 01546 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) 01547 #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) 01548 #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) 01549 01550 /* The count of DMA_CITER_ELINKYES */ 01551 #define DMA_CITER_ELINKYES_COUNT (4U) 01552 01553 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ 01554 #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) 01555 #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) 01556 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) 01557 01558 /* The count of DMA_DLAST_SGA */ 01559 #define DMA_DLAST_SGA_COUNT (4U) 01560 01561 /*! @name CSR - TCD Control and Status */ 01562 #define DMA_CSR_START_MASK (0x1U) 01563 #define DMA_CSR_START_SHIFT (0U) 01564 #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) 01565 #define DMA_CSR_INTMAJOR_MASK (0x2U) 01566 #define DMA_CSR_INTMAJOR_SHIFT (1U) 01567 #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) 01568 #define DMA_CSR_INTHALF_MASK (0x4U) 01569 #define DMA_CSR_INTHALF_SHIFT (2U) 01570 #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) 01571 #define DMA_CSR_DREQ_MASK (0x8U) 01572 #define DMA_CSR_DREQ_SHIFT (3U) 01573 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) 01574 #define DMA_CSR_ESG_MASK (0x10U) 01575 #define DMA_CSR_ESG_SHIFT (4U) 01576 #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) 01577 #define DMA_CSR_MAJORELINK_MASK (0x20U) 01578 #define DMA_CSR_MAJORELINK_SHIFT (5U) 01579 #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) 01580 #define DMA_CSR_ACTIVE_MASK (0x40U) 01581 #define DMA_CSR_ACTIVE_SHIFT (6U) 01582 #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) 01583 #define DMA_CSR_DONE_MASK (0x80U) 01584 #define DMA_CSR_DONE_SHIFT (7U) 01585 #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) 01586 #define DMA_CSR_MAJORLINKCH_MASK (0xF00U) 01587 #define DMA_CSR_MAJORLINKCH_SHIFT (8U) 01588 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) 01589 #define DMA_CSR_BWC_MASK (0xC000U) 01590 #define DMA_CSR_BWC_SHIFT (14U) 01591 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) 01592 01593 /* The count of DMA_CSR */ 01594 #define DMA_CSR_COUNT (4U) 01595 01596 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ 01597 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) 01598 #define DMA_BITER_ELINKNO_BITER_SHIFT (0U) 01599 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) 01600 #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) 01601 #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) 01602 #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) 01603 01604 /* The count of DMA_BITER_ELINKNO */ 01605 #define DMA_BITER_ELINKNO_COUNT (4U) 01606 01607 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ 01608 #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) 01609 #define DMA_BITER_ELINKYES_BITER_SHIFT (0U) 01610 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) 01611 #define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U) 01612 #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) 01613 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) 01614 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) 01615 #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) 01616 #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) 01617 01618 /* The count of DMA_BITER_ELINKYES */ 01619 #define DMA_BITER_ELINKYES_COUNT (4U) 01620 01621 01622 /*! 01623 * @} 01624 */ /* end of group DMA_Register_Masks */ 01625 01626 01627 /* DMA - Peripheral instance base addresses */ 01628 /** Peripheral DMA base address */ 01629 #define DMA_BASE (0x40008000u) 01630 /** Peripheral DMA base pointer */ 01631 #define DMA0 ((DMA_Type *)DMA_BASE) 01632 /** Array initializer of DMA peripheral base addresses */ 01633 #define DMA_BASE_ADDRS { DMA_BASE } 01634 /** Array initializer of DMA peripheral base pointers */ 01635 #define DMA_BASE_PTRS { DMA0 } 01636 /** Interrupt vectors for the DMA peripheral type */ 01637 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } 01638 #define DMA_ERROR_IRQS { DMA_Error_IRQn } 01639 01640 /*! 01641 * @} 01642 */ /* end of group DMA_Peripheral_Access_Layer */ 01643 01644 01645 /* ---------------------------------------------------------------------------- 01646 -- DMAMUX Peripheral Access Layer 01647 ---------------------------------------------------------------------------- */ 01648 01649 /*! 01650 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer 01651 * @{ 01652 */ 01653 01654 /** DMAMUX - Register Layout Typedef */ 01655 typedef struct { 01656 __IO uint8_t CHCFG[4]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */ 01657 } DMAMUX_Type; 01658 01659 /* ---------------------------------------------------------------------------- 01660 -- DMAMUX Register Masks 01661 ---------------------------------------------------------------------------- */ 01662 01663 /*! 01664 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks 01665 * @{ 01666 */ 01667 01668 /*! @name CHCFG - Channel Configuration Register */ 01669 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) 01670 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) 01671 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) 01672 #define DMAMUX_CHCFG_TRIG_MASK (0x40U) 01673 #define DMAMUX_CHCFG_TRIG_SHIFT (6U) 01674 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) 01675 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) 01676 #define DMAMUX_CHCFG_ENBL_SHIFT (7U) 01677 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) 01678 01679 /* The count of DMAMUX_CHCFG */ 01680 #define DMAMUX_CHCFG_COUNT (4U) 01681 01682 01683 /*! 01684 * @} 01685 */ /* end of group DMAMUX_Register_Masks */ 01686 01687 01688 /* DMAMUX - Peripheral instance base addresses */ 01689 /** Peripheral DMAMUX base address */ 01690 #define DMAMUX_BASE (0x40021000u) 01691 /** Peripheral DMAMUX base pointer */ 01692 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) 01693 /** Array initializer of DMAMUX peripheral base addresses */ 01694 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE } 01695 /** Array initializer of DMAMUX peripheral base pointers */ 01696 #define DMAMUX_BASE_PTRS { DMAMUX } 01697 01698 /*! 01699 * @} 01700 */ /* end of group DMAMUX_Peripheral_Access_Layer */ 01701 01702 01703 /* ---------------------------------------------------------------------------- 01704 -- EWM Peripheral Access Layer 01705 ---------------------------------------------------------------------------- */ 01706 01707 /*! 01708 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer 01709 * @{ 01710 */ 01711 01712 /** EWM - Register Layout Typedef */ 01713 typedef struct { 01714 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ 01715 __O uint8_t SERV; /**< Service Register, offset: 0x1 */ 01716 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ 01717 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ 01718 } EWM_Type; 01719 01720 /* ---------------------------------------------------------------------------- 01721 -- EWM Register Masks 01722 ---------------------------------------------------------------------------- */ 01723 01724 /*! 01725 * @addtogroup EWM_Register_Masks EWM Register Masks 01726 * @{ 01727 */ 01728 01729 /*! @name CTRL - Control Register */ 01730 #define EWM_CTRL_EWMEN_MASK (0x1U) 01731 #define EWM_CTRL_EWMEN_SHIFT (0U) 01732 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) 01733 #define EWM_CTRL_ASSIN_MASK (0x2U) 01734 #define EWM_CTRL_ASSIN_SHIFT (1U) 01735 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) 01736 #define EWM_CTRL_INEN_MASK (0x4U) 01737 #define EWM_CTRL_INEN_SHIFT (2U) 01738 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) 01739 #define EWM_CTRL_INTEN_MASK (0x8U) 01740 #define EWM_CTRL_INTEN_SHIFT (3U) 01741 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) 01742 01743 /*! @name SERV - Service Register */ 01744 #define EWM_SERV_SERVICE_MASK (0xFFU) 01745 #define EWM_SERV_SERVICE_SHIFT (0U) 01746 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) 01747 01748 /*! @name CMPL - Compare Low Register */ 01749 #define EWM_CMPL_COMPAREL_MASK (0xFFU) 01750 #define EWM_CMPL_COMPAREL_SHIFT (0U) 01751 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) 01752 01753 /*! @name CMPH - Compare High Register */ 01754 #define EWM_CMPH_COMPAREH_MASK (0xFFU) 01755 #define EWM_CMPH_COMPAREH_SHIFT (0U) 01756 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) 01757 01758 01759 /*! 01760 * @} 01761 */ /* end of group EWM_Register_Masks */ 01762 01763 01764 /* EWM - Peripheral instance base addresses */ 01765 /** Peripheral EWM base address */ 01766 #define EWM_BASE (0x40061000u) 01767 /** Peripheral EWM base pointer */ 01768 #define EWM ((EWM_Type *)EWM_BASE) 01769 /** Array initializer of EWM peripheral base addresses */ 01770 #define EWM_BASE_ADDRS { EWM_BASE } 01771 /** Array initializer of EWM peripheral base pointers */ 01772 #define EWM_BASE_PTRS { EWM } 01773 /** Interrupt vectors for the EWM peripheral type */ 01774 #define EWM_IRQS { Watchdog_IRQn } 01775 01776 /*! 01777 * @} 01778 */ /* end of group EWM_Peripheral_Access_Layer */ 01779 01780 01781 /* ---------------------------------------------------------------------------- 01782 -- FMC Peripheral Access Layer 01783 ---------------------------------------------------------------------------- */ 01784 01785 /*! 01786 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer 01787 * @{ 01788 */ 01789 01790 /** FMC - Register Layout Typedef */ 01791 typedef struct { 01792 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */ 01793 __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */ 01794 uint8_t RESERVED_0[248]; 01795 struct { /* offset: 0x100, array step: 0x20 */ 01796 __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */ 01797 uint8_t RESERVED_0[24]; 01798 } TAG_WAY[4]; 01799 uint8_t RESERVED_1[132]; 01800 struct { /* offset: 0x204, array step: 0x8 */ 01801 __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */ 01802 uint8_t RESERVED_0[4]; 01803 } DATAW0S[2]; 01804 uint8_t RESERVED_2[48]; 01805 struct { /* offset: 0x244, array step: 0x8 */ 01806 __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */ 01807 uint8_t RESERVED_0[4]; 01808 } DATAW1S[2]; 01809 uint8_t RESERVED_3[48]; 01810 struct { /* offset: 0x284, array step: 0x8 */ 01811 __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */ 01812 uint8_t RESERVED_0[4]; 01813 } DATAW2S[2]; 01814 uint8_t RESERVED_4[48]; 01815 struct { /* offset: 0x2C4, array step: 0x8 */ 01816 __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */ 01817 uint8_t RESERVED_0[4]; 01818 } DATAW3S[2]; 01819 } FMC_Type; 01820 01821 /* ---------------------------------------------------------------------------- 01822 -- FMC Register Masks 01823 ---------------------------------------------------------------------------- */ 01824 01825 /*! 01826 * @addtogroup FMC_Register_Masks FMC Register Masks 01827 * @{ 01828 */ 01829 01830 /*! @name PFAPR - Flash Access Protection Register */ 01831 #define FMC_PFAPR_M0AP_MASK (0x3U) 01832 #define FMC_PFAPR_M0AP_SHIFT (0U) 01833 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK) 01834 #define FMC_PFAPR_M1AP_MASK (0xCU) 01835 #define FMC_PFAPR_M1AP_SHIFT (2U) 01836 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK) 01837 #define FMC_PFAPR_M2AP_MASK (0x30U) 01838 #define FMC_PFAPR_M2AP_SHIFT (4U) 01839 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK) 01840 #define FMC_PFAPR_M3AP_MASK (0xC0U) 01841 #define FMC_PFAPR_M3AP_SHIFT (6U) 01842 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK) 01843 #define FMC_PFAPR_M0PFD_MASK (0x10000U) 01844 #define FMC_PFAPR_M0PFD_SHIFT (16U) 01845 #define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK) 01846 #define FMC_PFAPR_M1PFD_MASK (0x20000U) 01847 #define FMC_PFAPR_M1PFD_SHIFT (17U) 01848 #define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK) 01849 #define FMC_PFAPR_M2PFD_MASK (0x40000U) 01850 #define FMC_PFAPR_M2PFD_SHIFT (18U) 01851 #define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK) 01852 #define FMC_PFAPR_M3PFD_MASK (0x80000U) 01853 #define FMC_PFAPR_M3PFD_SHIFT (19U) 01854 #define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK) 01855 01856 /*! @name PFB0CR - Flash Control Register */ 01857 #define FMC_PFB0CR_B0SEBE_MASK (0x1U) 01858 #define FMC_PFB0CR_B0SEBE_SHIFT (0U) 01859 #define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK) 01860 #define FMC_PFB0CR_B0IPE_MASK (0x2U) 01861 #define FMC_PFB0CR_B0IPE_SHIFT (1U) 01862 #define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK) 01863 #define FMC_PFB0CR_B0DPE_MASK (0x4U) 01864 #define FMC_PFB0CR_B0DPE_SHIFT (2U) 01865 #define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK) 01866 #define FMC_PFB0CR_B0ICE_MASK (0x8U) 01867 #define FMC_PFB0CR_B0ICE_SHIFT (3U) 01868 #define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK) 01869 #define FMC_PFB0CR_B0DCE_MASK (0x10U) 01870 #define FMC_PFB0CR_B0DCE_SHIFT (4U) 01871 #define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK) 01872 #define FMC_PFB0CR_CRC_MASK (0xE0U) 01873 #define FMC_PFB0CR_CRC_SHIFT (5U) 01874 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK) 01875 #define FMC_PFB0CR_B0MW_MASK (0x60000U) 01876 #define FMC_PFB0CR_B0MW_SHIFT (17U) 01877 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK) 01878 #define FMC_PFB0CR_S_B_INV_MASK (0x80000U) 01879 #define FMC_PFB0CR_S_B_INV_SHIFT (19U) 01880 #define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK) 01881 #define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U) 01882 #define FMC_PFB0CR_CINV_WAY_SHIFT (20U) 01883 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK) 01884 #define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U) 01885 #define FMC_PFB0CR_CLCK_WAY_SHIFT (24U) 01886 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK) 01887 #define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U) 01888 #define FMC_PFB0CR_B0RWSC_SHIFT (28U) 01889 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK) 01890 01891 /*! @name TAGVD - Cache Tag Storage */ 01892 #define FMC_TAGVD_valid_MASK (0x1U) 01893 #define FMC_TAGVD_valid_SHIFT (0U) 01894 #define FMC_TAGVD_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_valid_SHIFT)) & FMC_TAGVD_valid_MASK) 01895 #define FMC_TAGVD_tag_MASK (0x7FFC0U) 01896 #define FMC_TAGVD_tag_SHIFT (6U) 01897 #define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_tag_SHIFT)) & FMC_TAGVD_tag_MASK) 01898 01899 /* The count of FMC_TAGVD */ 01900 #define FMC_TAGVD_COUNT (4U) 01901 01902 /* The count of FMC_TAGVD */ 01903 #define FMC_TAGVD_COUNT2 (2U) 01904 01905 /*! @name DATAW0S - Cache Data Storage */ 01906 #define FMC_DATAW0S_data_MASK (0xFFFFFFFFU) 01907 #define FMC_DATAW0S_data_SHIFT (0U) 01908 #define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATAW0S_data_SHIFT)) & FMC_DATAW0S_data_MASK) 01909 01910 /* The count of FMC_DATAW0S */ 01911 #define FMC_DATAW0S_COUNT (2U) 01912 01913 /*! @name DATAW1S - Cache Data Storage */ 01914 #define FMC_DATAW1S_data_MASK (0xFFFFFFFFU) 01915 #define FMC_DATAW1S_data_SHIFT (0U) 01916 #define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATAW1S_data_SHIFT)) & FMC_DATAW1S_data_MASK) 01917 01918 /* The count of FMC_DATAW1S */ 01919 #define FMC_DATAW1S_COUNT (2U) 01920 01921 /*! @name DATAW2S - Cache Data Storage */ 01922 #define FMC_DATAW2S_data_MASK (0xFFFFFFFFU) 01923 #define FMC_DATAW2S_data_SHIFT (0U) 01924 #define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATAW2S_data_SHIFT)) & FMC_DATAW2S_data_MASK) 01925 01926 /* The count of FMC_DATAW2S */ 01927 #define FMC_DATAW2S_COUNT (2U) 01928 01929 /*! @name DATAW3S - Cache Data Storage */ 01930 #define FMC_DATAW3S_data_MASK (0xFFFFFFFFU) 01931 #define FMC_DATAW3S_data_SHIFT (0U) 01932 #define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATAW3S_data_SHIFT)) & FMC_DATAW3S_data_MASK) 01933 01934 /* The count of FMC_DATAW3S */ 01935 #define FMC_DATAW3S_COUNT (2U) 01936 01937 01938 /*! 01939 * @} 01940 */ /* end of group FMC_Register_Masks */ 01941 01942 01943 /* FMC - Peripheral instance base addresses */ 01944 /** Peripheral FMC base address */ 01945 #define FMC_BASE (0x4001F000u) 01946 /** Peripheral FMC base pointer */ 01947 #define FMC ((FMC_Type *)FMC_BASE) 01948 /** Array initializer of FMC peripheral base addresses */ 01949 #define FMC_BASE_ADDRS { FMC_BASE } 01950 /** Array initializer of FMC peripheral base pointers */ 01951 #define FMC_BASE_PTRS { FMC } 01952 01953 /*! 01954 * @} 01955 */ /* end of group FMC_Peripheral_Access_Layer */ 01956 01957 01958 /* ---------------------------------------------------------------------------- 01959 -- FTFL Peripheral Access Layer 01960 ---------------------------------------------------------------------------- */ 01961 01962 /*! 01963 * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer 01964 * @{ 01965 */ 01966 01967 /** FTFL - Register Layout Typedef */ 01968 typedef struct { 01969 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ 01970 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ 01971 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ 01972 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ 01973 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ 01974 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ 01975 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ 01976 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ 01977 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ 01978 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ 01979 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ 01980 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ 01981 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ 01982 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ 01983 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ 01984 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ 01985 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ 01986 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ 01987 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ 01988 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ 01989 uint8_t RESERVED_0[2]; 01990 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */ 01991 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */ 01992 } FTFL_Type; 01993 01994 /* ---------------------------------------------------------------------------- 01995 -- FTFL Register Masks 01996 ---------------------------------------------------------------------------- */ 01997 01998 /*! 01999 * @addtogroup FTFL_Register_Masks FTFL Register Masks 02000 * @{ 02001 */ 02002 02003 /*! @name FSTAT - Flash Status Register */ 02004 #define FTFL_FSTAT_MGSTAT0_MASK (0x1U) 02005 #define FTFL_FSTAT_MGSTAT0_SHIFT (0U) 02006 #define FTFL_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_MGSTAT0_SHIFT)) & FTFL_FSTAT_MGSTAT0_MASK) 02007 #define FTFL_FSTAT_FPVIOL_MASK (0x10U) 02008 #define FTFL_FSTAT_FPVIOL_SHIFT (4U) 02009 #define FTFL_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_FPVIOL_SHIFT)) & FTFL_FSTAT_FPVIOL_MASK) 02010 #define FTFL_FSTAT_ACCERR_MASK (0x20U) 02011 #define FTFL_FSTAT_ACCERR_SHIFT (5U) 02012 #define FTFL_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_ACCERR_SHIFT)) & FTFL_FSTAT_ACCERR_MASK) 02013 #define FTFL_FSTAT_RDCOLERR_MASK (0x40U) 02014 #define FTFL_FSTAT_RDCOLERR_SHIFT (6U) 02015 #define FTFL_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_RDCOLERR_SHIFT)) & FTFL_FSTAT_RDCOLERR_MASK) 02016 #define FTFL_FSTAT_CCIF_MASK (0x80U) 02017 #define FTFL_FSTAT_CCIF_SHIFT (7U) 02018 #define FTFL_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_CCIF_SHIFT)) & FTFL_FSTAT_CCIF_MASK) 02019 02020 /*! @name FCNFG - Flash Configuration Register */ 02021 #define FTFL_FCNFG_EEERDY_MASK (0x1U) 02022 #define FTFL_FCNFG_EEERDY_SHIFT (0U) 02023 #define FTFL_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_EEERDY_SHIFT)) & FTFL_FCNFG_EEERDY_MASK) 02024 #define FTFL_FCNFG_RAMRDY_MASK (0x2U) 02025 #define FTFL_FCNFG_RAMRDY_SHIFT (1U) 02026 #define FTFL_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_RAMRDY_SHIFT)) & FTFL_FCNFG_RAMRDY_MASK) 02027 #define FTFL_FCNFG_PFLSH_MASK (0x4U) 02028 #define FTFL_FCNFG_PFLSH_SHIFT (2U) 02029 #define FTFL_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_PFLSH_SHIFT)) & FTFL_FCNFG_PFLSH_MASK) 02030 #define FTFL_FCNFG_ERSSUSP_MASK (0x10U) 02031 #define FTFL_FCNFG_ERSSUSP_SHIFT (4U) 02032 #define FTFL_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_ERSSUSP_SHIFT)) & FTFL_FCNFG_ERSSUSP_MASK) 02033 #define FTFL_FCNFG_ERSAREQ_MASK (0x20U) 02034 #define FTFL_FCNFG_ERSAREQ_SHIFT (5U) 02035 #define FTFL_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_ERSAREQ_SHIFT)) & FTFL_FCNFG_ERSAREQ_MASK) 02036 #define FTFL_FCNFG_RDCOLLIE_MASK (0x40U) 02037 #define FTFL_FCNFG_RDCOLLIE_SHIFT (6U) 02038 #define FTFL_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_RDCOLLIE_SHIFT)) & FTFL_FCNFG_RDCOLLIE_MASK) 02039 #define FTFL_FCNFG_CCIE_MASK (0x80U) 02040 #define FTFL_FCNFG_CCIE_SHIFT (7U) 02041 #define FTFL_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_CCIE_SHIFT)) & FTFL_FCNFG_CCIE_MASK) 02042 02043 /*! @name FSEC - Flash Security Register */ 02044 #define FTFL_FSEC_SEC_MASK (0x3U) 02045 #define FTFL_FSEC_SEC_SHIFT (0U) 02046 #define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_SEC_SHIFT)) & FTFL_FSEC_SEC_MASK) 02047 #define FTFL_FSEC_FSLACC_MASK (0xCU) 02048 #define FTFL_FSEC_FSLACC_SHIFT (2U) 02049 #define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_FSLACC_SHIFT)) & FTFL_FSEC_FSLACC_MASK) 02050 #define FTFL_FSEC_MEEN_MASK (0x30U) 02051 #define FTFL_FSEC_MEEN_SHIFT (4U) 02052 #define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_MEEN_SHIFT)) & FTFL_FSEC_MEEN_MASK) 02053 #define FTFL_FSEC_KEYEN_MASK (0xC0U) 02054 #define FTFL_FSEC_KEYEN_SHIFT (6U) 02055 #define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_KEYEN_SHIFT)) & FTFL_FSEC_KEYEN_MASK) 02056 02057 /*! @name FOPT - Flash Option Register */ 02058 #define FTFL_FOPT_OPT_MASK (0xFFU) 02059 #define FTFL_FOPT_OPT_SHIFT (0U) 02060 #define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FOPT_OPT_SHIFT)) & FTFL_FOPT_OPT_MASK) 02061 02062 /*! @name FCCOB3 - Flash Common Command Object Registers */ 02063 #define FTFL_FCCOB3_CCOBn_MASK (0xFFU) 02064 #define FTFL_FCCOB3_CCOBn_SHIFT (0U) 02065 #define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB3_CCOBn_SHIFT)) & FTFL_FCCOB3_CCOBn_MASK) 02066 02067 /*! @name FCCOB2 - Flash Common Command Object Registers */ 02068 #define FTFL_FCCOB2_CCOBn_MASK (0xFFU) 02069 #define FTFL_FCCOB2_CCOBn_SHIFT (0U) 02070 #define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB2_CCOBn_SHIFT)) & FTFL_FCCOB2_CCOBn_MASK) 02071 02072 /*! @name FCCOB1 - Flash Common Command Object Registers */ 02073 #define FTFL_FCCOB1_CCOBn_MASK (0xFFU) 02074 #define FTFL_FCCOB1_CCOBn_SHIFT (0U) 02075 #define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB1_CCOBn_SHIFT)) & FTFL_FCCOB1_CCOBn_MASK) 02076 02077 /*! @name FCCOB0 - Flash Common Command Object Registers */ 02078 #define FTFL_FCCOB0_CCOBn_MASK (0xFFU) 02079 #define FTFL_FCCOB0_CCOBn_SHIFT (0U) 02080 #define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB0_CCOBn_SHIFT)) & FTFL_FCCOB0_CCOBn_MASK) 02081 02082 /*! @name FCCOB7 - Flash Common Command Object Registers */ 02083 #define FTFL_FCCOB7_CCOBn_MASK (0xFFU) 02084 #define FTFL_FCCOB7_CCOBn_SHIFT (0U) 02085 #define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB7_CCOBn_SHIFT)) & FTFL_FCCOB7_CCOBn_MASK) 02086 02087 /*! @name FCCOB6 - Flash Common Command Object Registers */ 02088 #define FTFL_FCCOB6_CCOBn_MASK (0xFFU) 02089 #define FTFL_FCCOB6_CCOBn_SHIFT (0U) 02090 #define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB6_CCOBn_SHIFT)) & FTFL_FCCOB6_CCOBn_MASK) 02091 02092 /*! @name FCCOB5 - Flash Common Command Object Registers */ 02093 #define FTFL_FCCOB5_CCOBn_MASK (0xFFU) 02094 #define FTFL_FCCOB5_CCOBn_SHIFT (0U) 02095 #define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB5_CCOBn_SHIFT)) & FTFL_FCCOB5_CCOBn_MASK) 02096 02097 /*! @name FCCOB4 - Flash Common Command Object Registers */ 02098 #define FTFL_FCCOB4_CCOBn_MASK (0xFFU) 02099 #define FTFL_FCCOB4_CCOBn_SHIFT (0U) 02100 #define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB4_CCOBn_SHIFT)) & FTFL_FCCOB4_CCOBn_MASK) 02101 02102 /*! @name FCCOBB - Flash Common Command Object Registers */ 02103 #define FTFL_FCCOBB_CCOBn_MASK (0xFFU) 02104 #define FTFL_FCCOBB_CCOBn_SHIFT (0U) 02105 #define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOBB_CCOBn_SHIFT)) & FTFL_FCCOBB_CCOBn_MASK) 02106 02107 /*! @name FCCOBA - Flash Common Command Object Registers */ 02108 #define FTFL_FCCOBA_CCOBn_MASK (0xFFU) 02109 #define FTFL_FCCOBA_CCOBn_SHIFT (0U) 02110 #define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOBA_CCOBn_SHIFT)) & FTFL_FCCOBA_CCOBn_MASK) 02111 02112 /*! @name FCCOB9 - Flash Common Command Object Registers */ 02113 #define FTFL_FCCOB9_CCOBn_MASK (0xFFU) 02114 #define FTFL_FCCOB9_CCOBn_SHIFT (0U) 02115 #define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB9_CCOBn_SHIFT)) & FTFL_FCCOB9_CCOBn_MASK) 02116 02117 /*! @name FCCOB8 - Flash Common Command Object Registers */ 02118 #define FTFL_FCCOB8_CCOBn_MASK (0xFFU) 02119 #define FTFL_FCCOB8_CCOBn_SHIFT (0U) 02120 #define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB8_CCOBn_SHIFT)) & FTFL_FCCOB8_CCOBn_MASK) 02121 02122 /*! @name FPROT3 - Program Flash Protection Registers */ 02123 #define FTFL_FPROT3_PROT_MASK (0xFFU) 02124 #define FTFL_FPROT3_PROT_SHIFT (0U) 02125 #define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT3_PROT_SHIFT)) & FTFL_FPROT3_PROT_MASK) 02126 02127 /*! @name FPROT2 - Program Flash Protection Registers */ 02128 #define FTFL_FPROT2_PROT_MASK (0xFFU) 02129 #define FTFL_FPROT2_PROT_SHIFT (0U) 02130 #define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT2_PROT_SHIFT)) & FTFL_FPROT2_PROT_MASK) 02131 02132 /*! @name FPROT1 - Program Flash Protection Registers */ 02133 #define FTFL_FPROT1_PROT_MASK (0xFFU) 02134 #define FTFL_FPROT1_PROT_SHIFT (0U) 02135 #define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT1_PROT_SHIFT)) & FTFL_FPROT1_PROT_MASK) 02136 02137 /*! @name FPROT0 - Program Flash Protection Registers */ 02138 #define FTFL_FPROT0_PROT_MASK (0xFFU) 02139 #define FTFL_FPROT0_PROT_SHIFT (0U) 02140 #define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT0_PROT_SHIFT)) & FTFL_FPROT0_PROT_MASK) 02141 02142 /*! @name FEPROT - EEPROM Protection Register */ 02143 #define FTFL_FEPROT_EPROT_MASK (0xFFU) 02144 #define FTFL_FEPROT_EPROT_SHIFT (0U) 02145 #define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FEPROT_EPROT_SHIFT)) & FTFL_FEPROT_EPROT_MASK) 02146 02147 /*! @name FDPROT - Data Flash Protection Register */ 02148 #define FTFL_FDPROT_DPROT_MASK (0xFFU) 02149 #define FTFL_FDPROT_DPROT_SHIFT (0U) 02150 #define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FDPROT_DPROT_SHIFT)) & FTFL_FDPROT_DPROT_MASK) 02151 02152 02153 /*! 02154 * @} 02155 */ /* end of group FTFL_Register_Masks */ 02156 02157 02158 /* FTFL - Peripheral instance base addresses */ 02159 /** Peripheral FTFL base address */ 02160 #define FTFL_BASE (0x40020000u) 02161 /** Peripheral FTFL base pointer */ 02162 #define FTFL ((FTFL_Type *)FTFL_BASE) 02163 /** Array initializer of FTFL peripheral base addresses */ 02164 #define FTFL_BASE_ADDRS { FTFL_BASE } 02165 /** Array initializer of FTFL peripheral base pointers */ 02166 #define FTFL_BASE_PTRS { FTFL } 02167 /** Interrupt vectors for the FTFL peripheral type */ 02168 #define FTFL_COMMAND_COMPLETE_IRQS { FTFL_IRQn } 02169 #define FTFL_READ_COLLISION_IRQS { Read_Collision_IRQn } 02170 02171 /*! 02172 * @} 02173 */ /* end of group FTFL_Peripheral_Access_Layer */ 02174 02175 02176 /* ---------------------------------------------------------------------------- 02177 -- FTM Peripheral Access Layer 02178 ---------------------------------------------------------------------------- */ 02179 02180 /*! 02181 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer 02182 * @{ 02183 */ 02184 02185 /** FTM - Register Layout Typedef */ 02186 typedef struct { 02187 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */ 02188 __IO uint32_t CNT; /**< Counter, offset: 0x4 */ 02189 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ 02190 struct { /* offset: 0xC, array step: 0x8 */ 02191 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ 02192 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ 02193 } CONTROLS[8]; 02194 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ 02195 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ 02196 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ 02197 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ 02198 __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */ 02199 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ 02200 __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */ 02201 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ 02202 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ 02203 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ 02204 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ 02205 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ 02206 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ 02207 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */ 02208 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ 02209 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ 02210 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ 02211 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ 02212 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ 02213 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ 02214 } FTM_Type; 02215 02216 /* ---------------------------------------------------------------------------- 02217 -- FTM Register Masks 02218 ---------------------------------------------------------------------------- */ 02219 02220 /*! 02221 * @addtogroup FTM_Register_Masks FTM Register Masks 02222 * @{ 02223 */ 02224 02225 /*! @name SC - Status and Control */ 02226 #define FTM_SC_PS_MASK (0x7U) 02227 #define FTM_SC_PS_SHIFT (0U) 02228 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) 02229 #define FTM_SC_CLKS_MASK (0x18U) 02230 #define FTM_SC_CLKS_SHIFT (3U) 02231 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) 02232 #define FTM_SC_CPWMS_MASK (0x20U) 02233 #define FTM_SC_CPWMS_SHIFT (5U) 02234 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) 02235 #define FTM_SC_TOIE_MASK (0x40U) 02236 #define FTM_SC_TOIE_SHIFT (6U) 02237 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) 02238 #define FTM_SC_TOF_MASK (0x80U) 02239 #define FTM_SC_TOF_SHIFT (7U) 02240 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) 02241 02242 /*! @name CNT - Counter */ 02243 #define FTM_CNT_COUNT_MASK (0xFFFFU) 02244 #define FTM_CNT_COUNT_SHIFT (0U) 02245 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) 02246 02247 /*! @name MOD - Modulo */ 02248 #define FTM_MOD_MOD_MASK (0xFFFFU) 02249 #define FTM_MOD_MOD_SHIFT (0U) 02250 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) 02251 02252 /*! @name CnSC - Channel (n) Status and Control */ 02253 #define FTM_CnSC_DMA_MASK (0x1U) 02254 #define FTM_CnSC_DMA_SHIFT (0U) 02255 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK) 02256 #define FTM_CnSC_ELSA_MASK (0x4U) 02257 #define FTM_CnSC_ELSA_SHIFT (2U) 02258 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) 02259 #define FTM_CnSC_ELSB_MASK (0x8U) 02260 #define FTM_CnSC_ELSB_SHIFT (3U) 02261 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) 02262 #define FTM_CnSC_MSA_MASK (0x10U) 02263 #define FTM_CnSC_MSA_SHIFT (4U) 02264 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) 02265 #define FTM_CnSC_MSB_MASK (0x20U) 02266 #define FTM_CnSC_MSB_SHIFT (5U) 02267 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) 02268 #define FTM_CnSC_CHIE_MASK (0x40U) 02269 #define FTM_CnSC_CHIE_SHIFT (6U) 02270 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) 02271 #define FTM_CnSC_CHF_MASK (0x80U) 02272 #define FTM_CnSC_CHF_SHIFT (7U) 02273 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) 02274 02275 /* The count of FTM_CnSC */ 02276 #define FTM_CnSC_COUNT (8U) 02277 02278 /*! @name CnV - Channel (n) Value */ 02279 #define FTM_CnV_VAL_MASK (0xFFFFU) 02280 #define FTM_CnV_VAL_SHIFT (0U) 02281 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) 02282 02283 /* The count of FTM_CnV */ 02284 #define FTM_CnV_COUNT (8U) 02285 02286 /*! @name CNTIN - Counter Initial Value */ 02287 #define FTM_CNTIN_INIT_MASK (0xFFFFU) 02288 #define FTM_CNTIN_INIT_SHIFT (0U) 02289 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) 02290 02291 /*! @name STATUS - Capture and Compare Status */ 02292 #define FTM_STATUS_CH0F_MASK (0x1U) 02293 #define FTM_STATUS_CH0F_SHIFT (0U) 02294 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) 02295 #define FTM_STATUS_CH1F_MASK (0x2U) 02296 #define FTM_STATUS_CH1F_SHIFT (1U) 02297 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) 02298 #define FTM_STATUS_CH2F_MASK (0x4U) 02299 #define FTM_STATUS_CH2F_SHIFT (2U) 02300 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) 02301 #define FTM_STATUS_CH3F_MASK (0x8U) 02302 #define FTM_STATUS_CH3F_SHIFT (3U) 02303 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) 02304 #define FTM_STATUS_CH4F_MASK (0x10U) 02305 #define FTM_STATUS_CH4F_SHIFT (4U) 02306 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) 02307 #define FTM_STATUS_CH5F_MASK (0x20U) 02308 #define FTM_STATUS_CH5F_SHIFT (5U) 02309 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) 02310 #define FTM_STATUS_CH6F_MASK (0x40U) 02311 #define FTM_STATUS_CH6F_SHIFT (6U) 02312 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) 02313 #define FTM_STATUS_CH7F_MASK (0x80U) 02314 #define FTM_STATUS_CH7F_SHIFT (7U) 02315 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) 02316 02317 /*! @name MODE - Features Mode Selection */ 02318 #define FTM_MODE_FTMEN_MASK (0x1U) 02319 #define FTM_MODE_FTMEN_SHIFT (0U) 02320 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) 02321 #define FTM_MODE_INIT_MASK (0x2U) 02322 #define FTM_MODE_INIT_SHIFT (1U) 02323 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) 02324 #define FTM_MODE_WPDIS_MASK (0x4U) 02325 #define FTM_MODE_WPDIS_SHIFT (2U) 02326 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) 02327 #define FTM_MODE_PWMSYNC_MASK (0x8U) 02328 #define FTM_MODE_PWMSYNC_SHIFT (3U) 02329 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) 02330 #define FTM_MODE_CAPTEST_MASK (0x10U) 02331 #define FTM_MODE_CAPTEST_SHIFT (4U) 02332 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) 02333 #define FTM_MODE_FAULTM_MASK (0x60U) 02334 #define FTM_MODE_FAULTM_SHIFT (5U) 02335 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) 02336 #define FTM_MODE_FAULTIE_MASK (0x80U) 02337 #define FTM_MODE_FAULTIE_SHIFT (7U) 02338 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) 02339 02340 /*! @name SYNC - Synchronization */ 02341 #define FTM_SYNC_CNTMIN_MASK (0x1U) 02342 #define FTM_SYNC_CNTMIN_SHIFT (0U) 02343 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) 02344 #define FTM_SYNC_CNTMAX_MASK (0x2U) 02345 #define FTM_SYNC_CNTMAX_SHIFT (1U) 02346 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) 02347 #define FTM_SYNC_REINIT_MASK (0x4U) 02348 #define FTM_SYNC_REINIT_SHIFT (2U) 02349 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) 02350 #define FTM_SYNC_SYNCHOM_MASK (0x8U) 02351 #define FTM_SYNC_SYNCHOM_SHIFT (3U) 02352 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) 02353 #define FTM_SYNC_TRIG0_MASK (0x10U) 02354 #define FTM_SYNC_TRIG0_SHIFT (4U) 02355 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) 02356 #define FTM_SYNC_TRIG1_MASK (0x20U) 02357 #define FTM_SYNC_TRIG1_SHIFT (5U) 02358 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) 02359 #define FTM_SYNC_TRIG2_MASK (0x40U) 02360 #define FTM_SYNC_TRIG2_SHIFT (6U) 02361 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) 02362 #define FTM_SYNC_SWSYNC_MASK (0x80U) 02363 #define FTM_SYNC_SWSYNC_SHIFT (7U) 02364 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) 02365 02366 /*! @name OUTINIT - Initial State for Channels Output */ 02367 #define FTM_OUTINIT_CH0OI_MASK (0x1U) 02368 #define FTM_OUTINIT_CH0OI_SHIFT (0U) 02369 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) 02370 #define FTM_OUTINIT_CH1OI_MASK (0x2U) 02371 #define FTM_OUTINIT_CH1OI_SHIFT (1U) 02372 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) 02373 #define FTM_OUTINIT_CH2OI_MASK (0x4U) 02374 #define FTM_OUTINIT_CH2OI_SHIFT (2U) 02375 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) 02376 #define FTM_OUTINIT_CH3OI_MASK (0x8U) 02377 #define FTM_OUTINIT_CH3OI_SHIFT (3U) 02378 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) 02379 #define FTM_OUTINIT_CH4OI_MASK (0x10U) 02380 #define FTM_OUTINIT_CH4OI_SHIFT (4U) 02381 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) 02382 #define FTM_OUTINIT_CH5OI_MASK (0x20U) 02383 #define FTM_OUTINIT_CH5OI_SHIFT (5U) 02384 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) 02385 #define FTM_OUTINIT_CH6OI_MASK (0x40U) 02386 #define FTM_OUTINIT_CH6OI_SHIFT (6U) 02387 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) 02388 #define FTM_OUTINIT_CH7OI_MASK (0x80U) 02389 #define FTM_OUTINIT_CH7OI_SHIFT (7U) 02390 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) 02391 02392 /*! @name OUTMASK - Output Mask */ 02393 #define FTM_OUTMASK_CH0OM_MASK (0x1U) 02394 #define FTM_OUTMASK_CH0OM_SHIFT (0U) 02395 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) 02396 #define FTM_OUTMASK_CH1OM_MASK (0x2U) 02397 #define FTM_OUTMASK_CH1OM_SHIFT (1U) 02398 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) 02399 #define FTM_OUTMASK_CH2OM_MASK (0x4U) 02400 #define FTM_OUTMASK_CH2OM_SHIFT (2U) 02401 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) 02402 #define FTM_OUTMASK_CH3OM_MASK (0x8U) 02403 #define FTM_OUTMASK_CH3OM_SHIFT (3U) 02404 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) 02405 #define FTM_OUTMASK_CH4OM_MASK (0x10U) 02406 #define FTM_OUTMASK_CH4OM_SHIFT (4U) 02407 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) 02408 #define FTM_OUTMASK_CH5OM_MASK (0x20U) 02409 #define FTM_OUTMASK_CH5OM_SHIFT (5U) 02410 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) 02411 #define FTM_OUTMASK_CH6OM_MASK (0x40U) 02412 #define FTM_OUTMASK_CH6OM_SHIFT (6U) 02413 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) 02414 #define FTM_OUTMASK_CH7OM_MASK (0x80U) 02415 #define FTM_OUTMASK_CH7OM_SHIFT (7U) 02416 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) 02417 02418 /*! @name COMBINE - Function for Linked Channels */ 02419 #define FTM_COMBINE_COMBINE0_MASK (0x1U) 02420 #define FTM_COMBINE_COMBINE0_SHIFT (0U) 02421 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) 02422 #define FTM_COMBINE_COMP0_MASK (0x2U) 02423 #define FTM_COMBINE_COMP0_SHIFT (1U) 02424 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) 02425 #define FTM_COMBINE_DECAPEN0_MASK (0x4U) 02426 #define FTM_COMBINE_DECAPEN0_SHIFT (2U) 02427 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) 02428 #define FTM_COMBINE_DECAP0_MASK (0x8U) 02429 #define FTM_COMBINE_DECAP0_SHIFT (3U) 02430 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) 02431 #define FTM_COMBINE_DTEN0_MASK (0x10U) 02432 #define FTM_COMBINE_DTEN0_SHIFT (4U) 02433 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) 02434 #define FTM_COMBINE_SYNCEN0_MASK (0x20U) 02435 #define FTM_COMBINE_SYNCEN0_SHIFT (5U) 02436 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) 02437 #define FTM_COMBINE_FAULTEN0_MASK (0x40U) 02438 #define FTM_COMBINE_FAULTEN0_SHIFT (6U) 02439 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) 02440 #define FTM_COMBINE_COMBINE1_MASK (0x100U) 02441 #define FTM_COMBINE_COMBINE1_SHIFT (8U) 02442 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) 02443 #define FTM_COMBINE_COMP1_MASK (0x200U) 02444 #define FTM_COMBINE_COMP1_SHIFT (9U) 02445 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) 02446 #define FTM_COMBINE_DECAPEN1_MASK (0x400U) 02447 #define FTM_COMBINE_DECAPEN1_SHIFT (10U) 02448 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) 02449 #define FTM_COMBINE_DECAP1_MASK (0x800U) 02450 #define FTM_COMBINE_DECAP1_SHIFT (11U) 02451 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) 02452 #define FTM_COMBINE_DTEN1_MASK (0x1000U) 02453 #define FTM_COMBINE_DTEN1_SHIFT (12U) 02454 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) 02455 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U) 02456 #define FTM_COMBINE_SYNCEN1_SHIFT (13U) 02457 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) 02458 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U) 02459 #define FTM_COMBINE_FAULTEN1_SHIFT (14U) 02460 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) 02461 #define FTM_COMBINE_COMBINE2_MASK (0x10000U) 02462 #define FTM_COMBINE_COMBINE2_SHIFT (16U) 02463 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) 02464 #define FTM_COMBINE_COMP2_MASK (0x20000U) 02465 #define FTM_COMBINE_COMP2_SHIFT (17U) 02466 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) 02467 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U) 02468 #define FTM_COMBINE_DECAPEN2_SHIFT (18U) 02469 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) 02470 #define FTM_COMBINE_DECAP2_MASK (0x80000U) 02471 #define FTM_COMBINE_DECAP2_SHIFT (19U) 02472 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) 02473 #define FTM_COMBINE_DTEN2_MASK (0x100000U) 02474 #define FTM_COMBINE_DTEN2_SHIFT (20U) 02475 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) 02476 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U) 02477 #define FTM_COMBINE_SYNCEN2_SHIFT (21U) 02478 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) 02479 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U) 02480 #define FTM_COMBINE_FAULTEN2_SHIFT (22U) 02481 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) 02482 #define FTM_COMBINE_COMBINE3_MASK (0x1000000U) 02483 #define FTM_COMBINE_COMBINE3_SHIFT (24U) 02484 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) 02485 #define FTM_COMBINE_COMP3_MASK (0x2000000U) 02486 #define FTM_COMBINE_COMP3_SHIFT (25U) 02487 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) 02488 #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) 02489 #define FTM_COMBINE_DECAPEN3_SHIFT (26U) 02490 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) 02491 #define FTM_COMBINE_DECAP3_MASK (0x8000000U) 02492 #define FTM_COMBINE_DECAP3_SHIFT (27U) 02493 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) 02494 #define FTM_COMBINE_DTEN3_MASK (0x10000000U) 02495 #define FTM_COMBINE_DTEN3_SHIFT (28U) 02496 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) 02497 #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) 02498 #define FTM_COMBINE_SYNCEN3_SHIFT (29U) 02499 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) 02500 #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) 02501 #define FTM_COMBINE_FAULTEN3_SHIFT (30U) 02502 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) 02503 02504 /*! @name DEADTIME - Deadtime Insertion Control */ 02505 #define FTM_DEADTIME_DTVAL_MASK (0x3FU) 02506 #define FTM_DEADTIME_DTVAL_SHIFT (0U) 02507 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) 02508 #define FTM_DEADTIME_DTPS_MASK (0xC0U) 02509 #define FTM_DEADTIME_DTPS_SHIFT (6U) 02510 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) 02511 02512 /*! @name EXTTRIG - FTM External Trigger */ 02513 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) 02514 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) 02515 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) 02516 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) 02517 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) 02518 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) 02519 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) 02520 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) 02521 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) 02522 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) 02523 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) 02524 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) 02525 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) 02526 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) 02527 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) 02528 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) 02529 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) 02530 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) 02531 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) 02532 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) 02533 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) 02534 #define FTM_EXTTRIG_TRIGF_MASK (0x80U) 02535 #define FTM_EXTTRIG_TRIGF_SHIFT (7U) 02536 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) 02537 02538 /*! @name POL - Channels Polarity */ 02539 #define FTM_POL_POL0_MASK (0x1U) 02540 #define FTM_POL_POL0_SHIFT (0U) 02541 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) 02542 #define FTM_POL_POL1_MASK (0x2U) 02543 #define FTM_POL_POL1_SHIFT (1U) 02544 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) 02545 #define FTM_POL_POL2_MASK (0x4U) 02546 #define FTM_POL_POL2_SHIFT (2U) 02547 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) 02548 #define FTM_POL_POL3_MASK (0x8U) 02549 #define FTM_POL_POL3_SHIFT (3U) 02550 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) 02551 #define FTM_POL_POL4_MASK (0x10U) 02552 #define FTM_POL_POL4_SHIFT (4U) 02553 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) 02554 #define FTM_POL_POL5_MASK (0x20U) 02555 #define FTM_POL_POL5_SHIFT (5U) 02556 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) 02557 #define FTM_POL_POL6_MASK (0x40U) 02558 #define FTM_POL_POL6_SHIFT (6U) 02559 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) 02560 #define FTM_POL_POL7_MASK (0x80U) 02561 #define FTM_POL_POL7_SHIFT (7U) 02562 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) 02563 02564 /*! @name FMS - Fault Mode Status */ 02565 #define FTM_FMS_FAULTF0_MASK (0x1U) 02566 #define FTM_FMS_FAULTF0_SHIFT (0U) 02567 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) 02568 #define FTM_FMS_FAULTF1_MASK (0x2U) 02569 #define FTM_FMS_FAULTF1_SHIFT (1U) 02570 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) 02571 #define FTM_FMS_FAULTF2_MASK (0x4U) 02572 #define FTM_FMS_FAULTF2_SHIFT (2U) 02573 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) 02574 #define FTM_FMS_FAULTF3_MASK (0x8U) 02575 #define FTM_FMS_FAULTF3_SHIFT (3U) 02576 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) 02577 #define FTM_FMS_FAULTIN_MASK (0x20U) 02578 #define FTM_FMS_FAULTIN_SHIFT (5U) 02579 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) 02580 #define FTM_FMS_WPEN_MASK (0x40U) 02581 #define FTM_FMS_WPEN_SHIFT (6U) 02582 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) 02583 #define FTM_FMS_FAULTF_MASK (0x80U) 02584 #define FTM_FMS_FAULTF_SHIFT (7U) 02585 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) 02586 02587 /*! @name FILTER - Input Capture Filter Control */ 02588 #define FTM_FILTER_CH0FVAL_MASK (0xFU) 02589 #define FTM_FILTER_CH0FVAL_SHIFT (0U) 02590 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) 02591 #define FTM_FILTER_CH1FVAL_MASK (0xF0U) 02592 #define FTM_FILTER_CH1FVAL_SHIFT (4U) 02593 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) 02594 #define FTM_FILTER_CH2FVAL_MASK (0xF00U) 02595 #define FTM_FILTER_CH2FVAL_SHIFT (8U) 02596 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) 02597 #define FTM_FILTER_CH3FVAL_MASK (0xF000U) 02598 #define FTM_FILTER_CH3FVAL_SHIFT (12U) 02599 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) 02600 02601 /*! @name FLTCTRL - Fault Control */ 02602 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) 02603 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) 02604 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) 02605 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) 02606 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) 02607 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) 02608 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) 02609 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) 02610 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) 02611 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) 02612 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) 02613 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) 02614 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) 02615 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) 02616 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) 02617 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) 02618 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) 02619 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) 02620 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) 02621 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) 02622 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) 02623 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) 02624 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) 02625 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) 02626 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U) 02627 #define FTM_FLTCTRL_FFVAL_SHIFT (8U) 02628 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) 02629 02630 /*! @name QDCTRL - Quadrature Decoder Control and Status */ 02631 #define FTM_QDCTRL_QUADEN_MASK (0x1U) 02632 #define FTM_QDCTRL_QUADEN_SHIFT (0U) 02633 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK) 02634 #define FTM_QDCTRL_TOFDIR_MASK (0x2U) 02635 #define FTM_QDCTRL_TOFDIR_SHIFT (1U) 02636 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK) 02637 #define FTM_QDCTRL_QUADIR_MASK (0x4U) 02638 #define FTM_QDCTRL_QUADIR_SHIFT (2U) 02639 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK) 02640 #define FTM_QDCTRL_QUADMODE_MASK (0x8U) 02641 #define FTM_QDCTRL_QUADMODE_SHIFT (3U) 02642 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK) 02643 #define FTM_QDCTRL_PHBPOL_MASK (0x10U) 02644 #define FTM_QDCTRL_PHBPOL_SHIFT (4U) 02645 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK) 02646 #define FTM_QDCTRL_PHAPOL_MASK (0x20U) 02647 #define FTM_QDCTRL_PHAPOL_SHIFT (5U) 02648 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK) 02649 #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U) 02650 #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U) 02651 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK) 02652 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) 02653 #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U) 02654 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK) 02655 02656 /*! @name CONF - Configuration */ 02657 #define FTM_CONF_NUMTOF_MASK (0x1FU) 02658 #define FTM_CONF_NUMTOF_SHIFT (0U) 02659 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK) 02660 #define FTM_CONF_BDMMODE_MASK (0xC0U) 02661 #define FTM_CONF_BDMMODE_SHIFT (6U) 02662 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) 02663 #define FTM_CONF_GTBEEN_MASK (0x200U) 02664 #define FTM_CONF_GTBEEN_SHIFT (9U) 02665 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) 02666 #define FTM_CONF_GTBEOUT_MASK (0x400U) 02667 #define FTM_CONF_GTBEOUT_SHIFT (10U) 02668 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) 02669 02670 /*! @name FLTPOL - FTM Fault Input Polarity */ 02671 #define FTM_FLTPOL_FLT0POL_MASK (0x1U) 02672 #define FTM_FLTPOL_FLT0POL_SHIFT (0U) 02673 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) 02674 #define FTM_FLTPOL_FLT1POL_MASK (0x2U) 02675 #define FTM_FLTPOL_FLT1POL_SHIFT (1U) 02676 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) 02677 #define FTM_FLTPOL_FLT2POL_MASK (0x4U) 02678 #define FTM_FLTPOL_FLT2POL_SHIFT (2U) 02679 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) 02680 #define FTM_FLTPOL_FLT3POL_MASK (0x8U) 02681 #define FTM_FLTPOL_FLT3POL_SHIFT (3U) 02682 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) 02683 02684 /*! @name SYNCONF - Synchronization Configuration */ 02685 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) 02686 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) 02687 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) 02688 #define FTM_SYNCONF_CNTINC_MASK (0x4U) 02689 #define FTM_SYNCONF_CNTINC_SHIFT (2U) 02690 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) 02691 #define FTM_SYNCONF_INVC_MASK (0x10U) 02692 #define FTM_SYNCONF_INVC_SHIFT (4U) 02693 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) 02694 #define FTM_SYNCONF_SWOC_MASK (0x20U) 02695 #define FTM_SYNCONF_SWOC_SHIFT (5U) 02696 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) 02697 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U) 02698 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U) 02699 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) 02700 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) 02701 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) 02702 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) 02703 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U) 02704 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U) 02705 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) 02706 #define FTM_SYNCONF_SWOM_MASK (0x400U) 02707 #define FTM_SYNCONF_SWOM_SHIFT (10U) 02708 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) 02709 #define FTM_SYNCONF_SWINVC_MASK (0x800U) 02710 #define FTM_SYNCONF_SWINVC_SHIFT (11U) 02711 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) 02712 #define FTM_SYNCONF_SWSOC_MASK (0x1000U) 02713 #define FTM_SYNCONF_SWSOC_SHIFT (12U) 02714 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) 02715 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) 02716 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) 02717 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) 02718 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) 02719 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U) 02720 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) 02721 #define FTM_SYNCONF_HWOM_MASK (0x40000U) 02722 #define FTM_SYNCONF_HWOM_SHIFT (18U) 02723 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) 02724 #define FTM_SYNCONF_HWINVC_MASK (0x80000U) 02725 #define FTM_SYNCONF_HWINVC_SHIFT (19U) 02726 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) 02727 #define FTM_SYNCONF_HWSOC_MASK (0x100000U) 02728 #define FTM_SYNCONF_HWSOC_SHIFT (20U) 02729 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) 02730 02731 /*! @name INVCTRL - FTM Inverting Control */ 02732 #define FTM_INVCTRL_INV0EN_MASK (0x1U) 02733 #define FTM_INVCTRL_INV0EN_SHIFT (0U) 02734 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) 02735 #define FTM_INVCTRL_INV1EN_MASK (0x2U) 02736 #define FTM_INVCTRL_INV1EN_SHIFT (1U) 02737 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) 02738 #define FTM_INVCTRL_INV2EN_MASK (0x4U) 02739 #define FTM_INVCTRL_INV2EN_SHIFT (2U) 02740 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) 02741 #define FTM_INVCTRL_INV3EN_MASK (0x8U) 02742 #define FTM_INVCTRL_INV3EN_SHIFT (3U) 02743 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) 02744 02745 /*! @name SWOCTRL - FTM Software Output Control */ 02746 #define FTM_SWOCTRL_CH0OC_MASK (0x1U) 02747 #define FTM_SWOCTRL_CH0OC_SHIFT (0U) 02748 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) 02749 #define FTM_SWOCTRL_CH1OC_MASK (0x2U) 02750 #define FTM_SWOCTRL_CH1OC_SHIFT (1U) 02751 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) 02752 #define FTM_SWOCTRL_CH2OC_MASK (0x4U) 02753 #define FTM_SWOCTRL_CH2OC_SHIFT (2U) 02754 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) 02755 #define FTM_SWOCTRL_CH3OC_MASK (0x8U) 02756 #define FTM_SWOCTRL_CH3OC_SHIFT (3U) 02757 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) 02758 #define FTM_SWOCTRL_CH4OC_MASK (0x10U) 02759 #define FTM_SWOCTRL_CH4OC_SHIFT (4U) 02760 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) 02761 #define FTM_SWOCTRL_CH5OC_MASK (0x20U) 02762 #define FTM_SWOCTRL_CH5OC_SHIFT (5U) 02763 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) 02764 #define FTM_SWOCTRL_CH6OC_MASK (0x40U) 02765 #define FTM_SWOCTRL_CH6OC_SHIFT (6U) 02766 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) 02767 #define FTM_SWOCTRL_CH7OC_MASK (0x80U) 02768 #define FTM_SWOCTRL_CH7OC_SHIFT (7U) 02769 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) 02770 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U) 02771 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U) 02772 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) 02773 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U) 02774 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U) 02775 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) 02776 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U) 02777 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U) 02778 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) 02779 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U) 02780 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U) 02781 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) 02782 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) 02783 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U) 02784 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) 02785 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) 02786 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U) 02787 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) 02788 #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) 02789 #define FTM_SWOCTRL_CH6OCV_SHIFT (14U) 02790 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) 02791 #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) 02792 #define FTM_SWOCTRL_CH7OCV_SHIFT (15U) 02793 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) 02794 02795 /*! @name PWMLOAD - FTM PWM Load */ 02796 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U) 02797 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U) 02798 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) 02799 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U) 02800 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U) 02801 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) 02802 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U) 02803 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U) 02804 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) 02805 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U) 02806 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U) 02807 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) 02808 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U) 02809 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U) 02810 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) 02811 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U) 02812 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U) 02813 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) 02814 #define FTM_PWMLOAD_CH6SEL_MASK (0x40U) 02815 #define FTM_PWMLOAD_CH6SEL_SHIFT (6U) 02816 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) 02817 #define FTM_PWMLOAD_CH7SEL_MASK (0x80U) 02818 #define FTM_PWMLOAD_CH7SEL_SHIFT (7U) 02819 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) 02820 #define FTM_PWMLOAD_LDOK_MASK (0x200U) 02821 #define FTM_PWMLOAD_LDOK_SHIFT (9U) 02822 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) 02823 02824 02825 /*! 02826 * @} 02827 */ /* end of group FTM_Register_Masks */ 02828 02829 02830 /* FTM - Peripheral instance base addresses */ 02831 /** Peripheral FTM0 base address */ 02832 #define FTM0_BASE (0x40038000u) 02833 /** Peripheral FTM0 base pointer */ 02834 #define FTM0 ((FTM_Type *)FTM0_BASE) 02835 /** Peripheral FTM1 base address */ 02836 #define FTM1_BASE (0x40039000u) 02837 /** Peripheral FTM1 base pointer */ 02838 #define FTM1 ((FTM_Type *)FTM1_BASE) 02839 /** Array initializer of FTM peripheral base addresses */ 02840 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE } 02841 /** Array initializer of FTM peripheral base pointers */ 02842 #define FTM_BASE_PTRS { FTM0, FTM1 } 02843 /** Interrupt vectors for the FTM peripheral type */ 02844 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn } 02845 02846 /*! 02847 * @} 02848 */ /* end of group FTM_Peripheral_Access_Layer */ 02849 02850 02851 /* ---------------------------------------------------------------------------- 02852 -- GPIO Peripheral Access Layer 02853 ---------------------------------------------------------------------------- */ 02854 02855 /*! 02856 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 02857 * @{ 02858 */ 02859 02860 /** GPIO - Register Layout Typedef */ 02861 typedef struct { 02862 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 02863 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 02864 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 02865 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 02866 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 02867 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 02868 } GPIO_Type; 02869 02870 /* ---------------------------------------------------------------------------- 02871 -- GPIO Register Masks 02872 ---------------------------------------------------------------------------- */ 02873 02874 /*! 02875 * @addtogroup GPIO_Register_Masks GPIO Register Masks 02876 * @{ 02877 */ 02878 02879 /*! @name PDOR - Port Data Output Register */ 02880 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 02881 #define GPIO_PDOR_PDO_SHIFT (0U) 02882 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) 02883 02884 /*! @name PSOR - Port Set Output Register */ 02885 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 02886 #define GPIO_PSOR_PTSO_SHIFT (0U) 02887 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) 02888 02889 /*! @name PCOR - Port Clear Output Register */ 02890 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 02891 #define GPIO_PCOR_PTCO_SHIFT (0U) 02892 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) 02893 02894 /*! @name PTOR - Port Toggle Output Register */ 02895 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 02896 #define GPIO_PTOR_PTTO_SHIFT (0U) 02897 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) 02898 02899 /*! @name PDIR - Port Data Input Register */ 02900 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 02901 #define GPIO_PDIR_PDI_SHIFT (0U) 02902 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) 02903 02904 /*! @name PDDR - Port Data Direction Register */ 02905 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 02906 #define GPIO_PDDR_PDD_SHIFT (0U) 02907 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) 02908 02909 02910 /*! 02911 * @} 02912 */ /* end of group GPIO_Register_Masks */ 02913 02914 02915 /* GPIO - Peripheral instance base addresses */ 02916 /** Peripheral PTA base address */ 02917 #define PTA_BASE (0x400FF000u) 02918 /** Peripheral PTA base pointer */ 02919 #define PTA ((GPIO_Type *)PTA_BASE) 02920 /** Peripheral PTB base address */ 02921 #define PTB_BASE (0x400FF040u) 02922 /** Peripheral PTB base pointer */ 02923 #define PTB ((GPIO_Type *)PTB_BASE) 02924 /** Peripheral PTC base address */ 02925 #define PTC_BASE (0x400FF080u) 02926 /** Peripheral PTC base pointer */ 02927 #define PTC ((GPIO_Type *)PTC_BASE) 02928 /** Peripheral PTD base address */ 02929 #define PTD_BASE (0x400FF0C0u) 02930 /** Peripheral PTD base pointer */ 02931 #define PTD ((GPIO_Type *)PTD_BASE) 02932 /** Peripheral PTE base address */ 02933 #define PTE_BASE (0x400FF100u) 02934 /** Peripheral PTE base pointer */ 02935 #define PTE ((GPIO_Type *)PTE_BASE) 02936 /** Array initializer of GPIO peripheral base addresses */ 02937 #define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE } 02938 /** Array initializer of GPIO peripheral base pointers */ 02939 #define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE } 02940 02941 /*! 02942 * @} 02943 */ /* end of group GPIO_Peripheral_Access_Layer */ 02944 02945 02946 /* ---------------------------------------------------------------------------- 02947 -- I2C Peripheral Access Layer 02948 ---------------------------------------------------------------------------- */ 02949 02950 /*! 02951 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 02952 * @{ 02953 */ 02954 02955 /** I2C - Register Layout Typedef */ 02956 typedef struct { 02957 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ 02958 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ 02959 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ 02960 __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */ 02961 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ 02962 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ 02963 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ 02964 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ 02965 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ 02966 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ 02967 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ 02968 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ 02969 } I2C_Type; 02970 02971 /* ---------------------------------------------------------------------------- 02972 -- I2C Register Masks 02973 ---------------------------------------------------------------------------- */ 02974 02975 /*! 02976 * @addtogroup I2C_Register_Masks I2C Register Masks 02977 * @{ 02978 */ 02979 02980 /*! @name A1 - I2C Address Register 1 */ 02981 #define I2C_A1_AD_MASK (0xFEU) 02982 #define I2C_A1_AD_SHIFT (1U) 02983 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) 02984 02985 /*! @name F - I2C Frequency Divider register */ 02986 #define I2C_F_ICR_MASK (0x3FU) 02987 #define I2C_F_ICR_SHIFT (0U) 02988 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) 02989 #define I2C_F_MULT_MASK (0xC0U) 02990 #define I2C_F_MULT_SHIFT (6U) 02991 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) 02992 02993 /*! @name C1 - I2C Control Register 1 */ 02994 #define I2C_C1_DMAEN_MASK (0x1U) 02995 #define I2C_C1_DMAEN_SHIFT (0U) 02996 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) 02997 #define I2C_C1_WUEN_MASK (0x2U) 02998 #define I2C_C1_WUEN_SHIFT (1U) 02999 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) 03000 #define I2C_C1_RSTA_MASK (0x4U) 03001 #define I2C_C1_RSTA_SHIFT (2U) 03002 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) 03003 #define I2C_C1_TXAK_MASK (0x8U) 03004 #define I2C_C1_TXAK_SHIFT (3U) 03005 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) 03006 #define I2C_C1_TX_MASK (0x10U) 03007 #define I2C_C1_TX_SHIFT (4U) 03008 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) 03009 #define I2C_C1_MST_MASK (0x20U) 03010 #define I2C_C1_MST_SHIFT (5U) 03011 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) 03012 #define I2C_C1_IICIE_MASK (0x40U) 03013 #define I2C_C1_IICIE_SHIFT (6U) 03014 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) 03015 #define I2C_C1_IICEN_MASK (0x80U) 03016 #define I2C_C1_IICEN_SHIFT (7U) 03017 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) 03018 03019 /*! @name S - I2C Status Register */ 03020 #define I2C_S_RXAK_MASK (0x1U) 03021 #define I2C_S_RXAK_SHIFT (0U) 03022 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) 03023 #define I2C_S_IICIF_MASK (0x2U) 03024 #define I2C_S_IICIF_SHIFT (1U) 03025 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) 03026 #define I2C_S_SRW_MASK (0x4U) 03027 #define I2C_S_SRW_SHIFT (2U) 03028 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) 03029 #define I2C_S_RAM_MASK (0x8U) 03030 #define I2C_S_RAM_SHIFT (3U) 03031 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) 03032 #define I2C_S_ARBL_MASK (0x10U) 03033 #define I2C_S_ARBL_SHIFT (4U) 03034 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) 03035 #define I2C_S_BUSY_MASK (0x20U) 03036 #define I2C_S_BUSY_SHIFT (5U) 03037 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) 03038 #define I2C_S_IAAS_MASK (0x40U) 03039 #define I2C_S_IAAS_SHIFT (6U) 03040 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) 03041 #define I2C_S_TCF_MASK (0x80U) 03042 #define I2C_S_TCF_SHIFT (7U) 03043 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) 03044 03045 /*! @name D - I2C Data I/O register */ 03046 #define I2C_D_DATA_MASK (0xFFU) 03047 #define I2C_D_DATA_SHIFT (0U) 03048 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) 03049 03050 /*! @name C2 - I2C Control Register 2 */ 03051 #define I2C_C2_AD_MASK (0x7U) 03052 #define I2C_C2_AD_SHIFT (0U) 03053 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) 03054 #define I2C_C2_RMEN_MASK (0x8U) 03055 #define I2C_C2_RMEN_SHIFT (3U) 03056 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) 03057 #define I2C_C2_SBRC_MASK (0x10U) 03058 #define I2C_C2_SBRC_SHIFT (4U) 03059 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) 03060 #define I2C_C2_HDRS_MASK (0x20U) 03061 #define I2C_C2_HDRS_SHIFT (5U) 03062 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) 03063 #define I2C_C2_ADEXT_MASK (0x40U) 03064 #define I2C_C2_ADEXT_SHIFT (6U) 03065 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) 03066 #define I2C_C2_GCAEN_MASK (0x80U) 03067 #define I2C_C2_GCAEN_SHIFT (7U) 03068 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) 03069 03070 /*! @name FLT - I2C Programmable Input Glitch Filter register */ 03071 #define I2C_FLT_FLT_MASK (0x1FU) 03072 #define I2C_FLT_FLT_SHIFT (0U) 03073 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) 03074 03075 /*! @name RA - I2C Range Address register */ 03076 #define I2C_RA_RAD_MASK (0xFEU) 03077 #define I2C_RA_RAD_SHIFT (1U) 03078 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) 03079 03080 /*! @name SMB - I2C SMBus Control and Status register */ 03081 #define I2C_SMB_SHTF2IE_MASK (0x1U) 03082 #define I2C_SMB_SHTF2IE_SHIFT (0U) 03083 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) 03084 #define I2C_SMB_SHTF2_MASK (0x2U) 03085 #define I2C_SMB_SHTF2_SHIFT (1U) 03086 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) 03087 #define I2C_SMB_SHTF1_MASK (0x4U) 03088 #define I2C_SMB_SHTF1_SHIFT (2U) 03089 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) 03090 #define I2C_SMB_SLTF_MASK (0x8U) 03091 #define I2C_SMB_SLTF_SHIFT (3U) 03092 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) 03093 #define I2C_SMB_TCKSEL_MASK (0x10U) 03094 #define I2C_SMB_TCKSEL_SHIFT (4U) 03095 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) 03096 #define I2C_SMB_SIICAEN_MASK (0x20U) 03097 #define I2C_SMB_SIICAEN_SHIFT (5U) 03098 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) 03099 #define I2C_SMB_ALERTEN_MASK (0x40U) 03100 #define I2C_SMB_ALERTEN_SHIFT (6U) 03101 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) 03102 #define I2C_SMB_FACK_MASK (0x80U) 03103 #define I2C_SMB_FACK_SHIFT (7U) 03104 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) 03105 03106 /*! @name A2 - I2C Address Register 2 */ 03107 #define I2C_A2_SAD_MASK (0xFEU) 03108 #define I2C_A2_SAD_SHIFT (1U) 03109 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) 03110 03111 /*! @name SLTH - I2C SCL Low Timeout Register High */ 03112 #define I2C_SLTH_SSLT_MASK (0xFFU) 03113 #define I2C_SLTH_SSLT_SHIFT (0U) 03114 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) 03115 03116 /*! @name SLTL - I2C SCL Low Timeout Register Low */ 03117 #define I2C_SLTL_SSLT_MASK (0xFFU) 03118 #define I2C_SLTL_SSLT_SHIFT (0U) 03119 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) 03120 03121 03122 /*! 03123 * @} 03124 */ /* end of group I2C_Register_Masks */ 03125 03126 03127 /* I2C - Peripheral instance base addresses */ 03128 /** Peripheral I2C0 base address */ 03129 #define I2C0_BASE (0x40066000u) 03130 /** Peripheral I2C0 base pointer */ 03131 #define I2C0 ((I2C_Type *)I2C0_BASE) 03132 /** Array initializer of I2C peripheral base addresses */ 03133 #define I2C_BASE_ADDRS { I2C0_BASE } 03134 /** Array initializer of I2C peripheral base pointers */ 03135 #define I2C_BASE_PTRS { I2C0 } 03136 /** Interrupt vectors for the I2C peripheral type */ 03137 #define I2C_IRQS { I2C0_IRQn } 03138 03139 /*! 03140 * @} 03141 */ /* end of group I2C_Peripheral_Access_Layer */ 03142 03143 03144 /* ---------------------------------------------------------------------------- 03145 -- I2S Peripheral Access Layer 03146 ---------------------------------------------------------------------------- */ 03147 03148 /*! 03149 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer 03150 * @{ 03151 */ 03152 03153 /** I2S - Register Layout Typedef */ 03154 typedef struct { 03155 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ 03156 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ 03157 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ 03158 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ 03159 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ 03160 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ 03161 uint8_t RESERVED_0[8]; 03162 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ 03163 uint8_t RESERVED_1[24]; 03164 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ 03165 uint8_t RESERVED_2[24]; 03166 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ 03167 uint8_t RESERVED_3[28]; 03168 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ 03169 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ 03170 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ 03171 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ 03172 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ 03173 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ 03174 uint8_t RESERVED_4[8]; 03175 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ 03176 uint8_t RESERVED_5[24]; 03177 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ 03178 uint8_t RESERVED_6[24]; 03179 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ 03180 uint8_t RESERVED_7[28]; 03181 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */ 03182 __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */ 03183 } I2S_Type; 03184 03185 /* ---------------------------------------------------------------------------- 03186 -- I2S Register Masks 03187 ---------------------------------------------------------------------------- */ 03188 03189 /*! 03190 * @addtogroup I2S_Register_Masks I2S Register Masks 03191 * @{ 03192 */ 03193 03194 /*! @name TCSR - SAI Transmit Control Register */ 03195 #define I2S_TCSR_FRDE_MASK (0x1U) 03196 #define I2S_TCSR_FRDE_SHIFT (0U) 03197 #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) 03198 #define I2S_TCSR_FWDE_MASK (0x2U) 03199 #define I2S_TCSR_FWDE_SHIFT (1U) 03200 #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) 03201 #define I2S_TCSR_FRIE_MASK (0x100U) 03202 #define I2S_TCSR_FRIE_SHIFT (8U) 03203 #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) 03204 #define I2S_TCSR_FWIE_MASK (0x200U) 03205 #define I2S_TCSR_FWIE_SHIFT (9U) 03206 #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) 03207 #define I2S_TCSR_FEIE_MASK (0x400U) 03208 #define I2S_TCSR_FEIE_SHIFT (10U) 03209 #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) 03210 #define I2S_TCSR_SEIE_MASK (0x800U) 03211 #define I2S_TCSR_SEIE_SHIFT (11U) 03212 #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) 03213 #define I2S_TCSR_WSIE_MASK (0x1000U) 03214 #define I2S_TCSR_WSIE_SHIFT (12U) 03215 #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) 03216 #define I2S_TCSR_FRF_MASK (0x10000U) 03217 #define I2S_TCSR_FRF_SHIFT (16U) 03218 #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) 03219 #define I2S_TCSR_FWF_MASK (0x20000U) 03220 #define I2S_TCSR_FWF_SHIFT (17U) 03221 #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) 03222 #define I2S_TCSR_FEF_MASK (0x40000U) 03223 #define I2S_TCSR_FEF_SHIFT (18U) 03224 #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) 03225 #define I2S_TCSR_SEF_MASK (0x80000U) 03226 #define I2S_TCSR_SEF_SHIFT (19U) 03227 #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) 03228 #define I2S_TCSR_WSF_MASK (0x100000U) 03229 #define I2S_TCSR_WSF_SHIFT (20U) 03230 #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) 03231 #define I2S_TCSR_SR_MASK (0x1000000U) 03232 #define I2S_TCSR_SR_SHIFT (24U) 03233 #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) 03234 #define I2S_TCSR_FR_MASK (0x2000000U) 03235 #define I2S_TCSR_FR_SHIFT (25U) 03236 #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) 03237 #define I2S_TCSR_BCE_MASK (0x10000000U) 03238 #define I2S_TCSR_BCE_SHIFT (28U) 03239 #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) 03240 #define I2S_TCSR_DBGE_MASK (0x20000000U) 03241 #define I2S_TCSR_DBGE_SHIFT (29U) 03242 #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) 03243 #define I2S_TCSR_STOPE_MASK (0x40000000U) 03244 #define I2S_TCSR_STOPE_SHIFT (30U) 03245 #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) 03246 #define I2S_TCSR_TE_MASK (0x80000000U) 03247 #define I2S_TCSR_TE_SHIFT (31U) 03248 #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) 03249 03250 /*! @name TCR1 - SAI Transmit Configuration 1 Register */ 03251 #define I2S_TCR1_TFW_MASK (0x7U) 03252 #define I2S_TCR1_TFW_SHIFT (0U) 03253 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) 03254 03255 /*! @name TCR2 - SAI Transmit Configuration 2 Register */ 03256 #define I2S_TCR2_DIV_MASK (0xFFU) 03257 #define I2S_TCR2_DIV_SHIFT (0U) 03258 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) 03259 #define I2S_TCR2_BCD_MASK (0x1000000U) 03260 #define I2S_TCR2_BCD_SHIFT (24U) 03261 #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) 03262 #define I2S_TCR2_BCP_MASK (0x2000000U) 03263 #define I2S_TCR2_BCP_SHIFT (25U) 03264 #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) 03265 #define I2S_TCR2_MSEL_MASK (0xC000000U) 03266 #define I2S_TCR2_MSEL_SHIFT (26U) 03267 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) 03268 #define I2S_TCR2_BCI_MASK (0x10000000U) 03269 #define I2S_TCR2_BCI_SHIFT (28U) 03270 #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) 03271 #define I2S_TCR2_BCS_MASK (0x20000000U) 03272 #define I2S_TCR2_BCS_SHIFT (29U) 03273 #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) 03274 #define I2S_TCR2_SYNC_MASK (0xC0000000U) 03275 #define I2S_TCR2_SYNC_SHIFT (30U) 03276 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) 03277 03278 /*! @name TCR3 - SAI Transmit Configuration 3 Register */ 03279 #define I2S_TCR3_WDFL_MASK (0x1FU) 03280 #define I2S_TCR3_WDFL_SHIFT (0U) 03281 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) 03282 #define I2S_TCR3_TCE_MASK (0x30000U) 03283 #define I2S_TCR3_TCE_SHIFT (16U) 03284 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) 03285 03286 /*! @name TCR4 - SAI Transmit Configuration 4 Register */ 03287 #define I2S_TCR4_FSD_MASK (0x1U) 03288 #define I2S_TCR4_FSD_SHIFT (0U) 03289 #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) 03290 #define I2S_TCR4_FSP_MASK (0x2U) 03291 #define I2S_TCR4_FSP_SHIFT (1U) 03292 #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) 03293 #define I2S_TCR4_FSE_MASK (0x8U) 03294 #define I2S_TCR4_FSE_SHIFT (3U) 03295 #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) 03296 #define I2S_TCR4_MF_MASK (0x10U) 03297 #define I2S_TCR4_MF_SHIFT (4U) 03298 #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) 03299 #define I2S_TCR4_SYWD_MASK (0x1F00U) 03300 #define I2S_TCR4_SYWD_SHIFT (8U) 03301 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) 03302 #define I2S_TCR4_FRSZ_MASK (0x1F0000U) 03303 #define I2S_TCR4_FRSZ_SHIFT (16U) 03304 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) 03305 03306 /*! @name TCR5 - SAI Transmit Configuration 5 Register */ 03307 #define I2S_TCR5_FBT_MASK (0x1F00U) 03308 #define I2S_TCR5_FBT_SHIFT (8U) 03309 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) 03310 #define I2S_TCR5_W0W_MASK (0x1F0000U) 03311 #define I2S_TCR5_W0W_SHIFT (16U) 03312 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) 03313 #define I2S_TCR5_WNW_MASK (0x1F000000U) 03314 #define I2S_TCR5_WNW_SHIFT (24U) 03315 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) 03316 03317 /*! @name TDR - SAI Transmit Data Register */ 03318 #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) 03319 #define I2S_TDR_TDR_SHIFT (0U) 03320 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) 03321 03322 /* The count of I2S_TDR */ 03323 #define I2S_TDR_COUNT (2U) 03324 03325 /*! @name TFR - SAI Transmit FIFO Register */ 03326 #define I2S_TFR_RFP_MASK (0xFU) 03327 #define I2S_TFR_RFP_SHIFT (0U) 03328 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) 03329 #define I2S_TFR_WFP_MASK (0xF0000U) 03330 #define I2S_TFR_WFP_SHIFT (16U) 03331 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) 03332 03333 /* The count of I2S_TFR */ 03334 #define I2S_TFR_COUNT (2U) 03335 03336 /*! @name TMR - SAI Transmit Mask Register */ 03337 #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) 03338 #define I2S_TMR_TWM_SHIFT (0U) 03339 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) 03340 03341 /*! @name RCSR - SAI Receive Control Register */ 03342 #define I2S_RCSR_FRDE_MASK (0x1U) 03343 #define I2S_RCSR_FRDE_SHIFT (0U) 03344 #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) 03345 #define I2S_RCSR_FWDE_MASK (0x2U) 03346 #define I2S_RCSR_FWDE_SHIFT (1U) 03347 #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) 03348 #define I2S_RCSR_FRIE_MASK (0x100U) 03349 #define I2S_RCSR_FRIE_SHIFT (8U) 03350 #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) 03351 #define I2S_RCSR_FWIE_MASK (0x200U) 03352 #define I2S_RCSR_FWIE_SHIFT (9U) 03353 #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) 03354 #define I2S_RCSR_FEIE_MASK (0x400U) 03355 #define I2S_RCSR_FEIE_SHIFT (10U) 03356 #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) 03357 #define I2S_RCSR_SEIE_MASK (0x800U) 03358 #define I2S_RCSR_SEIE_SHIFT (11U) 03359 #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) 03360 #define I2S_RCSR_WSIE_MASK (0x1000U) 03361 #define I2S_RCSR_WSIE_SHIFT (12U) 03362 #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) 03363 #define I2S_RCSR_FRF_MASK (0x10000U) 03364 #define I2S_RCSR_FRF_SHIFT (16U) 03365 #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) 03366 #define I2S_RCSR_FWF_MASK (0x20000U) 03367 #define I2S_RCSR_FWF_SHIFT (17U) 03368 #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) 03369 #define I2S_RCSR_FEF_MASK (0x40000U) 03370 #define I2S_RCSR_FEF_SHIFT (18U) 03371 #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) 03372 #define I2S_RCSR_SEF_MASK (0x80000U) 03373 #define I2S_RCSR_SEF_SHIFT (19U) 03374 #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) 03375 #define I2S_RCSR_WSF_MASK (0x100000U) 03376 #define I2S_RCSR_WSF_SHIFT (20U) 03377 #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) 03378 #define I2S_RCSR_SR_MASK (0x1000000U) 03379 #define I2S_RCSR_SR_SHIFT (24U) 03380 #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) 03381 #define I2S_RCSR_FR_MASK (0x2000000U) 03382 #define I2S_RCSR_FR_SHIFT (25U) 03383 #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) 03384 #define I2S_RCSR_BCE_MASK (0x10000000U) 03385 #define I2S_RCSR_BCE_SHIFT (28U) 03386 #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) 03387 #define I2S_RCSR_DBGE_MASK (0x20000000U) 03388 #define I2S_RCSR_DBGE_SHIFT (29U) 03389 #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) 03390 #define I2S_RCSR_STOPE_MASK (0x40000000U) 03391 #define I2S_RCSR_STOPE_SHIFT (30U) 03392 #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) 03393 #define I2S_RCSR_RE_MASK (0x80000000U) 03394 #define I2S_RCSR_RE_SHIFT (31U) 03395 #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) 03396 03397 /*! @name RCR1 - SAI Receive Configuration 1 Register */ 03398 #define I2S_RCR1_RFW_MASK (0x7U) 03399 #define I2S_RCR1_RFW_SHIFT (0U) 03400 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) 03401 03402 /*! @name RCR2 - SAI Receive Configuration 2 Register */ 03403 #define I2S_RCR2_DIV_MASK (0xFFU) 03404 #define I2S_RCR2_DIV_SHIFT (0U) 03405 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) 03406 #define I2S_RCR2_BCD_MASK (0x1000000U) 03407 #define I2S_RCR2_BCD_SHIFT (24U) 03408 #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) 03409 #define I2S_RCR2_BCP_MASK (0x2000000U) 03410 #define I2S_RCR2_BCP_SHIFT (25U) 03411 #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) 03412 #define I2S_RCR2_MSEL_MASK (0xC000000U) 03413 #define I2S_RCR2_MSEL_SHIFT (26U) 03414 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) 03415 #define I2S_RCR2_BCI_MASK (0x10000000U) 03416 #define I2S_RCR2_BCI_SHIFT (28U) 03417 #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) 03418 #define I2S_RCR2_BCS_MASK (0x20000000U) 03419 #define I2S_RCR2_BCS_SHIFT (29U) 03420 #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) 03421 #define I2S_RCR2_SYNC_MASK (0xC0000000U) 03422 #define I2S_RCR2_SYNC_SHIFT (30U) 03423 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) 03424 03425 /*! @name RCR3 - SAI Receive Configuration 3 Register */ 03426 #define I2S_RCR3_WDFL_MASK (0x1FU) 03427 #define I2S_RCR3_WDFL_SHIFT (0U) 03428 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) 03429 #define I2S_RCR3_RCE_MASK (0x30000U) 03430 #define I2S_RCR3_RCE_SHIFT (16U) 03431 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) 03432 03433 /*! @name RCR4 - SAI Receive Configuration 4 Register */ 03434 #define I2S_RCR4_FSD_MASK (0x1U) 03435 #define I2S_RCR4_FSD_SHIFT (0U) 03436 #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) 03437 #define I2S_RCR4_FSP_MASK (0x2U) 03438 #define I2S_RCR4_FSP_SHIFT (1U) 03439 #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) 03440 #define I2S_RCR4_FSE_MASK (0x8U) 03441 #define I2S_RCR4_FSE_SHIFT (3U) 03442 #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) 03443 #define I2S_RCR4_MF_MASK (0x10U) 03444 #define I2S_RCR4_MF_SHIFT (4U) 03445 #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) 03446 #define I2S_RCR4_SYWD_MASK (0x1F00U) 03447 #define I2S_RCR4_SYWD_SHIFT (8U) 03448 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) 03449 #define I2S_RCR4_FRSZ_MASK (0x1F0000U) 03450 #define I2S_RCR4_FRSZ_SHIFT (16U) 03451 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) 03452 03453 /*! @name RCR5 - SAI Receive Configuration 5 Register */ 03454 #define I2S_RCR5_FBT_MASK (0x1F00U) 03455 #define I2S_RCR5_FBT_SHIFT (8U) 03456 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) 03457 #define I2S_RCR5_W0W_MASK (0x1F0000U) 03458 #define I2S_RCR5_W0W_SHIFT (16U) 03459 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) 03460 #define I2S_RCR5_WNW_MASK (0x1F000000U) 03461 #define I2S_RCR5_WNW_SHIFT (24U) 03462 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) 03463 03464 /*! @name RDR - SAI Receive Data Register */ 03465 #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) 03466 #define I2S_RDR_RDR_SHIFT (0U) 03467 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) 03468 03469 /* The count of I2S_RDR */ 03470 #define I2S_RDR_COUNT (2U) 03471 03472 /*! @name RFR - SAI Receive FIFO Register */ 03473 #define I2S_RFR_RFP_MASK (0xFU) 03474 #define I2S_RFR_RFP_SHIFT (0U) 03475 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) 03476 #define I2S_RFR_WFP_MASK (0xF0000U) 03477 #define I2S_RFR_WFP_SHIFT (16U) 03478 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) 03479 03480 /* The count of I2S_RFR */ 03481 #define I2S_RFR_COUNT (2U) 03482 03483 /*! @name RMR - SAI Receive Mask Register */ 03484 #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) 03485 #define I2S_RMR_RWM_SHIFT (0U) 03486 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) 03487 03488 /*! @name MCR - SAI MCLK Control Register */ 03489 #define I2S_MCR_MICS_MASK (0x3000000U) 03490 #define I2S_MCR_MICS_SHIFT (24U) 03491 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK) 03492 #define I2S_MCR_MOE_MASK (0x40000000U) 03493 #define I2S_MCR_MOE_SHIFT (30U) 03494 #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) 03495 #define I2S_MCR_DUF_MASK (0x80000000U) 03496 #define I2S_MCR_DUF_SHIFT (31U) 03497 #define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK) 03498 03499 /*! @name MDR - MCLK Divide Register */ 03500 #define I2S_MDR_DIVIDE_MASK (0xFFFU) 03501 #define I2S_MDR_DIVIDE_SHIFT (0U) 03502 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK) 03503 #define I2S_MDR_FRACT_MASK (0xFF000U) 03504 #define I2S_MDR_FRACT_SHIFT (12U) 03505 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK) 03506 03507 03508 /*! 03509 * @} 03510 */ /* end of group I2S_Register_Masks */ 03511 03512 03513 /* I2S - Peripheral instance base addresses */ 03514 /** Peripheral I2S0 base address */ 03515 #define I2S0_BASE (0x4002F000u) 03516 /** Peripheral I2S0 base pointer */ 03517 #define I2S0 ((I2S_Type *)I2S0_BASE) 03518 /** Array initializer of I2S peripheral base addresses */ 03519 #define I2S_BASE_ADDRS { I2S0_BASE } 03520 /** Array initializer of I2S peripheral base pointers */ 03521 #define I2S_BASE_PTRS { I2S0 } 03522 /** Interrupt vectors for the I2S peripheral type */ 03523 #define I2S_RX_IRQS { I2S0_Rx_IRQn } 03524 #define I2S_TX_IRQS { I2S0_Tx_IRQn } 03525 03526 /*! 03527 * @} 03528 */ /* end of group I2S_Peripheral_Access_Layer */ 03529 03530 03531 /* ---------------------------------------------------------------------------- 03532 -- LLWU Peripheral Access Layer 03533 ---------------------------------------------------------------------------- */ 03534 03535 /*! 03536 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer 03537 * @{ 03538 */ 03539 03540 /** LLWU - Register Layout Typedef */ 03541 typedef struct { 03542 __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */ 03543 __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */ 03544 __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */ 03545 __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */ 03546 __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */ 03547 __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */ 03548 __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */ 03549 __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */ 03550 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */ 03551 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */ 03552 __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */ 03553 } LLWU_Type; 03554 03555 /* ---------------------------------------------------------------------------- 03556 -- LLWU Register Masks 03557 ---------------------------------------------------------------------------- */ 03558 03559 /*! 03560 * @addtogroup LLWU_Register_Masks LLWU Register Masks 03561 * @{ 03562 */ 03563 03564 /*! @name PE1 - LLWU Pin Enable 1 Register */ 03565 #define LLWU_PE1_WUPE0_MASK (0x3U) 03566 #define LLWU_PE1_WUPE0_SHIFT (0U) 03567 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) 03568 #define LLWU_PE1_WUPE1_MASK (0xCU) 03569 #define LLWU_PE1_WUPE1_SHIFT (2U) 03570 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) 03571 #define LLWU_PE1_WUPE2_MASK (0x30U) 03572 #define LLWU_PE1_WUPE2_SHIFT (4U) 03573 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) 03574 #define LLWU_PE1_WUPE3_MASK (0xC0U) 03575 #define LLWU_PE1_WUPE3_SHIFT (6U) 03576 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) 03577 03578 /*! @name PE2 - LLWU Pin Enable 2 Register */ 03579 #define LLWU_PE2_WUPE4_MASK (0x3U) 03580 #define LLWU_PE2_WUPE4_SHIFT (0U) 03581 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) 03582 #define LLWU_PE2_WUPE5_MASK (0xCU) 03583 #define LLWU_PE2_WUPE5_SHIFT (2U) 03584 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) 03585 #define LLWU_PE2_WUPE6_MASK (0x30U) 03586 #define LLWU_PE2_WUPE6_SHIFT (4U) 03587 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) 03588 #define LLWU_PE2_WUPE7_MASK (0xC0U) 03589 #define LLWU_PE2_WUPE7_SHIFT (6U) 03590 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) 03591 03592 /*! @name PE3 - LLWU Pin Enable 3 Register */ 03593 #define LLWU_PE3_WUPE8_MASK (0x3U) 03594 #define LLWU_PE3_WUPE8_SHIFT (0U) 03595 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) 03596 #define LLWU_PE3_WUPE9_MASK (0xCU) 03597 #define LLWU_PE3_WUPE9_SHIFT (2U) 03598 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) 03599 #define LLWU_PE3_WUPE10_MASK (0x30U) 03600 #define LLWU_PE3_WUPE10_SHIFT (4U) 03601 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) 03602 #define LLWU_PE3_WUPE11_MASK (0xC0U) 03603 #define LLWU_PE3_WUPE11_SHIFT (6U) 03604 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) 03605 03606 /*! @name PE4 - LLWU Pin Enable 4 Register */ 03607 #define LLWU_PE4_WUPE12_MASK (0x3U) 03608 #define LLWU_PE4_WUPE12_SHIFT (0U) 03609 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) 03610 #define LLWU_PE4_WUPE13_MASK (0xCU) 03611 #define LLWU_PE4_WUPE13_SHIFT (2U) 03612 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) 03613 #define LLWU_PE4_WUPE14_MASK (0x30U) 03614 #define LLWU_PE4_WUPE14_SHIFT (4U) 03615 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) 03616 #define LLWU_PE4_WUPE15_MASK (0xC0U) 03617 #define LLWU_PE4_WUPE15_SHIFT (6U) 03618 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) 03619 03620 /*! @name ME - LLWU Module Enable Register */ 03621 #define LLWU_ME_WUME0_MASK (0x1U) 03622 #define LLWU_ME_WUME0_SHIFT (0U) 03623 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) 03624 #define LLWU_ME_WUME1_MASK (0x2U) 03625 #define LLWU_ME_WUME1_SHIFT (1U) 03626 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) 03627 #define LLWU_ME_WUME2_MASK (0x4U) 03628 #define LLWU_ME_WUME2_SHIFT (2U) 03629 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) 03630 #define LLWU_ME_WUME3_MASK (0x8U) 03631 #define LLWU_ME_WUME3_SHIFT (3U) 03632 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) 03633 #define LLWU_ME_WUME4_MASK (0x10U) 03634 #define LLWU_ME_WUME4_SHIFT (4U) 03635 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) 03636 #define LLWU_ME_WUME5_MASK (0x20U) 03637 #define LLWU_ME_WUME5_SHIFT (5U) 03638 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) 03639 #define LLWU_ME_WUME6_MASK (0x40U) 03640 #define LLWU_ME_WUME6_SHIFT (6U) 03641 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) 03642 #define LLWU_ME_WUME7_MASK (0x80U) 03643 #define LLWU_ME_WUME7_SHIFT (7U) 03644 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) 03645 03646 /*! @name F1 - LLWU Flag 1 Register */ 03647 #define LLWU_F1_WUF0_MASK (0x1U) 03648 #define LLWU_F1_WUF0_SHIFT (0U) 03649 #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK) 03650 #define LLWU_F1_WUF1_MASK (0x2U) 03651 #define LLWU_F1_WUF1_SHIFT (1U) 03652 #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK) 03653 #define LLWU_F1_WUF2_MASK (0x4U) 03654 #define LLWU_F1_WUF2_SHIFT (2U) 03655 #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK) 03656 #define LLWU_F1_WUF3_MASK (0x8U) 03657 #define LLWU_F1_WUF3_SHIFT (3U) 03658 #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK) 03659 #define LLWU_F1_WUF4_MASK (0x10U) 03660 #define LLWU_F1_WUF4_SHIFT (4U) 03661 #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK) 03662 #define LLWU_F1_WUF5_MASK (0x20U) 03663 #define LLWU_F1_WUF5_SHIFT (5U) 03664 #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK) 03665 #define LLWU_F1_WUF6_MASK (0x40U) 03666 #define LLWU_F1_WUF6_SHIFT (6U) 03667 #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK) 03668 #define LLWU_F1_WUF7_MASK (0x80U) 03669 #define LLWU_F1_WUF7_SHIFT (7U) 03670 #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK) 03671 03672 /*! @name F2 - LLWU Flag 2 Register */ 03673 #define LLWU_F2_WUF8_MASK (0x1U) 03674 #define LLWU_F2_WUF8_SHIFT (0U) 03675 #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK) 03676 #define LLWU_F2_WUF9_MASK (0x2U) 03677 #define LLWU_F2_WUF9_SHIFT (1U) 03678 #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK) 03679 #define LLWU_F2_WUF10_MASK (0x4U) 03680 #define LLWU_F2_WUF10_SHIFT (2U) 03681 #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK) 03682 #define LLWU_F2_WUF11_MASK (0x8U) 03683 #define LLWU_F2_WUF11_SHIFT (3U) 03684 #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK) 03685 #define LLWU_F2_WUF12_MASK (0x10U) 03686 #define LLWU_F2_WUF12_SHIFT (4U) 03687 #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK) 03688 #define LLWU_F2_WUF13_MASK (0x20U) 03689 #define LLWU_F2_WUF13_SHIFT (5U) 03690 #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK) 03691 #define LLWU_F2_WUF14_MASK (0x40U) 03692 #define LLWU_F2_WUF14_SHIFT (6U) 03693 #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK) 03694 #define LLWU_F2_WUF15_MASK (0x80U) 03695 #define LLWU_F2_WUF15_SHIFT (7U) 03696 #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK) 03697 03698 /*! @name F3 - LLWU Flag 3 Register */ 03699 #define LLWU_F3_MWUF0_MASK (0x1U) 03700 #define LLWU_F3_MWUF0_SHIFT (0U) 03701 #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK) 03702 #define LLWU_F3_MWUF1_MASK (0x2U) 03703 #define LLWU_F3_MWUF1_SHIFT (1U) 03704 #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK) 03705 #define LLWU_F3_MWUF2_MASK (0x4U) 03706 #define LLWU_F3_MWUF2_SHIFT (2U) 03707 #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK) 03708 #define LLWU_F3_MWUF3_MASK (0x8U) 03709 #define LLWU_F3_MWUF3_SHIFT (3U) 03710 #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK) 03711 #define LLWU_F3_MWUF4_MASK (0x10U) 03712 #define LLWU_F3_MWUF4_SHIFT (4U) 03713 #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK) 03714 #define LLWU_F3_MWUF5_MASK (0x20U) 03715 #define LLWU_F3_MWUF5_SHIFT (5U) 03716 #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK) 03717 #define LLWU_F3_MWUF6_MASK (0x40U) 03718 #define LLWU_F3_MWUF6_SHIFT (6U) 03719 #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK) 03720 #define LLWU_F3_MWUF7_MASK (0x80U) 03721 #define LLWU_F3_MWUF7_SHIFT (7U) 03722 #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK) 03723 03724 /*! @name FILT1 - LLWU Pin Filter 1 Register */ 03725 #define LLWU_FILT1_FILTSEL_MASK (0xFU) 03726 #define LLWU_FILT1_FILTSEL_SHIFT (0U) 03727 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) 03728 #define LLWU_FILT1_FILTE_MASK (0x60U) 03729 #define LLWU_FILT1_FILTE_SHIFT (5U) 03730 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) 03731 #define LLWU_FILT1_FILTF_MASK (0x80U) 03732 #define LLWU_FILT1_FILTF_SHIFT (7U) 03733 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) 03734 03735 /*! @name FILT2 - LLWU Pin Filter 2 Register */ 03736 #define LLWU_FILT2_FILTSEL_MASK (0xFU) 03737 #define LLWU_FILT2_FILTSEL_SHIFT (0U) 03738 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) 03739 #define LLWU_FILT2_FILTE_MASK (0x60U) 03740 #define LLWU_FILT2_FILTE_SHIFT (5U) 03741 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) 03742 #define LLWU_FILT2_FILTF_MASK (0x80U) 03743 #define LLWU_FILT2_FILTF_SHIFT (7U) 03744 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) 03745 03746 /*! @name RST - LLWU Reset Enable Register */ 03747 #define LLWU_RST_RSTFILT_MASK (0x1U) 03748 #define LLWU_RST_RSTFILT_SHIFT (0U) 03749 #define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK) 03750 #define LLWU_RST_LLRSTE_MASK (0x2U) 03751 #define LLWU_RST_LLRSTE_SHIFT (1U) 03752 #define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK) 03753 03754 03755 /*! 03756 * @} 03757 */ /* end of group LLWU_Register_Masks */ 03758 03759 03760 /* LLWU - Peripheral instance base addresses */ 03761 /** Peripheral LLWU base address */ 03762 #define LLWU_BASE (0x4007C000u) 03763 /** Peripheral LLWU base pointer */ 03764 #define LLWU ((LLWU_Type *)LLWU_BASE) 03765 /** Array initializer of LLWU peripheral base addresses */ 03766 #define LLWU_BASE_ADDRS { LLWU_BASE } 03767 /** Array initializer of LLWU peripheral base pointers */ 03768 #define LLWU_BASE_PTRS { LLWU } 03769 /** Interrupt vectors for the LLWU peripheral type */ 03770 #define LLWU_IRQS { LLW_IRQn } 03771 03772 /*! 03773 * @} 03774 */ /* end of group LLWU_Peripheral_Access_Layer */ 03775 03776 03777 /* ---------------------------------------------------------------------------- 03778 -- LPTMR Peripheral Access Layer 03779 ---------------------------------------------------------------------------- */ 03780 03781 /*! 03782 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer 03783 * @{ 03784 */ 03785 03786 /** LPTMR - Register Layout Typedef */ 03787 typedef struct { 03788 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ 03789 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ 03790 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ 03791 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ 03792 } LPTMR_Type; 03793 03794 /* ---------------------------------------------------------------------------- 03795 -- LPTMR Register Masks 03796 ---------------------------------------------------------------------------- */ 03797 03798 /*! 03799 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks 03800 * @{ 03801 */ 03802 03803 /*! @name CSR - Low Power Timer Control Status Register */ 03804 #define LPTMR_CSR_TEN_MASK (0x1U) 03805 #define LPTMR_CSR_TEN_SHIFT (0U) 03806 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) 03807 #define LPTMR_CSR_TMS_MASK (0x2U) 03808 #define LPTMR_CSR_TMS_SHIFT (1U) 03809 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) 03810 #define LPTMR_CSR_TFC_MASK (0x4U) 03811 #define LPTMR_CSR_TFC_SHIFT (2U) 03812 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) 03813 #define LPTMR_CSR_TPP_MASK (0x8U) 03814 #define LPTMR_CSR_TPP_SHIFT (3U) 03815 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) 03816 #define LPTMR_CSR_TPS_MASK (0x30U) 03817 #define LPTMR_CSR_TPS_SHIFT (4U) 03818 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) 03819 #define LPTMR_CSR_TIE_MASK (0x40U) 03820 #define LPTMR_CSR_TIE_SHIFT (6U) 03821 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) 03822 #define LPTMR_CSR_TCF_MASK (0x80U) 03823 #define LPTMR_CSR_TCF_SHIFT (7U) 03824 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) 03825 03826 /*! @name PSR - Low Power Timer Prescale Register */ 03827 #define LPTMR_PSR_PCS_MASK (0x3U) 03828 #define LPTMR_PSR_PCS_SHIFT (0U) 03829 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) 03830 #define LPTMR_PSR_PBYP_MASK (0x4U) 03831 #define LPTMR_PSR_PBYP_SHIFT (2U) 03832 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) 03833 #define LPTMR_PSR_PRESCALE_MASK (0x78U) 03834 #define LPTMR_PSR_PRESCALE_SHIFT (3U) 03835 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) 03836 03837 /*! @name CMR - Low Power Timer Compare Register */ 03838 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU) 03839 #define LPTMR_CMR_COMPARE_SHIFT (0U) 03840 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) 03841 03842 /*! @name CNR - Low Power Timer Counter Register */ 03843 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU) 03844 #define LPTMR_CNR_COUNTER_SHIFT (0U) 03845 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) 03846 03847 03848 /*! 03849 * @} 03850 */ /* end of group LPTMR_Register_Masks */ 03851 03852 03853 /* LPTMR - Peripheral instance base addresses */ 03854 /** Peripheral LPTMR0 base address */ 03855 #define LPTMR0_BASE (0x40040000u) 03856 /** Peripheral LPTMR0 base pointer */ 03857 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 03858 /** Array initializer of LPTMR peripheral base addresses */ 03859 #define LPTMR_BASE_ADDRS { LPTMR0_BASE } 03860 /** Array initializer of LPTMR peripheral base pointers */ 03861 #define LPTMR_BASE_PTRS { LPTMR0 } 03862 /** Interrupt vectors for the LPTMR peripheral type */ 03863 #define LPTMR_IRQS { LPTimer_IRQn } 03864 03865 /*! 03866 * @} 03867 */ /* end of group LPTMR_Peripheral_Access_Layer */ 03868 03869 03870 /* ---------------------------------------------------------------------------- 03871 -- MCG Peripheral Access Layer 03872 ---------------------------------------------------------------------------- */ 03873 03874 /*! 03875 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer 03876 * @{ 03877 */ 03878 03879 /** MCG - Register Layout Typedef */ 03880 typedef struct { 03881 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ 03882 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ 03883 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ 03884 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ 03885 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ 03886 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ 03887 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */ 03888 uint8_t RESERVED_0[1]; 03889 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ 03890 uint8_t RESERVED_1[1]; 03891 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ 03892 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ 03893 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ 03894 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ 03895 } MCG_Type; 03896 03897 /* ---------------------------------------------------------------------------- 03898 -- MCG Register Masks 03899 ---------------------------------------------------------------------------- */ 03900 03901 /*! 03902 * @addtogroup MCG_Register_Masks MCG Register Masks 03903 * @{ 03904 */ 03905 03906 /*! @name C1 - MCG Control 1 Register */ 03907 #define MCG_C1_IREFSTEN_MASK (0x1U) 03908 #define MCG_C1_IREFSTEN_SHIFT (0U) 03909 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) 03910 #define MCG_C1_IRCLKEN_MASK (0x2U) 03911 #define MCG_C1_IRCLKEN_SHIFT (1U) 03912 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) 03913 #define MCG_C1_IREFS_MASK (0x4U) 03914 #define MCG_C1_IREFS_SHIFT (2U) 03915 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK) 03916 #define MCG_C1_FRDIV_MASK (0x38U) 03917 #define MCG_C1_FRDIV_SHIFT (3U) 03918 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK) 03919 #define MCG_C1_CLKS_MASK (0xC0U) 03920 #define MCG_C1_CLKS_SHIFT (6U) 03921 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) 03922 03923 /*! @name C2 - MCG Control 2 Register */ 03924 #define MCG_C2_IRCS_MASK (0x1U) 03925 #define MCG_C2_IRCS_SHIFT (0U) 03926 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) 03927 #define MCG_C2_LP_MASK (0x2U) 03928 #define MCG_C2_LP_SHIFT (1U) 03929 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK) 03930 #define MCG_C2_EREFS0_MASK (0x4U) 03931 #define MCG_C2_EREFS0_SHIFT (2U) 03932 #define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK) 03933 #define MCG_C2_HGO0_MASK (0x8U) 03934 #define MCG_C2_HGO0_SHIFT (3U) 03935 #define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK) 03936 #define MCG_C2_RANGE0_MASK (0x30U) 03937 #define MCG_C2_RANGE0_SHIFT (4U) 03938 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK) 03939 #define MCG_C2_LOCRE0_MASK (0x80U) 03940 #define MCG_C2_LOCRE0_SHIFT (7U) 03941 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK) 03942 03943 /*! @name C3 - MCG Control 3 Register */ 03944 #define MCG_C3_SCTRIM_MASK (0xFFU) 03945 #define MCG_C3_SCTRIM_SHIFT (0U) 03946 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK) 03947 03948 /*! @name C4 - MCG Control 4 Register */ 03949 #define MCG_C4_SCFTRIM_MASK (0x1U) 03950 #define MCG_C4_SCFTRIM_SHIFT (0U) 03951 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK) 03952 #define MCG_C4_FCTRIM_MASK (0x1EU) 03953 #define MCG_C4_FCTRIM_SHIFT (1U) 03954 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK) 03955 #define MCG_C4_DRST_DRS_MASK (0x60U) 03956 #define MCG_C4_DRST_DRS_SHIFT (5U) 03957 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK) 03958 #define MCG_C4_DMX32_MASK (0x80U) 03959 #define MCG_C4_DMX32_SHIFT (7U) 03960 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK) 03961 03962 /*! @name C5 - MCG Control 5 Register */ 03963 #define MCG_C5_PRDIV0_MASK (0x1FU) 03964 #define MCG_C5_PRDIV0_SHIFT (0U) 03965 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK) 03966 #define MCG_C5_PLLSTEN0_MASK (0x20U) 03967 #define MCG_C5_PLLSTEN0_SHIFT (5U) 03968 #define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK) 03969 #define MCG_C5_PLLCLKEN0_MASK (0x40U) 03970 #define MCG_C5_PLLCLKEN0_SHIFT (6U) 03971 #define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK) 03972 03973 /*! @name C6 - MCG Control 6 Register */ 03974 #define MCG_C6_VDIV0_MASK (0x1FU) 03975 #define MCG_C6_VDIV0_SHIFT (0U) 03976 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK) 03977 #define MCG_C6_CME0_MASK (0x20U) 03978 #define MCG_C6_CME0_SHIFT (5U) 03979 #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK) 03980 #define MCG_C6_PLLS_MASK (0x40U) 03981 #define MCG_C6_PLLS_SHIFT (6U) 03982 #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK) 03983 #define MCG_C6_LOLIE0_MASK (0x80U) 03984 #define MCG_C6_LOLIE0_SHIFT (7U) 03985 #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK) 03986 03987 /*! @name S - MCG Status Register */ 03988 #define MCG_S_IRCST_MASK (0x1U) 03989 #define MCG_S_IRCST_SHIFT (0U) 03990 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK) 03991 #define MCG_S_OSCINIT0_MASK (0x2U) 03992 #define MCG_S_OSCINIT0_SHIFT (1U) 03993 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) 03994 #define MCG_S_CLKST_MASK (0xCU) 03995 #define MCG_S_CLKST_SHIFT (2U) 03996 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) 03997 #define MCG_S_IREFST_MASK (0x10U) 03998 #define MCG_S_IREFST_SHIFT (4U) 03999 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK) 04000 #define MCG_S_PLLST_MASK (0x20U) 04001 #define MCG_S_PLLST_SHIFT (5U) 04002 #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK) 04003 #define MCG_S_LOCK0_MASK (0x40U) 04004 #define MCG_S_LOCK0_SHIFT (6U) 04005 #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK) 04006 #define MCG_S_LOLS0_MASK (0x80U) 04007 #define MCG_S_LOLS0_SHIFT (7U) 04008 #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK) 04009 04010 /*! @name SC - MCG Status and Control Register */ 04011 #define MCG_SC_LOCS0_MASK (0x1U) 04012 #define MCG_SC_LOCS0_SHIFT (0U) 04013 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK) 04014 #define MCG_SC_FCRDIV_MASK (0xEU) 04015 #define MCG_SC_FCRDIV_SHIFT (1U) 04016 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) 04017 #define MCG_SC_FLTPRSRV_MASK (0x10U) 04018 #define MCG_SC_FLTPRSRV_SHIFT (4U) 04019 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK) 04020 #define MCG_SC_ATMF_MASK (0x20U) 04021 #define MCG_SC_ATMF_SHIFT (5U) 04022 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK) 04023 #define MCG_SC_ATMS_MASK (0x40U) 04024 #define MCG_SC_ATMS_SHIFT (6U) 04025 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK) 04026 #define MCG_SC_ATME_MASK (0x80U) 04027 #define MCG_SC_ATME_SHIFT (7U) 04028 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK) 04029 04030 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */ 04031 #define MCG_ATCVH_ATCVH_MASK (0xFFU) 04032 #define MCG_ATCVH_ATCVH_SHIFT (0U) 04033 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK) 04034 04035 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */ 04036 #define MCG_ATCVL_ATCVL_MASK (0xFFU) 04037 #define MCG_ATCVL_ATCVL_SHIFT (0U) 04038 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK) 04039 04040 /*! @name C7 - MCG Control 7 Register */ 04041 #define MCG_C7_OSCSEL_MASK (0x1U) 04042 #define MCG_C7_OSCSEL_SHIFT (0U) 04043 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK) 04044 04045 /*! @name C8 - MCG Control 8 Register */ 04046 #define MCG_C8_LOCS1_MASK (0x1U) 04047 #define MCG_C8_LOCS1_SHIFT (0U) 04048 #define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK) 04049 #define MCG_C8_CME1_MASK (0x20U) 04050 #define MCG_C8_CME1_SHIFT (5U) 04051 #define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK) 04052 #define MCG_C8_LOLRE_MASK (0x40U) 04053 #define MCG_C8_LOLRE_SHIFT (6U) 04054 #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK) 04055 #define MCG_C8_LOCRE1_MASK (0x80U) 04056 #define MCG_C8_LOCRE1_SHIFT (7U) 04057 #define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK) 04058 04059 04060 /*! 04061 * @} 04062 */ /* end of group MCG_Register_Masks */ 04063 04064 04065 /* MCG - Peripheral instance base addresses */ 04066 /** Peripheral MCG base address */ 04067 #define MCG_BASE (0x40064000u) 04068 /** Peripheral MCG base pointer */ 04069 #define MCG ((MCG_Type *)MCG_BASE) 04070 /** Array initializer of MCG peripheral base addresses */ 04071 #define MCG_BASE_ADDRS { MCG_BASE } 04072 /** Array initializer of MCG peripheral base pointers */ 04073 #define MCG_BASE_PTRS { MCG } 04074 /* MCG C2[EREFS] backward compatibility */ 04075 #define MCG_C2_EREFS_MASK (MCG_C2_EREFS0_MASK) 04076 #define MCG_C2_EREFS_SHIFT (MCG_C2_EREFS0_SHIFT) 04077 #define MCG_C2_EREFS_WIDTH (MCG_C2_EREFS0_WIDTH) 04078 #define MCG_C2_EREFS(x) (MCG_C2_EREFS0(x)) 04079 04080 /* MCG C2[HGO] backward compatibility */ 04081 #define MCG_C2_HGO_MASK (MCG_C2_HGO0_MASK) 04082 #define MCG_C2_HGO_SHIFT (MCG_C2_HGO0_SHIFT) 04083 #define MCG_C2_HGO_WIDTH (MCG_C2_HGO0_WIDTH) 04084 #define MCG_C2_HGO(x) (MCG_C2_HGO0(x)) 04085 04086 /* MCG C2[RANGE] backward compatibility */ 04087 #define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK) 04088 #define MCG_C2_RANGE_SHIFT (MCG_C2_RANGE0_SHIFT) 04089 #define MCG_C2_RANGE_WIDTH (MCG_C2_RANGE0_WIDTH) 04090 #define MCG_C2_RANGE(x) (MCG_C2_RANGE0(x)) 04091 04092 04093 /*! 04094 * @} 04095 */ /* end of group MCG_Peripheral_Access_Layer */ 04096 04097 04098 /* ---------------------------------------------------------------------------- 04099 -- NV Peripheral Access Layer 04100 ---------------------------------------------------------------------------- */ 04101 04102 /*! 04103 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer 04104 * @{ 04105 */ 04106 04107 /** NV - Register Layout Typedef */ 04108 typedef struct { 04109 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ 04110 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ 04111 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ 04112 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ 04113 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ 04114 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ 04115 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ 04116 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ 04117 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ 04118 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ 04119 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ 04120 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ 04121 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ 04122 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ 04123 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */ 04124 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */ 04125 } NV_Type; 04126 04127 /* ---------------------------------------------------------------------------- 04128 -- NV Register Masks 04129 ---------------------------------------------------------------------------- */ 04130 04131 /*! 04132 * @addtogroup NV_Register_Masks NV Register Masks 04133 * @{ 04134 */ 04135 04136 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */ 04137 #define NV_BACKKEY3_KEY_MASK (0xFFU) 04138 #define NV_BACKKEY3_KEY_SHIFT (0U) 04139 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) 04140 04141 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */ 04142 #define NV_BACKKEY2_KEY_MASK (0xFFU) 04143 #define NV_BACKKEY2_KEY_SHIFT (0U) 04144 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) 04145 04146 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */ 04147 #define NV_BACKKEY1_KEY_MASK (0xFFU) 04148 #define NV_BACKKEY1_KEY_SHIFT (0U) 04149 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) 04150 04151 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */ 04152 #define NV_BACKKEY0_KEY_MASK (0xFFU) 04153 #define NV_BACKKEY0_KEY_SHIFT (0U) 04154 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) 04155 04156 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */ 04157 #define NV_BACKKEY7_KEY_MASK (0xFFU) 04158 #define NV_BACKKEY7_KEY_SHIFT (0U) 04159 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) 04160 04161 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */ 04162 #define NV_BACKKEY6_KEY_MASK (0xFFU) 04163 #define NV_BACKKEY6_KEY_SHIFT (0U) 04164 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) 04165 04166 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */ 04167 #define NV_BACKKEY5_KEY_MASK (0xFFU) 04168 #define NV_BACKKEY5_KEY_SHIFT (0U) 04169 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) 04170 04171 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */ 04172 #define NV_BACKKEY4_KEY_MASK (0xFFU) 04173 #define NV_BACKKEY4_KEY_SHIFT (0U) 04174 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) 04175 04176 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ 04177 #define NV_FPROT3_PROT_MASK (0xFFU) 04178 #define NV_FPROT3_PROT_SHIFT (0U) 04179 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) 04180 04181 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ 04182 #define NV_FPROT2_PROT_MASK (0xFFU) 04183 #define NV_FPROT2_PROT_SHIFT (0U) 04184 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) 04185 04186 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ 04187 #define NV_FPROT1_PROT_MASK (0xFFU) 04188 #define NV_FPROT1_PROT_SHIFT (0U) 04189 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) 04190 04191 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ 04192 #define NV_FPROT0_PROT_MASK (0xFFU) 04193 #define NV_FPROT0_PROT_SHIFT (0U) 04194 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) 04195 04196 /*! @name FSEC - Non-volatile Flash Security Register */ 04197 #define NV_FSEC_SEC_MASK (0x3U) 04198 #define NV_FSEC_SEC_SHIFT (0U) 04199 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) 04200 #define NV_FSEC_FSLACC_MASK (0xCU) 04201 #define NV_FSEC_FSLACC_SHIFT (2U) 04202 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) 04203 #define NV_FSEC_MEEN_MASK (0x30U) 04204 #define NV_FSEC_MEEN_SHIFT (4U) 04205 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) 04206 #define NV_FSEC_KEYEN_MASK (0xC0U) 04207 #define NV_FSEC_KEYEN_SHIFT (6U) 04208 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) 04209 04210 /*! @name FOPT - Non-volatile Flash Option Register */ 04211 #define NV_FOPT_LPBOOT_MASK (0x1U) 04212 #define NV_FOPT_LPBOOT_SHIFT (0U) 04213 #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK) 04214 #define NV_FOPT_EZPORT_DIS_MASK (0x2U) 04215 #define NV_FOPT_EZPORT_DIS_SHIFT (1U) 04216 #define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK) 04217 #define NV_FOPT_NMI_DIS_MASK (0x4U) 04218 #define NV_FOPT_NMI_DIS_SHIFT (2U) 04219 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK) 04220 04221 /*! @name FEPROT - Non-volatile EERAM Protection Register */ 04222 #define NV_FEPROT_EPROT_MASK (0xFFU) 04223 #define NV_FEPROT_EPROT_SHIFT (0U) 04224 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK) 04225 04226 /*! @name FDPROT - Non-volatile D-Flash Protection Register */ 04227 #define NV_FDPROT_DPROT_MASK (0xFFU) 04228 #define NV_FDPROT_DPROT_SHIFT (0U) 04229 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK) 04230 04231 04232 /*! 04233 * @} 04234 */ /* end of group NV_Register_Masks */ 04235 04236 04237 /* NV - Peripheral instance base addresses */ 04238 /** Peripheral FTFL_FlashConfig base address */ 04239 #define FTFL_FlashConfig_BASE (0x400u) 04240 /** Peripheral FTFL_FlashConfig base pointer */ 04241 #define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE) 04242 /** Array initializer of NV peripheral base addresses */ 04243 #define NV_BASE_ADDRS { FTFL_FlashConfig_BASE } 04244 /** Array initializer of NV peripheral base pointers */ 04245 #define NV_BASE_PTRS { FTFL_FlashConfig } 04246 04247 /*! 04248 * @} 04249 */ /* end of group NV_Peripheral_Access_Layer */ 04250 04251 04252 /* ---------------------------------------------------------------------------- 04253 -- OSC Peripheral Access Layer 04254 ---------------------------------------------------------------------------- */ 04255 04256 /*! 04257 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer 04258 * @{ 04259 */ 04260 04261 /** OSC - Register Layout Typedef */ 04262 typedef struct { 04263 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ 04264 } OSC_Type; 04265 04266 /* ---------------------------------------------------------------------------- 04267 -- OSC Register Masks 04268 ---------------------------------------------------------------------------- */ 04269 04270 /*! 04271 * @addtogroup OSC_Register_Masks OSC Register Masks 04272 * @{ 04273 */ 04274 04275 /*! @name CR - OSC Control Register */ 04276 #define OSC_CR_SC16P_MASK (0x1U) 04277 #define OSC_CR_SC16P_SHIFT (0U) 04278 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) 04279 #define OSC_CR_SC8P_MASK (0x2U) 04280 #define OSC_CR_SC8P_SHIFT (1U) 04281 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) 04282 #define OSC_CR_SC4P_MASK (0x4U) 04283 #define OSC_CR_SC4P_SHIFT (2U) 04284 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) 04285 #define OSC_CR_SC2P_MASK (0x8U) 04286 #define OSC_CR_SC2P_SHIFT (3U) 04287 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) 04288 #define OSC_CR_EREFSTEN_MASK (0x20U) 04289 #define OSC_CR_EREFSTEN_SHIFT (5U) 04290 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) 04291 #define OSC_CR_ERCLKEN_MASK (0x80U) 04292 #define OSC_CR_ERCLKEN_SHIFT (7U) 04293 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) 04294 04295 04296 /*! 04297 * @} 04298 */ /* end of group OSC_Register_Masks */ 04299 04300 04301 /* OSC - Peripheral instance base addresses */ 04302 /** Peripheral OSC0 base address */ 04303 #define OSC0_BASE (0x40065000u) 04304 /** Peripheral OSC0 base pointer */ 04305 #define OSC0 ((OSC_Type *)OSC0_BASE) 04306 /** Array initializer of OSC peripheral base addresses */ 04307 #define OSC_BASE_ADDRS { OSC0_BASE } 04308 /** Array initializer of OSC peripheral base pointers */ 04309 #define OSC_BASE_PTRS { OSC0 } 04310 04311 /*! 04312 * @} 04313 */ /* end of group OSC_Peripheral_Access_Layer */ 04314 04315 04316 /* ---------------------------------------------------------------------------- 04317 -- PDB Peripheral Access Layer 04318 ---------------------------------------------------------------------------- */ 04319 04320 /*! 04321 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer 04322 * @{ 04323 */ 04324 04325 /** PDB - Register Layout Typedef */ 04326 typedef struct { 04327 __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */ 04328 __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */ 04329 __I uint32_t CNT; /**< Counter Register, offset: 0x8 */ 04330 __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */ 04331 struct { /* offset: 0x10, array step: 0x10 */ 04332 __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */ 04333 __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */ 04334 __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */ 04335 } CH[1]; 04336 uint8_t RESERVED_0[368]; 04337 __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */ 04338 __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */ 04339 } PDB_Type; 04340 04341 /* ---------------------------------------------------------------------------- 04342 -- PDB Register Masks 04343 ---------------------------------------------------------------------------- */ 04344 04345 /*! 04346 * @addtogroup PDB_Register_Masks PDB Register Masks 04347 * @{ 04348 */ 04349 04350 /*! @name SC - Status and Control Register */ 04351 #define PDB_SC_LDOK_MASK (0x1U) 04352 #define PDB_SC_LDOK_SHIFT (0U) 04353 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK) 04354 #define PDB_SC_CONT_MASK (0x2U) 04355 #define PDB_SC_CONT_SHIFT (1U) 04356 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK) 04357 #define PDB_SC_MULT_MASK (0xCU) 04358 #define PDB_SC_MULT_SHIFT (2U) 04359 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK) 04360 #define PDB_SC_PDBIE_MASK (0x20U) 04361 #define PDB_SC_PDBIE_SHIFT (5U) 04362 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK) 04363 #define PDB_SC_PDBIF_MASK (0x40U) 04364 #define PDB_SC_PDBIF_SHIFT (6U) 04365 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK) 04366 #define PDB_SC_PDBEN_MASK (0x80U) 04367 #define PDB_SC_PDBEN_SHIFT (7U) 04368 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK) 04369 #define PDB_SC_TRGSEL_MASK (0xF00U) 04370 #define PDB_SC_TRGSEL_SHIFT (8U) 04371 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK) 04372 #define PDB_SC_PRESCALER_MASK (0x7000U) 04373 #define PDB_SC_PRESCALER_SHIFT (12U) 04374 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK) 04375 #define PDB_SC_DMAEN_MASK (0x8000U) 04376 #define PDB_SC_DMAEN_SHIFT (15U) 04377 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK) 04378 #define PDB_SC_SWTRIG_MASK (0x10000U) 04379 #define PDB_SC_SWTRIG_SHIFT (16U) 04380 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK) 04381 #define PDB_SC_PDBEIE_MASK (0x20000U) 04382 #define PDB_SC_PDBEIE_SHIFT (17U) 04383 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK) 04384 #define PDB_SC_LDMOD_MASK (0xC0000U) 04385 #define PDB_SC_LDMOD_SHIFT (18U) 04386 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK) 04387 04388 /*! @name MOD - Modulus Register */ 04389 #define PDB_MOD_MOD_MASK (0xFFFFU) 04390 #define PDB_MOD_MOD_SHIFT (0U) 04391 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK) 04392 04393 /*! @name CNT - Counter Register */ 04394 #define PDB_CNT_CNT_MASK (0xFFFFU) 04395 #define PDB_CNT_CNT_SHIFT (0U) 04396 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK) 04397 04398 /*! @name IDLY - Interrupt Delay Register */ 04399 #define PDB_IDLY_IDLY_MASK (0xFFFFU) 04400 #define PDB_IDLY_IDLY_SHIFT (0U) 04401 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK) 04402 04403 /*! @name C1 - Channel n Control Register 1 */ 04404 #define PDB_C1_EN_MASK (0xFFU) 04405 #define PDB_C1_EN_SHIFT (0U) 04406 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK) 04407 #define PDB_C1_TOS_MASK (0xFF00U) 04408 #define PDB_C1_TOS_SHIFT (8U) 04409 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK) 04410 #define PDB_C1_BB_MASK (0xFF0000U) 04411 #define PDB_C1_BB_SHIFT (16U) 04412 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK) 04413 04414 /* The count of PDB_C1 */ 04415 #define PDB_C1_COUNT (1U) 04416 04417 /*! @name S - Channel n Status Register */ 04418 #define PDB_S_ERR_MASK (0xFFU) 04419 #define PDB_S_ERR_SHIFT (0U) 04420 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK) 04421 #define PDB_S_CF_MASK (0xFF0000U) 04422 #define PDB_S_CF_SHIFT (16U) 04423 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK) 04424 04425 /* The count of PDB_S */ 04426 #define PDB_S_COUNT (1U) 04427 04428 /*! @name DLY - Channel n Delay 0 Register..Channel n Delay 1 Register */ 04429 #define PDB_DLY_DLY_MASK (0xFFFFU) 04430 #define PDB_DLY_DLY_SHIFT (0U) 04431 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK) 04432 04433 /* The count of PDB_DLY */ 04434 #define PDB_DLY_COUNT (1U) 04435 04436 /* The count of PDB_DLY */ 04437 #define PDB_DLY_COUNT2 (2U) 04438 04439 /*! @name POEN - Pulse-Out n Enable Register */ 04440 #define PDB_POEN_POEN_MASK (0xFFU) 04441 #define PDB_POEN_POEN_SHIFT (0U) 04442 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK) 04443 04444 /*! @name PODLY - Pulse-Out n Delay Register */ 04445 #define PDB_PODLY_DLY2_MASK (0xFFFFU) 04446 #define PDB_PODLY_DLY2_SHIFT (0U) 04447 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK) 04448 #define PDB_PODLY_DLY1_MASK (0xFFFF0000U) 04449 #define PDB_PODLY_DLY1_SHIFT (16U) 04450 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK) 04451 04452 /* The count of PDB_PODLY */ 04453 #define PDB_PODLY_COUNT (2U) 04454 04455 04456 /*! 04457 * @} 04458 */ /* end of group PDB_Register_Masks */ 04459 04460 04461 /* PDB - Peripheral instance base addresses */ 04462 /** Peripheral PDB0 base address */ 04463 #define PDB0_BASE (0x40036000u) 04464 /** Peripheral PDB0 base pointer */ 04465 #define PDB0 ((PDB_Type *)PDB0_BASE) 04466 /** Array initializer of PDB peripheral base addresses */ 04467 #define PDB_BASE_ADDRS { PDB0_BASE } 04468 /** Array initializer of PDB peripheral base pointers */ 04469 #define PDB_BASE_PTRS { PDB0 } 04470 /** Interrupt vectors for the PDB peripheral type */ 04471 #define PDB_IRQS { PDB0_IRQn } 04472 04473 /*! 04474 * @} 04475 */ /* end of group PDB_Peripheral_Access_Layer */ 04476 04477 04478 /* ---------------------------------------------------------------------------- 04479 -- PIT Peripheral Access Layer 04480 ---------------------------------------------------------------------------- */ 04481 04482 /*! 04483 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer 04484 * @{ 04485 */ 04486 04487 /** PIT - Register Layout Typedef */ 04488 typedef struct { 04489 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ 04490 uint8_t RESERVED_0[252]; 04491 struct { /* offset: 0x100, array step: 0x10 */ 04492 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ 04493 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ 04494 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ 04495 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ 04496 } CHANNEL[4]; 04497 } PIT_Type; 04498 04499 /* ---------------------------------------------------------------------------- 04500 -- PIT Register Masks 04501 ---------------------------------------------------------------------------- */ 04502 04503 /*! 04504 * @addtogroup PIT_Register_Masks PIT Register Masks 04505 * @{ 04506 */ 04507 04508 /*! @name MCR - PIT Module Control Register */ 04509 #define PIT_MCR_FRZ_MASK (0x1U) 04510 #define PIT_MCR_FRZ_SHIFT (0U) 04511 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) 04512 #define PIT_MCR_MDIS_MASK (0x2U) 04513 #define PIT_MCR_MDIS_SHIFT (1U) 04514 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) 04515 04516 /*! @name LDVAL - Timer Load Value Register */ 04517 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) 04518 #define PIT_LDVAL_TSV_SHIFT (0U) 04519 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) 04520 04521 /* The count of PIT_LDVAL */ 04522 #define PIT_LDVAL_COUNT (4U) 04523 04524 /*! @name CVAL - Current Timer Value Register */ 04525 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) 04526 #define PIT_CVAL_TVL_SHIFT (0U) 04527 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) 04528 04529 /* The count of PIT_CVAL */ 04530 #define PIT_CVAL_COUNT (4U) 04531 04532 /*! @name TCTRL - Timer Control Register */ 04533 #define PIT_TCTRL_TEN_MASK (0x1U) 04534 #define PIT_TCTRL_TEN_SHIFT (0U) 04535 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) 04536 #define PIT_TCTRL_TIE_MASK (0x2U) 04537 #define PIT_TCTRL_TIE_SHIFT (1U) 04538 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) 04539 04540 /* The count of PIT_TCTRL */ 04541 #define PIT_TCTRL_COUNT (4U) 04542 04543 /*! @name TFLG - Timer Flag Register */ 04544 #define PIT_TFLG_TIF_MASK (0x1U) 04545 #define PIT_TFLG_TIF_SHIFT (0U) 04546 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) 04547 04548 /* The count of PIT_TFLG */ 04549 #define PIT_TFLG_COUNT (4U) 04550 04551 04552 /*! 04553 * @} 04554 */ /* end of group PIT_Register_Masks */ 04555 04556 04557 /* PIT - Peripheral instance base addresses */ 04558 /** Peripheral PIT base address */ 04559 #define PIT_BASE (0x40037000u) 04560 /** Peripheral PIT base pointer */ 04561 #define PIT ((PIT_Type *)PIT_BASE) 04562 /** Array initializer of PIT peripheral base addresses */ 04563 #define PIT_BASE_ADDRS { PIT_BASE } 04564 /** Array initializer of PIT peripheral base pointers */ 04565 #define PIT_BASE_PTRS { PIT } 04566 /** Interrupt vectors for the PIT peripheral type */ 04567 #define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } 04568 04569 /*! 04570 * @} 04571 */ /* end of group PIT_Peripheral_Access_Layer */ 04572 04573 04574 /* ---------------------------------------------------------------------------- 04575 -- PMC Peripheral Access Layer 04576 ---------------------------------------------------------------------------- */ 04577 04578 /*! 04579 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer 04580 * @{ 04581 */ 04582 04583 /** PMC - Register Layout Typedef */ 04584 typedef struct { 04585 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */ 04586 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */ 04587 __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */ 04588 } PMC_Type; 04589 04590 /* ---------------------------------------------------------------------------- 04591 -- PMC Register Masks 04592 ---------------------------------------------------------------------------- */ 04593 04594 /*! 04595 * @addtogroup PMC_Register_Masks PMC Register Masks 04596 * @{ 04597 */ 04598 04599 /*! @name LVDSC1 - Low Voltage Detect Status and Control 1 Register */ 04600 #define PMC_LVDSC1_LVDV_MASK (0x3U) 04601 #define PMC_LVDSC1_LVDV_SHIFT (0U) 04602 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) 04603 #define PMC_LVDSC1_LVDRE_MASK (0x10U) 04604 #define PMC_LVDSC1_LVDRE_SHIFT (4U) 04605 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) 04606 #define PMC_LVDSC1_LVDIE_MASK (0x20U) 04607 #define PMC_LVDSC1_LVDIE_SHIFT (5U) 04608 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) 04609 #define PMC_LVDSC1_LVDACK_MASK (0x40U) 04610 #define PMC_LVDSC1_LVDACK_SHIFT (6U) 04611 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) 04612 #define PMC_LVDSC1_LVDF_MASK (0x80U) 04613 #define PMC_LVDSC1_LVDF_SHIFT (7U) 04614 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) 04615 04616 /*! @name LVDSC2 - Low Voltage Detect Status and Control 2 Register */ 04617 #define PMC_LVDSC2_LVWV_MASK (0x3U) 04618 #define PMC_LVDSC2_LVWV_SHIFT (0U) 04619 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) 04620 #define PMC_LVDSC2_LVWIE_MASK (0x20U) 04621 #define PMC_LVDSC2_LVWIE_SHIFT (5U) 04622 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) 04623 #define PMC_LVDSC2_LVWACK_MASK (0x40U) 04624 #define PMC_LVDSC2_LVWACK_SHIFT (6U) 04625 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) 04626 #define PMC_LVDSC2_LVWF_MASK (0x80U) 04627 #define PMC_LVDSC2_LVWF_SHIFT (7U) 04628 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) 04629 04630 /*! @name REGSC - Regulator Status and Control Register */ 04631 #define PMC_REGSC_BGBE_MASK (0x1U) 04632 #define PMC_REGSC_BGBE_SHIFT (0U) 04633 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) 04634 #define PMC_REGSC_REGONS_MASK (0x4U) 04635 #define PMC_REGSC_REGONS_SHIFT (2U) 04636 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) 04637 #define PMC_REGSC_ACKISO_MASK (0x8U) 04638 #define PMC_REGSC_ACKISO_SHIFT (3U) 04639 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) 04640 04641 04642 /*! 04643 * @} 04644 */ /* end of group PMC_Register_Masks */ 04645 04646 04647 /* PMC - Peripheral instance base addresses */ 04648 /** Peripheral PMC base address */ 04649 #define PMC_BASE (0x4007D000u) 04650 /** Peripheral PMC base pointer */ 04651 #define PMC ((PMC_Type *)PMC_BASE) 04652 /** Array initializer of PMC peripheral base addresses */ 04653 #define PMC_BASE_ADDRS { PMC_BASE } 04654 /** Array initializer of PMC peripheral base pointers */ 04655 #define PMC_BASE_PTRS { PMC } 04656 /** Interrupt vectors for the PMC peripheral type */ 04657 #define PMC_IRQS { LVD_LVW_IRQn } 04658 04659 /*! 04660 * @} 04661 */ /* end of group PMC_Peripheral_Access_Layer */ 04662 04663 04664 /* ---------------------------------------------------------------------------- 04665 -- PORT Peripheral Access Layer 04666 ---------------------------------------------------------------------------- */ 04667 04668 /*! 04669 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer 04670 * @{ 04671 */ 04672 04673 /** PORT - Register Layout Typedef */ 04674 typedef struct { 04675 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ 04676 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ 04677 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ 04678 uint8_t RESERVED_0[24]; 04679 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ 04680 uint8_t RESERVED_1[28]; 04681 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ 04682 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ 04683 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ 04684 } PORT_Type; 04685 04686 /* ---------------------------------------------------------------------------- 04687 -- PORT Register Masks 04688 ---------------------------------------------------------------------------- */ 04689 04690 /*! 04691 * @addtogroup PORT_Register_Masks PORT Register Masks 04692 * @{ 04693 */ 04694 04695 /*! @name PCR - Pin Control Register n */ 04696 #define PORT_PCR_PS_MASK (0x1U) 04697 #define PORT_PCR_PS_SHIFT (0U) 04698 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) 04699 #define PORT_PCR_PE_MASK (0x2U) 04700 #define PORT_PCR_PE_SHIFT (1U) 04701 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) 04702 #define PORT_PCR_SRE_MASK (0x4U) 04703 #define PORT_PCR_SRE_SHIFT (2U) 04704 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) 04705 #define PORT_PCR_PFE_MASK (0x10U) 04706 #define PORT_PCR_PFE_SHIFT (4U) 04707 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) 04708 #define PORT_PCR_ODE_MASK (0x20U) 04709 #define PORT_PCR_ODE_SHIFT (5U) 04710 #define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) 04711 #define PORT_PCR_DSE_MASK (0x40U) 04712 #define PORT_PCR_DSE_SHIFT (6U) 04713 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) 04714 #define PORT_PCR_MUX_MASK (0x700U) 04715 #define PORT_PCR_MUX_SHIFT (8U) 04716 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) 04717 #define PORT_PCR_LK_MASK (0x8000U) 04718 #define PORT_PCR_LK_SHIFT (15U) 04719 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) 04720 #define PORT_PCR_IRQC_MASK (0xF0000U) 04721 #define PORT_PCR_IRQC_SHIFT (16U) 04722 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) 04723 #define PORT_PCR_ISF_MASK (0x1000000U) 04724 #define PORT_PCR_ISF_SHIFT (24U) 04725 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) 04726 04727 /* The count of PORT_PCR */ 04728 #define PORT_PCR_COUNT (32U) 04729 04730 /*! @name GPCLR - Global Pin Control Low Register */ 04731 #define PORT_GPCLR_GPWD_MASK (0xFFFFU) 04732 #define PORT_GPCLR_GPWD_SHIFT (0U) 04733 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) 04734 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) 04735 #define PORT_GPCLR_GPWE_SHIFT (16U) 04736 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) 04737 04738 /*! @name GPCHR - Global Pin Control High Register */ 04739 #define PORT_GPCHR_GPWD_MASK (0xFFFFU) 04740 #define PORT_GPCHR_GPWD_SHIFT (0U) 04741 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) 04742 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) 04743 #define PORT_GPCHR_GPWE_SHIFT (16U) 04744 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) 04745 04746 /*! @name ISFR - Interrupt Status Flag Register */ 04747 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) 04748 #define PORT_ISFR_ISF_SHIFT (0U) 04749 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) 04750 04751 /*! @name DFER - Digital Filter Enable Register */ 04752 #define PORT_DFER_DFE_MASK (0xFFFFFFFFU) 04753 #define PORT_DFER_DFE_SHIFT (0U) 04754 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK) 04755 04756 /*! @name DFCR - Digital Filter Clock Register */ 04757 #define PORT_DFCR_CS_MASK (0x1U) 04758 #define PORT_DFCR_CS_SHIFT (0U) 04759 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK) 04760 04761 /*! @name DFWR - Digital Filter Width Register */ 04762 #define PORT_DFWR_FILT_MASK (0x1FU) 04763 #define PORT_DFWR_FILT_SHIFT (0U) 04764 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK) 04765 04766 04767 /*! 04768 * @} 04769 */ /* end of group PORT_Register_Masks */ 04770 04771 04772 /* PORT - Peripheral instance base addresses */ 04773 /** Peripheral PORTA base address */ 04774 #define PORTA_BASE (0x40049000u) 04775 /** Peripheral PORTA base pointer */ 04776 #define PORTA ((PORT_Type *)PORTA_BASE) 04777 /** Peripheral PORTB base address */ 04778 #define PORTB_BASE (0x4004A000u) 04779 /** Peripheral PORTB base pointer */ 04780 #define PORTB ((PORT_Type *)PORTB_BASE) 04781 /** Peripheral PORTC base address */ 04782 #define PORTC_BASE (0x4004B000u) 04783 /** Peripheral PORTC base pointer */ 04784 #define PORTC ((PORT_Type *)PORTC_BASE) 04785 /** Peripheral PORTD base address */ 04786 #define PORTD_BASE (0x4004C000u) 04787 /** Peripheral PORTD base pointer */ 04788 #define PORTD ((PORT_Type *)PORTD_BASE) 04789 /** Peripheral PORTE base address */ 04790 #define PORTE_BASE (0x4004D000u) 04791 /** Peripheral PORTE base pointer */ 04792 #define PORTE ((PORT_Type *)PORTE_BASE) 04793 /** Array initializer of PORT peripheral base addresses */ 04794 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } 04795 /** Array initializer of PORT peripheral base pointers */ 04796 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } 04797 /** Interrupt vectors for the PORT peripheral type */ 04798 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn } 04799 04800 /*! 04801 * @} 04802 */ /* end of group PORT_Peripheral_Access_Layer */ 04803 04804 04805 /* ---------------------------------------------------------------------------- 04806 -- RCM Peripheral Access Layer 04807 ---------------------------------------------------------------------------- */ 04808 04809 /*! 04810 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer 04811 * @{ 04812 */ 04813 04814 /** RCM - Register Layout Typedef */ 04815 typedef struct { 04816 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ 04817 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ 04818 uint8_t RESERVED_0[2]; 04819 __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */ 04820 __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */ 04821 uint8_t RESERVED_1[1]; 04822 __I uint8_t MR; /**< Mode Register, offset: 0x7 */ 04823 } RCM_Type; 04824 04825 /* ---------------------------------------------------------------------------- 04826 -- RCM Register Masks 04827 ---------------------------------------------------------------------------- */ 04828 04829 /*! 04830 * @addtogroup RCM_Register_Masks RCM Register Masks 04831 * @{ 04832 */ 04833 04834 /*! @name SRS0 - System Reset Status Register 0 */ 04835 #define RCM_SRS0_WAKEUP_MASK (0x1U) 04836 #define RCM_SRS0_WAKEUP_SHIFT (0U) 04837 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) 04838 #define RCM_SRS0_LVD_MASK (0x2U) 04839 #define RCM_SRS0_LVD_SHIFT (1U) 04840 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) 04841 #define RCM_SRS0_LOC_MASK (0x4U) 04842 #define RCM_SRS0_LOC_SHIFT (2U) 04843 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK) 04844 #define RCM_SRS0_LOL_MASK (0x8U) 04845 #define RCM_SRS0_LOL_SHIFT (3U) 04846 #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK) 04847 #define RCM_SRS0_WDOG_MASK (0x20U) 04848 #define RCM_SRS0_WDOG_SHIFT (5U) 04849 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) 04850 #define RCM_SRS0_PIN_MASK (0x40U) 04851 #define RCM_SRS0_PIN_SHIFT (6U) 04852 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) 04853 #define RCM_SRS0_POR_MASK (0x80U) 04854 #define RCM_SRS0_POR_SHIFT (7U) 04855 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) 04856 04857 /*! @name SRS1 - System Reset Status Register 1 */ 04858 #define RCM_SRS1_JTAG_MASK (0x1U) 04859 #define RCM_SRS1_JTAG_SHIFT (0U) 04860 #define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK) 04861 #define RCM_SRS1_LOCKUP_MASK (0x2U) 04862 #define RCM_SRS1_LOCKUP_SHIFT (1U) 04863 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) 04864 #define RCM_SRS1_SW_MASK (0x4U) 04865 #define RCM_SRS1_SW_SHIFT (2U) 04866 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) 04867 #define RCM_SRS1_MDM_AP_MASK (0x8U) 04868 #define RCM_SRS1_MDM_AP_SHIFT (3U) 04869 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) 04870 #define RCM_SRS1_EZPT_MASK (0x10U) 04871 #define RCM_SRS1_EZPT_SHIFT (4U) 04872 #define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK) 04873 #define RCM_SRS1_SACKERR_MASK (0x20U) 04874 #define RCM_SRS1_SACKERR_SHIFT (5U) 04875 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) 04876 04877 /*! @name RPFC - Reset Pin Filter Control Register */ 04878 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U) 04879 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U) 04880 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) 04881 #define RCM_RPFC_RSTFLTSS_MASK (0x4U) 04882 #define RCM_RPFC_RSTFLTSS_SHIFT (2U) 04883 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) 04884 04885 /*! @name RPFW - Reset Pin Filter Width Register */ 04886 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) 04887 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U) 04888 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) 04889 04890 /*! @name MR - Mode Register */ 04891 #define RCM_MR_EZP_MS_MASK (0x2U) 04892 #define RCM_MR_EZP_MS_SHIFT (1U) 04893 #define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK) 04894 04895 04896 /*! 04897 * @} 04898 */ /* end of group RCM_Register_Masks */ 04899 04900 04901 /* RCM - Peripheral instance base addresses */ 04902 /** Peripheral RCM base address */ 04903 #define RCM_BASE (0x4007F000u) 04904 /** Peripheral RCM base pointer */ 04905 #define RCM ((RCM_Type *)RCM_BASE) 04906 /** Array initializer of RCM peripheral base addresses */ 04907 #define RCM_BASE_ADDRS { RCM_BASE } 04908 /** Array initializer of RCM peripheral base pointers */ 04909 #define RCM_BASE_PTRS { RCM } 04910 04911 /*! 04912 * @} 04913 */ /* end of group RCM_Peripheral_Access_Layer */ 04914 04915 04916 /* ---------------------------------------------------------------------------- 04917 -- RFSYS Peripheral Access Layer 04918 ---------------------------------------------------------------------------- */ 04919 04920 /*! 04921 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer 04922 * @{ 04923 */ 04924 04925 /** RFSYS - Register Layout Typedef */ 04926 typedef struct { 04927 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ 04928 } RFSYS_Type; 04929 04930 /* ---------------------------------------------------------------------------- 04931 -- RFSYS Register Masks 04932 ---------------------------------------------------------------------------- */ 04933 04934 /*! 04935 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks 04936 * @{ 04937 */ 04938 04939 /*! @name REG - Register file register */ 04940 #define RFSYS_REG_LL_MASK (0xFFU) 04941 #define RFSYS_REG_LL_SHIFT (0U) 04942 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK) 04943 #define RFSYS_REG_LH_MASK (0xFF00U) 04944 #define RFSYS_REG_LH_SHIFT (8U) 04945 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK) 04946 #define RFSYS_REG_HL_MASK (0xFF0000U) 04947 #define RFSYS_REG_HL_SHIFT (16U) 04948 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK) 04949 #define RFSYS_REG_HH_MASK (0xFF000000U) 04950 #define RFSYS_REG_HH_SHIFT (24U) 04951 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK) 04952 04953 /* The count of RFSYS_REG */ 04954 #define RFSYS_REG_COUNT (8U) 04955 04956 04957 /*! 04958 * @} 04959 */ /* end of group RFSYS_Register_Masks */ 04960 04961 04962 /* RFSYS - Peripheral instance base addresses */ 04963 /** Peripheral RFSYS base address */ 04964 #define RFSYS_BASE (0x40041000u) 04965 /** Peripheral RFSYS base pointer */ 04966 #define RFSYS ((RFSYS_Type *)RFSYS_BASE) 04967 /** Array initializer of RFSYS peripheral base addresses */ 04968 #define RFSYS_BASE_ADDRS { RFSYS_BASE } 04969 /** Array initializer of RFSYS peripheral base pointers */ 04970 #define RFSYS_BASE_PTRS { RFSYS } 04971 04972 /*! 04973 * @} 04974 */ /* end of group RFSYS_Peripheral_Access_Layer */ 04975 04976 04977 /* ---------------------------------------------------------------------------- 04978 -- RFVBAT Peripheral Access Layer 04979 ---------------------------------------------------------------------------- */ 04980 04981 /*! 04982 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer 04983 * @{ 04984 */ 04985 04986 /** RFVBAT - Register Layout Typedef */ 04987 typedef struct { 04988 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */ 04989 } RFVBAT_Type; 04990 04991 /* ---------------------------------------------------------------------------- 04992 -- RFVBAT Register Masks 04993 ---------------------------------------------------------------------------- */ 04994 04995 /*! 04996 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks 04997 * @{ 04998 */ 04999 05000 /*! @name REG - VBAT register file register */ 05001 #define RFVBAT_REG_LL_MASK (0xFFU) 05002 #define RFVBAT_REG_LL_SHIFT (0U) 05003 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK) 05004 #define RFVBAT_REG_LH_MASK (0xFF00U) 05005 #define RFVBAT_REG_LH_SHIFT (8U) 05006 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK) 05007 #define RFVBAT_REG_HL_MASK (0xFF0000U) 05008 #define RFVBAT_REG_HL_SHIFT (16U) 05009 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK) 05010 #define RFVBAT_REG_HH_MASK (0xFF000000U) 05011 #define RFVBAT_REG_HH_SHIFT (24U) 05012 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK) 05013 05014 /* The count of RFVBAT_REG */ 05015 #define RFVBAT_REG_COUNT (8U) 05016 05017 05018 /*! 05019 * @} 05020 */ /* end of group RFVBAT_Register_Masks */ 05021 05022 05023 /* RFVBAT - Peripheral instance base addresses */ 05024 /** Peripheral RFVBAT base address */ 05025 #define RFVBAT_BASE (0x4003E000u) 05026 /** Peripheral RFVBAT base pointer */ 05027 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE) 05028 /** Array initializer of RFVBAT peripheral base addresses */ 05029 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE } 05030 /** Array initializer of RFVBAT peripheral base pointers */ 05031 #define RFVBAT_BASE_PTRS { RFVBAT } 05032 05033 /*! 05034 * @} 05035 */ /* end of group RFVBAT_Peripheral_Access_Layer */ 05036 05037 05038 /* ---------------------------------------------------------------------------- 05039 -- RTC Peripheral Access Layer 05040 ---------------------------------------------------------------------------- */ 05041 05042 /*! 05043 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer 05044 * @{ 05045 */ 05046 05047 /** RTC - Register Layout Typedef */ 05048 typedef struct { 05049 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ 05050 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ 05051 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ 05052 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ 05053 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ 05054 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ 05055 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ 05056 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ 05057 uint8_t RESERVED_0[2016]; 05058 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ 05059 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ 05060 } RTC_Type; 05061 05062 /* ---------------------------------------------------------------------------- 05063 -- RTC Register Masks 05064 ---------------------------------------------------------------------------- */ 05065 05066 /*! 05067 * @addtogroup RTC_Register_Masks RTC Register Masks 05068 * @{ 05069 */ 05070 05071 /*! @name TSR - RTC Time Seconds Register */ 05072 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU) 05073 #define RTC_TSR_TSR_SHIFT (0U) 05074 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) 05075 05076 /*! @name TPR - RTC Time Prescaler Register */ 05077 #define RTC_TPR_TPR_MASK (0xFFFFU) 05078 #define RTC_TPR_TPR_SHIFT (0U) 05079 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) 05080 05081 /*! @name TAR - RTC Time Alarm Register */ 05082 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU) 05083 #define RTC_TAR_TAR_SHIFT (0U) 05084 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) 05085 05086 /*! @name TCR - RTC Time Compensation Register */ 05087 #define RTC_TCR_TCR_MASK (0xFFU) 05088 #define RTC_TCR_TCR_SHIFT (0U) 05089 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) 05090 #define RTC_TCR_CIR_MASK (0xFF00U) 05091 #define RTC_TCR_CIR_SHIFT (8U) 05092 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) 05093 #define RTC_TCR_TCV_MASK (0xFF0000U) 05094 #define RTC_TCR_TCV_SHIFT (16U) 05095 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) 05096 #define RTC_TCR_CIC_MASK (0xFF000000U) 05097 #define RTC_TCR_CIC_SHIFT (24U) 05098 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) 05099 05100 /*! @name CR - RTC Control Register */ 05101 #define RTC_CR_SWR_MASK (0x1U) 05102 #define RTC_CR_SWR_SHIFT (0U) 05103 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) 05104 #define RTC_CR_WPE_MASK (0x2U) 05105 #define RTC_CR_WPE_SHIFT (1U) 05106 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) 05107 #define RTC_CR_SUP_MASK (0x4U) 05108 #define RTC_CR_SUP_SHIFT (2U) 05109 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) 05110 #define RTC_CR_UM_MASK (0x8U) 05111 #define RTC_CR_UM_SHIFT (3U) 05112 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) 05113 #define RTC_CR_OSCE_MASK (0x100U) 05114 #define RTC_CR_OSCE_SHIFT (8U) 05115 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) 05116 #define RTC_CR_CLKO_MASK (0x200U) 05117 #define RTC_CR_CLKO_SHIFT (9U) 05118 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) 05119 #define RTC_CR_SC16P_MASK (0x400U) 05120 #define RTC_CR_SC16P_SHIFT (10U) 05121 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) 05122 #define RTC_CR_SC8P_MASK (0x800U) 05123 #define RTC_CR_SC8P_SHIFT (11U) 05124 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) 05125 #define RTC_CR_SC4P_MASK (0x1000U) 05126 #define RTC_CR_SC4P_SHIFT (12U) 05127 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) 05128 #define RTC_CR_SC2P_MASK (0x2000U) 05129 #define RTC_CR_SC2P_SHIFT (13U) 05130 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) 05131 05132 /*! @name SR - RTC Status Register */ 05133 #define RTC_SR_TIF_MASK (0x1U) 05134 #define RTC_SR_TIF_SHIFT (0U) 05135 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) 05136 #define RTC_SR_TOF_MASK (0x2U) 05137 #define RTC_SR_TOF_SHIFT (1U) 05138 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) 05139 #define RTC_SR_TAF_MASK (0x4U) 05140 #define RTC_SR_TAF_SHIFT (2U) 05141 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) 05142 #define RTC_SR_TCE_MASK (0x10U) 05143 #define RTC_SR_TCE_SHIFT (4U) 05144 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) 05145 05146 /*! @name LR - RTC Lock Register */ 05147 #define RTC_LR_TCL_MASK (0x8U) 05148 #define RTC_LR_TCL_SHIFT (3U) 05149 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) 05150 #define RTC_LR_CRL_MASK (0x10U) 05151 #define RTC_LR_CRL_SHIFT (4U) 05152 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) 05153 #define RTC_LR_SRL_MASK (0x20U) 05154 #define RTC_LR_SRL_SHIFT (5U) 05155 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) 05156 #define RTC_LR_LRL_MASK (0x40U) 05157 #define RTC_LR_LRL_SHIFT (6U) 05158 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) 05159 05160 /*! @name IER - RTC Interrupt Enable Register */ 05161 #define RTC_IER_TIIE_MASK (0x1U) 05162 #define RTC_IER_TIIE_SHIFT (0U) 05163 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) 05164 #define RTC_IER_TOIE_MASK (0x2U) 05165 #define RTC_IER_TOIE_SHIFT (1U) 05166 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) 05167 #define RTC_IER_TAIE_MASK (0x4U) 05168 #define RTC_IER_TAIE_SHIFT (2U) 05169 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) 05170 #define RTC_IER_TSIE_MASK (0x10U) 05171 #define RTC_IER_TSIE_SHIFT (4U) 05172 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) 05173 05174 /*! @name WAR - RTC Write Access Register */ 05175 #define RTC_WAR_TSRW_MASK (0x1U) 05176 #define RTC_WAR_TSRW_SHIFT (0U) 05177 #define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK) 05178 #define RTC_WAR_TPRW_MASK (0x2U) 05179 #define RTC_WAR_TPRW_SHIFT (1U) 05180 #define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK) 05181 #define RTC_WAR_TARW_MASK (0x4U) 05182 #define RTC_WAR_TARW_SHIFT (2U) 05183 #define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK) 05184 #define RTC_WAR_TCRW_MASK (0x8U) 05185 #define RTC_WAR_TCRW_SHIFT (3U) 05186 #define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK) 05187 #define RTC_WAR_CRW_MASK (0x10U) 05188 #define RTC_WAR_CRW_SHIFT (4U) 05189 #define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK) 05190 #define RTC_WAR_SRW_MASK (0x20U) 05191 #define RTC_WAR_SRW_SHIFT (5U) 05192 #define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK) 05193 #define RTC_WAR_LRW_MASK (0x40U) 05194 #define RTC_WAR_LRW_SHIFT (6U) 05195 #define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK) 05196 #define RTC_WAR_IERW_MASK (0x80U) 05197 #define RTC_WAR_IERW_SHIFT (7U) 05198 #define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK) 05199 05200 /*! @name RAR - RTC Read Access Register */ 05201 #define RTC_RAR_TSRR_MASK (0x1U) 05202 #define RTC_RAR_TSRR_SHIFT (0U) 05203 #define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK) 05204 #define RTC_RAR_TPRR_MASK (0x2U) 05205 #define RTC_RAR_TPRR_SHIFT (1U) 05206 #define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK) 05207 #define RTC_RAR_TARR_MASK (0x4U) 05208 #define RTC_RAR_TARR_SHIFT (2U) 05209 #define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK) 05210 #define RTC_RAR_TCRR_MASK (0x8U) 05211 #define RTC_RAR_TCRR_SHIFT (3U) 05212 #define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK) 05213 #define RTC_RAR_CRR_MASK (0x10U) 05214 #define RTC_RAR_CRR_SHIFT (4U) 05215 #define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK) 05216 #define RTC_RAR_SRR_MASK (0x20U) 05217 #define RTC_RAR_SRR_SHIFT (5U) 05218 #define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK) 05219 #define RTC_RAR_LRR_MASK (0x40U) 05220 #define RTC_RAR_LRR_SHIFT (6U) 05221 #define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK) 05222 #define RTC_RAR_IERR_MASK (0x80U) 05223 #define RTC_RAR_IERR_SHIFT (7U) 05224 #define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK) 05225 05226 05227 /*! 05228 * @} 05229 */ /* end of group RTC_Register_Masks */ 05230 05231 05232 /* RTC - Peripheral instance base addresses */ 05233 /** Peripheral RTC base address */ 05234 #define RTC_BASE (0x4003D000u) 05235 /** Peripheral RTC base pointer */ 05236 #define RTC ((RTC_Type *)RTC_BASE) 05237 /** Array initializer of RTC peripheral base addresses */ 05238 #define RTC_BASE_ADDRS { RTC_BASE } 05239 /** Array initializer of RTC peripheral base pointers */ 05240 #define RTC_BASE_PTRS { RTC } 05241 /** Interrupt vectors for the RTC peripheral type */ 05242 #define RTC_IRQS { RTC_IRQn } 05243 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } 05244 05245 /*! 05246 * @} 05247 */ /* end of group RTC_Peripheral_Access_Layer */ 05248 05249 05250 /* ---------------------------------------------------------------------------- 05251 -- SIM Peripheral Access Layer 05252 ---------------------------------------------------------------------------- */ 05253 05254 /*! 05255 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer 05256 * @{ 05257 */ 05258 05259 /** SIM - Register Layout Typedef */ 05260 typedef struct { 05261 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ 05262 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ 05263 uint8_t RESERVED_0[4092]; 05264 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ 05265 uint8_t RESERVED_1[4]; 05266 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ 05267 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ 05268 uint8_t RESERVED_2[4]; 05269 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ 05270 uint8_t RESERVED_3[8]; 05271 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ 05272 uint8_t RESERVED_4[12]; 05273 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ 05274 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ 05275 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ 05276 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ 05277 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ 05278 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */ 05279 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ 05280 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ 05281 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */ 05282 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ 05283 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ 05284 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ 05285 } SIM_Type; 05286 05287 /* ---------------------------------------------------------------------------- 05288 -- SIM Register Masks 05289 ---------------------------------------------------------------------------- */ 05290 05291 /*! 05292 * @addtogroup SIM_Register_Masks SIM Register Masks 05293 * @{ 05294 */ 05295 05296 /*! @name SOPT1 - System Options Register 1 */ 05297 #define SIM_SOPT1_RAMSIZE_MASK (0xF000U) 05298 #define SIM_SOPT1_RAMSIZE_SHIFT (12U) 05299 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK) 05300 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) 05301 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U) 05302 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) 05303 #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U) 05304 #define SIM_SOPT1_USBVSTBY_SHIFT (29U) 05305 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK) 05306 #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U) 05307 #define SIM_SOPT1_USBSSTBY_SHIFT (30U) 05308 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK) 05309 #define SIM_SOPT1_USBREGEN_MASK (0x80000000U) 05310 #define SIM_SOPT1_USBREGEN_SHIFT (31U) 05311 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK) 05312 05313 /*! @name SOPT1CFG - SOPT1 Configuration Register */ 05314 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) 05315 #define SIM_SOPT1CFG_URWE_SHIFT (24U) 05316 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK) 05317 #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U) 05318 #define SIM_SOPT1CFG_UVSWE_SHIFT (25U) 05319 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK) 05320 #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U) 05321 #define SIM_SOPT1CFG_USSWE_SHIFT (26U) 05322 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK) 05323 05324 /*! @name SOPT2 - System Options Register 2 */ 05325 #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U) 05326 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U) 05327 #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK) 05328 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U) 05329 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U) 05330 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK) 05331 #define SIM_SOPT2_PTD7PAD_MASK (0x800U) 05332 #define SIM_SOPT2_PTD7PAD_SHIFT (11U) 05333 #define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK) 05334 #define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U) 05335 #define SIM_SOPT2_TRACECLKSEL_SHIFT (12U) 05336 #define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK) 05337 #define SIM_SOPT2_PLLFLLSEL_MASK (0x10000U) 05338 #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U) 05339 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK) 05340 #define SIM_SOPT2_USBSRC_MASK (0x40000U) 05341 #define SIM_SOPT2_USBSRC_SHIFT (18U) 05342 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK) 05343 05344 /*! @name SOPT4 - System Options Register 4 */ 05345 #define SIM_SOPT4_FTM0FLT0_MASK (0x1U) 05346 #define SIM_SOPT4_FTM0FLT0_SHIFT (0U) 05347 #define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK) 05348 #define SIM_SOPT4_FTM0FLT1_MASK (0x2U) 05349 #define SIM_SOPT4_FTM0FLT1_SHIFT (1U) 05350 #define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK) 05351 #define SIM_SOPT4_FTM1FLT0_MASK (0x10U) 05352 #define SIM_SOPT4_FTM1FLT0_SHIFT (4U) 05353 #define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK) 05354 #define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U) 05355 #define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U) 05356 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK) 05357 #define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U) 05358 #define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U) 05359 #define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK) 05360 #define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U) 05361 #define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U) 05362 #define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK) 05363 #define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U) 05364 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U) 05365 #define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK) 05366 05367 /*! @name SOPT5 - System Options Register 5 */ 05368 #define SIM_SOPT5_UART0TXSRC_MASK (0x1U) 05369 #define SIM_SOPT5_UART0TXSRC_SHIFT (0U) 05370 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK) 05371 #define SIM_SOPT5_UART0RXSRC_MASK (0xCU) 05372 #define SIM_SOPT5_UART0RXSRC_SHIFT (2U) 05373 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK) 05374 #define SIM_SOPT5_UART1TXSRC_MASK (0x10U) 05375 #define SIM_SOPT5_UART1TXSRC_SHIFT (4U) 05376 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK) 05377 #define SIM_SOPT5_UART1RXSRC_MASK (0xC0U) 05378 #define SIM_SOPT5_UART1RXSRC_SHIFT (6U) 05379 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK) 05380 05381 /*! @name SOPT7 - System Options Register 7 */ 05382 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) 05383 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) 05384 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) 05385 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) 05386 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) 05387 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) 05388 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U) 05389 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U) 05390 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK) 05391 05392 /*! @name SDID - System Device Identification Register */ 05393 #define SIM_SDID_PINID_MASK (0xFU) 05394 #define SIM_SDID_PINID_SHIFT (0U) 05395 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) 05396 #define SIM_SDID_FAMID_MASK (0x70U) 05397 #define SIM_SDID_FAMID_SHIFT (4U) 05398 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) 05399 #define SIM_SDID_REVID_MASK (0xF000U) 05400 #define SIM_SDID_REVID_SHIFT (12U) 05401 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) 05402 05403 /*! @name SCGC4 - System Clock Gating Control Register 4 */ 05404 #define SIM_SCGC4_EWM_MASK (0x2U) 05405 #define SIM_SCGC4_EWM_SHIFT (1U) 05406 #define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK) 05407 #define SIM_SCGC4_CMT_MASK (0x4U) 05408 #define SIM_SCGC4_CMT_SHIFT (2U) 05409 #define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK) 05410 #define SIM_SCGC4_I2C0_MASK (0x40U) 05411 #define SIM_SCGC4_I2C0_SHIFT (6U) 05412 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) 05413 #define SIM_SCGC4_UART0_MASK (0x400U) 05414 #define SIM_SCGC4_UART0_SHIFT (10U) 05415 #define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK) 05416 #define SIM_SCGC4_UART1_MASK (0x800U) 05417 #define SIM_SCGC4_UART1_SHIFT (11U) 05418 #define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK) 05419 #define SIM_SCGC4_UART2_MASK (0x1000U) 05420 #define SIM_SCGC4_UART2_SHIFT (12U) 05421 #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK) 05422 #define SIM_SCGC4_USBOTG_MASK (0x40000U) 05423 #define SIM_SCGC4_USBOTG_SHIFT (18U) 05424 #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK) 05425 #define SIM_SCGC4_CMP_MASK (0x80000U) 05426 #define SIM_SCGC4_CMP_SHIFT (19U) 05427 #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK) 05428 #define SIM_SCGC4_VREF_MASK (0x100000U) 05429 #define SIM_SCGC4_VREF_SHIFT (20U) 05430 #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK) 05431 05432 /*! @name SCGC5 - System Clock Gating Control Register 5 */ 05433 #define SIM_SCGC5_LPTIMER_MASK (0x1U) 05434 #define SIM_SCGC5_LPTIMER_SHIFT (0U) 05435 #define SIM_SCGC5_LPTIMER(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTIMER_SHIFT)) & SIM_SCGC5_LPTIMER_MASK) 05436 #define SIM_SCGC5_TSI_MASK (0x20U) 05437 #define SIM_SCGC5_TSI_SHIFT (5U) 05438 #define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK) 05439 #define SIM_SCGC5_PORTA_MASK (0x200U) 05440 #define SIM_SCGC5_PORTA_SHIFT (9U) 05441 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) 05442 #define SIM_SCGC5_PORTB_MASK (0x400U) 05443 #define SIM_SCGC5_PORTB_SHIFT (10U) 05444 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) 05445 #define SIM_SCGC5_PORTC_MASK (0x800U) 05446 #define SIM_SCGC5_PORTC_SHIFT (11U) 05447 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) 05448 #define SIM_SCGC5_PORTD_MASK (0x1000U) 05449 #define SIM_SCGC5_PORTD_SHIFT (12U) 05450 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK) 05451 #define SIM_SCGC5_PORTE_MASK (0x2000U) 05452 #define SIM_SCGC5_PORTE_SHIFT (13U) 05453 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK) 05454 05455 /*! @name SCGC6 - System Clock Gating Control Register 6 */ 05456 #define SIM_SCGC6_FTFL_MASK (0x1U) 05457 #define SIM_SCGC6_FTFL_SHIFT (0U) 05458 #define SIM_SCGC6_FTFL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTFL_SHIFT)) & SIM_SCGC6_FTFL_MASK) 05459 #define SIM_SCGC6_DMAMUX_MASK (0x2U) 05460 #define SIM_SCGC6_DMAMUX_SHIFT (1U) 05461 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK) 05462 #define SIM_SCGC6_SPI0_MASK (0x1000U) 05463 #define SIM_SCGC6_SPI0_SHIFT (12U) 05464 #define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK) 05465 #define SIM_SCGC6_I2S_MASK (0x8000U) 05466 #define SIM_SCGC6_I2S_SHIFT (15U) 05467 #define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK) 05468 #define SIM_SCGC6_CRC_MASK (0x40000U) 05469 #define SIM_SCGC6_CRC_SHIFT (18U) 05470 #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK) 05471 #define SIM_SCGC6_USBDCD_MASK (0x200000U) 05472 #define SIM_SCGC6_USBDCD_SHIFT (21U) 05473 #define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK) 05474 #define SIM_SCGC6_PDB_MASK (0x400000U) 05475 #define SIM_SCGC6_PDB_SHIFT (22U) 05476 #define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK) 05477 #define SIM_SCGC6_PIT_MASK (0x800000U) 05478 #define SIM_SCGC6_PIT_SHIFT (23U) 05479 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK) 05480 #define SIM_SCGC6_FTM0_MASK (0x1000000U) 05481 #define SIM_SCGC6_FTM0_SHIFT (24U) 05482 #define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK) 05483 #define SIM_SCGC6_FTM1_MASK (0x2000000U) 05484 #define SIM_SCGC6_FTM1_SHIFT (25U) 05485 #define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK) 05486 #define SIM_SCGC6_ADC0_MASK (0x8000000U) 05487 #define SIM_SCGC6_ADC0_SHIFT (27U) 05488 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) 05489 #define SIM_SCGC6_RTC_MASK (0x20000000U) 05490 #define SIM_SCGC6_RTC_SHIFT (29U) 05491 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK) 05492 05493 /*! @name SCGC7 - System Clock Gating Control Register 7 */ 05494 #define SIM_SCGC7_DMA_MASK (0x2U) 05495 #define SIM_SCGC7_DMA_SHIFT (1U) 05496 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) 05497 05498 /*! @name CLKDIV1 - System Clock Divider Register 1 */ 05499 #define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U) 05500 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) 05501 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) 05502 #define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U) 05503 #define SIM_CLKDIV1_OUTDIV2_SHIFT (24U) 05504 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK) 05505 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) 05506 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) 05507 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) 05508 05509 /*! @name CLKDIV2 - System Clock Divider Register 2 */ 05510 #define SIM_CLKDIV2_USBFRAC_MASK (0x1U) 05511 #define SIM_CLKDIV2_USBFRAC_SHIFT (0U) 05512 #define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK) 05513 #define SIM_CLKDIV2_USBDIV_MASK (0xEU) 05514 #define SIM_CLKDIV2_USBDIV_SHIFT (1U) 05515 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK) 05516 05517 /*! @name FCFG1 - Flash Configuration Register 1 */ 05518 #define SIM_FCFG1_FLASHDIS_MASK (0x1U) 05519 #define SIM_FCFG1_FLASHDIS_SHIFT (0U) 05520 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) 05521 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U) 05522 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U) 05523 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) 05524 #define SIM_FCFG1_DEPART_MASK (0xF00U) 05525 #define SIM_FCFG1_DEPART_SHIFT (8U) 05526 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK) 05527 #define SIM_FCFG1_EESIZE_MASK (0xF0000U) 05528 #define SIM_FCFG1_EESIZE_SHIFT (16U) 05529 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK) 05530 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U) 05531 #define SIM_FCFG1_PFSIZE_SHIFT (24U) 05532 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) 05533 #define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U) 05534 #define SIM_FCFG1_NVMSIZE_SHIFT (28U) 05535 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK) 05536 05537 /*! @name FCFG2 - Flash Configuration Register 2 */ 05538 #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U) 05539 #define SIM_FCFG2_MAXADDR1_SHIFT (16U) 05540 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK) 05541 #define SIM_FCFG2_PFLSH_MASK (0x800000U) 05542 #define SIM_FCFG2_PFLSH_SHIFT (23U) 05543 #define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK) 05544 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) 05545 #define SIM_FCFG2_MAXADDR0_SHIFT (24U) 05546 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) 05547 05548 /*! @name UIDH - Unique Identification Register High */ 05549 #define SIM_UIDH_UID_MASK (0xFFFFFFFFU) 05550 #define SIM_UIDH_UID_SHIFT (0U) 05551 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK) 05552 05553 /*! @name UIDMH - Unique Identification Register Mid-High */ 05554 #define SIM_UIDMH_UID_MASK (0xFFFFFFFFU) 05555 #define SIM_UIDMH_UID_SHIFT (0U) 05556 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) 05557 05558 /*! @name UIDML - Unique Identification Register Mid Low */ 05559 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU) 05560 #define SIM_UIDML_UID_SHIFT (0U) 05561 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) 05562 05563 /*! @name UIDL - Unique Identification Register Low */ 05564 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU) 05565 #define SIM_UIDL_UID_SHIFT (0U) 05566 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) 05567 05568 05569 /*! 05570 * @} 05571 */ /* end of group SIM_Register_Masks */ 05572 05573 05574 /* SIM - Peripheral instance base addresses */ 05575 /** Peripheral SIM base address */ 05576 #define SIM_BASE (0x40047000u) 05577 /** Peripheral SIM base pointer */ 05578 #define SIM ((SIM_Type *)SIM_BASE) 05579 /** Array initializer of SIM peripheral base addresses */ 05580 #define SIM_BASE_ADDRS { SIM_BASE } 05581 /** Array initializer of SIM peripheral base pointers */ 05582 #define SIM_BASE_PTRS { SIM } 05583 05584 /*! 05585 * @} 05586 */ /* end of group SIM_Peripheral_Access_Layer */ 05587 05588 05589 /* ---------------------------------------------------------------------------- 05590 -- SMC Peripheral Access Layer 05591 ---------------------------------------------------------------------------- */ 05592 05593 /*! 05594 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer 05595 * @{ 05596 */ 05597 05598 /** SMC - Register Layout Typedef */ 05599 typedef struct { 05600 __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */ 05601 __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */ 05602 __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */ 05603 __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */ 05604 } SMC_Type; 05605 05606 /* ---------------------------------------------------------------------------- 05607 -- SMC Register Masks 05608 ---------------------------------------------------------------------------- */ 05609 05610 /*! 05611 * @addtogroup SMC_Register_Masks SMC Register Masks 05612 * @{ 05613 */ 05614 05615 /*! @name PMPROT - Power Mode Protection Register */ 05616 #define SMC_PMPROT_AVLLS_MASK (0x2U) 05617 #define SMC_PMPROT_AVLLS_SHIFT (1U) 05618 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) 05619 #define SMC_PMPROT_ALLS_MASK (0x8U) 05620 #define SMC_PMPROT_ALLS_SHIFT (3U) 05621 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) 05622 #define SMC_PMPROT_AVLP_MASK (0x20U) 05623 #define SMC_PMPROT_AVLP_SHIFT (5U) 05624 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) 05625 05626 /*! @name PMCTRL - Power Mode Control Register */ 05627 #define SMC_PMCTRL_STOPM_MASK (0x7U) 05628 #define SMC_PMCTRL_STOPM_SHIFT (0U) 05629 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) 05630 #define SMC_PMCTRL_STOPA_MASK (0x8U) 05631 #define SMC_PMCTRL_STOPA_SHIFT (3U) 05632 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) 05633 #define SMC_PMCTRL_RUNM_MASK (0x60U) 05634 #define SMC_PMCTRL_RUNM_SHIFT (5U) 05635 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) 05636 #define SMC_PMCTRL_LPWUI_MASK (0x80U) 05637 #define SMC_PMCTRL_LPWUI_SHIFT (7U) 05638 #define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK) 05639 05640 /*! @name VLLSCTRL - VLLS Control Register */ 05641 #define SMC_VLLSCTRL_VLLSM_MASK (0x7U) 05642 #define SMC_VLLSCTRL_VLLSM_SHIFT (0U) 05643 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK) 05644 #define SMC_VLLSCTRL_PORPO_MASK (0x20U) 05645 #define SMC_VLLSCTRL_PORPO_SHIFT (5U) 05646 #define SMC_VLLSCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_PORPO_SHIFT)) & SMC_VLLSCTRL_PORPO_MASK) 05647 05648 /*! @name PMSTAT - Power Mode Status Register */ 05649 #define SMC_PMSTAT_PMSTAT_MASK (0x7FU) 05650 #define SMC_PMSTAT_PMSTAT_SHIFT (0U) 05651 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) 05652 05653 05654 /*! 05655 * @} 05656 */ /* end of group SMC_Register_Masks */ 05657 05658 05659 /* SMC - Peripheral instance base addresses */ 05660 /** Peripheral SMC base address */ 05661 #define SMC_BASE (0x4007E000u) 05662 /** Peripheral SMC base pointer */ 05663 #define SMC ((SMC_Type *)SMC_BASE) 05664 /** Array initializer of SMC peripheral base addresses */ 05665 #define SMC_BASE_ADDRS { SMC_BASE } 05666 /** Array initializer of SMC peripheral base pointers */ 05667 #define SMC_BASE_PTRS { SMC } 05668 05669 /*! 05670 * @} 05671 */ /* end of group SMC_Peripheral_Access_Layer */ 05672 05673 05674 /* ---------------------------------------------------------------------------- 05675 -- SPI Peripheral Access Layer 05676 ---------------------------------------------------------------------------- */ 05677 05678 /*! 05679 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 05680 * @{ 05681 */ 05682 05683 /** SPI - Register Layout Typedef */ 05684 typedef struct { 05685 __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */ 05686 uint8_t RESERVED_0[4]; 05687 __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */ 05688 union { /* offset: 0xC */ 05689 __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ 05690 __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ 05691 }; 05692 uint8_t RESERVED_1[24]; 05693 __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */ 05694 __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ 05695 union { /* offset: 0x34 */ 05696 __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */ 05697 __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ 05698 }; 05699 __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */ 05700 __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */ 05701 __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */ 05702 __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */ 05703 __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */ 05704 uint8_t RESERVED_2[48]; 05705 __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */ 05706 __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */ 05707 __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */ 05708 __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */ 05709 } SPI_Type; 05710 05711 /* ---------------------------------------------------------------------------- 05712 -- SPI Register Masks 05713 ---------------------------------------------------------------------------- */ 05714 05715 /*! 05716 * @addtogroup SPI_Register_Masks SPI Register Masks 05717 * @{ 05718 */ 05719 05720 /*! @name MCR - DSPI Module Configuration Register */ 05721 #define SPI_MCR_HALT_MASK (0x1U) 05722 #define SPI_MCR_HALT_SHIFT (0U) 05723 #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK) 05724 #define SPI_MCR_SMPL_PT_MASK (0x300U) 05725 #define SPI_MCR_SMPL_PT_SHIFT (8U) 05726 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK) 05727 #define SPI_MCR_CLR_RXF_MASK (0x400U) 05728 #define SPI_MCR_CLR_RXF_SHIFT (10U) 05729 #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK) 05730 #define SPI_MCR_CLR_TXF_MASK (0x800U) 05731 #define SPI_MCR_CLR_TXF_SHIFT (11U) 05732 #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK) 05733 #define SPI_MCR_DIS_RXF_MASK (0x1000U) 05734 #define SPI_MCR_DIS_RXF_SHIFT (12U) 05735 #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK) 05736 #define SPI_MCR_DIS_TXF_MASK (0x2000U) 05737 #define SPI_MCR_DIS_TXF_SHIFT (13U) 05738 #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK) 05739 #define SPI_MCR_MDIS_MASK (0x4000U) 05740 #define SPI_MCR_MDIS_SHIFT (14U) 05741 #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK) 05742 #define SPI_MCR_DOZE_MASK (0x8000U) 05743 #define SPI_MCR_DOZE_SHIFT (15U) 05744 #define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK) 05745 #define SPI_MCR_PCSIS_MASK (0x3F0000U) 05746 #define SPI_MCR_PCSIS_SHIFT (16U) 05747 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK) 05748 #define SPI_MCR_ROOE_MASK (0x1000000U) 05749 #define SPI_MCR_ROOE_SHIFT (24U) 05750 #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK) 05751 #define SPI_MCR_PCSSE_MASK (0x2000000U) 05752 #define SPI_MCR_PCSSE_SHIFT (25U) 05753 #define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK) 05754 #define SPI_MCR_MTFE_MASK (0x4000000U) 05755 #define SPI_MCR_MTFE_SHIFT (26U) 05756 #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK) 05757 #define SPI_MCR_FRZ_MASK (0x8000000U) 05758 #define SPI_MCR_FRZ_SHIFT (27U) 05759 #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK) 05760 #define SPI_MCR_DCONF_MASK (0x30000000U) 05761 #define SPI_MCR_DCONF_SHIFT (28U) 05762 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK) 05763 #define SPI_MCR_CONT_SCKE_MASK (0x40000000U) 05764 #define SPI_MCR_CONT_SCKE_SHIFT (30U) 05765 #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK) 05766 #define SPI_MCR_MSTR_MASK (0x80000000U) 05767 #define SPI_MCR_MSTR_SHIFT (31U) 05768 #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK) 05769 05770 /*! @name TCR - DSPI Transfer Count Register */ 05771 #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U) 05772 #define SPI_TCR_SPI_TCNT_SHIFT (16U) 05773 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK) 05774 05775 /*! @name CTAR - DSPI Clock and Transfer Attributes Register (In Master Mode) */ 05776 #define SPI_CTAR_BR_MASK (0xFU) 05777 #define SPI_CTAR_BR_SHIFT (0U) 05778 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK) 05779 #define SPI_CTAR_DT_MASK (0xF0U) 05780 #define SPI_CTAR_DT_SHIFT (4U) 05781 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK) 05782 #define SPI_CTAR_ASC_MASK (0xF00U) 05783 #define SPI_CTAR_ASC_SHIFT (8U) 05784 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK) 05785 #define SPI_CTAR_CSSCK_MASK (0xF000U) 05786 #define SPI_CTAR_CSSCK_SHIFT (12U) 05787 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK) 05788 #define SPI_CTAR_PBR_MASK (0x30000U) 05789 #define SPI_CTAR_PBR_SHIFT (16U) 05790 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK) 05791 #define SPI_CTAR_PDT_MASK (0xC0000U) 05792 #define SPI_CTAR_PDT_SHIFT (18U) 05793 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK) 05794 #define SPI_CTAR_PASC_MASK (0x300000U) 05795 #define SPI_CTAR_PASC_SHIFT (20U) 05796 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK) 05797 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) 05798 #define SPI_CTAR_PCSSCK_SHIFT (22U) 05799 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK) 05800 #define SPI_CTAR_LSBFE_MASK (0x1000000U) 05801 #define SPI_CTAR_LSBFE_SHIFT (24U) 05802 #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK) 05803 #define SPI_CTAR_CPHA_MASK (0x2000000U) 05804 #define SPI_CTAR_CPHA_SHIFT (25U) 05805 #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK) 05806 #define SPI_CTAR_CPOL_MASK (0x4000000U) 05807 #define SPI_CTAR_CPOL_SHIFT (26U) 05808 #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK) 05809 #define SPI_CTAR_FMSZ_MASK (0x78000000U) 05810 #define SPI_CTAR_FMSZ_SHIFT (27U) 05811 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK) 05812 #define SPI_CTAR_DBR_MASK (0x80000000U) 05813 #define SPI_CTAR_DBR_SHIFT (31U) 05814 #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK) 05815 05816 /* The count of SPI_CTAR */ 05817 #define SPI_CTAR_COUNT (2U) 05818 05819 /*! @name CTAR_SLAVE - DSPI Clock and Transfer Attributes Register (In Slave Mode) */ 05820 #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U) 05821 #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U) 05822 #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK) 05823 #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U) 05824 #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U) 05825 #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK) 05826 #define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U) 05827 #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U) 05828 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK) 05829 05830 /* The count of SPI_CTAR_SLAVE */ 05831 #define SPI_CTAR_SLAVE_COUNT (1U) 05832 05833 /*! @name SR - DSPI Status Register */ 05834 #define SPI_SR_POPNXTPTR_MASK (0xFU) 05835 #define SPI_SR_POPNXTPTR_SHIFT (0U) 05836 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK) 05837 #define SPI_SR_RXCTR_MASK (0xF0U) 05838 #define SPI_SR_RXCTR_SHIFT (4U) 05839 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK) 05840 #define SPI_SR_TXNXTPTR_MASK (0xF00U) 05841 #define SPI_SR_TXNXTPTR_SHIFT (8U) 05842 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK) 05843 #define SPI_SR_TXCTR_MASK (0xF000U) 05844 #define SPI_SR_TXCTR_SHIFT (12U) 05845 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK) 05846 #define SPI_SR_RFDF_MASK (0x20000U) 05847 #define SPI_SR_RFDF_SHIFT (17U) 05848 #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK) 05849 #define SPI_SR_RFOF_MASK (0x80000U) 05850 #define SPI_SR_RFOF_SHIFT (19U) 05851 #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK) 05852 #define SPI_SR_TFFF_MASK (0x2000000U) 05853 #define SPI_SR_TFFF_SHIFT (25U) 05854 #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK) 05855 #define SPI_SR_TFUF_MASK (0x8000000U) 05856 #define SPI_SR_TFUF_SHIFT (27U) 05857 #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK) 05858 #define SPI_SR_EOQF_MASK (0x10000000U) 05859 #define SPI_SR_EOQF_SHIFT (28U) 05860 #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK) 05861 #define SPI_SR_TXRXS_MASK (0x40000000U) 05862 #define SPI_SR_TXRXS_SHIFT (30U) 05863 #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK) 05864 #define SPI_SR_TCF_MASK (0x80000000U) 05865 #define SPI_SR_TCF_SHIFT (31U) 05866 #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK) 05867 05868 /*! @name RSER - DSPI DMA/Interrupt Request Select and Enable Register */ 05869 #define SPI_RSER_RFDF_DIRS_MASK (0x10000U) 05870 #define SPI_RSER_RFDF_DIRS_SHIFT (16U) 05871 #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK) 05872 #define SPI_RSER_RFDF_RE_MASK (0x20000U) 05873 #define SPI_RSER_RFDF_RE_SHIFT (17U) 05874 #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK) 05875 #define SPI_RSER_RFOF_RE_MASK (0x80000U) 05876 #define SPI_RSER_RFOF_RE_SHIFT (19U) 05877 #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK) 05878 #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U) 05879 #define SPI_RSER_TFFF_DIRS_SHIFT (24U) 05880 #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK) 05881 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) 05882 #define SPI_RSER_TFFF_RE_SHIFT (25U) 05883 #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK) 05884 #define SPI_RSER_TFUF_RE_MASK (0x8000000U) 05885 #define SPI_RSER_TFUF_RE_SHIFT (27U) 05886 #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK) 05887 #define SPI_RSER_EOQF_RE_MASK (0x10000000U) 05888 #define SPI_RSER_EOQF_RE_SHIFT (28U) 05889 #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK) 05890 #define SPI_RSER_TCF_RE_MASK (0x80000000U) 05891 #define SPI_RSER_TCF_RE_SHIFT (31U) 05892 #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK) 05893 05894 /*! @name PUSHR - DSPI PUSH TX FIFO Register In Master Mode */ 05895 #define SPI_PUSHR_TXDATA_MASK (0xFFFFU) 05896 #define SPI_PUSHR_TXDATA_SHIFT (0U) 05897 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK) 05898 #define SPI_PUSHR_PCS_MASK (0x3F0000U) 05899 #define SPI_PUSHR_PCS_SHIFT (16U) 05900 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK) 05901 #define SPI_PUSHR_CTCNT_MASK (0x4000000U) 05902 #define SPI_PUSHR_CTCNT_SHIFT (26U) 05903 #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK) 05904 #define SPI_PUSHR_EOQ_MASK (0x8000000U) 05905 #define SPI_PUSHR_EOQ_SHIFT (27U) 05906 #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK) 05907 #define SPI_PUSHR_CTAS_MASK (0x70000000U) 05908 #define SPI_PUSHR_CTAS_SHIFT (28U) 05909 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK) 05910 #define SPI_PUSHR_CONT_MASK (0x80000000U) 05911 #define SPI_PUSHR_CONT_SHIFT (31U) 05912 #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK) 05913 05914 /*! @name PUSHR_SLAVE - DSPI PUSH TX FIFO Register In Slave Mode */ 05915 #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU) 05916 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U) 05917 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK) 05918 05919 /*! @name POPR - DSPI POP RX FIFO Register */ 05920 #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU) 05921 #define SPI_POPR_RXDATA_SHIFT (0U) 05922 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK) 05923 05924 /*! @name TXFR0 - DSPI Transmit FIFO Registers */ 05925 #define SPI_TXFR0_TXDATA_MASK (0xFFFFU) 05926 #define SPI_TXFR0_TXDATA_SHIFT (0U) 05927 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK) 05928 #define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U) 05929 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U) 05930 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK) 05931 05932 /*! @name TXFR1 - DSPI Transmit FIFO Registers */ 05933 #define SPI_TXFR1_TXDATA_MASK (0xFFFFU) 05934 #define SPI_TXFR1_TXDATA_SHIFT (0U) 05935 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK) 05936 #define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U) 05937 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U) 05938 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK) 05939 05940 /*! @name TXFR2 - DSPI Transmit FIFO Registers */ 05941 #define SPI_TXFR2_TXDATA_MASK (0xFFFFU) 05942 #define SPI_TXFR2_TXDATA_SHIFT (0U) 05943 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK) 05944 #define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U) 05945 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U) 05946 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK) 05947 05948 /*! @name TXFR3 - DSPI Transmit FIFO Registers */ 05949 #define SPI_TXFR3_TXDATA_MASK (0xFFFFU) 05950 #define SPI_TXFR3_TXDATA_SHIFT (0U) 05951 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK) 05952 #define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U) 05953 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U) 05954 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK) 05955 05956 /*! @name RXFR0 - DSPI Receive FIFO Registers */ 05957 #define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU) 05958 #define SPI_RXFR0_RXDATA_SHIFT (0U) 05959 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK) 05960 05961 /*! @name RXFR1 - DSPI Receive FIFO Registers */ 05962 #define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU) 05963 #define SPI_RXFR1_RXDATA_SHIFT (0U) 05964 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK) 05965 05966 /*! @name RXFR2 - DSPI Receive FIFO Registers */ 05967 #define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU) 05968 #define SPI_RXFR2_RXDATA_SHIFT (0U) 05969 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK) 05970 05971 /*! @name RXFR3 - DSPI Receive FIFO Registers */ 05972 #define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU) 05973 #define SPI_RXFR3_RXDATA_SHIFT (0U) 05974 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK) 05975 05976 05977 /*! 05978 * @} 05979 */ /* end of group SPI_Register_Masks */ 05980 05981 05982 /* SPI - Peripheral instance base addresses */ 05983 /** Peripheral SPI0 base address */ 05984 #define SPI0_BASE (0x4002C000u) 05985 /** Peripheral SPI0 base pointer */ 05986 #define SPI0 ((SPI_Type *)SPI0_BASE) 05987 /** Array initializer of SPI peripheral base addresses */ 05988 #define SPI_BASE_ADDRS { SPI0_BASE } 05989 /** Array initializer of SPI peripheral base pointers */ 05990 #define SPI_BASE_PTRS { SPI0 } 05991 /** Interrupt vectors for the SPI peripheral type */ 05992 #define SPI_IRQS { SPI0_IRQn } 05993 05994 /*! 05995 * @} 05996 */ /* end of group SPI_Peripheral_Access_Layer */ 05997 05998 05999 /* ---------------------------------------------------------------------------- 06000 -- TSI Peripheral Access Layer 06001 ---------------------------------------------------------------------------- */ 06002 06003 /*! 06004 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer 06005 * @{ 06006 */ 06007 06008 /** TSI - Register Layout Typedef */ 06009 typedef struct { 06010 __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */ 06011 __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */ 06012 __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */ 06013 __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */ 06014 uint8_t RESERVED_0[240]; 06015 __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */ 06016 __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */ 06017 __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */ 06018 __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */ 06019 __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */ 06020 __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */ 06021 __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */ 06022 __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */ 06023 __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */ 06024 } TSI_Type; 06025 06026 /* ---------------------------------------------------------------------------- 06027 -- TSI Register Masks 06028 ---------------------------------------------------------------------------- */ 06029 06030 /*! 06031 * @addtogroup TSI_Register_Masks TSI Register Masks 06032 * @{ 06033 */ 06034 06035 /*! @name GENCS - General Control and Status Register */ 06036 #define TSI_GENCS_STPE_MASK (0x1U) 06037 #define TSI_GENCS_STPE_SHIFT (0U) 06038 #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK) 06039 #define TSI_GENCS_STM_MASK (0x2U) 06040 #define TSI_GENCS_STM_SHIFT (1U) 06041 #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK) 06042 #define TSI_GENCS_ESOR_MASK (0x10U) 06043 #define TSI_GENCS_ESOR_SHIFT (4U) 06044 #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK) 06045 #define TSI_GENCS_ERIE_MASK (0x20U) 06046 #define TSI_GENCS_ERIE_SHIFT (5U) 06047 #define TSI_GENCS_ERIE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ERIE_SHIFT)) & TSI_GENCS_ERIE_MASK) 06048 #define TSI_GENCS_TSIIE_MASK (0x40U) 06049 #define TSI_GENCS_TSIIE_SHIFT (6U) 06050 #define TSI_GENCS_TSIIE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIE_SHIFT)) & TSI_GENCS_TSIIE_MASK) 06051 #define TSI_GENCS_TSIEN_MASK (0x80U) 06052 #define TSI_GENCS_TSIEN_SHIFT (7U) 06053 #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK) 06054 #define TSI_GENCS_SWTS_MASK (0x100U) 06055 #define TSI_GENCS_SWTS_SHIFT (8U) 06056 #define TSI_GENCS_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SWTS_SHIFT)) & TSI_GENCS_SWTS_MASK) 06057 #define TSI_GENCS_SCNIP_MASK (0x200U) 06058 #define TSI_GENCS_SCNIP_SHIFT (9U) 06059 #define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK) 06060 #define TSI_GENCS_OVRF_MASK (0x1000U) 06061 #define TSI_GENCS_OVRF_SHIFT (12U) 06062 #define TSI_GENCS_OVRF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OVRF_SHIFT)) & TSI_GENCS_OVRF_MASK) 06063 #define TSI_GENCS_EXTERF_MASK (0x2000U) 06064 #define TSI_GENCS_EXTERF_SHIFT (13U) 06065 #define TSI_GENCS_EXTERF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTERF_SHIFT)) & TSI_GENCS_EXTERF_MASK) 06066 #define TSI_GENCS_OUTRGF_MASK (0x4000U) 06067 #define TSI_GENCS_OUTRGF_SHIFT (14U) 06068 #define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK) 06069 #define TSI_GENCS_EOSF_MASK (0x8000U) 06070 #define TSI_GENCS_EOSF_SHIFT (15U) 06071 #define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK) 06072 #define TSI_GENCS_PS_MASK (0x70000U) 06073 #define TSI_GENCS_PS_SHIFT (16U) 06074 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK) 06075 #define TSI_GENCS_NSCN_MASK (0xF80000U) 06076 #define TSI_GENCS_NSCN_SHIFT (19U) 06077 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK) 06078 #define TSI_GENCS_LPSCNITV_MASK (0xF000000U) 06079 #define TSI_GENCS_LPSCNITV_SHIFT (24U) 06080 #define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_LPSCNITV_SHIFT)) & TSI_GENCS_LPSCNITV_MASK) 06081 #define TSI_GENCS_LPCLKS_MASK (0x10000000U) 06082 #define TSI_GENCS_LPCLKS_SHIFT (28U) 06083 #define TSI_GENCS_LPCLKS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_LPCLKS_SHIFT)) & TSI_GENCS_LPCLKS_MASK) 06084 06085 /*! @name SCANC - SCAN Control Register */ 06086 #define TSI_SCANC_AMPSC_MASK (0x7U) 06087 #define TSI_SCANC_AMPSC_SHIFT (0U) 06088 #define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_AMPSC_SHIFT)) & TSI_SCANC_AMPSC_MASK) 06089 #define TSI_SCANC_AMCLKS_MASK (0x18U) 06090 #define TSI_SCANC_AMCLKS_SHIFT (3U) 06091 #define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_AMCLKS_SHIFT)) & TSI_SCANC_AMCLKS_MASK) 06092 #define TSI_SCANC_SMOD_MASK (0xFF00U) 06093 #define TSI_SCANC_SMOD_SHIFT (8U) 06094 #define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_SMOD_SHIFT)) & TSI_SCANC_SMOD_MASK) 06095 #define TSI_SCANC_EXTCHRG_MASK (0xF0000U) 06096 #define TSI_SCANC_EXTCHRG_SHIFT (16U) 06097 #define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_EXTCHRG_SHIFT)) & TSI_SCANC_EXTCHRG_MASK) 06098 #define TSI_SCANC_REFCHRG_MASK (0xF000000U) 06099 #define TSI_SCANC_REFCHRG_SHIFT (24U) 06100 #define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_SCANC_REFCHRG_SHIFT)) & TSI_SCANC_REFCHRG_MASK) 06101 06102 /*! @name PEN - Pin Enable Register */ 06103 #define TSI_PEN_PEN0_MASK (0x1U) 06104 #define TSI_PEN_PEN0_SHIFT (0U) 06105 #define TSI_PEN_PEN0(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN0_SHIFT)) & TSI_PEN_PEN0_MASK) 06106 #define TSI_PEN_PEN1_MASK (0x2U) 06107 #define TSI_PEN_PEN1_SHIFT (1U) 06108 #define TSI_PEN_PEN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN1_SHIFT)) & TSI_PEN_PEN1_MASK) 06109 #define TSI_PEN_PEN2_MASK (0x4U) 06110 #define TSI_PEN_PEN2_SHIFT (2U) 06111 #define TSI_PEN_PEN2(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN2_SHIFT)) & TSI_PEN_PEN2_MASK) 06112 #define TSI_PEN_PEN3_MASK (0x8U) 06113 #define TSI_PEN_PEN3_SHIFT (3U) 06114 #define TSI_PEN_PEN3(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN3_SHIFT)) & TSI_PEN_PEN3_MASK) 06115 #define TSI_PEN_PEN4_MASK (0x10U) 06116 #define TSI_PEN_PEN4_SHIFT (4U) 06117 #define TSI_PEN_PEN4(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN4_SHIFT)) & TSI_PEN_PEN4_MASK) 06118 #define TSI_PEN_PEN5_MASK (0x20U) 06119 #define TSI_PEN_PEN5_SHIFT (5U) 06120 #define TSI_PEN_PEN5(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN5_SHIFT)) & TSI_PEN_PEN5_MASK) 06121 #define TSI_PEN_PEN6_MASK (0x40U) 06122 #define TSI_PEN_PEN6_SHIFT (6U) 06123 #define TSI_PEN_PEN6(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN6_SHIFT)) & TSI_PEN_PEN6_MASK) 06124 #define TSI_PEN_PEN7_MASK (0x80U) 06125 #define TSI_PEN_PEN7_SHIFT (7U) 06126 #define TSI_PEN_PEN7(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN7_SHIFT)) & TSI_PEN_PEN7_MASK) 06127 #define TSI_PEN_PEN8_MASK (0x100U) 06128 #define TSI_PEN_PEN8_SHIFT (8U) 06129 #define TSI_PEN_PEN8(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN8_SHIFT)) & TSI_PEN_PEN8_MASK) 06130 #define TSI_PEN_PEN9_MASK (0x200U) 06131 #define TSI_PEN_PEN9_SHIFT (9U) 06132 #define TSI_PEN_PEN9(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN9_SHIFT)) & TSI_PEN_PEN9_MASK) 06133 #define TSI_PEN_PEN10_MASK (0x400U) 06134 #define TSI_PEN_PEN10_SHIFT (10U) 06135 #define TSI_PEN_PEN10(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN10_SHIFT)) & TSI_PEN_PEN10_MASK) 06136 #define TSI_PEN_PEN11_MASK (0x800U) 06137 #define TSI_PEN_PEN11_SHIFT (11U) 06138 #define TSI_PEN_PEN11(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN11_SHIFT)) & TSI_PEN_PEN11_MASK) 06139 #define TSI_PEN_PEN12_MASK (0x1000U) 06140 #define TSI_PEN_PEN12_SHIFT (12U) 06141 #define TSI_PEN_PEN12(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN12_SHIFT)) & TSI_PEN_PEN12_MASK) 06142 #define TSI_PEN_PEN13_MASK (0x2000U) 06143 #define TSI_PEN_PEN13_SHIFT (13U) 06144 #define TSI_PEN_PEN13(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN13_SHIFT)) & TSI_PEN_PEN13_MASK) 06145 #define TSI_PEN_PEN14_MASK (0x4000U) 06146 #define TSI_PEN_PEN14_SHIFT (14U) 06147 #define TSI_PEN_PEN14(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN14_SHIFT)) & TSI_PEN_PEN14_MASK) 06148 #define TSI_PEN_PEN15_MASK (0x8000U) 06149 #define TSI_PEN_PEN15_SHIFT (15U) 06150 #define TSI_PEN_PEN15(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_PEN15_SHIFT)) & TSI_PEN_PEN15_MASK) 06151 #define TSI_PEN_LPSP_MASK (0xF0000U) 06152 #define TSI_PEN_LPSP_SHIFT (16U) 06153 #define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x)) << TSI_PEN_LPSP_SHIFT)) & TSI_PEN_LPSP_MASK) 06154 06155 /*! @name WUCNTR - Wake-Up Channel Counter Register */ 06156 #define TSI_WUCNTR_WUCNT_MASK (0xFFFFU) 06157 #define TSI_WUCNTR_WUCNT_SHIFT (0U) 06158 #define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_WUCNTR_WUCNT_SHIFT)) & TSI_WUCNTR_WUCNT_MASK) 06159 06160 /*! @name CNTR1 - Counter Register */ 06161 #define TSI_CNTR1_CTN1_MASK (0xFFFFU) 06162 #define TSI_CNTR1_CTN1_SHIFT (0U) 06163 #define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR1_CTN1_SHIFT)) & TSI_CNTR1_CTN1_MASK) 06164 #define TSI_CNTR1_CTN_MASK (0xFFFF0000U) 06165 #define TSI_CNTR1_CTN_SHIFT (16U) 06166 #define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR1_CTN_SHIFT)) & TSI_CNTR1_CTN_MASK) 06167 06168 /*! @name CNTR3 - Counter Register */ 06169 #define TSI_CNTR3_CTN1_MASK (0xFFFFU) 06170 #define TSI_CNTR3_CTN1_SHIFT (0U) 06171 #define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR3_CTN1_SHIFT)) & TSI_CNTR3_CTN1_MASK) 06172 #define TSI_CNTR3_CTN_MASK (0xFFFF0000U) 06173 #define TSI_CNTR3_CTN_SHIFT (16U) 06174 #define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR3_CTN_SHIFT)) & TSI_CNTR3_CTN_MASK) 06175 06176 /*! @name CNTR5 - Counter Register */ 06177 #define TSI_CNTR5_CTN1_MASK (0xFFFFU) 06178 #define TSI_CNTR5_CTN1_SHIFT (0U) 06179 #define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR5_CTN1_SHIFT)) & TSI_CNTR5_CTN1_MASK) 06180 #define TSI_CNTR5_CTN_MASK (0xFFFF0000U) 06181 #define TSI_CNTR5_CTN_SHIFT (16U) 06182 #define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR5_CTN_SHIFT)) & TSI_CNTR5_CTN_MASK) 06183 06184 /*! @name CNTR7 - Counter Register */ 06185 #define TSI_CNTR7_CTN1_MASK (0xFFFFU) 06186 #define TSI_CNTR7_CTN1_SHIFT (0U) 06187 #define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR7_CTN1_SHIFT)) & TSI_CNTR7_CTN1_MASK) 06188 #define TSI_CNTR7_CTN_MASK (0xFFFF0000U) 06189 #define TSI_CNTR7_CTN_SHIFT (16U) 06190 #define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR7_CTN_SHIFT)) & TSI_CNTR7_CTN_MASK) 06191 06192 /*! @name CNTR9 - Counter Register */ 06193 #define TSI_CNTR9_CTN1_MASK (0xFFFFU) 06194 #define TSI_CNTR9_CTN1_SHIFT (0U) 06195 #define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR9_CTN1_SHIFT)) & TSI_CNTR9_CTN1_MASK) 06196 #define TSI_CNTR9_CTN_MASK (0xFFFF0000U) 06197 #define TSI_CNTR9_CTN_SHIFT (16U) 06198 #define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR9_CTN_SHIFT)) & TSI_CNTR9_CTN_MASK) 06199 06200 /*! @name CNTR11 - Counter Register */ 06201 #define TSI_CNTR11_CTN1_MASK (0xFFFFU) 06202 #define TSI_CNTR11_CTN1_SHIFT (0U) 06203 #define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR11_CTN1_SHIFT)) & TSI_CNTR11_CTN1_MASK) 06204 #define TSI_CNTR11_CTN_MASK (0xFFFF0000U) 06205 #define TSI_CNTR11_CTN_SHIFT (16U) 06206 #define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR11_CTN_SHIFT)) & TSI_CNTR11_CTN_MASK) 06207 06208 /*! @name CNTR13 - Counter Register */ 06209 #define TSI_CNTR13_CTN1_MASK (0xFFFFU) 06210 #define TSI_CNTR13_CTN1_SHIFT (0U) 06211 #define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR13_CTN1_SHIFT)) & TSI_CNTR13_CTN1_MASK) 06212 #define TSI_CNTR13_CTN_MASK (0xFFFF0000U) 06213 #define TSI_CNTR13_CTN_SHIFT (16U) 06214 #define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR13_CTN_SHIFT)) & TSI_CNTR13_CTN_MASK) 06215 06216 /*! @name CNTR15 - Counter Register */ 06217 #define TSI_CNTR15_CTN1_MASK (0xFFFFU) 06218 #define TSI_CNTR15_CTN1_SHIFT (0U) 06219 #define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR15_CTN1_SHIFT)) & TSI_CNTR15_CTN1_MASK) 06220 #define TSI_CNTR15_CTN_MASK (0xFFFF0000U) 06221 #define TSI_CNTR15_CTN_SHIFT (16U) 06222 #define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x)) << TSI_CNTR15_CTN_SHIFT)) & TSI_CNTR15_CTN_MASK) 06223 06224 /*! @name THRESHOLD - Low Power Channel Threshold Register */ 06225 #define TSI_THRESHOLD_HTHH_MASK (0xFFFFU) 06226 #define TSI_THRESHOLD_HTHH_SHIFT (0U) 06227 #define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x)) << TSI_THRESHOLD_HTHH_SHIFT)) & TSI_THRESHOLD_HTHH_MASK) 06228 #define TSI_THRESHOLD_LTHH_MASK (0xFFFF0000U) 06229 #define TSI_THRESHOLD_LTHH_SHIFT (16U) 06230 #define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x)) << TSI_THRESHOLD_LTHH_SHIFT)) & TSI_THRESHOLD_LTHH_MASK) 06231 06232 06233 /*! 06234 * @} 06235 */ /* end of group TSI_Register_Masks */ 06236 06237 06238 /* TSI - Peripheral instance base addresses */ 06239 /** Peripheral TSI0 base address */ 06240 #define TSI0_BASE (0x40045000u) 06241 /** Peripheral TSI0 base pointer */ 06242 #define TSI0 ((TSI_Type *)TSI0_BASE) 06243 /** Array initializer of TSI peripheral base addresses */ 06244 #define TSI_BASE_ADDRS { TSI0_BASE } 06245 /** Array initializer of TSI peripheral base pointers */ 06246 #define TSI_BASE_PTRS { TSI0 } 06247 /** Interrupt vectors for the TSI peripheral type */ 06248 #define TSI_IRQS { TSI0_IRQn } 06249 06250 /*! 06251 * @} 06252 */ /* end of group TSI_Peripheral_Access_Layer */ 06253 06254 06255 /* ---------------------------------------------------------------------------- 06256 -- UART Peripheral Access Layer 06257 ---------------------------------------------------------------------------- */ 06258 06259 /*! 06260 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer 06261 * @{ 06262 */ 06263 06264 /** UART - Register Layout Typedef */ 06265 typedef struct { 06266 __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */ 06267 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ 06268 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 06269 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 06270 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 06271 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 06272 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 06273 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 06274 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ 06275 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ 06276 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ 06277 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ 06278 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */ 06279 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */ 06280 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */ 06281 uint8_t RESERVED_0[1]; 06282 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */ 06283 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */ 06284 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */ 06285 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */ 06286 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */ 06287 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */ 06288 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */ 06289 uint8_t RESERVED_1[1]; 06290 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ 06291 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ 06292 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ 06293 union { /* offset: 0x1B */ 06294 __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ 06295 __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ 06296 }; 06297 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ 06298 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ 06299 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ 06300 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ 06301 uint8_t RESERVED_2[1]; 06302 __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */ 06303 __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */ 06304 __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */ 06305 __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */ 06306 __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */ 06307 __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */ 06308 __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */ 06309 __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */ 06310 __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */ 06311 __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */ 06312 __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */ 06313 __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */ 06314 __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */ 06315 __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */ 06316 __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */ 06317 __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */ 06318 __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */ 06319 } UART_Type; 06320 06321 /* ---------------------------------------------------------------------------- 06322 -- UART Register Masks 06323 ---------------------------------------------------------------------------- */ 06324 06325 /*! 06326 * @addtogroup UART_Register_Masks UART Register Masks 06327 * @{ 06328 */ 06329 06330 /*! @name BDH - UART Baud Rate Registers:High */ 06331 #define UART_BDH_SBR_MASK (0x1FU) 06332 #define UART_BDH_SBR_SHIFT (0U) 06333 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) 06334 #define UART_BDH_RXEDGIE_MASK (0x40U) 06335 #define UART_BDH_RXEDGIE_SHIFT (6U) 06336 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) 06337 #define UART_BDH_LBKDIE_MASK (0x80U) 06338 #define UART_BDH_LBKDIE_SHIFT (7U) 06339 #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK) 06340 06341 /*! @name BDL - UART Baud Rate Registers: Low */ 06342 #define UART_BDL_SBR_MASK (0xFFU) 06343 #define UART_BDL_SBR_SHIFT (0U) 06344 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) 06345 06346 /*! @name C1 - UART Control Register 1 */ 06347 #define UART_C1_PT_MASK (0x1U) 06348 #define UART_C1_PT_SHIFT (0U) 06349 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) 06350 #define UART_C1_PE_MASK (0x2U) 06351 #define UART_C1_PE_SHIFT (1U) 06352 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) 06353 #define UART_C1_ILT_MASK (0x4U) 06354 #define UART_C1_ILT_SHIFT (2U) 06355 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) 06356 #define UART_C1_WAKE_MASK (0x8U) 06357 #define UART_C1_WAKE_SHIFT (3U) 06358 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) 06359 #define UART_C1_M_MASK (0x10U) 06360 #define UART_C1_M_SHIFT (4U) 06361 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) 06362 #define UART_C1_RSRC_MASK (0x20U) 06363 #define UART_C1_RSRC_SHIFT (5U) 06364 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) 06365 #define UART_C1_UARTSWAI_MASK (0x40U) 06366 #define UART_C1_UARTSWAI_SHIFT (6U) 06367 #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK) 06368 #define UART_C1_LOOPS_MASK (0x80U) 06369 #define UART_C1_LOOPS_SHIFT (7U) 06370 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) 06371 06372 /*! @name C2 - UART Control Register 2 */ 06373 #define UART_C2_SBK_MASK (0x1U) 06374 #define UART_C2_SBK_SHIFT (0U) 06375 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) 06376 #define UART_C2_RWU_MASK (0x2U) 06377 #define UART_C2_RWU_SHIFT (1U) 06378 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) 06379 #define UART_C2_RE_MASK (0x4U) 06380 #define UART_C2_RE_SHIFT (2U) 06381 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) 06382 #define UART_C2_TE_MASK (0x8U) 06383 #define UART_C2_TE_SHIFT (3U) 06384 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) 06385 #define UART_C2_ILIE_MASK (0x10U) 06386 #define UART_C2_ILIE_SHIFT (4U) 06387 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) 06388 #define UART_C2_RIE_MASK (0x20U) 06389 #define UART_C2_RIE_SHIFT (5U) 06390 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) 06391 #define UART_C2_TCIE_MASK (0x40U) 06392 #define UART_C2_TCIE_SHIFT (6U) 06393 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) 06394 #define UART_C2_TIE_MASK (0x80U) 06395 #define UART_C2_TIE_SHIFT (7U) 06396 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) 06397 06398 /*! @name S1 - UART Status Register 1 */ 06399 #define UART_S1_PF_MASK (0x1U) 06400 #define UART_S1_PF_SHIFT (0U) 06401 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) 06402 #define UART_S1_FE_MASK (0x2U) 06403 #define UART_S1_FE_SHIFT (1U) 06404 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) 06405 #define UART_S1_NF_MASK (0x4U) 06406 #define UART_S1_NF_SHIFT (2U) 06407 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) 06408 #define UART_S1_OR_MASK (0x8U) 06409 #define UART_S1_OR_SHIFT (3U) 06410 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) 06411 #define UART_S1_IDLE_MASK (0x10U) 06412 #define UART_S1_IDLE_SHIFT (4U) 06413 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) 06414 #define UART_S1_RDRF_MASK (0x20U) 06415 #define UART_S1_RDRF_SHIFT (5U) 06416 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) 06417 #define UART_S1_TC_MASK (0x40U) 06418 #define UART_S1_TC_SHIFT (6U) 06419 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) 06420 #define UART_S1_TDRE_MASK (0x80U) 06421 #define UART_S1_TDRE_SHIFT (7U) 06422 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) 06423 06424 /*! @name S2 - UART Status Register 2 */ 06425 #define UART_S2_RAF_MASK (0x1U) 06426 #define UART_S2_RAF_SHIFT (0U) 06427 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) 06428 #define UART_S2_LBKDE_MASK (0x2U) 06429 #define UART_S2_LBKDE_SHIFT (1U) 06430 #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK) 06431 #define UART_S2_BRK13_MASK (0x4U) 06432 #define UART_S2_BRK13_SHIFT (2U) 06433 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) 06434 #define UART_S2_RWUID_MASK (0x8U) 06435 #define UART_S2_RWUID_SHIFT (3U) 06436 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) 06437 #define UART_S2_RXINV_MASK (0x10U) 06438 #define UART_S2_RXINV_SHIFT (4U) 06439 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) 06440 #define UART_S2_MSBF_MASK (0x20U) 06441 #define UART_S2_MSBF_SHIFT (5U) 06442 #define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK) 06443 #define UART_S2_RXEDGIF_MASK (0x40U) 06444 #define UART_S2_RXEDGIF_SHIFT (6U) 06445 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) 06446 #define UART_S2_LBKDIF_MASK (0x80U) 06447 #define UART_S2_LBKDIF_SHIFT (7U) 06448 #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK) 06449 06450 /*! @name C3 - UART Control Register 3 */ 06451 #define UART_C3_PEIE_MASK (0x1U) 06452 #define UART_C3_PEIE_SHIFT (0U) 06453 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) 06454 #define UART_C3_FEIE_MASK (0x2U) 06455 #define UART_C3_FEIE_SHIFT (1U) 06456 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) 06457 #define UART_C3_NEIE_MASK (0x4U) 06458 #define UART_C3_NEIE_SHIFT (2U) 06459 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) 06460 #define UART_C3_ORIE_MASK (0x8U) 06461 #define UART_C3_ORIE_SHIFT (3U) 06462 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) 06463 #define UART_C3_TXINV_MASK (0x10U) 06464 #define UART_C3_TXINV_SHIFT (4U) 06465 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) 06466 #define UART_C3_TXDIR_MASK (0x20U) 06467 #define UART_C3_TXDIR_SHIFT (5U) 06468 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) 06469 #define UART_C3_T8_MASK (0x40U) 06470 #define UART_C3_T8_SHIFT (6U) 06471 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) 06472 #define UART_C3_R8_MASK (0x80U) 06473 #define UART_C3_R8_SHIFT (7U) 06474 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) 06475 06476 /*! @name D - UART Data Register */ 06477 #define UART_D_RT_MASK (0xFFU) 06478 #define UART_D_RT_SHIFT (0U) 06479 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK) 06480 06481 /*! @name MA1 - UART Match Address Registers 1 */ 06482 #define UART_MA1_MA_MASK (0xFFU) 06483 #define UART_MA1_MA_SHIFT (0U) 06484 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK) 06485 06486 /*! @name MA2 - UART Match Address Registers 2 */ 06487 #define UART_MA2_MA_MASK (0xFFU) 06488 #define UART_MA2_MA_SHIFT (0U) 06489 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK) 06490 06491 /*! @name C4 - UART Control Register 4 */ 06492 #define UART_C4_BRFA_MASK (0x1FU) 06493 #define UART_C4_BRFA_SHIFT (0U) 06494 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK) 06495 #define UART_C4_M10_MASK (0x20U) 06496 #define UART_C4_M10_SHIFT (5U) 06497 #define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK) 06498 #define UART_C4_MAEN2_MASK (0x40U) 06499 #define UART_C4_MAEN2_SHIFT (6U) 06500 #define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK) 06501 #define UART_C4_MAEN1_MASK (0x80U) 06502 #define UART_C4_MAEN1_SHIFT (7U) 06503 #define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK) 06504 06505 /*! @name C5 - UART Control Register 5 */ 06506 #define UART_C5_RDMAS_MASK (0x20U) 06507 #define UART_C5_RDMAS_SHIFT (5U) 06508 #define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK) 06509 #define UART_C5_TDMAS_MASK (0x80U) 06510 #define UART_C5_TDMAS_SHIFT (7U) 06511 #define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK) 06512 06513 /*! @name ED - UART Extended Data Register */ 06514 #define UART_ED_PARITYE_MASK (0x40U) 06515 #define UART_ED_PARITYE_SHIFT (6U) 06516 #define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK) 06517 #define UART_ED_NOISY_MASK (0x80U) 06518 #define UART_ED_NOISY_SHIFT (7U) 06519 #define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK) 06520 06521 /*! @name MODEM - UART Modem Register */ 06522 #define UART_MODEM_TXCTSE_MASK (0x1U) 06523 #define UART_MODEM_TXCTSE_SHIFT (0U) 06524 #define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK) 06525 #define UART_MODEM_TXRTSE_MASK (0x2U) 06526 #define UART_MODEM_TXRTSE_SHIFT (1U) 06527 #define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK) 06528 #define UART_MODEM_TXRTSPOL_MASK (0x4U) 06529 #define UART_MODEM_TXRTSPOL_SHIFT (2U) 06530 #define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK) 06531 #define UART_MODEM_RXRTSE_MASK (0x8U) 06532 #define UART_MODEM_RXRTSE_SHIFT (3U) 06533 #define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK) 06534 06535 /*! @name IR - UART Infrared Register */ 06536 #define UART_IR_TNP_MASK (0x3U) 06537 #define UART_IR_TNP_SHIFT (0U) 06538 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK) 06539 #define UART_IR_IREN_MASK (0x4U) 06540 #define UART_IR_IREN_SHIFT (2U) 06541 #define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK) 06542 06543 /*! @name PFIFO - UART FIFO Parameters */ 06544 #define UART_PFIFO_RXFIFOSIZE_MASK (0x7U) 06545 #define UART_PFIFO_RXFIFOSIZE_SHIFT (0U) 06546 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK) 06547 #define UART_PFIFO_RXFE_MASK (0x8U) 06548 #define UART_PFIFO_RXFE_SHIFT (3U) 06549 #define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK) 06550 #define UART_PFIFO_TXFIFOSIZE_MASK (0x70U) 06551 #define UART_PFIFO_TXFIFOSIZE_SHIFT (4U) 06552 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK) 06553 #define UART_PFIFO_TXFE_MASK (0x80U) 06554 #define UART_PFIFO_TXFE_SHIFT (7U) 06555 #define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK) 06556 06557 /*! @name CFIFO - UART FIFO Control Register */ 06558 #define UART_CFIFO_RXUFE_MASK (0x1U) 06559 #define UART_CFIFO_RXUFE_SHIFT (0U) 06560 #define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK) 06561 #define UART_CFIFO_TXOFE_MASK (0x2U) 06562 #define UART_CFIFO_TXOFE_SHIFT (1U) 06563 #define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK) 06564 #define UART_CFIFO_RXFLUSH_MASK (0x40U) 06565 #define UART_CFIFO_RXFLUSH_SHIFT (6U) 06566 #define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK) 06567 #define UART_CFIFO_TXFLUSH_MASK (0x80U) 06568 #define UART_CFIFO_TXFLUSH_SHIFT (7U) 06569 #define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK) 06570 06571 /*! @name SFIFO - UART FIFO Status Register */ 06572 #define UART_SFIFO_RXUF_MASK (0x1U) 06573 #define UART_SFIFO_RXUF_SHIFT (0U) 06574 #define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK) 06575 #define UART_SFIFO_TXOF_MASK (0x2U) 06576 #define UART_SFIFO_TXOF_SHIFT (1U) 06577 #define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK) 06578 #define UART_SFIFO_RXEMPT_MASK (0x40U) 06579 #define UART_SFIFO_RXEMPT_SHIFT (6U) 06580 #define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK) 06581 #define UART_SFIFO_TXEMPT_MASK (0x80U) 06582 #define UART_SFIFO_TXEMPT_SHIFT (7U) 06583 #define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK) 06584 06585 /*! @name TWFIFO - UART FIFO Transmit Watermark */ 06586 #define UART_TWFIFO_TXWATER_MASK (0xFFU) 06587 #define UART_TWFIFO_TXWATER_SHIFT (0U) 06588 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK) 06589 06590 /*! @name TCFIFO - UART FIFO Transmit Count */ 06591 #define UART_TCFIFO_TXCOUNT_MASK (0xFFU) 06592 #define UART_TCFIFO_TXCOUNT_SHIFT (0U) 06593 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK) 06594 06595 /*! @name RWFIFO - UART FIFO Receive Watermark */ 06596 #define UART_RWFIFO_RXWATER_MASK (0xFFU) 06597 #define UART_RWFIFO_RXWATER_SHIFT (0U) 06598 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK) 06599 06600 /*! @name RCFIFO - UART FIFO Receive Count */ 06601 #define UART_RCFIFO_RXCOUNT_MASK (0xFFU) 06602 #define UART_RCFIFO_RXCOUNT_SHIFT (0U) 06603 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK) 06604 06605 /*! @name C7816 - UART 7816 Control Register */ 06606 #define UART_C7816_ISO_7816E_MASK (0x1U) 06607 #define UART_C7816_ISO_7816E_SHIFT (0U) 06608 #define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK) 06609 #define UART_C7816_TTYPE_MASK (0x2U) 06610 #define UART_C7816_TTYPE_SHIFT (1U) 06611 #define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK) 06612 #define UART_C7816_INIT_MASK (0x4U) 06613 #define UART_C7816_INIT_SHIFT (2U) 06614 #define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK) 06615 #define UART_C7816_ANACK_MASK (0x8U) 06616 #define UART_C7816_ANACK_SHIFT (3U) 06617 #define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK) 06618 #define UART_C7816_ONACK_MASK (0x10U) 06619 #define UART_C7816_ONACK_SHIFT (4U) 06620 #define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK) 06621 06622 /*! @name IE7816 - UART 7816 Interrupt Enable Register */ 06623 #define UART_IE7816_RXTE_MASK (0x1U) 06624 #define UART_IE7816_RXTE_SHIFT (0U) 06625 #define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK) 06626 #define UART_IE7816_TXTE_MASK (0x2U) 06627 #define UART_IE7816_TXTE_SHIFT (1U) 06628 #define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK) 06629 #define UART_IE7816_GTVE_MASK (0x4U) 06630 #define UART_IE7816_GTVE_SHIFT (2U) 06631 #define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK) 06632 #define UART_IE7816_INITDE_MASK (0x10U) 06633 #define UART_IE7816_INITDE_SHIFT (4U) 06634 #define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK) 06635 #define UART_IE7816_BWTE_MASK (0x20U) 06636 #define UART_IE7816_BWTE_SHIFT (5U) 06637 #define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK) 06638 #define UART_IE7816_CWTE_MASK (0x40U) 06639 #define UART_IE7816_CWTE_SHIFT (6U) 06640 #define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK) 06641 #define UART_IE7816_WTE_MASK (0x80U) 06642 #define UART_IE7816_WTE_SHIFT (7U) 06643 #define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK) 06644 06645 /*! @name IS7816 - UART 7816 Interrupt Status Register */ 06646 #define UART_IS7816_RXT_MASK (0x1U) 06647 #define UART_IS7816_RXT_SHIFT (0U) 06648 #define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK) 06649 #define UART_IS7816_TXT_MASK (0x2U) 06650 #define UART_IS7816_TXT_SHIFT (1U) 06651 #define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK) 06652 #define UART_IS7816_GTV_MASK (0x4U) 06653 #define UART_IS7816_GTV_SHIFT (2U) 06654 #define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK) 06655 #define UART_IS7816_INITD_MASK (0x10U) 06656 #define UART_IS7816_INITD_SHIFT (4U) 06657 #define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK) 06658 #define UART_IS7816_BWT_MASK (0x20U) 06659 #define UART_IS7816_BWT_SHIFT (5U) 06660 #define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK) 06661 #define UART_IS7816_CWT_MASK (0x40U) 06662 #define UART_IS7816_CWT_SHIFT (6U) 06663 #define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK) 06664 #define UART_IS7816_WT_MASK (0x80U) 06665 #define UART_IS7816_WT_SHIFT (7U) 06666 #define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK) 06667 06668 /*! @name WP7816T0 - UART 7816 Wait Parameter Register */ 06669 #define UART_WP7816T0_WI_MASK (0xFFU) 06670 #define UART_WP7816T0_WI_SHIFT (0U) 06671 #define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK) 06672 06673 /*! @name WP7816T1 - UART 7816 Wait Parameter Register */ 06674 #define UART_WP7816T1_BWI_MASK (0xFU) 06675 #define UART_WP7816T1_BWI_SHIFT (0U) 06676 #define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK) 06677 #define UART_WP7816T1_CWI_MASK (0xF0U) 06678 #define UART_WP7816T1_CWI_SHIFT (4U) 06679 #define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK) 06680 06681 /*! @name WN7816 - UART 7816 Wait N Register */ 06682 #define UART_WN7816_GTN_MASK (0xFFU) 06683 #define UART_WN7816_GTN_SHIFT (0U) 06684 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK) 06685 06686 /*! @name WF7816 - UART 7816 Wait FD Register */ 06687 #define UART_WF7816_GTFD_MASK (0xFFU) 06688 #define UART_WF7816_GTFD_SHIFT (0U) 06689 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK) 06690 06691 /*! @name ET7816 - UART 7816 Error Threshold Register */ 06692 #define UART_ET7816_RXTHRESHOLD_MASK (0xFU) 06693 #define UART_ET7816_RXTHRESHOLD_SHIFT (0U) 06694 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK) 06695 #define UART_ET7816_TXTHRESHOLD_MASK (0xF0U) 06696 #define UART_ET7816_TXTHRESHOLD_SHIFT (4U) 06697 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK) 06698 06699 /*! @name TL7816 - UART 7816 Transmit Length Register */ 06700 #define UART_TL7816_TLEN_MASK (0xFFU) 06701 #define UART_TL7816_TLEN_SHIFT (0U) 06702 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK) 06703 06704 /*! @name C6 - UART CEA709.1-B Control Register 6 */ 06705 #define UART_C6_CP_MASK (0x10U) 06706 #define UART_C6_CP_SHIFT (4U) 06707 #define UART_C6_CP(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_CP_SHIFT)) & UART_C6_CP_MASK) 06708 #define UART_C6_CE_MASK (0x20U) 06709 #define UART_C6_CE_SHIFT (5U) 06710 #define UART_C6_CE(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_CE_SHIFT)) & UART_C6_CE_MASK) 06711 #define UART_C6_TX709_MASK (0x40U) 06712 #define UART_C6_TX709_SHIFT (6U) 06713 #define UART_C6_TX709(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_TX709_SHIFT)) & UART_C6_TX709_MASK) 06714 #define UART_C6_EN709_MASK (0x80U) 06715 #define UART_C6_EN709_SHIFT (7U) 06716 #define UART_C6_EN709(x) (((uint8_t)(((uint8_t)(x)) << UART_C6_EN709_SHIFT)) & UART_C6_EN709_MASK) 06717 06718 /*! @name PCTH - UART CEA709.1-B Packet Cycle Time Counter High */ 06719 #define UART_PCTH_PCTH_MASK (0xFFU) 06720 #define UART_PCTH_PCTH_SHIFT (0U) 06721 #define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x)) << UART_PCTH_PCTH_SHIFT)) & UART_PCTH_PCTH_MASK) 06722 06723 /*! @name PCTL - UART CEA709.1-B Packet Cycle Time Counter Low */ 06724 #define UART_PCTL_PCTL_MASK (0xFFU) 06725 #define UART_PCTL_PCTL_SHIFT (0U) 06726 #define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x)) << UART_PCTL_PCTL_SHIFT)) & UART_PCTL_PCTL_MASK) 06727 06728 /*! @name B1T - UART CEA709.1-B Beta1 Timer */ 06729 #define UART_B1T_B1T_MASK (0xFFU) 06730 #define UART_B1T_B1T_SHIFT (0U) 06731 #define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x)) << UART_B1T_B1T_SHIFT)) & UART_B1T_B1T_MASK) 06732 06733 /*! @name SDTH - UART CEA709.1-B Secondary Delay Timer High */ 06734 #define UART_SDTH_SDTH_MASK (0xFFU) 06735 #define UART_SDTH_SDTH_SHIFT (0U) 06736 #define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x)) << UART_SDTH_SDTH_SHIFT)) & UART_SDTH_SDTH_MASK) 06737 06738 /*! @name SDTL - UART CEA709.1-B Secondary Delay Timer Low */ 06739 #define UART_SDTL_SDTL_MASK (0xFFU) 06740 #define UART_SDTL_SDTL_SHIFT (0U) 06741 #define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x)) << UART_SDTL_SDTL_SHIFT)) & UART_SDTL_SDTL_MASK) 06742 06743 /*! @name PRE - UART CEA709.1-B Preamble */ 06744 #define UART_PRE_PREAMBLE_MASK (0xFFU) 06745 #define UART_PRE_PREAMBLE_SHIFT (0U) 06746 #define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x)) << UART_PRE_PREAMBLE_SHIFT)) & UART_PRE_PREAMBLE_MASK) 06747 06748 /*! @name TPL - UART CEA709.1-B Transmit Packet Length */ 06749 #define UART_TPL_TPL_MASK (0xFFU) 06750 #define UART_TPL_TPL_SHIFT (0U) 06751 #define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x)) << UART_TPL_TPL_SHIFT)) & UART_TPL_TPL_MASK) 06752 06753 /*! @name IE - UART CEA709.1-B Interrupt Enable Register */ 06754 #define UART_IE_TXFIE_MASK (0x1U) 06755 #define UART_IE_TXFIE_SHIFT (0U) 06756 #define UART_IE_TXFIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_TXFIE_SHIFT)) & UART_IE_TXFIE_MASK) 06757 #define UART_IE_PSIE_MASK (0x2U) 06758 #define UART_IE_PSIE_SHIFT (1U) 06759 #define UART_IE_PSIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PSIE_SHIFT)) & UART_IE_PSIE_MASK) 06760 #define UART_IE_PCTEIE_MASK (0x4U) 06761 #define UART_IE_PCTEIE_SHIFT (2U) 06762 #define UART_IE_PCTEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PCTEIE_SHIFT)) & UART_IE_PCTEIE_MASK) 06763 #define UART_IE_PTXIE_MASK (0x8U) 06764 #define UART_IE_PTXIE_SHIFT (3U) 06765 #define UART_IE_PTXIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PTXIE_SHIFT)) & UART_IE_PTXIE_MASK) 06766 #define UART_IE_PRXIE_MASK (0x10U) 06767 #define UART_IE_PRXIE_SHIFT (4U) 06768 #define UART_IE_PRXIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_PRXIE_SHIFT)) & UART_IE_PRXIE_MASK) 06769 #define UART_IE_ISDIE_MASK (0x20U) 06770 #define UART_IE_ISDIE_SHIFT (5U) 06771 #define UART_IE_ISDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_ISDIE_SHIFT)) & UART_IE_ISDIE_MASK) 06772 #define UART_IE_WBEIE_MASK (0x40U) 06773 #define UART_IE_WBEIE_SHIFT (6U) 06774 #define UART_IE_WBEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE_WBEIE_SHIFT)) & UART_IE_WBEIE_MASK) 06775 06776 /*! @name WB - UART CEA709.1-B WBASE */ 06777 #define UART_WB_WBASE_MASK (0xFFU) 06778 #define UART_WB_WBASE_SHIFT (0U) 06779 #define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x)) << UART_WB_WBASE_SHIFT)) & UART_WB_WBASE_MASK) 06780 06781 /*! @name S3 - UART CEA709.1-B Status Register */ 06782 #define UART_S3_TXFF_MASK (0x1U) 06783 #define UART_S3_TXFF_SHIFT (0U) 06784 #define UART_S3_TXFF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_TXFF_SHIFT)) & UART_S3_TXFF_MASK) 06785 #define UART_S3_PSF_MASK (0x2U) 06786 #define UART_S3_PSF_SHIFT (1U) 06787 #define UART_S3_PSF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PSF_SHIFT)) & UART_S3_PSF_MASK) 06788 #define UART_S3_PCTEF_MASK (0x4U) 06789 #define UART_S3_PCTEF_SHIFT (2U) 06790 #define UART_S3_PCTEF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PCTEF_SHIFT)) & UART_S3_PCTEF_MASK) 06791 #define UART_S3_PTXF_MASK (0x8U) 06792 #define UART_S3_PTXF_SHIFT (3U) 06793 #define UART_S3_PTXF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PTXF_SHIFT)) & UART_S3_PTXF_MASK) 06794 #define UART_S3_PRXF_MASK (0x10U) 06795 #define UART_S3_PRXF_SHIFT (4U) 06796 #define UART_S3_PRXF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PRXF_SHIFT)) & UART_S3_PRXF_MASK) 06797 #define UART_S3_ISD_MASK (0x20U) 06798 #define UART_S3_ISD_SHIFT (5U) 06799 #define UART_S3_ISD(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_ISD_SHIFT)) & UART_S3_ISD_MASK) 06800 #define UART_S3_WBEF_MASK (0x40U) 06801 #define UART_S3_WBEF_SHIFT (6U) 06802 #define UART_S3_WBEF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_WBEF_SHIFT)) & UART_S3_WBEF_MASK) 06803 #define UART_S3_PEF_MASK (0x80U) 06804 #define UART_S3_PEF_SHIFT (7U) 06805 #define UART_S3_PEF(x) (((uint8_t)(((uint8_t)(x)) << UART_S3_PEF_SHIFT)) & UART_S3_PEF_MASK) 06806 06807 /*! @name S4 - UART CEA709.1-B Status Register */ 06808 #define UART_S4_FE_MASK (0x1U) 06809 #define UART_S4_FE_SHIFT (0U) 06810 #define UART_S4_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_FE_SHIFT)) & UART_S4_FE_MASK) 06811 #define UART_S4_ILCV_MASK (0x2U) 06812 #define UART_S4_ILCV_SHIFT (1U) 06813 #define UART_S4_ILCV(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_ILCV_SHIFT)) & UART_S4_ILCV_MASK) 06814 #define UART_S4_CDET_MASK (0xCU) 06815 #define UART_S4_CDET_SHIFT (2U) 06816 #define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_CDET_SHIFT)) & UART_S4_CDET_MASK) 06817 #define UART_S4_INITF_MASK (0x10U) 06818 #define UART_S4_INITF_SHIFT (4U) 06819 #define UART_S4_INITF(x) (((uint8_t)(((uint8_t)(x)) << UART_S4_INITF_SHIFT)) & UART_S4_INITF_MASK) 06820 06821 /*! @name RPL - UART CEA709.1-B Received Packet Length */ 06822 #define UART_RPL_RPL_MASK (0xFFU) 06823 #define UART_RPL_RPL_SHIFT (0U) 06824 #define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x)) << UART_RPL_RPL_SHIFT)) & UART_RPL_RPL_MASK) 06825 06826 /*! @name RPREL - UART CEA709.1-B Received Preamble Length */ 06827 #define UART_RPREL_RPREL_MASK (0xFFU) 06828 #define UART_RPREL_RPREL_SHIFT (0U) 06829 #define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x)) << UART_RPREL_RPREL_SHIFT)) & UART_RPREL_RPREL_MASK) 06830 06831 /*! @name CPW - UART CEA709.1-B Collision Pulse Width */ 06832 #define UART_CPW_CPW_MASK (0xFFU) 06833 #define UART_CPW_CPW_SHIFT (0U) 06834 #define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x)) << UART_CPW_CPW_SHIFT)) & UART_CPW_CPW_MASK) 06835 06836 /*! @name RIDT - UART CEA709.1-B Receive Indeterminate Time */ 06837 #define UART_RIDT_RIDT_MASK (0xFFU) 06838 #define UART_RIDT_RIDT_SHIFT (0U) 06839 #define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x)) << UART_RIDT_RIDT_SHIFT)) & UART_RIDT_RIDT_MASK) 06840 06841 /*! @name TIDT - UART CEA709.1-B Transmit Indeterminate Time */ 06842 #define UART_TIDT_TIDT_MASK (0xFFU) 06843 #define UART_TIDT_TIDT_SHIFT (0U) 06844 #define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x)) << UART_TIDT_TIDT_SHIFT)) & UART_TIDT_TIDT_MASK) 06845 06846 06847 /*! 06848 * @} 06849 */ /* end of group UART_Register_Masks */ 06850 06851 06852 /* UART - Peripheral instance base addresses */ 06853 /** Peripheral UART0 base address */ 06854 #define UART0_BASE (0x4006A000u) 06855 /** Peripheral UART0 base pointer */ 06856 #define UART0 ((UART_Type *)UART0_BASE) 06857 /** Peripheral UART1 base address */ 06858 #define UART1_BASE (0x4006B000u) 06859 /** Peripheral UART1 base pointer */ 06860 #define UART1 ((UART_Type *)UART1_BASE) 06861 /** Peripheral UART2 base address */ 06862 #define UART2_BASE (0x4006C000u) 06863 /** Peripheral UART2 base pointer */ 06864 #define UART2 ((UART_Type *)UART2_BASE) 06865 /** Array initializer of UART peripheral base addresses */ 06866 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE } 06867 /** Array initializer of UART peripheral base pointers */ 06868 #define UART_BASE_PTRS { UART0, UART1, UART2 } 06869 /** Interrupt vectors for the UART peripheral type */ 06870 #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn } 06871 #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn } 06872 #define UART_LON_IRQS { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn } 06873 06874 /*! 06875 * @} 06876 */ /* end of group UART_Peripheral_Access_Layer */ 06877 06878 06879 /* ---------------------------------------------------------------------------- 06880 -- USB Peripheral Access Layer 06881 ---------------------------------------------------------------------------- */ 06882 06883 /*! 06884 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer 06885 * @{ 06886 */ 06887 06888 /** USB - Register Layout Typedef */ 06889 typedef struct { 06890 __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */ 06891 uint8_t RESERVED_0[3]; 06892 __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */ 06893 uint8_t RESERVED_1[3]; 06894 __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */ 06895 uint8_t RESERVED_2[3]; 06896 __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */ 06897 uint8_t RESERVED_3[3]; 06898 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */ 06899 uint8_t RESERVED_4[3]; 06900 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */ 06901 uint8_t RESERVED_5[3]; 06902 __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */ 06903 uint8_t RESERVED_6[3]; 06904 __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */ 06905 uint8_t RESERVED_7[99]; 06906 __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */ 06907 uint8_t RESERVED_8[3]; 06908 __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */ 06909 uint8_t RESERVED_9[3]; 06910 __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */ 06911 uint8_t RESERVED_10[3]; 06912 __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */ 06913 uint8_t RESERVED_11[3]; 06914 __I uint8_t STAT; /**< Status Register, offset: 0x90 */ 06915 uint8_t RESERVED_12[3]; 06916 __IO uint8_t CTL; /**< Control Register, offset: 0x94 */ 06917 uint8_t RESERVED_13[3]; 06918 __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */ 06919 uint8_t RESERVED_14[3]; 06920 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */ 06921 uint8_t RESERVED_15[3]; 06922 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */ 06923 uint8_t RESERVED_16[3]; 06924 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */ 06925 uint8_t RESERVED_17[3]; 06926 __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */ 06927 uint8_t RESERVED_18[3]; 06928 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */ 06929 uint8_t RESERVED_19[3]; 06930 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ 06931 uint8_t RESERVED_20[3]; 06932 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ 06933 uint8_t RESERVED_21[11]; 06934 struct { /* offset: 0xC0, array step: 0x4 */ 06935 __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */ 06936 uint8_t RESERVED_0[3]; 06937 } ENDPOINT[16]; 06938 __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */ 06939 uint8_t RESERVED_22[3]; 06940 __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */ 06941 uint8_t RESERVED_23[3]; 06942 __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */ 06943 uint8_t RESERVED_24[3]; 06944 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */ 06945 uint8_t RESERVED_25[7]; 06946 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ 06947 } USB_Type; 06948 06949 /* ---------------------------------------------------------------------------- 06950 -- USB Register Masks 06951 ---------------------------------------------------------------------------- */ 06952 06953 /*! 06954 * @addtogroup USB_Register_Masks USB Register Masks 06955 * @{ 06956 */ 06957 06958 /*! @name PERID - Peripheral ID Register */ 06959 #define USB_PERID_ID_MASK (0x3FU) 06960 #define USB_PERID_ID_SHIFT (0U) 06961 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) 06962 06963 /*! @name IDCOMP - Peripheral ID Complement Register */ 06964 #define USB_IDCOMP_NID_MASK (0x3FU) 06965 #define USB_IDCOMP_NID_SHIFT (0U) 06966 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) 06967 06968 /*! @name REV - Peripheral Revision Register */ 06969 #define USB_REV_REV_MASK (0xFFU) 06970 #define USB_REV_REV_SHIFT (0U) 06971 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) 06972 06973 /*! @name ADDINFO - Peripheral Additional Info Register */ 06974 #define USB_ADDINFO_IEHOST_MASK (0x1U) 06975 #define USB_ADDINFO_IEHOST_SHIFT (0U) 06976 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) 06977 #define USB_ADDINFO_IRQNUM_MASK (0xF8U) 06978 #define USB_ADDINFO_IRQNUM_SHIFT (3U) 06979 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK) 06980 06981 /*! @name OTGISTAT - OTG Interrupt Status Register */ 06982 #define USB_OTGISTAT_AVBUSCHG_MASK (0x1U) 06983 #define USB_OTGISTAT_AVBUSCHG_SHIFT (0U) 06984 #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK) 06985 #define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U) 06986 #define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U) 06987 #define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK) 06988 #define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U) 06989 #define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U) 06990 #define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK) 06991 #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) 06992 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) 06993 #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) 06994 #define USB_OTGISTAT_ONEMSEC_MASK (0x40U) 06995 #define USB_OTGISTAT_ONEMSEC_SHIFT (6U) 06996 #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) 06997 #define USB_OTGISTAT_IDCHG_MASK (0x80U) 06998 #define USB_OTGISTAT_IDCHG_SHIFT (7U) 06999 #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK) 07000 07001 /*! @name OTGICR - OTG Interrupt Control Register */ 07002 #define USB_OTGICR_AVBUSEN_MASK (0x1U) 07003 #define USB_OTGICR_AVBUSEN_SHIFT (0U) 07004 #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK) 07005 #define USB_OTGICR_BSESSEN_MASK (0x4U) 07006 #define USB_OTGICR_BSESSEN_SHIFT (2U) 07007 #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK) 07008 #define USB_OTGICR_SESSVLDEN_MASK (0x8U) 07009 #define USB_OTGICR_SESSVLDEN_SHIFT (3U) 07010 #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK) 07011 #define USB_OTGICR_LINESTATEEN_MASK (0x20U) 07012 #define USB_OTGICR_LINESTATEEN_SHIFT (5U) 07013 #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) 07014 #define USB_OTGICR_ONEMSECEN_MASK (0x40U) 07015 #define USB_OTGICR_ONEMSECEN_SHIFT (6U) 07016 #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) 07017 #define USB_OTGICR_IDEN_MASK (0x80U) 07018 #define USB_OTGICR_IDEN_SHIFT (7U) 07019 #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK) 07020 07021 /*! @name OTGSTAT - OTG Status Register */ 07022 #define USB_OTGSTAT_AVBUSVLD_MASK (0x1U) 07023 #define USB_OTGSTAT_AVBUSVLD_SHIFT (0U) 07024 #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK) 07025 #define USB_OTGSTAT_BSESSEND_MASK (0x4U) 07026 #define USB_OTGSTAT_BSESSEND_SHIFT (2U) 07027 #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK) 07028 #define USB_OTGSTAT_SESS_VLD_MASK (0x8U) 07029 #define USB_OTGSTAT_SESS_VLD_SHIFT (3U) 07030 #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK) 07031 #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) 07032 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) 07033 #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) 07034 #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U) 07035 #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U) 07036 #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK) 07037 #define USB_OTGSTAT_ID_MASK (0x80U) 07038 #define USB_OTGSTAT_ID_SHIFT (7U) 07039 #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK) 07040 07041 /*! @name OTGCTL - OTG Control Register */ 07042 #define USB_OTGCTL_OTGEN_MASK (0x4U) 07043 #define USB_OTGCTL_OTGEN_SHIFT (2U) 07044 #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) 07045 #define USB_OTGCTL_DMLOW_MASK (0x10U) 07046 #define USB_OTGCTL_DMLOW_SHIFT (4U) 07047 #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) 07048 #define USB_OTGCTL_DPLOW_MASK (0x20U) 07049 #define USB_OTGCTL_DPLOW_SHIFT (5U) 07050 #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) 07051 #define USB_OTGCTL_DPHIGH_MASK (0x80U) 07052 #define USB_OTGCTL_DPHIGH_SHIFT (7U) 07053 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) 07054 07055 /*! @name ISTAT - Interrupt Status Register */ 07056 #define USB_ISTAT_USBRST_MASK (0x1U) 07057 #define USB_ISTAT_USBRST_SHIFT (0U) 07058 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) 07059 #define USB_ISTAT_ERROR_MASK (0x2U) 07060 #define USB_ISTAT_ERROR_SHIFT (1U) 07061 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) 07062 #define USB_ISTAT_SOFTOK_MASK (0x4U) 07063 #define USB_ISTAT_SOFTOK_SHIFT (2U) 07064 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) 07065 #define USB_ISTAT_TOKDNE_MASK (0x8U) 07066 #define USB_ISTAT_TOKDNE_SHIFT (3U) 07067 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) 07068 #define USB_ISTAT_SLEEP_MASK (0x10U) 07069 #define USB_ISTAT_SLEEP_SHIFT (4U) 07070 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) 07071 #define USB_ISTAT_RESUME_MASK (0x20U) 07072 #define USB_ISTAT_RESUME_SHIFT (5U) 07073 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) 07074 #define USB_ISTAT_ATTACH_MASK (0x40U) 07075 #define USB_ISTAT_ATTACH_SHIFT (6U) 07076 #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) 07077 #define USB_ISTAT_STALL_MASK (0x80U) 07078 #define USB_ISTAT_STALL_SHIFT (7U) 07079 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) 07080 07081 /*! @name INTEN - Interrupt Enable Register */ 07082 #define USB_INTEN_USBRSTEN_MASK (0x1U) 07083 #define USB_INTEN_USBRSTEN_SHIFT (0U) 07084 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) 07085 #define USB_INTEN_ERROREN_MASK (0x2U) 07086 #define USB_INTEN_ERROREN_SHIFT (1U) 07087 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) 07088 #define USB_INTEN_SOFTOKEN_MASK (0x4U) 07089 #define USB_INTEN_SOFTOKEN_SHIFT (2U) 07090 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) 07091 #define USB_INTEN_TOKDNEEN_MASK (0x8U) 07092 #define USB_INTEN_TOKDNEEN_SHIFT (3U) 07093 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) 07094 #define USB_INTEN_SLEEPEN_MASK (0x10U) 07095 #define USB_INTEN_SLEEPEN_SHIFT (4U) 07096 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) 07097 #define USB_INTEN_RESUMEEN_MASK (0x20U) 07098 #define USB_INTEN_RESUMEEN_SHIFT (5U) 07099 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) 07100 #define USB_INTEN_ATTACHEN_MASK (0x40U) 07101 #define USB_INTEN_ATTACHEN_SHIFT (6U) 07102 #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) 07103 #define USB_INTEN_STALLEN_MASK (0x80U) 07104 #define USB_INTEN_STALLEN_SHIFT (7U) 07105 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) 07106 07107 /*! @name ERRSTAT - Error Interrupt Status Register */ 07108 #define USB_ERRSTAT_PIDERR_MASK (0x1U) 07109 #define USB_ERRSTAT_PIDERR_SHIFT (0U) 07110 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) 07111 #define USB_ERRSTAT_CRC5EOF_MASK (0x2U) 07112 #define USB_ERRSTAT_CRC5EOF_SHIFT (1U) 07113 #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) 07114 #define USB_ERRSTAT_CRC16_MASK (0x4U) 07115 #define USB_ERRSTAT_CRC16_SHIFT (2U) 07116 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) 07117 #define USB_ERRSTAT_DFN8_MASK (0x8U) 07118 #define USB_ERRSTAT_DFN8_SHIFT (3U) 07119 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) 07120 #define USB_ERRSTAT_BTOERR_MASK (0x10U) 07121 #define USB_ERRSTAT_BTOERR_SHIFT (4U) 07122 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) 07123 #define USB_ERRSTAT_DMAERR_MASK (0x20U) 07124 #define USB_ERRSTAT_DMAERR_SHIFT (5U) 07125 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) 07126 #define USB_ERRSTAT_BTSERR_MASK (0x80U) 07127 #define USB_ERRSTAT_BTSERR_SHIFT (7U) 07128 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) 07129 07130 /*! @name ERREN - Error Interrupt Enable Register */ 07131 #define USB_ERREN_PIDERREN_MASK (0x1U) 07132 #define USB_ERREN_PIDERREN_SHIFT (0U) 07133 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) 07134 #define USB_ERREN_CRC5EOFEN_MASK (0x2U) 07135 #define USB_ERREN_CRC5EOFEN_SHIFT (1U) 07136 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) 07137 #define USB_ERREN_CRC16EN_MASK (0x4U) 07138 #define USB_ERREN_CRC16EN_SHIFT (2U) 07139 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) 07140 #define USB_ERREN_DFN8EN_MASK (0x8U) 07141 #define USB_ERREN_DFN8EN_SHIFT (3U) 07142 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) 07143 #define USB_ERREN_BTOERREN_MASK (0x10U) 07144 #define USB_ERREN_BTOERREN_SHIFT (4U) 07145 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) 07146 #define USB_ERREN_DMAERREN_MASK (0x20U) 07147 #define USB_ERREN_DMAERREN_SHIFT (5U) 07148 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) 07149 #define USB_ERREN_BTSERREN_MASK (0x80U) 07150 #define USB_ERREN_BTSERREN_SHIFT (7U) 07151 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) 07152 07153 /*! @name STAT - Status Register */ 07154 #define USB_STAT_ODD_MASK (0x4U) 07155 #define USB_STAT_ODD_SHIFT (2U) 07156 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) 07157 #define USB_STAT_TX_MASK (0x8U) 07158 #define USB_STAT_TX_SHIFT (3U) 07159 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) 07160 #define USB_STAT_ENDP_MASK (0xF0U) 07161 #define USB_STAT_ENDP_SHIFT (4U) 07162 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) 07163 07164 /*! @name CTL - Control Register */ 07165 #define USB_CTL_USBENSOFEN_MASK (0x1U) 07166 #define USB_CTL_USBENSOFEN_SHIFT (0U) 07167 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) 07168 #define USB_CTL_ODDRST_MASK (0x2U) 07169 #define USB_CTL_ODDRST_SHIFT (1U) 07170 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) 07171 #define USB_CTL_RESUME_MASK (0x4U) 07172 #define USB_CTL_RESUME_SHIFT (2U) 07173 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) 07174 #define USB_CTL_HOSTMODEEN_MASK (0x8U) 07175 #define USB_CTL_HOSTMODEEN_SHIFT (3U) 07176 #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) 07177 #define USB_CTL_RESET_MASK (0x10U) 07178 #define USB_CTL_RESET_SHIFT (4U) 07179 #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) 07180 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) 07181 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) 07182 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) 07183 #define USB_CTL_SE0_MASK (0x40U) 07184 #define USB_CTL_SE0_SHIFT (6U) 07185 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) 07186 #define USB_CTL_JSTATE_MASK (0x80U) 07187 #define USB_CTL_JSTATE_SHIFT (7U) 07188 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) 07189 07190 /*! @name ADDR - Address Register */ 07191 #define USB_ADDR_ADDR_MASK (0x7FU) 07192 #define USB_ADDR_ADDR_SHIFT (0U) 07193 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) 07194 #define USB_ADDR_LSEN_MASK (0x80U) 07195 #define USB_ADDR_LSEN_SHIFT (7U) 07196 #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) 07197 07198 /*! @name BDTPAGE1 - BDT Page Register 1 */ 07199 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU) 07200 #define USB_BDTPAGE1_BDTBA_SHIFT (1U) 07201 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) 07202 07203 /*! @name FRMNUML - Frame Number Register Low */ 07204 #define USB_FRMNUML_FRM_MASK (0xFFU) 07205 #define USB_FRMNUML_FRM_SHIFT (0U) 07206 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) 07207 07208 /*! @name FRMNUMH - Frame Number Register High */ 07209 #define USB_FRMNUMH_FRM_MASK (0x7U) 07210 #define USB_FRMNUMH_FRM_SHIFT (0U) 07211 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) 07212 07213 /*! @name TOKEN - Token Register */ 07214 #define USB_TOKEN_TOKENENDPT_MASK (0xFU) 07215 #define USB_TOKEN_TOKENENDPT_SHIFT (0U) 07216 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) 07217 #define USB_TOKEN_TOKENPID_MASK (0xF0U) 07218 #define USB_TOKEN_TOKENPID_SHIFT (4U) 07219 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) 07220 07221 /*! @name SOFTHLD - SOF Threshold Register */ 07222 #define USB_SOFTHLD_CNT_MASK (0xFFU) 07223 #define USB_SOFTHLD_CNT_SHIFT (0U) 07224 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) 07225 07226 /*! @name BDTPAGE2 - BDT Page Register 2 */ 07227 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU) 07228 #define USB_BDTPAGE2_BDTBA_SHIFT (0U) 07229 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) 07230 07231 /*! @name BDTPAGE3 - BDT Page Register 3 */ 07232 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU) 07233 #define USB_BDTPAGE3_BDTBA_SHIFT (0U) 07234 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) 07235 07236 /*! @name ENDPT - Endpoint Control Register */ 07237 #define USB_ENDPT_EPHSHK_MASK (0x1U) 07238 #define USB_ENDPT_EPHSHK_SHIFT (0U) 07239 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) 07240 #define USB_ENDPT_EPSTALL_MASK (0x2U) 07241 #define USB_ENDPT_EPSTALL_SHIFT (1U) 07242 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) 07243 #define USB_ENDPT_EPTXEN_MASK (0x4U) 07244 #define USB_ENDPT_EPTXEN_SHIFT (2U) 07245 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) 07246 #define USB_ENDPT_EPRXEN_MASK (0x8U) 07247 #define USB_ENDPT_EPRXEN_SHIFT (3U) 07248 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) 07249 #define USB_ENDPT_EPCTLDIS_MASK (0x10U) 07250 #define USB_ENDPT_EPCTLDIS_SHIFT (4U) 07251 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) 07252 #define USB_ENDPT_RETRYDIS_MASK (0x40U) 07253 #define USB_ENDPT_RETRYDIS_SHIFT (6U) 07254 #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) 07255 #define USB_ENDPT_HOSTWOHUB_MASK (0x80U) 07256 #define USB_ENDPT_HOSTWOHUB_SHIFT (7U) 07257 #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) 07258 07259 /* The count of USB_ENDPT */ 07260 #define USB_ENDPT_COUNT (16U) 07261 07262 /*! @name USBCTRL - USB Control Register */ 07263 #define USB_USBCTRL_PDE_MASK (0x40U) 07264 #define USB_USBCTRL_PDE_SHIFT (6U) 07265 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) 07266 #define USB_USBCTRL_SUSP_MASK (0x80U) 07267 #define USB_USBCTRL_SUSP_SHIFT (7U) 07268 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) 07269 07270 /*! @name OBSERVE - USB OTG Observe Register */ 07271 #define USB_OBSERVE_DMPD_MASK (0x10U) 07272 #define USB_OBSERVE_DMPD_SHIFT (4U) 07273 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) 07274 #define USB_OBSERVE_DPPD_MASK (0x40U) 07275 #define USB_OBSERVE_DPPD_SHIFT (6U) 07276 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) 07277 #define USB_OBSERVE_DPPU_MASK (0x80U) 07278 #define USB_OBSERVE_DPPU_SHIFT (7U) 07279 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) 07280 07281 /*! @name CONTROL - USB OTG Control Register */ 07282 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) 07283 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) 07284 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) 07285 07286 /*! @name USBTRC0 - USB Transceiver Control Register 0 */ 07287 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) 07288 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) 07289 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) 07290 #define USB_USBTRC0_SYNC_DET_MASK (0x2U) 07291 #define USB_USBTRC0_SYNC_DET_SHIFT (1U) 07292 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) 07293 #define USB_USBTRC0_USBRESMEN_MASK (0x20U) 07294 #define USB_USBTRC0_USBRESMEN_SHIFT (5U) 07295 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) 07296 #define USB_USBTRC0_USBRESET_MASK (0x80U) 07297 #define USB_USBTRC0_USBRESET_SHIFT (7U) 07298 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) 07299 07300 /*! @name USBFRMADJUST - Frame Adjust Register */ 07301 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU) 07302 #define USB_USBFRMADJUST_ADJ_SHIFT (0U) 07303 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) 07304 07305 07306 /*! 07307 * @} 07308 */ /* end of group USB_Register_Masks */ 07309 07310 07311 /* USB - Peripheral instance base addresses */ 07312 /** Peripheral USB0 base address */ 07313 #define USB0_BASE (0x40072000u) 07314 /** Peripheral USB0 base pointer */ 07315 #define USB0 ((USB_Type *)USB0_BASE) 07316 /** Array initializer of USB peripheral base addresses */ 07317 #define USB_BASE_ADDRS { USB0_BASE } 07318 /** Array initializer of USB peripheral base pointers */ 07319 #define USB_BASE_PTRS { USB0 } 07320 /** Interrupt vectors for the USB peripheral type */ 07321 #define USB_IRQS { USB0_IRQn } 07322 07323 /*! 07324 * @} 07325 */ /* end of group USB_Peripheral_Access_Layer */ 07326 07327 07328 /* ---------------------------------------------------------------------------- 07329 -- USBDCD Peripheral Access Layer 07330 ---------------------------------------------------------------------------- */ 07331 07332 /*! 07333 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer 07334 * @{ 07335 */ 07336 07337 /** USBDCD - Register Layout Typedef */ 07338 typedef struct { 07339 __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */ 07340 __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */ 07341 __I uint32_t STATUS; /**< Status Register, offset: 0x8 */ 07342 uint8_t RESERVED_0[4]; 07343 __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */ 07344 __IO uint32_t TIMER1; /**< , offset: 0x14 */ 07345 __IO uint32_t TIMER2; /**< , offset: 0x18 */ 07346 } USBDCD_Type; 07347 07348 /* ---------------------------------------------------------------------------- 07349 -- USBDCD Register Masks 07350 ---------------------------------------------------------------------------- */ 07351 07352 /*! 07353 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks 07354 * @{ 07355 */ 07356 07357 /*! @name CONTROL - Control Register */ 07358 #define USBDCD_CONTROL_IACK_MASK (0x1U) 07359 #define USBDCD_CONTROL_IACK_SHIFT (0U) 07360 #define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK) 07361 #define USBDCD_CONTROL_IF_MASK (0x100U) 07362 #define USBDCD_CONTROL_IF_SHIFT (8U) 07363 #define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK) 07364 #define USBDCD_CONTROL_IE_MASK (0x10000U) 07365 #define USBDCD_CONTROL_IE_SHIFT (16U) 07366 #define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK) 07367 #define USBDCD_CONTROL_START_MASK (0x1000000U) 07368 #define USBDCD_CONTROL_START_SHIFT (24U) 07369 #define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK) 07370 #define USBDCD_CONTROL_SR_MASK (0x2000000U) 07371 #define USBDCD_CONTROL_SR_SHIFT (25U) 07372 #define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK) 07373 07374 /*! @name CLOCK - Clock Register */ 07375 #define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) 07376 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) 07377 #define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK) 07378 #define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) 07379 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) 07380 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK) 07381 07382 /*! @name STATUS - Status Register */ 07383 #define USBDCD_STATUS_SEQ_RES_MASK (0x30000U) 07384 #define USBDCD_STATUS_SEQ_RES_SHIFT (16U) 07385 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK) 07386 #define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U) 07387 #define USBDCD_STATUS_SEQ_STAT_SHIFT (18U) 07388 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK) 07389 #define USBDCD_STATUS_ERR_MASK (0x100000U) 07390 #define USBDCD_STATUS_ERR_SHIFT (20U) 07391 #define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK) 07392 #define USBDCD_STATUS_TO_MASK (0x200000U) 07393 #define USBDCD_STATUS_TO_SHIFT (21U) 07394 #define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK) 07395 #define USBDCD_STATUS_ACTIVE_MASK (0x400000U) 07396 #define USBDCD_STATUS_ACTIVE_SHIFT (22U) 07397 #define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK) 07398 07399 /*! @name TIMER0 - TIMER0 Register */ 07400 #define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU) 07401 #define USBDCD_TIMER0_TUNITCON_SHIFT (0U) 07402 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK) 07403 #define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) 07404 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U) 07405 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK) 07406 07407 /*! @name TIMER1 - */ 07408 #define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) 07409 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) 07410 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK) 07411 #define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) 07412 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U) 07413 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK) 07414 07415 /*! @name TIMER2 - */ 07416 #define USBDCD_TIMER2_CHECK_DM_MASK (0xFU) 07417 #define USBDCD_TIMER2_CHECK_DM_SHIFT (0U) 07418 #define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_CHECK_DM_SHIFT)) & USBDCD_TIMER2_CHECK_DM_MASK) 07419 #define USBDCD_TIMER2_TVDPSRC_CON_MASK (0x3FF0000U) 07420 #define USBDCD_TIMER2_TVDPSRC_CON_SHIFT (16U) 07421 #define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_TVDPSRC_CON_MASK) 07422 07423 07424 /*! 07425 * @} 07426 */ /* end of group USBDCD_Register_Masks */ 07427 07428 07429 /* USBDCD - Peripheral instance base addresses */ 07430 /** Peripheral USBDCD base address */ 07431 #define USBDCD_BASE (0x40035000u) 07432 /** Peripheral USBDCD base pointer */ 07433 #define USBDCD ((USBDCD_Type *)USBDCD_BASE) 07434 /** Array initializer of USBDCD peripheral base addresses */ 07435 #define USBDCD_BASE_ADDRS { USBDCD_BASE } 07436 /** Array initializer of USBDCD peripheral base pointers */ 07437 #define USBDCD_BASE_PTRS { USBDCD } 07438 /** Interrupt vectors for the USBDCD peripheral type */ 07439 #define USBDCD_IRQS { USBDCD_IRQn } 07440 07441 /*! 07442 * @} 07443 */ /* end of group USBDCD_Peripheral_Access_Layer */ 07444 07445 07446 /* ---------------------------------------------------------------------------- 07447 -- VREF Peripheral Access Layer 07448 ---------------------------------------------------------------------------- */ 07449 07450 /*! 07451 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer 07452 * @{ 07453 */ 07454 07455 /** VREF - Register Layout Typedef */ 07456 typedef struct { 07457 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ 07458 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ 07459 } VREF_Type; 07460 07461 /* ---------------------------------------------------------------------------- 07462 -- VREF Register Masks 07463 ---------------------------------------------------------------------------- */ 07464 07465 /*! 07466 * @addtogroup VREF_Register_Masks VREF Register Masks 07467 * @{ 07468 */ 07469 07470 /*! @name TRM - VREF Trim Register */ 07471 #define VREF_TRM_TRIM_MASK (0x3FU) 07472 #define VREF_TRM_TRIM_SHIFT (0U) 07473 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK) 07474 #define VREF_TRM_CHOPEN_MASK (0x40U) 07475 #define VREF_TRM_CHOPEN_SHIFT (6U) 07476 #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK) 07477 07478 /*! @name SC - VREF Status and Control Register */ 07479 #define VREF_SC_MODE_LV_MASK (0x3U) 07480 #define VREF_SC_MODE_LV_SHIFT (0U) 07481 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK) 07482 #define VREF_SC_VREFST_MASK (0x4U) 07483 #define VREF_SC_VREFST_SHIFT (2U) 07484 #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK) 07485 #define VREF_SC_REGEN_MASK (0x40U) 07486 #define VREF_SC_REGEN_SHIFT (6U) 07487 #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK) 07488 #define VREF_SC_VREFEN_MASK (0x80U) 07489 #define VREF_SC_VREFEN_SHIFT (7U) 07490 #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK) 07491 07492 07493 /*! 07494 * @} 07495 */ /* end of group VREF_Register_Masks */ 07496 07497 07498 /* VREF - Peripheral instance base addresses */ 07499 /** Peripheral VREF base address */ 07500 #define VREF_BASE (0x40074000u) 07501 /** Peripheral VREF base pointer */ 07502 #define VREF ((VREF_Type *)VREF_BASE) 07503 /** Array initializer of VREF peripheral base addresses */ 07504 #define VREF_BASE_ADDRS { VREF_BASE } 07505 /** Array initializer of VREF peripheral base pointers */ 07506 #define VREF_BASE_PTRS { VREF } 07507 07508 /*! 07509 * @} 07510 */ /* end of group VREF_Peripheral_Access_Layer */ 07511 07512 07513 /* ---------------------------------------------------------------------------- 07514 -- WDOG Peripheral Access Layer 07515 ---------------------------------------------------------------------------- */ 07516 07517 /*! 07518 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer 07519 * @{ 07520 */ 07521 07522 /** WDOG - Register Layout Typedef */ 07523 typedef struct { 07524 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */ 07525 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */ 07526 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */ 07527 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */ 07528 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */ 07529 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */ 07530 __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */ 07531 __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */ 07532 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */ 07533 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */ 07534 __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */ 07535 __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */ 07536 } WDOG_Type; 07537 07538 /* ---------------------------------------------------------------------------- 07539 -- WDOG Register Masks 07540 ---------------------------------------------------------------------------- */ 07541 07542 /*! 07543 * @addtogroup WDOG_Register_Masks WDOG Register Masks 07544 * @{ 07545 */ 07546 07547 /*! @name STCTRLH - Watchdog Status and Control Register High */ 07548 #define WDOG_STCTRLH_WDOGEN_MASK (0x1U) 07549 #define WDOG_STCTRLH_WDOGEN_SHIFT (0U) 07550 #define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK) 07551 #define WDOG_STCTRLH_CLKSRC_MASK (0x2U) 07552 #define WDOG_STCTRLH_CLKSRC_SHIFT (1U) 07553 #define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK) 07554 #define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U) 07555 #define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U) 07556 #define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK) 07557 #define WDOG_STCTRLH_WINEN_MASK (0x8U) 07558 #define WDOG_STCTRLH_WINEN_SHIFT (3U) 07559 #define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK) 07560 #define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U) 07561 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U) 07562 #define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK) 07563 #define WDOG_STCTRLH_DBGEN_MASK (0x20U) 07564 #define WDOG_STCTRLH_DBGEN_SHIFT (5U) 07565 #define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK) 07566 #define WDOG_STCTRLH_STOPEN_MASK (0x40U) 07567 #define WDOG_STCTRLH_STOPEN_SHIFT (6U) 07568 #define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK) 07569 #define WDOG_STCTRLH_WAITEN_MASK (0x80U) 07570 #define WDOG_STCTRLH_WAITEN_SHIFT (7U) 07571 #define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK) 07572 #define WDOG_STCTRLH_TESTWDOG_MASK (0x400U) 07573 #define WDOG_STCTRLH_TESTWDOG_SHIFT (10U) 07574 #define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK) 07575 #define WDOG_STCTRLH_TESTSEL_MASK (0x800U) 07576 #define WDOG_STCTRLH_TESTSEL_SHIFT (11U) 07577 #define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK) 07578 #define WDOG_STCTRLH_BYTESEL_MASK (0x3000U) 07579 #define WDOG_STCTRLH_BYTESEL_SHIFT (12U) 07580 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK) 07581 #define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U) 07582 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U) 07583 #define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK) 07584 07585 /*! @name STCTRLL - Watchdog Status and Control Register Low */ 07586 #define WDOG_STCTRLL_INTFLG_MASK (0x8000U) 07587 #define WDOG_STCTRLL_INTFLG_SHIFT (15U) 07588 #define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK) 07589 07590 /*! @name TOVALH - Watchdog Time-out Value Register High */ 07591 #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU) 07592 #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U) 07593 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK) 07594 07595 /*! @name TOVALL - Watchdog Time-out Value Register Low */ 07596 #define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU) 07597 #define WDOG_TOVALL_TOVALLOW_SHIFT (0U) 07598 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK) 07599 07600 /*! @name WINH - Watchdog Window Register High */ 07601 #define WDOG_WINH_WINHIGH_MASK (0xFFFFU) 07602 #define WDOG_WINH_WINHIGH_SHIFT (0U) 07603 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK) 07604 07605 /*! @name WINL - Watchdog Window Register Low */ 07606 #define WDOG_WINL_WINLOW_MASK (0xFFFFU) 07607 #define WDOG_WINL_WINLOW_SHIFT (0U) 07608 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK) 07609 07610 /*! @name REFRESH - Watchdog Refresh Register */ 07611 #define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU) 07612 #define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U) 07613 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK) 07614 07615 /*! @name UNLOCK - Watchdog Unlock Register */ 07616 #define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU) 07617 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U) 07618 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK) 07619 07620 /*! @name TMROUTH - Watchdog Timer Output Register High */ 07621 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU) 07622 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U) 07623 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK) 07624 07625 /*! @name TMROUTL - Watchdog Timer Output Register Low */ 07626 #define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU) 07627 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U) 07628 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK) 07629 07630 /*! @name RSTCNT - Watchdog Reset Count Register */ 07631 #define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU) 07632 #define WDOG_RSTCNT_RSTCNT_SHIFT (0U) 07633 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK) 07634 07635 /*! @name PRESC - Watchdog Prescaler Register */ 07636 #define WDOG_PRESC_PRESCVAL_MASK (0x700U) 07637 #define WDOG_PRESC_PRESCVAL_SHIFT (8U) 07638 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK) 07639 07640 07641 /*! 07642 * @} 07643 */ /* end of group WDOG_Register_Masks */ 07644 07645 07646 /* WDOG - Peripheral instance base addresses */ 07647 /** Peripheral WDOG base address */ 07648 #define WDOG_BASE (0x40052000u) 07649 /** Peripheral WDOG base pointer */ 07650 #define WDOG ((WDOG_Type *)WDOG_BASE) 07651 /** Array initializer of WDOG peripheral base addresses */ 07652 #define WDOG_BASE_ADDRS { WDOG_BASE } 07653 /** Array initializer of WDOG peripheral base pointers */ 07654 #define WDOG_BASE_PTRS { WDOG } 07655 /** Interrupt vectors for the WDOG peripheral type */ 07656 #define WDOG_IRQS { Watchdog_IRQn } 07657 07658 /*! 07659 * @} 07660 */ /* end of group WDOG_Peripheral_Access_Layer */ 07661 07662 07663 /* 07664 ** End of section using anonymous unions 07665 */ 07666 07667 #if defined(__ARMCC_VERSION) 07668 #pragma pop 07669 #elif defined(__CWCC__) 07670 #pragma pop 07671 #elif defined(__GNUC__) 07672 /* leave anonymous unions enabled */ 07673 #elif defined(__IAR_SYSTEMS_ICC__) 07674 #pragma language=default 07675 #else 07676 #error Not supported compiler type 07677 #endif 07678 07679 /*! 07680 * @} 07681 */ /* end of group Peripheral_access_layer */ 07682 07683 07684 /* ---------------------------------------------------------------------------- 07685 -- SDK Compatibility 07686 ---------------------------------------------------------------------------- */ 07687 07688 /*! 07689 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 07690 * @{ 07691 */ 07692 07693 #define PDB_CHC1_REG(base,index) PDB_C1_REG(base,index) 07694 #define PDB_CHDLY0_REG(base,index) PDB_DLY_REG(base,index,0) 07695 #define PDB_CHDLY1_REG(base,index) PDB_DLY_REG(base,index,1) 07696 #define PDB_CHC1_EN_MASK PDB_C1_EN_MASK 07697 #define PDB_CHC1_EN_SHIFT PDB_C1_EN_SHIFT 07698 #define PDB_CHC1_EN(x) PDB_C1_EN(x) 07699 #define PDB_CHC1_TOS_MASK PDB_C1_TOS_MASK 07700 #define PDB_CHC1_TOS_SHIFT PDB_C1_TOS_SHIFT 07701 #define PDB_CHC1_TOS(x) PDB_C1_TOS(x) 07702 #define PDB_CHC1_BB_MASK PDB_C1_BB_MASK 07703 #define PDB_CHC1_BB_SHIFT PDB_C1_BB_SHIFT 07704 #define PDB_CHC1_BB(x) PDB_C1_BB(x) 07705 #define PDB_CHDLY0_DLY_MASK PDB_DLY_DLY_MASK 07706 #define PDB_CHDLY0_DLY_SHIFT PDB_DLY_DLY_SHIFT 07707 #define PDB_CHDLY0_DLY(x) PDB_DLY_DLY(x) 07708 #define PDB_CHDLY1_DLY_MASK PDB_DLY_DLY_MASK 07709 #define PDB_CHDLY1_DLY_SHIFT PDB_DLY_DLY_SHIFT 07710 #define PDB_CHDLY1_DLY(x) PDB_DLY_DLY(x) 07711 #define PDB0_CHC1(index) PDB0_C1(index) 07712 #define PDB0_CHDLY0(index) PDB0_DLY(index,0) 07713 #define PDB0_CHDLY1(index) PDB0_DLY(index,1) 07714 #define GPIOA_BASE PTA_BASE 07715 #define GPIOA PTA 07716 #define GPIOB_BASE PTB_BASE 07717 #define GPIOB PTB 07718 #define GPIOC_BASE PTC_BASE 07719 #define GPIOC PTC 07720 #define GPIOD_BASE PTD_BASE 07721 #define GPIOD PTD 07722 #define GPIOE_BASE PTE_BASE 07723 #define GPIOE PTE 07724 #define DMAMUX0 DMAMUX 07725 07726 /*! 07727 * @} 07728 */ /* end of group SDK_Compatibility_Symbols */ 07729 07730 07731 #endif /* _MK20D5_H_ */ 07732
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