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LLWU_Type Struct Reference
[LLWU Peripheral Access Layer]
LLWU - Register Layout Typedef. More...
#include <MK20D5.h>
Data Fields | |
| __IO uint8_t | PE1 |
| LLWU Pin Enable 1 Register, offset: 0x0. | |
| __IO uint8_t | PE2 |
| LLWU Pin Enable 2 Register, offset: 0x1. | |
| __IO uint8_t | PE3 |
| LLWU Pin Enable 3 Register, offset: 0x2. | |
| __IO uint8_t | PE4 |
| LLWU Pin Enable 4 Register, offset: 0x3. | |
| __IO uint8_t | ME |
| LLWU Module Enable Register, offset: 0x4. | |
| __IO uint8_t | F1 |
| LLWU Flag 1 Register, offset: 0x5. | |
| __IO uint8_t | F2 |
| LLWU Flag 2 Register, offset: 0x6. | |
| __I uint8_t | F3 |
| LLWU Flag 3 Register, offset: 0x7. | |
| __IO uint8_t | FILT1 |
| LLWU Pin Filter 1 Register, offset: 0x8. | |
| __IO uint8_t | FILT2 |
| LLWU Pin Filter 2 Register, offset: 0x9. | |
| __IO uint8_t | RST |
| LLWU Reset Enable Register, offset: 0xA. | |
| __IO uint8_t | PE5 |
| LLWU Pin Enable 5 register, offset: 0x4. | |
| __IO uint8_t | PE6 |
| LLWU Pin Enable 6 register, offset: 0x5. | |
| __IO uint8_t | PE7 |
| LLWU Pin Enable 7 register, offset: 0x6. | |
| __IO uint8_t | PE8 |
| LLWU Pin Enable 8 register, offset: 0x7. | |
| __IO uint8_t | PF1 |
| LLWU Pin Flag 1 register, offset: 0x9. | |
| __IO uint8_t | PF2 |
| LLWU Pin Flag 2 register, offset: 0xA. | |
| __IO uint8_t | PF3 |
| LLWU Pin Flag 3 register, offset: 0xB. | |
| __IO uint8_t | PF4 |
| LLWU Pin Flag 4 register, offset: 0xC. | |
| __I uint8_t | MF5 |
| LLWU Module Flag 5 register, offset: 0xD. | |
| __IO uint8_t | FILT3 |
| LLWU Pin Filter 3 register, offset: 0x10. | |
| __IO uint8_t | FILT4 |
| LLWU Pin Filter 4 register, offset: 0x11. | |
Detailed Description
LLWU - Register Layout Typedef.
Definition at line 3541 of file MK20D5.h.
Field Documentation
| __IO uint8_t FILT3 |
| __IO uint8_t FILT4 |
| __I uint8_t MF5 |
| __IO uint8_t PE1 |
| __IO uint8_t PE5 |
| __IO uint8_t PE6 |
| __IO uint8_t PE7 |
| __IO uint8_t PE8 |
Generated on Tue Jul 12 2022 15:37:37 by
1.7.2