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SIM_Type Struct Reference
[SIM Peripheral Access Layer]
SIM - Register Layout Typedef. More...
#include <MK20D5.h>
Data Fields | |
| __IO uint32_t | SOPT1 |
| System Options Register 1, offset: 0x0. | |
| __IO uint32_t | SOPT1CFG |
| SOPT1 Configuration Register, offset: 0x4. | |
| __IO uint32_t | SOPT2 |
| System Options Register 2, offset: 0x1004. | |
| __IO uint32_t | SOPT4 |
| System Options Register 4, offset: 0x100C. | |
| __IO uint32_t | SOPT5 |
| System Options Register 5, offset: 0x1010. | |
| __IO uint32_t | SOPT7 |
| System Options Register 7, offset: 0x1018. | |
| __I uint32_t | SDID |
| System Device Identification Register, offset: 0x1024. | |
| __IO uint32_t | SCGC4 |
| System Clock Gating Control Register 4, offset: 0x1034. | |
| __IO uint32_t | SCGC5 |
| System Clock Gating Control Register 5, offset: 0x1038. | |
| __IO uint32_t | SCGC6 |
| System Clock Gating Control Register 6, offset: 0x103C. | |
| __IO uint32_t | SCGC7 |
| System Clock Gating Control Register 7, offset: 0x1040. | |
| __IO uint32_t | CLKDIV1 |
| System Clock Divider Register 1, offset: 0x1044. | |
| __IO uint32_t | CLKDIV2 |
| System Clock Divider Register 2, offset: 0x1048. | |
| __IO uint32_t | FCFG1 |
| Flash Configuration Register 1, offset: 0x104C. | |
| __I uint32_t | FCFG2 |
| Flash Configuration Register 2, offset: 0x1050. | |
| __I uint32_t | UIDH |
| Unique Identification Register High, offset: 0x1054. | |
| __I uint32_t | UIDMH |
| Unique Identification Register Mid-High, offset: 0x1058. | |
| __I uint32_t | UIDML |
| Unique Identification Register Mid Low, offset: 0x105C. | |
| __I uint32_t | UIDL |
| Unique Identification Register Low, offset: 0x1060. | |
| __IO uint32_t | USBPHYCTL |
| USB PHY Control Register, offset: 0x8. | |
| __IO uint32_t | SOPT8 |
| System Options Register 8, offset: 0x101C. | |
| __IO uint32_t | SOPT9 |
| System Options Register 9, offset: 0x1020. | |
| __IO uint32_t | SCGC1 |
| System Clock Gating Control Register 1, offset: 0x1028. | |
| __IO uint32_t | SCGC2 |
| System Clock Gating Control Register 2, offset: 0x102C. | |
| __IO uint32_t | SCGC3 |
| System Clock Gating Control Register 3, offset: 0x1030. | |
| __IO uint32_t | CLKDIV3 |
| System Clock Divider Register 3, offset: 0x1064. | |
| __IO uint32_t | CLKDIV4 |
| System Clock Divider Register 4, offset: 0x1068. | |
| __IO uint32_t | COPC |
| COP Control Register, offset: 0x1100. | |
| __O uint32_t | SRVCOP |
| Service COP, offset: 0x1104. | |
Detailed Description
SIM - Register Layout Typedef.
Definition at line 5260 of file MK20D5.h.
Field Documentation
| __IO uint32_t CLKDIV3 |
| __IO uint32_t CLKDIV4 |
| __IO uint32_t SCGC1 |
| __IO uint32_t SCGC2 |
| __IO uint32_t SCGC3 |
| __IO uint32_t SOPT1 |
| __IO uint32_t SOPT8 |
| __IO uint32_t SOPT9 |
Generated on Tue Jul 12 2022 15:37:38 by
1.7.2