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VREF Peripheral Access Layer
Data Structures | Modules | Enumerator | Variables

VREF Peripheral Access Layer
[USBDCD Peripheral Access Layer, Device Peripheral Access Layer]

Data Structures

struct  VREF_Type
 VREF - Register Layout Typedef. More...

Modules

 VREF Register Masks
 WDOG Peripheral Access Layer
 SDK Compatibility

Variables

__IO uint32_t CFG1
 ADC configuration register 1, offset: 0x8.
__IO uint32_t CFG2
 Configuration register 2, offset: 0xC.
__I uint32_t R [2]
 ADC data result register, array offset: 0x10, array step: 0x4.
__IO uint32_t CV1
 Compare value registers, offset: 0x18.
__IO uint32_t CV2
 Compare value registers, offset: 0x1C.
__IO uint32_t SC2
 Status and control register 2, offset: 0x20.
__IO uint32_t SC3
 Status and control register 3, offset: 0x24.
__IO uint32_t OFS
 ADC offset correction register, offset: 0x28.
__IO uint32_t PG
 ADC plus-side gain register, offset: 0x2C.
__IO uint32_t MG
 ADC minus-side gain register, offset: 0x30.
__IO uint32_t CLPD
 ADC plus-side general calibration value register, offset: 0x34.
__IO uint32_t CLPS
 ADC plus-side general calibration value register, offset: 0x38.
__IO uint32_t CLP4
 ADC plus-side general calibration value register, offset: 0x3C.
__IO uint32_t CLP3
 ADC plus-side general calibration value register, offset: 0x40.
__IO uint32_t CLP2
 ADC plus-side general calibration value register, offset: 0x44.
__IO uint32_t CLP1
 ADC plus-side general calibration value register, offset: 0x48.
__IO uint32_t CLP0
 ADC plus-side general calibration value register, offset: 0x4C.
__IO uint32_t CLMD
 ADC minus-side general calibration value register, offset: 0x54.
__IO uint32_t CLMS
 ADC minus-side general calibration value register, offset: 0x58.
__IO uint32_t CLM4
 ADC minus-side general calibration value register, offset: 0x5C.
__IO uint32_t CLM3
 ADC minus-side general calibration value register, offset: 0x60.
__IO uint32_t CLM2
 ADC minus-side general calibration value register, offset: 0x64.
__IO uint32_t CLM1
 ADC minus-side general calibration value register, offset: 0x68.
__IO uint32_t CLM0
 ADC minus-side general calibration value register, offset: 0x6C.
__IO uint8_t CR1
 CMP Control Register 1, offset: 0x1.
__IO uint8_t FPR
 CMP Filter Period Register, offset: 0x2.
__IO uint8_t SCR
 CMP Status and Control Register, offset: 0x3.
__IO uint8_t DACCR
 DAC Control Register, offset: 0x4.
__IO uint8_t MUXCR
 MUX Control Register, offset: 0x5.
__IO uint8_t CGL1
 CMT Carrier Generator Low Data Register 1, offset: 0x1.
__IO uint8_t CGH2
 CMT Carrier Generator High Data Register 2, offset: 0x2.
__IO uint8_t CGL2
 CMT Carrier Generator Low Data Register 2, offset: 0x3.
__IO uint8_t OC
 CMT Output Control Register, offset: 0x4.
__IO uint8_t MSC
 CMT Modulator Status and Control Register, offset: 0x5.
__IO uint8_t CMD1
 CMT Modulator Data Register Mark High, offset: 0x6.
__IO uint8_t CMD2
 CMT Modulator Data Register Mark Low, offset: 0x7.
__IO uint8_t CMD3
 CMT Modulator Data Register Space High, offset: 0x8.
__IO uint8_t CMD4
 CMT Modulator Data Register Space Low, offset: 0x9.
__IO uint8_t PPS
 CMT Primary Prescaler Register, offset: 0xA.
__IO uint8_t DMA
 CMT Direct Memory Access, offset: 0xB.
__IO uint16_t   CRCH
 CRC_CRCH register., offset: 0x2.
__IO uint32_t   CRC
 CRC Data Register, offset: 0x0.
__IO uint8_t   CRCLU
 CRC_CRCLU register., offset: 0x1.
__IO uint8_t   CRCHL
 CRC_CRCHL register., offset: 0x2.
__IO uint8_t   CRCHU
 CRC_CRCHU register., offset: 0x3.
__IO uint16_t   GPOLYH
 CRC_GPOLYH register., offset: 0x6.
__IO uint32_t   GPOLY
 CRC Polynomial Register, offset: 0x4.
__IO uint8_t   GPOLYLU
 CRC_GPOLYLU register., offset: 0x5.
__IO uint8_t   GPOLYHL
 CRC_GPOLYHL register., offset: 0x6.
__IO uint8_t   GPOLYHU
 CRC_GPOLYHU register., offset: 0x7.
__IO uint8_t   CTRLHU
 CRC_CTRLHU register., offset: 0xB.
__I uint32_t ES
 Error Status Register, offset: 0x4.
__IO uint32_t ERQ
 Enable Request Register, offset: 0xC.
__IO uint32_t EEI
 Enable Error Interrupt Register, offset: 0x14.
__O uint8_t CEEI
 Clear Enable Error Interrupt Register, offset: 0x18.
__O uint8_t SEEI
 Set Enable Error Interrupt Register, offset: 0x19.
__O uint8_t CERQ
 Clear Enable Request Register, offset: 0x1A.
__O uint8_t SERQ
 Set Enable Request Register, offset: 0x1B.
__O uint8_t CDNE
 Clear DONE Status Bit Register, offset: 0x1C.
__O uint8_t SSRT
 Set START Bit Register, offset: 0x1D.
__O uint8_t CERR
 Clear Error Register, offset: 0x1E.
__O uint8_t CINT
 Clear Interrupt Request Register, offset: 0x1F.
__IO uint32_t INT
 Interrupt Request Register, offset: 0x24.
__IO uint32_t ERR
 Error Register, offset: 0x2C.
__IO uint32_t HRS
 Hardware Request Status Register, offset: 0x34.
__IO uint8_t DCHPRI3
 Channel n Priority Register, offset: 0x100.
__IO uint8_t DCHPRI2
 Channel n Priority Register, offset: 0x101.
__IO uint8_t DCHPRI1
 Channel n Priority Register, offset: 0x102.
__IO uint8_t DCHPRI0
 Channel n Priority Register, offset: 0x103.
__IO uint16_t   SOFF
 TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20.
__IO uint16_t   ATTR
 TCD Transfer Attributes, array offset: 0x1006, array step: 0x20.
__IO uint32_t   NBYTES_MLOFFNO
 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20.
__IO uint32_t   NBYTES_MLOFFYES
 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20.
__IO uint32_t   SLAST
 TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20.
__IO uint32_t   DADDR
 TCD Destination Address, array offset: 0x1010, array step: 0x20.
__IO uint16_t   DOFF
 TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20.
__IO uint16_t   CITER_ELINKYES
 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20.
__IO uint32_t   DLAST_SGA
 TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20.
__IO uint16_t   CSR
 TCD Control and Status, array offset: 0x101C, array step: 0x20.
__IO uint16_t   BITER_ELINKYES
 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20.
__O uint8_t SERV
 Service Register, offset: 0x1.
__IO uint8_t CMPL
 Compare Low Register, offset: 0x2.
__IO uint8_t CMPH
 Compare High Register, offset: 0x3.
__IO uint32_t PFB0CR
 Flash Control Register, offset: 0x4.
__IO uint8_t FCNFG
 Flash Configuration Register, offset: 0x1.
__I uint8_t FSEC
 Flash Security Register, offset: 0x2.
__I uint8_t FOPT
 Flash Option Register, offset: 0x3.
__IO uint8_t FCCOB3
 Flash Common Command Object Registers, offset: 0x4.
__IO uint8_t FCCOB2
 Flash Common Command Object Registers, offset: 0x5.
__IO uint8_t FCCOB1
 Flash Common Command Object Registers, offset: 0x6.
__IO uint8_t FCCOB0
 Flash Common Command Object Registers, offset: 0x7.
__IO uint8_t FCCOB7
 Flash Common Command Object Registers, offset: 0x8.
__IO uint8_t FCCOB6
 Flash Common Command Object Registers, offset: 0x9.
__IO uint8_t FCCOB5
 Flash Common Command Object Registers, offset: 0xA.
__IO uint8_t FCCOB4
 Flash Common Command Object Registers, offset: 0xB.
__IO uint8_t FCCOBB
 Flash Common Command Object Registers, offset: 0xC.
__IO uint8_t FCCOBA
 Flash Common Command Object Registers, offset: 0xD.
__IO uint8_t FCCOB9
 Flash Common Command Object Registers, offset: 0xE.
__IO uint8_t FCCOB8
 Flash Common Command Object Registers, offset: 0xF.
__IO uint8_t FPROT3
 Program Flash Protection Registers, offset: 0x10.
__IO uint8_t FPROT2
 Program Flash Protection Registers, offset: 0x11.
__IO uint8_t FPROT1
 Program Flash Protection Registers, offset: 0x12.
__IO uint8_t FPROT0
 Program Flash Protection Registers, offset: 0x13.
__IO uint8_t FEPROT
 EEPROM Protection Register, offset: 0x16.
__IO uint8_t FDPROT
 Data Flash Protection Register, offset: 0x17.
__IO uint32_t CNT
 Counter, offset: 0x4.
__IO uint32_t MOD
 Modulo, offset: 0x8.
__IO uint32_t   CnV
 Channel (n) Value, array offset: 0x10, array step: 0x8.
__IO uint32_t CNTIN
 Counter Initial Value, offset: 0x4C.
__IO uint32_t STATUS
 Capture and Compare Status, offset: 0x50.
__IO uint32_t MODE
 Features Mode Selection, offset: 0x54.
__IO uint32_t SYNC
 Synchronization, offset: 0x58.
__IO uint32_t OUTINIT
 Initial State for Channels Output, offset: 0x5C.
__IO uint32_t OUTMASK
 Output Mask, offset: 0x60.
__IO uint32_t COMBINE
 Function for Linked Channels, offset: 0x64.
__IO uint32_t DEADTIME
 Deadtime Insertion Control, offset: 0x68.
__IO uint32_t EXTTRIG
 FTM External Trigger, offset: 0x6C.
__IO uint32_t POL
 Channels Polarity, offset: 0x70.
__IO uint32_t FMS
 Fault Mode Status, offset: 0x74.
__IO uint32_t FILTER
 Input Capture Filter Control, offset: 0x78.
__IO uint32_t FLTCTRL
 Fault Control, offset: 0x7C.
__IO uint32_t QDCTRL
 Quadrature Decoder Control and Status, offset: 0x80.
__IO uint32_t CONF
 Configuration, offset: 0x84.
__IO uint32_t FLTPOL
 FTM Fault Input Polarity, offset: 0x88.
__IO uint32_t SYNCONF
 Synchronization Configuration, offset: 0x8C.
__IO uint32_t INVCTRL
 FTM Inverting Control, offset: 0x90.
__IO uint32_t SWOCTRL
 FTM Software Output Control, offset: 0x94.
__IO uint32_t PWMLOAD
 FTM PWM Load, offset: 0x98.
__O uint32_t PSOR
 Port Set Output Register, offset: 0x4.
__O uint32_t PCOR
 Port Clear Output Register, offset: 0x8.
__O uint32_t PTOR
 Port Toggle Output Register, offset: 0xC.
__I uint32_t PDIR
 Port Data Input Register, offset: 0x10.
__IO uint32_t PDDR
 Port Data Direction Register, offset: 0x14.
__IO uint8_t F
 I2C Frequency Divider register, offset: 0x1.
__IO uint8_t C1
 I2C Control Register 1, offset: 0x2.
__IO uint8_t S
 I2C Status Register, offset: 0x3.
__IO uint8_t D
 I2C Data I/O register, offset: 0x4.
__IO uint8_t C2
 I2C Control Register 2, offset: 0x5.
__IO uint8_t FLT
 I2C Programmable Input Glitch Filter register, offset: 0x6.
__IO uint8_t RA
 I2C Range Address register, offset: 0x7.
__IO uint8_t SMB
 I2C SMBus Control and Status register, offset: 0x8.
__IO uint8_t A2
 I2C Address Register 2, offset: 0x9.
__IO uint8_t SLTH
 I2C SCL Low Timeout Register High, offset: 0xA.
__IO uint8_t SLTL
 I2C SCL Low Timeout Register Low, offset: 0xB.
__IO uint32_t TCR1
 SAI Transmit Configuration 1 Register, offset: 0x4.
__IO uint32_t TCR2
 SAI Transmit Configuration 2 Register, offset: 0x8.
__IO uint32_t TCR3
 SAI Transmit Configuration 3 Register, offset: 0xC.
__IO uint32_t TCR4
 SAI Transmit Configuration 4 Register, offset: 0x10.
__IO uint32_t TCR5
 SAI Transmit Configuration 5 Register, offset: 0x14.
__O uint32_t TDR [2]
 SAI Transmit Data Register, array offset: 0x20, array step: 0x4.
__I uint32_t TFR [2]
 SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4.
__IO uint32_t TMR
 SAI Transmit Mask Register, offset: 0x60.
__IO uint32_t RCSR
 SAI Receive Control Register, offset: 0x80.
__IO uint32_t RCR1
 SAI Receive Configuration 1 Register, offset: 0x84.
__IO uint32_t RCR2
 SAI Receive Configuration 2 Register, offset: 0x88.
__IO uint32_t RCR3
 SAI Receive Configuration 3 Register, offset: 0x8C.
__IO uint32_t RCR4
 SAI Receive Configuration 4 Register, offset: 0x90.
__IO uint32_t RCR5
 SAI Receive Configuration 5 Register, offset: 0x94.
__I uint32_t RDR [2]
 SAI Receive Data Register, array offset: 0xA0, array step: 0x4.
__I uint32_t RFR [2]
 SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4.
__IO uint32_t RMR
 SAI Receive Mask Register, offset: 0xE0.
__IO uint32_t MCR
 SAI MCLK Control Register, offset: 0x100.
__IO uint32_t MDR
 MCLK Divide Register, offset: 0x104.
__IO uint8_t PE2
 LLWU Pin Enable 2 Register, offset: 0x1.
__IO uint8_t PE3
 LLWU Pin Enable 3 Register, offset: 0x2.
__IO uint8_t PE4
 LLWU Pin Enable 4 Register, offset: 0x3.
__IO uint8_t ME
 LLWU Module Enable Register, offset: 0x4.
__IO uint8_t F1
 LLWU Flag 1 Register, offset: 0x5.
__IO uint8_t F2
 LLWU Flag 2 Register, offset: 0x6.
__I uint8_t F3
 LLWU Flag 3 Register, offset: 0x7.
__IO uint8_t FILT1
 LLWU Pin Filter 1 Register, offset: 0x8.
__IO uint8_t FILT2
 LLWU Pin Filter 2 Register, offset: 0x9.
__IO uint8_t RST
 LLWU Reset Enable Register, offset: 0xA.
__IO uint32_t PSR
 Low Power Timer Prescale Register, offset: 0x4.
__IO uint32_t CMR
 Low Power Timer Compare Register, offset: 0x8.
__IO uint32_t CNR
 Low Power Timer Counter Register, offset: 0xC.
__IO uint8_t C2
 MCG Control 2 Register, offset: 0x1.
__IO uint8_t C3
 MCG Control 3 Register, offset: 0x2.
__IO uint8_t C4
 MCG Control 4 Register, offset: 0x3.
__IO uint8_t C5
 MCG Control 5 Register, offset: 0x4.
__IO uint8_t C6
 MCG Control 6 Register, offset: 0x5.
__IO uint8_t S
 MCG Status Register, offset: 0x6.
__IO uint8_t SC
 MCG Status and Control Register, offset: 0x8.
__IO uint8_t ATCVH
 MCG Auto Trim Compare Value High Register, offset: 0xA.
__IO uint8_t ATCVL
 MCG Auto Trim Compare Value Low Register, offset: 0xB.
__IO uint8_t C7
 MCG Control 7 Register, offset: 0xC.
__IO uint8_t C8
 MCG Control 8 Register, offset: 0xD.
__I uint8_t BACKKEY2
 Backdoor Comparison Key 2., offset: 0x1.
__I uint8_t BACKKEY1
 Backdoor Comparison Key 1., offset: 0x2.
__I uint8_t BACKKEY0
 Backdoor Comparison Key 0., offset: 0x3.
__I uint8_t BACKKEY7
 Backdoor Comparison Key 7., offset: 0x4.
__I uint8_t BACKKEY6
 Backdoor Comparison Key 6., offset: 0x5.
__I uint8_t BACKKEY5
 Backdoor Comparison Key 5., offset: 0x6.
__I uint8_t BACKKEY4
 Backdoor Comparison Key 4., offset: 0x7.
__I uint8_t FPROT3
 Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8.
__I uint8_t FPROT2
 Non-volatile P-Flash Protection 1 - High Register, offset: 0x9.
__I uint8_t FPROT1
 Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA.
__I uint8_t FPROT0
 Non-volatile P-Flash Protection 0 - High Register, offset: 0xB.
__I uint8_t FSEC
 Non-volatile Flash Security Register, offset: 0xC.
__I uint8_t FOPT
 Non-volatile Flash Option Register, offset: 0xD.
__I uint8_t FEPROT
 Non-volatile EERAM Protection Register, offset: 0xE.
__I uint8_t FDPROT
 Non-volatile D-Flash Protection Register, offset: 0xF.
__IO uint32_t MOD
 Modulus Register, offset: 0x4.
__I uint32_t CNT
 Counter Register, offset: 0x8.
__IO uint32_t IDLY
 Interrupt Delay Register, offset: 0xC.
__IO uint32_t   S
 Channel n Status Register, array offset: 0x14, array step: 0x10.
__IO uint32_t   DLY [2]
 Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4.
__IO uint32_t POEN
 Pulse-Out n Enable Register, offset: 0x190.
__IO uint32_t PODLY [2]
 Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4.
__I uint32_t   CVAL
 Current Timer Value Register, array offset: 0x104, array step: 0x10.
__IO uint32_t   TCTRL
 Timer Control Register, array offset: 0x108, array step: 0x10.
__IO uint32_t   TFLG
 Timer Flag Register, array offset: 0x10C, array step: 0x10.
__IO uint8_t LVDSC2
 Low Voltage Detect Status and Control 2 Register, offset: 0x1.
__IO uint8_t REGSC
 Regulator Status and Control Register, offset: 0x2.
__O uint32_t GPCLR
 Global Pin Control Low Register, offset: 0x80.
__O uint32_t GPCHR
 Global Pin Control High Register, offset: 0x84.
__IO uint32_t ISFR
 Interrupt Status Flag Register, offset: 0xA0.
__IO uint32_t DFER
 Digital Filter Enable Register, offset: 0xC0.
__IO uint32_t DFCR
 Digital Filter Clock Register, offset: 0xC4.
__IO uint32_t DFWR
 Digital Filter Width Register, offset: 0xC8.
__I uint8_t SRS1
 System Reset Status Register 1, offset: 0x1.
__IO uint8_t RPFC
 Reset Pin Filter Control Register, offset: 0x4.
__IO uint8_t RPFW
 Reset Pin Filter Width Register, offset: 0x5.
__I uint8_t MR
 Mode Register, offset: 0x7.
__IO uint32_t TPR
 RTC Time Prescaler Register, offset: 0x4.
__IO uint32_t TAR
 RTC Time Alarm Register, offset: 0x8.
__IO uint32_t TCR
 RTC Time Compensation Register, offset: 0xC.
__IO uint32_t CR
 RTC Control Register, offset: 0x10.
__IO uint32_t SR
 RTC Status Register, offset: 0x14.
__IO uint32_t LR
 RTC Lock Register, offset: 0x18.
__IO uint32_t IER
 RTC Interrupt Enable Register, offset: 0x1C.
__IO uint32_t WAR
 RTC Write Access Register, offset: 0x800.
__IO uint32_t RAR
 RTC Read Access Register, offset: 0x804.
__IO uint32_t SOPT1CFG
 SOPT1 Configuration Register, offset: 0x4.
__IO uint32_t SOPT2
 System Options Register 2, offset: 0x1004.
__IO uint32_t SOPT4
 System Options Register 4, offset: 0x100C.
__IO uint32_t SOPT5
 System Options Register 5, offset: 0x1010.
__IO uint32_t SOPT7
 System Options Register 7, offset: 0x1018.
__I uint32_t SDID
 System Device Identification Register, offset: 0x1024.
__IO uint32_t SCGC4
 System Clock Gating Control Register 4, offset: 0x1034.
__IO uint32_t SCGC5
 System Clock Gating Control Register 5, offset: 0x1038.
__IO uint32_t SCGC6
 System Clock Gating Control Register 6, offset: 0x103C.
__IO uint32_t SCGC7
 System Clock Gating Control Register 7, offset: 0x1040.
__IO uint32_t CLKDIV1
 System Clock Divider Register 1, offset: 0x1044.
__IO uint32_t CLKDIV2
 System Clock Divider Register 2, offset: 0x1048.
__IO uint32_t FCFG1
 Flash Configuration Register 1, offset: 0x104C.
__I uint32_t FCFG2
 Flash Configuration Register 2, offset: 0x1050.
__I uint32_t UIDH
 Unique Identification Register High, offset: 0x1054.
__I uint32_t UIDMH
 Unique Identification Register Mid-High, offset: 0x1058.
__I uint32_t UIDML
 Unique Identification Register Mid Low, offset: 0x105C.
__I uint32_t UIDL
 Unique Identification Register Low, offset: 0x1060.
__IO uint8_t PMCTRL
 Power Mode Control Register, offset: 0x1.
__IO uint8_t VLLSCTRL
 VLLS Control Register, offset: 0x2.
__I uint8_t PMSTAT
 Power Mode Status Register, offset: 0x3.
__IO uint32_t TCR
 DSPI Transfer Count Register, offset: 0x8.
__IO uint32_t   CTAR_SLAVE [1]
 DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4.
__IO uint32_t SR
 DSPI Status Register, offset: 0x2C.
__IO uint32_t RSER
 DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30.
__IO uint32_t   PUSHR_SLAVE
 DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34.
__I uint32_t POPR
 DSPI POP RX FIFO Register, offset: 0x38.
__I uint32_t TXFR0
 DSPI Transmit FIFO Registers, offset: 0x3C.
__I uint32_t TXFR1
 DSPI Transmit FIFO Registers, offset: 0x40.
__I uint32_t TXFR2
 DSPI Transmit FIFO Registers, offset: 0x44.
__I uint32_t TXFR3
 DSPI Transmit FIFO Registers, offset: 0x48.
__I uint32_t RXFR0
 DSPI Receive FIFO Registers, offset: 0x7C.
__I uint32_t RXFR1
 DSPI Receive FIFO Registers, offset: 0x80.
__I uint32_t RXFR2
 DSPI Receive FIFO Registers, offset: 0x84.
__I uint32_t RXFR3
 DSPI Receive FIFO Registers, offset: 0x88.
__IO uint32_t SCANC
 SCAN Control Register, offset: 0x4.
__IO uint32_t PEN
 Pin Enable Register, offset: 0x8.
__I uint32_t WUCNTR
 Wake-Up Channel Counter Register, offset: 0xC.
__I uint32_t CNTR1
 Counter Register, offset: 0x100.
__I uint32_t CNTR3
 Counter Register, offset: 0x104.
__I uint32_t CNTR5
 Counter Register, offset: 0x108.
__I uint32_t CNTR7
 Counter Register, offset: 0x10C.
__I uint32_t CNTR9
 Counter Register, offset: 0x110.
__I uint32_t CNTR11
 Counter Register, offset: 0x114.
__I uint32_t CNTR13
 Counter Register, offset: 0x118.
__I uint32_t CNTR15
 Counter Register, offset: 0x11C.
__IO uint32_t THRESHOLD
 Low Power Channel Threshold Register, offset: 0x120.
__IO uint8_t BDL
 UART Baud Rate Registers: Low, offset: 0x1.
__IO uint8_t C1
 UART Control Register 1, offset: 0x2.
__IO uint8_t C2
 UART Control Register 2, offset: 0x3.
__I uint8_t S1
 UART Status Register 1, offset: 0x4.
__IO uint8_t S2
 UART Status Register 2, offset: 0x5.
__IO uint8_t C3
 UART Control Register 3, offset: 0x6.
__IO uint8_t D
 UART Data Register, offset: 0x7.
__IO uint8_t MA1
 UART Match Address Registers 1, offset: 0x8.
__IO uint8_t MA2
 UART Match Address Registers 2, offset: 0x9.
__IO uint8_t C4
 UART Control Register 4, offset: 0xA.
__IO uint8_t C5
 UART Control Register 5, offset: 0xB.
__I uint8_t ED
 UART Extended Data Register, offset: 0xC.
__IO uint8_t MODEM
 UART Modem Register, offset: 0xD.
__IO uint8_t IR
 UART Infrared Register, offset: 0xE.
__IO uint8_t PFIFO
 UART FIFO Parameters, offset: 0x10.
__IO uint8_t CFIFO
 UART FIFO Control Register, offset: 0x11.
__IO uint8_t SFIFO
 UART FIFO Status Register, offset: 0x12.
__IO uint8_t TWFIFO
 UART FIFO Transmit Watermark, offset: 0x13.
__I uint8_t TCFIFO
 UART FIFO Transmit Count, offset: 0x14.
__IO uint8_t RWFIFO
 UART FIFO Receive Watermark, offset: 0x15.
__I uint8_t RCFIFO
 UART FIFO Receive Count, offset: 0x16.
__IO uint8_t C7816
 UART 7816 Control Register, offset: 0x18.
__IO uint8_t IE7816
 UART 7816 Interrupt Enable Register, offset: 0x19.
__IO uint8_t IS7816
 UART 7816 Interrupt Status Register, offset: 0x1A.
__IO uint8_t   WP7816T1
 UART 7816 Wait Parameter Register, offset: 0x1B.
__IO uint8_t WN7816
 UART 7816 Wait N Register, offset: 0x1C.
__IO uint8_t WF7816
 UART 7816 Wait FD Register, offset: 0x1D.
__IO uint8_t ET7816
 UART 7816 Error Threshold Register, offset: 0x1E.
__IO uint8_t TL7816
 UART 7816 Transmit Length Register, offset: 0x1F.
__IO uint8_t C6
 UART CEA709.1-B Control Register 6, offset: 0x21.
__IO uint8_t PCTH
 UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22.
__IO uint8_t PCTL
 UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23.
__IO uint8_t B1T
 UART CEA709.1-B Beta1 Timer, offset: 0x24.
__IO uint8_t SDTH
 UART CEA709.1-B Secondary Delay Timer High, offset: 0x25.
__IO uint8_t SDTL
 UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26.
__IO uint8_t PRE
 UART CEA709.1-B Preamble, offset: 0x27.
__IO uint8_t TPL
 UART CEA709.1-B Transmit Packet Length, offset: 0x28.
__IO uint8_t IE
 UART CEA709.1-B Interrupt Enable Register, offset: 0x29.
__IO uint8_t WB
 UART CEA709.1-B WBASE, offset: 0x2A.
__IO uint8_t S3
 UART CEA709.1-B Status Register, offset: 0x2B.
__IO uint8_t S4
 UART CEA709.1-B Status Register, offset: 0x2C.
__I uint8_t RPL
 UART CEA709.1-B Received Packet Length, offset: 0x2D.
__I uint8_t RPREL
 UART CEA709.1-B Received Preamble Length, offset: 0x2E.
__IO uint8_t CPW
 UART CEA709.1-B Collision Pulse Width, offset: 0x2F.
__IO uint8_t RIDT
 UART CEA709.1-B Receive Indeterminate Time, offset: 0x30.
__IO uint8_t TIDT
 UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31.
__I uint8_t IDCOMP
 Peripheral ID Complement Register, offset: 0x4.
__I uint8_t REV
 Peripheral Revision Register, offset: 0x8.
__I uint8_t ADDINFO
 Peripheral Additional Info Register, offset: 0xC.
__IO uint8_t OTGISTAT
 OTG Interrupt Status Register, offset: 0x10.
__IO uint8_t OTGICR
 OTG Interrupt Control Register, offset: 0x14.
__IO uint8_t OTGSTAT
 OTG Status Register, offset: 0x18.
__IO uint8_t OTGCTL
 OTG Control Register, offset: 0x1C.
__IO uint8_t ISTAT
 Interrupt Status Register, offset: 0x80.
__IO uint8_t INTEN
 Interrupt Enable Register, offset: 0x84.
__IO uint8_t ERRSTAT
 Error Interrupt Status Register, offset: 0x88.
__IO uint8_t ERREN
 Error Interrupt Enable Register, offset: 0x8C.
__I uint8_t STAT
 Status Register, offset: 0x90.
__IO uint8_t CTL
 Control Register, offset: 0x94.
__IO uint8_t ADDR
 Address Register, offset: 0x98.
__IO uint8_t BDTPAGE1
 BDT Page Register 1, offset: 0x9C.
__IO uint8_t FRMNUML
 Frame Number Register Low, offset: 0xA0.
__IO uint8_t FRMNUMH
 Frame Number Register High, offset: 0xA4.
__IO uint8_t TOKEN
 Token Register, offset: 0xA8.
__IO uint8_t SOFTHLD
 SOF Threshold Register, offset: 0xAC.
__IO uint8_t BDTPAGE2
 BDT Page Register 2, offset: 0xB0.
__IO uint8_t BDTPAGE3
 BDT Page Register 3, offset: 0xB4.
__IO uint8_t USBCTRL
 USB Control Register, offset: 0x100.
__I uint8_t OBSERVE
 USB OTG Observe Register, offset: 0x104.
__IO uint8_t CONTROL
 USB OTG Control Register, offset: 0x108.
__IO uint8_t USBTRC0
 USB Transceiver Control Register 0, offset: 0x10C.
__IO uint8_t USBFRMADJUST
 Frame Adjust Register, offset: 0x114.
__IO uint32_t CLOCK
 Clock Register, offset: 0x4.
__I uint32_t STATUS
 Status Register, offset: 0x8.
__IO uint32_t TIMER0
 TIMER0 Register, offset: 0x10.
__IO uint32_t TIMER1
 , offset: 0x14
__IO uint32_t TIMER2
 , offset: 0x18
__IO uint8_t SC
 VREF Status and Control Register, offset: 0x1.
__IO uint16_t STCTRLL
 Watchdog Status and Control Register Low, offset: 0x2.
__IO uint16_t TOVALH
 Watchdog Time-out Value Register High, offset: 0x4.
__IO uint16_t TOVALL
 Watchdog Time-out Value Register Low, offset: 0x6.
__IO uint16_t WINH
 Watchdog Window Register High, offset: 0x8.
__IO uint16_t WINL
 Watchdog Window Register Low, offset: 0xA.
__IO uint16_t REFRESH
 Watchdog Refresh Register, offset: 0xC.
__IO uint16_t UNLOCK
 Watchdog Unlock Register, offset: 0xE.
__IO uint16_t TMROUTH
 Watchdog Timer Output Register High, offset: 0x10.
__IO uint16_t TMROUTL
 Watchdog Timer Output Register Low, offset: 0x12.
__IO uint16_t RSTCNT
 Watchdog Reset Count Register, offset: 0x14.
__IO uint16_t PRESC
 Watchdog Prescaler Register, offset: 0x16.

Variable Documentation

__IO uint8_t A2 [inherited]

I2C Address Register 2, offset: 0x9.

Definition at line 2966 of file MK20D5.h.

__I uint8_t ADDINFO [inherited]

Peripheral Additional Info Register, offset: 0xC.

Peripheral Additional Info register, offset: 0xC.

Definition at line 6896 of file MK20D5.h.

__IO uint8_t ADDR [inherited]

Address Register, offset: 0x98.

Address register, offset: 0x98.

Definition at line 6918 of file MK20D5.h.

__IO uint8_t ATCVH [inherited]

MCG Auto Trim Compare Value High Register, offset: 0xA.

Definition at line 3891 of file MK20D5.h.

__IO uint8_t ATCVL [inherited]

MCG Auto Trim Compare Value Low Register, offset: 0xB.

Definition at line 3892 of file MK20D5.h.

__IO uint16_t ATTR [inherited]

TCD Transfer Attributes, array offset: 0x1006, array step: 0x20.

Definition at line 1135 of file MK20D5.h.

__IO uint16_t ATTR [inherited]

TCD Transfer Attributes, array offset: 0x1006, array step: 0x20.

Definition at line 1135 of file MK20D5.h.

__IO uint8_t B1T [inherited]

UART CEA709.1-B Beta1 Timer, offset: 0x24.

Definition at line 6305 of file MK20D5.h.

__I uint8_t BACKKEY0 [inherited]

Backdoor Comparison Key 0., offset: 0x3.

Definition at line 4112 of file MK20D5.h.

__I uint8_t BACKKEY1 [inherited]

Backdoor Comparison Key 1., offset: 0x2.

Definition at line 4111 of file MK20D5.h.

__I uint8_t BACKKEY2 [inherited]

Backdoor Comparison Key 2., offset: 0x1.

Definition at line 4110 of file MK20D5.h.

__I uint8_t BACKKEY4 [inherited]

Backdoor Comparison Key 4., offset: 0x7.

Definition at line 4116 of file MK20D5.h.

__I uint8_t BACKKEY5 [inherited]

Backdoor Comparison Key 5., offset: 0x6.

Definition at line 4115 of file MK20D5.h.

__I uint8_t BACKKEY6 [inherited]

Backdoor Comparison Key 6., offset: 0x5.

Definition at line 4114 of file MK20D5.h.

__I uint8_t BACKKEY7 [inherited]

Backdoor Comparison Key 7., offset: 0x4.

Definition at line 4113 of file MK20D5.h.

__IO uint8_t BDL [inherited]

UART Baud Rate Registers: Low, offset: 0x1.

UART Baud Rate Register: Low, offset: 0x1.

Definition at line 6267 of file MK20D5.h.

__IO uint8_t BDTPAGE1 [inherited]

BDT Page Register 1, offset: 0x9C.

BDT Page register 1, offset: 0x9C.

Definition at line 6920 of file MK20D5.h.

__IO uint8_t BDTPAGE2 [inherited]

BDT Page Register 2, offset: 0xB0.

Definition at line 6930 of file MK20D5.h.

__IO uint8_t BDTPAGE3 [inherited]

BDT Page Register 3, offset: 0xB4.

Definition at line 6932 of file MK20D5.h.

__IO uint16_t BITER_ELINKNO [inherited]

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20.

Definition at line 1151 of file MK20D5.h.

__IO uint16_t BITER_ELINKYES [inherited]

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20.

Definition at line 1152 of file MK20D5.h.

__IO uint16_t BITER_ELINKYES [inherited]

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20.

Definition at line 1152 of file MK20D5.h.

__IO uint32_t C1 [inherited]

Channel n Control Register 1, array offset: 0x10, array step: 0x10.

Definition at line 4332 of file MK20D5.h.

__IO uint8_t C1 [inherited]

UART Control Register 1, offset: 0x2.

Definition at line 6268 of file MK20D5.h.

__IO uint8_t C1 [inherited]

I2C Control Register 1, offset: 0x2.

Definition at line 2959 of file MK20D5.h.

__IO uint8_t C2 [inherited]

MCG Control 2 Register, offset: 0x1.

Definition at line 3882 of file MK20D5.h.

__IO uint8_t C2 [inherited]

UART Control Register 2, offset: 0x3.

Definition at line 6269 of file MK20D5.h.

__IO uint8_t C2 [inherited]

I2C Control Register 2, offset: 0x5.

Definition at line 2962 of file MK20D5.h.

__IO uint8_t C3 [inherited]

MCG Control 3 Register, offset: 0x2.

Definition at line 3883 of file MK20D5.h.

__IO uint8_t C3 [inherited]

UART Control Register 3, offset: 0x6.

Definition at line 6272 of file MK20D5.h.

__IO uint8_t C4 [inherited]

MCG Control 4 Register, offset: 0x3.

Definition at line 3884 of file MK20D5.h.

__IO uint8_t C4 [inherited]

UART Control Register 4, offset: 0xA.

UART Control Register 4, offset: 0x8.

Definition at line 6276 of file MK20D5.h.

__IO uint8_t C5 [inherited]

MCG Control 5 Register, offset: 0x4.

Definition at line 3885 of file MK20D5.h.

__IO uint8_t C5 [inherited]

UART Control Register 5, offset: 0xB.

Definition at line 6277 of file MK20D5.h.

__IO uint8_t C6 [inherited]

MCG Control 6 Register, offset: 0x5.

Definition at line 3886 of file MK20D5.h.

__IO uint8_t C6 [inherited]

UART CEA709.1-B Control Register 6, offset: 0x21.

Definition at line 6302 of file MK20D5.h.

__IO uint8_t C7 [inherited]

MCG Control 7 Register, offset: 0xC.

Definition at line 3893 of file MK20D5.h.

__IO uint8_t C7816 [inherited]

UART 7816 Control Register, offset: 0x18.

Definition at line 6290 of file MK20D5.h.

__IO uint8_t C8 [inherited]

MCG Control 8 Register, offset: 0xD.

Definition at line 3894 of file MK20D5.h.

__O uint8_t CDNE [inherited]

Clear DONE Status Bit Register, offset: 0x1C.

Definition at line 1116 of file MK20D5.h.

__O uint8_t CEEI [inherited]

Clear Enable Error Interrupt Register, offset: 0x18.

Definition at line 1112 of file MK20D5.h.

__O uint8_t CERQ [inherited]

Clear Enable Request Register, offset: 0x1A.

Definition at line 1114 of file MK20D5.h.

__O uint8_t CERR [inherited]

Clear Error Register, offset: 0x1E.

Definition at line 1118 of file MK20D5.h.

__IO uint32_t CFG1 [inherited]

ADC configuration register 1, offset: 0x8.

ADC Configuration Register 1, offset: 0x8.

Definition at line 382 of file MK20D5.h.

__IO uint32_t CFG2 [inherited]

Configuration register 2, offset: 0xC.

ADC Configuration Register 2, offset: 0xC.

Definition at line 383 of file MK20D5.h.

__IO uint8_t CFIFO [inherited]

UART FIFO Control Register, offset: 0x11.

Definition at line 6283 of file MK20D5.h.

__IO uint8_t CGH2 [inherited]

CMT Carrier Generator High Data Register 2, offset: 0x2.

Definition at line 775 of file MK20D5.h.

__IO uint8_t CGL1 [inherited]

CMT Carrier Generator Low Data Register 1, offset: 0x1.

Definition at line 774 of file MK20D5.h.

__IO uint8_t CGL2 [inherited]

CMT Carrier Generator Low Data Register 2, offset: 0x3.

Definition at line 776 of file MK20D5.h.

__O uint8_t CINT [inherited]

Clear Interrupt Request Register, offset: 0x1F.

Definition at line 1119 of file MK20D5.h.

__IO uint16_t CITER_ELINKNO [inherited]

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20.

Definition at line 1145 of file MK20D5.h.

__IO uint16_t CITER_ELINKYES [inherited]

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20.

Definition at line 1146 of file MK20D5.h.

__IO uint16_t CITER_ELINKYES [inherited]

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20.

Definition at line 1146 of file MK20D5.h.

__IO uint32_t CLKDIV1 [inherited]

System Clock Divider Register 1, offset: 0x1044.

Definition at line 5277 of file MK20D5.h.

__IO uint32_t CLKDIV2 [inherited]

System Clock Divider Register 2, offset: 0x1048.

Definition at line 5278 of file MK20D5.h.

__IO uint32_t CLM0 [inherited]

ADC minus-side general calibration value register, offset: 0x6C.

ADC Minus-Side General Calibration Value Register, offset: 0x6C.

Definition at line 406 of file MK20D5.h.

__IO uint32_t CLM1 [inherited]

ADC minus-side general calibration value register, offset: 0x68.

ADC Minus-Side General Calibration Value Register, offset: 0x68.

Definition at line 405 of file MK20D5.h.

__IO uint32_t CLM2 [inherited]

ADC minus-side general calibration value register, offset: 0x64.

ADC Minus-Side General Calibration Value Register, offset: 0x64.

Definition at line 404 of file MK20D5.h.

__IO uint32_t CLM3 [inherited]

ADC minus-side general calibration value register, offset: 0x60.

ADC Minus-Side General Calibration Value Register, offset: 0x60.

Definition at line 403 of file MK20D5.h.

__IO uint32_t CLM4 [inherited]

ADC minus-side general calibration value register, offset: 0x5C.

ADC Minus-Side General Calibration Value Register, offset: 0x5C.

Definition at line 402 of file MK20D5.h.

__IO uint32_t CLMD [inherited]

ADC minus-side general calibration value register, offset: 0x54.

ADC Minus-Side General Calibration Value Register, offset: 0x54.

Definition at line 400 of file MK20D5.h.

__IO uint32_t CLMS [inherited]

ADC minus-side general calibration value register, offset: 0x58.

ADC Minus-Side General Calibration Value Register, offset: 0x58.

Definition at line 401 of file MK20D5.h.

__IO uint32_t CLOCK [inherited]

Clock Register, offset: 0x4.

Clock register, offset: 0x4.

Definition at line 7340 of file MK20D5.h.

__IO uint32_t CLP0 [inherited]

ADC plus-side general calibration value register, offset: 0x4C.

ADC Plus-Side General Calibration Value Register, offset: 0x4C.

Definition at line 398 of file MK20D5.h.

__IO uint32_t CLP1 [inherited]

ADC plus-side general calibration value register, offset: 0x48.

ADC Plus-Side General Calibration Value Register, offset: 0x48.

Definition at line 397 of file MK20D5.h.

__IO uint32_t CLP2 [inherited]

ADC plus-side general calibration value register, offset: 0x44.

ADC Plus-Side General Calibration Value Register, offset: 0x44.

Definition at line 396 of file MK20D5.h.

__IO uint32_t CLP3 [inherited]

ADC plus-side general calibration value register, offset: 0x40.

ADC Plus-Side General Calibration Value Register, offset: 0x40.

Definition at line 395 of file MK20D5.h.

__IO uint32_t CLP4 [inherited]

ADC plus-side general calibration value register, offset: 0x3C.

ADC Plus-Side General Calibration Value Register, offset: 0x3C.

Definition at line 394 of file MK20D5.h.

__IO uint32_t CLPD [inherited]

ADC plus-side general calibration value register, offset: 0x34.

ADC Plus-Side General Calibration Value Register, offset: 0x34.

Definition at line 392 of file MK20D5.h.

__IO uint32_t CLPS [inherited]

ADC plus-side general calibration value register, offset: 0x38.

ADC Plus-Side General Calibration Value Register, offset: 0x38.

Definition at line 393 of file MK20D5.h.

__IO uint8_t CMD1 [inherited]

CMT Modulator Data Register Mark High, offset: 0x6.

Definition at line 779 of file MK20D5.h.

__IO uint8_t CMD2 [inherited]

CMT Modulator Data Register Mark Low, offset: 0x7.

Definition at line 780 of file MK20D5.h.

__IO uint8_t CMD3 [inherited]

CMT Modulator Data Register Space High, offset: 0x8.

Definition at line 781 of file MK20D5.h.

__IO uint8_t CMD4 [inherited]

CMT Modulator Data Register Space Low, offset: 0x9.

Definition at line 782 of file MK20D5.h.

__IO uint8_t CMPH [inherited]

Compare High Register, offset: 0x3.

Definition at line 1717 of file MK20D5.h.

__IO uint8_t CMPL [inherited]

Compare Low Register, offset: 0x2.

Definition at line 1716 of file MK20D5.h.

__IO uint32_t CMR [inherited]

Low Power Timer Compare Register, offset: 0x8.

Definition at line 3790 of file MK20D5.h.

__IO uint32_t CNR [inherited]

Low Power Timer Counter Register, offset: 0xC.

Definition at line 3791 of file MK20D5.h.

__IO uint32_t CnSC [inherited]

Channel (n) Status and Control, array offset: 0xC, array step: 0x8.

Definition at line 2191 of file MK20D5.h.

__I uint32_t CNT [inherited]

Counter Register, offset: 0x8.

Counter register, offset: 0x8.

Definition at line 4329 of file MK20D5.h.

__IO uint32_t CNT [inherited]

Counter, offset: 0x4.

Definition at line 2188 of file MK20D5.h.

__IO uint32_t CNTIN [inherited]

Counter Initial Value, offset: 0x4C.

Definition at line 2194 of file MK20D5.h.

__I uint32_t CNTR1 [inherited]

Counter Register, offset: 0x100.

Definition at line 6015 of file MK20D5.h.

__I uint32_t CNTR11 [inherited]

Counter Register, offset: 0x114.

Definition at line 6020 of file MK20D5.h.

__I uint32_t CNTR13 [inherited]

Counter Register, offset: 0x118.

Definition at line 6021 of file MK20D5.h.

__I uint32_t CNTR15 [inherited]

Counter Register, offset: 0x11C.

Definition at line 6022 of file MK20D5.h.

__I uint32_t CNTR3 [inherited]

Counter Register, offset: 0x104.

Definition at line 6016 of file MK20D5.h.

__I uint32_t CNTR5 [inherited]

Counter Register, offset: 0x108.

Definition at line 6017 of file MK20D5.h.

__I uint32_t CNTR7 [inherited]

Counter Register, offset: 0x10C.

Definition at line 6018 of file MK20D5.h.

__I uint32_t CNTR9 [inherited]

Counter Register, offset: 0x110.

Definition at line 6019 of file MK20D5.h.

__IO uint32_t CnV [inherited]

Channel (n) Value, array offset: 0x10, array step: 0x8.

Definition at line 2192 of file MK20D5.h.

__IO uint32_t CnV [inherited]

Channel (n) Value, array offset: 0x10, array step: 0x8.

Definition at line 2192 of file MK20D5.h.

__IO uint32_t COMBINE [inherited]

Function for Linked Channels, offset: 0x64.

Function For Linked Channels, offset: 0x64.

Definition at line 2200 of file MK20D5.h.

__IO uint32_t CONF [inherited]

Configuration, offset: 0x84.

Definition at line 2208 of file MK20D5.h.

__IO uint8_t CONTROL [inherited]

USB OTG Control Register, offset: 0x108.

USB OTG Control register, offset: 0x108.

Definition at line 6942 of file MK20D5.h.

__IO uint8_t CPW [inherited]

UART CEA709.1-B Collision Pulse Width, offset: 0x2F.

Definition at line 6316 of file MK20D5.h.

__IO uint32_t CR [inherited]

RTC Control Register, offset: 0x10.

Definition at line 5053 of file MK20D5.h.

__IO uint8_t CR1 [inherited]

CMP Control Register 1, offset: 0x1.

Definition at line 644 of file MK20D5.h.

__IO uint32_t CRC [inherited]

CRC Data Register, offset: 0x0.

Definition at line 919 of file MK20D5.h.

__IO uint32_t CRC [inherited]

CRC Data Register, offset: 0x0.

Definition at line 919 of file MK20D5.h.

__IO uint16_t CRCH [inherited]

CRC_CRCH register., offset: 0x2.

Definition at line 917 of file MK20D5.h.

__IO uint16_t CRCH [inherited]

CRC_CRCH register., offset: 0x2.

Definition at line 917 of file MK20D5.h.

__IO uint8_t CRCHL [inherited]

CRC_CRCHL register., offset: 0x2.

Definition at line 923 of file MK20D5.h.

__IO uint8_t CRCHL [inherited]

CRC_CRCHL register., offset: 0x2.

Definition at line 923 of file MK20D5.h.

__IO uint8_t CRCHU [inherited]

CRC_CRCHU register., offset: 0x3.

Definition at line 924 of file MK20D5.h.

__IO uint8_t CRCHU [inherited]

CRC_CRCHU register., offset: 0x3.

Definition at line 924 of file MK20D5.h.

__IO uint8_t CRCLL [inherited]

CRC_CRCLL register., offset: 0x0.

Definition at line 921 of file MK20D5.h.

__IO uint8_t CRCLU [inherited]

CRC_CRCLU register., offset: 0x1.

Definition at line 922 of file MK20D5.h.

__IO uint8_t CRCLU [inherited]

CRC_CRCLU register., offset: 0x1.

Definition at line 922 of file MK20D5.h.

__IO uint16_t CSR [inherited]

TCD Control and Status, array offset: 0x101C, array step: 0x20.

Definition at line 1149 of file MK20D5.h.

__IO uint16_t CSR [inherited]

TCD Control and Status, array offset: 0x101C, array step: 0x20.

Definition at line 1149 of file MK20D5.h.

__IO uint32_t CTAR[2] [inherited]

DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4.

Definition at line 5689 of file MK20D5.h.

__IO uint32_t CTAR_SLAVE[1] [inherited]

DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4.

Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4.

Definition at line 5690 of file MK20D5.h.

__IO uint32_t CTAR_SLAVE[1] [inherited]

DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4.

Definition at line 5690 of file MK20D5.h.

__IO uint8_t CTL [inherited]

Control Register, offset: 0x94.

Control register, offset: 0x94.

Definition at line 6916 of file MK20D5.h.

__IO uint32_t CTRL [inherited]

CRC Control Register, offset: 0x8.

Definition at line 941 of file MK20D5.h.

__IO uint8_t CTRLHU [inherited]

CRC_CTRLHU register., offset: 0xB.

Definition at line 944 of file MK20D5.h.

__IO uint8_t CTRLHU [inherited]

CRC_CTRLHU register., offset: 0xB.

Definition at line 944 of file MK20D5.h.

__IO uint32_t CV1 [inherited]

Compare value registers, offset: 0x18.

Compare Value Registers, offset: 0x18.

Definition at line 385 of file MK20D5.h.

__IO uint32_t CV2 [inherited]

Compare value registers, offset: 0x1C.

Compare Value Registers, offset: 0x1C.

Definition at line 386 of file MK20D5.h.

__I uint32_t CVAL [inherited]

Current Timer Value Register, array offset: 0x104, array step: 0x10.

Definition at line 4493 of file MK20D5.h.

__I uint32_t CVAL [inherited]

Current Timer Value Register, array offset: 0x104, array step: 0x10.

Definition at line 4493 of file MK20D5.h.

__IO uint8_t D [inherited]

UART Data Register, offset: 0x7.

Definition at line 6273 of file MK20D5.h.

__IO uint8_t D [inherited]

I2C Data I/O register, offset: 0x4.

Definition at line 2961 of file MK20D5.h.

__IO uint8_t DACCR [inherited]

DAC Control Register, offset: 0x4.

Definition at line 647 of file MK20D5.h.

__IO uint32_t DADDR [inherited]

TCD Destination Address, array offset: 0x1010, array step: 0x20.

Definition at line 1142 of file MK20D5.h.

__IO uint32_t DADDR [inherited]

TCD Destination Address, array offset: 0x1010, array step: 0x20.

Definition at line 1142 of file MK20D5.h.

__IO uint32_t DATAW0S [inherited]

Cache Data Storage, array offset: 0x204, array step: 0x8.

Definition at line 1801 of file MK20D5.h.

__IO uint32_t DATAW1S [inherited]

Cache Data Storage, array offset: 0x244, array step: 0x8.

Definition at line 1806 of file MK20D5.h.

__IO uint32_t DATAW2S [inherited]

Cache Data Storage, array offset: 0x284, array step: 0x8.

Definition at line 1811 of file MK20D5.h.

__IO uint32_t DATAW3S [inherited]

Cache Data Storage, array offset: 0x2C4, array step: 0x8.

Definition at line 1816 of file MK20D5.h.

__IO uint8_t DCHPRI0 [inherited]

Channel n Priority Register, offset: 0x103.

Definition at line 1130 of file MK20D5.h.

__IO uint8_t DCHPRI1 [inherited]

Channel n Priority Register, offset: 0x102.

Definition at line 1129 of file MK20D5.h.

__IO uint8_t DCHPRI2 [inherited]

Channel n Priority Register, offset: 0x101.

Definition at line 1128 of file MK20D5.h.

__IO uint8_t DCHPRI3 [inherited]

Channel n Priority Register, offset: 0x100.

Definition at line 1127 of file MK20D5.h.

__IO uint32_t DEADTIME [inherited]

Deadtime Insertion Control, offset: 0x68.

Definition at line 2201 of file MK20D5.h.

__IO uint32_t DFCR [inherited]

Digital Filter Clock Register, offset: 0xC4.

Definition at line 4682 of file MK20D5.h.

__IO uint32_t DFER [inherited]

Digital Filter Enable Register, offset: 0xC0.

Definition at line 4681 of file MK20D5.h.

__IO uint32_t DFWR [inherited]

Digital Filter Width Register, offset: 0xC8.

Definition at line 4683 of file MK20D5.h.

__IO uint32_t DLAST_SGA [inherited]

TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20.

Definition at line 1148 of file MK20D5.h.

__IO uint32_t DLAST_SGA [inherited]

TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20.

Definition at line 1148 of file MK20D5.h.

__IO uint32_t DLY[2] [inherited]

Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4.

Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4.

Definition at line 4334 of file MK20D5.h.

__IO uint32_t DLY[2] [inherited]

Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4.

Definition at line 4334 of file MK20D5.h.

__IO uint8_t DMA [inherited]

CMT Direct Memory Access, offset: 0xB.

CMT Direct Memory Access Register, offset: 0xB.

Definition at line 784 of file MK20D5.h.

__IO uint16_t DOFF [inherited]

TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20.

Definition at line 1143 of file MK20D5.h.

__IO uint16_t DOFF [inherited]

TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20.

Definition at line 1143 of file MK20D5.h.

__I uint8_t ED [inherited]

UART Extended Data Register, offset: 0xC.

Definition at line 6278 of file MK20D5.h.

__IO uint32_t EEI [inherited]

Enable Error Interrupt Register, offset: 0x14.

Definition at line 1111 of file MK20D5.h.

__IO uint8_t ENDPT [inherited]

Endpoint Control Register, array offset: 0xC0, array step: 0x4.

Definition at line 6935 of file MK20D5.h.

__IO uint32_t ERQ [inherited]

Enable Request Register, offset: 0xC.

Definition at line 1109 of file MK20D5.h.

__IO uint32_t ERR [inherited]

Error Register, offset: 0x2C.

Definition at line 1123 of file MK20D5.h.

__IO uint8_t ERREN [inherited]

Error Interrupt Enable Register, offset: 0x8C.

Error Interrupt Enable register, offset: 0x8C.

Definition at line 6912 of file MK20D5.h.

__IO uint8_t ERRSTAT [inherited]

Error Interrupt Status Register, offset: 0x88.

Error Interrupt Status register, offset: 0x88.

Definition at line 6910 of file MK20D5.h.

__I uint32_t ES [inherited]

Error Status Register, offset: 0x4.

Definition at line 1107 of file MK20D5.h.

__IO uint8_t ET7816 [inherited]

UART 7816 Error Threshold Register, offset: 0x1E.

Definition at line 6299 of file MK20D5.h.

__IO uint32_t EXTTRIG [inherited]

FTM External Trigger, offset: 0x6C.

Definition at line 2202 of file MK20D5.h.

__IO uint8_t F [inherited]

I2C Frequency Divider register, offset: 0x1.

Definition at line 2958 of file MK20D5.h.

__IO uint8_t F1 [inherited]

LLWU Flag 1 Register, offset: 0x5.

LLWU Flag 1 register, offset: 0x5.

Definition at line 3547 of file MK20D5.h.

__IO uint8_t F2 [inherited]

LLWU Flag 2 Register, offset: 0x6.

LLWU Flag 2 register, offset: 0x6.

Definition at line 3548 of file MK20D5.h.

__I uint8_t F3 [inherited]

LLWU Flag 3 Register, offset: 0x7.

LLWU Flag 3 register, offset: 0x7.

Definition at line 3549 of file MK20D5.h.

__IO uint8_t FCCOB0 [inherited]

Flash Common Command Object Registers, offset: 0x7.

Definition at line 1976 of file MK20D5.h.

__IO uint8_t FCCOB1 [inherited]

Flash Common Command Object Registers, offset: 0x6.

Definition at line 1975 of file MK20D5.h.

__IO uint8_t FCCOB2 [inherited]

Flash Common Command Object Registers, offset: 0x5.

Definition at line 1974 of file MK20D5.h.

__IO uint8_t FCCOB3 [inherited]

Flash Common Command Object Registers, offset: 0x4.

Definition at line 1973 of file MK20D5.h.

__IO uint8_t FCCOB4 [inherited]

Flash Common Command Object Registers, offset: 0xB.

Definition at line 1980 of file MK20D5.h.

__IO uint8_t FCCOB5 [inherited]

Flash Common Command Object Registers, offset: 0xA.

Definition at line 1979 of file MK20D5.h.

__IO uint8_t FCCOB6 [inherited]

Flash Common Command Object Registers, offset: 0x9.

Definition at line 1978 of file MK20D5.h.

__IO uint8_t FCCOB7 [inherited]

Flash Common Command Object Registers, offset: 0x8.

Definition at line 1977 of file MK20D5.h.

__IO uint8_t FCCOB8 [inherited]

Flash Common Command Object Registers, offset: 0xF.

Definition at line 1984 of file MK20D5.h.

__IO uint8_t FCCOB9 [inherited]

Flash Common Command Object Registers, offset: 0xE.

Definition at line 1983 of file MK20D5.h.

__IO uint8_t FCCOBA [inherited]

Flash Common Command Object Registers, offset: 0xD.

Definition at line 1982 of file MK20D5.h.

__IO uint8_t FCCOBB [inherited]

Flash Common Command Object Registers, offset: 0xC.

Definition at line 1981 of file MK20D5.h.

__IO uint32_t FCFG1 [inherited]

Flash Configuration Register 1, offset: 0x104C.

Definition at line 5279 of file MK20D5.h.

__I uint32_t FCFG2 [inherited]

Flash Configuration Register 2, offset: 0x1050.

Definition at line 5280 of file MK20D5.h.

__IO uint8_t FCNFG [inherited]

Flash Configuration Register, offset: 0x1.

Definition at line 1970 of file MK20D5.h.

__I uint8_t FDPROT [inherited]

Non-volatile D-Flash Protection Register, offset: 0xF.

Definition at line 4124 of file MK20D5.h.

__IO uint8_t FDPROT [inherited]

Data Flash Protection Register, offset: 0x17.

Definition at line 1991 of file MK20D5.h.

__I uint8_t FEPROT [inherited]

Non-volatile EERAM Protection Register, offset: 0xE.

Definition at line 4123 of file MK20D5.h.

__IO uint8_t FEPROT [inherited]

EEPROM Protection Register, offset: 0x16.

Definition at line 1990 of file MK20D5.h.

__IO uint8_t FILT1 [inherited]

LLWU Pin Filter 1 Register, offset: 0x8.

LLWU Pin Filter 1 register, offset: 0x8.

LLWU Pin Filter 1 register, offset: 0xE.

Definition at line 3550 of file MK20D5.h.

__IO uint8_t FILT2 [inherited]

LLWU Pin Filter 2 Register, offset: 0x9.

LLWU Pin Filter 2 register, offset: 0x9.

LLWU Pin Filter 2 register, offset: 0xF.

Definition at line 3551 of file MK20D5.h.

__IO uint32_t FILTER [inherited]

Input Capture Filter Control, offset: 0x78.

Definition at line 2205 of file MK20D5.h.

__IO uint8_t FLT [inherited]

I2C Programmable Input Glitch Filter register, offset: 0x6.

I2C Programmable Input Glitch Filter Register, offset: 0x6.

Definition at line 2963 of file MK20D5.h.

__IO uint32_t FLTCTRL [inherited]

Fault Control, offset: 0x7C.

Definition at line 2206 of file MK20D5.h.

__IO uint32_t FLTPOL [inherited]

FTM Fault Input Polarity, offset: 0x88.

Definition at line 2209 of file MK20D5.h.

__IO uint32_t FMS [inherited]

Fault Mode Status, offset: 0x74.

Definition at line 2204 of file MK20D5.h.

__I uint8_t FOPT [inherited]

Non-volatile Flash Option Register, offset: 0xD.

Definition at line 4122 of file MK20D5.h.

__I uint8_t FOPT [inherited]

Flash Option Register, offset: 0x3.

Definition at line 1972 of file MK20D5.h.

__IO uint8_t FPR [inherited]

CMP Filter Period Register, offset: 0x2.

Definition at line 645 of file MK20D5.h.

__I uint8_t FPROT0 [inherited]

Non-volatile P-Flash Protection 0 - High Register, offset: 0xB.

Definition at line 4120 of file MK20D5.h.

__IO uint8_t FPROT0 [inherited]

Program Flash Protection Registers, offset: 0x13.

Definition at line 1988 of file MK20D5.h.

__I uint8_t FPROT1 [inherited]

Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA.

Definition at line 4119 of file MK20D5.h.

__IO uint8_t FPROT1 [inherited]

Program Flash Protection Registers, offset: 0x12.

Definition at line 1987 of file MK20D5.h.

__I uint8_t FPROT2 [inherited]

Non-volatile P-Flash Protection 1 - High Register, offset: 0x9.

Definition at line 4118 of file MK20D5.h.

__IO uint8_t FPROT2 [inherited]

Program Flash Protection Registers, offset: 0x11.

Definition at line 1986 of file MK20D5.h.

__I uint8_t FPROT3 [inherited]

Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8.

Definition at line 4117 of file MK20D5.h.

__IO uint8_t FPROT3 [inherited]

Program Flash Protection Registers, offset: 0x10.

Definition at line 1985 of file MK20D5.h.

__IO uint8_t FRMNUMH [inherited]

Frame Number Register High, offset: 0xA4.

Frame Number register High, offset: 0xA4.

Definition at line 6924 of file MK20D5.h.

__IO uint8_t FRMNUML [inherited]

Frame Number Register Low, offset: 0xA0.

Frame Number register Low, offset: 0xA0.

Definition at line 6922 of file MK20D5.h.

__I uint8_t FSEC [inherited]

Non-volatile Flash Security Register, offset: 0xC.

Definition at line 4121 of file MK20D5.h.

__I uint8_t FSEC [inherited]

Flash Security Register, offset: 0x2.

Definition at line 1971 of file MK20D5.h.

__O uint32_t GPCHR [inherited]

Global Pin Control High Register, offset: 0x84.

Definition at line 4677 of file MK20D5.h.

__O uint32_t GPCLR [inherited]

Global Pin Control Low Register, offset: 0x80.

Definition at line 4676 of file MK20D5.h.

__IO uint32_t GPOLY [inherited]

CRC Polynomial Register, offset: 0x4.

CRC Polynomial register, offset: 0x4.

Definition at line 932 of file MK20D5.h.

__IO uint32_t GPOLY [inherited]

CRC Polynomial Register, offset: 0x4.

Definition at line 932 of file MK20D5.h.

__IO uint16_t GPOLYH [inherited]

CRC_GPOLYH register., offset: 0x6.

Definition at line 930 of file MK20D5.h.

__IO uint16_t GPOLYH [inherited]

CRC_GPOLYH register., offset: 0x6.

Definition at line 930 of file MK20D5.h.

__IO uint8_t GPOLYHL [inherited]

CRC_GPOLYHL register., offset: 0x6.

Definition at line 936 of file MK20D5.h.

__IO uint8_t GPOLYHL [inherited]

CRC_GPOLYHL register., offset: 0x6.

Definition at line 936 of file MK20D5.h.

__IO uint8_t GPOLYHU [inherited]

CRC_GPOLYHU register., offset: 0x7.

Definition at line 937 of file MK20D5.h.

__IO uint8_t GPOLYHU [inherited]

CRC_GPOLYHU register., offset: 0x7.

Definition at line 937 of file MK20D5.h.

__IO uint16_t GPOLYL [inherited]

CRC_GPOLYL register., offset: 0x4.

Definition at line 929 of file MK20D5.h.

__IO uint8_t GPOLYLL [inherited]

CRC_GPOLYLL register., offset: 0x4.

Definition at line 934 of file MK20D5.h.

__IO uint8_t GPOLYLU [inherited]

CRC_GPOLYLU register., offset: 0x5.

Definition at line 935 of file MK20D5.h.

__IO uint8_t GPOLYLU [inherited]

CRC_GPOLYLU register., offset: 0x5.

Definition at line 935 of file MK20D5.h.

__IO uint32_t HRS [inherited]

Hardware Request Status Register, offset: 0x34.

Definition at line 1125 of file MK20D5.h.

__I uint8_t IDCOMP [inherited]

Peripheral ID Complement Register, offset: 0x4.

Peripheral ID Complement register, offset: 0x4.

Definition at line 6892 of file MK20D5.h.

__IO uint32_t IDLY [inherited]

Interrupt Delay Register, offset: 0xC.

Interrupt Delay register, offset: 0xC.

Definition at line 4330 of file MK20D5.h.

__IO uint8_t IE [inherited]

UART CEA709.1-B Interrupt Enable Register, offset: 0x29.

Definition at line 6310 of file MK20D5.h.

__IO uint8_t IE7816 [inherited]

UART 7816 Interrupt Enable Register, offset: 0x19.

Definition at line 6291 of file MK20D5.h.

__IO uint32_t IER [inherited]

RTC Interrupt Enable Register, offset: 0x1C.

Definition at line 5056 of file MK20D5.h.

__IO uint32_t INT [inherited]

Interrupt Request Register, offset: 0x24.

Definition at line 1121 of file MK20D5.h.

__IO uint8_t INTEN [inherited]

Interrupt Enable Register, offset: 0x84.

Interrupt Enable register, offset: 0x84.

Definition at line 6908 of file MK20D5.h.

__IO uint32_t INVCTRL [inherited]

FTM Inverting Control, offset: 0x90.

Definition at line 2211 of file MK20D5.h.

__IO uint8_t IR [inherited]

UART Infrared Register, offset: 0xE.

Definition at line 6280 of file MK20D5.h.

__IO uint8_t IS7816 [inherited]

UART 7816 Interrupt Status Register, offset: 0x1A.

Definition at line 6292 of file MK20D5.h.

__IO uint32_t ISFR [inherited]

Interrupt Status Flag Register, offset: 0xA0.

Definition at line 4679 of file MK20D5.h.

__IO uint8_t ISTAT [inherited]

Interrupt Status Register, offset: 0x80.

Interrupt Status register, offset: 0x80.

Definition at line 6906 of file MK20D5.h.

__IO uint32_t LDVAL [inherited]

Timer Load Value Register, array offset: 0x100, array step: 0x10.

Definition at line 4492 of file MK20D5.h.

__IO uint32_t LR [inherited]

RTC Lock Register, offset: 0x18.

Definition at line 5055 of file MK20D5.h.

__IO uint8_t LVDSC2 [inherited]

Low Voltage Detect Status and Control 2 Register, offset: 0x1.

Low Voltage Detect Status And Control 2 register, offset: 0x1.

Definition at line 4586 of file MK20D5.h.

__IO uint8_t MA1 [inherited]

UART Match Address Registers 1, offset: 0x8.

Definition at line 6274 of file MK20D5.h.

__IO uint8_t MA2 [inherited]

UART Match Address Registers 2, offset: 0x9.

Definition at line 6275 of file MK20D5.h.

__IO uint32_t MCR [inherited]

SAI MCLK Control Register, offset: 0x100.

Definition at line 3181 of file MK20D5.h.

__IO uint32_t MDR [inherited]

MCLK Divide Register, offset: 0x104.

SAI MCLK Divide Register, offset: 0x104.

Definition at line 3182 of file MK20D5.h.

__IO uint8_t ME [inherited]

LLWU Module Enable Register, offset: 0x4.

LLWU Module Enable register, offset: 0x4.

LLWU Module Enable register, offset: 0x8.

Definition at line 3546 of file MK20D5.h.

__IO uint32_t MG [inherited]

ADC minus-side gain register, offset: 0x30.

ADC Minus-Side Gain Register, offset: 0x30.

Definition at line 391 of file MK20D5.h.

__IO uint32_t MOD [inherited]

Modulus Register, offset: 0x4.

Modulus register, offset: 0x4.

Definition at line 4328 of file MK20D5.h.

__IO uint32_t MOD [inherited]

Modulo, offset: 0x8.

Definition at line 2189 of file MK20D5.h.

__IO uint32_t MODE [inherited]

Features Mode Selection, offset: 0x54.

Definition at line 2196 of file MK20D5.h.

__IO uint8_t MODEM [inherited]

UART Modem Register, offset: 0xD.

Definition at line 6279 of file MK20D5.h.

__I uint8_t MR [inherited]

Mode Register, offset: 0x7.

Definition at line 4822 of file MK20D5.h.

__IO uint8_t MSC [inherited]

CMT Modulator Status and Control Register, offset: 0x5.

Definition at line 778 of file MK20D5.h.

__IO uint8_t MUXCR [inherited]

MUX Control Register, offset: 0x5.

Definition at line 648 of file MK20D5.h.

__IO uint32_t NBYTES_MLNO [inherited]

TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20.

Definition at line 1137 of file MK20D5.h.

__IO uint32_t NBYTES_MLOFFNO [inherited]

TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20.

TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20.

Definition at line 1138 of file MK20D5.h.

__IO uint32_t NBYTES_MLOFFNO [inherited]

TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20.

Definition at line 1138 of file MK20D5.h.

__IO uint32_t NBYTES_MLOFFYES [inherited]

TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20.

TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20.

Definition at line 1139 of file MK20D5.h.

__IO uint32_t NBYTES_MLOFFYES [inherited]

TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20.

Definition at line 1139 of file MK20D5.h.

__I uint8_t OBSERVE [inherited]

USB OTG Observe Register, offset: 0x104.

USB OTG Observe register, offset: 0x104.

Definition at line 6940 of file MK20D5.h.

__IO uint8_t OC [inherited]

CMT Output Control Register, offset: 0x4.

Definition at line 777 of file MK20D5.h.

__IO uint32_t OFS [inherited]

ADC offset correction register, offset: 0x28.

ADC Offset Correction Register, offset: 0x28.

Definition at line 389 of file MK20D5.h.

__IO uint8_t OTGCTL [inherited]

OTG Control Register, offset: 0x1C.

OTG Control register, offset: 0x1C.

Definition at line 6904 of file MK20D5.h.

__IO uint8_t OTGICR [inherited]

OTG Interrupt Control Register, offset: 0x14.

OTG Interrupt Control register, offset: 0x14.

Definition at line 6900 of file MK20D5.h.

__IO uint8_t OTGISTAT [inherited]

OTG Interrupt Status Register, offset: 0x10.

OTG Interrupt Status register, offset: 0x10.

Definition at line 6898 of file MK20D5.h.

__IO uint8_t OTGSTAT [inherited]

OTG Status Register, offset: 0x18.

OTG Status register, offset: 0x18.

Definition at line 6902 of file MK20D5.h.

__IO uint32_t OUTINIT [inherited]

Initial State for Channels Output, offset: 0x5C.

Initial State For Channels Output, offset: 0x5C.

Definition at line 2198 of file MK20D5.h.

__IO uint32_t OUTMASK [inherited]

Output Mask, offset: 0x60.

Definition at line 2199 of file MK20D5.h.

__O uint32_t PCOR [inherited]

Port Clear Output Register, offset: 0x8.

Definition at line 2864 of file MK20D5.h.

__IO uint8_t PCTH [inherited]

UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22.

Definition at line 6303 of file MK20D5.h.

__IO uint8_t PCTL [inherited]

UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23.

Definition at line 6304 of file MK20D5.h.

__IO uint32_t PDDR [inherited]

Port Data Direction Register, offset: 0x14.

Definition at line 2867 of file MK20D5.h.

__I uint32_t PDIR [inherited]

Port Data Input Register, offset: 0x10.

Definition at line 2866 of file MK20D5.h.

__IO uint8_t PE2 [inherited]

LLWU Pin Enable 2 Register, offset: 0x1.

LLWU Pin Enable 2 register, offset: 0x1.

Definition at line 3543 of file MK20D5.h.

__IO uint8_t PE3 [inherited]

LLWU Pin Enable 3 Register, offset: 0x2.

LLWU Pin Enable 3 register, offset: 0x2.

Definition at line 3544 of file MK20D5.h.

__IO uint8_t PE4 [inherited]

LLWU Pin Enable 4 Register, offset: 0x3.

LLWU Pin Enable 4 register, offset: 0x3.

Definition at line 3545 of file MK20D5.h.

__IO uint32_t PEN [inherited]

Pin Enable Register, offset: 0x8.

Definition at line 6012 of file MK20D5.h.

__IO uint32_t PFB0CR [inherited]

Flash Control Register, offset: 0x4.

Definition at line 1793 of file MK20D5.h.

__IO uint8_t PFIFO [inherited]

UART FIFO Parameters, offset: 0x10.

Definition at line 6282 of file MK20D5.h.

__IO uint32_t PG [inherited]

ADC plus-side gain register, offset: 0x2C.

ADC Plus-Side Gain Register, offset: 0x2C.

Definition at line 390 of file MK20D5.h.

__IO uint8_t PMCTRL [inherited]

Power Mode Control Register, offset: 0x1.

Power Mode Control register, offset: 0x1.

Definition at line 5601 of file MK20D5.h.

__I uint8_t PMSTAT [inherited]

Power Mode Status Register, offset: 0x3.

Power Mode Status register, offset: 0x3.

Definition at line 5603 of file MK20D5.h.

__IO uint32_t PODLY [inherited]

Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4.

Pulse-Out n Delay register, array offset: 0x194, array step: 0x4.

Definition at line 4338 of file MK20D5.h.

__IO uint32_t POEN [inherited]

Pulse-Out n Enable Register, offset: 0x190.

Pulse-Out n Enable register, offset: 0x190.

Definition at line 4337 of file MK20D5.h.

__IO uint32_t POL [inherited]

Channels Polarity, offset: 0x70.

Definition at line 2203 of file MK20D5.h.

__I uint32_t POPR [inherited]

DSPI POP RX FIFO Register, offset: 0x38.

POP RX FIFO Register, offset: 0x38.

Definition at line 5699 of file MK20D5.h.

__IO uint8_t PPS [inherited]

CMT Primary Prescaler Register, offset: 0xA.

Definition at line 783 of file MK20D5.h.

__IO uint8_t PRE [inherited]

UART CEA709.1-B Preamble, offset: 0x27.

Definition at line 6308 of file MK20D5.h.

__IO uint16_t PRESC [inherited]

Watchdog Prescaler Register, offset: 0x16.

Watchdog Prescaler register, offset: 0x16.

Definition at line 7535 of file MK20D5.h.

__O uint32_t PSOR [inherited]

Port Set Output Register, offset: 0x4.

Definition at line 2863 of file MK20D5.h.

__IO uint32_t PSR [inherited]

Low Power Timer Prescale Register, offset: 0x4.

Definition at line 3789 of file MK20D5.h.

__O uint32_t PTOR [inherited]

Port Toggle Output Register, offset: 0xC.

Definition at line 2865 of file MK20D5.h.

__IO uint32_t PUSHR [inherited]

DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34.

Definition at line 5696 of file MK20D5.h.

__IO uint32_t PUSHR_SLAVE [inherited]

DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34.

PUSH TX FIFO Register In Slave Mode, offset: 0x34.

Definition at line 5697 of file MK20D5.h.

__IO uint32_t PUSHR_SLAVE [inherited]

DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34.

Definition at line 5697 of file MK20D5.h.

__IO uint32_t PWMLOAD [inherited]

FTM PWM Load, offset: 0x98.

Definition at line 2213 of file MK20D5.h.

__IO uint32_t QDCTRL [inherited]

Quadrature Decoder Control and Status, offset: 0x80.

Quadrature Decoder Control And Status, offset: 0x80.

Definition at line 2207 of file MK20D5.h.

__I uint32_t R [inherited]

ADC data result register, array offset: 0x10, array step: 0x4.

ADC Data Result Register, array offset: 0x10, array step: 0x4.

Definition at line 384 of file MK20D5.h.

__IO uint8_t RA [inherited]

I2C Range Address register, offset: 0x7.

Definition at line 2964 of file MK20D5.h.

__IO uint32_t RAR [inherited]

RTC Read Access Register, offset: 0x804.

Definition at line 5059 of file MK20D5.h.

__I uint8_t RCFIFO [inherited]

UART FIFO Receive Count, offset: 0x16.

Definition at line 6288 of file MK20D5.h.

__IO uint32_t RCR1 [inherited]

SAI Receive Configuration 1 Register, offset: 0x84.

Definition at line 3169 of file MK20D5.h.

__IO uint32_t RCR2 [inherited]

SAI Receive Configuration 2 Register, offset: 0x88.

Definition at line 3170 of file MK20D5.h.

__IO uint32_t RCR3 [inherited]

SAI Receive Configuration 3 Register, offset: 0x8C.

Definition at line 3171 of file MK20D5.h.

__IO uint32_t RCR4 [inherited]

SAI Receive Configuration 4 Register, offset: 0x90.

Definition at line 3172 of file MK20D5.h.

__IO uint32_t RCR5 [inherited]

SAI Receive Configuration 5 Register, offset: 0x94.

Definition at line 3173 of file MK20D5.h.

__IO uint32_t RCSR [inherited]

SAI Receive Control Register, offset: 0x80.

Definition at line 3168 of file MK20D5.h.

__I uint32_t RDR [inherited]

SAI Receive Data Register, array offset: 0xA0, array step: 0x4.

Definition at line 3175 of file MK20D5.h.

__IO uint16_t REFRESH [inherited]

Watchdog Refresh Register, offset: 0xC.

Watchdog Refresh register, offset: 0xC.

Definition at line 7530 of file MK20D5.h.

__IO uint8_t REGSC [inherited]

Regulator Status and Control Register, offset: 0x2.

Regulator Status And Control register, offset: 0x2.

Definition at line 4587 of file MK20D5.h.

__I uint8_t REV [inherited]

Peripheral Revision Register, offset: 0x8.

Peripheral Revision register, offset: 0x8.

Definition at line 6894 of file MK20D5.h.

__I uint32_t RFR [inherited]

SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4.

Definition at line 3177 of file MK20D5.h.

__IO uint8_t RIDT [inherited]

UART CEA709.1-B Receive Indeterminate Time, offset: 0x30.

Definition at line 6317 of file MK20D5.h.

__IO uint32_t RMR [inherited]

SAI Receive Mask Register, offset: 0xE0.

Definition at line 3179 of file MK20D5.h.

__IO uint8_t RPFC [inherited]

Reset Pin Filter Control Register, offset: 0x4.

Reset Pin Filter Control register, offset: 0x4.

Definition at line 4819 of file MK20D5.h.

__IO uint8_t RPFW [inherited]

Reset Pin Filter Width Register, offset: 0x5.

Reset Pin Filter Width register, offset: 0x5.

Definition at line 4820 of file MK20D5.h.

__I uint8_t RPL [inherited]

UART CEA709.1-B Received Packet Length, offset: 0x2D.

Definition at line 6314 of file MK20D5.h.

__I uint8_t RPREL [inherited]

UART CEA709.1-B Received Preamble Length, offset: 0x2E.

Definition at line 6315 of file MK20D5.h.

__IO uint32_t RSER [inherited]

DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30.

DMA/Interrupt Request Select and Enable Register, offset: 0x30.

Definition at line 5694 of file MK20D5.h.

__IO uint8_t RST [inherited]

LLWU Reset Enable Register, offset: 0xA.

Definition at line 3552 of file MK20D5.h.

__IO uint16_t RSTCNT [inherited]

Watchdog Reset Count Register, offset: 0x14.

Watchdog Reset Count register, offset: 0x14.

Definition at line 7534 of file MK20D5.h.

__IO uint8_t RWFIFO [inherited]

UART FIFO Receive Watermark, offset: 0x15.

Definition at line 6287 of file MK20D5.h.

__I uint32_t RXFR0 [inherited]

DSPI Receive FIFO Registers, offset: 0x7C.

Receive FIFO Registers, offset: 0x7C.

Definition at line 5705 of file MK20D5.h.

__I uint32_t RXFR1 [inherited]

DSPI Receive FIFO Registers, offset: 0x80.

Receive FIFO Registers, offset: 0x80.

Definition at line 5706 of file MK20D5.h.

__I uint32_t RXFR2 [inherited]

DSPI Receive FIFO Registers, offset: 0x84.

Receive FIFO Registers, offset: 0x84.

Definition at line 5707 of file MK20D5.h.

__I uint32_t RXFR3 [inherited]

DSPI Receive FIFO Registers, offset: 0x88.

Receive FIFO Registers, offset: 0x88.

Definition at line 5708 of file MK20D5.h.

__IO uint32_t S [inherited]

Channel n Status Register, array offset: 0x14, array step: 0x10.

Channel n Status register, array offset: 0x14, array step: 0x28.

Definition at line 4333 of file MK20D5.h.

__IO uint8_t S [inherited]

MCG Status Register, offset: 0x6.

Definition at line 3887 of file MK20D5.h.

__IO uint8_t S [inherited]

I2C Status Register, offset: 0x3.

I2C Status register, offset: 0x3.

Definition at line 2960 of file MK20D5.h.

__IO uint32_t S [inherited]

Channel n Status Register, array offset: 0x14, array step: 0x10.

Definition at line 4333 of file MK20D5.h.

__I uint8_t S1 [inherited]

UART Status Register 1, offset: 0x4.

Definition at line 6270 of file MK20D5.h.

__IO uint8_t S2 [inherited]

UART Status Register 2, offset: 0x5.

Definition at line 6271 of file MK20D5.h.

__IO uint8_t S3 [inherited]

UART CEA709.1-B Status Register, offset: 0x2B.

Definition at line 6312 of file MK20D5.h.

__IO uint8_t S4 [inherited]

UART CEA709.1-B Status Register, offset: 0x2C.

Definition at line 6313 of file MK20D5.h.

__IO uint32_t SADDR [inherited]

TCD Source Address, array offset: 0x1000, array step: 0x20.

Definition at line 1133 of file MK20D5.h.

__IO uint8_t SC [inherited]

VREF Status and Control Register, offset: 0x1.

Definition at line 7458 of file MK20D5.h.

__IO uint8_t SC [inherited]

MCG Status and Control Register, offset: 0x8.

Definition at line 3889 of file MK20D5.h.

__IO uint32_t SC2 [inherited]

Status and control register 2, offset: 0x20.

Status and Control Register 2, offset: 0x20.

Definition at line 387 of file MK20D5.h.

__IO uint32_t SC3 [inherited]

Status and control register 3, offset: 0x24.

Status and Control Register 3, offset: 0x24.

Definition at line 388 of file MK20D5.h.

__IO uint32_t SCANC [inherited]

SCAN Control Register, offset: 0x4.

Definition at line 6011 of file MK20D5.h.

__IO uint32_t SCGC4 [inherited]

System Clock Gating Control Register 4, offset: 0x1034.

Definition at line 5273 of file MK20D5.h.

__IO uint32_t SCGC5 [inherited]

System Clock Gating Control Register 5, offset: 0x1038.

Definition at line 5274 of file MK20D5.h.

__IO uint32_t SCGC6 [inherited]

System Clock Gating Control Register 6, offset: 0x103C.

Definition at line 5275 of file MK20D5.h.

__IO uint32_t SCGC7 [inherited]

System Clock Gating Control Register 7, offset: 0x1040.

Definition at line 5276 of file MK20D5.h.

__IO uint8_t SCR [inherited]

CMP Status and Control Register, offset: 0x3.

Definition at line 646 of file MK20D5.h.

__I uint32_t SDID [inherited]

System Device Identification Register, offset: 0x1024.

Definition at line 5271 of file MK20D5.h.

__IO uint8_t SDTH [inherited]

UART CEA709.1-B Secondary Delay Timer High, offset: 0x25.

Definition at line 6306 of file MK20D5.h.

__IO uint8_t SDTL [inherited]

UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26.

Definition at line 6307 of file MK20D5.h.

__O uint8_t SEEI [inherited]

Set Enable Error Interrupt Register, offset: 0x19.

Definition at line 1113 of file MK20D5.h.

__O uint8_t SERQ [inherited]

Set Enable Request Register, offset: 0x1B.

Definition at line 1115 of file MK20D5.h.

__O uint8_t SERV [inherited]

Service Register, offset: 0x1.

Definition at line 1715 of file MK20D5.h.

__IO uint8_t SFIFO [inherited]

UART FIFO Status Register, offset: 0x12.

Definition at line 6284 of file MK20D5.h.

__IO uint32_t SLAST [inherited]

TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20.

Definition at line 1141 of file MK20D5.h.

__IO uint32_t SLAST [inherited]

TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20.

Definition at line 1141 of file MK20D5.h.

__IO uint8_t SLTH [inherited]

I2C SCL Low Timeout Register High, offset: 0xA.

Definition at line 2967 of file MK20D5.h.

__IO uint8_t SLTL [inherited]

I2C SCL Low Timeout Register Low, offset: 0xB.

Definition at line 2968 of file MK20D5.h.

__IO uint8_t SMB [inherited]

I2C SMBus Control and Status register, offset: 0x8.

Definition at line 2965 of file MK20D5.h.

__IO uint16_t SOFF [inherited]

TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20.

Definition at line 1134 of file MK20D5.h.

__IO uint16_t SOFF [inherited]

TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20.

Definition at line 1134 of file MK20D5.h.

__IO uint8_t SOFTHLD [inherited]

SOF Threshold Register, offset: 0xAC.

SOF Threshold register, offset: 0xAC.

Definition at line 6928 of file MK20D5.h.

__IO uint32_t SOPT1CFG [inherited]

SOPT1 Configuration Register, offset: 0x4.

Definition at line 5262 of file MK20D5.h.

__IO uint32_t SOPT2 [inherited]

System Options Register 2, offset: 0x1004.

Definition at line 5264 of file MK20D5.h.

__IO uint32_t SOPT4 [inherited]

System Options Register 4, offset: 0x100C.

Definition at line 5266 of file MK20D5.h.

__IO uint32_t SOPT5 [inherited]

System Options Register 5, offset: 0x1010.

Definition at line 5267 of file MK20D5.h.

__IO uint32_t SOPT7 [inherited]

System Options Register 7, offset: 0x1018.

Definition at line 5269 of file MK20D5.h.

__IO uint32_t SR [inherited]

RTC Status Register, offset: 0x14.

Definition at line 5054 of file MK20D5.h.

__IO uint32_t SR [inherited]

DSPI Status Register, offset: 0x2C.

Status Register, offset: 0x2C.

Definition at line 5693 of file MK20D5.h.

__I uint8_t SRS1 [inherited]

System Reset Status Register 1, offset: 0x1.

Definition at line 4817 of file MK20D5.h.

__O uint8_t SSRT [inherited]

Set START Bit Register, offset: 0x1D.

Definition at line 1117 of file MK20D5.h.

__I uint8_t STAT [inherited]

Status Register, offset: 0x90.

Status register, offset: 0x90.

Definition at line 6914 of file MK20D5.h.

__IO uint32_t STATUS [inherited]

Capture and Compare Status, offset: 0x50.

Capture And Compare Status, offset: 0x50.

Definition at line 2195 of file MK20D5.h.

__I uint32_t STATUS [inherited]

Status Register, offset: 0x8.

Status register, offset: 0x8.

Definition at line 7341 of file MK20D5.h.

__IO uint16_t STCTRLL [inherited]

Watchdog Status and Control Register Low, offset: 0x2.

Definition at line 7525 of file MK20D5.h.

__IO uint32_t SWOCTRL [inherited]

FTM Software Output Control, offset: 0x94.

Definition at line 2212 of file MK20D5.h.

__IO uint32_t SYNC [inherited]

Synchronization, offset: 0x58.

Definition at line 2197 of file MK20D5.h.

__IO uint32_t SYNCONF [inherited]

Synchronization Configuration, offset: 0x8C.

Definition at line 2210 of file MK20D5.h.

__IO uint32_t TAGVD[2] [inherited]

Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4.

Definition at line 1796 of file MK20D5.h.

__IO uint32_t TAR [inherited]

RTC Time Alarm Register, offset: 0x8.

Definition at line 5051 of file MK20D5.h.

__I uint8_t TCFIFO [inherited]

UART FIFO Transmit Count, offset: 0x14.

Definition at line 6286 of file MK20D5.h.

__IO uint32_t TCR [inherited]

DSPI Transfer Count Register, offset: 0x8.

Transfer Count Register, offset: 0x8.

Definition at line 5687 of file MK20D5.h.

__IO uint32_t TCR [inherited]

RTC Time Compensation Register, offset: 0xC.

Definition at line 5052 of file MK20D5.h.

__IO uint32_t TCR1 [inherited]

SAI Transmit Configuration 1 Register, offset: 0x4.

Definition at line 3156 of file MK20D5.h.

__IO uint32_t TCR2 [inherited]

SAI Transmit Configuration 2 Register, offset: 0x8.

Definition at line 3157 of file MK20D5.h.

__IO uint32_t TCR3 [inherited]

SAI Transmit Configuration 3 Register, offset: 0xC.

Definition at line 3158 of file MK20D5.h.

__IO uint32_t TCR4 [inherited]

SAI Transmit Configuration 4 Register, offset: 0x10.

Definition at line 3159 of file MK20D5.h.

__IO uint32_t TCR5 [inherited]

SAI Transmit Configuration 5 Register, offset: 0x14.

Definition at line 3160 of file MK20D5.h.

__IO uint32_t TCTRL [inherited]

Timer Control Register, array offset: 0x108, array step: 0x10.

Definition at line 4494 of file MK20D5.h.

__IO uint32_t TCTRL [inherited]

Timer Control Register, array offset: 0x108, array step: 0x10.

Definition at line 4494 of file MK20D5.h.

__O uint32_t TDR [inherited]

SAI Transmit Data Register, array offset: 0x20, array step: 0x4.

Definition at line 3162 of file MK20D5.h.

__IO uint32_t TFLG [inherited]

Timer Flag Register, array offset: 0x10C, array step: 0x10.

Definition at line 4495 of file MK20D5.h.

__IO uint32_t TFLG [inherited]

Timer Flag Register, array offset: 0x10C, array step: 0x10.

Definition at line 4495 of file MK20D5.h.

__I uint32_t TFR [inherited]

SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4.

Definition at line 3164 of file MK20D5.h.

__IO uint32_t THRESHOLD [inherited]

Low Power Channel Threshold Register, offset: 0x120.

Definition at line 6023 of file MK20D5.h.

__IO uint8_t TIDT [inherited]

UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31.

Definition at line 6318 of file MK20D5.h.

__IO uint32_t TIMER0 [inherited]

TIMER0 Register, offset: 0x10.

TIMER0 register, offset: 0x10.

Definition at line 7343 of file MK20D5.h.

__IO uint32_t TIMER1 [inherited]

, offset: 0x14

TIMER1 register, offset: 0x14.

Definition at line 7344 of file MK20D5.h.

__IO uint32_t TIMER2 [inherited]

, offset: 0x18

Definition at line 7345 of file MK20D5.h.

__IO uint8_t TL7816 [inherited]

UART 7816 Transmit Length Register, offset: 0x1F.

Definition at line 6300 of file MK20D5.h.

__IO uint32_t TMR [inherited]

SAI Transmit Mask Register, offset: 0x60.

Definition at line 3166 of file MK20D5.h.

__IO uint16_t TMROUTH [inherited]

Watchdog Timer Output Register High, offset: 0x10.

Definition at line 7532 of file MK20D5.h.

__IO uint16_t TMROUTL [inherited]

Watchdog Timer Output Register Low, offset: 0x12.

Definition at line 7533 of file MK20D5.h.

__IO uint8_t TOKEN [inherited]

Token Register, offset: 0xA8.

Token register, offset: 0xA8.

Definition at line 6926 of file MK20D5.h.

__IO uint16_t TOVALH [inherited]

Watchdog Time-out Value Register High, offset: 0x4.

Definition at line 7526 of file MK20D5.h.

__IO uint16_t TOVALL [inherited]

Watchdog Time-out Value Register Low, offset: 0x6.

Definition at line 7527 of file MK20D5.h.

__IO uint8_t TPL [inherited]

UART CEA709.1-B Transmit Packet Length, offset: 0x28.

Definition at line 6309 of file MK20D5.h.

__IO uint32_t TPR [inherited]

RTC Time Prescaler Register, offset: 0x4.

Definition at line 5050 of file MK20D5.h.

__IO uint8_t TWFIFO [inherited]

UART FIFO Transmit Watermark, offset: 0x13.

Definition at line 6285 of file MK20D5.h.

__I uint32_t TXFR0 [inherited]

DSPI Transmit FIFO Registers, offset: 0x3C.

Transmit FIFO Registers, offset: 0x3C.

Definition at line 5700 of file MK20D5.h.

__I uint32_t TXFR1 [inherited]

DSPI Transmit FIFO Registers, offset: 0x40.

Transmit FIFO Registers, offset: 0x40.

Definition at line 5701 of file MK20D5.h.

__I uint32_t TXFR2 [inherited]

DSPI Transmit FIFO Registers, offset: 0x44.

Transmit FIFO Registers, offset: 0x44.

Definition at line 5702 of file MK20D5.h.

__I uint32_t TXFR3 [inherited]

DSPI Transmit FIFO Registers, offset: 0x48.

Transmit FIFO Registers, offset: 0x48.

Definition at line 5703 of file MK20D5.h.

__I uint32_t UIDH [inherited]

Unique Identification Register High, offset: 0x1054.

Definition at line 5281 of file MK20D5.h.

__I uint32_t UIDL [inherited]

Unique Identification Register Low, offset: 0x1060.

Definition at line 5284 of file MK20D5.h.

__I uint32_t UIDMH [inherited]

Unique Identification Register Mid-High, offset: 0x1058.

Definition at line 5282 of file MK20D5.h.

__I uint32_t UIDML [inherited]

Unique Identification Register Mid Low, offset: 0x105C.

Definition at line 5283 of file MK20D5.h.

__IO uint16_t UNLOCK [inherited]

Watchdog Unlock Register, offset: 0xE.

Watchdog Unlock register, offset: 0xE.

Definition at line 7531 of file MK20D5.h.

__IO uint8_t USBCTRL [inherited]

USB Control Register, offset: 0x100.

USB Control register, offset: 0x100.

Definition at line 6938 of file MK20D5.h.

__IO uint8_t USBFRMADJUST [inherited]

Frame Adjust Register, offset: 0x114.

Definition at line 6946 of file MK20D5.h.

__IO uint8_t USBTRC0 [inherited]

USB Transceiver Control Register 0, offset: 0x10C.

USB Transceiver Control register 0, offset: 0x10C.

Definition at line 6944 of file MK20D5.h.

__IO uint8_t VLLSCTRL [inherited]

VLLS Control Register, offset: 0x2.

Definition at line 5602 of file MK20D5.h.

__IO uint32_t WAR [inherited]

RTC Write Access Register, offset: 0x800.

Definition at line 5058 of file MK20D5.h.

__IO uint8_t WB [inherited]

UART CEA709.1-B WBASE, offset: 0x2A.

Definition at line 6311 of file MK20D5.h.

__IO uint8_t WF7816 [inherited]

UART 7816 Wait FD Register, offset: 0x1D.

Definition at line 6298 of file MK20D5.h.

__IO uint16_t WINH [inherited]

Watchdog Window Register High, offset: 0x8.

Definition at line 7528 of file MK20D5.h.

__IO uint16_t WINL [inherited]

Watchdog Window Register Low, offset: 0xA.

Definition at line 7529 of file MK20D5.h.

__IO uint8_t WN7816 [inherited]

UART 7816 Wait N Register, offset: 0x1C.

Definition at line 6297 of file MK20D5.h.

__IO uint8_t WP7816T0 [inherited]

UART 7816 Wait Parameter Register, offset: 0x1B.

Definition at line 6294 of file MK20D5.h.

__IO uint8_t WP7816T1 [inherited]

UART 7816 Wait Parameter Register, offset: 0x1B.

Definition at line 6295 of file MK20D5.h.

__IO uint8_t WP7816T1 [inherited]

UART 7816 Wait Parameter Register, offset: 0x1B.

Definition at line 6295 of file MK20D5.h.

__I uint32_t WUCNTR [inherited]

Wake-Up Channel Counter Register, offset: 0xC.

Definition at line 6013 of file MK20D5.h.

Generated on Tue Jul 12 2022 15:37:33 by  doxygen 1.7.2