Data Fields |
| __IO uint32_t | CR |
| | Control Register, offset: 0x0.
|
| __I uint32_t | ES |
| | Error Status Register, offset: 0x4.
|
| __IO uint32_t | ERQ |
| | Enable Request Register, offset: 0xC.
|
| __IO uint32_t | EEI |
| | Enable Error Interrupt Register, offset: 0x14.
|
| __O uint8_t | CEEI |
| | Clear Enable Error Interrupt Register, offset: 0x18.
|
| __O uint8_t | SEEI |
| | Set Enable Error Interrupt Register, offset: 0x19.
|
| __O uint8_t | CERQ |
| | Clear Enable Request Register, offset: 0x1A.
|
| __O uint8_t | SERQ |
| | Set Enable Request Register, offset: 0x1B.
|
| __O uint8_t | CDNE |
| | Clear DONE Status Bit Register, offset: 0x1C.
|
| __O uint8_t | SSRT |
| | Set START Bit Register, offset: 0x1D.
|
| __O uint8_t | CERR |
| | Clear Error Register, offset: 0x1E.
|
| __O uint8_t | CINT |
| | Clear Interrupt Request Register, offset: 0x1F.
|
| __IO uint32_t | INT |
| | Interrupt Request Register, offset: 0x24.
|
| __IO uint32_t | ERR |
| | Error Register, offset: 0x2C.
|
| __IO uint32_t | HRS |
| | Hardware Request Status Register, offset: 0x34.
|
| __IO uint8_t | DCHPRI3 |
| | Channel n Priority Register, offset: 0x100.
|
| __IO uint8_t | DCHPRI2 |
| | Channel n Priority Register, offset: 0x101.
|
| __IO uint8_t | DCHPRI1 |
| | Channel n Priority Register, offset: 0x102.
|
| __IO uint8_t | DCHPRI0 |
| | Channel n Priority Register, offset: 0x103.
|
| __I uint32_t | HRS |
| | Hardware Request Status Register, offset: 0x34.
|
| __IO uint32_t | EARS |
| | Enable Asynchronous Request in Stop Register, offset: 0x44.
|
| __IO uint8_t | DCHPRI7 |
| | Channel n Priority Register, offset: 0x104.
|
| __IO uint8_t | DCHPRI6 |
| | Channel n Priority Register, offset: 0x105.
|
| __IO uint8_t | DCHPRI5 |
| | Channel n Priority Register, offset: 0x106.
|
| __IO uint8_t | DCHPRI4 |
| | Channel n Priority Register, offset: 0x107.
|
| __IO uint8_t | DCHPRI11 |
| | Channel n Priority Register, offset: 0x108.
|
| __IO uint8_t | DCHPRI10 |
| | Channel n Priority Register, offset: 0x109.
|
| __IO uint8_t | DCHPRI9 |
| | Channel n Priority Register, offset: 0x10A.
|
| __IO uint8_t | DCHPRI8 |
| | Channel n Priority Register, offset: 0x10B.
|
| __IO uint8_t | DCHPRI15 |
| | Channel n Priority Register, offset: 0x10C.
|
| __IO uint8_t | DCHPRI14 |
| | Channel n Priority Register, offset: 0x10D.
|
| __IO uint8_t | DCHPRI13 |
| | Channel n Priority Register, offset: 0x10E.
|
| __IO uint8_t | DCHPRI12 |
| | Channel n Priority Register, offset: 0x10F.
|
| __IO uint8_t | DCHPRI19 |
| | Channel n Priority Register, offset: 0x110.
|
| __IO uint8_t | DCHPRI18 |
| | Channel n Priority Register, offset: 0x111.
|
| __IO uint8_t | DCHPRI17 |
| | Channel n Priority Register, offset: 0x112.
|
| __IO uint8_t | DCHPRI16 |
| | Channel n Priority Register, offset: 0x113.
|
| __IO uint8_t | DCHPRI23 |
| | Channel n Priority Register, offset: 0x114.
|
| __IO uint8_t | DCHPRI22 |
| | Channel n Priority Register, offset: 0x115.
|
| __IO uint8_t | DCHPRI21 |
| | Channel n Priority Register, offset: 0x116.
|
| __IO uint8_t | DCHPRI20 |
| | Channel n Priority Register, offset: 0x117.
|
| __IO uint8_t | DCHPRI27 |
| | Channel n Priority Register, offset: 0x118.
|
| __IO uint8_t | DCHPRI26 |
| | Channel n Priority Register, offset: 0x119.
|
| __IO uint8_t | DCHPRI25 |
| | Channel n Priority Register, offset: 0x11A.
|
| __IO uint8_t | DCHPRI24 |
| | Channel n Priority Register, offset: 0x11B.
|
| __IO uint8_t | DCHPRI31 |
| | Channel n Priority Register, offset: 0x11C.
|
| __IO uint8_t | DCHPRI30 |
| | Channel n Priority Register, offset: 0x11D.
|
| __IO uint8_t | DCHPRI29 |
| | Channel n Priority Register, offset: 0x11E.
|
| __IO uint8_t | DCHPRI28 |
| | Channel n Priority Register, offset: 0x11F.
|
| __IO uint32_t | SADDR |
| | TCD Source Address, array offset: 0x1000, array step: 0x20.
|
| __IO uint32_t | NBYTES_MLNO |
| | TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20.
|
| __IO uint16_t | CITER_ELINKNO |
| | TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20.
|
| __IO uint16_t | BITER_ELINKNO |
| | TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20.
|
| __IO uint32_t | SAR |
| | Source Address Register, array offset: 0x100, array step: 0x10.
|
| __IO uint32_t | DSR_BCR |
| | DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10.
|
DMA - Register Layout Typedef.
1.7.2