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FMC_Type Struct Reference
FMC - Register Layout Typedef.
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#include <MK20D5.h >
__IO uint32_t PFAPR Flash Access Protection Register, offset: 0x0. __IO uint32_t PFB0CR Flash Control Register, offset: 0x4. __IO uint32_t PFB01CR Flash Bank 0-1 Control Register, offset: 0x4. __IO uint32_t PFB23CR Flash Bank 2-3 Control Register, offset: 0x8. __IO uint32_t TAGVDW0S [4] Cache Tag Storage, array offset: 0x100, array step: 0x4. __IO uint32_t TAGVDW1S [4] Cache Tag Storage, array offset: 0x110, array step: 0x4. __IO uint32_t TAGVDW2S [4] Cache Tag Storage, array offset: 0x120, array step: 0x4. __IO uint32_t TAGVDW3S [4] Cache Tag Storage, array offset: 0x130, array step: 0x4. __IO uint32_t TAGVD [2] Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4. __IO uint32_t DATAW0S Cache Data Storage, array offset: 0x204, array step: 0x8. __IO uint32_t DATAW1S Cache Data Storage, array offset: 0x244, array step: 0x8. __IO uint32_t DATAW2S Cache Data Storage, array offset: 0x284, array step: 0x8. __IO uint32_t DATAW3S Cache Data Storage, array offset: 0x2C4, array step: 0x8. __IO uint32_t DATA_UM Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10. __IO uint32_t DATA_MU Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10. __IO uint32_t DATA_ML Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10. __IO uint32_t DATA_LM Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10.
Detailed Description
FMC - Register Layout Typedef.
Definition at line 1791 of file MK20D5.h .
Field Documentation
Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10.
Definition at line 9836 of file MK26F18.h .
Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10.
Definition at line 9835 of file MK26F18.h .
Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10.
Definition at line 9834 of file MK26F18.h .
Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10.
Definition at line 9833 of file MK26F18.h .
Cache Data Storage, array offset: 0x204, array step: 0x8.
Definition at line 1801 of file MK20D5.h .
Cache Data Storage, array offset: 0x244, array step: 0x8.
Definition at line 1806 of file MK20D5.h .
Cache Data Storage, array offset: 0x284, array step: 0x8.
Definition at line 1811 of file MK20D5.h .
Cache Data Storage, array offset: 0x2C4, array step: 0x8.
Definition at line 1816 of file MK20D5.h .
Flash Access Protection Register, offset: 0x0.
Definition at line 1792 of file MK20D5.h .
Flash Bank 0-1 Control Register, offset: 0x4.
Definition at line 9824 of file MK26F18.h .
Flash Bank 2-3 Control Register, offset: 0x8.
Definition at line 9825 of file MK26F18.h .
Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4.
Definition at line 1796 of file MK20D5.h .
Cache Tag Storage, array offset: 0x100, array step: 0x4.
Definition at line 9827 of file MK26F18.h .
Cache Tag Storage, array offset: 0x110, array step: 0x4.
Definition at line 9828 of file MK26F18.h .
Cache Tag Storage, array offset: 0x120, array step: 0x4.
Definition at line 9829 of file MK26F18.h .
Cache Tag Storage, array offset: 0x130, array step: 0x4.
Definition at line 9830 of file MK26F18.h .
1.7.2