Data Structures |
| struct | ADC_Type |
| | ADC - Register Layout Typedef. More...
|
| struct | CMP_Type |
| | CMP - Register Layout Typedef. More...
|
| struct | CMT_Type |
| | CMT - Register Layout Typedef. More...
|
| struct | CRC_Type |
| | CRC - Register Layout Typedef. More...
|
| struct | DMA_Type |
| | DMA - Register Layout Typedef. More...
|
| struct | DMAMUX_Type |
| | DMAMUX - Register Layout Typedef. More...
|
| struct | EWM_Type |
| | EWM - Register Layout Typedef. More...
|
| struct | FMC_Type |
| | FMC - Register Layout Typedef. More...
|
| struct | FTFL_Type |
| | FTFL - Register Layout Typedef. More...
|
| struct | FTM_Type |
| | FTM - Register Layout Typedef. More...
|
| struct | GPIO_Type |
| | GPIO - Register Layout Typedef. More...
|
| struct | I2C_Type |
| | I2C - Register Layout Typedef. More...
|
| struct | I2S_Type |
| | I2S - Register Layout Typedef. More...
|
| struct | LLWU_Type |
| | LLWU - Register Layout Typedef. More...
|
| struct | LPTMR_Type |
| | LPTMR - Register Layout Typedef. More...
|
| struct | MCG_Type |
| | MCG - Register Layout Typedef. More...
|
| struct | NV_Type |
| | NV - Register Layout Typedef. More...
|
| struct | OSC_Type |
| | OSC - Register Layout Typedef. More...
|
| struct | PDB_Type |
| | PDB - Register Layout Typedef. More...
|
| struct | PIT_Type |
| | PIT - Register Layout Typedef. More...
|
| struct | PMC_Type |
| | PMC - Register Layout Typedef. More...
|
| struct | PORT_Type |
| | PORT - Register Layout Typedef. More...
|
| struct | RCM_Type |
| | RCM - Register Layout Typedef. More...
|
| struct | RFSYS_Type |
| | RFSYS - Register Layout Typedef. More...
|
| struct | RFVBAT_Type |
| | RFVBAT - Register Layout Typedef. More...
|
| struct | RTC_Type |
| | RTC - Register Layout Typedef. More...
|
| struct | SIM_Type |
| | SIM - Register Layout Typedef. More...
|
| struct | SMC_Type |
| | SMC - Register Layout Typedef. More...
|
| struct | SPI_Type |
| | SPI - Register Layout Typedef. More...
|
| struct | TSI_Type |
| | TSI - Register Layout Typedef. More...
|
| struct | UART_Type |
| | UART - Register Layout Typedef. More...
|
| struct | USB_Type |
| | USB - Register Layout Typedef. More...
|
| struct | USBDCD_Type |
| | USBDCD - Register Layout Typedef. More...
|
| struct | VREF_Type |
| | VREF - Register Layout Typedef. More...
|
| struct | WDOG_Type |
| | WDOG - Register Layout Typedef. More...
|
Typedefs |
| typedef enum _dma_request_source | dma_request_source_t |
| | Structure for the DMA hardware request.
|
Enumerations |
| enum | IRQn {
NonMaskableInt_IRQn = -14,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
SUPC_IRQn = 0,
RSTC_IRQn = 1,
RTC_IRQn = 2,
RTT_IRQn = 3,
WDT_IRQn = 4,
PMC_IRQn = 5,
EFC0_IRQn = 6,
UART_IRQn = 8,
SMC_IRQn = 9,
PIOA_IRQn = 10,
PIOB_IRQn = 11,
USART0_IRQn = 13,
USART1_IRQn = 14,
USART2_IRQn = 15,
HSMCI_IRQn = 17,
TWI0_IRQn = 18,
TWI1_IRQn = 19,
SPI_IRQn = 20,
SSC_IRQn = 21,
TC0_IRQn = 22,
TC1_IRQn = 23,
TC2_IRQn = 24,
PWM_IRQn = 25,
ADC12B_IRQn = 26,
ADC_IRQn = 27,
DMAC_IRQn = 28,
UDPHS_IRQn = 29,
PERIPH_COUNT_IRQn = 30,
NotAvail_IRQn = -128,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
DMA0_IRQn = 0,
DMA1_IRQn = 1,
DMA2_IRQn = 2,
DMA3_IRQn = 3,
DMA_Error_IRQn = 4,
Reserved21_IRQn = 5,
FTFL_IRQn = 6,
Read_Collision_IRQn = 7,
LVD_LVW_IRQn = 8,
LLW_IRQn = 9,
Watchdog_IRQn = 10,
I2C0_IRQn = 11,
SPI0_IRQn = 12,
I2S0_Tx_IRQn = 13,
I2S0_Rx_IRQn = 14,
UART0_LON_IRQn = 15,
UART0_RX_TX_IRQn = 16,
UART0_ERR_IRQn = 17,
UART1_RX_TX_IRQn = 18,
UART1_ERR_IRQn = 19,
UART2_RX_TX_IRQn = 20,
UART2_ERR_IRQn = 21,
ADC0_IRQn = 22,
CMP0_IRQn = 23,
CMP1_IRQn = 24,
FTM0_IRQn = 25,
FTM1_IRQn = 26,
CMT_IRQn = 27,
RTC_IRQn = 28,
RTC_Seconds_IRQn = 29,
PIT0_IRQn = 30,
PIT1_IRQn = 31,
PIT2_IRQn = 32,
PIT3_IRQn = 33,
PDB0_IRQn = 34,
USB0_IRQn = 35,
USBDCD_IRQn = 36,
TSI0_IRQn = 37,
MCG_IRQn = 38,
LPTimer_IRQn = 39,
PORTA_IRQn = 40,
PORTB_IRQn = 41,
PORTC_IRQn = 42,
PORTD_IRQn = 43,
PORTE_IRQn = 44,
SWI_IRQn = 45,
NotAvail_IRQn = -128,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
DMA0_DMA16_IRQn = 0,
DMA1_DMA17_IRQn = 1,
DMA2_DMA18_IRQn = 2,
DMA3_DMA19_IRQn = 3,
DMA4_DMA20_IRQn = 4,
DMA5_DMA21_IRQn = 5,
DMA6_DMA22_IRQn = 6,
DMA7_DMA23_IRQn = 7,
DMA8_DMA24_IRQn = 8,
DMA9_DMA25_IRQn = 9,
DMA10_DMA26_IRQn = 10,
DMA11_DMA27_IRQn = 11,
DMA12_DMA28_IRQn = 12,
DMA13_DMA29_IRQn = 13,
DMA14_DMA30_IRQn = 14,
DMA15_DMA31_IRQn = 15,
DMA_Error_IRQn = 16,
MCM_IRQn = 17,
FTFE_IRQn = 18,
Read_Collision_IRQn = 19,
LVD_LVW_IRQn = 20,
LLWU_IRQn = 21,
WDOG_EWM_IRQn = 22,
RNG_IRQn = 23,
I2C0_IRQn = 24,
I2C1_IRQn = 25,
SPI0_IRQn = 26,
SPI1_IRQn = 27,
I2S0_Tx_IRQn = 28,
I2S0_Rx_IRQn = 29,
Reserved46_IRQn = 30,
UART0_RX_TX_IRQn = 31,
UART0_ERR_IRQn = 32,
UART1_RX_TX_IRQn = 33,
UART1_ERR_IRQn = 34,
UART2_RX_TX_IRQn = 35,
UART2_ERR_IRQn = 36,
UART3_RX_TX_IRQn = 37,
UART3_ERR_IRQn = 38,
ADC0_IRQn = 39,
CMP0_IRQn = 40,
CMP1_IRQn = 41,
FTM0_IRQn = 42,
FTM1_IRQn = 43,
FTM2_IRQn = 44,
CMT_IRQn = 45,
RTC_IRQn = 46,
RTC_Seconds_IRQn = 47,
PIT0_IRQn = 48,
PIT1_IRQn = 49,
PIT2_IRQn = 50,
PIT3_IRQn = 51,
PDB0_IRQn = 52,
USB0_IRQn = 53,
USBDCD_IRQn = 54,
Reserved71_IRQn = 55,
DAC0_IRQn = 56,
MCG_IRQn = 57,
LPTMR0_IRQn = 58,
PORTA_IRQn = 59,
PORTB_IRQn = 60,
PORTC_IRQn = 61,
PORTD_IRQn = 62,
PORTE_IRQn = 63,
SWI_IRQn = 64,
SPI2_IRQn = 65,
UART4_RX_TX_IRQn = 66,
UART4_ERR_IRQn = 67,
Reserved84_IRQn = 68,
Reserved85_IRQn = 69,
CMP2_IRQn = 70,
FTM3_IRQn = 71,
DAC1_IRQn = 72,
ADC1_IRQn = 73,
I2C2_IRQn = 74,
CAN0_ORed_Message_buffer_IRQn = 75,
CAN0_Bus_Off_IRQn = 76,
CAN0_Error_IRQn = 77,
CAN0_Tx_Warning_IRQn = 78,
CAN0_Rx_Warning_IRQn = 79,
CAN0_Wake_Up_IRQn = 80,
SDHC_IRQn = 81,
Reserved98_IRQn = 82,
Reserved99_IRQn = 83,
Reserved100_IRQn = 84,
Reserved101_IRQn = 85,
LPUART0_IRQn = 86,
TSI0_IRQn = 87,
TPM1_IRQn = 88,
TPM2_IRQn = 89,
USBHSDCD_IRQn = 90,
I2C3_IRQn = 91,
CMP3_IRQn = 92,
USBHS_IRQn = 93,
CAN1_ORed_Message_buffer_IRQn = 94,
CAN1_Bus_Off_IRQn = 95,
CAN1_Error_IRQn = 96,
CAN1_Tx_Warning_IRQn = 97,
CAN1_Rx_Warning_IRQn = 98,
CAN1_Wake_Up_IRQn = 99,
NotAvail_IRQn = -128,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
SVCall_IRQn = -5,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
DMA0_IRQn = 0,
DMA1_IRQn = 1,
DMA2_IRQn = 2,
DMA3_IRQn = 3,
Reserved20_IRQn = 4,
FTFA_IRQn = 5,
LVD_LVW_IRQn = 6,
LLWU_IRQn = 7,
I2C0_IRQn = 8,
I2C1_IRQn = 9,
SPI0_IRQn = 10,
SPI1_IRQn = 11,
UART0_IRQn = 12,
UART1_IRQn = 13,
UART2_IRQn = 14,
ADC0_IRQn = 15,
CMP0_IRQn = 16,
TPM0_IRQn = 17,
TPM1_IRQn = 18,
TPM2_IRQn = 19,
RTC_IRQn = 20,
RTC_Seconds_IRQn = 21,
PIT_IRQn = 22,
I2S0_IRQn = 23,
USB0_IRQn = 24,
DAC0_IRQn = 25,
TSI0_IRQn = 26,
MCG_IRQn = 27,
LPTMR0_IRQn = 28,
Reserved45_IRQn = 29,
PORTA_IRQn = 30,
PORTC_PORTD_IRQn = 31,
NonMaskableInt_IRQn = -14,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
BOD_IRQn = 0,
IRC_IRQn = 1,
PWRWU_IRQn = 2,
RAMPE_IRQn = 3,
CKFAIL_IRQn = 4,
RTC_IRQn = 6,
TAMPER_IRQn = 7,
WDT_IRQn = 8,
WWDT_IRQn = 9,
EINT0_IRQn = 10,
EINT1_IRQn = 11,
EINT2_IRQn = 12,
EINT3_IRQn = 13,
EINT4_IRQn = 14,
EINT5_IRQn = 15,
GPA_IRQn = 16,
GPB_IRQn = 17,
GPC_IRQn = 18,
GPD_IRQn = 19,
GPE_IRQn = 20,
GPF_IRQn = 21,
QSPI0_IRQn = 22,
SPI0_IRQn = 23,
BRAKE0_IRQn = 24,
EPWM0P0_IRQn = 25,
EPWM0P1_IRQn = 26,
EPWM0P2_IRQn = 27,
BRAKE1_IRQn = 28,
EPWM1P0_IRQn = 29,
EPWM1P1_IRQn = 30,
EPWM1P2_IRQn = 31,
TMR0_IRQn = 32,
TMR1_IRQn = 33,
TMR2_IRQn = 34,
TMR3_IRQn = 35,
UART0_IRQn = 36,
UART1_IRQn = 37,
I2C0_IRQn = 38,
I2C1_IRQn = 39,
PDMA_IRQn = 40,
DAC_IRQn = 41,
ADC0_IRQn = 42,
ADC1_IRQn = 43,
ACMP01_IRQn = 44,
ADC2_IRQn = 46,
ADC3_IRQn = 47,
UART2_IRQn = 48,
UART3_IRQn = 49,
SPI1_IRQn = 51,
SPI2_IRQn = 52,
USBD_IRQn = 53,
USBH_IRQn = 54,
USBOTG_IRQn = 55,
CAN0_IRQn = 56,
CAN1_IRQn = 57,
SC0_IRQn = 58,
SC1_IRQn = 59,
SC2_IRQn = 60,
SPI3_IRQn = 62,
EMAC_TX_IRQn = 66,
EMAC_RX_IRQn = 67,
SDH0_IRQn = 64,
USBD20_IRQn = 65,
I2S0_IRQn = 68,
OPA_IRQn = 70,
CRPT_IRQn = 71,
GPG_IRQn = 72,
EINT6_IRQn = 73,
UART4_IRQn = 74,
UART5_IRQn = 75,
USCI0_IRQn = 76,
USCI1_IRQn = 77,
BPWM0_IRQn = 78,
BPWM1_IRQn = 79,
SPIM_IRQn = 80,
I2C2_IRQn = 82,
QEI0_IRQn = 84,
QEI1_IRQn = 85,
ECAP0_IRQn = 86,
ECAP1_IRQn = 87,
GPH_IRQn = 88,
EINT7_IRQn = 89,
SDH1_IRQn = 90,
HSUSBH_IRQn = 92,
USBOTG20_IRQn = 93
} |
| enum | _dma_request_source {
kDmaRequestMux0SoftwareDMARequest = 0|0x100U,
kDmaRequestMux0Reserved1 = 1|0x100U,
kDmaRequestMux0UART0ReceiveDMARequest = 2|0x100U,
kDmaRequestMux0UART0TransmitDMARequest = 3|0x100U,
kDmaRequestMux0UART1ReceiveDMARequest = 4|0x100U,
kDmaRequestMux0UART1TransmitDMARequest = 5|0x100U,
kDmaRequestMux0UART2ReceiveDMARequest = 6|0x100U,
kDmaRequestMux0UART2TransmitDMARequest = 7|0x100U,
kDmaRequestMux0Reserved8 = 8|0x100U,
kDmaRequestMux0Reserved9 = 9|0x100U,
kDmaRequestMux0Reserved10 = 10|0x100U,
kDmaRequestMux0Reserved11 = 11|0x100U,
kDmaRequestMux0Reserved12 = 12|0x100U,
kDmaRequestMux0Reserved13 = 13|0x100U,
kDmaRequestMux0I2S0ReceiveDMARequest = 14|0x100U,
kDmaRequestMux0I2S0TransmitDMARequest = 15|0x100U,
kDmaRequestMux0SPI0ReceiveDMARequest = 16|0x100U,
kDmaRequestMux0SPI0TransmitDMARequest = 17|0x100U,
kDmaRequestMux0Reserved18 = 18|0x100U,
kDmaRequestMux0Reserved19 = 19|0x100U,
kDmaRequestMux0Reserved20 = 20|0x100U,
kDmaRequestMux0Reserved21 = 21|0x100U,
kDmaRequestMux0I2C0DMARequest = 22|0x100U,
kDmaRequestMux0Reserved23 = 23|0x100U,
kDmaRequestMux0FTM0C0DMARequest = 24|0x100U,
kDmaRequestMux0FTM0C1DMARequest = 25|0x100U,
kDmaRequestMux0FTM0C2DMARequest = 26|0x100U,
kDmaRequestMux0FTM0C3DMARequest = 27|0x100U,
kDmaRequestMux0FTM0C4DMARequest = 28|0x100U,
kDmaRequestMux0FTM0C5DMARequest = 29|0x100U,
kDmaRequestMux0FTM0C6DMARequest = 30|0x100U,
kDmaRequestMux0FTM0C7DMARequest = 31|0x100U,
kDmaRequestMux0FTM1C0DMARequest = 32|0x100U,
kDmaRequestMux0FTM1C1DMARequest = 33|0x100U,
kDmaRequestMux0Reserved34 = 34|0x100U,
kDmaRequestMux0Reserved35 = 35|0x100U,
kDmaRequestMux0Reserved36 = 36|0x100U,
kDmaRequestMux0Reserved37 = 37|0x100U,
kDmaRequestMux0Reserved38 = 38|0x100U,
kDmaRequestMux0Reserved39 = 39|0x100U,
kDmaRequestMux0ADC0DMARequest = 40|0x100U,
kDmaRequestMux0Reserved41 = 41|0x100U,
kDmaRequestMux0CMP0DMARequest = 42|0x100U,
kDmaRequestMux0CMP1DMARequest = 43|0x100U,
kDmaRequestMux0Reserved44 = 44|0x100U,
kDmaRequestMux0Reserved45 = 45|0x100U,
kDmaRequestMux0Reserved46 = 46|0x100U,
kDmaRequestMux0CMTDMARequest = 47|0x100U,
kDmaRequestMux0PDBDMARequest = 48|0x100U,
kDmaRequestMux0GPIOPortADMARequest = 49|0x100U,
kDmaRequestMux0GPIOPortBDMARequest = 50|0x100U,
kDmaRequestMux0GPIOPortCDMARequest = 51|0x100U,
kDmaRequestMux0GPIOPortDDMARequest = 52|0x100U,
kDmaRequestMux0GPIOPortEDMARequest = 53|0x100U,
kDmaRequestMux0AlwaysEnabledslot54DMARequest = 54|0x100U,
kDmaRequestMux0AlwaysEnabledslot55DMARequest = 55|0x100U,
kDmaRequestMux0AlwaysEnabledslot56DMARequest = 56|0x100U,
kDmaRequestMux0AlwaysEnabledslot57DMARequest = 57|0x100U,
kDmaRequestMux0AlwaysEnabledslot58DMARequest = 58|0x100U,
kDmaRequestMux0AlwaysEnabledslot59DMARequest = 59|0x100U,
kDmaRequestMux0AlwaysEnabledslot60DMARequest = 60|0x100U,
kDmaRequestMux0AlwaysEnabledslot61DMARequest = 61|0x100U,
kDmaRequestMux0AlwaysEnabledslot62DMARequest = 62|0x100U,
kDmaRequestMux0AlwaysEnabledslot63DMARequest = 63|0x100U,
kDmaRequestMux0Disable = 0|0x100U,
kDmaRequestMux0TSI0 = 1|0x100U,
kDmaRequestMux0UART0Rx = 2|0x100U,
kDmaRequestMux0UART0Tx = 3|0x100U,
kDmaRequestMux0UART1Rx = 4|0x100U,
kDmaRequestMux0UART1Tx = 5|0x100U,
kDmaRequestMux0UART2Rx = 6|0x100U,
kDmaRequestMux0UART2Tx = 7|0x100U,
kDmaRequestMux0UART3Rx = 8|0x100U,
kDmaRequestMux0UART3Tx = 9|0x100U,
kDmaRequestMux0UART4 = 10|0x100U,
kDmaRequestMux0Reserved11 = 11|0x100U,
kDmaRequestMux0I2S0Rx = 12|0x100U,
kDmaRequestMux0I2S0Tx = 13|0x100U,
kDmaRequestMux0SPI0Rx = 14|0x100U,
kDmaRequestMux0SPI0Tx = 15|0x100U,
kDmaRequestMux0SPI1Rx = 16|0x100U,
kDmaRequestMux0SPI1Tx = 17|0x100U,
kDmaRequestMux0I2C0I2C3 = 18|0x100U,
kDmaRequestMux0I2C0 = 18|0x100U,
kDmaRequestMux0I2C3 = 18|0x100U,
kDmaRequestMux0I2C1I2C2 = 19|0x100U,
kDmaRequestMux0I2C1 = 19|0x100U,
kDmaRequestMux0I2C2 = 19|0x100U,
kDmaRequestMux0FTM0Channel0 = 20|0x100U,
kDmaRequestMux0FTM0Channel1 = 21|0x100U,
kDmaRequestMux0FTM0Channel2 = 22|0x100U,
kDmaRequestMux0FTM0Channel3 = 23|0x100U,
kDmaRequestMux0FTM0Channel4 = 24|0x100U,
kDmaRequestMux0FTM0Channel5 = 25|0x100U,
kDmaRequestMux0FTM0Channel6 = 26|0x100U,
kDmaRequestMux0FTM0Channel7 = 27|0x100U,
kDmaRequestMux0FTM1TPM1Channel0 = 28|0x100U,
kDmaRequestMux0FTM1Channel0 = 28|0x100U,
kDmaRequestMux0TPM1Channel0 = 28|0x100U,
kDmaRequestMux0FTM1TPM1Channel1 = 29|0x100U,
kDmaRequestMux0FTM1Channel1 = 29|0x100U,
kDmaRequestMux0TPM1Channel1 = 29|0x100U,
kDmaRequestMux0FTM2TPM2Channel0 = 30|0x100U,
kDmaRequestMux0FTM2Channel0 = 30|0x100U,
kDmaRequestMux0TPM2Channel0 = 30|0x100U,
kDmaRequestMux0FTM2TPM2Channel1 = 31|0x100U,
kDmaRequestMux0FTM2Channel1 = 31|0x100U,
kDmaRequestMux0TPM2Channel1 = 31|0x100U,
kDmaRequestMux0FTM3Channel0 = 32|0x100U,
kDmaRequestMux0FTM3Channel1 = 33|0x100U,
kDmaRequestMux0FTM3Channel2 = 34|0x100U,
kDmaRequestMux0FTM3Channel3 = 35|0x100U,
kDmaRequestMux0FTM3Channel4 = 36|0x100U,
kDmaRequestMux0FTM3Channel5 = 37|0x100U,
kDmaRequestMux0FTM3Channel6SPI2Rx = 38|0x100U,
kDmaRequestMux0FTM3Channel6 = 38|0x100U,
kDmaRequestMux0SPI2Rx = 38|0x100U,
kDmaRequestMux0FTM3Channel7SPI2Tx = 39|0x100U,
kDmaRequestMux0FTM3Channel7 = 39|0x100U,
kDmaRequestMux0SPI2Tx = 39|0x100U,
kDmaRequestMux0ADC0 = 40|0x100U,
kDmaRequestMux0ADC1 = 41|0x100U,
kDmaRequestMux0CMP0 = 42|0x100U,
kDmaRequestMux0CMP1 = 43|0x100U,
kDmaRequestMux0CMP2CMP3 = 44|0x100U,
kDmaRequestMux0CMP2 = 44|0x100U,
kDmaRequestMux0CMP3 = 44|0x100U,
kDmaRequestMux0DAC0 = 45|0x100U,
kDmaRequestMux0DAC1 = 46|0x100U,
kDmaRequestMux0CMT = 47|0x100U,
kDmaRequestMux0PDB = 48|0x100U,
kDmaRequestMux0PortA = 49|0x100U,
kDmaRequestMux0PortB = 50|0x100U,
kDmaRequestMux0PortC = 51|0x100U,
kDmaRequestMux0PortD = 52|0x100U,
kDmaRequestMux0PortE = 53|0x100U,
kDmaRequestMux0Reserved54 = 54|0x100U,
kDmaRequestMux0TPM1Overflow = 55|0x100U,
kDmaRequestMux0TPM2Overflow = 56|0x100U,
kDmaRequestMux0Reserved57 = 57|0x100U,
kDmaRequestMux0LPUART0Rx = 58|0x100U,
kDmaRequestMux0LPUART0Tx = 59|0x100U,
kDmaRequestMux0AlwaysOn60 = 60|0x100U,
kDmaRequestMux0AlwaysOn61 = 61|0x100U,
kDmaRequestMux0AlwaysOn62 = 62|0x100U,
kDmaRequestMux0AlwaysOn63 = 63|0x100U,
kDmaRequestMux0Disable = 0|0x100U,
kDmaRequestMux0Reserved1 = 1|0x100U,
kDmaRequestMux0UART0Rx = 2|0x100U,
kDmaRequestMux0LPSCI0Rx = 2|0x100U,
kDmaRequestMux0UART0Tx = 3|0x100U,
kDmaRequestMux0LPSCI0Tx = 3|0x100U,
kDmaRequestMux0UART1Rx = 4|0x100U,
kDmaRequestMux0UART1Tx = 5|0x100U,
kDmaRequestMux0UART2Rx = 6|0x100U,
kDmaRequestMux0UART2Tx = 7|0x100U,
kDmaRequestMux0Reserved8 = 8|0x100U,
kDmaRequestMux0Reserved9 = 9|0x100U,
kDmaRequestMux0Reserved10 = 10|0x100U,
kDmaRequestMux0Reserved11 = 11|0x100U,
kDmaRequestMux0Reserved12 = 12|0x100U,
kDmaRequestMux0Reserved13 = 13|0x100U,
kDmaRequestMux0I2S0Rx = 14|0x100U,
kDmaRequestMux0I2S0Tx = 15|0x100U,
kDmaRequestMux0SPI0Rx = 16|0x100U,
kDmaRequestMux0SPI0Tx = 17|0x100U,
kDmaRequestMux0SPI1Rx = 18|0x100U,
kDmaRequestMux0SPI1Tx = 19|0x100U,
kDmaRequestMux0Reserved20 = 20|0x100U,
kDmaRequestMux0Reserved21 = 21|0x100U,
kDmaRequestMux0I2C0 = 22|0x100U,
kDmaRequestMux0I2C1 = 23|0x100U,
kDmaRequestMux0TPM0Channel0 = 24|0x100U,
kDmaRequestMux0TPM0Channel1 = 25|0x100U,
kDmaRequestMux0TPM0Channel2 = 26|0x100U,
kDmaRequestMux0TPM0Channel3 = 27|0x100U,
kDmaRequestMux0TPM0Channel4 = 28|0x100U,
kDmaRequestMux0TPM0Channel5 = 29|0x100U,
kDmaRequestMux0Reserved30 = 30|0x100U,
kDmaRequestMux0Reserved31 = 31|0x100U,
kDmaRequestMux0TPM1Channel0 = 32|0x100U,
kDmaRequestMux0TPM1Channel1 = 33|0x100U,
kDmaRequestMux0TPM2Channel0 = 34|0x100U,
kDmaRequestMux0TPM2Channel1 = 35|0x100U,
kDmaRequestMux0Reserved36 = 36|0x100U,
kDmaRequestMux0Reserved37 = 37|0x100U,
kDmaRequestMux0Reserved38 = 38|0x100U,
kDmaRequestMux0Reserved39 = 39|0x100U,
kDmaRequestMux0ADC0 = 40|0x100U,
kDmaRequestMux0Reserved41 = 41|0x100U,
kDmaRequestMux0CMP0 = 42|0x100U,
kDmaRequestMux0Reserved43 = 43|0x100U,
kDmaRequestMux0Reserved44 = 44|0x100U,
kDmaRequestMux0DAC0 = 45|0x100U,
kDmaRequestMux0Reserved46 = 46|0x100U,
kDmaRequestMux0Reserved47 = 47|0x100U,
kDmaRequestMux0Reserved48 = 48|0x100U,
kDmaRequestMux0PortA = 49|0x100U,
kDmaRequestMux0Reserved50 = 50|0x100U,
kDmaRequestMux0PortC = 51|0x100U,
kDmaRequestMux0PortD = 52|0x100U,
kDmaRequestMux0Reserved53 = 53|0x100U,
kDmaRequestMux0TPM0Overflow = 54|0x100U,
kDmaRequestMux0TPM1Overflow = 55|0x100U,
kDmaRequestMux0TPM2Overflow = 56|0x100U,
kDmaRequestMux0TSI = 57|0x100U,
kDmaRequestMux0Reserved58 = 58|0x100U,
kDmaRequestMux0Reserved59 = 59|0x100U,
kDmaRequestMux0AlwaysOn60 = 60|0x100U,
kDmaRequestMux0AlwaysOn61 = 61|0x100U,
kDmaRequestMux0AlwaysOn62 = 62|0x100U,
kDmaRequestMux0AlwaysOn63 = 63|0x100U
} |
| | Structure for the DMA hardware request.
More...
|
CMSIS Peripheral Access Layer for MK20D5.
1.7.2