Arrow
/
DAPLink Reset
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Embed:
(wiki syntax)
SPI_Type Struct Reference
[SPI Peripheral Access Layer]
SPI - Register Layout Typedef. More...
#include <MK20D5.h>
Data Fields | |
| __IO uint32_t | MCR |
| DSPI Module Configuration Register, offset: 0x0. | |
| __IO uint32_t | TCR |
| DSPI Transfer Count Register, offset: 0x8. | |
| __IO uint32_t | SR |
| DSPI Status Register, offset: 0x2C. | |
| __IO uint32_t | RSER |
| DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30. | |
| __I uint32_t | POPR |
| DSPI POP RX FIFO Register, offset: 0x38. | |
| __I uint32_t | TXFR0 |
| DSPI Transmit FIFO Registers, offset: 0x3C. | |
| __I uint32_t | TXFR1 |
| DSPI Transmit FIFO Registers, offset: 0x40. | |
| __I uint32_t | TXFR2 |
| DSPI Transmit FIFO Registers, offset: 0x44. | |
| __I uint32_t | TXFR3 |
| DSPI Transmit FIFO Registers, offset: 0x48. | |
| __I uint32_t | RXFR0 |
| DSPI Receive FIFO Registers, offset: 0x7C. | |
| __I uint32_t | RXFR1 |
| DSPI Receive FIFO Registers, offset: 0x80. | |
| __I uint32_t | RXFR2 |
| DSPI Receive FIFO Registers, offset: 0x84. | |
| __I uint32_t | RXFR3 |
| DSPI Receive FIFO Registers, offset: 0x88. | |
| __IO uint8_t | S |
| SPI Status Register, offset: 0x0. | |
| __IO uint8_t | BR |
| SPI Baud Rate Register, offset: 0x1. | |
| __IO uint8_t | C2 |
| SPI Control Register 2, offset: 0x2. | |
| __IO uint8_t | C1 |
| SPI Control Register 1, offset: 0x3. | |
| __IO uint8_t | ML |
| SPI Match Register low, offset: 0x4. | |
| __IO uint8_t | MH |
| SPI match register high, offset: 0x5. | |
| __IO uint8_t | DL |
| SPI Data Register low, offset: 0x6. | |
| __IO uint8_t | DH |
| SPI data register high, offset: 0x7. | |
| __IO uint8_t | CI |
| SPI clear interrupt register, offset: 0xA. | |
| __IO uint8_t | C3 |
| SPI control register 3, offset: 0xB. | |
| __IO uint32_t | CTAR [2] |
| DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4. | |
| __IO uint32_t | PUSHR |
| DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34. | |
Detailed Description
SPI - Register Layout Typedef.
Definition at line 5684 of file MK20D5.h.
Field Documentation
| __IO uint32_t CTAR[2] |
| __IO uint32_t MCR |
| __IO uint32_t PUSHR |
Generated on Tue Jul 12 2022 15:37:38 by
1.7.2