Mapping Information. More...

Typedefs
typedef enum _dma_request_source	dma_request_source_t
	Structure for the DMA hardware request.
typedef enum _dma_request_source	dma_request_source_t
	Structure for the DMA hardware request.
typedef enum _dma_request_source	dma_request_source_t
	Structure for the DMA hardware request.
Enumerations
enum	_dma_request_source { kDmaRequestMux0SoftwareDMARequest = 0\|0x100U, kDmaRequestMux0Reserved1 = 1\|0x100U, kDmaRequestMux0UART0ReceiveDMARequest = 2\|0x100U, kDmaRequestMux0UART0TransmitDMARequest = 3\|0x100U, kDmaRequestMux0UART1ReceiveDMARequest = 4\|0x100U, kDmaRequestMux0UART1TransmitDMARequest = 5\|0x100U, kDmaRequestMux0UART2ReceiveDMARequest = 6\|0x100U, kDmaRequestMux0UART2TransmitDMARequest = 7\|0x100U, kDmaRequestMux0Reserved8 = 8\|0x100U, kDmaRequestMux0Reserved9 = 9\|0x100U, kDmaRequestMux0Reserved10 = 10\|0x100U, kDmaRequestMux0Reserved11 = 11\|0x100U, kDmaRequestMux0Reserved12 = 12\|0x100U, kDmaRequestMux0Reserved13 = 13\|0x100U, kDmaRequestMux0I2S0ReceiveDMARequest = 14\|0x100U, kDmaRequestMux0I2S0TransmitDMARequest = 15\|0x100U, kDmaRequestMux0SPI0ReceiveDMARequest = 16\|0x100U, kDmaRequestMux0SPI0TransmitDMARequest = 17\|0x100U, kDmaRequestMux0Reserved18 = 18\|0x100U, kDmaRequestMux0Reserved19 = 19\|0x100U, kDmaRequestMux0Reserved20 = 20\|0x100U, kDmaRequestMux0Reserved21 = 21\|0x100U, kDmaRequestMux0I2C0DMARequest = 22\|0x100U, kDmaRequestMux0Reserved23 = 23\|0x100U, kDmaRequestMux0FTM0C0DMARequest = 24\|0x100U, kDmaRequestMux0FTM0C1DMARequest = 25\|0x100U, kDmaRequestMux0FTM0C2DMARequest = 26\|0x100U, kDmaRequestMux0FTM0C3DMARequest = 27\|0x100U, kDmaRequestMux0FTM0C4DMARequest = 28\|0x100U, kDmaRequestMux0FTM0C5DMARequest = 29\|0x100U, kDmaRequestMux0FTM0C6DMARequest = 30\|0x100U, kDmaRequestMux0FTM0C7DMARequest = 31\|0x100U, kDmaRequestMux0FTM1C0DMARequest = 32\|0x100U, kDmaRequestMux0FTM1C1DMARequest = 33\|0x100U, kDmaRequestMux0Reserved34 = 34\|0x100U, kDmaRequestMux0Reserved35 = 35\|0x100U, kDmaRequestMux0Reserved36 = 36\|0x100U, kDmaRequestMux0Reserved37 = 37\|0x100U, kDmaRequestMux0Reserved38 = 38\|0x100U, kDmaRequestMux0Reserved39 = 39\|0x100U, kDmaRequestMux0ADC0DMARequest = 40\|0x100U, kDmaRequestMux0Reserved41 = 41\|0x100U, kDmaRequestMux0CMP0DMARequest = 42\|0x100U, kDmaRequestMux0CMP1DMARequest = 43\|0x100U, kDmaRequestMux0Reserved44 = 44\|0x100U, kDmaRequestMux0Reserved45 = 45\|0x100U, kDmaRequestMux0Reserved46 = 46\|0x100U, kDmaRequestMux0CMTDMARequest = 47\|0x100U, kDmaRequestMux0PDBDMARequest = 48\|0x100U, kDmaRequestMux0GPIOPortADMARequest = 49\|0x100U, kDmaRequestMux0GPIOPortBDMARequest = 50\|0x100U, kDmaRequestMux0GPIOPortCDMARequest = 51\|0x100U, kDmaRequestMux0GPIOPortDDMARequest = 52\|0x100U, kDmaRequestMux0GPIOPortEDMARequest = 53\|0x100U, kDmaRequestMux0AlwaysEnabledslot54DMARequest = 54\|0x100U, kDmaRequestMux0AlwaysEnabledslot55DMARequest = 55\|0x100U, kDmaRequestMux0AlwaysEnabledslot56DMARequest = 56\|0x100U, kDmaRequestMux0AlwaysEnabledslot57DMARequest = 57\|0x100U, kDmaRequestMux0AlwaysEnabledslot58DMARequest = 58\|0x100U, kDmaRequestMux0AlwaysEnabledslot59DMARequest = 59\|0x100U, kDmaRequestMux0AlwaysEnabledslot60DMARequest = 60\|0x100U, kDmaRequestMux0AlwaysEnabledslot61DMARequest = 61\|0x100U, kDmaRequestMux0AlwaysEnabledslot62DMARequest = 62\|0x100U, kDmaRequestMux0AlwaysEnabledslot63DMARequest = 63\|0x100U, kDmaRequestMux0Disable = 0\|0x100U, kDmaRequestMux0TSI0 = 1\|0x100U, kDmaRequestMux0UART0Rx = 2\|0x100U, kDmaRequestMux0UART0Tx = 3\|0x100U, kDmaRequestMux0UART1Rx = 4\|0x100U, kDmaRequestMux0UART1Tx = 5\|0x100U, kDmaRequestMux0UART2Rx = 6\|0x100U, kDmaRequestMux0UART2Tx = 7\|0x100U, kDmaRequestMux0UART3Rx = 8\|0x100U, kDmaRequestMux0UART3Tx = 9\|0x100U, kDmaRequestMux0UART4 = 10\|0x100U, kDmaRequestMux0Reserved11 = 11\|0x100U, kDmaRequestMux0I2S0Rx = 12\|0x100U, kDmaRequestMux0I2S0Tx = 13\|0x100U, kDmaRequestMux0SPI0Rx = 14\|0x100U, kDmaRequestMux0SPI0Tx = 15\|0x100U, kDmaRequestMux0SPI1Rx = 16\|0x100U, kDmaRequestMux0SPI1Tx = 17\|0x100U, kDmaRequestMux0I2C0I2C3 = 18\|0x100U, kDmaRequestMux0I2C0 = 18\|0x100U, kDmaRequestMux0I2C3 = 18\|0x100U, kDmaRequestMux0I2C1I2C2 = 19\|0x100U, kDmaRequestMux0I2C1 = 19\|0x100U, kDmaRequestMux0I2C2 = 19\|0x100U, kDmaRequestMux0FTM0Channel0 = 20\|0x100U, kDmaRequestMux0FTM0Channel1 = 21\|0x100U, kDmaRequestMux0FTM0Channel2 = 22\|0x100U, kDmaRequestMux0FTM0Channel3 = 23\|0x100U, kDmaRequestMux0FTM0Channel4 = 24\|0x100U, kDmaRequestMux0FTM0Channel5 = 25\|0x100U, kDmaRequestMux0FTM0Channel6 = 26\|0x100U, kDmaRequestMux0FTM0Channel7 = 27\|0x100U, kDmaRequestMux0FTM1TPM1Channel0 = 28\|0x100U, kDmaRequestMux0FTM1Channel0 = 28\|0x100U, kDmaRequestMux0TPM1Channel0 = 28\|0x100U, kDmaRequestMux0FTM1TPM1Channel1 = 29\|0x100U, kDmaRequestMux0FTM1Channel1 = 29\|0x100U, kDmaRequestMux0TPM1Channel1 = 29\|0x100U, kDmaRequestMux0FTM2TPM2Channel0 = 30\|0x100U, kDmaRequestMux0FTM2Channel0 = 30\|0x100U, kDmaRequestMux0TPM2Channel0 = 30\|0x100U, kDmaRequestMux0FTM2TPM2Channel1 = 31\|0x100U, kDmaRequestMux0FTM2Channel1 = 31\|0x100U, kDmaRequestMux0TPM2Channel1 = 31\|0x100U, kDmaRequestMux0FTM3Channel0 = 32\|0x100U, kDmaRequestMux0FTM3Channel1 = 33\|0x100U, kDmaRequestMux0FTM3Channel2 = 34\|0x100U, kDmaRequestMux0FTM3Channel3 = 35\|0x100U, kDmaRequestMux0FTM3Channel4 = 36\|0x100U, kDmaRequestMux0FTM3Channel5 = 37\|0x100U, kDmaRequestMux0FTM3Channel6SPI2Rx = 38\|0x100U, kDmaRequestMux0FTM3Channel6 = 38\|0x100U, kDmaRequestMux0SPI2Rx = 38\|0x100U, kDmaRequestMux0FTM3Channel7SPI2Tx = 39\|0x100U, kDmaRequestMux0FTM3Channel7 = 39\|0x100U, kDmaRequestMux0SPI2Tx = 39\|0x100U, kDmaRequestMux0ADC0 = 40\|0x100U, kDmaRequestMux0ADC1 = 41\|0x100U, kDmaRequestMux0CMP0 = 42\|0x100U, kDmaRequestMux0CMP1 = 43\|0x100U, kDmaRequestMux0CMP2CMP3 = 44\|0x100U, kDmaRequestMux0CMP2 = 44\|0x100U, kDmaRequestMux0CMP3 = 44\|0x100U, kDmaRequestMux0DAC0 = 45\|0x100U, kDmaRequestMux0DAC1 = 46\|0x100U, kDmaRequestMux0CMT = 47\|0x100U, kDmaRequestMux0PDB = 48\|0x100U, kDmaRequestMux0PortA = 49\|0x100U, kDmaRequestMux0PortB = 50\|0x100U, kDmaRequestMux0PortC = 51\|0x100U, kDmaRequestMux0PortD = 52\|0x100U, kDmaRequestMux0PortE = 53\|0x100U, kDmaRequestMux0Reserved54 = 54\|0x100U, kDmaRequestMux0TPM1Overflow = 55\|0x100U, kDmaRequestMux0TPM2Overflow = 56\|0x100U, kDmaRequestMux0Reserved57 = 57\|0x100U, kDmaRequestMux0LPUART0Rx = 58\|0x100U, kDmaRequestMux0LPUART0Tx = 59\|0x100U, kDmaRequestMux0AlwaysOn60 = 60\|0x100U, kDmaRequestMux0AlwaysOn61 = 61\|0x100U, kDmaRequestMux0AlwaysOn62 = 62\|0x100U, kDmaRequestMux0AlwaysOn63 = 63\|0x100U, kDmaRequestMux0Disable = 0\|0x100U, kDmaRequestMux0Reserved1 = 1\|0x100U, kDmaRequestMux0UART0Rx = 2\|0x100U, kDmaRequestMux0LPSCI0Rx = 2\|0x100U, kDmaRequestMux0UART0Tx = 3\|0x100U, kDmaRequestMux0LPSCI0Tx = 3\|0x100U, kDmaRequestMux0UART1Rx = 4\|0x100U, kDmaRequestMux0UART1Tx = 5\|0x100U, kDmaRequestMux0UART2Rx = 6\|0x100U, kDmaRequestMux0UART2Tx = 7\|0x100U, kDmaRequestMux0Reserved8 = 8\|0x100U, kDmaRequestMux0Reserved9 = 9\|0x100U, kDmaRequestMux0Reserved10 = 10\|0x100U, kDmaRequestMux0Reserved11 = 11\|0x100U, kDmaRequestMux0Reserved12 = 12\|0x100U, kDmaRequestMux0Reserved13 = 13\|0x100U, kDmaRequestMux0I2S0Rx = 14\|0x100U, kDmaRequestMux0I2S0Tx = 15\|0x100U, kDmaRequestMux0SPI0Rx = 16\|0x100U, kDmaRequestMux0SPI0Tx = 17\|0x100U, kDmaRequestMux0SPI1Rx = 18\|0x100U, kDmaRequestMux0SPI1Tx = 19\|0x100U, kDmaRequestMux0Reserved20 = 20\|0x100U, kDmaRequestMux0Reserved21 = 21\|0x100U, kDmaRequestMux0I2C0 = 22\|0x100U, kDmaRequestMux0I2C1 = 23\|0x100U, kDmaRequestMux0TPM0Channel0 = 24\|0x100U, kDmaRequestMux0TPM0Channel1 = 25\|0x100U, kDmaRequestMux0TPM0Channel2 = 26\|0x100U, kDmaRequestMux0TPM0Channel3 = 27\|0x100U, kDmaRequestMux0TPM0Channel4 = 28\|0x100U, kDmaRequestMux0TPM0Channel5 = 29\|0x100U, kDmaRequestMux0Reserved30 = 30\|0x100U, kDmaRequestMux0Reserved31 = 31\|0x100U, kDmaRequestMux0TPM1Channel0 = 32\|0x100U, kDmaRequestMux0TPM1Channel1 = 33\|0x100U, kDmaRequestMux0TPM2Channel0 = 34\|0x100U, kDmaRequestMux0TPM2Channel1 = 35\|0x100U, kDmaRequestMux0Reserved36 = 36\|0x100U, kDmaRequestMux0Reserved37 = 37\|0x100U, kDmaRequestMux0Reserved38 = 38\|0x100U, kDmaRequestMux0Reserved39 = 39\|0x100U, kDmaRequestMux0ADC0 = 40\|0x100U, kDmaRequestMux0Reserved41 = 41\|0x100U, kDmaRequestMux0CMP0 = 42\|0x100U, kDmaRequestMux0Reserved43 = 43\|0x100U, kDmaRequestMux0Reserved44 = 44\|0x100U, kDmaRequestMux0DAC0 = 45\|0x100U, kDmaRequestMux0Reserved46 = 46\|0x100U, kDmaRequestMux0Reserved47 = 47\|0x100U, kDmaRequestMux0Reserved48 = 48\|0x100U, kDmaRequestMux0PortA = 49\|0x100U, kDmaRequestMux0Reserved50 = 50\|0x100U, kDmaRequestMux0PortC = 51\|0x100U, kDmaRequestMux0PortD = 52\|0x100U, kDmaRequestMux0Reserved53 = 53\|0x100U, kDmaRequestMux0TPM0Overflow = 54\|0x100U, kDmaRequestMux0TPM1Overflow = 55\|0x100U, kDmaRequestMux0TPM2Overflow = 56\|0x100U, kDmaRequestMux0TSI = 57\|0x100U, kDmaRequestMux0Reserved58 = 58\|0x100U, kDmaRequestMux0Reserved59 = 59\|0x100U, kDmaRequestMux0AlwaysOn60 = 60\|0x100U, kDmaRequestMux0AlwaysOn61 = 61\|0x100U, kDmaRequestMux0AlwaysOn62 = 62\|0x100U, kDmaRequestMux0AlwaysOn63 = 63\|0x100U }
	Structure for the DMA hardware request. More...
enum	_dma_request_source { kDmaRequestMux0SoftwareDMARequest = 0\|0x100U, kDmaRequestMux0Reserved1 = 1\|0x100U, kDmaRequestMux0UART0ReceiveDMARequest = 2\|0x100U, kDmaRequestMux0UART0TransmitDMARequest = 3\|0x100U, kDmaRequestMux0UART1ReceiveDMARequest = 4\|0x100U, kDmaRequestMux0UART1TransmitDMARequest = 5\|0x100U, kDmaRequestMux0UART2ReceiveDMARequest = 6\|0x100U, kDmaRequestMux0UART2TransmitDMARequest = 7\|0x100U, kDmaRequestMux0Reserved8 = 8\|0x100U, kDmaRequestMux0Reserved9 = 9\|0x100U, kDmaRequestMux0Reserved10 = 10\|0x100U, kDmaRequestMux0Reserved11 = 11\|0x100U, kDmaRequestMux0Reserved12 = 12\|0x100U, kDmaRequestMux0Reserved13 = 13\|0x100U, kDmaRequestMux0I2S0ReceiveDMARequest = 14\|0x100U, kDmaRequestMux0I2S0TransmitDMARequest = 15\|0x100U, kDmaRequestMux0SPI0ReceiveDMARequest = 16\|0x100U, kDmaRequestMux0SPI0TransmitDMARequest = 17\|0x100U, kDmaRequestMux0Reserved18 = 18\|0x100U, kDmaRequestMux0Reserved19 = 19\|0x100U, kDmaRequestMux0Reserved20 = 20\|0x100U, kDmaRequestMux0Reserved21 = 21\|0x100U, kDmaRequestMux0I2C0DMARequest = 22\|0x100U, kDmaRequestMux0Reserved23 = 23\|0x100U, kDmaRequestMux0FTM0C0DMARequest = 24\|0x100U, kDmaRequestMux0FTM0C1DMARequest = 25\|0x100U, kDmaRequestMux0FTM0C2DMARequest = 26\|0x100U, kDmaRequestMux0FTM0C3DMARequest = 27\|0x100U, kDmaRequestMux0FTM0C4DMARequest = 28\|0x100U, kDmaRequestMux0FTM0C5DMARequest = 29\|0x100U, kDmaRequestMux0FTM0C6DMARequest = 30\|0x100U, kDmaRequestMux0FTM0C7DMARequest = 31\|0x100U, kDmaRequestMux0FTM1C0DMARequest = 32\|0x100U, kDmaRequestMux0FTM1C1DMARequest = 33\|0x100U, kDmaRequestMux0Reserved34 = 34\|0x100U, kDmaRequestMux0Reserved35 = 35\|0x100U, kDmaRequestMux0Reserved36 = 36\|0x100U, kDmaRequestMux0Reserved37 = 37\|0x100U, kDmaRequestMux0Reserved38 = 38\|0x100U, kDmaRequestMux0Reserved39 = 39\|0x100U, kDmaRequestMux0ADC0DMARequest = 40\|0x100U, kDmaRequestMux0Reserved41 = 41\|0x100U, kDmaRequestMux0CMP0DMARequest = 42\|0x100U, kDmaRequestMux0CMP1DMARequest = 43\|0x100U, kDmaRequestMux0Reserved44 = 44\|0x100U, kDmaRequestMux0Reserved45 = 45\|0x100U, kDmaRequestMux0Reserved46 = 46\|0x100U, kDmaRequestMux0CMTDMARequest = 47\|0x100U, kDmaRequestMux0PDBDMARequest = 48\|0x100U, kDmaRequestMux0GPIOPortADMARequest = 49\|0x100U, kDmaRequestMux0GPIOPortBDMARequest = 50\|0x100U, kDmaRequestMux0GPIOPortCDMARequest = 51\|0x100U, kDmaRequestMux0GPIOPortDDMARequest = 52\|0x100U, kDmaRequestMux0GPIOPortEDMARequest = 53\|0x100U, kDmaRequestMux0AlwaysEnabledslot54DMARequest = 54\|0x100U, kDmaRequestMux0AlwaysEnabledslot55DMARequest = 55\|0x100U, kDmaRequestMux0AlwaysEnabledslot56DMARequest = 56\|0x100U, kDmaRequestMux0AlwaysEnabledslot57DMARequest = 57\|0x100U, kDmaRequestMux0AlwaysEnabledslot58DMARequest = 58\|0x100U, kDmaRequestMux0AlwaysEnabledslot59DMARequest = 59\|0x100U, kDmaRequestMux0AlwaysEnabledslot60DMARequest = 60\|0x100U, kDmaRequestMux0AlwaysEnabledslot61DMARequest = 61\|0x100U, kDmaRequestMux0AlwaysEnabledslot62DMARequest = 62\|0x100U, kDmaRequestMux0AlwaysEnabledslot63DMARequest = 63\|0x100U, kDmaRequestMux0Disable = 0\|0x100U, kDmaRequestMux0TSI0 = 1\|0x100U, kDmaRequestMux0UART0Rx = 2\|0x100U, kDmaRequestMux0UART0Tx = 3\|0x100U, kDmaRequestMux0UART1Rx = 4\|0x100U, kDmaRequestMux0UART1Tx = 5\|0x100U, kDmaRequestMux0UART2Rx = 6\|0x100U, kDmaRequestMux0UART2Tx = 7\|0x100U, kDmaRequestMux0UART3Rx = 8\|0x100U, kDmaRequestMux0UART3Tx = 9\|0x100U, kDmaRequestMux0UART4 = 10\|0x100U, kDmaRequestMux0Reserved11 = 11\|0x100U, kDmaRequestMux0I2S0Rx = 12\|0x100U, kDmaRequestMux0I2S0Tx = 13\|0x100U, kDmaRequestMux0SPI0Rx = 14\|0x100U, kDmaRequestMux0SPI0Tx = 15\|0x100U, kDmaRequestMux0SPI1Rx = 16\|0x100U, kDmaRequestMux0SPI1Tx = 17\|0x100U, kDmaRequestMux0I2C0I2C3 = 18\|0x100U, kDmaRequestMux0I2C0 = 18\|0x100U, kDmaRequestMux0I2C3 = 18\|0x100U, kDmaRequestMux0I2C1I2C2 = 19\|0x100U, kDmaRequestMux0I2C1 = 19\|0x100U, kDmaRequestMux0I2C2 = 19\|0x100U, kDmaRequestMux0FTM0Channel0 = 20\|0x100U, kDmaRequestMux0FTM0Channel1 = 21\|0x100U, kDmaRequestMux0FTM0Channel2 = 22\|0x100U, kDmaRequestMux0FTM0Channel3 = 23\|0x100U, kDmaRequestMux0FTM0Channel4 = 24\|0x100U, kDmaRequestMux0FTM0Channel5 = 25\|0x100U, kDmaRequestMux0FTM0Channel6 = 26\|0x100U, kDmaRequestMux0FTM0Channel7 = 27\|0x100U, kDmaRequestMux0FTM1TPM1Channel0 = 28\|0x100U, kDmaRequestMux0FTM1Channel0 = 28\|0x100U, kDmaRequestMux0TPM1Channel0 = 28\|0x100U, kDmaRequestMux0FTM1TPM1Channel1 = 29\|0x100U, kDmaRequestMux0FTM1Channel1 = 29\|0x100U, kDmaRequestMux0TPM1Channel1 = 29\|0x100U, kDmaRequestMux0FTM2TPM2Channel0 = 30\|0x100U, kDmaRequestMux0FTM2Channel0 = 30\|0x100U, kDmaRequestMux0TPM2Channel0 = 30\|0x100U, kDmaRequestMux0FTM2TPM2Channel1 = 31\|0x100U, kDmaRequestMux0FTM2Channel1 = 31\|0x100U, kDmaRequestMux0TPM2Channel1 = 31\|0x100U, kDmaRequestMux0FTM3Channel0 = 32\|0x100U, kDmaRequestMux0FTM3Channel1 = 33\|0x100U, kDmaRequestMux0FTM3Channel2 = 34\|0x100U, kDmaRequestMux0FTM3Channel3 = 35\|0x100U, kDmaRequestMux0FTM3Channel4 = 36\|0x100U, kDmaRequestMux0FTM3Channel5 = 37\|0x100U, kDmaRequestMux0FTM3Channel6SPI2Rx = 38\|0x100U, kDmaRequestMux0FTM3Channel6 = 38\|0x100U, kDmaRequestMux0SPI2Rx = 38\|0x100U, kDmaRequestMux0FTM3Channel7SPI2Tx = 39\|0x100U, kDmaRequestMux0FTM3Channel7 = 39\|0x100U, kDmaRequestMux0SPI2Tx = 39\|0x100U, kDmaRequestMux0ADC0 = 40\|0x100U, kDmaRequestMux0ADC1 = 41\|0x100U, kDmaRequestMux0CMP0 = 42\|0x100U, kDmaRequestMux0CMP1 = 43\|0x100U, kDmaRequestMux0CMP2CMP3 = 44\|0x100U, kDmaRequestMux0CMP2 = 44\|0x100U, kDmaRequestMux0CMP3 = 44\|0x100U, kDmaRequestMux0DAC0 = 45\|0x100U, kDmaRequestMux0DAC1 = 46\|0x100U, kDmaRequestMux0CMT = 47\|0x100U, kDmaRequestMux0PDB = 48\|0x100U, kDmaRequestMux0PortA = 49\|0x100U, kDmaRequestMux0PortB = 50\|0x100U, kDmaRequestMux0PortC = 51\|0x100U, kDmaRequestMux0PortD = 52\|0x100U, kDmaRequestMux0PortE = 53\|0x100U, kDmaRequestMux0Reserved54 = 54\|0x100U, kDmaRequestMux0TPM1Overflow = 55\|0x100U, kDmaRequestMux0TPM2Overflow = 56\|0x100U, kDmaRequestMux0Reserved57 = 57\|0x100U, kDmaRequestMux0LPUART0Rx = 58\|0x100U, kDmaRequestMux0LPUART0Tx = 59\|0x100U, kDmaRequestMux0AlwaysOn60 = 60\|0x100U, kDmaRequestMux0AlwaysOn61 = 61\|0x100U, kDmaRequestMux0AlwaysOn62 = 62\|0x100U, kDmaRequestMux0AlwaysOn63 = 63\|0x100U, kDmaRequestMux0Disable = 0\|0x100U, kDmaRequestMux0Reserved1 = 1\|0x100U, kDmaRequestMux0UART0Rx = 2\|0x100U, kDmaRequestMux0LPSCI0Rx = 2\|0x100U, kDmaRequestMux0UART0Tx = 3\|0x100U, kDmaRequestMux0LPSCI0Tx = 3\|0x100U, kDmaRequestMux0UART1Rx = 4\|0x100U, kDmaRequestMux0UART1Tx = 5\|0x100U, kDmaRequestMux0UART2Rx = 6\|0x100U, kDmaRequestMux0UART2Tx = 7\|0x100U, kDmaRequestMux0Reserved8 = 8\|0x100U, kDmaRequestMux0Reserved9 = 9\|0x100U, kDmaRequestMux0Reserved10 = 10\|0x100U, kDmaRequestMux0Reserved11 = 11\|0x100U, kDmaRequestMux0Reserved12 = 12\|0x100U, kDmaRequestMux0Reserved13 = 13\|0x100U, kDmaRequestMux0I2S0Rx = 14\|0x100U, kDmaRequestMux0I2S0Tx = 15\|0x100U, kDmaRequestMux0SPI0Rx = 16\|0x100U, kDmaRequestMux0SPI0Tx = 17\|0x100U, kDmaRequestMux0SPI1Rx = 18\|0x100U, kDmaRequestMux0SPI1Tx = 19\|0x100U, kDmaRequestMux0Reserved20 = 20\|0x100U, kDmaRequestMux0Reserved21 = 21\|0x100U, kDmaRequestMux0I2C0 = 22\|0x100U, kDmaRequestMux0I2C1 = 23\|0x100U, kDmaRequestMux0TPM0Channel0 = 24\|0x100U, kDmaRequestMux0TPM0Channel1 = 25\|0x100U, kDmaRequestMux0TPM0Channel2 = 26\|0x100U, kDmaRequestMux0TPM0Channel3 = 27\|0x100U, kDmaRequestMux0TPM0Channel4 = 28\|0x100U, kDmaRequestMux0TPM0Channel5 = 29\|0x100U, kDmaRequestMux0Reserved30 = 30\|0x100U, kDmaRequestMux0Reserved31 = 31\|0x100U, kDmaRequestMux0TPM1Channel0 = 32\|0x100U, kDmaRequestMux0TPM1Channel1 = 33\|0x100U, kDmaRequestMux0TPM2Channel0 = 34\|0x100U, kDmaRequestMux0TPM2Channel1 = 35\|0x100U, kDmaRequestMux0Reserved36 = 36\|0x100U, kDmaRequestMux0Reserved37 = 37\|0x100U, kDmaRequestMux0Reserved38 = 38\|0x100U, kDmaRequestMux0Reserved39 = 39\|0x100U, kDmaRequestMux0ADC0 = 40\|0x100U, kDmaRequestMux0Reserved41 = 41\|0x100U, kDmaRequestMux0CMP0 = 42\|0x100U, kDmaRequestMux0Reserved43 = 43\|0x100U, kDmaRequestMux0Reserved44 = 44\|0x100U, kDmaRequestMux0DAC0 = 45\|0x100U, kDmaRequestMux0Reserved46 = 46\|0x100U, kDmaRequestMux0Reserved47 = 47\|0x100U, kDmaRequestMux0Reserved48 = 48\|0x100U, kDmaRequestMux0PortA = 49\|0x100U, kDmaRequestMux0Reserved50 = 50\|0x100U, kDmaRequestMux0PortC = 51\|0x100U, kDmaRequestMux0PortD = 52\|0x100U, kDmaRequestMux0Reserved53 = 53\|0x100U, kDmaRequestMux0TPM0Overflow = 54\|0x100U, kDmaRequestMux0TPM1Overflow = 55\|0x100U, kDmaRequestMux0TPM2Overflow = 56\|0x100U, kDmaRequestMux0TSI = 57\|0x100U, kDmaRequestMux0Reserved58 = 58\|0x100U, kDmaRequestMux0Reserved59 = 59\|0x100U, kDmaRequestMux0AlwaysOn60 = 60\|0x100U, kDmaRequestMux0AlwaysOn61 = 61\|0x100U, kDmaRequestMux0AlwaysOn62 = 62\|0x100U, kDmaRequestMux0AlwaysOn63 = 63\|0x100U }
	Structure for the DMA hardware request. More...
enum	_dma_request_source { kDmaRequestMux0SoftwareDMARequest = 0\|0x100U, kDmaRequestMux0Reserved1 = 1\|0x100U, kDmaRequestMux0UART0ReceiveDMARequest = 2\|0x100U, kDmaRequestMux0UART0TransmitDMARequest = 3\|0x100U, kDmaRequestMux0UART1ReceiveDMARequest = 4\|0x100U, kDmaRequestMux0UART1TransmitDMARequest = 5\|0x100U, kDmaRequestMux0UART2ReceiveDMARequest = 6\|0x100U, kDmaRequestMux0UART2TransmitDMARequest = 7\|0x100U, kDmaRequestMux0Reserved8 = 8\|0x100U, kDmaRequestMux0Reserved9 = 9\|0x100U, kDmaRequestMux0Reserved10 = 10\|0x100U, kDmaRequestMux0Reserved11 = 11\|0x100U, kDmaRequestMux0Reserved12 = 12\|0x100U, kDmaRequestMux0Reserved13 = 13\|0x100U, kDmaRequestMux0I2S0ReceiveDMARequest = 14\|0x100U, kDmaRequestMux0I2S0TransmitDMARequest = 15\|0x100U, kDmaRequestMux0SPI0ReceiveDMARequest = 16\|0x100U, kDmaRequestMux0SPI0TransmitDMARequest = 17\|0x100U, kDmaRequestMux0Reserved18 = 18\|0x100U, kDmaRequestMux0Reserved19 = 19\|0x100U, kDmaRequestMux0Reserved20 = 20\|0x100U, kDmaRequestMux0Reserved21 = 21\|0x100U, kDmaRequestMux0I2C0DMARequest = 22\|0x100U, kDmaRequestMux0Reserved23 = 23\|0x100U, kDmaRequestMux0FTM0C0DMARequest = 24\|0x100U, kDmaRequestMux0FTM0C1DMARequest = 25\|0x100U, kDmaRequestMux0FTM0C2DMARequest = 26\|0x100U, kDmaRequestMux0FTM0C3DMARequest = 27\|0x100U, kDmaRequestMux0FTM0C4DMARequest = 28\|0x100U, kDmaRequestMux0FTM0C5DMARequest = 29\|0x100U, kDmaRequestMux0FTM0C6DMARequest = 30\|0x100U, kDmaRequestMux0FTM0C7DMARequest = 31\|0x100U, kDmaRequestMux0FTM1C0DMARequest = 32\|0x100U, kDmaRequestMux0FTM1C1DMARequest = 33\|0x100U, kDmaRequestMux0Reserved34 = 34\|0x100U, kDmaRequestMux0Reserved35 = 35\|0x100U, kDmaRequestMux0Reserved36 = 36\|0x100U, kDmaRequestMux0Reserved37 = 37\|0x100U, kDmaRequestMux0Reserved38 = 38\|0x100U, kDmaRequestMux0Reserved39 = 39\|0x100U, kDmaRequestMux0ADC0DMARequest = 40\|0x100U, kDmaRequestMux0Reserved41 = 41\|0x100U, kDmaRequestMux0CMP0DMARequest = 42\|0x100U, kDmaRequestMux0CMP1DMARequest = 43\|0x100U, kDmaRequestMux0Reserved44 = 44\|0x100U, kDmaRequestMux0Reserved45 = 45\|0x100U, kDmaRequestMux0Reserved46 = 46\|0x100U, kDmaRequestMux0CMTDMARequest = 47\|0x100U, kDmaRequestMux0PDBDMARequest = 48\|0x100U, kDmaRequestMux0GPIOPortADMARequest = 49\|0x100U, kDmaRequestMux0GPIOPortBDMARequest = 50\|0x100U, kDmaRequestMux0GPIOPortCDMARequest = 51\|0x100U, kDmaRequestMux0GPIOPortDDMARequest = 52\|0x100U, kDmaRequestMux0GPIOPortEDMARequest = 53\|0x100U, kDmaRequestMux0AlwaysEnabledslot54DMARequest = 54\|0x100U, kDmaRequestMux0AlwaysEnabledslot55DMARequest = 55\|0x100U, kDmaRequestMux0AlwaysEnabledslot56DMARequest = 56\|0x100U, kDmaRequestMux0AlwaysEnabledslot57DMARequest = 57\|0x100U, kDmaRequestMux0AlwaysEnabledslot58DMARequest = 58\|0x100U, kDmaRequestMux0AlwaysEnabledslot59DMARequest = 59\|0x100U, kDmaRequestMux0AlwaysEnabledslot60DMARequest = 60\|0x100U, kDmaRequestMux0AlwaysEnabledslot61DMARequest = 61\|0x100U, kDmaRequestMux0AlwaysEnabledslot62DMARequest = 62\|0x100U, kDmaRequestMux0AlwaysEnabledslot63DMARequest = 63\|0x100U, kDmaRequestMux0Disable = 0\|0x100U, kDmaRequestMux0TSI0 = 1\|0x100U, kDmaRequestMux0UART0Rx = 2\|0x100U, kDmaRequestMux0UART0Tx = 3\|0x100U, kDmaRequestMux0UART1Rx = 4\|0x100U, kDmaRequestMux0UART1Tx = 5\|0x100U, kDmaRequestMux0UART2Rx = 6\|0x100U, kDmaRequestMux0UART2Tx = 7\|0x100U, kDmaRequestMux0UART3Rx = 8\|0x100U, kDmaRequestMux0UART3Tx = 9\|0x100U, kDmaRequestMux0UART4 = 10\|0x100U, kDmaRequestMux0Reserved11 = 11\|0x100U, kDmaRequestMux0I2S0Rx = 12\|0x100U, kDmaRequestMux0I2S0Tx = 13\|0x100U, kDmaRequestMux0SPI0Rx = 14\|0x100U, kDmaRequestMux0SPI0Tx = 15\|0x100U, kDmaRequestMux0SPI1Rx = 16\|0x100U, kDmaRequestMux0SPI1Tx = 17\|0x100U, kDmaRequestMux0I2C0I2C3 = 18\|0x100U, kDmaRequestMux0I2C0 = 18\|0x100U, kDmaRequestMux0I2C3 = 18\|0x100U, kDmaRequestMux0I2C1I2C2 = 19\|0x100U, kDmaRequestMux0I2C1 = 19\|0x100U, kDmaRequestMux0I2C2 = 19\|0x100U, kDmaRequestMux0FTM0Channel0 = 20\|0x100U, kDmaRequestMux0FTM0Channel1 = 21\|0x100U, kDmaRequestMux0FTM0Channel2 = 22\|0x100U, kDmaRequestMux0FTM0Channel3 = 23\|0x100U, kDmaRequestMux0FTM0Channel4 = 24\|0x100U, kDmaRequestMux0FTM0Channel5 = 25\|0x100U, kDmaRequestMux0FTM0Channel6 = 26\|0x100U, kDmaRequestMux0FTM0Channel7 = 27\|0x100U, kDmaRequestMux0FTM1TPM1Channel0 = 28\|0x100U, kDmaRequestMux0FTM1Channel0 = 28\|0x100U, kDmaRequestMux0TPM1Channel0 = 28\|0x100U, kDmaRequestMux0FTM1TPM1Channel1 = 29\|0x100U, kDmaRequestMux0FTM1Channel1 = 29\|0x100U, kDmaRequestMux0TPM1Channel1 = 29\|0x100U, kDmaRequestMux0FTM2TPM2Channel0 = 30\|0x100U, kDmaRequestMux0FTM2Channel0 = 30\|0x100U, kDmaRequestMux0TPM2Channel0 = 30\|0x100U, kDmaRequestMux0FTM2TPM2Channel1 = 31\|0x100U, kDmaRequestMux0FTM2Channel1 = 31\|0x100U, kDmaRequestMux0TPM2Channel1 = 31\|0x100U, kDmaRequestMux0FTM3Channel0 = 32\|0x100U, kDmaRequestMux0FTM3Channel1 = 33\|0x100U, kDmaRequestMux0FTM3Channel2 = 34\|0x100U, kDmaRequestMux0FTM3Channel3 = 35\|0x100U, kDmaRequestMux0FTM3Channel4 = 36\|0x100U, kDmaRequestMux0FTM3Channel5 = 37\|0x100U, kDmaRequestMux0FTM3Channel6SPI2Rx = 38\|0x100U, kDmaRequestMux0FTM3Channel6 = 38\|0x100U, kDmaRequestMux0SPI2Rx = 38\|0x100U, kDmaRequestMux0FTM3Channel7SPI2Tx = 39\|0x100U, kDmaRequestMux0FTM3Channel7 = 39\|0x100U, kDmaRequestMux0SPI2Tx = 39\|0x100U, kDmaRequestMux0ADC0 = 40\|0x100U, kDmaRequestMux0ADC1 = 41\|0x100U, kDmaRequestMux0CMP0 = 42\|0x100U, kDmaRequestMux0CMP1 = 43\|0x100U, kDmaRequestMux0CMP2CMP3 = 44\|0x100U, kDmaRequestMux0CMP2 = 44\|0x100U, kDmaRequestMux0CMP3 = 44\|0x100U, kDmaRequestMux0DAC0 = 45\|0x100U, kDmaRequestMux0DAC1 = 46\|0x100U, kDmaRequestMux0CMT = 47\|0x100U, kDmaRequestMux0PDB = 48\|0x100U, kDmaRequestMux0PortA = 49\|0x100U, kDmaRequestMux0PortB = 50\|0x100U, kDmaRequestMux0PortC = 51\|0x100U, kDmaRequestMux0PortD = 52\|0x100U, kDmaRequestMux0PortE = 53\|0x100U, kDmaRequestMux0Reserved54 = 54\|0x100U, kDmaRequestMux0TPM1Overflow = 55\|0x100U, kDmaRequestMux0TPM2Overflow = 56\|0x100U, kDmaRequestMux0Reserved57 = 57\|0x100U, kDmaRequestMux0LPUART0Rx = 58\|0x100U, kDmaRequestMux0LPUART0Tx = 59\|0x100U, kDmaRequestMux0AlwaysOn60 = 60\|0x100U, kDmaRequestMux0AlwaysOn61 = 61\|0x100U, kDmaRequestMux0AlwaysOn62 = 62\|0x100U, kDmaRequestMux0AlwaysOn63 = 63\|0x100U, kDmaRequestMux0Disable = 0\|0x100U, kDmaRequestMux0Reserved1 = 1\|0x100U, kDmaRequestMux0UART0Rx = 2\|0x100U, kDmaRequestMux0LPSCI0Rx = 2\|0x100U, kDmaRequestMux0UART0Tx = 3\|0x100U, kDmaRequestMux0LPSCI0Tx = 3\|0x100U, kDmaRequestMux0UART1Rx = 4\|0x100U, kDmaRequestMux0UART1Tx = 5\|0x100U, kDmaRequestMux0UART2Rx = 6\|0x100U, kDmaRequestMux0UART2Tx = 7\|0x100U, kDmaRequestMux0Reserved8 = 8\|0x100U, kDmaRequestMux0Reserved9 = 9\|0x100U, kDmaRequestMux0Reserved10 = 10\|0x100U, kDmaRequestMux0Reserved11 = 11\|0x100U, kDmaRequestMux0Reserved12 = 12\|0x100U, kDmaRequestMux0Reserved13 = 13\|0x100U, kDmaRequestMux0I2S0Rx = 14\|0x100U, kDmaRequestMux0I2S0Tx = 15\|0x100U, kDmaRequestMux0SPI0Rx = 16\|0x100U, kDmaRequestMux0SPI0Tx = 17\|0x100U, kDmaRequestMux0SPI1Rx = 18\|0x100U, kDmaRequestMux0SPI1Tx = 19\|0x100U, kDmaRequestMux0Reserved20 = 20\|0x100U, kDmaRequestMux0Reserved21 = 21\|0x100U, kDmaRequestMux0I2C0 = 22\|0x100U, kDmaRequestMux0I2C1 = 23\|0x100U, kDmaRequestMux0TPM0Channel0 = 24\|0x100U, kDmaRequestMux0TPM0Channel1 = 25\|0x100U, kDmaRequestMux0TPM0Channel2 = 26\|0x100U, kDmaRequestMux0TPM0Channel3 = 27\|0x100U, kDmaRequestMux0TPM0Channel4 = 28\|0x100U, kDmaRequestMux0TPM0Channel5 = 29\|0x100U, kDmaRequestMux0Reserved30 = 30\|0x100U, kDmaRequestMux0Reserved31 = 31\|0x100U, kDmaRequestMux0TPM1Channel0 = 32\|0x100U, kDmaRequestMux0TPM1Channel1 = 33\|0x100U, kDmaRequestMux0TPM2Channel0 = 34\|0x100U, kDmaRequestMux0TPM2Channel1 = 35\|0x100U, kDmaRequestMux0Reserved36 = 36\|0x100U, kDmaRequestMux0Reserved37 = 37\|0x100U, kDmaRequestMux0Reserved38 = 38\|0x100U, kDmaRequestMux0Reserved39 = 39\|0x100U, kDmaRequestMux0ADC0 = 40\|0x100U, kDmaRequestMux0Reserved41 = 41\|0x100U, kDmaRequestMux0CMP0 = 42\|0x100U, kDmaRequestMux0Reserved43 = 43\|0x100U, kDmaRequestMux0Reserved44 = 44\|0x100U, kDmaRequestMux0DAC0 = 45\|0x100U, kDmaRequestMux0Reserved46 = 46\|0x100U, kDmaRequestMux0Reserved47 = 47\|0x100U, kDmaRequestMux0Reserved48 = 48\|0x100U, kDmaRequestMux0PortA = 49\|0x100U, kDmaRequestMux0Reserved50 = 50\|0x100U, kDmaRequestMux0PortC = 51\|0x100U, kDmaRequestMux0PortD = 52\|0x100U, kDmaRequestMux0Reserved53 = 53\|0x100U, kDmaRequestMux0TPM0Overflow = 54\|0x100U, kDmaRequestMux0TPM1Overflow = 55\|0x100U, kDmaRequestMux0TPM2Overflow = 56\|0x100U, kDmaRequestMux0TSI = 57\|0x100U, kDmaRequestMux0Reserved58 = 58\|0x100U, kDmaRequestMux0Reserved59 = 59\|0x100U, kDmaRequestMux0AlwaysOn60 = 60\|0x100U, kDmaRequestMux0AlwaysOn61 = 61\|0x100U, kDmaRequestMux0AlwaysOn62 = 62\|0x100U, kDmaRequestMux0AlwaysOn63 = 63\|0x100U }
	Structure for the DMA hardware request. More...

Detailed Description

Mapping Information.