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I2S_Type Struct Reference
[I2S Peripheral Access Layer]
I2S - Register Layout Typedef. More...
#include <MK20D5.h>
Data Fields | |
| __IO uint32_t | TCSR |
| SAI Transmit Control Register, offset: 0x0. | |
| __IO uint32_t | TCR1 |
| SAI Transmit Configuration 1 Register, offset: 0x4. | |
| __IO uint32_t | TCR2 |
| SAI Transmit Configuration 2 Register, offset: 0x8. | |
| __IO uint32_t | TCR3 |
| SAI Transmit Configuration 3 Register, offset: 0xC. | |
| __IO uint32_t | TCR4 |
| SAI Transmit Configuration 4 Register, offset: 0x10. | |
| __IO uint32_t | TCR5 |
| SAI Transmit Configuration 5 Register, offset: 0x14. | |
| __O uint32_t | TDR [2] |
| SAI Transmit Data Register, array offset: 0x20, array step: 0x4. | |
| __I uint32_t | TFR [2] |
| SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4. | |
| __IO uint32_t | TMR |
| SAI Transmit Mask Register, offset: 0x60. | |
| __IO uint32_t | RCSR |
| SAI Receive Control Register, offset: 0x80. | |
| __IO uint32_t | RCR1 |
| SAI Receive Configuration 1 Register, offset: 0x84. | |
| __IO uint32_t | RCR2 |
| SAI Receive Configuration 2 Register, offset: 0x88. | |
| __IO uint32_t | RCR3 |
| SAI Receive Configuration 3 Register, offset: 0x8C. | |
| __IO uint32_t | RCR4 |
| SAI Receive Configuration 4 Register, offset: 0x90. | |
| __IO uint32_t | RCR5 |
| SAI Receive Configuration 5 Register, offset: 0x94. | |
| __I uint32_t | RDR [2] |
| SAI Receive Data Register, array offset: 0xA0, array step: 0x4. | |
| __I uint32_t | RFR [2] |
| SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4. | |
| __IO uint32_t | RMR |
| SAI Receive Mask Register, offset: 0xE0. | |
| __IO uint32_t | MCR |
| SAI MCLK Control Register, offset: 0x100. | |
| __IO uint32_t | MDR |
| MCLK Divide Register, offset: 0x104. | |
Detailed Description
I2S - Register Layout Typedef.
Definition at line 3154 of file MK20D5.h.
Field Documentation
Generated on Tue Jul 12 2022 15:37:37 by
1.7.2