Mark Underwood / Mbed OS MAX11043_Serial_Tester

Test program running on MAX32625MBED. Control through USB Serial commands using a terminal emulator such as teraterm or putty.

Dependencies:   MaximTinyTester CmdLine MAX541 USBDevice

MAX11043/MAX11043.cpp@91:9e78c6194d6e, 2020-03-02 (annotated)

Committer:
whismanoid
Date:
Mon Mar 02 11:47:44 2020 +0000
Revision:
91:9e78c6194d6e
Parent:
90:d6ed8a8c5f26
Child:
93:6b22269935a6
update adca as 2's complement

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 53:3d5a3d241a5e 1 // /*******************************************************************************
whismanoid 53:3d5a3d241a5e 2 // * Copyright (C) 2020 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 53:3d5a3d241a5e 3 // *
whismanoid 53:3d5a3d241a5e 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 53:3d5a3d241a5e 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 53:3d5a3d241a5e 6 // * to deal in the Software without restriction, including without limitation
whismanoid 53:3d5a3d241a5e 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 53:3d5a3d241a5e 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 53:3d5a3d241a5e 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 53:3d5a3d241a5e 10 // *
whismanoid 53:3d5a3d241a5e 11 // * The above copyright notice and this permission notice shall be included
whismanoid 53:3d5a3d241a5e 12 // * in all copies or substantial portions of the Software.
whismanoid 53:3d5a3d241a5e 13 // *
whismanoid 53:3d5a3d241a5e 14 // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid 53:3d5a3d241a5e 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 53:3d5a3d241a5e 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 53:3d5a3d241a5e 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 53:3d5a3d241a5e 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 53:3d5a3d241a5e 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 53:3d5a3d241a5e 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 53:3d5a3d241a5e 21 // *
whismanoid 53:3d5a3d241a5e 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 53:3d5a3d241a5e 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 53:3d5a3d241a5e 24 // * Products, Inc. Branding Policy.
whismanoid 53:3d5a3d241a5e 25 // *
whismanoid 53:3d5a3d241a5e 26 // * The mere transfer of this software does not imply any licenses
whismanoid 53:3d5a3d241a5e 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 53:3d5a3d241a5e 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 53:3d5a3d241a5e 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 53:3d5a3d241a5e 30 // * ownership rights.
whismanoid 53:3d5a3d241a5e 31 // *******************************************************************************
whismanoid 53:3d5a3d241a5e 32 // */
whismanoid 53:3d5a3d241a5e 33 // *********************************************************************
whismanoid 53:3d5a3d241a5e 34 // @file MAX11043.cpp
whismanoid 53:3d5a3d241a5e 35 // *********************************************************************
whismanoid 53:3d5a3d241a5e 36 // Device Driver file
whismanoid 83:29bb86cc45bc 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file. * MANUAL EDITS PRESENT *
whismanoid 53:3d5a3d241a5e 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 53:3d5a3d241a5e 39 // System Name = ExampleSystem
whismanoid 53:3d5a3d241a5e 40 // System Description = Device driver example
whismanoid 53:3d5a3d241a5e 41
whismanoid 53:3d5a3d241a5e 42 #include "MAX11043.h"
whismanoid 69:989e392cf635 43 //--------------------------------------------------
whismanoid 69:989e392cf635 44 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 45 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 46 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 47 #ifndef MAX11043_EOC_INTERRUPT_POLLING
whismanoid 81:167dee56c45b 48 #define MAX11043_EOC_INTERRUPT_POLLING 1
whismanoid 69:989e392cf635 49 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 73:879578472009 50 //--------------------------------------------------
whismanoid 76:0397493d7baf 51 // SPI is not interrupt-safe, so use EventQueue to defer execution to user context.
whismanoid 76:0397493d7baf 52 #ifndef MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 83:29bb86cc45bc 53 #define MAX11043_EOC_INTERRUPT_EVENTQUEUE 0
whismanoid 76:0397493d7baf 54 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 55 #if MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 56 #else // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 57 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 58 #if MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 59 // SPI is not interrupt-safe, so use EventQueue to defer execution to user context.
whismanoid 76:0397493d7baf 60 #include "mbed_events.h"
whismanoid 76:0397493d7baf 61 #define MYONEOCTHREADEVENTFLAG_ENABLE_SPI (1UL << 0)
whismanoid 76:0397493d7baf 62 EventFlags myOnEOCThread_event_flags;
whismanoid 76:0397493d7baf 63 Thread myOnEOCThread;
whismanoid 82:9ea067fad5c3 64 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 82:9ea067fad5c3 65 // MAX11043 myOnEOCThread_POLLING_handler needs 18.80us, still too slow
whismanoid 82:9ea067fad5c3 66 extern DigitalInOut digitalInOut2; // m_EOC_pin declared in Test_Main_MAX11043.cpp
whismanoid 82:9ea067fad5c3 67 extern void myOnEOCThread_POLLING_handler();
whismanoid 82:9ea067fad5c3 68 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 82:9ea067fad5c3 69 extern void myOnEOCThread_EVENTFLAG_ENABLE_SPI_handler();
whismanoid 82:9ea067fad5c3 70 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 76:0397493d7baf 71 #else // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 72 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 73 //--------------------------------------------------
whismanoid 73:879578472009 74 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 73:879578472009 75 #ifndef MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 76 #define MAX11043_ScopeTrigger_MAX32625MBED_D5 1
whismanoid 73:879578472009 77 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 78 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 79 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 73:879578472009 80 // WIP MAX11043 interrupt EOC echo - moving DigitalOut ScopeTrigger to global scope, it compiles but there is no activity on scope
whismanoid 74:f4f969c9a7a9 81 extern DigitalInOut digitalInOut5; // declared in Test_Main_MAX11043.cpp (D5, PIN_INPUT, PullUp, 1)
whismanoid 75:0900a57f2e5d 82 const size_t byteCount_onEOCFallingEdge = 1 + (2 * 4);
whismanoid 75:0900a57f2e5d 83 const uint8_t mosiData_onEOCFallingEdge[9] = {
whismanoid 75:0900a57f2e5d 84 MAX11043::CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd,
whismanoid 75:0900a57f2e5d 85 0, 0, 0, 0, 0, 0, 0, 0
whismanoid 75:0900a57f2e5d 86 };
whismanoid 75:0900a57f2e5d 87 uint8_t misoData_onEOCFallingEdge[9];
whismanoid 73:879578472009 88 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 53:3d5a3d241a5e 89
whismanoid 53:3d5a3d241a5e 90 // Device Name = MAX11043
whismanoid 53:3d5a3d241a5e 91 // Device Description = 200ksps, Low-Power, Serial SPI 24-Bit, 4-Channel, Differential/Single-Ended Input, Simultaneous-Sampling SD ADC
whismanoid 53:3d5a3d241a5e 92 // Device DeviceBriefDescription = 24-bit 200ksps Delta-Sigma ADC
whismanoid 53:3d5a3d241a5e 93 // Device Manufacturer = Maxim Integrated
whismanoid 53:3d5a3d241a5e 94 // Device PartNumber = MAX11043ATL+
whismanoid 53:3d5a3d241a5e 95 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 53:3d5a3d241a5e 96 //
whismanoid 53:3d5a3d241a5e 97 // ADC MaxOutputDataRate = 200ksps
whismanoid 53:3d5a3d241a5e 98 // ADC NumChannels = 4
whismanoid 53:3d5a3d241a5e 99 // ADC ResolutionBits = 24
whismanoid 53:3d5a3d241a5e 100 //
whismanoid 53:3d5a3d241a5e 101 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 102 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 103 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 104 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 105 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 106 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 107 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 108 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 109 //
whismanoid 53:3d5a3d241a5e 110 // InputPin Name = CONVRUN
whismanoid 53:3d5a3d241a5e 111 // InputPin Description = CONVRUN (digital input). Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 53:3d5a3d241a5e 112 // CONVRUN is low.
whismanoid 53:3d5a3d241a5e 113 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 114 //
whismanoid 53:3d5a3d241a5e 115 // InputPin Name = SHDN
whismanoid 53:3d5a3d241a5e 116 // InputPin Description = Shutdown (digital input). Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 53:3d5a3d241a5e 117 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 118 //
whismanoid 53:3d5a3d241a5e 119 // InputPin Name = DACSTEP
whismanoid 53:3d5a3d241a5e 120 // InputPin Description = DACSTEP (digital input). DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 53:3d5a3d241a5e 121 // edge of the system clock.
whismanoid 53:3d5a3d241a5e 122 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 123 //
whismanoid 53:3d5a3d241a5e 124 // InputPin Name = UP/DWN#
whismanoid 53:3d5a3d241a5e 125 // InputPin Description = UP/DWN# (digital input). DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 53:3d5a3d241a5e 126 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 127 //
whismanoid 53:3d5a3d241a5e 128 // OutputPin Name = EOC
whismanoid 53:3d5a3d241a5e 129 // OutputPin Description = End of Conversion Output. Active-Low End-of-Conversion Indicator. EOC asserts low to indicate that new data is ready.
whismanoid 53:3d5a3d241a5e 130 // OutputPin Function = Event
whismanoid 53:3d5a3d241a5e 131 //
whismanoid 58:2fea32db466b 132 // SupplyPin Name = AVDD
whismanoid 58:2fea32db466b 133 // SupplyPin Description = Analog Power-Supply Input. Bypass each AVDD with a nominal 1uF capacitor to AGND.
whismanoid 58:2fea32db466b 134 // SupplyPin VinMax = 3.60
whismanoid 58:2fea32db466b 135 // SupplyPin VinMin = 3.00
whismanoid 58:2fea32db466b 136 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 137 //
whismanoid 58:2fea32db466b 138 // SupplyPin Name = AGND
whismanoid 58:2fea32db466b 139 // SupplyPin Description = Analog Ground. Connect all AGND inputs together.
whismanoid 58:2fea32db466b 140 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 141 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 142 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 143 //
whismanoid 58:2fea32db466b 144 // SupplyPin Name = DGND
whismanoid 58:2fea32db466b 145 // SupplyPin Description = Digital Ground. Connect all DGND inputs together.
whismanoid 58:2fea32db466b 146 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 147 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 148 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 149 //
whismanoid 58:2fea32db466b 150 // SupplyPin Name = DVDD
whismanoid 58:2fea32db466b 151 // SupplyPin Description = Digital Power-Supply Input. Bypass each DVDD with a nominal 1uF capacitor to DGND.
whismanoid 83:29bb86cc45bc 152 // SupplyPin VinMax = 3.60
whismanoid 83:29bb86cc45bc 153 // SupplyPin VinMin = 3.00
whismanoid 58:2fea32db466b 154 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 155 //
whismanoid 58:2fea32db466b 156 // SupplyPin Name = DVREG
whismanoid 58:2fea32db466b 157 // SupplyPin Description = Regulated Digital Core Supply (from internal +2.5V regulator). Bypass DVREG to DGND with a 10uF capacitor.
whismanoid 58:2fea32db466b 158 // SupplyPin VinMax = 2.50
whismanoid 58:2fea32db466b 159 // SupplyPin VinMin = 2.50
whismanoid 58:2fea32db466b 160 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 161 //
whismanoid 53:3d5a3d241a5e 162
whismanoid 53:3d5a3d241a5e 163 // CODE GENERATOR: class constructor definition
whismanoid 53:3d5a3d241a5e 164 MAX11043::MAX11043(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 53:3d5a3d241a5e 165 // CODE GENERATOR: class constructor definition gpio InputPin pins
whismanoid 53:3d5a3d241a5e 166 DigitalOut &CONVRUN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 167 DigitalOut &SHDN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 168 DigitalOut &DACSTEP_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 169 DigitalOut &UP_slash_DWNb_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 170 // CODE GENERATOR: class constructor definition gpio OutputPin pins
whismanoid 69:989e392cf635 171 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 172 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 173 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 174 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 175 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 53:3d5a3d241a5e 176 DigitalIn &EOC_pin, // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 177 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 178 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 179 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 69:989e392cf635 180 InterruptIn &EOC_pin, // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 181 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 182 // CODE GENERATOR: class constructor definition ic_variant
whismanoid 53:3d5a3d241a5e 183 MAX11043_ic_t ic_variant)
whismanoid 53:3d5a3d241a5e 184 // CODE GENERATOR: class constructor initializer list
whismanoid 53:3d5a3d241a5e 185 : m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid 53:3d5a3d241a5e 186 // CODE GENERATOR: class constructor initializer list gpio InputPin pins
whismanoid 53:3d5a3d241a5e 187 m_CONVRUN_pin(CONVRUN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 188 m_SHDN_pin(SHDN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 189 m_DACSTEP_pin(DACSTEP_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 190 m_UP_slash_DWNb_pin(UP_slash_DWNb_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 191 // CODE GENERATOR: class constructor initializer list gpio OutputPin pins
whismanoid 69:989e392cf635 192 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 193 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 194 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 195 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 53:3d5a3d241a5e 196 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 197 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 198 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 70:f44a577c9e59 199 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 200 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 201 // CODE GENERATOR: class constructor initializer list ic_variant
whismanoid 53:3d5a3d241a5e 202 m_ic_variant(ic_variant)
whismanoid 53:3d5a3d241a5e 203 {
whismanoid 53:3d5a3d241a5e 204 // CODE GENERATOR: class constructor definition SPI interface initialization
whismanoid 53:3d5a3d241a5e 205 //
whismanoid 53:3d5a3d241a5e 206 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 207 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 208 m_SPI_cs_state = 1;
whismanoid 67:5b8a495dda1c 209 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 210 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 211 }
whismanoid 53:3d5a3d241a5e 212
whismanoid 53:3d5a3d241a5e 213 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 214 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 215 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 216 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 217 m_SPI_dataMode = 0; //SPI_MODE0; // CPOL=0,CPHA=0: Rising Edge stable; SCLK idle Low
whismanoid 53:3d5a3d241a5e 218 m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid 53:3d5a3d241a5e 219
whismanoid 53:3d5a3d241a5e 220 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 221 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 222 //#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid 53:3d5a3d241a5e 223 //#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid 53:3d5a3d241a5e 224 //#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid 53:3d5a3d241a5e 225 //#define SPI_SCLK_Hz 6000000 // 6MHz
whismanoid 53:3d5a3d241a5e 226 //#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid 53:3d5a3d241a5e 227 //#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid 53:3d5a3d241a5e 228 //#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid 61:b4f3051578ef 229 m_SPI_SCLK_Hz = 24000000; // platform limit 24MHz; MAX11043 limit is 40MHz
whismanoid 53:3d5a3d241a5e 230 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 231
whismanoid 53:3d5a3d241a5e 232 //
whismanoid 53:3d5a3d241a5e 233 // CODE GENERATOR: class constructor definition gpio InputPin (Input to device) initialization
whismanoid 53:3d5a3d241a5e 234 //
whismanoid 53:3d5a3d241a5e 235 // CONVRUN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 236 m_CONVRUN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 237 //
whismanoid 53:3d5a3d241a5e 238 // SHDN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 239 m_SHDN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 240 //
whismanoid 53:3d5a3d241a5e 241 // DACSTEP Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 242 m_DACSTEP_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 243 //
whismanoid 53:3d5a3d241a5e 244 // UP_slash_DWNb Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 245 m_UP_slash_DWNb_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 246 //
whismanoid 53:3d5a3d241a5e 247 // CODE GENERATOR: class constructor definition gpio OutputPin (Output from MAX11043 device) initialization
whismanoid 53:3d5a3d241a5e 248 //
whismanoid 53:3d5a3d241a5e 249 // EOC Event Output from device
whismanoid 69:989e392cf635 250 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 82:9ea067fad5c3 251 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 82:9ea067fad5c3 252 digitalInOut5.output(); // ScopeTrigger
whismanoid 82:9ea067fad5c3 253 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 76:0397493d7baf 254 #if MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 255 // SPI is not interrupt-safe, so use EventQueue to defer execution to user context.
whismanoid 82:9ea067fad5c3 256 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 82:9ea067fad5c3 257 myOnEOCThread.start(myOnEOCThread_POLLING_handler);
whismanoid 82:9ea067fad5c3 258 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 82:9ea067fad5c3 259 myOnEOCThread.start(myOnEOCThread_EVENTFLAG_ENABLE_SPI_handler);
whismanoid 82:9ea067fad5c3 260 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 76:0397493d7baf 261 #else // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 262 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 263 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 264 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 265 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 266 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 267 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 268 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 269 // TODO: onEOCFallingEdge: interrupt handler requires global object extern MAX11043 g_MAX11043_device
whismanoid 71:62bcd01ea87f 270 // InterruptIn interruptEOC(EOC_pin); // InterruptIn constructor requires PinName, not DigitalIn -- Error: No instance of constructor "mbed::InterruptIn::InterruptIn" matches the argument list in "MAX11043/MAX11043.cpp", Line: 187, Col: 31
whismanoid 69:989e392cf635 271 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 70:f44a577c9e59 272 extern void onEOCFallingEdge(void);
whismanoid 71:62bcd01ea87f 273 // interruptEOC.fall(&onEOCFallingEdge);
whismanoid 71:62bcd01ea87f 274 EOC_pin.fall(&onEOCFallingEdge);
whismanoid 69:989e392cf635 275 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 76:0397493d7baf 276 }
whismanoid 69:989e392cf635 277
whismanoid 76:0397493d7baf 278 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 76:0397493d7baf 279 // SPI is not interrupt-safe, so use EventQueue to defer execution to user context.
whismanoid 76:0397493d7baf 280 #if MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 82:9ea067fad5c3 281 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 82:9ea067fad5c3 282 void myOnEOCThread_POLLING_handler()
whismanoid 76:0397493d7baf 283 {
whismanoid 76:0397493d7baf 284 while (true) {
whismanoid 80:96bc693e0f79 285 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 80:96bc693e0f79 286 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 80:96bc693e0f79 287 // poll m_EOC_pin if CONVRUN is high
whismanoid 82:9ea067fad5c3 288 //if (m_CONVRUN_pin)
whismanoid 82:9ea067fad5c3 289 //{
whismanoid 82:9ea067fad5c3 290 //#warning "myOnEOCThread_handler() Potential infinite loop if EOC pin not connected"
whismanoid 80:96bc693e0f79 291 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 82:9ea067fad5c3 292 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 82:9ea067fad5c3 293 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 82:9ea067fad5c3 294 //~ digitalInOut5.write(0); // ScopeTrigger low -- waiting for EOC# high
whismanoid 82:9ea067fad5c3 295 //~ digitalInOut5.write(1); // ScopeTrigger
whismanoid 82:9ea067fad5c3 296 //~ digitalInOut5.write(0); // ScopeTrigger
whismanoid 82:9ea067fad5c3 297 //~ digitalInOut5.write(1); // ScopeTrigger
whismanoid 82:9ea067fad5c3 298 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 82:9ea067fad5c3 299 //for (int futility_countdown = 100;
whismanoid 82:9ea067fad5c3 300 // ((futility_countdown > 0) &&
whismanoid 82:9ea067fad5c3 301 // (m_EOC_pin != 1));
whismanoid 82:9ea067fad5c3 302 // futility_countdown--)
whismanoid 82:9ea067fad5c3 303 //while (digitalInOut2.read() != 1) // digitalInOut2 m_EOC_pin
whismanoid 82:9ea067fad5c3 304 //{
whismanoid 82:9ea067fad5c3 305 // // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 82:9ea067fad5c3 306 //}
whismanoid 82:9ea067fad5c3 307 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 82:9ea067fad5c3 308 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 82:9ea067fad5c3 309 //~ digitalInOut5.write(0); // ScopeTrigger
whismanoid 82:9ea067fad5c3 310 //~ digitalInOut5.write(1); // ScopeTrigger high -- waiting for EOC# falling edge
whismanoid 82:9ea067fad5c3 311 //~ digitalInOut5.write(0); // ScopeTrigger
whismanoid 82:9ea067fad5c3 312 //~ digitalInOut5.write(1); // ScopeTrigger
whismanoid 82:9ea067fad5c3 313 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 82:9ea067fad5c3 314 //for (int futility_countdown = 100;
whismanoid 82:9ea067fad5c3 315 // ((futility_countdown > 0) &&
whismanoid 82:9ea067fad5c3 316 // (m_EOC_pin != 0));
whismanoid 82:9ea067fad5c3 317 // futility_countdown--)
whismanoid 82:9ea067fad5c3 318 while (digitalInOut2.read() != 0) // digitalInOut2 m_EOC_pin
whismanoid 80:96bc693e0f79 319 {
whismanoid 80:96bc693e0f79 320 // spinlock waiting for logic low pin state (new data is available)
whismanoid 80:96bc693e0f79 321 }
whismanoid 82:9ea067fad5c3 322 //}
whismanoid 82:9ea067fad5c3 323 //else
whismanoid 82:9ea067fad5c3 324 //{
whismanoid 82:9ea067fad5c3 325 // // CONVRUN pin is being driven low, so conversion result will not change, EOC# remains high
whismanoid 82:9ea067fad5c3 326 // continue;
whismanoid 82:9ea067fad5c3 327 //}
whismanoid 82:9ea067fad5c3 328 //
whismanoid 82:9ea067fad5c3 329 //extern MAX11043 g_MAX11043_device;
whismanoid 82:9ea067fad5c3 330 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 82:9ea067fad5c3 331 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 82:9ea067fad5c3 332 //~ digitalInOut5.write(0); // ScopeTrigger low -- EOC# falling edge detected, about to start SPI
whismanoid 82:9ea067fad5c3 333 //~ digitalInOut5.write(1); // ScopeTrigger
whismanoid 82:9ea067fad5c3 334 //~ digitalInOut5.write(0); // ScopeTrigger
whismanoid 82:9ea067fad5c3 335 //~ digitalInOut5.write(1); // ScopeTrigger
whismanoid 82:9ea067fad5c3 336 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 82:9ea067fad5c3 337 extern SPI spi; // declared in Test_Main_MAX11043.cpp
whismanoid 82:9ea067fad5c3 338 spi.write((char*)mosiData_onEOCFallingEdge, byteCount_onEOCFallingEdge, (char*)misoData_onEOCFallingEdge, byteCount_onEOCFallingEdge);
whismanoid 82:9ea067fad5c3 339 // Note: EOC# is high immediately after SPI read ADCabcd
whismanoid 82:9ea067fad5c3 340 // SPI timing: CS low 13.30us after EOC# falling edge
whismanoid 82:9ea067fad5c3 341 // SPI timing: SCLK first 14.60us after EOC# falling edge
whismanoid 82:9ea067fad5c3 342 // SPI timing: SCLK last 17.70us after EOC# falling edge
whismanoid 82:9ea067fad5c3 343 // SPI timing: CS high 17.70us after EOC# falling edge
whismanoid 82:9ea067fad5c3 344 //
whismanoid 82:9ea067fad5c3 345 // TODO1: update adca
whismanoid 82:9ea067fad5c3 346 //g_MAX11043_device.adca = (misoData_onEOCFallingEdge[1] << 8) | misoData_onEOCFallingEdge[2];
whismanoid 82:9ea067fad5c3 347 // TODO1: update adcb
whismanoid 82:9ea067fad5c3 348 //g_MAX11043_device.adcb = (misoData_onEOCFallingEdge[3] << 8) | misoData_onEOCFallingEdge[4];
whismanoid 82:9ea067fad5c3 349 // TODO1: update adcc
whismanoid 82:9ea067fad5c3 350 //g_MAX11043_device.adcc = (misoData_onEOCFallingEdge[5] << 8) | misoData_onEOCFallingEdge[6];
whismanoid 82:9ea067fad5c3 351 // TODO1: update adcd
whismanoid 82:9ea067fad5c3 352 //g_MAX11043_device.adcd = (misoData_onEOCFallingEdge[7] << 8) | misoData_onEOCFallingEdge[8];
whismanoid 82:9ea067fad5c3 353 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 82:9ea067fad5c3 354 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 82:9ea067fad5c3 355 //~ digitalInOut5.write(0); // ScopeTrigger
whismanoid 82:9ea067fad5c3 356 //~ digitalInOut5.write(1); // ScopeTrigger high -- end of while loop
whismanoid 82:9ea067fad5c3 357 //~ digitalInOut5.write(0); // ScopeTrigger
whismanoid 82:9ea067fad5c3 358 //~ digitalInOut5.write(1); // ScopeTrigger
whismanoid 82:9ea067fad5c3 359 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 82:9ea067fad5c3 360 } // while (true)
whismanoid 82:9ea067fad5c3 361 } // myOnEOCThread_POLLING_handler()
whismanoid 80:96bc693e0f79 362 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 82:9ea067fad5c3 363 // Waiting for EOC# fall to signal EventQueue is too slow, ~25us to handle event but events happen every 9us.
whismanoid 82:9ea067fad5c3 364 void myOnEOCThread_EVENTFLAG_ENABLE_SPI_handler()
whismanoid 82:9ea067fad5c3 365 {
whismanoid 82:9ea067fad5c3 366 while (true) {
whismanoid 80:96bc693e0f79 367 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 80:96bc693e0f79 368 // Interrupt Handler: EOC Event Output from device
whismanoid 80:96bc693e0f79 369 // Wait for MYONEOCTHREADEVENTFLAG_ENABLE_SPI event sent from onEOCFallingEdge interrupt
whismanoid 76:0397493d7baf 370 //signal_wait(int32_t signals, uint32_t millisec=osWaitForever)
whismanoid 76:0397493d7baf 371 //flags_read = myOnEOCThread_event_flags.wait_any(MYONEOCTHREADEVENTFLAG_ENABLE_SPI);
whismanoid 76:0397493d7baf 372 // myOnEOCThread_event_flags.wait_any(MYONEOCTHREADEVENTFLAG_ENABLE_SPI, osWaitForever, false); // clear=false: don't auto clear the flag
whismanoid 76:0397493d7baf 373 myOnEOCThread_event_flags.wait_any(MYONEOCTHREADEVENTFLAG_ENABLE_SPI, osWaitForever, true); // clear=true: auto clear the flag
whismanoid 76:0397493d7baf 374 //
whismanoid 82:9ea067fad5c3 375 //extern MAX11043 g_MAX11043_device;
whismanoid 76:0397493d7baf 376 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 76:0397493d7baf 377 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 77:3a6e2a5cd7d9 378 digitalInOut5.write(0); // ScopeTrigger happens at 1.8us after EOC# falling edge
whismanoid 76:0397493d7baf 379 digitalInOut5.write(1); // ScopeTrigger
whismanoid 76:0397493d7baf 380 digitalInOut5.write(0); // ScopeTrigger
whismanoid 76:0397493d7baf 381 digitalInOut5.write(1); // ScopeTrigger
whismanoid 76:0397493d7baf 382 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 76:0397493d7baf 383 extern SPI spi; // declared in Test_Main_MAX11043.cpp
whismanoid 76:0397493d7baf 384 spi.write((char*)mosiData_onEOCFallingEdge, byteCount_onEOCFallingEdge, (char*)misoData_onEOCFallingEdge, byteCount_onEOCFallingEdge);
whismanoid 77:3a6e2a5cd7d9 385 // SPI timing: CS low 13.30us after EOC# falling edge
whismanoid 77:3a6e2a5cd7d9 386 // SPI timing: SCLK first 14.60us after EOC# falling edge
whismanoid 77:3a6e2a5cd7d9 387 // SPI timing: SCLK last 17.70us after EOC# falling edge
whismanoid 77:3a6e2a5cd7d9 388 // SPI timing: CS high 17.70us after EOC# falling edge
whismanoid 77:3a6e2a5cd7d9 389 //
whismanoid 76:0397493d7baf 390 // TODO1: update adca
whismanoid 76:0397493d7baf 391 //g_MAX11043_device.adca = (misoData_onEOCFallingEdge[1] << 8) | misoData_onEOCFallingEdge[2];
whismanoid 76:0397493d7baf 392 // TODO1: update adcb
whismanoid 76:0397493d7baf 393 //g_MAX11043_device.adcb = (misoData_onEOCFallingEdge[3] << 8) | misoData_onEOCFallingEdge[4];
whismanoid 76:0397493d7baf 394 // TODO1: update adcc
whismanoid 76:0397493d7baf 395 //g_MAX11043_device.adcc = (misoData_onEOCFallingEdge[5] << 8) | misoData_onEOCFallingEdge[6];
whismanoid 76:0397493d7baf 396 // TODO1: update adcd
whismanoid 76:0397493d7baf 397 //g_MAX11043_device.adcd = (misoData_onEOCFallingEdge[7] << 8) | misoData_onEOCFallingEdge[8];
whismanoid 77:3a6e2a5cd7d9 398 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 77:3a6e2a5cd7d9 399 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 77:3a6e2a5cd7d9 400 digitalInOut5.write(0); // ScopeTrigger happens at 22.5us after EOC# falling edge
whismanoid 77:3a6e2a5cd7d9 401 digitalInOut5.write(1); // ScopeTrigger
whismanoid 77:3a6e2a5cd7d9 402 digitalInOut5.write(0); // ScopeTrigger
whismanoid 77:3a6e2a5cd7d9 403 digitalInOut5.write(1); // ScopeTrigger
whismanoid 77:3a6e2a5cd7d9 404 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 80:96bc693e0f79 405 } // while (true)
whismanoid 82:9ea067fad5c3 406 } // myOnEOCThread_EVENTFLAG_ENABLE_SPI_handler()
whismanoid 82:9ea067fad5c3 407 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 76:0397493d7baf 408 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 53:3d5a3d241a5e 409
whismanoid 69:989e392cf635 410 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 411 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 412 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 413 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 414 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 415 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 416 // Interrupt Handler: EOC Event Output from device
whismanoid 69:989e392cf635 417 void onEOCFallingEdge(void)
whismanoid 69:989e392cf635 418 {
whismanoid 72:40feab5fd579 419 // VERIFIED: if DO NOTHING inside interrupt service routine, no crash
whismanoid 72:40feab5fd579 420 #if 1
whismanoid 72:40feab5fd579 421 // VERIFIED: GPIO PIN pulse in response to EOC# falling edge, no crash on HH, no missed pulses
whismanoid 73:879578472009 422 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 423 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 74:f4f969c9a7a9 424 digitalInOut5.write(0); // ScopeTrigger 1.8us after EOC# falling edge
whismanoid 74:f4f969c9a7a9 425 digitalInOut5.write(1); // ScopeTrigger
whismanoid 74:f4f969c9a7a9 426 digitalInOut5.write(0); // ScopeTrigger
whismanoid 74:f4f969c9a7a9 427 digitalInOut5.write(1); // ScopeTrigger
whismanoid 73:879578472009 428 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 72:40feab5fd579 429 #endif
whismanoid 76:0397493d7baf 430 #if MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 431 // SPI is not interrupt-safe, so use EventQueue to defer execution to user context.
whismanoid 76:0397493d7baf 432 myOnEOCThread_event_flags.set(MYONEOCTHREADEVENTFLAG_ENABLE_SPI);
whismanoid 76:0397493d7baf 433 #else // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 434 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 435 #if 0
whismanoid 72:40feab5fd579 436 // TODO: read 4 channels in response to EOC# falling edge
whismanoid 72:40feab5fd579 437 // WIP MAX11043 interrupt CRASH on Menu item HH CONVRUN High
whismanoid 72:40feab5fd579 438 //
whismanoid 72:40feab5fd579 439 // ++ MbedOS Error Info ++
whismanoid 72:40feab5fd579 440 // Error Status: 0x80020115 Code: 277 Module: 2
whismanoid 72:40feab5fd579 441 // Error Message: Mutex lock failed
whismanoid 72:40feab5fd579 442 // Location: 0xBA33
whismanoid 72:40feab5fd579 443 // Error Value: 0xFFFFFFFA
whismanoid 72:40feab5fd579 444 // Current Thread: main Id: 0x20002CD0 Entry: 0xBD17 StackSize: 0x1000 StackMem: 0x20001CD0 SP: 0x20027ED0
whismanoid 72:40feab5fd579 445 // For more info, visit: https://armmbed.github.io/mbedos-error/?error=0x80020115
whismanoid 72:40feab5fd579 446 // -- MbedOS Error Info --
whismanoid 69:989e392cf635 447 extern MAX11043 g_MAX11043_device;
whismanoid 75:0900a57f2e5d 448 //~ g_MAX11043_device.Read_ADCabcd();
whismanoid 74:f4f969c9a7a9 449 // read register ADCabcd -> &adca, &adcb, &adcc, &adcd
whismanoid 74:f4f969c9a7a9 450 // g_MAX11043_device.RegRead(CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd, 0);
whismanoid 75:0900a57f2e5d 451 // SPI 8+64 = 72-bit transfer
whismanoid 75:0900a57f2e5d 452 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72
whismanoid 75:0900a57f2e5d 453 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 75:0900a57f2e5d 454 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 75:0900a57f2e5d 455 // global const size_t byteCount_onEOCFallingEdge = 1 + (2 * 4);
whismanoid 75:0900a57f2e5d 456 // global const uint8_t mosiData_onEOCFallingEdge[9] = {
whismanoid 75:0900a57f2e5d 457 // global CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd,
whismanoid 75:0900a57f2e5d 458 // global 0, 0, 0, 0, 0, 0, 0, 0
whismanoid 75:0900a57f2e5d 459 // global };
whismanoid 75:0900a57f2e5d 460 // global uint8_t misoData_onEOCFallingEdge[9];
whismanoid 75:0900a57f2e5d 461 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 75:0900a57f2e5d 462 // SPIreadWriteWithLowCS(byteCount_onEOCFallingEdge, mosiData_onEOCFallingEdge, misoData_onEOCFallingEdge);
whismanoid 75:0900a57f2e5d 463 // onSPIprint() is not interrupt-safe
whismanoid 75:0900a57f2e5d 464 // unsigned int numBytesTransferred = m_spi.write((char*)mosiData, byteCount, (char*)misoData, byteCount);
whismanoid 75:0900a57f2e5d 465 // g_MAX11043_device.m_spi is inaccessible
whismanoid 75:0900a57f2e5d 466 extern SPI spi; // declared in Test_Main_MAX11043.cpp
whismanoid 75:0900a57f2e5d 467 spi.write((char*)mosiData_onEOCFallingEdge, byteCount_onEOCFallingEdge, (char*)misoData_onEOCFallingEdge, byteCount_onEOCFallingEdge);
whismanoid 75:0900a57f2e5d 468 //
whismanoid 75:0900a57f2e5d 469 // ++ MbedOS Error Info ++
whismanoid 75:0900a57f2e5d 470 // Error Status: 0x80020115 Code: 277 Module: 2
whismanoid 75:0900a57f2e5d 471 // Error Message: Mutex lock failed
whismanoid 75:0900a57f2e5d 472 // Location: 0xBABB
whismanoid 75:0900a57f2e5d 473 // Error Value: 0xFFFFFFFA
whismanoid 75:0900a57f2e5d 474 // Current Thread: main Id: 0x20002CD0 Entry: 0xBD9F StackSize: 0x1000 StackMem: 0x20001CD0 SP: 0x20027F10
whismanoid 75:0900a57f2e5d 475 // For more info, visit: https://armmbed.github.io/mbedos-error/?error=0x80020115
whismanoid 75:0900a57f2e5d 476 // -- MbedOS Error Info --
whismanoid 75:0900a57f2e5d 477 //
whismanoid 75:0900a57f2e5d 478 //if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 75:0900a57f2e5d 479 //if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 75:0900a57f2e5d 480 // TODO1: update adca
whismanoid 75:0900a57f2e5d 481 //g_MAX11043_device.adca = (misoData_onEOCFallingEdge[1] << 8) | misoData_onEOCFallingEdge[2];
whismanoid 75:0900a57f2e5d 482 // TODO1: update adcb
whismanoid 75:0900a57f2e5d 483 //g_MAX11043_device.adcb = (misoData_onEOCFallingEdge[3] << 8) | misoData_onEOCFallingEdge[4];
whismanoid 75:0900a57f2e5d 484 // TODO1: update adcc
whismanoid 75:0900a57f2e5d 485 //g_MAX11043_device.adcc = (misoData_onEOCFallingEdge[5] << 8) | misoData_onEOCFallingEdge[6];
whismanoid 75:0900a57f2e5d 486 // TODO1: update adcd
whismanoid 75:0900a57f2e5d 487 //g_MAX11043_device.adcd = (misoData_onEOCFallingEdge[7] << 8) | misoData_onEOCFallingEdge[8];
whismanoid 75:0900a57f2e5d 488 //}
whismanoid 72:40feab5fd579 489 #endif
whismanoid 76:0397493d7baf 490 #if 0 // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 75:0900a57f2e5d 491 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 75:0900a57f2e5d 492 digitalInOut5.write(0); // ScopeTrigger
whismanoid 75:0900a57f2e5d 493 digitalInOut5.write(1); // ScopeTrigger
whismanoid 75:0900a57f2e5d 494 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 69:989e392cf635 495 }
whismanoid 69:989e392cf635 496 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 497
whismanoid 53:3d5a3d241a5e 498 // CODE GENERATOR: class destructor definition
whismanoid 53:3d5a3d241a5e 499 MAX11043::~MAX11043()
whismanoid 53:3d5a3d241a5e 500 {
whismanoid 53:3d5a3d241a5e 501 // do nothing
whismanoid 53:3d5a3d241a5e 502 }
whismanoid 53:3d5a3d241a5e 503
whismanoid 53:3d5a3d241a5e 504 // CODE GENERATOR: spi_frequency setter definition
whismanoid 53:3d5a3d241a5e 505 /// set SPI SCLK frequency
whismanoid 53:3d5a3d241a5e 506 void MAX11043::spi_frequency(int spi_sclk_Hz)
whismanoid 53:3d5a3d241a5e 507 {
whismanoid 53:3d5a3d241a5e 508 m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid 53:3d5a3d241a5e 509 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 510 }
whismanoid 53:3d5a3d241a5e 511
whismanoid 53:3d5a3d241a5e 512 // CODE GENERATOR: omit global g_MAX11043_device
whismanoid 53:3d5a3d241a5e 513 // CODE GENERATOR: extern function declarations
whismanoid 53:3d5a3d241a5e 514 // CODE GENERATOR: extern function requirement MAX11043::SPIoutputCS
whismanoid 53:3d5a3d241a5e 515 // Assert SPI Chip Select
whismanoid 53:3d5a3d241a5e 516 // SPI chip-select for MAX11043
whismanoid 53:3d5a3d241a5e 517 //
whismanoid 62:8223a7253c90 518 inline void MAX11043::SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 519 {
whismanoid 53:3d5a3d241a5e 520 // CODE GENERATOR: extern function definition for function SPIoutputCS
whismanoid 53:3d5a3d241a5e 521 // CODE GENERATOR: extern function definition for standard SPI interface function SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 522 m_SPI_cs_state = isLogicHigh;
whismanoid 67:5b8a495dda1c 523 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 524 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 525 }
whismanoid 53:3d5a3d241a5e 526 }
whismanoid 53:3d5a3d241a5e 527
whismanoid 62:8223a7253c90 528 // CODE GENERATOR: extern function requirement MAX11043::SPIreadWriteWithLowCS
whismanoid 62:8223a7253c90 529 // SPI read and write arbitrary number of 8-bit bytes
whismanoid 62:8223a7253c90 530 // SPI interface to MAX11043 shift mosiData into MAX11043 DIN
whismanoid 62:8223a7253c90 531 // while simultaneously capturing miso data from MAX11043 DOUT
whismanoid 62:8223a7253c90 532 //
whismanoid 62:8223a7253c90 533 int MAX11043::SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 534 {
whismanoid 62:8223a7253c90 535 // CODE GENERATOR: extern function definition for function SPIreadWriteWithLowCS
whismanoid 63:8f39d21d6157 536 // TODO1: CODE GENERATOR: extern function definition for standard SPI interface function SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 537 //size_t byteCount = 4;
whismanoid 62:8223a7253c90 538 //static char mosiData[4];
whismanoid 62:8223a7253c90 539 //static char misoData[4];
whismanoid 62:8223a7253c90 540 //
whismanoid 62:8223a7253c90 541 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 542 //~ noInterrupts();
whismanoid 62:8223a7253c90 543 //
whismanoid 62:8223a7253c90 544 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 545 //
whismanoid 67:5b8a495dda1c 546 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 547 m_cs_pin = 0;
whismanoid 67:5b8a495dda1c 548 }
whismanoid 62:8223a7253c90 549 unsigned int numBytesTransferred = m_spi.write((char*)mosiData, byteCount, (char*)misoData, byteCount);
whismanoid 67:5b8a495dda1c 550 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 551 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 552 }
whismanoid 62:8223a7253c90 553 //
whismanoid 62:8223a7253c90 554 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 555 //
whismanoid 62:8223a7253c90 556 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 557 //~ interrupts();
whismanoid 62:8223a7253c90 558 // Optional Diagnostic function to print SPI transactions
whismanoid 62:8223a7253c90 559 if (onSPIprint)
whismanoid 62:8223a7253c90 560 {
whismanoid 62:8223a7253c90 561 onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
whismanoid 62:8223a7253c90 562 }
whismanoid 62:8223a7253c90 563 return numBytesTransferred;
whismanoid 62:8223a7253c90 564 }
whismanoid 62:8223a7253c90 565
whismanoid 53:3d5a3d241a5e 566 // TODO1: CODE GENERATOR: extern function GPIOoutputSHDN alias SHDNoutputValue
whismanoid 53:3d5a3d241a5e 567 // CODE GENERATOR: extern function requirement MAX11043::SHDNoutputValue
whismanoid 58:2fea32db466b 568 // Assert MAX11043 SHDN pin : High = Shut Down, Low = Normal Operation.
whismanoid 53:3d5a3d241a5e 569 //
whismanoid 53:3d5a3d241a5e 570 void MAX11043::SHDNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 571 {
whismanoid 53:3d5a3d241a5e 572 // CODE GENERATOR: extern function definition for function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 573 // TODO1: CODE GENERATOR: extern function definition for gpio interface function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 574 // TODO1: CODE GENERATOR: gpio pin SHDN assuming member function m_SHDN_pin
whismanoid 53:3d5a3d241a5e 575 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 576 // m_SHDN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 577 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 578 m_SHDN_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 579 }
whismanoid 52:607010f0c54e 580
whismanoid 53:3d5a3d241a5e 581 // TODO1: CODE GENERATOR: extern function GPIOoutputCONVRUN alias CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 582 // CODE GENERATOR: extern function requirement MAX11043::CONVRUNoutputValue
whismanoid 58:2fea32db466b 583 // Assert MAX11043 CONVRUN pin : High = start continuous conversions on all 4 channels, Low = Idle.
whismanoid 53:3d5a3d241a5e 584 //
whismanoid 53:3d5a3d241a5e 585 void MAX11043::CONVRUNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 586 {
whismanoid 53:3d5a3d241a5e 587 // CODE GENERATOR: extern function definition for function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 588 // TODO1: CODE GENERATOR: extern function definition for gpio interface function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 589 // TODO1: CODE GENERATOR: gpio pin CONVRUN assuming member function m_CONVRUN_pin
whismanoid 53:3d5a3d241a5e 590 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 591 // m_CONVRUN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 592 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 593 m_CONVRUN_pin = isLogicHigh;
whismanoid 69:989e392cf635 594 //--------------------------------------------------
whismanoid 69:989e392cf635 595 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 596 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 597 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 598 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 599 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 600 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 601 if (m_CONVRUN_pin)
whismanoid 69:989e392cf635 602 {
whismanoid 69:989e392cf635 603 // CONVRUN was switched high, EOC# will now begin toggling
whismanoid 69:989e392cf635 604 }
whismanoid 69:989e392cf635 605 else
whismanoid 69:989e392cf635 606 {
whismanoid 69:989e392cf635 607 // CONVRUN was switched low, so wait until EOC# returns high
whismanoid 69:989e392cf635 608 #warning "MAX11043::Read_ADCabcd() Potential infinite loop if EOC pin not connected"
whismanoid 69:989e392cf635 609 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 69:989e392cf635 610 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 611 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 612 (m_EOC_pin != 1));
whismanoid 69:989e392cf635 613 futility_countdown--)
whismanoid 69:989e392cf635 614 {
whismanoid 69:989e392cf635 615 // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 69:989e392cf635 616 }
whismanoid 69:989e392cf635 617 }
whismanoid 69:989e392cf635 618 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 619 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 620 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 621 //--------------------------------------------------
whismanoid 53:3d5a3d241a5e 622 }
whismanoid 53:3d5a3d241a5e 623
whismanoid 89:20fd6ce5e4dd 624 // CODE GENERATOR: extern function requirement MAX11043::CONVRUNoutputGetValue
whismanoid 89:20fd6ce5e4dd 625 // Return the state being driven onto the MAX11043 CONVRUN pin.
whismanoid 89:20fd6ce5e4dd 626 //
whismanoid 89:20fd6ce5e4dd 627 int MAX11043::CONVRUNoutputGetValue()
whismanoid 89:20fd6ce5e4dd 628 {
whismanoid 89:20fd6ce5e4dd 629 // CODE GENERATOR: extern function definition for function CONVRUNoutputGetValue
whismanoid 89:20fd6ce5e4dd 630 // TODO1: CODE GENERATOR: extern function definition for gpio interface function CONVRUNoutputGetValue
whismanoid 89:20fd6ce5e4dd 631 // TODO1: CODE GENERATOR: gpio pin CONVRUN assuming member function m_CONVRUN_pin
whismanoid 89:20fd6ce5e4dd 632 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 89:20fd6ce5e4dd 633 // m_CONVRUN_pin.output(); // only applicable to DigitalInOut
whismanoid 89:20fd6ce5e4dd 634 // TODO1: CODE GENERATOR: gpio function GetValue
whismanoid 89:20fd6ce5e4dd 635 return m_CONVRUN_pin;
whismanoid 89:20fd6ce5e4dd 636 }
whismanoid 89:20fd6ce5e4dd 637
whismanoid 53:3d5a3d241a5e 638 // TODO1: CODE GENERATOR: extern function GPIOoutputDACSTEP alias DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 639 // CODE GENERATOR: extern function requirement MAX11043::DACSTEPoutputValue
whismanoid 58:2fea32db466b 640 // Assert MAX11043 DACSTEP pin : High = Active, Low = Idle.
whismanoid 53:3d5a3d241a5e 641 //
whismanoid 53:3d5a3d241a5e 642 void MAX11043::DACSTEPoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 643 {
whismanoid 53:3d5a3d241a5e 644 // CODE GENERATOR: extern function definition for function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 645 // TODO1: CODE GENERATOR: extern function definition for gpio interface function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 646 // TODO1: CODE GENERATOR: gpio pin DACSTEP assuming member function m_DACSTEP_pin
whismanoid 53:3d5a3d241a5e 647 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 648 // m_DACSTEP_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 649 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 650 m_DACSTEP_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 651 }
whismanoid 53:3d5a3d241a5e 652
whismanoid 53:3d5a3d241a5e 653 // TODO1: CODE GENERATOR: extern function GPIOoutputUP_slash_DWNb alias UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 654 // CODE GENERATOR: extern function requirement MAX11043::UP_slash_DWNboutputValue
whismanoid 58:2fea32db466b 655 // Assert MAX11043 UP_slash_DWNb pin : High = Up, Low = Down.
whismanoid 53:3d5a3d241a5e 656 //
whismanoid 53:3d5a3d241a5e 657 void MAX11043::UP_slash_DWNboutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 658 {
whismanoid 53:3d5a3d241a5e 659 // CODE GENERATOR: extern function definition for function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 660 // TODO1: CODE GENERATOR: extern function definition for gpio interface function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 661 // TODO1: CODE GENERATOR: gpio pin UP_slash_DWNb assuming member function m_UP_slash_DWNb_pin
whismanoid 53:3d5a3d241a5e 662 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 663 // m_UP_slash_DWNb_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 664 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 665 m_UP_slash_DWNb_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 666 }
whismanoid 53:3d5a3d241a5e 667
whismanoid 53:3d5a3d241a5e 668 // CODE GENERATOR: extern function requirement MAX11043::EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 669 // Wait for MAX11043 EOC pin low, indicating end of conversion.
whismanoid 53:3d5a3d241a5e 670 // Required when using any of the InternalClock modes.
whismanoid 53:3d5a3d241a5e 671 //
whismanoid 53:3d5a3d241a5e 672 void MAX11043::EOCinputWaitUntilLow()
whismanoid 53:3d5a3d241a5e 673 {
whismanoid 53:3d5a3d241a5e 674 // CODE GENERATOR: extern function definition for function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 675 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 676 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 677 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 678 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 679 // TODO1: CODE GENERATOR: gpio function WaitUntilLow
whismanoid 53:3d5a3d241a5e 680 while (m_EOC_pin != 0)
whismanoid 53:3d5a3d241a5e 681 {
whismanoid 53:3d5a3d241a5e 682 // spinlock waiting for logic low pin state
whismanoid 53:3d5a3d241a5e 683 }
whismanoid 53:3d5a3d241a5e 684 }
whismanoid 53:3d5a3d241a5e 685
whismanoid 53:3d5a3d241a5e 686 // CODE GENERATOR: extern function requirement MAX11043::EOCinputValue
whismanoid 53:3d5a3d241a5e 687 // Return the status of the MAX11043 EOC pin.
whismanoid 53:3d5a3d241a5e 688 //
whismanoid 53:3d5a3d241a5e 689 int MAX11043::EOCinputValue()
whismanoid 53:3d5a3d241a5e 690 {
whismanoid 53:3d5a3d241a5e 691 // CODE GENERATOR: extern function definition for function EOCinputValue
whismanoid 53:3d5a3d241a5e 692 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputValue
whismanoid 53:3d5a3d241a5e 693 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 694 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 695 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 696 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 697 return m_EOC_pin.read();
whismanoid 53:3d5a3d241a5e 698 }
whismanoid 53:3d5a3d241a5e 699
whismanoid 53:3d5a3d241a5e 700 // CODE GENERATOR: class member function definitions
whismanoid 53:3d5a3d241a5e 701 //----------------------------------------
whismanoid 53:3d5a3d241a5e 702 // Menu item '!'
whismanoid 53:3d5a3d241a5e 703 // Initialize device
whismanoid 53:3d5a3d241a5e 704 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 705 uint8_t MAX11043::Init(void)
whismanoid 53:3d5a3d241a5e 706 {
whismanoid 53:3d5a3d241a5e 707
whismanoid 53:3d5a3d241a5e 708 //----------------------------------------
whismanoid 59:47538bcf6cda 709 // reference voltage, in Volts
whismanoid 59:47538bcf6cda 710 VRef = 2.500;
whismanoid 59:47538bcf6cda 711
whismanoid 59:47538bcf6cda 712 //----------------------------------------
whismanoid 90:d6ed8a8c5f26 713 // shadow of register config CMD_0010_0000_d16_Wr08_Configuration
whismanoid 59:47538bcf6cda 714 config = 0x6000;
whismanoid 59:47538bcf6cda 715
whismanoid 59:47538bcf6cda 716 //----------------------------------------
whismanoid 59:47538bcf6cda 717 // shadow of register status CMD_0001_1110_d8_Rd07_Status
whismanoid 59:47538bcf6cda 718 status = 0x00;
whismanoid 53:3d5a3d241a5e 719
whismanoid 53:3d5a3d241a5e 720 //----------------------------------------
whismanoid 59:47538bcf6cda 721 // shadow of register ADCa CMD_0000_0010_d16o8_Rd00_ADCa
whismanoid 59:47538bcf6cda 722 adca = 0x0000;
whismanoid 53:3d5a3d241a5e 723
whismanoid 53:3d5a3d241a5e 724 //----------------------------------------
whismanoid 59:47538bcf6cda 725 // shadow of register ADCb CMD_0000_0110_d16o8_Rd01_ADCb
whismanoid 59:47538bcf6cda 726 adcb = 0x0000;
whismanoid 59:47538bcf6cda 727
whismanoid 59:47538bcf6cda 728 //----------------------------------------
whismanoid 59:47538bcf6cda 729 // shadow of register ADCc CMD_0000_1010_d16o8_Rd02_ADCc
whismanoid 59:47538bcf6cda 730 adcc = 0x0000;
whismanoid 59:47538bcf6cda 731
whismanoid 59:47538bcf6cda 732 //----------------------------------------
whismanoid 59:47538bcf6cda 733 // shadow of register ADCd CMD_0000_1110_d16o8_Rd03_ADCd
whismanoid 59:47538bcf6cda 734 adcd = 0x0000;
whismanoid 53:3d5a3d241a5e 735
whismanoid 53:3d5a3d241a5e 736 //----------------------------------------
whismanoid 53:3d5a3d241a5e 737 // init (based on old EV kit GUI)
whismanoid 53:3d5a3d241a5e 738 #warning "Not Implemented Yet: MAX11043::Init init..."
whismanoid 53:3d5a3d241a5e 739 // bool bOpResult = false;
whismanoid 53:3d5a3d241a5e 740 // String FWVersionString = "00";
whismanoid 53:3d5a3d241a5e 741 // bool bDemoMode = true;
whismanoid 53:3d5a3d241a5e 742 // int scan_resolution = 0;
whismanoid 53:3d5a3d241a5e 743 // int scan_channels = 0;
whismanoid 53:3d5a3d241a5e 744 // int scan_bits = 0;
whismanoid 53:3d5a3d241a5e 745 // int sampleRateFactore = 0;
whismanoid 53:3d5a3d241a5e 746 // double sampleRate = 0;
whismanoid 53:3d5a3d241a5e 747 // unsigned long banks_requested = 0;
whismanoid 53:3d5a3d241a5e 748 // bool bScanMode = 0;
whismanoid 53:3d5a3d241a5e 749
whismanoid 53:3d5a3d241a5e 750 //----------------------------------------
whismanoid 59:47538bcf6cda 751 // Device ID Validation -- not used, no device ID register
whismanoid 53:3d5a3d241a5e 752 #warning "Not Implemented Yet: MAX11043::Init Device ID Validation..."
whismanoid 53:3d5a3d241a5e 753 // const uint32_t part_id_expect = 0x000F02;
whismanoid 53:3d5a3d241a5e 754 // uint32_t part_id_readback;
whismanoid 53:3d5a3d241a5e 755 // RegRead(xxxxxxxxxxxxCMD_r001_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xddd_PART_ID, &part_id_readback);
whismanoid 53:3d5a3d241a5e 756 // if (part_id_readback != part_id_expect) return 0;
whismanoid 53:3d5a3d241a5e 757
whismanoid 53:3d5a3d241a5e 758 //----------------------------------------
whismanoid 58:2fea32db466b 759 // Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 58:2fea32db466b 760 SHDNoutputValue(0); // SHDN Inactive
whismanoid 58:2fea32db466b 761
whismanoid 58:2fea32db466b 762 //----------------------------------------
whismanoid 58:2fea32db466b 763 // Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 58:2fea32db466b 764 // CONVRUN is low.
whismanoid 58:2fea32db466b 765 CONVRUNoutputValue(0); // CONVRUN Idle
whismanoid 58:2fea32db466b 766
whismanoid 58:2fea32db466b 767 //----------------------------------------
whismanoid 58:2fea32db466b 768 // DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 58:2fea32db466b 769 // edge of the system clock.
whismanoid 58:2fea32db466b 770 DACSTEPoutputValue(0); // DACSTEP Idle
whismanoid 58:2fea32db466b 771
whismanoid 58:2fea32db466b 772 //----------------------------------------
whismanoid 58:2fea32db466b 773 // DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 58:2fea32db466b 774 UP_slash_DWNboutputValue(0); // UP/DWN# Down
whismanoid 58:2fea32db466b 775
whismanoid 58:2fea32db466b 776 //----------------------------------------
whismanoid 53:3d5a3d241a5e 777 // success
whismanoid 53:3d5a3d241a5e 778 return 1;
whismanoid 53:3d5a3d241a5e 779 }
whismanoid 53:3d5a3d241a5e 780
whismanoid 53:3d5a3d241a5e 781 //----------------------------------------
whismanoid 53:3d5a3d241a5e 782 // Write a MAX11043 register.
whismanoid 53:3d5a3d241a5e 783 //
whismanoid 57:1c9da8e90737 784 // CMDOP_1aaa_aaaa_ReadRegister bit is cleared 0 indicating a write operation.
whismanoid 53:3d5a3d241a5e 785 //
whismanoid 53:3d5a3d241a5e 786 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 787 //
whismanoid 53:3d5a3d241a5e 788 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 789 //
whismanoid 53:3d5a3d241a5e 790 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 791 //
whismanoid 53:3d5a3d241a5e 792 // SPI MOSI = 0aaa_aaaa_dddd_dddd
whismanoid 53:3d5a3d241a5e 793 //
whismanoid 53:3d5a3d241a5e 794 // SPI MISO = xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 795 //
whismanoid 53:3d5a3d241a5e 796 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 797 //
whismanoid 53:3d5a3d241a5e 798 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 799 //
whismanoid 53:3d5a3d241a5e 800 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 801 //
whismanoid 53:3d5a3d241a5e 802 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 803 //
whismanoid 53:3d5a3d241a5e 804 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 805 //
whismanoid 53:3d5a3d241a5e 806 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 807 //
whismanoid 53:3d5a3d241a5e 808 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 809 //
whismanoid 53:3d5a3d241a5e 810 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 811 //
whismanoid 53:3d5a3d241a5e 812 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 813 uint8_t MAX11043::RegWrite(MAX11043_CMD_enum_t commandByte, uint32_t regData)
whismanoid 53:3d5a3d241a5e 814 {
whismanoid 53:3d5a3d241a5e 815
whismanoid 53:3d5a3d241a5e 816 //----------------------------------------
whismanoid 53:3d5a3d241a5e 817 // switch based on register address szie RegSize(commandByte)
whismanoid 57:1c9da8e90737 818 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 819 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 820 {
whismanoid 53:3d5a3d241a5e 821 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 822 {
whismanoid 63:8f39d21d6157 823 // SPI 8+8 = 16-bit transfer
whismanoid 63:8f39d21d6157 824 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 825 // SPI MOSI = 0aaa_aaaa_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 826 // SPI MISO = xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 827 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 828 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 829 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 830 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 831 mosiData[1] = regData;
whismanoid 63:8f39d21d6157 832 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 833 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 834 // TODO: cache CMD_0101_0100_d8_Wr15_FilterCAddress
whismanoid 63:8f39d21d6157 835 // if (commandByte == CMD_0101_0100_d8_Wr15_FilterCAddress) {
whismanoid 63:8f39d21d6157 836 // FilterCAddress = regData;
whismanoid 63:8f39d21d6157 837 // }
whismanoid 63:8f39d21d6157 838 // TODO: cache CMD_0110_0000_d8_Wr18_FlashMode
whismanoid 63:8f39d21d6157 839 // if (commandByte == CMD_0110_0000_d8_Wr18_FlashMode) {
whismanoid 63:8f39d21d6157 840 // FlashMode = regData;
whismanoid 63:8f39d21d6157 841 // }
whismanoid 53:3d5a3d241a5e 842 }
whismanoid 53:3d5a3d241a5e 843 break;
whismanoid 53:3d5a3d241a5e 844 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 845 #warning "Not Verified Yet: MAX11043::RegWrite 16-bit"
whismanoid 53:3d5a3d241a5e 846 {
whismanoid 63:8f39d21d6157 847 // SPI 8+16 = 24-bit transfer
whismanoid 63:8f39d21d6157 848 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 63:8f39d21d6157 849 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 850 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 851 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 852 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 853 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 854 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 855 mosiData[1] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 856 mosiData[2] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 857 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 858 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 859 // cache CMD_0010_0000_d16_Wr08_Configuration
whismanoid 63:8f39d21d6157 860 if (commandByte == CMD_0010_0000_d16_Wr08_Configuration) {
whismanoid 63:8f39d21d6157 861 config = regData;
whismanoid 63:8f39d21d6157 862 }
whismanoid 63:8f39d21d6157 863 // TODO: cache CMD_0010_0100_d16_Wr09_DAC
whismanoid 63:8f39d21d6157 864 // TODO: cache CMD_0010_1000_d16_Wr0A_DACStep
whismanoid 63:8f39d21d6157 865 // TODO: cache CMD_0010_1100_d16_Wr0B_DACHDACL
whismanoid 63:8f39d21d6157 866 // TODO: cache CMD_0011_0000_d16_Wr0C_ConfigA
whismanoid 63:8f39d21d6157 867 // TODO: cache CMD_0011_0100_d16_Wr0D_ConfigB
whismanoid 63:8f39d21d6157 868 // TODO: cache CMD_0011_1000_d16_Wr0E_ConfigC
whismanoid 63:8f39d21d6157 869 // TODO: cache CMD_0011_1100_d16_Wr0F_ConfigD
whismanoid 63:8f39d21d6157 870 // TODO: cache CMD_0100_0000_d16_Wr10_Reference
whismanoid 63:8f39d21d6157 871 // TODO: cache CMD_0100_0100_d16_Wr11_AGain
whismanoid 63:8f39d21d6157 872 // TODO: cache CMD_0100_1000_d16_Wr12_BGain
whismanoid 63:8f39d21d6157 873 // TODO: cache CMD_0100_1100_d16_Wr13_CGain
whismanoid 63:8f39d21d6157 874 // TODO: cache CMD_0101_0000_d16_Wr14_DGain
whismanoid 63:8f39d21d6157 875 // TODO: cache CMD_0110_0100_d16_Wr19_FlashAddr
whismanoid 63:8f39d21d6157 876 // TODO: cache CMD_0110_1000_d16_Wr1A_FlashDataIn
whismanoid 53:3d5a3d241a5e 877 }
whismanoid 53:3d5a3d241a5e 878 break;
whismanoid 63:8f39d21d6157 879 case 32: // 32-bit register size
whismanoid 63:8f39d21d6157 880 #warning "Not Verified Yet: MAX11043::RegWrite 32-bit"
whismanoid 53:3d5a3d241a5e 881 {
whismanoid 63:8f39d21d6157 882 // SPI 8+32 = 40-bit transfer
whismanoid 63:8f39d21d6157 883 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 63:8f39d21d6157 884 // SPI MOSI = 1aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 885 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 886 //
whismanoid 63:8f39d21d6157 887 size_t byteCount = 1 + (2 * 2);
whismanoid 63:8f39d21d6157 888 uint8_t mosiData[5];
whismanoid 63:8f39d21d6157 889 uint8_t misoData[5];
whismanoid 63:8f39d21d6157 890 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 891 mosiData[1] = (uint8_t)((regData >> 24) & 0xFF);
whismanoid 63:8f39d21d6157 892 mosiData[2] = (uint8_t)((regData >> 16) & 0xFF);
whismanoid 63:8f39d21d6157 893 mosiData[3] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 894 mosiData[4] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 895 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 896 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 897 // TODO: cache CMD_0101_1000_d32_Wr16_FilterCDataOut
whismanoid 63:8f39d21d6157 898 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 899 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 900 // }
whismanoid 63:8f39d21d6157 901 // TODO: cache CMD_0101_1100_d32_Wr17_FilterCDataIn
whismanoid 63:8f39d21d6157 902 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 903 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 904 // }
whismanoid 53:3d5a3d241a5e 905 }
whismanoid 53:3d5a3d241a5e 906 break;
whismanoid 53:3d5a3d241a5e 907 }
whismanoid 53:3d5a3d241a5e 908
whismanoid 53:3d5a3d241a5e 909 //----------------------------------------
whismanoid 53:3d5a3d241a5e 910 // success
whismanoid 53:3d5a3d241a5e 911 return 1;
whismanoid 53:3d5a3d241a5e 912 }
whismanoid 53:3d5a3d241a5e 913
whismanoid 53:3d5a3d241a5e 914 //----------------------------------------
whismanoid 53:3d5a3d241a5e 915 // Read an 8-bit MAX11043 register
whismanoid 53:3d5a3d241a5e 916 //
whismanoid 57:1c9da8e90737 917 // CMDOP_1aaa_aaaa_ReadRegister bit is set 1 indicating a read operation.
whismanoid 53:3d5a3d241a5e 918 //
whismanoid 53:3d5a3d241a5e 919 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 920 //
whismanoid 53:3d5a3d241a5e 921 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 922 //
whismanoid 53:3d5a3d241a5e 923 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 924 //
whismanoid 53:3d5a3d241a5e 925 // SPI MOSI = 1aaa_aaaa_0000_0000
whismanoid 53:3d5a3d241a5e 926 //
whismanoid 53:3d5a3d241a5e 927 // SPI MISO = xxxx_xxxx_dddd_dddd
whismanoid 53:3d5a3d241a5e 928 //
whismanoid 53:3d5a3d241a5e 929 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 930 //
whismanoid 53:3d5a3d241a5e 931 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 932 //
whismanoid 53:3d5a3d241a5e 933 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 934 //
whismanoid 53:3d5a3d241a5e 935 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 936 //
whismanoid 53:3d5a3d241a5e 937 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 938 //
whismanoid 53:3d5a3d241a5e 939 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 940 //
whismanoid 53:3d5a3d241a5e 941 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 942 //
whismanoid 53:3d5a3d241a5e 943 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 944 //
whismanoid 53:3d5a3d241a5e 945 //
whismanoid 53:3d5a3d241a5e 946 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 947 uint8_t MAX11043::RegRead(MAX11043_CMD_enum_t commandByte, uint32_t* ptrRegData)
whismanoid 53:3d5a3d241a5e 948 {
whismanoid 91:9e78c6194d6e 949 #define SIGN_EXTEND_INT16_VALUE(x) (((x)&(0x8000))?((x)-65536):(x))
whismanoid 53:3d5a3d241a5e 950
whismanoid 53:3d5a3d241a5e 951 //----------------------------------------
whismanoid 53:3d5a3d241a5e 952 // switch based on register address szie RegSize(regAddress)
whismanoid 57:1c9da8e90737 953 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 954 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 955 {
whismanoid 53:3d5a3d241a5e 956 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 957 {
whismanoid 60:d1d1eaa90fb7 958 // SPI 8+8 = 16-bit transfer
whismanoid 62:8223a7253c90 959 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 960 // SPI MOSI = 1aaa_aaaa_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 961 // SPI MISO = xxxx_xxxx_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 962 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 963 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 964 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 965 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 966 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 967 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 968 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 969 if (ptrRegData) { (*ptrRegData) = misoData[1]; }
whismanoid 59:47538bcf6cda 970 if (commandByte == CMD_0001_1110_d8_Rd07_Status) {
whismanoid 59:47538bcf6cda 971 // TODO1: update status
whismanoid 63:8f39d21d6157 972 status = misoData[1];
whismanoid 59:47538bcf6cda 973 }
whismanoid 53:3d5a3d241a5e 974 }
whismanoid 53:3d5a3d241a5e 975 break;
whismanoid 53:3d5a3d241a5e 976 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 977 #warning "Not Verified Yet: MAX11043::RegRead 16-bit"
whismanoid 53:3d5a3d241a5e 978 {
whismanoid 60:d1d1eaa90fb7 979 // SPI 8+16 = 24-bit transfer
whismanoid 62:8223a7253c90 980 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 60:d1d1eaa90fb7 981 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 982 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 983 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 984 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 985 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 986 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 987 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 988 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 989 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 990 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 991 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 59:47538bcf6cda 992 if (commandByte == CMD_0010_0010_d16_Rd08_Configuration) {
whismanoid 59:47538bcf6cda 993 // TODO1: update config
whismanoid 63:8f39d21d6157 994 config = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 995 }
whismanoid 59:47538bcf6cda 996 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 997 // TODO1: update adca
whismanoid 91:9e78c6194d6e 998 // adca = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 999 // TODO1: update adca as 2's complement
whismanoid 91:9e78c6194d6e 1000 // int raw_code = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 1001 // if (raw_code & 0x8000) { adca = raw_code - 65536; } else { adca = raw_code; }
whismanoid 91:9e78c6194d6e 1002 adca = SIGN_EXTEND_INT16_VALUE((int)(misoData[1] << 8) | misoData[2]);
whismanoid 59:47538bcf6cda 1003 }
whismanoid 59:47538bcf6cda 1004 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 1005 // TODO1: update adcb
whismanoid 91:9e78c6194d6e 1006 // adcb = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 1007 // TODO1: update adca as 2's complement
whismanoid 91:9e78c6194d6e 1008 // int raw_code = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 1009 // if (raw_code & 0x8000) { adca = raw_code - 65536; } else { adca = raw_code; }
whismanoid 91:9e78c6194d6e 1010 adcb = SIGN_EXTEND_INT16_VALUE((int)(misoData[1] << 8) | misoData[2]);
whismanoid 59:47538bcf6cda 1011 }
whismanoid 59:47538bcf6cda 1012 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 1013 // TODO1: update adcc
whismanoid 91:9e78c6194d6e 1014 // adcc = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 1015 // TODO1: update adca as 2's complement
whismanoid 91:9e78c6194d6e 1016 // int raw_code = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 1017 // if (raw_code & 0x8000) { adca = raw_code - 65536; } else { adca = raw_code; }
whismanoid 91:9e78c6194d6e 1018 adcc = SIGN_EXTEND_INT16_VALUE((int)(misoData[1] << 8) | misoData[2]);
whismanoid 59:47538bcf6cda 1019 }
whismanoid 59:47538bcf6cda 1020 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 1021 // TODO1: update adcd
whismanoid 91:9e78c6194d6e 1022 // adcd = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 1023 // TODO1: update adca as 2's complement
whismanoid 91:9e78c6194d6e 1024 // int raw_code = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 1025 // if (raw_code & 0x8000) { adca = raw_code - 65536; } else { adca = raw_code; }
whismanoid 91:9e78c6194d6e 1026 adcd = SIGN_EXTEND_INT16_VALUE((int)(misoData[1] << 8) | misoData[2]);
whismanoid 59:47538bcf6cda 1027 }
whismanoid 53:3d5a3d241a5e 1028 }
whismanoid 53:3d5a3d241a5e 1029 break;
whismanoid 53:3d5a3d241a5e 1030 case 24: // 24-bit register size
whismanoid 53:3d5a3d241a5e 1031 {
whismanoid 60:d1d1eaa90fb7 1032 // SPI 8+24 = 32-bit transfer
whismanoid 62:8223a7253c90 1033 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32
whismanoid 63:8f39d21d6157 1034 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 1035 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 1036 size_t byteCount = 1 + 3;
whismanoid 63:8f39d21d6157 1037 uint8_t mosiData[4];
whismanoid 63:8f39d21d6157 1038 uint8_t misoData[4];
whismanoid 63:8f39d21d6157 1039 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 1040 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 1041 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 1042 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 1043 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 1044 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 1045 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 59:47538bcf6cda 1046 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 1047 // TODO1: update adca
whismanoid 63:8f39d21d6157 1048 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 1049 }
whismanoid 59:47538bcf6cda 1050 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 1051 // TODO1: update adcb
whismanoid 63:8f39d21d6157 1052 adcb = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 1053 }
whismanoid 59:47538bcf6cda 1054 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 1055 // TODO1: update adcc
whismanoid 63:8f39d21d6157 1056 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 1057 }
whismanoid 59:47538bcf6cda 1058 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 1059 // TODO1: update adcd
whismanoid 63:8f39d21d6157 1060 adcd = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 1061 }
whismanoid 59:47538bcf6cda 1062 }
whismanoid 59:47538bcf6cda 1063 break;
whismanoid 63:8f39d21d6157 1064 case 32: // 32-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 1065 //
whismanoid 63:8f39d21d6157 1066 #warning "Not Implemented Yet: MAX11043::RegRead 32-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 1067 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 1068 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 1069 // update adca, adcb
whismanoid 59:47538bcf6cda 1070 //
whismanoid 63:8f39d21d6157 1071 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 1072 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 1073 // update adcc, adcd
whismanoid 59:47538bcf6cda 1074 //
whismanoid 59:47538bcf6cda 1075 {
whismanoid 60:d1d1eaa90fb7 1076 // SPI 8+32 = 40-bit transfer
whismanoid 62:8223a7253c90 1077 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 60:d1d1eaa90fb7 1078 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 1079 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 1080 size_t byteCount = 1 + (2 * 2);
whismanoid 62:8223a7253c90 1081 uint8_t mosiData[5];
whismanoid 62:8223a7253c90 1082 uint8_t misoData[5];
whismanoid 62:8223a7253c90 1083 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 1084 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1085 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1086 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1087 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1088 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 1089 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 1090 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 1091 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 1092 // TODO1: update adca
whismanoid 91:9e78c6194d6e 1093 // adca = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 1094 // TODO1: update adca as 2's complement
whismanoid 91:9e78c6194d6e 1095 // int raw_code = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 1096 // if (raw_code & 0x8000) { adca = raw_code - 65536; } else { adca = raw_code; }
whismanoid 91:9e78c6194d6e 1097 adca = SIGN_EXTEND_INT16_VALUE((int)(misoData[1] << 8) | misoData[2]);
whismanoid 59:47538bcf6cda 1098 // TODO1: update adcb
whismanoid 91:9e78c6194d6e 1099 // adcb = (misoData[3] << 8) | misoData[4];
whismanoid 91:9e78c6194d6e 1100 // TODO1: update adca as 2's complement
whismanoid 91:9e78c6194d6e 1101 // int raw_code = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 1102 // if (raw_code & 0x8000) { adca = raw_code - 65536; } else { adca = raw_code; }
whismanoid 91:9e78c6194d6e 1103 adcb = SIGN_EXTEND_INT16_VALUE((int)(misoData[3] << 8) | misoData[4]);
whismanoid 59:47538bcf6cda 1104 }
whismanoid 63:8f39d21d6157 1105 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 1106 // TODO1: update adcc
whismanoid 62:8223a7253c90 1107 adcc = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 1108 // TODO1: update adca as 2's complement
whismanoid 91:9e78c6194d6e 1109 // int raw_code = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 1110 // if (raw_code & 0x8000) { adca = raw_code - 65536; } else { adca = raw_code; }
whismanoid 91:9e78c6194d6e 1111 adcc = SIGN_EXTEND_INT16_VALUE((int)(misoData[1] << 8) | misoData[2]);
whismanoid 59:47538bcf6cda 1112 // TODO1: update adcd
whismanoid 91:9e78c6194d6e 1113 // adcd = (misoData[3] << 8) | misoData[4];
whismanoid 91:9e78c6194d6e 1114 // TODO1: update adca as 2's complement
whismanoid 91:9e78c6194d6e 1115 // int raw_code = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 1116 // if (raw_code & 0x8000) { adca = raw_code - 65536; } else { adca = raw_code; }
whismanoid 91:9e78c6194d6e 1117 adcd = SIGN_EXTEND_INT16_VALUE((int)(misoData[3] << 8) | misoData[4]);
whismanoid 59:47538bcf6cda 1118 }
whismanoid 59:47538bcf6cda 1119 }
whismanoid 59:47538bcf6cda 1120 break;
whismanoid 63:8f39d21d6157 1121 case 48: // 48-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 1122 //
whismanoid 63:8f39d21d6157 1123 #warning "Not Verified Yet: MAX11043::RegRead 48-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 1124 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 1125 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 1126 // update adca, adcb
whismanoid 59:47538bcf6cda 1127 //
whismanoid 63:8f39d21d6157 1128 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 1129 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 1130 // update adcc, adcd
whismanoid 59:47538bcf6cda 1131 //
whismanoid 59:47538bcf6cda 1132 {
whismanoid 60:d1d1eaa90fb7 1133 // SPI 8+48 = 56-bit transfer
whismanoid 62:8223a7253c90 1134 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56
whismanoid 60:d1d1eaa90fb7 1135 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 1136 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 1137 size_t byteCount = 1 + (3 * 2);
whismanoid 62:8223a7253c90 1138 uint8_t mosiData[7];
whismanoid 62:8223a7253c90 1139 uint8_t misoData[7];
whismanoid 62:8223a7253c90 1140 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 1141 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1142 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1143 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1144 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1145 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1146 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1147 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 1148 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 1149 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 1150 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 1151 // TODO1: update adca
whismanoid 62:8223a7253c90 1152 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 1153 // TODO1: update adcb
whismanoid 62:8223a7253c90 1154 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 1155 }
whismanoid 63:8f39d21d6157 1156 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 1157 // TODO1: update adcc
whismanoid 62:8223a7253c90 1158 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 1159 // TODO1: update adcd
whismanoid 62:8223a7253c90 1160 adcd = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 1161 }
whismanoid 59:47538bcf6cda 1162 }
whismanoid 59:47538bcf6cda 1163 break;
whismanoid 63:8f39d21d6157 1164 case 64: // 64-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 1165 //
whismanoid 63:8f39d21d6157 1166 #warning "Not Verified Yet: MAX11043::RegRead 64-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 1167 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 1168 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1169 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 1170 //
whismanoid 59:47538bcf6cda 1171 {
whismanoid 60:d1d1eaa90fb7 1172 // SPI 8+64 = 72-bit transfer
whismanoid 62:8223a7253c90 1173 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72
whismanoid 60:d1d1eaa90fb7 1174 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 1175 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 1176 size_t byteCount = 1 + (2 * 4);
whismanoid 62:8223a7253c90 1177 uint8_t mosiData[9];
whismanoid 62:8223a7253c90 1178 uint8_t misoData[9];
whismanoid 62:8223a7253c90 1179 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 1180 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1181 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1182 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1183 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1184 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1185 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1186 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1187 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1188 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 1189 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 1190 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 1191 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 1192 // TODO1: update adca
whismanoid 91:9e78c6194d6e 1193 // adca = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 1194 // TODO1: update adca as 2's complement
whismanoid 91:9e78c6194d6e 1195 // int raw_code = (misoData[1] << 8) | misoData[2];
whismanoid 91:9e78c6194d6e 1196 // if (raw_code & 0x8000) { adca = raw_code - 65536; } else { adca = raw_code; }
whismanoid 91:9e78c6194d6e 1197 adca = SIGN_EXTEND_INT16_VALUE((int)(misoData[1] << 8) | misoData[2]);
whismanoid 91:9e78c6194d6e 1198 //
whismanoid 59:47538bcf6cda 1199 // TODO1: update adcb
whismanoid 91:9e78c6194d6e 1200 // adcb = (misoData[3] << 8) | misoData[4];
whismanoid 91:9e78c6194d6e 1201 // TODO1: update adcb as 2's complement
whismanoid 91:9e78c6194d6e 1202 // raw_code = (misoData[3] << 8) | misoData[4];
whismanoid 91:9e78c6194d6e 1203 // if (raw_code & 0x8000) { adcb = raw_code - 65536; } else { adcb = raw_code; }
whismanoid 91:9e78c6194d6e 1204 adcb = SIGN_EXTEND_INT16_VALUE((int)(misoData[3] << 8) | misoData[4]);
whismanoid 91:9e78c6194d6e 1205 //
whismanoid 59:47538bcf6cda 1206 // TODO1: update adcc
whismanoid 91:9e78c6194d6e 1207 // adcc = (misoData[5] << 8) | misoData[6];
whismanoid 91:9e78c6194d6e 1208 // TODO1: update adcc as 2's complement
whismanoid 91:9e78c6194d6e 1209 // raw_code = (misoData[5] << 8) | misoData[6];
whismanoid 91:9e78c6194d6e 1210 // if (raw_code & 0x8000) { adcc = raw_code - 65536; } else { adcc = raw_code; }
whismanoid 91:9e78c6194d6e 1211 adcc = SIGN_EXTEND_INT16_VALUE((int)(misoData[5] << 8) | misoData[6]);
whismanoid 91:9e78c6194d6e 1212 //
whismanoid 59:47538bcf6cda 1213 // TODO1: update adcd
whismanoid 91:9e78c6194d6e 1214 // adcd = (misoData[7] << 8) | misoData[8];
whismanoid 91:9e78c6194d6e 1215 // TODO1: update adcd as 2's complement
whismanoid 91:9e78c6194d6e 1216 // raw_code = (misoData[7] << 8) | misoData[8];
whismanoid 91:9e78c6194d6e 1217 // if (raw_code & 0x8000) { adcd = raw_code - 65536; } else { adcd = raw_code; }
whismanoid 91:9e78c6194d6e 1218 adcd = SIGN_EXTEND_INT16_VALUE((int)(misoData[7] << 8) | misoData[8]);
whismanoid 91:9e78c6194d6e 1219 //
whismanoid 59:47538bcf6cda 1220 }
whismanoid 59:47538bcf6cda 1221 }
whismanoid 59:47538bcf6cda 1222 break;
whismanoid 63:8f39d21d6157 1223 case 96: // 96-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 1224 //
whismanoid 63:8f39d21d6157 1225 #warning "Not Verified Yet: MAX11043::RegRead 96-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 1226 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 1227 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1228 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 1229 //
whismanoid 59:47538bcf6cda 1230 {
whismanoid 60:d1d1eaa90fb7 1231 // SPI 8+96 = 104-bit transfer
whismanoid 62:8223a7253c90 1232 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72 ___[9]_80 __[10]_88 __[11]_96 __[12]104
whismanoid 60:d1d1eaa90fb7 1233 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 1234 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 1235 size_t byteCount = 1 + (3 * 4);
whismanoid 62:8223a7253c90 1236 uint8_t mosiData[13];
whismanoid 62:8223a7253c90 1237 uint8_t misoData[13];
whismanoid 62:8223a7253c90 1238 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 1239 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1240 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1241 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1242 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1243 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1244 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1245 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1246 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1247 mosiData[9] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1248 mosiData[10] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1249 mosiData[11] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1250 mosiData[12] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1251 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 1252 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 1253 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 1254 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 1255 // TODO1: update adca
whismanoid 62:8223a7253c90 1256 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 1257 // TODO1: update adcb
whismanoid 62:8223a7253c90 1258 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 1259 // TODO1: update adcc
whismanoid 62:8223a7253c90 1260 adcc = (misoData[7] << 16) | (misoData[8] << 8) | misoData[9];
whismanoid 59:47538bcf6cda 1261 // TODO1: update adcd
whismanoid 62:8223a7253c90 1262 adcd = (misoData[10] << 16) | (misoData[11] << 8) | misoData[12];
whismanoid 59:47538bcf6cda 1263 }
whismanoid 53:3d5a3d241a5e 1264 }
whismanoid 53:3d5a3d241a5e 1265 break;
whismanoid 53:3d5a3d241a5e 1266 }
whismanoid 53:3d5a3d241a5e 1267
whismanoid 53:3d5a3d241a5e 1268 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1269 // success
whismanoid 53:3d5a3d241a5e 1270 return 1;
whismanoid 53:3d5a3d241a5e 1271 }
whismanoid 53:3d5a3d241a5e 1272
whismanoid 53:3d5a3d241a5e 1273 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1274 // Return the size of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1275 //
whismanoid 53:3d5a3d241a5e 1276 // @return 8 for 8-bit, 16 for 16-bit, 24 for 24-bit, else 0 for undefined register size
whismanoid 53:3d5a3d241a5e 1277 uint8_t MAX11043::RegSize(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1278 {
whismanoid 53:3d5a3d241a5e 1279
whismanoid 53:3d5a3d241a5e 1280 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1281 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 1282 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 1283 switch(commandByte)
whismanoid 53:3d5a3d241a5e 1284 {
whismanoid 53:3d5a3d241a5e 1285 default:
whismanoid 57:1c9da8e90737 1286 // case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 1287 // case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 1288 // case CMDOP_1111_1111_NoOperationMOSIidleHigh:
whismanoid 53:3d5a3d241a5e 1289 return 0; // undefined register size
whismanoid 53:3d5a3d241a5e 1290 case CMD_0001_1110_d8_Rd07_Status:
whismanoid 53:3d5a3d241a5e 1291 case CMD_0101_0100_d8_Wr15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 1292 case CMD_0101_0110_d8_Rd15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 1293 case CMD_0110_0000_d8_Wr18_FlashMode:
whismanoid 53:3d5a3d241a5e 1294 case CMD_0110_0010_d8_Rd18_FlashMode:
whismanoid 53:3d5a3d241a5e 1295 return 8; // 8-bit register size
whismanoid 53:3d5a3d241a5e 1296 case CMD_0010_0000_d16_Wr08_Configuration:
whismanoid 53:3d5a3d241a5e 1297 case CMD_0010_0010_d16_Rd08_Configuration:
whismanoid 53:3d5a3d241a5e 1298 case CMD_0010_0100_d16_Wr09_DAC:
whismanoid 53:3d5a3d241a5e 1299 case CMD_0010_0110_d16_Rd09_DAC:
whismanoid 53:3d5a3d241a5e 1300 case CMD_0010_1000_d16_Wr0A_DACStep:
whismanoid 53:3d5a3d241a5e 1301 case CMD_0010_1010_d16_Rd0A_DACStep:
whismanoid 53:3d5a3d241a5e 1302 case CMD_0010_1100_d16_Wr0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 1303 case CMD_0010_1110_d16_Rd0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 1304 case CMD_0011_0000_d16_Wr0C_ConfigA:
whismanoid 53:3d5a3d241a5e 1305 case CMD_0011_0010_d16_Rd0C_ConfigA:
whismanoid 53:3d5a3d241a5e 1306 case CMD_0011_0100_d16_Wr0D_ConfigB:
whismanoid 53:3d5a3d241a5e 1307 case CMD_0011_0110_d16_Rd0D_ConfigB:
whismanoid 53:3d5a3d241a5e 1308 case CMD_0011_1000_d16_Wr0E_ConfigC:
whismanoid 53:3d5a3d241a5e 1309 case CMD_0011_1010_d16_Rd0E_ConfigC:
whismanoid 53:3d5a3d241a5e 1310 case CMD_0011_1100_d16_Wr0F_ConfigD:
whismanoid 53:3d5a3d241a5e 1311 case CMD_0011_1110_d16_Rd0F_ConfigD:
whismanoid 53:3d5a3d241a5e 1312 case CMD_0100_0000_d16_Wr10_Reference:
whismanoid 53:3d5a3d241a5e 1313 case CMD_0100_0010_d16_Rd10_Reference:
whismanoid 53:3d5a3d241a5e 1314 case CMD_0100_0100_d16_Wr11_AGain:
whismanoid 53:3d5a3d241a5e 1315 case CMD_0100_0110_d16_Rd11_AGain:
whismanoid 53:3d5a3d241a5e 1316 case CMD_0100_1000_d16_Wr12_BGain:
whismanoid 53:3d5a3d241a5e 1317 case CMD_0100_1010_d16_Rd12_BGain:
whismanoid 53:3d5a3d241a5e 1318 case CMD_0100_1100_d16_Wr13_CGain:
whismanoid 53:3d5a3d241a5e 1319 case CMD_0100_1110_d16_Rd13_CGain:
whismanoid 53:3d5a3d241a5e 1320 case CMD_0101_0000_d16_Wr14_DGain:
whismanoid 53:3d5a3d241a5e 1321 case CMD_0101_0010_d16_Rd14_DGain:
whismanoid 53:3d5a3d241a5e 1322 case CMD_0110_0100_d16_Wr19_FlashAddr:
whismanoid 53:3d5a3d241a5e 1323 case CMD_0110_0110_d16_Rd19_FlashAddr:
whismanoid 53:3d5a3d241a5e 1324 case CMD_0110_1000_d16_Wr1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 1325 case CMD_0110_1010_d16_Rd1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 1326 case CMD_0110_1110_d16_Rd1B_FlashDataOut:
whismanoid 53:3d5a3d241a5e 1327 return 16; // 16-bit register size
whismanoid 59:47538bcf6cda 1328 case CMD_0000_0010_d16o8_Rd00_ADCa:
whismanoid 59:47538bcf6cda 1329 case CMD_0000_0110_d16o8_Rd01_ADCb:
whismanoid 59:47538bcf6cda 1330 case CMD_0000_1010_d16o8_Rd02_ADCc:
whismanoid 59:47538bcf6cda 1331 case CMD_0000_1110_d16o8_Rd03_ADCd:
whismanoid 59:47538bcf6cda 1332 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1333 {
whismanoid 59:47538bcf6cda 1334 // %SW 0x02 (0 0 0) -- for 24-bit read
whismanoid 59:47538bcf6cda 1335 return 24; // 24-bit register size
whismanoid 59:47538bcf6cda 1336 }
whismanoid 59:47538bcf6cda 1337 // %SW 0x02 (0 0) -- for 16-bit read
whismanoid 59:47538bcf6cda 1338 //
whismanoid 59:47538bcf6cda 1339 return 16; // 16-bit register size
whismanoid 63:8f39d21d6157 1340 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab:
whismanoid 63:8f39d21d6157 1341 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd:
whismanoid 59:47538bcf6cda 1342 //
whismanoid 59:47538bcf6cda 1343 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 1344 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1345 {
whismanoid 59:47538bcf6cda 1346 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 1347 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 1348 return 48; // 48-bit register size: 2*(24)
whismanoid 59:47538bcf6cda 1349 }
whismanoid 59:47538bcf6cda 1350 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 1351 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 1352 //
whismanoid 59:47538bcf6cda 1353 return 32; // 32-bit register size: 2*(16)
whismanoid 63:8f39d21d6157 1354 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd:
whismanoid 59:47538bcf6cda 1355 //
whismanoid 59:47538bcf6cda 1356 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 1357 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1358 {
whismanoid 59:47538bcf6cda 1359 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1360 return 96; // 96-bit register size: 4*(24)
whismanoid 59:47538bcf6cda 1361 }
whismanoid 59:47538bcf6cda 1362 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1363 //
whismanoid 59:47538bcf6cda 1364 return 64; // 64-bit register size: 4*(16)
whismanoid 53:3d5a3d241a5e 1365 case CMD_0101_1000_d32_Wr16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 1366 case CMD_0101_1010_d32_Rd16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 1367 case CMD_0101_1100_d32_Wr17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 1368 case CMD_0101_1110_d32_Rd17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 1369 return 32; // 32-bit register size
whismanoid 53:3d5a3d241a5e 1370 }
whismanoid 53:3d5a3d241a5e 1371 }
whismanoid 53:3d5a3d241a5e 1372
whismanoid 53:3d5a3d241a5e 1373 //----------------------------------------
whismanoid 57:1c9da8e90737 1374 // Decode operation from commandByte
whismanoid 57:1c9da8e90737 1375 //
whismanoid 57:1c9da8e90737 1376 // @return operation such as idle, read register, write register, etc.
whismanoid 57:1c9da8e90737 1377 MAX11043::MAX11043_CMDOP_enum_t MAX11043::DecodeCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 57:1c9da8e90737 1378 {
whismanoid 57:1c9da8e90737 1379
whismanoid 57:1c9da8e90737 1380 //----------------------------------------
whismanoid 57:1c9da8e90737 1381 // decode operation from command byte
whismanoid 57:1c9da8e90737 1382 switch (commandByte & 0x83)
whismanoid 57:1c9da8e90737 1383 {
whismanoid 57:1c9da8e90737 1384 case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 1385 return CMDOP_0aaa_aa10_ReadRegister;
whismanoid 57:1c9da8e90737 1386 case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 1387 return CMDOP_0aaa_aa00_WriteRegister;
whismanoid 57:1c9da8e90737 1388 default:
whismanoid 57:1c9da8e90737 1389 return CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 57:1c9da8e90737 1390 }
whismanoid 57:1c9da8e90737 1391 }
whismanoid 57:1c9da8e90737 1392
whismanoid 57:1c9da8e90737 1393 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1394 // Return the address field of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1395 //
whismanoid 53:3d5a3d241a5e 1396 // @return register address field as given in datasheet
whismanoid 53:3d5a3d241a5e 1397 uint8_t MAX11043::RegAddrOfCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1398 {
whismanoid 53:3d5a3d241a5e 1399
whismanoid 53:3d5a3d241a5e 1400 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1401 // extract register address value from command byte
whismanoid 57:1c9da8e90737 1402 return (uint8_t)((commandByte &~ 0x83) >> 2); // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 1403 }
whismanoid 53:3d5a3d241a5e 1404
whismanoid 53:3d5a3d241a5e 1405 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1406 // Test whether a command byte is a register read command
whismanoid 53:3d5a3d241a5e 1407 //
whismanoid 53:3d5a3d241a5e 1408 // @return true if command byte is a register read command
whismanoid 53:3d5a3d241a5e 1409 uint8_t MAX11043::IsRegReadCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1410 {
whismanoid 53:3d5a3d241a5e 1411
whismanoid 53:3d5a3d241a5e 1412 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1413 // Test whether a command byte is a register read command
whismanoid 57:1c9da8e90737 1414 return (commandByte &~ 0x02) ? 1 : 0; // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 1415 }
whismanoid 53:3d5a3d241a5e 1416
whismanoid 53:3d5a3d241a5e 1417 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1418 // Return the name of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1419 //
whismanoid 53:3d5a3d241a5e 1420 // @return null-terminated constant C string containing register name or empty string
whismanoid 53:3d5a3d241a5e 1421 const char* MAX11043::RegName(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1422 {
whismanoid 53:3d5a3d241a5e 1423
whismanoid 53:3d5a3d241a5e 1424 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1425 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 1426 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 1427 switch(commandByte)
whismanoid 53:3d5a3d241a5e 1428 {
whismanoid 53:3d5a3d241a5e 1429 default:
whismanoid 53:3d5a3d241a5e 1430 return ""; // undefined register
whismanoid 57:1c9da8e90737 1431 // case CMDOP_0aaa_aa00_WriteRegister: return "_______";
whismanoid 57:1c9da8e90737 1432 // case CMDOP_0aaa_aa10_ReadRegister: return "_______";
whismanoid 57:1c9da8e90737 1433 // case CMDOP_1111_1111_NoOperationMOSIidleHigh: return "_______";
whismanoid 59:47538bcf6cda 1434 case CMD_0000_0010_d16o8_Rd00_ADCa: return "ADCa";
whismanoid 59:47538bcf6cda 1435 case CMD_0000_0110_d16o8_Rd01_ADCb: return "ADCb";
whismanoid 59:47538bcf6cda 1436 case CMD_0000_1010_d16o8_Rd02_ADCc: return "ADCc";
whismanoid 59:47538bcf6cda 1437 case CMD_0000_1110_d16o8_Rd03_ADCd: return "ADCd";
whismanoid 63:8f39d21d6157 1438 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab: return "ADCab";
whismanoid 63:8f39d21d6157 1439 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd: return "ADCcd";
whismanoid 63:8f39d21d6157 1440 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd: return "ADCabcd";
whismanoid 53:3d5a3d241a5e 1441 case CMD_0001_1110_d8_Rd07_Status: return "Status";
whismanoid 53:3d5a3d241a5e 1442 case CMD_0010_0000_d16_Wr08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1443 case CMD_0010_0010_d16_Rd08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1444 case CMD_0010_0100_d16_Wr09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1445 case CMD_0010_0110_d16_Rd09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1446 case CMD_0010_1000_d16_Wr0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1447 case CMD_0010_1010_d16_Rd0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1448 case CMD_0010_1100_d16_Wr0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1449 case CMD_0010_1110_d16_Rd0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1450 case CMD_0011_0000_d16_Wr0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1451 case CMD_0011_0010_d16_Rd0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1452 case CMD_0011_0100_d16_Wr0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1453 case CMD_0011_0110_d16_Rd0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1454 case CMD_0011_1000_d16_Wr0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1455 case CMD_0011_1010_d16_Rd0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1456 case CMD_0011_1100_d16_Wr0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1457 case CMD_0011_1110_d16_Rd0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1458 case CMD_0100_0000_d16_Wr10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1459 case CMD_0100_0010_d16_Rd10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1460 case CMD_0100_0100_d16_Wr11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1461 case CMD_0100_0110_d16_Rd11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1462 case CMD_0100_1000_d16_Wr12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1463 case CMD_0100_1010_d16_Rd12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1464 case CMD_0100_1100_d16_Wr13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1465 case CMD_0100_1110_d16_Rd13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1466 case CMD_0101_0000_d16_Wr14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1467 case CMD_0101_0010_d16_Rd14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1468 case CMD_0101_0100_d8_Wr15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1469 case CMD_0101_0110_d8_Rd15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1470 case CMD_0101_1000_d32_Wr16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1471 case CMD_0101_1010_d32_Rd16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1472 case CMD_0101_1100_d32_Wr17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1473 case CMD_0101_1110_d32_Rd17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1474 case CMD_0110_0000_d8_Wr18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1475 case CMD_0110_0010_d8_Rd18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1476 case CMD_0110_0100_d16_Wr19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1477 case CMD_0110_0110_d16_Rd19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1478 case CMD_0110_1000_d16_Wr1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1479 case CMD_0110_1010_d16_Rd1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1480 case CMD_0110_1110_d16_Rd1B_FlashDataOut: return "FlashDataOut";
whismanoid 53:3d5a3d241a5e 1481 }
whismanoid 53:3d5a3d241a5e 1482 }
whismanoid 53:3d5a3d241a5e 1483
whismanoid 59:47538bcf6cda 1484 //----------------------------------------
whismanoid 64:a667cfd83492 1485 // Menu item '$' -> adca, adcb, adcc, adcd
whismanoid 64:a667cfd83492 1486 // Read ADCabcd
whismanoid 64:a667cfd83492 1487 //
whismanoid 64:a667cfd83492 1488 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1489 uint8_t MAX11043::Read_ADCabcd(void)
whismanoid 64:a667cfd83492 1490 {
whismanoid 64:a667cfd83492 1491
whismanoid 64:a667cfd83492 1492 //----------------------------------------
whismanoid 64:a667cfd83492 1493 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1494 #warning "Not Tested Yet: MAX11043::Read_ADCabcd..."
whismanoid 64:a667cfd83492 1495
whismanoid 69:989e392cf635 1496 //--------------------------------------------------
whismanoid 69:989e392cf635 1497 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 89:20fd6ce5e4dd 1498 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1499 // warning -- WIP work in progress
whismanoid 89:20fd6ce5e4dd 1500 #warning "need CONVRUNoutputGetValue() -- is CONVRUN being driven high?"
whismanoid 89:20fd6ce5e4dd 1501
whismanoid 89:20fd6ce5e4dd 1502 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1503 // Synchronize with EOC End Of Conversion
whismanoid 89:20fd6ce5e4dd 1504 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 1505 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 1506 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 1507 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1508 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 1509 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 1510 // 2020-02-20 MAX11043_EOC_INTERRUPT_POLLING works on MAX32625MBED at 9us conversion rate, with 1us timing margin
whismanoid 69:989e392cf635 1511 // TODO: poll m_EOC_pin if CONVRUN is high
whismanoid 89:20fd6ce5e4dd 1512 if (CONVRUNoutputGetValue()) // is CONVRUN being driven high?
whismanoid 69:989e392cf635 1513 {
whismanoid 89:20fd6ce5e4dd 1514 // CONVRUN pin is being driven high, so EOC# will be changing.
whismanoid 89:20fd6ce5e4dd 1515 // Try to read as close as possible to EOC# falling edge,
whismanoid 89:20fd6ce5e4dd 1516 // because if EOC# falling edge happens during SPI data readout,
whismanoid 89:20fd6ce5e4dd 1517 // the data will be corrupted.
whismanoid 69:989e392cf635 1518 #warning "MAX11043::Read_ADCabcd() Potential infinite loop if EOC pin not connected"
whismanoid 69:989e392cf635 1519 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 69:989e392cf635 1520 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 1521 ((futility_countdown > 0) &&
whismanoid 89:20fd6ce5e4dd 1522 (EOCinputValue() != 1));
whismanoid 69:989e392cf635 1523 futility_countdown--)
whismanoid 69:989e392cf635 1524 {
whismanoid 69:989e392cf635 1525 // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 69:989e392cf635 1526 }
whismanoid 69:989e392cf635 1527 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 1528 ((futility_countdown > 0) &&
whismanoid 89:20fd6ce5e4dd 1529 (EOCinputValue() != 0));
whismanoid 69:989e392cf635 1530 futility_countdown--)
whismanoid 69:989e392cf635 1531 {
whismanoid 69:989e392cf635 1532 // spinlock waiting for logic low pin state (new data is available)
whismanoid 69:989e392cf635 1533 }
whismanoid 69:989e392cf635 1534 }
whismanoid 69:989e392cf635 1535 else
whismanoid 69:989e392cf635 1536 {
whismanoid 69:989e392cf635 1537 // CONVRUN pin is being driven low, so conversion result will not change, EOC# remains high
whismanoid 69:989e392cf635 1538 }
whismanoid 69:989e392cf635 1539 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1540 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 1541 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1542 //--------------------------------------------------
whismanoid 69:989e392cf635 1543
whismanoid 64:a667cfd83492 1544 //----------------------------------------
whismanoid 64:a667cfd83492 1545 // read register ADCabcd -> &adca, &adcb, &adcc, &adcd
whismanoid 90:d6ed8a8c5f26 1546 RegRead(CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd, 0); // updates &adca, &adcb, &adcc, &adcd
whismanoid 64:a667cfd83492 1547
whismanoid 64:a667cfd83492 1548 //----------------------------------------
whismanoid 64:a667cfd83492 1549 // success
whismanoid 64:a667cfd83492 1550 return 1;
whismanoid 64:a667cfd83492 1551 }
whismanoid 64:a667cfd83492 1552
whismanoid 64:a667cfd83492 1553 //----------------------------------------
whismanoid 66:3fe92f6f1cfa 1554 // Menu item 'GA'
whismanoid 64:a667cfd83492 1555 // Write AGain register
whismanoid 64:a667cfd83492 1556 //
whismanoid 64:a667cfd83492 1557 // @param[in] gain 2's complement, 0x800=0.25V/V, 0x1000=0.5V/V, 0x2000=1VV/V, 0x4000=2V/V, default=0x2000
whismanoid 64:a667cfd83492 1558 //
whismanoid 64:a667cfd83492 1559 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1560 uint8_t MAX11043::Write_AGain(uint32_t gain)
whismanoid 64:a667cfd83492 1561 {
whismanoid 64:a667cfd83492 1562
whismanoid 64:a667cfd83492 1563 //----------------------------------------
whismanoid 64:a667cfd83492 1564 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1565 #warning "Not Tested Yet: MAX11043::Write_AGain..."
whismanoid 64:a667cfd83492 1566
whismanoid 64:a667cfd83492 1567 //----------------------------------------
whismanoid 64:a667cfd83492 1568 // write register
whismanoid 64:a667cfd83492 1569 RegWrite(CMD_0100_0100_d16_Wr11_AGain, gain);
whismanoid 64:a667cfd83492 1570
whismanoid 64:a667cfd83492 1571 //----------------------------------------
whismanoid 64:a667cfd83492 1572 // success
whismanoid 64:a667cfd83492 1573 return 1;
whismanoid 64:a667cfd83492 1574 }
whismanoid 64:a667cfd83492 1575
whismanoid 64:a667cfd83492 1576 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1577 // Menu item 'XD'
whismanoid 89:20fd6ce5e4dd 1578 // Example configuration.
whismanoid 89:20fd6ce5e4dd 1579 // Slowest conversion rate 1:6 = 9us,
whismanoid 89:20fd6ce5e4dd 1580 // Bypass PGA and filters, Gain=1V/V,
whismanoid 89:20fd6ce5e4dd 1581 // AOUT = 2.0V
whismanoid 89:20fd6ce5e4dd 1582 //
whismanoid 89:20fd6ce5e4dd 1583 void MAX11043::Configure_Demo(void)
whismanoid 89:20fd6ce5e4dd 1584 {
whismanoid 89:20fd6ce5e4dd 1585
whismanoid 89:20fd6ce5e4dd 1586 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1587 // warning -- WIP work in progress
whismanoid 89:20fd6ce5e4dd 1588 #warning "Not Tested Yet: MAX11043::Configure_Demo..."
whismanoid 89:20fd6ce5e4dd 1589
whismanoid 89:20fd6ce5e4dd 1590 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1591 // *Config=0x6000 (POR default, slowest conversion rate 1:6 = 9us)
whismanoid 89:20fd6ce5e4dd 1592 RegWrite(CMD_0010_0000_d16_Wr08_Configuration, 0x6000);
whismanoid 89:20fd6ce5e4dd 1593
whismanoid 89:20fd6ce5e4dd 1594 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1595 // *ConfigA=0x0018 (Bypass PGA and filters, Gain=1V/V)
whismanoid 89:20fd6ce5e4dd 1596 RegWrite(CMD_0011_0000_d16_Wr0C_ConfigA, 0x0018);
whismanoid 89:20fd6ce5e4dd 1597
whismanoid 89:20fd6ce5e4dd 1598 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1599 // *AGain=0x1000 (0.5) (default is 0x2000=1.0)
whismanoid 89:20fd6ce5e4dd 1600 RegWrite(CMD_0100_0100_d16_Wr11_AGain, 0x1000);
whismanoid 89:20fd6ce5e4dd 1601
whismanoid 89:20fd6ce5e4dd 1602 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1603 // *ConfigB=0x0018 (Bypass PGA and filters, Gain=1V/V)
whismanoid 89:20fd6ce5e4dd 1604 RegWrite(CMD_0011_0100_d16_Wr0D_ConfigB, 0x0018);
whismanoid 89:20fd6ce5e4dd 1605
whismanoid 89:20fd6ce5e4dd 1606 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1607 // *BGain=0x1000 (0.5) (default is 0x2000=1.0)
whismanoid 89:20fd6ce5e4dd 1608 RegWrite(CMD_0100_1000_d16_Wr12_BGain, 0x1000);
whismanoid 89:20fd6ce5e4dd 1609
whismanoid 89:20fd6ce5e4dd 1610 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1611 // *ConfigC=0x0018 (Bypass PGA and filters, Gain=1V/V)
whismanoid 89:20fd6ce5e4dd 1612 RegWrite(CMD_0011_1000_d16_Wr0E_ConfigC, 0x0018);
whismanoid 89:20fd6ce5e4dd 1613
whismanoid 89:20fd6ce5e4dd 1614 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1615 // *CGain=0x1000 (0.5) (default is 0x2000=1.0)
whismanoid 89:20fd6ce5e4dd 1616 RegWrite(CMD_0100_1100_d16_Wr13_CGain, 0x1000);
whismanoid 89:20fd6ce5e4dd 1617
whismanoid 89:20fd6ce5e4dd 1618 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1619 // *ConfigD=0x0018 (Bypass PGA and filters, Gain=1V/V)
whismanoid 89:20fd6ce5e4dd 1620 RegWrite(CMD_0011_1100_d16_Wr0F_ConfigD, 0x0018);
whismanoid 89:20fd6ce5e4dd 1621
whismanoid 89:20fd6ce5e4dd 1622 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1623 // *DGain=0x1000 (0.5) (default is 0x2000=1.0)
whismanoid 89:20fd6ce5e4dd 1624 RegWrite(CMD_0101_0000_d16_Wr14_DGain, 0x1000);
whismanoid 89:20fd6ce5e4dd 1625
whismanoid 89:20fd6ce5e4dd 1626 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1627 // *DacHDacL=0xFF00 (DAC code 0xFFF fullscale 2.5V, DAC code 0x000 lowest 0V)
whismanoid 89:20fd6ce5e4dd 1628 RegWrite(CMD_0010_1100_d16_Wr0B_DACHDACL, 0xFF00);
whismanoid 89:20fd6ce5e4dd 1629
whismanoid 89:20fd6ce5e4dd 1630 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1631 // *DacStep=0x0001 (DAC increment value triggered by DACSTEP pin)
whismanoid 89:20fd6ce5e4dd 1632 RegWrite(CMD_0010_1000_d16_Wr0A_DACStep, 0x0001);
whismanoid 89:20fd6ce5e4dd 1633
whismanoid 89:20fd6ce5e4dd 1634 //----------------------------------------
whismanoid 89:20fd6ce5e4dd 1635 // *Dac=0x0ccc (AOUT=2V)
whismanoid 89:20fd6ce5e4dd 1636 RegWrite(CMD_0010_0100_d16_Wr09_DAC, 0x0ccc);
whismanoid 89:20fd6ce5e4dd 1637 }
whismanoid 89:20fd6ce5e4dd 1638
whismanoid 89:20fd6ce5e4dd 1639 //----------------------------------------
whismanoid 59:47538bcf6cda 1640 // Menu item 'XX'
whismanoid 59:47538bcf6cda 1641 //
whismanoid 59:47538bcf6cda 1642 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1643 uint8_t MAX11043::Configure_XXXXX(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1644 {
whismanoid 59:47538bcf6cda 1645
whismanoid 59:47538bcf6cda 1646 //----------------------------------------
whismanoid 59:47538bcf6cda 1647 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1648 #warning "Not Tested Yet: MAX11043::Configure_XXXXX..."
whismanoid 59:47538bcf6cda 1649
whismanoid 59:47538bcf6cda 1650 //----------------------------------------
whismanoid 59:47538bcf6cda 1651 // read register
whismanoid 90:d6ed8a8c5f26 1652 RegRead(CMD_0000_0010_d16o8_Rd00_ADCa, 0); // updates &adca
whismanoid 59:47538bcf6cda 1653
whismanoid 59:47538bcf6cda 1654 //----------------------------------------
whismanoid 59:47538bcf6cda 1655 // success
whismanoid 59:47538bcf6cda 1656 return 1;
whismanoid 59:47538bcf6cda 1657 }
whismanoid 59:47538bcf6cda 1658
whismanoid 59:47538bcf6cda 1659 //----------------------------------------
whismanoid 59:47538bcf6cda 1660 // Menu item 'XY'
whismanoid 59:47538bcf6cda 1661 //
whismanoid 59:47538bcf6cda 1662 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1663 uint8_t MAX11043::Configure_XXXXY(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1664 {
whismanoid 59:47538bcf6cda 1665
whismanoid 59:47538bcf6cda 1666 //----------------------------------------
whismanoid 59:47538bcf6cda 1667 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1668 #warning "Not Tested Yet: MAX11043::Configure_XXXXY..."
whismanoid 59:47538bcf6cda 1669
whismanoid 59:47538bcf6cda 1670 //----------------------------------------
whismanoid 59:47538bcf6cda 1671 // read register
whismanoid 90:d6ed8a8c5f26 1672 RegRead(CMD_0001_1110_d8_Rd07_Status, 0); // udpates &status
whismanoid 59:47538bcf6cda 1673
whismanoid 59:47538bcf6cda 1674 //----------------------------------------
whismanoid 59:47538bcf6cda 1675 // success
whismanoid 59:47538bcf6cda 1676 return 1;
whismanoid 59:47538bcf6cda 1677 }
whismanoid 59:47538bcf6cda 1678
whismanoid 53:3d5a3d241a5e 1679
whismanoid 53:3d5a3d241a5e 1680 // End of file