Mark Underwood / Mbed OS MAX11043_Serial_Tester

Test program running on MAX32625MBED. Control through USB Serial commands using a terminal emulator such as teraterm or putty.

Dependencies:   MaximTinyTester CmdLine MAX541 USBDevice

MAX11043/MAX11043.cpp@73:879578472009, 2020-02-22 (annotated)

Committer:
whismanoid
Date:
Sat Feb 22 01:04:36 2020 +0000
Revision:
73:879578472009
Parent:
72:40feab5fd579
Child:
74:f4f969c9a7a9
WIP MAX11043 interrupt EOC echo - moving DigitalOut ScopeTrigger to global scope, it compiles but there is no activity on scope

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 53:3d5a3d241a5e 1 // /*******************************************************************************
whismanoid 53:3d5a3d241a5e 2 // * Copyright (C) 2020 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 53:3d5a3d241a5e 3 // *
whismanoid 53:3d5a3d241a5e 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 53:3d5a3d241a5e 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 53:3d5a3d241a5e 6 // * to deal in the Software without restriction, including without limitation
whismanoid 53:3d5a3d241a5e 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 53:3d5a3d241a5e 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 53:3d5a3d241a5e 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 53:3d5a3d241a5e 10 // *
whismanoid 53:3d5a3d241a5e 11 // * The above copyright notice and this permission notice shall be included
whismanoid 53:3d5a3d241a5e 12 // * in all copies or substantial portions of the Software.
whismanoid 53:3d5a3d241a5e 13 // *
whismanoid 53:3d5a3d241a5e 14 // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid 53:3d5a3d241a5e 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 53:3d5a3d241a5e 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 53:3d5a3d241a5e 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 53:3d5a3d241a5e 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 53:3d5a3d241a5e 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 53:3d5a3d241a5e 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 53:3d5a3d241a5e 21 // *
whismanoid 53:3d5a3d241a5e 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 53:3d5a3d241a5e 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 53:3d5a3d241a5e 24 // * Products, Inc. Branding Policy.
whismanoid 53:3d5a3d241a5e 25 // *
whismanoid 53:3d5a3d241a5e 26 // * The mere transfer of this software does not imply any licenses
whismanoid 53:3d5a3d241a5e 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 53:3d5a3d241a5e 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 53:3d5a3d241a5e 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 53:3d5a3d241a5e 30 // * ownership rights.
whismanoid 53:3d5a3d241a5e 31 // *******************************************************************************
whismanoid 53:3d5a3d241a5e 32 // */
whismanoid 53:3d5a3d241a5e 33 // *********************************************************************
whismanoid 53:3d5a3d241a5e 34 // @file MAX11043.cpp
whismanoid 53:3d5a3d241a5e 35 // *********************************************************************
whismanoid 53:3d5a3d241a5e 36 // Device Driver file
whismanoid 53:3d5a3d241a5e 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid 53:3d5a3d241a5e 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 53:3d5a3d241a5e 39 // System Name = ExampleSystem
whismanoid 53:3d5a3d241a5e 40 // System Description = Device driver example
whismanoid 53:3d5a3d241a5e 41
whismanoid 53:3d5a3d241a5e 42 #include "MAX11043.h"
whismanoid 69:989e392cf635 43 //--------------------------------------------------
whismanoid 69:989e392cf635 44 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 45 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 46 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 47 #ifndef MAX11043_EOC_INTERRUPT_POLLING
whismanoid 71:62bcd01ea87f 48 #define MAX11043_EOC_INTERRUPT_POLLING 0
whismanoid 69:989e392cf635 49 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 73:879578472009 50 //--------------------------------------------------
whismanoid 73:879578472009 51 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 73:879578472009 52 #ifndef MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 53 #define MAX11043_ScopeTrigger_MAX32625MBED_D5 1
whismanoid 73:879578472009 54 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 55 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 56 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 73:879578472009 57 #define D5 P0_5
whismanoid 73:879578472009 58 // WIP MAX11043 interrupt EOC echo - moving DigitalOut ScopeTrigger to global scope, it compiles but there is no activity on scope
whismanoid 73:879578472009 59 // DigitalOut ScopeTrigger(D5);
whismanoid 73:879578472009 60 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 53:3d5a3d241a5e 61
whismanoid 53:3d5a3d241a5e 62 // Device Name = MAX11043
whismanoid 53:3d5a3d241a5e 63 // Device Description = 200ksps, Low-Power, Serial SPI 24-Bit, 4-Channel, Differential/Single-Ended Input, Simultaneous-Sampling SD ADC
whismanoid 53:3d5a3d241a5e 64 // Device DeviceBriefDescription = 24-bit 200ksps Delta-Sigma ADC
whismanoid 53:3d5a3d241a5e 65 // Device Manufacturer = Maxim Integrated
whismanoid 53:3d5a3d241a5e 66 // Device PartNumber = MAX11043ATL+
whismanoid 53:3d5a3d241a5e 67 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 53:3d5a3d241a5e 68 //
whismanoid 53:3d5a3d241a5e 69 // ADC MaxOutputDataRate = 200ksps
whismanoid 53:3d5a3d241a5e 70 // ADC NumChannels = 4
whismanoid 53:3d5a3d241a5e 71 // ADC ResolutionBits = 24
whismanoid 53:3d5a3d241a5e 72 //
whismanoid 53:3d5a3d241a5e 73 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 74 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 75 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 76 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 77 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 78 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 79 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 80 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 81 //
whismanoid 53:3d5a3d241a5e 82 // InputPin Name = CONVRUN
whismanoid 53:3d5a3d241a5e 83 // InputPin Description = CONVRUN (digital input). Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 53:3d5a3d241a5e 84 // CONVRUN is low.
whismanoid 53:3d5a3d241a5e 85 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 86 //
whismanoid 53:3d5a3d241a5e 87 // InputPin Name = SHDN
whismanoid 53:3d5a3d241a5e 88 // InputPin Description = Shutdown (digital input). Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 53:3d5a3d241a5e 89 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 90 //
whismanoid 53:3d5a3d241a5e 91 // InputPin Name = DACSTEP
whismanoid 53:3d5a3d241a5e 92 // InputPin Description = DACSTEP (digital input). DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 53:3d5a3d241a5e 93 // edge of the system clock.
whismanoid 53:3d5a3d241a5e 94 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 95 //
whismanoid 53:3d5a3d241a5e 96 // InputPin Name = UP/DWN#
whismanoid 53:3d5a3d241a5e 97 // InputPin Description = UP/DWN# (digital input). DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 53:3d5a3d241a5e 98 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 99 //
whismanoid 53:3d5a3d241a5e 100 // OutputPin Name = EOC
whismanoid 53:3d5a3d241a5e 101 // OutputPin Description = End of Conversion Output. Active-Low End-of-Conversion Indicator. EOC asserts low to indicate that new data is ready.
whismanoid 53:3d5a3d241a5e 102 // OutputPin Function = Event
whismanoid 53:3d5a3d241a5e 103 //
whismanoid 58:2fea32db466b 104 // SupplyPin Name = AVDD
whismanoid 58:2fea32db466b 105 // SupplyPin Description = Analog Power-Supply Input. Bypass each AVDD with a nominal 1uF capacitor to AGND.
whismanoid 58:2fea32db466b 106 // SupplyPin VinMax = 3.60
whismanoid 58:2fea32db466b 107 // SupplyPin VinMin = 3.00
whismanoid 58:2fea32db466b 108 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 109 //
whismanoid 58:2fea32db466b 110 // SupplyPin Name = AGND
whismanoid 58:2fea32db466b 111 // SupplyPin Description = Analog Ground. Connect all AGND inputs together.
whismanoid 58:2fea32db466b 112 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 113 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 114 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 115 //
whismanoid 58:2fea32db466b 116 // SupplyPin Name = DGND
whismanoid 58:2fea32db466b 117 // SupplyPin Description = Digital Ground. Connect all DGND inputs together.
whismanoid 58:2fea32db466b 118 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 119 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 120 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 121 //
whismanoid 58:2fea32db466b 122 // SupplyPin Name = DVDD
whismanoid 58:2fea32db466b 123 // SupplyPin Description = Digital Power-Supply Input. Bypass each DVDD with a nominal 1uF capacitor to DGND.
whismanoid 58:2fea32db466b 124 // SupplyPin VinMax = 3.60 (*TODO PENDING VERIFICATION*)
whismanoid 58:2fea32db466b 125 // SupplyPin VinMin = 3.00 (*TODO PENDING VERIFICATION*)
whismanoid 58:2fea32db466b 126 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 127 //
whismanoid 58:2fea32db466b 128 // SupplyPin Name = DVREG
whismanoid 58:2fea32db466b 129 // SupplyPin Description = Regulated Digital Core Supply (from internal +2.5V regulator). Bypass DVREG to DGND with a 10uF capacitor.
whismanoid 58:2fea32db466b 130 // SupplyPin VinMax = 2.50
whismanoid 58:2fea32db466b 131 // SupplyPin VinMin = 2.50
whismanoid 58:2fea32db466b 132 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 133 //
whismanoid 53:3d5a3d241a5e 134
whismanoid 53:3d5a3d241a5e 135 // CODE GENERATOR: class constructor definition
whismanoid 53:3d5a3d241a5e 136 MAX11043::MAX11043(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 53:3d5a3d241a5e 137 // CODE GENERATOR: class constructor definition gpio InputPin pins
whismanoid 53:3d5a3d241a5e 138 DigitalOut &CONVRUN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 139 DigitalOut &SHDN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 140 DigitalOut &DACSTEP_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 141 DigitalOut &UP_slash_DWNb_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 142 // CODE GENERATOR: class constructor definition gpio OutputPin pins
whismanoid 69:989e392cf635 143 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 144 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 145 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 146 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 147 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 53:3d5a3d241a5e 148 DigitalIn &EOC_pin, // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 149 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 150 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 151 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 69:989e392cf635 152 InterruptIn &EOC_pin, // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 153 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 154 // CODE GENERATOR: class constructor definition ic_variant
whismanoid 53:3d5a3d241a5e 155 MAX11043_ic_t ic_variant)
whismanoid 53:3d5a3d241a5e 156 // CODE GENERATOR: class constructor initializer list
whismanoid 53:3d5a3d241a5e 157 : m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid 53:3d5a3d241a5e 158 // CODE GENERATOR: class constructor initializer list gpio InputPin pins
whismanoid 53:3d5a3d241a5e 159 m_CONVRUN_pin(CONVRUN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 160 m_SHDN_pin(SHDN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 161 m_DACSTEP_pin(DACSTEP_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 162 m_UP_slash_DWNb_pin(UP_slash_DWNb_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 163 // CODE GENERATOR: class constructor initializer list gpio OutputPin pins
whismanoid 69:989e392cf635 164 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 165 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 166 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 167 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 53:3d5a3d241a5e 168 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 169 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 170 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 70:f44a577c9e59 171 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 172 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 173 // CODE GENERATOR: class constructor initializer list ic_variant
whismanoid 53:3d5a3d241a5e 174 m_ic_variant(ic_variant)
whismanoid 53:3d5a3d241a5e 175 {
whismanoid 53:3d5a3d241a5e 176 // CODE GENERATOR: class constructor definition SPI interface initialization
whismanoid 53:3d5a3d241a5e 177 //
whismanoid 53:3d5a3d241a5e 178 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 179 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 180 m_SPI_cs_state = 1;
whismanoid 67:5b8a495dda1c 181 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 182 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 183 }
whismanoid 53:3d5a3d241a5e 184
whismanoid 53:3d5a3d241a5e 185 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 186 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 187 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 188 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 189 m_SPI_dataMode = 0; //SPI_MODE0; // CPOL=0,CPHA=0: Rising Edge stable; SCLK idle Low
whismanoid 53:3d5a3d241a5e 190 m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid 53:3d5a3d241a5e 191
whismanoid 53:3d5a3d241a5e 192 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 193 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 194 //#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid 53:3d5a3d241a5e 195 //#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid 53:3d5a3d241a5e 196 //#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid 53:3d5a3d241a5e 197 //#define SPI_SCLK_Hz 6000000 // 6MHz
whismanoid 53:3d5a3d241a5e 198 //#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid 53:3d5a3d241a5e 199 //#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid 53:3d5a3d241a5e 200 //#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid 61:b4f3051578ef 201 m_SPI_SCLK_Hz = 24000000; // platform limit 24MHz; MAX11043 limit is 40MHz
whismanoid 53:3d5a3d241a5e 202 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 203
whismanoid 53:3d5a3d241a5e 204 //
whismanoid 53:3d5a3d241a5e 205 // CODE GENERATOR: class constructor definition gpio InputPin (Input to device) initialization
whismanoid 53:3d5a3d241a5e 206 //
whismanoid 53:3d5a3d241a5e 207 // CONVRUN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 208 m_CONVRUN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 209 //
whismanoid 53:3d5a3d241a5e 210 // SHDN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 211 m_SHDN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 212 //
whismanoid 53:3d5a3d241a5e 213 // DACSTEP Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 214 m_DACSTEP_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 215 //
whismanoid 53:3d5a3d241a5e 216 // UP_slash_DWNb Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 217 m_UP_slash_DWNb_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 218 //
whismanoid 53:3d5a3d241a5e 219 // CODE GENERATOR: class constructor definition gpio OutputPin (Output from MAX11043 device) initialization
whismanoid 53:3d5a3d241a5e 220 //
whismanoid 53:3d5a3d241a5e 221 // EOC Event Output from device
whismanoid 69:989e392cf635 222 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 223 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 224 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 225 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 226 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 227 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 228 // TODO: onEOCFallingEdge: interrupt handler requires global object extern MAX11043 g_MAX11043_device
whismanoid 71:62bcd01ea87f 229 // InterruptIn interruptEOC(EOC_pin); // InterruptIn constructor requires PinName, not DigitalIn -- Error: No instance of constructor "mbed::InterruptIn::InterruptIn" matches the argument list in "MAX11043/MAX11043.cpp", Line: 187, Col: 31
whismanoid 69:989e392cf635 230 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 70:f44a577c9e59 231 extern void onEOCFallingEdge(void);
whismanoid 71:62bcd01ea87f 232 // interruptEOC.fall(&onEOCFallingEdge);
whismanoid 71:62bcd01ea87f 233 EOC_pin.fall(&onEOCFallingEdge);
whismanoid 69:989e392cf635 234 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 235
whismanoid 53:3d5a3d241a5e 236 }
whismanoid 53:3d5a3d241a5e 237
whismanoid 69:989e392cf635 238 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 239 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 240 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 241 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 242 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 243 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 244 // Interrupt Handler: EOC Event Output from device
whismanoid 69:989e392cf635 245 void onEOCFallingEdge(void)
whismanoid 69:989e392cf635 246 {
whismanoid 72:40feab5fd579 247 // VERIFIED: if DO NOTHING inside interrupt service routine, no crash
whismanoid 72:40feab5fd579 248 #if 1
whismanoid 72:40feab5fd579 249 // VERIFIED: GPIO PIN pulse in response to EOC# falling edge, no crash on HH, no missed pulses
whismanoid 73:879578472009 250 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 251 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 73:879578472009 252 // WIP MAX11043 interrupt EOC echo - moving DigitalOut ScopeTrigger to global scope, it compiles but there is no activity on scope
whismanoid 72:40feab5fd579 253 DigitalOut ScopeTrigger(D5);
whismanoid 73:879578472009 254 // With ScopeTrigger declared inside interrupt handler,
whismanoid 73:879578472009 255 // latency is 2.64us before first ScopeTrigger even visible on scope
whismanoid 73:879578472009 256 // then 5.32us to final event,
whismanoid 73:879578472009 257 // 160us between high/low events.
whismanoid 72:40feab5fd579 258 ScopeTrigger = 0;
whismanoid 72:40feab5fd579 259 ScopeTrigger = 1;
whismanoid 72:40feab5fd579 260 ScopeTrigger = 0;
whismanoid 72:40feab5fd579 261 ScopeTrigger = 1;
whismanoid 73:879578472009 262 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 72:40feab5fd579 263 #endif
whismanoid 72:40feab5fd579 264 #if 0
whismanoid 72:40feab5fd579 265 // TODO: read 4 channels in response to EOC# falling edge
whismanoid 72:40feab5fd579 266 // WIP MAX11043 interrupt CRASH on Menu item HH CONVRUN High
whismanoid 72:40feab5fd579 267 //
whismanoid 72:40feab5fd579 268 // ++ MbedOS Error Info ++
whismanoid 72:40feab5fd579 269 // Error Status: 0x80020115 Code: 277 Module: 2
whismanoid 72:40feab5fd579 270 // Error Message: Mutex lock failed
whismanoid 72:40feab5fd579 271 // Location: 0xBA33
whismanoid 72:40feab5fd579 272 // Error Value: 0xFFFFFFFA
whismanoid 72:40feab5fd579 273 // Current Thread: main Id: 0x20002CD0 Entry: 0xBD17 StackSize: 0x1000 StackMem: 0x20001CD0 SP: 0x20027ED0
whismanoid 72:40feab5fd579 274 // For more info, visit: https://armmbed.github.io/mbedos-error/?error=0x80020115
whismanoid 72:40feab5fd579 275 // -- MbedOS Error Info --
whismanoid 69:989e392cf635 276 extern MAX11043 g_MAX11043_device;
whismanoid 69:989e392cf635 277 g_MAX11043_device.Read_ADCabcd();
whismanoid 72:40feab5fd579 278 #endif
whismanoid 69:989e392cf635 279 }
whismanoid 69:989e392cf635 280 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 281
whismanoid 53:3d5a3d241a5e 282 // CODE GENERATOR: class destructor definition
whismanoid 53:3d5a3d241a5e 283 MAX11043::~MAX11043()
whismanoid 53:3d5a3d241a5e 284 {
whismanoid 53:3d5a3d241a5e 285 // do nothing
whismanoid 53:3d5a3d241a5e 286 }
whismanoid 53:3d5a3d241a5e 287
whismanoid 53:3d5a3d241a5e 288 // CODE GENERATOR: spi_frequency setter definition
whismanoid 53:3d5a3d241a5e 289 /// set SPI SCLK frequency
whismanoid 53:3d5a3d241a5e 290 void MAX11043::spi_frequency(int spi_sclk_Hz)
whismanoid 53:3d5a3d241a5e 291 {
whismanoid 53:3d5a3d241a5e 292 m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid 53:3d5a3d241a5e 293 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 294 }
whismanoid 53:3d5a3d241a5e 295
whismanoid 53:3d5a3d241a5e 296 // CODE GENERATOR: omit global g_MAX11043_device
whismanoid 53:3d5a3d241a5e 297 // CODE GENERATOR: extern function declarations
whismanoid 53:3d5a3d241a5e 298 // CODE GENERATOR: extern function requirement MAX11043::SPIoutputCS
whismanoid 53:3d5a3d241a5e 299 // Assert SPI Chip Select
whismanoid 53:3d5a3d241a5e 300 // SPI chip-select for MAX11043
whismanoid 53:3d5a3d241a5e 301 //
whismanoid 62:8223a7253c90 302 inline void MAX11043::SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 303 {
whismanoid 53:3d5a3d241a5e 304 // CODE GENERATOR: extern function definition for function SPIoutputCS
whismanoid 53:3d5a3d241a5e 305 // CODE GENERATOR: extern function definition for standard SPI interface function SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 306 m_SPI_cs_state = isLogicHigh;
whismanoid 67:5b8a495dda1c 307 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 308 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 309 }
whismanoid 53:3d5a3d241a5e 310 }
whismanoid 53:3d5a3d241a5e 311
whismanoid 62:8223a7253c90 312 // CODE GENERATOR: extern function requirement MAX11043::SPIreadWriteWithLowCS
whismanoid 62:8223a7253c90 313 // SPI read and write arbitrary number of 8-bit bytes
whismanoid 62:8223a7253c90 314 // SPI interface to MAX11043 shift mosiData into MAX11043 DIN
whismanoid 62:8223a7253c90 315 // while simultaneously capturing miso data from MAX11043 DOUT
whismanoid 62:8223a7253c90 316 //
whismanoid 62:8223a7253c90 317 int MAX11043::SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 318 {
whismanoid 62:8223a7253c90 319 // CODE GENERATOR: extern function definition for function SPIreadWriteWithLowCS
whismanoid 63:8f39d21d6157 320 // TODO1: CODE GENERATOR: extern function definition for standard SPI interface function SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 321 //size_t byteCount = 4;
whismanoid 62:8223a7253c90 322 //static char mosiData[4];
whismanoid 62:8223a7253c90 323 //static char misoData[4];
whismanoid 62:8223a7253c90 324 //
whismanoid 62:8223a7253c90 325 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 326 //~ noInterrupts();
whismanoid 62:8223a7253c90 327 //
whismanoid 62:8223a7253c90 328 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 329 //
whismanoid 67:5b8a495dda1c 330 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 331 m_cs_pin = 0;
whismanoid 67:5b8a495dda1c 332 }
whismanoid 62:8223a7253c90 333 unsigned int numBytesTransferred = m_spi.write((char*)mosiData, byteCount, (char*)misoData, byteCount);
whismanoid 67:5b8a495dda1c 334 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 335 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 336 }
whismanoid 62:8223a7253c90 337 //
whismanoid 62:8223a7253c90 338 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 339 //
whismanoid 62:8223a7253c90 340 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 341 //~ interrupts();
whismanoid 62:8223a7253c90 342 // Optional Diagnostic function to print SPI transactions
whismanoid 62:8223a7253c90 343 if (onSPIprint)
whismanoid 62:8223a7253c90 344 {
whismanoid 62:8223a7253c90 345 onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
whismanoid 62:8223a7253c90 346 }
whismanoid 62:8223a7253c90 347 return numBytesTransferred;
whismanoid 62:8223a7253c90 348 }
whismanoid 62:8223a7253c90 349
whismanoid 53:3d5a3d241a5e 350 // TODO1: CODE GENERATOR: extern function GPIOoutputSHDN alias SHDNoutputValue
whismanoid 53:3d5a3d241a5e 351 // CODE GENERATOR: extern function requirement MAX11043::SHDNoutputValue
whismanoid 58:2fea32db466b 352 // Assert MAX11043 SHDN pin : High = Shut Down, Low = Normal Operation.
whismanoid 53:3d5a3d241a5e 353 //
whismanoid 53:3d5a3d241a5e 354 void MAX11043::SHDNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 355 {
whismanoid 53:3d5a3d241a5e 356 // CODE GENERATOR: extern function definition for function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 357 // TODO1: CODE GENERATOR: extern function definition for gpio interface function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 358 // TODO1: CODE GENERATOR: gpio pin SHDN assuming member function m_SHDN_pin
whismanoid 53:3d5a3d241a5e 359 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 360 // m_SHDN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 361 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 362 m_SHDN_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 363 }
whismanoid 52:607010f0c54e 364
whismanoid 53:3d5a3d241a5e 365 // TODO1: CODE GENERATOR: extern function GPIOoutputCONVRUN alias CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 366 // CODE GENERATOR: extern function requirement MAX11043::CONVRUNoutputValue
whismanoid 58:2fea32db466b 367 // Assert MAX11043 CONVRUN pin : High = start continuous conversions on all 4 channels, Low = Idle.
whismanoid 53:3d5a3d241a5e 368 //
whismanoid 53:3d5a3d241a5e 369 void MAX11043::CONVRUNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 370 {
whismanoid 53:3d5a3d241a5e 371 // CODE GENERATOR: extern function definition for function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 372 // TODO1: CODE GENERATOR: extern function definition for gpio interface function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 373 // TODO1: CODE GENERATOR: gpio pin CONVRUN assuming member function m_CONVRUN_pin
whismanoid 53:3d5a3d241a5e 374 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 375 // m_CONVRUN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 376 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 377 m_CONVRUN_pin = isLogicHigh;
whismanoid 69:989e392cf635 378 //--------------------------------------------------
whismanoid 69:989e392cf635 379 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 380 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 381 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 382 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 383 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 384 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 385 if (m_CONVRUN_pin)
whismanoid 69:989e392cf635 386 {
whismanoid 69:989e392cf635 387 // CONVRUN was switched high, EOC# will now begin toggling
whismanoid 69:989e392cf635 388 }
whismanoid 69:989e392cf635 389 else
whismanoid 69:989e392cf635 390 {
whismanoid 69:989e392cf635 391 // CONVRUN was switched low, so wait until EOC# returns high
whismanoid 69:989e392cf635 392 #warning "MAX11043::Read_ADCabcd() Potential infinite loop if EOC pin not connected"
whismanoid 69:989e392cf635 393 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 69:989e392cf635 394 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 395 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 396 (m_EOC_pin != 1));
whismanoid 69:989e392cf635 397 futility_countdown--)
whismanoid 69:989e392cf635 398 {
whismanoid 69:989e392cf635 399 // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 69:989e392cf635 400 }
whismanoid 69:989e392cf635 401 }
whismanoid 69:989e392cf635 402 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 403 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 404 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 405 //--------------------------------------------------
whismanoid 53:3d5a3d241a5e 406 }
whismanoid 53:3d5a3d241a5e 407
whismanoid 53:3d5a3d241a5e 408 // TODO1: CODE GENERATOR: extern function GPIOoutputDACSTEP alias DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 409 // CODE GENERATOR: extern function requirement MAX11043::DACSTEPoutputValue
whismanoid 58:2fea32db466b 410 // Assert MAX11043 DACSTEP pin : High = Active, Low = Idle.
whismanoid 53:3d5a3d241a5e 411 //
whismanoid 53:3d5a3d241a5e 412 void MAX11043::DACSTEPoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 413 {
whismanoid 53:3d5a3d241a5e 414 // CODE GENERATOR: extern function definition for function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 415 // TODO1: CODE GENERATOR: extern function definition for gpio interface function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 416 // TODO1: CODE GENERATOR: gpio pin DACSTEP assuming member function m_DACSTEP_pin
whismanoid 53:3d5a3d241a5e 417 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 418 // m_DACSTEP_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 419 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 420 m_DACSTEP_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 421 }
whismanoid 53:3d5a3d241a5e 422
whismanoid 53:3d5a3d241a5e 423 // TODO1: CODE GENERATOR: extern function GPIOoutputUP_slash_DWNb alias UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 424 // CODE GENERATOR: extern function requirement MAX11043::UP_slash_DWNboutputValue
whismanoid 58:2fea32db466b 425 // Assert MAX11043 UP_slash_DWNb pin : High = Up, Low = Down.
whismanoid 53:3d5a3d241a5e 426 //
whismanoid 53:3d5a3d241a5e 427 void MAX11043::UP_slash_DWNboutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 428 {
whismanoid 53:3d5a3d241a5e 429 // CODE GENERATOR: extern function definition for function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 430 // TODO1: CODE GENERATOR: extern function definition for gpio interface function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 431 // TODO1: CODE GENERATOR: gpio pin UP_slash_DWNb assuming member function m_UP_slash_DWNb_pin
whismanoid 53:3d5a3d241a5e 432 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 433 // m_UP_slash_DWNb_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 434 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 435 m_UP_slash_DWNb_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 436 }
whismanoid 53:3d5a3d241a5e 437
whismanoid 53:3d5a3d241a5e 438 // CODE GENERATOR: extern function requirement MAX11043::EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 439 // Wait for MAX11043 EOC pin low, indicating end of conversion.
whismanoid 53:3d5a3d241a5e 440 // Required when using any of the InternalClock modes.
whismanoid 53:3d5a3d241a5e 441 //
whismanoid 53:3d5a3d241a5e 442 void MAX11043::EOCinputWaitUntilLow()
whismanoid 53:3d5a3d241a5e 443 {
whismanoid 53:3d5a3d241a5e 444 // CODE GENERATOR: extern function definition for function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 445 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 446 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 447 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 448 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 449 // TODO1: CODE GENERATOR: gpio function WaitUntilLow
whismanoid 53:3d5a3d241a5e 450 while (m_EOC_pin != 0)
whismanoid 53:3d5a3d241a5e 451 {
whismanoid 53:3d5a3d241a5e 452 // spinlock waiting for logic low pin state
whismanoid 53:3d5a3d241a5e 453 }
whismanoid 53:3d5a3d241a5e 454 }
whismanoid 53:3d5a3d241a5e 455
whismanoid 53:3d5a3d241a5e 456 // CODE GENERATOR: extern function requirement MAX11043::EOCinputValue
whismanoid 53:3d5a3d241a5e 457 // Return the status of the MAX11043 EOC pin.
whismanoid 53:3d5a3d241a5e 458 //
whismanoid 53:3d5a3d241a5e 459 int MAX11043::EOCinputValue()
whismanoid 53:3d5a3d241a5e 460 {
whismanoid 53:3d5a3d241a5e 461 // CODE GENERATOR: extern function definition for function EOCinputValue
whismanoid 53:3d5a3d241a5e 462 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputValue
whismanoid 53:3d5a3d241a5e 463 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 464 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 465 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 466 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 467 return m_EOC_pin.read();
whismanoid 53:3d5a3d241a5e 468 }
whismanoid 53:3d5a3d241a5e 469
whismanoid 53:3d5a3d241a5e 470 // CODE GENERATOR: class member function definitions
whismanoid 53:3d5a3d241a5e 471 //----------------------------------------
whismanoid 53:3d5a3d241a5e 472 // Menu item '!'
whismanoid 53:3d5a3d241a5e 473 // Initialize device
whismanoid 53:3d5a3d241a5e 474 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 475 uint8_t MAX11043::Init(void)
whismanoid 53:3d5a3d241a5e 476 {
whismanoid 53:3d5a3d241a5e 477
whismanoid 53:3d5a3d241a5e 478 //----------------------------------------
whismanoid 59:47538bcf6cda 479 // reference voltage, in Volts
whismanoid 59:47538bcf6cda 480 VRef = 2.500;
whismanoid 59:47538bcf6cda 481
whismanoid 59:47538bcf6cda 482 //----------------------------------------
whismanoid 59:47538bcf6cda 483 // shadow of register config CMD_0010_0010_d16_Rd08_Configuration
whismanoid 59:47538bcf6cda 484 config = 0x6000;
whismanoid 59:47538bcf6cda 485
whismanoid 59:47538bcf6cda 486 //----------------------------------------
whismanoid 59:47538bcf6cda 487 // shadow of register status CMD_0001_1110_d8_Rd07_Status
whismanoid 59:47538bcf6cda 488 status = 0x00;
whismanoid 53:3d5a3d241a5e 489
whismanoid 53:3d5a3d241a5e 490 //----------------------------------------
whismanoid 59:47538bcf6cda 491 // shadow of register ADCa CMD_0000_0010_d16o8_Rd00_ADCa
whismanoid 59:47538bcf6cda 492 adca = 0x0000;
whismanoid 53:3d5a3d241a5e 493
whismanoid 53:3d5a3d241a5e 494 //----------------------------------------
whismanoid 59:47538bcf6cda 495 // shadow of register ADCb CMD_0000_0110_d16o8_Rd01_ADCb
whismanoid 59:47538bcf6cda 496 adcb = 0x0000;
whismanoid 59:47538bcf6cda 497
whismanoid 59:47538bcf6cda 498 //----------------------------------------
whismanoid 59:47538bcf6cda 499 // shadow of register ADCc CMD_0000_1010_d16o8_Rd02_ADCc
whismanoid 59:47538bcf6cda 500 adcc = 0x0000;
whismanoid 59:47538bcf6cda 501
whismanoid 59:47538bcf6cda 502 //----------------------------------------
whismanoid 59:47538bcf6cda 503 // shadow of register ADCd CMD_0000_1110_d16o8_Rd03_ADCd
whismanoid 59:47538bcf6cda 504 adcd = 0x0000;
whismanoid 53:3d5a3d241a5e 505
whismanoid 53:3d5a3d241a5e 506 //----------------------------------------
whismanoid 53:3d5a3d241a5e 507 // init (based on old EV kit GUI)
whismanoid 53:3d5a3d241a5e 508 #warning "Not Implemented Yet: MAX11043::Init init..."
whismanoid 53:3d5a3d241a5e 509 // bool bOpResult = false;
whismanoid 53:3d5a3d241a5e 510 // String FWVersionString = "00";
whismanoid 53:3d5a3d241a5e 511 // bool bDemoMode = true;
whismanoid 53:3d5a3d241a5e 512 // int scan_resolution = 0;
whismanoid 53:3d5a3d241a5e 513 // int scan_channels = 0;
whismanoid 53:3d5a3d241a5e 514 // int scan_bits = 0;
whismanoid 53:3d5a3d241a5e 515 // int sampleRateFactore = 0;
whismanoid 53:3d5a3d241a5e 516 // double sampleRate = 0;
whismanoid 53:3d5a3d241a5e 517 // unsigned long banks_requested = 0;
whismanoid 53:3d5a3d241a5e 518 // bool bScanMode = 0;
whismanoid 53:3d5a3d241a5e 519
whismanoid 53:3d5a3d241a5e 520 //----------------------------------------
whismanoid 59:47538bcf6cda 521 // Device ID Validation -- not used, no device ID register
whismanoid 53:3d5a3d241a5e 522 #warning "Not Implemented Yet: MAX11043::Init Device ID Validation..."
whismanoid 53:3d5a3d241a5e 523 // const uint32_t part_id_expect = 0x000F02;
whismanoid 53:3d5a3d241a5e 524 // uint32_t part_id_readback;
whismanoid 53:3d5a3d241a5e 525 // RegRead(xxxxxxxxxxxxCMD_r001_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xddd_PART_ID, &part_id_readback);
whismanoid 53:3d5a3d241a5e 526 // if (part_id_readback != part_id_expect) return 0;
whismanoid 53:3d5a3d241a5e 527
whismanoid 53:3d5a3d241a5e 528 //----------------------------------------
whismanoid 58:2fea32db466b 529 // Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 58:2fea32db466b 530 SHDNoutputValue(0); // SHDN Inactive
whismanoid 58:2fea32db466b 531
whismanoid 58:2fea32db466b 532 //----------------------------------------
whismanoid 58:2fea32db466b 533 // Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 58:2fea32db466b 534 // CONVRUN is low.
whismanoid 58:2fea32db466b 535 CONVRUNoutputValue(0); // CONVRUN Idle
whismanoid 58:2fea32db466b 536
whismanoid 58:2fea32db466b 537 //----------------------------------------
whismanoid 58:2fea32db466b 538 // DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 58:2fea32db466b 539 // edge of the system clock.
whismanoid 58:2fea32db466b 540 DACSTEPoutputValue(0); // DACSTEP Idle
whismanoid 58:2fea32db466b 541
whismanoid 58:2fea32db466b 542 //----------------------------------------
whismanoid 58:2fea32db466b 543 // DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 58:2fea32db466b 544 UP_slash_DWNboutputValue(0); // UP/DWN# Down
whismanoid 58:2fea32db466b 545
whismanoid 58:2fea32db466b 546 //----------------------------------------
whismanoid 53:3d5a3d241a5e 547 // success
whismanoid 53:3d5a3d241a5e 548 return 1;
whismanoid 53:3d5a3d241a5e 549 }
whismanoid 53:3d5a3d241a5e 550
whismanoid 53:3d5a3d241a5e 551 //----------------------------------------
whismanoid 53:3d5a3d241a5e 552 // Write a MAX11043 register.
whismanoid 53:3d5a3d241a5e 553 //
whismanoid 57:1c9da8e90737 554 // CMDOP_1aaa_aaaa_ReadRegister bit is cleared 0 indicating a write operation.
whismanoid 53:3d5a3d241a5e 555 //
whismanoid 53:3d5a3d241a5e 556 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 557 //
whismanoid 53:3d5a3d241a5e 558 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 559 //
whismanoid 53:3d5a3d241a5e 560 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 561 //
whismanoid 53:3d5a3d241a5e 562 // SPI MOSI = 0aaa_aaaa_dddd_dddd
whismanoid 53:3d5a3d241a5e 563 //
whismanoid 53:3d5a3d241a5e 564 // SPI MISO = xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 565 //
whismanoid 53:3d5a3d241a5e 566 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 567 //
whismanoid 53:3d5a3d241a5e 568 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 569 //
whismanoid 53:3d5a3d241a5e 570 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 571 //
whismanoid 53:3d5a3d241a5e 572 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 573 //
whismanoid 53:3d5a3d241a5e 574 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 575 //
whismanoid 53:3d5a3d241a5e 576 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 577 //
whismanoid 53:3d5a3d241a5e 578 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 579 //
whismanoid 53:3d5a3d241a5e 580 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 581 //
whismanoid 53:3d5a3d241a5e 582 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 583 uint8_t MAX11043::RegWrite(MAX11043_CMD_enum_t commandByte, uint32_t regData)
whismanoid 53:3d5a3d241a5e 584 {
whismanoid 53:3d5a3d241a5e 585
whismanoid 53:3d5a3d241a5e 586 //----------------------------------------
whismanoid 53:3d5a3d241a5e 587 // switch based on register address szie RegSize(commandByte)
whismanoid 57:1c9da8e90737 588 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 589 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 590 {
whismanoid 53:3d5a3d241a5e 591 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 592 {
whismanoid 63:8f39d21d6157 593 // SPI 8+8 = 16-bit transfer
whismanoid 63:8f39d21d6157 594 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 595 // SPI MOSI = 0aaa_aaaa_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 596 // SPI MISO = xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 597 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 598 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 599 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 600 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 601 mosiData[1] = regData;
whismanoid 63:8f39d21d6157 602 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 603 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 604 // TODO: cache CMD_0101_0100_d8_Wr15_FilterCAddress
whismanoid 63:8f39d21d6157 605 // if (commandByte == CMD_0101_0100_d8_Wr15_FilterCAddress) {
whismanoid 63:8f39d21d6157 606 // FilterCAddress = regData;
whismanoid 63:8f39d21d6157 607 // }
whismanoid 63:8f39d21d6157 608 // TODO: cache CMD_0110_0000_d8_Wr18_FlashMode
whismanoid 63:8f39d21d6157 609 // if (commandByte == CMD_0110_0000_d8_Wr18_FlashMode) {
whismanoid 63:8f39d21d6157 610 // FlashMode = regData;
whismanoid 63:8f39d21d6157 611 // }
whismanoid 53:3d5a3d241a5e 612 }
whismanoid 53:3d5a3d241a5e 613 break;
whismanoid 53:3d5a3d241a5e 614 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 615 #warning "Not Verified Yet: MAX11043::RegWrite 16-bit"
whismanoid 53:3d5a3d241a5e 616 {
whismanoid 63:8f39d21d6157 617 // SPI 8+16 = 24-bit transfer
whismanoid 63:8f39d21d6157 618 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 63:8f39d21d6157 619 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 620 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 621 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 622 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 623 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 624 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 625 mosiData[1] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 626 mosiData[2] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 627 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 628 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 629 // cache CMD_0010_0000_d16_Wr08_Configuration
whismanoid 63:8f39d21d6157 630 if (commandByte == CMD_0010_0000_d16_Wr08_Configuration) {
whismanoid 63:8f39d21d6157 631 config = regData;
whismanoid 63:8f39d21d6157 632 }
whismanoid 63:8f39d21d6157 633 // TODO: cache CMD_0010_0100_d16_Wr09_DAC
whismanoid 63:8f39d21d6157 634 // TODO: cache CMD_0010_1000_d16_Wr0A_DACStep
whismanoid 63:8f39d21d6157 635 // TODO: cache CMD_0010_1100_d16_Wr0B_DACHDACL
whismanoid 63:8f39d21d6157 636 // TODO: cache CMD_0011_0000_d16_Wr0C_ConfigA
whismanoid 63:8f39d21d6157 637 // TODO: cache CMD_0011_0100_d16_Wr0D_ConfigB
whismanoid 63:8f39d21d6157 638 // TODO: cache CMD_0011_1000_d16_Wr0E_ConfigC
whismanoid 63:8f39d21d6157 639 // TODO: cache CMD_0011_1100_d16_Wr0F_ConfigD
whismanoid 63:8f39d21d6157 640 // TODO: cache CMD_0100_0000_d16_Wr10_Reference
whismanoid 63:8f39d21d6157 641 // TODO: cache CMD_0100_0100_d16_Wr11_AGain
whismanoid 63:8f39d21d6157 642 // TODO: cache CMD_0100_1000_d16_Wr12_BGain
whismanoid 63:8f39d21d6157 643 // TODO: cache CMD_0100_1100_d16_Wr13_CGain
whismanoid 63:8f39d21d6157 644 // TODO: cache CMD_0101_0000_d16_Wr14_DGain
whismanoid 63:8f39d21d6157 645 // TODO: cache CMD_0110_0100_d16_Wr19_FlashAddr
whismanoid 63:8f39d21d6157 646 // TODO: cache CMD_0110_1000_d16_Wr1A_FlashDataIn
whismanoid 53:3d5a3d241a5e 647 }
whismanoid 53:3d5a3d241a5e 648 break;
whismanoid 63:8f39d21d6157 649 case 32: // 32-bit register size
whismanoid 63:8f39d21d6157 650 #warning "Not Verified Yet: MAX11043::RegWrite 32-bit"
whismanoid 53:3d5a3d241a5e 651 {
whismanoid 63:8f39d21d6157 652 // SPI 8+32 = 40-bit transfer
whismanoid 63:8f39d21d6157 653 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 63:8f39d21d6157 654 // SPI MOSI = 1aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 655 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 656 //
whismanoid 63:8f39d21d6157 657 size_t byteCount = 1 + (2 * 2);
whismanoid 63:8f39d21d6157 658 uint8_t mosiData[5];
whismanoid 63:8f39d21d6157 659 uint8_t misoData[5];
whismanoid 63:8f39d21d6157 660 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 661 mosiData[1] = (uint8_t)((regData >> 24) & 0xFF);
whismanoid 63:8f39d21d6157 662 mosiData[2] = (uint8_t)((regData >> 16) & 0xFF);
whismanoid 63:8f39d21d6157 663 mosiData[3] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 664 mosiData[4] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 665 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 666 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 667 // TODO: cache CMD_0101_1000_d32_Wr16_FilterCDataOut
whismanoid 63:8f39d21d6157 668 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 669 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 670 // }
whismanoid 63:8f39d21d6157 671 // TODO: cache CMD_0101_1100_d32_Wr17_FilterCDataIn
whismanoid 63:8f39d21d6157 672 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 673 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 674 // }
whismanoid 53:3d5a3d241a5e 675 }
whismanoid 53:3d5a3d241a5e 676 break;
whismanoid 53:3d5a3d241a5e 677 }
whismanoid 53:3d5a3d241a5e 678
whismanoid 53:3d5a3d241a5e 679 //----------------------------------------
whismanoid 53:3d5a3d241a5e 680 // success
whismanoid 53:3d5a3d241a5e 681 return 1;
whismanoid 53:3d5a3d241a5e 682 }
whismanoid 53:3d5a3d241a5e 683
whismanoid 53:3d5a3d241a5e 684 //----------------------------------------
whismanoid 53:3d5a3d241a5e 685 // Read an 8-bit MAX11043 register
whismanoid 53:3d5a3d241a5e 686 //
whismanoid 57:1c9da8e90737 687 // CMDOP_1aaa_aaaa_ReadRegister bit is set 1 indicating a read operation.
whismanoid 53:3d5a3d241a5e 688 //
whismanoid 53:3d5a3d241a5e 689 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 690 //
whismanoid 53:3d5a3d241a5e 691 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 692 //
whismanoid 53:3d5a3d241a5e 693 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 694 //
whismanoid 53:3d5a3d241a5e 695 // SPI MOSI = 1aaa_aaaa_0000_0000
whismanoid 53:3d5a3d241a5e 696 //
whismanoid 53:3d5a3d241a5e 697 // SPI MISO = xxxx_xxxx_dddd_dddd
whismanoid 53:3d5a3d241a5e 698 //
whismanoid 53:3d5a3d241a5e 699 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 700 //
whismanoid 53:3d5a3d241a5e 701 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 702 //
whismanoid 53:3d5a3d241a5e 703 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 704 //
whismanoid 53:3d5a3d241a5e 705 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 706 //
whismanoid 53:3d5a3d241a5e 707 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 708 //
whismanoid 53:3d5a3d241a5e 709 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 710 //
whismanoid 53:3d5a3d241a5e 711 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 712 //
whismanoid 53:3d5a3d241a5e 713 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 714 //
whismanoid 53:3d5a3d241a5e 715 //
whismanoid 53:3d5a3d241a5e 716 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 717 uint8_t MAX11043::RegRead(MAX11043_CMD_enum_t commandByte, uint32_t* ptrRegData)
whismanoid 53:3d5a3d241a5e 718 {
whismanoid 53:3d5a3d241a5e 719
whismanoid 53:3d5a3d241a5e 720 //----------------------------------------
whismanoid 53:3d5a3d241a5e 721 // switch based on register address szie RegSize(regAddress)
whismanoid 57:1c9da8e90737 722 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 723 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 724 {
whismanoid 53:3d5a3d241a5e 725 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 726 {
whismanoid 60:d1d1eaa90fb7 727 // SPI 8+8 = 16-bit transfer
whismanoid 62:8223a7253c90 728 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 729 // SPI MOSI = 1aaa_aaaa_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 730 // SPI MISO = xxxx_xxxx_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 731 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 732 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 733 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 734 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 735 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 736 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 737 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 738 if (ptrRegData) { (*ptrRegData) = misoData[1]; }
whismanoid 59:47538bcf6cda 739 if (commandByte == CMD_0001_1110_d8_Rd07_Status) {
whismanoid 59:47538bcf6cda 740 // TODO1: update status
whismanoid 63:8f39d21d6157 741 status = misoData[1];
whismanoid 59:47538bcf6cda 742 }
whismanoid 53:3d5a3d241a5e 743 }
whismanoid 53:3d5a3d241a5e 744 break;
whismanoid 53:3d5a3d241a5e 745 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 746 #warning "Not Verified Yet: MAX11043::RegRead 16-bit"
whismanoid 53:3d5a3d241a5e 747 {
whismanoid 60:d1d1eaa90fb7 748 // SPI 8+16 = 24-bit transfer
whismanoid 62:8223a7253c90 749 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 60:d1d1eaa90fb7 750 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 751 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 752 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 753 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 754 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 755 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 756 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 757 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 758 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 759 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 760 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 59:47538bcf6cda 761 if (commandByte == CMD_0010_0010_d16_Rd08_Configuration) {
whismanoid 59:47538bcf6cda 762 // TODO1: update config
whismanoid 63:8f39d21d6157 763 config = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 764 }
whismanoid 59:47538bcf6cda 765 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 766 // TODO1: update adca
whismanoid 63:8f39d21d6157 767 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 768 }
whismanoid 59:47538bcf6cda 769 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 770 // TODO1: update adcb
whismanoid 63:8f39d21d6157 771 adcb = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 772 }
whismanoid 59:47538bcf6cda 773 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 774 // TODO1: update adcc
whismanoid 63:8f39d21d6157 775 adcc = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 776 }
whismanoid 59:47538bcf6cda 777 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 778 // TODO1: update adcd
whismanoid 63:8f39d21d6157 779 adcd = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 780 }
whismanoid 53:3d5a3d241a5e 781 }
whismanoid 53:3d5a3d241a5e 782 break;
whismanoid 53:3d5a3d241a5e 783 case 24: // 24-bit register size
whismanoid 53:3d5a3d241a5e 784 {
whismanoid 60:d1d1eaa90fb7 785 // SPI 8+24 = 32-bit transfer
whismanoid 62:8223a7253c90 786 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32
whismanoid 63:8f39d21d6157 787 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 788 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 789 size_t byteCount = 1 + 3;
whismanoid 63:8f39d21d6157 790 uint8_t mosiData[4];
whismanoid 63:8f39d21d6157 791 uint8_t misoData[4];
whismanoid 63:8f39d21d6157 792 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 793 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 794 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 795 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 796 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 797 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 798 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 59:47538bcf6cda 799 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 800 // TODO1: update adca
whismanoid 63:8f39d21d6157 801 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 802 }
whismanoid 59:47538bcf6cda 803 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 804 // TODO1: update adcb
whismanoid 63:8f39d21d6157 805 adcb = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 806 }
whismanoid 59:47538bcf6cda 807 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 808 // TODO1: update adcc
whismanoid 63:8f39d21d6157 809 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 810 }
whismanoid 59:47538bcf6cda 811 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 812 // TODO1: update adcd
whismanoid 63:8f39d21d6157 813 adcd = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 814 }
whismanoid 59:47538bcf6cda 815 }
whismanoid 59:47538bcf6cda 816 break;
whismanoid 63:8f39d21d6157 817 case 32: // 32-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 818 //
whismanoid 63:8f39d21d6157 819 #warning "Not Implemented Yet: MAX11043::RegRead 32-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 820 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 821 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 822 // update adca, adcb
whismanoid 59:47538bcf6cda 823 //
whismanoid 63:8f39d21d6157 824 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 825 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 826 // update adcc, adcd
whismanoid 59:47538bcf6cda 827 //
whismanoid 59:47538bcf6cda 828 {
whismanoid 60:d1d1eaa90fb7 829 // SPI 8+32 = 40-bit transfer
whismanoid 62:8223a7253c90 830 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 60:d1d1eaa90fb7 831 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 832 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 833 size_t byteCount = 1 + (2 * 2);
whismanoid 62:8223a7253c90 834 uint8_t mosiData[5];
whismanoid 62:8223a7253c90 835 uint8_t misoData[5];
whismanoid 62:8223a7253c90 836 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 837 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 838 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 839 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 840 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 841 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 842 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 843 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 844 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 845 // TODO1: update adca
whismanoid 62:8223a7253c90 846 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 847 // TODO1: update adcb
whismanoid 62:8223a7253c90 848 adcb = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 849 }
whismanoid 63:8f39d21d6157 850 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 851 // TODO1: update adcc
whismanoid 62:8223a7253c90 852 adcc = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 853 // TODO1: update adcd
whismanoid 62:8223a7253c90 854 adcd = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 855 }
whismanoid 59:47538bcf6cda 856 }
whismanoid 59:47538bcf6cda 857 break;
whismanoid 63:8f39d21d6157 858 case 48: // 48-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 859 //
whismanoid 63:8f39d21d6157 860 #warning "Not Verified Yet: MAX11043::RegRead 48-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 861 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 862 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 863 // update adca, adcb
whismanoid 59:47538bcf6cda 864 //
whismanoid 63:8f39d21d6157 865 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 866 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 867 // update adcc, adcd
whismanoid 59:47538bcf6cda 868 //
whismanoid 59:47538bcf6cda 869 {
whismanoid 60:d1d1eaa90fb7 870 // SPI 8+48 = 56-bit transfer
whismanoid 62:8223a7253c90 871 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56
whismanoid 60:d1d1eaa90fb7 872 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 873 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 874 size_t byteCount = 1 + (3 * 2);
whismanoid 62:8223a7253c90 875 uint8_t mosiData[7];
whismanoid 62:8223a7253c90 876 uint8_t misoData[7];
whismanoid 62:8223a7253c90 877 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 878 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 879 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 880 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 881 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 882 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 883 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 884 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 885 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 886 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 887 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 888 // TODO1: update adca
whismanoid 62:8223a7253c90 889 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 890 // TODO1: update adcb
whismanoid 62:8223a7253c90 891 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 892 }
whismanoid 63:8f39d21d6157 893 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 894 // TODO1: update adcc
whismanoid 62:8223a7253c90 895 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 896 // TODO1: update adcd
whismanoid 62:8223a7253c90 897 adcd = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 898 }
whismanoid 59:47538bcf6cda 899 }
whismanoid 59:47538bcf6cda 900 break;
whismanoid 63:8f39d21d6157 901 case 64: // 64-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 902 //
whismanoid 63:8f39d21d6157 903 #warning "Not Verified Yet: MAX11043::RegRead 64-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 904 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 905 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 906 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 907 //
whismanoid 59:47538bcf6cda 908 {
whismanoid 60:d1d1eaa90fb7 909 // SPI 8+64 = 72-bit transfer
whismanoid 62:8223a7253c90 910 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72
whismanoid 60:d1d1eaa90fb7 911 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 912 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 913 size_t byteCount = 1 + (2 * 4);
whismanoid 62:8223a7253c90 914 uint8_t mosiData[9];
whismanoid 62:8223a7253c90 915 uint8_t misoData[9];
whismanoid 62:8223a7253c90 916 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 917 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 918 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 919 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 920 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 921 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 922 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 923 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 924 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 925 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 926 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 927 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 928 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 929 // TODO1: update adca
whismanoid 62:8223a7253c90 930 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 931 // TODO1: update adcb
whismanoid 62:8223a7253c90 932 adcb = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 933 // TODO1: update adcc
whismanoid 62:8223a7253c90 934 adcc = (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 935 // TODO1: update adcd
whismanoid 62:8223a7253c90 936 adcd = (misoData[7] << 8) | misoData[8];
whismanoid 59:47538bcf6cda 937 }
whismanoid 59:47538bcf6cda 938 }
whismanoid 59:47538bcf6cda 939 break;
whismanoid 63:8f39d21d6157 940 case 96: // 96-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 941 //
whismanoid 63:8f39d21d6157 942 #warning "Not Verified Yet: MAX11043::RegRead 96-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 943 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 944 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 945 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 946 //
whismanoid 59:47538bcf6cda 947 {
whismanoid 60:d1d1eaa90fb7 948 // SPI 8+96 = 104-bit transfer
whismanoid 62:8223a7253c90 949 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72 ___[9]_80 __[10]_88 __[11]_96 __[12]104
whismanoid 60:d1d1eaa90fb7 950 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 951 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 952 size_t byteCount = 1 + (3 * 4);
whismanoid 62:8223a7253c90 953 uint8_t mosiData[13];
whismanoid 62:8223a7253c90 954 uint8_t misoData[13];
whismanoid 62:8223a7253c90 955 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 956 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 957 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 958 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 959 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 960 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 961 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 962 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 963 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 964 mosiData[9] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 965 mosiData[10] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 966 mosiData[11] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 967 mosiData[12] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 968 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 969 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 970 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 971 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 972 // TODO1: update adca
whismanoid 62:8223a7253c90 973 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 974 // TODO1: update adcb
whismanoid 62:8223a7253c90 975 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 976 // TODO1: update adcc
whismanoid 62:8223a7253c90 977 adcc = (misoData[7] << 16) | (misoData[8] << 8) | misoData[9];
whismanoid 59:47538bcf6cda 978 // TODO1: update adcd
whismanoid 62:8223a7253c90 979 adcd = (misoData[10] << 16) | (misoData[11] << 8) | misoData[12];
whismanoid 59:47538bcf6cda 980 }
whismanoid 53:3d5a3d241a5e 981 }
whismanoid 53:3d5a3d241a5e 982 break;
whismanoid 53:3d5a3d241a5e 983 }
whismanoid 53:3d5a3d241a5e 984
whismanoid 53:3d5a3d241a5e 985 //----------------------------------------
whismanoid 53:3d5a3d241a5e 986 // success
whismanoid 53:3d5a3d241a5e 987 return 1;
whismanoid 53:3d5a3d241a5e 988 }
whismanoid 53:3d5a3d241a5e 989
whismanoid 53:3d5a3d241a5e 990 //----------------------------------------
whismanoid 53:3d5a3d241a5e 991 // Return the size of a MAX11043 register
whismanoid 53:3d5a3d241a5e 992 //
whismanoid 53:3d5a3d241a5e 993 // @return 8 for 8-bit, 16 for 16-bit, 24 for 24-bit, else 0 for undefined register size
whismanoid 53:3d5a3d241a5e 994 uint8_t MAX11043::RegSize(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 995 {
whismanoid 53:3d5a3d241a5e 996
whismanoid 53:3d5a3d241a5e 997 //----------------------------------------
whismanoid 53:3d5a3d241a5e 998 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 999 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 1000 switch(commandByte)
whismanoid 53:3d5a3d241a5e 1001 {
whismanoid 53:3d5a3d241a5e 1002 default:
whismanoid 57:1c9da8e90737 1003 // case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 1004 // case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 1005 // case CMDOP_1111_1111_NoOperationMOSIidleHigh:
whismanoid 53:3d5a3d241a5e 1006 return 0; // undefined register size
whismanoid 53:3d5a3d241a5e 1007 case CMD_0001_1110_d8_Rd07_Status:
whismanoid 53:3d5a3d241a5e 1008 case CMD_0101_0100_d8_Wr15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 1009 case CMD_0101_0110_d8_Rd15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 1010 case CMD_0110_0000_d8_Wr18_FlashMode:
whismanoid 53:3d5a3d241a5e 1011 case CMD_0110_0010_d8_Rd18_FlashMode:
whismanoid 53:3d5a3d241a5e 1012 return 8; // 8-bit register size
whismanoid 53:3d5a3d241a5e 1013 case CMD_0010_0000_d16_Wr08_Configuration:
whismanoid 53:3d5a3d241a5e 1014 case CMD_0010_0010_d16_Rd08_Configuration:
whismanoid 53:3d5a3d241a5e 1015 case CMD_0010_0100_d16_Wr09_DAC:
whismanoid 53:3d5a3d241a5e 1016 case CMD_0010_0110_d16_Rd09_DAC:
whismanoid 53:3d5a3d241a5e 1017 case CMD_0010_1000_d16_Wr0A_DACStep:
whismanoid 53:3d5a3d241a5e 1018 case CMD_0010_1010_d16_Rd0A_DACStep:
whismanoid 53:3d5a3d241a5e 1019 case CMD_0010_1100_d16_Wr0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 1020 case CMD_0010_1110_d16_Rd0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 1021 case CMD_0011_0000_d16_Wr0C_ConfigA:
whismanoid 53:3d5a3d241a5e 1022 case CMD_0011_0010_d16_Rd0C_ConfigA:
whismanoid 53:3d5a3d241a5e 1023 case CMD_0011_0100_d16_Wr0D_ConfigB:
whismanoid 53:3d5a3d241a5e 1024 case CMD_0011_0110_d16_Rd0D_ConfigB:
whismanoid 53:3d5a3d241a5e 1025 case CMD_0011_1000_d16_Wr0E_ConfigC:
whismanoid 53:3d5a3d241a5e 1026 case CMD_0011_1010_d16_Rd0E_ConfigC:
whismanoid 53:3d5a3d241a5e 1027 case CMD_0011_1100_d16_Wr0F_ConfigD:
whismanoid 53:3d5a3d241a5e 1028 case CMD_0011_1110_d16_Rd0F_ConfigD:
whismanoid 53:3d5a3d241a5e 1029 case CMD_0100_0000_d16_Wr10_Reference:
whismanoid 53:3d5a3d241a5e 1030 case CMD_0100_0010_d16_Rd10_Reference:
whismanoid 53:3d5a3d241a5e 1031 case CMD_0100_0100_d16_Wr11_AGain:
whismanoid 53:3d5a3d241a5e 1032 case CMD_0100_0110_d16_Rd11_AGain:
whismanoid 53:3d5a3d241a5e 1033 case CMD_0100_1000_d16_Wr12_BGain:
whismanoid 53:3d5a3d241a5e 1034 case CMD_0100_1010_d16_Rd12_BGain:
whismanoid 53:3d5a3d241a5e 1035 case CMD_0100_1100_d16_Wr13_CGain:
whismanoid 53:3d5a3d241a5e 1036 case CMD_0100_1110_d16_Rd13_CGain:
whismanoid 53:3d5a3d241a5e 1037 case CMD_0101_0000_d16_Wr14_DGain:
whismanoid 53:3d5a3d241a5e 1038 case CMD_0101_0010_d16_Rd14_DGain:
whismanoid 53:3d5a3d241a5e 1039 case CMD_0110_0100_d16_Wr19_FlashAddr:
whismanoid 53:3d5a3d241a5e 1040 case CMD_0110_0110_d16_Rd19_FlashAddr:
whismanoid 53:3d5a3d241a5e 1041 case CMD_0110_1000_d16_Wr1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 1042 case CMD_0110_1010_d16_Rd1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 1043 case CMD_0110_1110_d16_Rd1B_FlashDataOut:
whismanoid 53:3d5a3d241a5e 1044 return 16; // 16-bit register size
whismanoid 59:47538bcf6cda 1045 case CMD_0000_0010_d16o8_Rd00_ADCa:
whismanoid 59:47538bcf6cda 1046 case CMD_0000_0110_d16o8_Rd01_ADCb:
whismanoid 59:47538bcf6cda 1047 case CMD_0000_1010_d16o8_Rd02_ADCc:
whismanoid 59:47538bcf6cda 1048 case CMD_0000_1110_d16o8_Rd03_ADCd:
whismanoid 59:47538bcf6cda 1049 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1050 {
whismanoid 59:47538bcf6cda 1051 // %SW 0x02 (0 0 0) -- for 24-bit read
whismanoid 59:47538bcf6cda 1052 return 24; // 24-bit register size
whismanoid 59:47538bcf6cda 1053 }
whismanoid 59:47538bcf6cda 1054 // %SW 0x02 (0 0) -- for 16-bit read
whismanoid 59:47538bcf6cda 1055 //
whismanoid 59:47538bcf6cda 1056 return 16; // 16-bit register size
whismanoid 63:8f39d21d6157 1057 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab:
whismanoid 63:8f39d21d6157 1058 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd:
whismanoid 59:47538bcf6cda 1059 //
whismanoid 59:47538bcf6cda 1060 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 1061 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1062 {
whismanoid 59:47538bcf6cda 1063 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 1064 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 1065 return 48; // 48-bit register size: 2*(24)
whismanoid 59:47538bcf6cda 1066 }
whismanoid 59:47538bcf6cda 1067 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 1068 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 1069 //
whismanoid 59:47538bcf6cda 1070 return 32; // 32-bit register size: 2*(16)
whismanoid 63:8f39d21d6157 1071 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd:
whismanoid 59:47538bcf6cda 1072 //
whismanoid 59:47538bcf6cda 1073 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 1074 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1075 {
whismanoid 59:47538bcf6cda 1076 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1077 return 96; // 96-bit register size: 4*(24)
whismanoid 59:47538bcf6cda 1078 }
whismanoid 59:47538bcf6cda 1079 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1080 //
whismanoid 59:47538bcf6cda 1081 return 64; // 64-bit register size: 4*(16)
whismanoid 53:3d5a3d241a5e 1082 case CMD_0101_1000_d32_Wr16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 1083 case CMD_0101_1010_d32_Rd16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 1084 case CMD_0101_1100_d32_Wr17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 1085 case CMD_0101_1110_d32_Rd17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 1086 return 32; // 32-bit register size
whismanoid 53:3d5a3d241a5e 1087 }
whismanoid 53:3d5a3d241a5e 1088 }
whismanoid 53:3d5a3d241a5e 1089
whismanoid 53:3d5a3d241a5e 1090 //----------------------------------------
whismanoid 57:1c9da8e90737 1091 // Decode operation from commandByte
whismanoid 57:1c9da8e90737 1092 //
whismanoid 57:1c9da8e90737 1093 // @return operation such as idle, read register, write register, etc.
whismanoid 57:1c9da8e90737 1094 MAX11043::MAX11043_CMDOP_enum_t MAX11043::DecodeCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 57:1c9da8e90737 1095 {
whismanoid 57:1c9da8e90737 1096
whismanoid 57:1c9da8e90737 1097 //----------------------------------------
whismanoid 57:1c9da8e90737 1098 // decode operation from command byte
whismanoid 57:1c9da8e90737 1099 switch (commandByte & 0x83)
whismanoid 57:1c9da8e90737 1100 {
whismanoid 57:1c9da8e90737 1101 case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 1102 return CMDOP_0aaa_aa10_ReadRegister;
whismanoid 57:1c9da8e90737 1103 case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 1104 return CMDOP_0aaa_aa00_WriteRegister;
whismanoid 57:1c9da8e90737 1105 default:
whismanoid 57:1c9da8e90737 1106 return CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 57:1c9da8e90737 1107 }
whismanoid 57:1c9da8e90737 1108 }
whismanoid 57:1c9da8e90737 1109
whismanoid 57:1c9da8e90737 1110 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1111 // Return the address field of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1112 //
whismanoid 53:3d5a3d241a5e 1113 // @return register address field as given in datasheet
whismanoid 53:3d5a3d241a5e 1114 uint8_t MAX11043::RegAddrOfCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1115 {
whismanoid 53:3d5a3d241a5e 1116
whismanoid 53:3d5a3d241a5e 1117 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1118 // extract register address value from command byte
whismanoid 57:1c9da8e90737 1119 return (uint8_t)((commandByte &~ 0x83) >> 2); // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 1120 }
whismanoid 53:3d5a3d241a5e 1121
whismanoid 53:3d5a3d241a5e 1122 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1123 // Test whether a command byte is a register read command
whismanoid 53:3d5a3d241a5e 1124 //
whismanoid 53:3d5a3d241a5e 1125 // @return true if command byte is a register read command
whismanoid 53:3d5a3d241a5e 1126 uint8_t MAX11043::IsRegReadCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1127 {
whismanoid 53:3d5a3d241a5e 1128
whismanoid 53:3d5a3d241a5e 1129 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1130 // Test whether a command byte is a register read command
whismanoid 57:1c9da8e90737 1131 return (commandByte &~ 0x02) ? 1 : 0; // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 1132 }
whismanoid 53:3d5a3d241a5e 1133
whismanoid 53:3d5a3d241a5e 1134 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1135 // Return the name of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1136 //
whismanoid 53:3d5a3d241a5e 1137 // @return null-terminated constant C string containing register name or empty string
whismanoid 53:3d5a3d241a5e 1138 const char* MAX11043::RegName(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1139 {
whismanoid 53:3d5a3d241a5e 1140
whismanoid 53:3d5a3d241a5e 1141 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1142 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 1143 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 1144 switch(commandByte)
whismanoid 53:3d5a3d241a5e 1145 {
whismanoid 53:3d5a3d241a5e 1146 default:
whismanoid 53:3d5a3d241a5e 1147 return ""; // undefined register
whismanoid 57:1c9da8e90737 1148 // case CMDOP_0aaa_aa00_WriteRegister: return "_______";
whismanoid 57:1c9da8e90737 1149 // case CMDOP_0aaa_aa10_ReadRegister: return "_______";
whismanoid 57:1c9da8e90737 1150 // case CMDOP_1111_1111_NoOperationMOSIidleHigh: return "_______";
whismanoid 59:47538bcf6cda 1151 case CMD_0000_0010_d16o8_Rd00_ADCa: return "ADCa";
whismanoid 59:47538bcf6cda 1152 case CMD_0000_0110_d16o8_Rd01_ADCb: return "ADCb";
whismanoid 59:47538bcf6cda 1153 case CMD_0000_1010_d16o8_Rd02_ADCc: return "ADCc";
whismanoid 59:47538bcf6cda 1154 case CMD_0000_1110_d16o8_Rd03_ADCd: return "ADCd";
whismanoid 63:8f39d21d6157 1155 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab: return "ADCab";
whismanoid 63:8f39d21d6157 1156 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd: return "ADCcd";
whismanoid 63:8f39d21d6157 1157 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd: return "ADCabcd";
whismanoid 53:3d5a3d241a5e 1158 case CMD_0001_1110_d8_Rd07_Status: return "Status";
whismanoid 53:3d5a3d241a5e 1159 case CMD_0010_0000_d16_Wr08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1160 case CMD_0010_0010_d16_Rd08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1161 case CMD_0010_0100_d16_Wr09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1162 case CMD_0010_0110_d16_Rd09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1163 case CMD_0010_1000_d16_Wr0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1164 case CMD_0010_1010_d16_Rd0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1165 case CMD_0010_1100_d16_Wr0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1166 case CMD_0010_1110_d16_Rd0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1167 case CMD_0011_0000_d16_Wr0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1168 case CMD_0011_0010_d16_Rd0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1169 case CMD_0011_0100_d16_Wr0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1170 case CMD_0011_0110_d16_Rd0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1171 case CMD_0011_1000_d16_Wr0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1172 case CMD_0011_1010_d16_Rd0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1173 case CMD_0011_1100_d16_Wr0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1174 case CMD_0011_1110_d16_Rd0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1175 case CMD_0100_0000_d16_Wr10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1176 case CMD_0100_0010_d16_Rd10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1177 case CMD_0100_0100_d16_Wr11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1178 case CMD_0100_0110_d16_Rd11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1179 case CMD_0100_1000_d16_Wr12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1180 case CMD_0100_1010_d16_Rd12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1181 case CMD_0100_1100_d16_Wr13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1182 case CMD_0100_1110_d16_Rd13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1183 case CMD_0101_0000_d16_Wr14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1184 case CMD_0101_0010_d16_Rd14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1185 case CMD_0101_0100_d8_Wr15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1186 case CMD_0101_0110_d8_Rd15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1187 case CMD_0101_1000_d32_Wr16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1188 case CMD_0101_1010_d32_Rd16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1189 case CMD_0101_1100_d32_Wr17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1190 case CMD_0101_1110_d32_Rd17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1191 case CMD_0110_0000_d8_Wr18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1192 case CMD_0110_0010_d8_Rd18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1193 case CMD_0110_0100_d16_Wr19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1194 case CMD_0110_0110_d16_Rd19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1195 case CMD_0110_1000_d16_Wr1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1196 case CMD_0110_1010_d16_Rd1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1197 case CMD_0110_1110_d16_Rd1B_FlashDataOut: return "FlashDataOut";
whismanoid 53:3d5a3d241a5e 1198 }
whismanoid 53:3d5a3d241a5e 1199 }
whismanoid 53:3d5a3d241a5e 1200
whismanoid 59:47538bcf6cda 1201 //----------------------------------------
whismanoid 64:a667cfd83492 1202 // Menu item '$' -> adca, adcb, adcc, adcd
whismanoid 64:a667cfd83492 1203 // Read ADCabcd
whismanoid 64:a667cfd83492 1204 //
whismanoid 64:a667cfd83492 1205 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1206 uint8_t MAX11043::Read_ADCabcd(void)
whismanoid 64:a667cfd83492 1207 {
whismanoid 64:a667cfd83492 1208
whismanoid 64:a667cfd83492 1209 //----------------------------------------
whismanoid 64:a667cfd83492 1210 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1211 #warning "Not Tested Yet: MAX11043::Read_ADCabcd..."
whismanoid 64:a667cfd83492 1212
whismanoid 69:989e392cf635 1213 //--------------------------------------------------
whismanoid 69:989e392cf635 1214 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 1215 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 1216 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 1217 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1218 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 1219 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 1220 // 2020-02-20 MAX11043_EOC_INTERRUPT_POLLING works on MAX32625MBED at 9us conversion rate, with 1us timing margin
whismanoid 69:989e392cf635 1221 // TODO: poll m_EOC_pin if CONVRUN is high
whismanoid 69:989e392cf635 1222 if (m_CONVRUN_pin)
whismanoid 69:989e392cf635 1223 {
whismanoid 69:989e392cf635 1224 #warning "MAX11043::Read_ADCabcd() Potential infinite loop if EOC pin not connected"
whismanoid 69:989e392cf635 1225 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 69:989e392cf635 1226 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 1227 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 1228 (m_EOC_pin != 1));
whismanoid 69:989e392cf635 1229 futility_countdown--)
whismanoid 69:989e392cf635 1230 {
whismanoid 69:989e392cf635 1231 // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 69:989e392cf635 1232 }
whismanoid 69:989e392cf635 1233 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 1234 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 1235 (m_EOC_pin != 0));
whismanoid 69:989e392cf635 1236 futility_countdown--)
whismanoid 69:989e392cf635 1237 {
whismanoid 69:989e392cf635 1238 // spinlock waiting for logic low pin state (new data is available)
whismanoid 69:989e392cf635 1239 }
whismanoid 69:989e392cf635 1240 }
whismanoid 69:989e392cf635 1241 else
whismanoid 69:989e392cf635 1242 {
whismanoid 69:989e392cf635 1243 // CONVRUN pin is being driven low, so conversion result will not change, EOC# remains high
whismanoid 69:989e392cf635 1244 }
whismanoid 69:989e392cf635 1245 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1246 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 1247 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1248 //--------------------------------------------------
whismanoid 69:989e392cf635 1249
whismanoid 64:a667cfd83492 1250 //----------------------------------------
whismanoid 64:a667cfd83492 1251 // read register ADCabcd -> &adca, &adcb, &adcc, &adcd
whismanoid 64:a667cfd83492 1252 RegRead(CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd, 0);
whismanoid 64:a667cfd83492 1253
whismanoid 64:a667cfd83492 1254 //----------------------------------------
whismanoid 64:a667cfd83492 1255 // success
whismanoid 64:a667cfd83492 1256 return 1;
whismanoid 64:a667cfd83492 1257 }
whismanoid 64:a667cfd83492 1258
whismanoid 64:a667cfd83492 1259 //----------------------------------------
whismanoid 66:3fe92f6f1cfa 1260 // Menu item 'GA'
whismanoid 64:a667cfd83492 1261 // Write AGain register
whismanoid 64:a667cfd83492 1262 //
whismanoid 64:a667cfd83492 1263 // @param[in] gain 2's complement, 0x800=0.25V/V, 0x1000=0.5V/V, 0x2000=1VV/V, 0x4000=2V/V, default=0x2000
whismanoid 64:a667cfd83492 1264 //
whismanoid 64:a667cfd83492 1265 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1266 uint8_t MAX11043::Write_AGain(uint32_t gain)
whismanoid 64:a667cfd83492 1267 {
whismanoid 64:a667cfd83492 1268
whismanoid 64:a667cfd83492 1269 //----------------------------------------
whismanoid 64:a667cfd83492 1270 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1271 #warning "Not Tested Yet: MAX11043::Write_AGain..."
whismanoid 64:a667cfd83492 1272
whismanoid 64:a667cfd83492 1273 //----------------------------------------
whismanoid 64:a667cfd83492 1274 // write register
whismanoid 64:a667cfd83492 1275 RegWrite(CMD_0100_0100_d16_Wr11_AGain, gain);
whismanoid 64:a667cfd83492 1276
whismanoid 64:a667cfd83492 1277 //----------------------------------------
whismanoid 64:a667cfd83492 1278 // success
whismanoid 64:a667cfd83492 1279 return 1;
whismanoid 64:a667cfd83492 1280 }
whismanoid 64:a667cfd83492 1281
whismanoid 64:a667cfd83492 1282 //----------------------------------------
whismanoid 59:47538bcf6cda 1283 // Menu item 'XX'
whismanoid 59:47538bcf6cda 1284 //
whismanoid 59:47538bcf6cda 1285 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1286 uint8_t MAX11043::Configure_XXXXX(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1287 {
whismanoid 59:47538bcf6cda 1288
whismanoid 59:47538bcf6cda 1289 //----------------------------------------
whismanoid 59:47538bcf6cda 1290 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1291 #warning "Not Tested Yet: MAX11043::Configure_XXXXX..."
whismanoid 59:47538bcf6cda 1292
whismanoid 59:47538bcf6cda 1293 //----------------------------------------
whismanoid 59:47538bcf6cda 1294 // read register
whismanoid 59:47538bcf6cda 1295 RegRead(CMD_0000_0010_d16o8_Rd00_ADCa, &adca);
whismanoid 59:47538bcf6cda 1296
whismanoid 59:47538bcf6cda 1297 //----------------------------------------
whismanoid 59:47538bcf6cda 1298 // success
whismanoid 59:47538bcf6cda 1299 return 1;
whismanoid 59:47538bcf6cda 1300 }
whismanoid 59:47538bcf6cda 1301
whismanoid 59:47538bcf6cda 1302 //----------------------------------------
whismanoid 59:47538bcf6cda 1303 // Menu item 'XY'
whismanoid 59:47538bcf6cda 1304 //
whismanoid 59:47538bcf6cda 1305 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1306 uint8_t MAX11043::Configure_XXXXY(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1307 {
whismanoid 59:47538bcf6cda 1308
whismanoid 59:47538bcf6cda 1309 //----------------------------------------
whismanoid 59:47538bcf6cda 1310 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1311 #warning "Not Tested Yet: MAX11043::Configure_XXXXY..."
whismanoid 59:47538bcf6cda 1312
whismanoid 59:47538bcf6cda 1313 //----------------------------------------
whismanoid 59:47538bcf6cda 1314 // read register
whismanoid 59:47538bcf6cda 1315 RegRead(CMD_0001_1110_d8_Rd07_Status, &status);
whismanoid 59:47538bcf6cda 1316
whismanoid 59:47538bcf6cda 1317 //----------------------------------------
whismanoid 59:47538bcf6cda 1318 // success
whismanoid 59:47538bcf6cda 1319 return 1;
whismanoid 59:47538bcf6cda 1320 }
whismanoid 59:47538bcf6cda 1321
whismanoid 53:3d5a3d241a5e 1322
whismanoid 53:3d5a3d241a5e 1323 // End of file