Mark Underwood / Mbed OS MAX11043_Serial_Tester

Test program running on MAX32625MBED. Control through USB Serial commands using a terminal emulator such as teraterm or putty.

Dependencies:   MaximTinyTester CmdLine MAX541 USBDevice

MAX11043/MAX11043.cpp@70:f44a577c9e59, 2020-02-21 (annotated)

Committer:
whismanoid
Date:
Fri Feb 21 10:40:45 2020 +0000
Revision:
70:f44a577c9e59
Parent:
69:989e392cf635
Child:
71:62bcd01ea87f
WIP #define MAX11043_EOC_INTERRUPT_POLLING 0; need test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 53:3d5a3d241a5e 1 // /*******************************************************************************
whismanoid 53:3d5a3d241a5e 2 // * Copyright (C) 2020 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 53:3d5a3d241a5e 3 // *
whismanoid 53:3d5a3d241a5e 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 53:3d5a3d241a5e 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 53:3d5a3d241a5e 6 // * to deal in the Software without restriction, including without limitation
whismanoid 53:3d5a3d241a5e 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 53:3d5a3d241a5e 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 53:3d5a3d241a5e 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 53:3d5a3d241a5e 10 // *
whismanoid 53:3d5a3d241a5e 11 // * The above copyright notice and this permission notice shall be included
whismanoid 53:3d5a3d241a5e 12 // * in all copies or substantial portions of the Software.
whismanoid 53:3d5a3d241a5e 13 // *
whismanoid 53:3d5a3d241a5e 14 // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid 53:3d5a3d241a5e 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 53:3d5a3d241a5e 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 53:3d5a3d241a5e 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 53:3d5a3d241a5e 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 53:3d5a3d241a5e 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 53:3d5a3d241a5e 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 53:3d5a3d241a5e 21 // *
whismanoid 53:3d5a3d241a5e 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 53:3d5a3d241a5e 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 53:3d5a3d241a5e 24 // * Products, Inc. Branding Policy.
whismanoid 53:3d5a3d241a5e 25 // *
whismanoid 53:3d5a3d241a5e 26 // * The mere transfer of this software does not imply any licenses
whismanoid 53:3d5a3d241a5e 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 53:3d5a3d241a5e 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 53:3d5a3d241a5e 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 53:3d5a3d241a5e 30 // * ownership rights.
whismanoid 53:3d5a3d241a5e 31 // *******************************************************************************
whismanoid 53:3d5a3d241a5e 32 // */
whismanoid 53:3d5a3d241a5e 33 // *********************************************************************
whismanoid 53:3d5a3d241a5e 34 // @file MAX11043.cpp
whismanoid 53:3d5a3d241a5e 35 // *********************************************************************
whismanoid 53:3d5a3d241a5e 36 // Device Driver file
whismanoid 53:3d5a3d241a5e 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid 53:3d5a3d241a5e 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 53:3d5a3d241a5e 39 // System Name = ExampleSystem
whismanoid 53:3d5a3d241a5e 40 // System Description = Device driver example
whismanoid 53:3d5a3d241a5e 41
whismanoid 53:3d5a3d241a5e 42 #include "MAX11043.h"
whismanoid 69:989e392cf635 43 //--------------------------------------------------
whismanoid 69:989e392cf635 44 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 45 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 46 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 47 #ifndef MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 48 #define MAX11043_EOC_INTERRUPT_POLLING 1
whismanoid 69:989e392cf635 49 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 50
whismanoid 53:3d5a3d241a5e 51 // Device Name = MAX11043
whismanoid 53:3d5a3d241a5e 52 // Device Description = 200ksps, Low-Power, Serial SPI 24-Bit, 4-Channel, Differential/Single-Ended Input, Simultaneous-Sampling SD ADC
whismanoid 53:3d5a3d241a5e 53 // Device DeviceBriefDescription = 24-bit 200ksps Delta-Sigma ADC
whismanoid 53:3d5a3d241a5e 54 // Device Manufacturer = Maxim Integrated
whismanoid 53:3d5a3d241a5e 55 // Device PartNumber = MAX11043ATL+
whismanoid 53:3d5a3d241a5e 56 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 53:3d5a3d241a5e 57 //
whismanoid 53:3d5a3d241a5e 58 // ADC MaxOutputDataRate = 200ksps
whismanoid 53:3d5a3d241a5e 59 // ADC NumChannels = 4
whismanoid 53:3d5a3d241a5e 60 // ADC ResolutionBits = 24
whismanoid 53:3d5a3d241a5e 61 //
whismanoid 53:3d5a3d241a5e 62 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 63 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 64 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 65 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 66 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 67 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 68 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 69 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 70 //
whismanoid 53:3d5a3d241a5e 71 // InputPin Name = CONVRUN
whismanoid 53:3d5a3d241a5e 72 // InputPin Description = CONVRUN (digital input). Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 53:3d5a3d241a5e 73 // CONVRUN is low.
whismanoid 53:3d5a3d241a5e 74 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 75 //
whismanoid 53:3d5a3d241a5e 76 // InputPin Name = SHDN
whismanoid 53:3d5a3d241a5e 77 // InputPin Description = Shutdown (digital input). Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 53:3d5a3d241a5e 78 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 79 //
whismanoid 53:3d5a3d241a5e 80 // InputPin Name = DACSTEP
whismanoid 53:3d5a3d241a5e 81 // InputPin Description = DACSTEP (digital input). DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 53:3d5a3d241a5e 82 // edge of the system clock.
whismanoid 53:3d5a3d241a5e 83 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 84 //
whismanoid 53:3d5a3d241a5e 85 // InputPin Name = UP/DWN#
whismanoid 53:3d5a3d241a5e 86 // InputPin Description = UP/DWN# (digital input). DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 53:3d5a3d241a5e 87 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 88 //
whismanoid 53:3d5a3d241a5e 89 // OutputPin Name = EOC
whismanoid 53:3d5a3d241a5e 90 // OutputPin Description = End of Conversion Output. Active-Low End-of-Conversion Indicator. EOC asserts low to indicate that new data is ready.
whismanoid 53:3d5a3d241a5e 91 // OutputPin Function = Event
whismanoid 53:3d5a3d241a5e 92 //
whismanoid 58:2fea32db466b 93 // SupplyPin Name = AVDD
whismanoid 58:2fea32db466b 94 // SupplyPin Description = Analog Power-Supply Input. Bypass each AVDD with a nominal 1uF capacitor to AGND.
whismanoid 58:2fea32db466b 95 // SupplyPin VinMax = 3.60
whismanoid 58:2fea32db466b 96 // SupplyPin VinMin = 3.00
whismanoid 58:2fea32db466b 97 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 98 //
whismanoid 58:2fea32db466b 99 // SupplyPin Name = AGND
whismanoid 58:2fea32db466b 100 // SupplyPin Description = Analog Ground. Connect all AGND inputs together.
whismanoid 58:2fea32db466b 101 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 102 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 103 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 104 //
whismanoid 58:2fea32db466b 105 // SupplyPin Name = DGND
whismanoid 58:2fea32db466b 106 // SupplyPin Description = Digital Ground. Connect all DGND inputs together.
whismanoid 58:2fea32db466b 107 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 108 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 109 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 110 //
whismanoid 58:2fea32db466b 111 // SupplyPin Name = DVDD
whismanoid 58:2fea32db466b 112 // SupplyPin Description = Digital Power-Supply Input. Bypass each DVDD with a nominal 1uF capacitor to DGND.
whismanoid 58:2fea32db466b 113 // SupplyPin VinMax = 3.60 (*TODO PENDING VERIFICATION*)
whismanoid 58:2fea32db466b 114 // SupplyPin VinMin = 3.00 (*TODO PENDING VERIFICATION*)
whismanoid 58:2fea32db466b 115 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 116 //
whismanoid 58:2fea32db466b 117 // SupplyPin Name = DVREG
whismanoid 58:2fea32db466b 118 // SupplyPin Description = Regulated Digital Core Supply (from internal +2.5V regulator). Bypass DVREG to DGND with a 10uF capacitor.
whismanoid 58:2fea32db466b 119 // SupplyPin VinMax = 2.50
whismanoid 58:2fea32db466b 120 // SupplyPin VinMin = 2.50
whismanoid 58:2fea32db466b 121 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 122 //
whismanoid 53:3d5a3d241a5e 123
whismanoid 53:3d5a3d241a5e 124 // CODE GENERATOR: class constructor definition
whismanoid 53:3d5a3d241a5e 125 MAX11043::MAX11043(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 53:3d5a3d241a5e 126 // CODE GENERATOR: class constructor definition gpio InputPin pins
whismanoid 53:3d5a3d241a5e 127 DigitalOut &CONVRUN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 128 DigitalOut &SHDN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 129 DigitalOut &DACSTEP_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 130 DigitalOut &UP_slash_DWNb_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 131 // CODE GENERATOR: class constructor definition gpio OutputPin pins
whismanoid 69:989e392cf635 132 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 133 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 134 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 135 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 136 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 53:3d5a3d241a5e 137 DigitalIn &EOC_pin, // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 138 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 139 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 140 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 69:989e392cf635 141 InterruptIn &EOC_pin, // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 142 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 143 // CODE GENERATOR: class constructor definition ic_variant
whismanoid 53:3d5a3d241a5e 144 MAX11043_ic_t ic_variant)
whismanoid 53:3d5a3d241a5e 145 // CODE GENERATOR: class constructor initializer list
whismanoid 53:3d5a3d241a5e 146 : m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid 53:3d5a3d241a5e 147 // CODE GENERATOR: class constructor initializer list gpio InputPin pins
whismanoid 53:3d5a3d241a5e 148 m_CONVRUN_pin(CONVRUN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 149 m_SHDN_pin(SHDN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 150 m_DACSTEP_pin(DACSTEP_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 151 m_UP_slash_DWNb_pin(UP_slash_DWNb_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 152 // CODE GENERATOR: class constructor initializer list gpio OutputPin pins
whismanoid 69:989e392cf635 153 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 154 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 155 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 156 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 53:3d5a3d241a5e 157 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 158 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 159 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 70:f44a577c9e59 160 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 161 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 162 // CODE GENERATOR: class constructor initializer list ic_variant
whismanoid 53:3d5a3d241a5e 163 m_ic_variant(ic_variant)
whismanoid 53:3d5a3d241a5e 164 {
whismanoid 53:3d5a3d241a5e 165 // CODE GENERATOR: class constructor definition SPI interface initialization
whismanoid 53:3d5a3d241a5e 166 //
whismanoid 53:3d5a3d241a5e 167 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 168 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 169 m_SPI_cs_state = 1;
whismanoid 67:5b8a495dda1c 170 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 171 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 172 }
whismanoid 53:3d5a3d241a5e 173
whismanoid 53:3d5a3d241a5e 174 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 175 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 176 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 177 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 178 m_SPI_dataMode = 0; //SPI_MODE0; // CPOL=0,CPHA=0: Rising Edge stable; SCLK idle Low
whismanoid 53:3d5a3d241a5e 179 m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid 53:3d5a3d241a5e 180
whismanoid 53:3d5a3d241a5e 181 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 182 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 183 //#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid 53:3d5a3d241a5e 184 //#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid 53:3d5a3d241a5e 185 //#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid 53:3d5a3d241a5e 186 //#define SPI_SCLK_Hz 6000000 // 6MHz
whismanoid 53:3d5a3d241a5e 187 //#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid 53:3d5a3d241a5e 188 //#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid 53:3d5a3d241a5e 189 //#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid 61:b4f3051578ef 190 m_SPI_SCLK_Hz = 24000000; // platform limit 24MHz; MAX11043 limit is 40MHz
whismanoid 53:3d5a3d241a5e 191 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 192
whismanoid 53:3d5a3d241a5e 193 //
whismanoid 53:3d5a3d241a5e 194 // CODE GENERATOR: class constructor definition gpio InputPin (Input to device) initialization
whismanoid 53:3d5a3d241a5e 195 //
whismanoid 53:3d5a3d241a5e 196 // CONVRUN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 197 m_CONVRUN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 198 //
whismanoid 53:3d5a3d241a5e 199 // SHDN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 200 m_SHDN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 201 //
whismanoid 53:3d5a3d241a5e 202 // DACSTEP Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 203 m_DACSTEP_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 204 //
whismanoid 53:3d5a3d241a5e 205 // UP_slash_DWNb Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 206 m_UP_slash_DWNb_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 207 //
whismanoid 53:3d5a3d241a5e 208 // CODE GENERATOR: class constructor definition gpio OutputPin (Output from MAX11043 device) initialization
whismanoid 53:3d5a3d241a5e 209 //
whismanoid 53:3d5a3d241a5e 210 // EOC Event Output from device
whismanoid 69:989e392cf635 211 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 212 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 213 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 214 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 215 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 216 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 217 // TODO: onEOCFallingEdge: interrupt handler requires global object extern MAX11043 g_MAX11043_device
whismanoid 69:989e392cf635 218 InterruptIn interruptEOC(EOC_pin); // InterruptIn constructor requires PinName, not DigitalIn -- Error: No instance of constructor "mbed::InterruptIn::InterruptIn" matches the argument list in "MAX11043/MAX11043.cpp", Line: 187, Col: 31
whismanoid 69:989e392cf635 219 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 70:f44a577c9e59 220 extern void onEOCFallingEdge(void);
whismanoid 69:989e392cf635 221 interruptEOC.fall(&onEOCFallingEdge);
whismanoid 69:989e392cf635 222 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 223
whismanoid 53:3d5a3d241a5e 224 }
whismanoid 53:3d5a3d241a5e 225
whismanoid 69:989e392cf635 226 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 227 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 228 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 229 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 230 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 231 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 232 // Interrupt Handler: EOC Event Output from device
whismanoid 69:989e392cf635 233 void onEOCFallingEdge(void)
whismanoid 69:989e392cf635 234 {
whismanoid 69:989e392cf635 235 extern MAX11043 g_MAX11043_device;
whismanoid 69:989e392cf635 236 g_MAX11043_device.Read_ADCabcd();
whismanoid 69:989e392cf635 237 }
whismanoid 69:989e392cf635 238 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 239
whismanoid 53:3d5a3d241a5e 240 // CODE GENERATOR: class destructor definition
whismanoid 53:3d5a3d241a5e 241 MAX11043::~MAX11043()
whismanoid 53:3d5a3d241a5e 242 {
whismanoid 53:3d5a3d241a5e 243 // do nothing
whismanoid 53:3d5a3d241a5e 244 }
whismanoid 53:3d5a3d241a5e 245
whismanoid 53:3d5a3d241a5e 246 // CODE GENERATOR: spi_frequency setter definition
whismanoid 53:3d5a3d241a5e 247 /// set SPI SCLK frequency
whismanoid 53:3d5a3d241a5e 248 void MAX11043::spi_frequency(int spi_sclk_Hz)
whismanoid 53:3d5a3d241a5e 249 {
whismanoid 53:3d5a3d241a5e 250 m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid 53:3d5a3d241a5e 251 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 252 }
whismanoid 53:3d5a3d241a5e 253
whismanoid 53:3d5a3d241a5e 254 // CODE GENERATOR: omit global g_MAX11043_device
whismanoid 53:3d5a3d241a5e 255 // CODE GENERATOR: extern function declarations
whismanoid 53:3d5a3d241a5e 256 // CODE GENERATOR: extern function requirement MAX11043::SPIoutputCS
whismanoid 53:3d5a3d241a5e 257 // Assert SPI Chip Select
whismanoid 53:3d5a3d241a5e 258 // SPI chip-select for MAX11043
whismanoid 53:3d5a3d241a5e 259 //
whismanoid 62:8223a7253c90 260 inline void MAX11043::SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 261 {
whismanoid 53:3d5a3d241a5e 262 // CODE GENERATOR: extern function definition for function SPIoutputCS
whismanoid 53:3d5a3d241a5e 263 // CODE GENERATOR: extern function definition for standard SPI interface function SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 264 m_SPI_cs_state = isLogicHigh;
whismanoid 67:5b8a495dda1c 265 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 266 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 267 }
whismanoid 53:3d5a3d241a5e 268 }
whismanoid 53:3d5a3d241a5e 269
whismanoid 62:8223a7253c90 270 // CODE GENERATOR: extern function requirement MAX11043::SPIreadWriteWithLowCS
whismanoid 62:8223a7253c90 271 // SPI read and write arbitrary number of 8-bit bytes
whismanoid 62:8223a7253c90 272 // SPI interface to MAX11043 shift mosiData into MAX11043 DIN
whismanoid 62:8223a7253c90 273 // while simultaneously capturing miso data from MAX11043 DOUT
whismanoid 62:8223a7253c90 274 //
whismanoid 62:8223a7253c90 275 int MAX11043::SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 276 {
whismanoid 62:8223a7253c90 277 // CODE GENERATOR: extern function definition for function SPIreadWriteWithLowCS
whismanoid 63:8f39d21d6157 278 // TODO1: CODE GENERATOR: extern function definition for standard SPI interface function SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 279 //size_t byteCount = 4;
whismanoid 62:8223a7253c90 280 //static char mosiData[4];
whismanoid 62:8223a7253c90 281 //static char misoData[4];
whismanoid 62:8223a7253c90 282 //
whismanoid 62:8223a7253c90 283 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 284 //~ noInterrupts();
whismanoid 62:8223a7253c90 285 //
whismanoid 62:8223a7253c90 286 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 287 //
whismanoid 67:5b8a495dda1c 288 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 289 m_cs_pin = 0;
whismanoid 67:5b8a495dda1c 290 }
whismanoid 62:8223a7253c90 291 unsigned int numBytesTransferred = m_spi.write((char*)mosiData, byteCount, (char*)misoData, byteCount);
whismanoid 67:5b8a495dda1c 292 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 293 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 294 }
whismanoid 62:8223a7253c90 295 //
whismanoid 62:8223a7253c90 296 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 297 //
whismanoid 62:8223a7253c90 298 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 299 //~ interrupts();
whismanoid 62:8223a7253c90 300 // Optional Diagnostic function to print SPI transactions
whismanoid 62:8223a7253c90 301 if (onSPIprint)
whismanoid 62:8223a7253c90 302 {
whismanoid 62:8223a7253c90 303 onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
whismanoid 62:8223a7253c90 304 }
whismanoid 62:8223a7253c90 305 return numBytesTransferred;
whismanoid 62:8223a7253c90 306 }
whismanoid 62:8223a7253c90 307
whismanoid 53:3d5a3d241a5e 308 // TODO1: CODE GENERATOR: extern function GPIOoutputSHDN alias SHDNoutputValue
whismanoid 53:3d5a3d241a5e 309 // CODE GENERATOR: extern function requirement MAX11043::SHDNoutputValue
whismanoid 58:2fea32db466b 310 // Assert MAX11043 SHDN pin : High = Shut Down, Low = Normal Operation.
whismanoid 53:3d5a3d241a5e 311 //
whismanoid 53:3d5a3d241a5e 312 void MAX11043::SHDNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 313 {
whismanoid 53:3d5a3d241a5e 314 // CODE GENERATOR: extern function definition for function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 315 // TODO1: CODE GENERATOR: extern function definition for gpio interface function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 316 // TODO1: CODE GENERATOR: gpio pin SHDN assuming member function m_SHDN_pin
whismanoid 53:3d5a3d241a5e 317 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 318 // m_SHDN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 319 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 320 m_SHDN_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 321 }
whismanoid 52:607010f0c54e 322
whismanoid 53:3d5a3d241a5e 323 // TODO1: CODE GENERATOR: extern function GPIOoutputCONVRUN alias CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 324 // CODE GENERATOR: extern function requirement MAX11043::CONVRUNoutputValue
whismanoid 58:2fea32db466b 325 // Assert MAX11043 CONVRUN pin : High = start continuous conversions on all 4 channels, Low = Idle.
whismanoid 53:3d5a3d241a5e 326 //
whismanoid 53:3d5a3d241a5e 327 void MAX11043::CONVRUNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 328 {
whismanoid 53:3d5a3d241a5e 329 // CODE GENERATOR: extern function definition for function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 330 // TODO1: CODE GENERATOR: extern function definition for gpio interface function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 331 // TODO1: CODE GENERATOR: gpio pin CONVRUN assuming member function m_CONVRUN_pin
whismanoid 53:3d5a3d241a5e 332 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 333 // m_CONVRUN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 334 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 335 m_CONVRUN_pin = isLogicHigh;
whismanoid 69:989e392cf635 336 //--------------------------------------------------
whismanoid 69:989e392cf635 337 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 338 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 339 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 340 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 341 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 342 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 343 if (m_CONVRUN_pin)
whismanoid 69:989e392cf635 344 {
whismanoid 69:989e392cf635 345 // CONVRUN was switched high, EOC# will now begin toggling
whismanoid 69:989e392cf635 346 }
whismanoid 69:989e392cf635 347 else
whismanoid 69:989e392cf635 348 {
whismanoid 69:989e392cf635 349 // CONVRUN was switched low, so wait until EOC# returns high
whismanoid 69:989e392cf635 350 #warning "MAX11043::Read_ADCabcd() Potential infinite loop if EOC pin not connected"
whismanoid 69:989e392cf635 351 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 69:989e392cf635 352 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 353 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 354 (m_EOC_pin != 1));
whismanoid 69:989e392cf635 355 futility_countdown--)
whismanoid 69:989e392cf635 356 {
whismanoid 69:989e392cf635 357 // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 69:989e392cf635 358 }
whismanoid 69:989e392cf635 359 }
whismanoid 69:989e392cf635 360 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 361 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 362 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 363 //--------------------------------------------------
whismanoid 53:3d5a3d241a5e 364 }
whismanoid 53:3d5a3d241a5e 365
whismanoid 53:3d5a3d241a5e 366 // TODO1: CODE GENERATOR: extern function GPIOoutputDACSTEP alias DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 367 // CODE GENERATOR: extern function requirement MAX11043::DACSTEPoutputValue
whismanoid 58:2fea32db466b 368 // Assert MAX11043 DACSTEP pin : High = Active, Low = Idle.
whismanoid 53:3d5a3d241a5e 369 //
whismanoid 53:3d5a3d241a5e 370 void MAX11043::DACSTEPoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 371 {
whismanoid 53:3d5a3d241a5e 372 // CODE GENERATOR: extern function definition for function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 373 // TODO1: CODE GENERATOR: extern function definition for gpio interface function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 374 // TODO1: CODE GENERATOR: gpio pin DACSTEP assuming member function m_DACSTEP_pin
whismanoid 53:3d5a3d241a5e 375 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 376 // m_DACSTEP_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 377 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 378 m_DACSTEP_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 379 }
whismanoid 53:3d5a3d241a5e 380
whismanoid 53:3d5a3d241a5e 381 // TODO1: CODE GENERATOR: extern function GPIOoutputUP_slash_DWNb alias UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 382 // CODE GENERATOR: extern function requirement MAX11043::UP_slash_DWNboutputValue
whismanoid 58:2fea32db466b 383 // Assert MAX11043 UP_slash_DWNb pin : High = Up, Low = Down.
whismanoid 53:3d5a3d241a5e 384 //
whismanoid 53:3d5a3d241a5e 385 void MAX11043::UP_slash_DWNboutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 386 {
whismanoid 53:3d5a3d241a5e 387 // CODE GENERATOR: extern function definition for function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 388 // TODO1: CODE GENERATOR: extern function definition for gpio interface function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 389 // TODO1: CODE GENERATOR: gpio pin UP_slash_DWNb assuming member function m_UP_slash_DWNb_pin
whismanoid 53:3d5a3d241a5e 390 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 391 // m_UP_slash_DWNb_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 392 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 393 m_UP_slash_DWNb_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 394 }
whismanoid 53:3d5a3d241a5e 395
whismanoid 53:3d5a3d241a5e 396 // CODE GENERATOR: extern function requirement MAX11043::EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 397 // Wait for MAX11043 EOC pin low, indicating end of conversion.
whismanoid 53:3d5a3d241a5e 398 // Required when using any of the InternalClock modes.
whismanoid 53:3d5a3d241a5e 399 //
whismanoid 53:3d5a3d241a5e 400 void MAX11043::EOCinputWaitUntilLow()
whismanoid 53:3d5a3d241a5e 401 {
whismanoid 53:3d5a3d241a5e 402 // CODE GENERATOR: extern function definition for function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 403 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 404 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 405 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 406 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 407 // TODO1: CODE GENERATOR: gpio function WaitUntilLow
whismanoid 53:3d5a3d241a5e 408 while (m_EOC_pin != 0)
whismanoid 53:3d5a3d241a5e 409 {
whismanoid 53:3d5a3d241a5e 410 // spinlock waiting for logic low pin state
whismanoid 53:3d5a3d241a5e 411 }
whismanoid 53:3d5a3d241a5e 412 }
whismanoid 53:3d5a3d241a5e 413
whismanoid 53:3d5a3d241a5e 414 // CODE GENERATOR: extern function requirement MAX11043::EOCinputValue
whismanoid 53:3d5a3d241a5e 415 // Return the status of the MAX11043 EOC pin.
whismanoid 53:3d5a3d241a5e 416 //
whismanoid 53:3d5a3d241a5e 417 int MAX11043::EOCinputValue()
whismanoid 53:3d5a3d241a5e 418 {
whismanoid 53:3d5a3d241a5e 419 // CODE GENERATOR: extern function definition for function EOCinputValue
whismanoid 53:3d5a3d241a5e 420 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputValue
whismanoid 53:3d5a3d241a5e 421 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 422 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 423 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 424 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 425 return m_EOC_pin.read();
whismanoid 53:3d5a3d241a5e 426 }
whismanoid 53:3d5a3d241a5e 427
whismanoid 53:3d5a3d241a5e 428 // CODE GENERATOR: class member function definitions
whismanoid 53:3d5a3d241a5e 429 //----------------------------------------
whismanoid 53:3d5a3d241a5e 430 // Menu item '!'
whismanoid 53:3d5a3d241a5e 431 // Initialize device
whismanoid 53:3d5a3d241a5e 432 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 433 uint8_t MAX11043::Init(void)
whismanoid 53:3d5a3d241a5e 434 {
whismanoid 53:3d5a3d241a5e 435
whismanoid 53:3d5a3d241a5e 436 //----------------------------------------
whismanoid 59:47538bcf6cda 437 // reference voltage, in Volts
whismanoid 59:47538bcf6cda 438 VRef = 2.500;
whismanoid 59:47538bcf6cda 439
whismanoid 59:47538bcf6cda 440 //----------------------------------------
whismanoid 59:47538bcf6cda 441 // shadow of register config CMD_0010_0010_d16_Rd08_Configuration
whismanoid 59:47538bcf6cda 442 config = 0x6000;
whismanoid 59:47538bcf6cda 443
whismanoid 59:47538bcf6cda 444 //----------------------------------------
whismanoid 59:47538bcf6cda 445 // shadow of register status CMD_0001_1110_d8_Rd07_Status
whismanoid 59:47538bcf6cda 446 status = 0x00;
whismanoid 53:3d5a3d241a5e 447
whismanoid 53:3d5a3d241a5e 448 //----------------------------------------
whismanoid 59:47538bcf6cda 449 // shadow of register ADCa CMD_0000_0010_d16o8_Rd00_ADCa
whismanoid 59:47538bcf6cda 450 adca = 0x0000;
whismanoid 53:3d5a3d241a5e 451
whismanoid 53:3d5a3d241a5e 452 //----------------------------------------
whismanoid 59:47538bcf6cda 453 // shadow of register ADCb CMD_0000_0110_d16o8_Rd01_ADCb
whismanoid 59:47538bcf6cda 454 adcb = 0x0000;
whismanoid 59:47538bcf6cda 455
whismanoid 59:47538bcf6cda 456 //----------------------------------------
whismanoid 59:47538bcf6cda 457 // shadow of register ADCc CMD_0000_1010_d16o8_Rd02_ADCc
whismanoid 59:47538bcf6cda 458 adcc = 0x0000;
whismanoid 59:47538bcf6cda 459
whismanoid 59:47538bcf6cda 460 //----------------------------------------
whismanoid 59:47538bcf6cda 461 // shadow of register ADCd CMD_0000_1110_d16o8_Rd03_ADCd
whismanoid 59:47538bcf6cda 462 adcd = 0x0000;
whismanoid 53:3d5a3d241a5e 463
whismanoid 53:3d5a3d241a5e 464 //----------------------------------------
whismanoid 53:3d5a3d241a5e 465 // init (based on old EV kit GUI)
whismanoid 53:3d5a3d241a5e 466 #warning "Not Implemented Yet: MAX11043::Init init..."
whismanoid 53:3d5a3d241a5e 467 // bool bOpResult = false;
whismanoid 53:3d5a3d241a5e 468 // String FWVersionString = "00";
whismanoid 53:3d5a3d241a5e 469 // bool bDemoMode = true;
whismanoid 53:3d5a3d241a5e 470 // int scan_resolution = 0;
whismanoid 53:3d5a3d241a5e 471 // int scan_channels = 0;
whismanoid 53:3d5a3d241a5e 472 // int scan_bits = 0;
whismanoid 53:3d5a3d241a5e 473 // int sampleRateFactore = 0;
whismanoid 53:3d5a3d241a5e 474 // double sampleRate = 0;
whismanoid 53:3d5a3d241a5e 475 // unsigned long banks_requested = 0;
whismanoid 53:3d5a3d241a5e 476 // bool bScanMode = 0;
whismanoid 53:3d5a3d241a5e 477
whismanoid 53:3d5a3d241a5e 478 //----------------------------------------
whismanoid 59:47538bcf6cda 479 // Device ID Validation -- not used, no device ID register
whismanoid 53:3d5a3d241a5e 480 #warning "Not Implemented Yet: MAX11043::Init Device ID Validation..."
whismanoid 53:3d5a3d241a5e 481 // const uint32_t part_id_expect = 0x000F02;
whismanoid 53:3d5a3d241a5e 482 // uint32_t part_id_readback;
whismanoid 53:3d5a3d241a5e 483 // RegRead(xxxxxxxxxxxxCMD_r001_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xddd_PART_ID, &part_id_readback);
whismanoid 53:3d5a3d241a5e 484 // if (part_id_readback != part_id_expect) return 0;
whismanoid 53:3d5a3d241a5e 485
whismanoid 53:3d5a3d241a5e 486 //----------------------------------------
whismanoid 58:2fea32db466b 487 // Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 58:2fea32db466b 488 SHDNoutputValue(0); // SHDN Inactive
whismanoid 58:2fea32db466b 489
whismanoid 58:2fea32db466b 490 //----------------------------------------
whismanoid 58:2fea32db466b 491 // Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 58:2fea32db466b 492 // CONVRUN is low.
whismanoid 58:2fea32db466b 493 CONVRUNoutputValue(0); // CONVRUN Idle
whismanoid 58:2fea32db466b 494
whismanoid 58:2fea32db466b 495 //----------------------------------------
whismanoid 58:2fea32db466b 496 // DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 58:2fea32db466b 497 // edge of the system clock.
whismanoid 58:2fea32db466b 498 DACSTEPoutputValue(0); // DACSTEP Idle
whismanoid 58:2fea32db466b 499
whismanoid 58:2fea32db466b 500 //----------------------------------------
whismanoid 58:2fea32db466b 501 // DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 58:2fea32db466b 502 UP_slash_DWNboutputValue(0); // UP/DWN# Down
whismanoid 58:2fea32db466b 503
whismanoid 58:2fea32db466b 504 //----------------------------------------
whismanoid 53:3d5a3d241a5e 505 // success
whismanoid 53:3d5a3d241a5e 506 return 1;
whismanoid 53:3d5a3d241a5e 507 }
whismanoid 53:3d5a3d241a5e 508
whismanoid 53:3d5a3d241a5e 509 //----------------------------------------
whismanoid 53:3d5a3d241a5e 510 // Write a MAX11043 register.
whismanoid 53:3d5a3d241a5e 511 //
whismanoid 57:1c9da8e90737 512 // CMDOP_1aaa_aaaa_ReadRegister bit is cleared 0 indicating a write operation.
whismanoid 53:3d5a3d241a5e 513 //
whismanoid 53:3d5a3d241a5e 514 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 515 //
whismanoid 53:3d5a3d241a5e 516 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 517 //
whismanoid 53:3d5a3d241a5e 518 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 519 //
whismanoid 53:3d5a3d241a5e 520 // SPI MOSI = 0aaa_aaaa_dddd_dddd
whismanoid 53:3d5a3d241a5e 521 //
whismanoid 53:3d5a3d241a5e 522 // SPI MISO = xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 523 //
whismanoid 53:3d5a3d241a5e 524 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 525 //
whismanoid 53:3d5a3d241a5e 526 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 527 //
whismanoid 53:3d5a3d241a5e 528 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 529 //
whismanoid 53:3d5a3d241a5e 530 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 531 //
whismanoid 53:3d5a3d241a5e 532 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 533 //
whismanoid 53:3d5a3d241a5e 534 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 535 //
whismanoid 53:3d5a3d241a5e 536 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 537 //
whismanoid 53:3d5a3d241a5e 538 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 539 //
whismanoid 53:3d5a3d241a5e 540 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 541 uint8_t MAX11043::RegWrite(MAX11043_CMD_enum_t commandByte, uint32_t regData)
whismanoid 53:3d5a3d241a5e 542 {
whismanoid 53:3d5a3d241a5e 543
whismanoid 53:3d5a3d241a5e 544 //----------------------------------------
whismanoid 53:3d5a3d241a5e 545 // switch based on register address szie RegSize(commandByte)
whismanoid 57:1c9da8e90737 546 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 547 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 548 {
whismanoid 53:3d5a3d241a5e 549 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 550 {
whismanoid 63:8f39d21d6157 551 // SPI 8+8 = 16-bit transfer
whismanoid 63:8f39d21d6157 552 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 553 // SPI MOSI = 0aaa_aaaa_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 554 // SPI MISO = xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 555 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 556 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 557 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 558 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 559 mosiData[1] = regData;
whismanoid 63:8f39d21d6157 560 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 561 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 562 // TODO: cache CMD_0101_0100_d8_Wr15_FilterCAddress
whismanoid 63:8f39d21d6157 563 // if (commandByte == CMD_0101_0100_d8_Wr15_FilterCAddress) {
whismanoid 63:8f39d21d6157 564 // FilterCAddress = regData;
whismanoid 63:8f39d21d6157 565 // }
whismanoid 63:8f39d21d6157 566 // TODO: cache CMD_0110_0000_d8_Wr18_FlashMode
whismanoid 63:8f39d21d6157 567 // if (commandByte == CMD_0110_0000_d8_Wr18_FlashMode) {
whismanoid 63:8f39d21d6157 568 // FlashMode = regData;
whismanoid 63:8f39d21d6157 569 // }
whismanoid 53:3d5a3d241a5e 570 }
whismanoid 53:3d5a3d241a5e 571 break;
whismanoid 53:3d5a3d241a5e 572 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 573 #warning "Not Verified Yet: MAX11043::RegWrite 16-bit"
whismanoid 53:3d5a3d241a5e 574 {
whismanoid 63:8f39d21d6157 575 // SPI 8+16 = 24-bit transfer
whismanoid 63:8f39d21d6157 576 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 63:8f39d21d6157 577 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 578 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 579 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 580 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 581 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 582 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 583 mosiData[1] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 584 mosiData[2] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 585 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 586 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 587 // cache CMD_0010_0000_d16_Wr08_Configuration
whismanoid 63:8f39d21d6157 588 if (commandByte == CMD_0010_0000_d16_Wr08_Configuration) {
whismanoid 63:8f39d21d6157 589 config = regData;
whismanoid 63:8f39d21d6157 590 }
whismanoid 63:8f39d21d6157 591 // TODO: cache CMD_0010_0100_d16_Wr09_DAC
whismanoid 63:8f39d21d6157 592 // TODO: cache CMD_0010_1000_d16_Wr0A_DACStep
whismanoid 63:8f39d21d6157 593 // TODO: cache CMD_0010_1100_d16_Wr0B_DACHDACL
whismanoid 63:8f39d21d6157 594 // TODO: cache CMD_0011_0000_d16_Wr0C_ConfigA
whismanoid 63:8f39d21d6157 595 // TODO: cache CMD_0011_0100_d16_Wr0D_ConfigB
whismanoid 63:8f39d21d6157 596 // TODO: cache CMD_0011_1000_d16_Wr0E_ConfigC
whismanoid 63:8f39d21d6157 597 // TODO: cache CMD_0011_1100_d16_Wr0F_ConfigD
whismanoid 63:8f39d21d6157 598 // TODO: cache CMD_0100_0000_d16_Wr10_Reference
whismanoid 63:8f39d21d6157 599 // TODO: cache CMD_0100_0100_d16_Wr11_AGain
whismanoid 63:8f39d21d6157 600 // TODO: cache CMD_0100_1000_d16_Wr12_BGain
whismanoid 63:8f39d21d6157 601 // TODO: cache CMD_0100_1100_d16_Wr13_CGain
whismanoid 63:8f39d21d6157 602 // TODO: cache CMD_0101_0000_d16_Wr14_DGain
whismanoid 63:8f39d21d6157 603 // TODO: cache CMD_0110_0100_d16_Wr19_FlashAddr
whismanoid 63:8f39d21d6157 604 // TODO: cache CMD_0110_1000_d16_Wr1A_FlashDataIn
whismanoid 53:3d5a3d241a5e 605 }
whismanoid 53:3d5a3d241a5e 606 break;
whismanoid 63:8f39d21d6157 607 case 32: // 32-bit register size
whismanoid 63:8f39d21d6157 608 #warning "Not Verified Yet: MAX11043::RegWrite 32-bit"
whismanoid 53:3d5a3d241a5e 609 {
whismanoid 63:8f39d21d6157 610 // SPI 8+32 = 40-bit transfer
whismanoid 63:8f39d21d6157 611 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 63:8f39d21d6157 612 // SPI MOSI = 1aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 613 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 614 //
whismanoid 63:8f39d21d6157 615 size_t byteCount = 1 + (2 * 2);
whismanoid 63:8f39d21d6157 616 uint8_t mosiData[5];
whismanoid 63:8f39d21d6157 617 uint8_t misoData[5];
whismanoid 63:8f39d21d6157 618 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 619 mosiData[1] = (uint8_t)((regData >> 24) & 0xFF);
whismanoid 63:8f39d21d6157 620 mosiData[2] = (uint8_t)((regData >> 16) & 0xFF);
whismanoid 63:8f39d21d6157 621 mosiData[3] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 622 mosiData[4] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 623 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 624 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 625 // TODO: cache CMD_0101_1000_d32_Wr16_FilterCDataOut
whismanoid 63:8f39d21d6157 626 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 627 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 628 // }
whismanoid 63:8f39d21d6157 629 // TODO: cache CMD_0101_1100_d32_Wr17_FilterCDataIn
whismanoid 63:8f39d21d6157 630 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 631 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 632 // }
whismanoid 53:3d5a3d241a5e 633 }
whismanoid 53:3d5a3d241a5e 634 break;
whismanoid 53:3d5a3d241a5e 635 }
whismanoid 53:3d5a3d241a5e 636
whismanoid 53:3d5a3d241a5e 637 //----------------------------------------
whismanoid 53:3d5a3d241a5e 638 // success
whismanoid 53:3d5a3d241a5e 639 return 1;
whismanoid 53:3d5a3d241a5e 640 }
whismanoid 53:3d5a3d241a5e 641
whismanoid 53:3d5a3d241a5e 642 //----------------------------------------
whismanoid 53:3d5a3d241a5e 643 // Read an 8-bit MAX11043 register
whismanoid 53:3d5a3d241a5e 644 //
whismanoid 57:1c9da8e90737 645 // CMDOP_1aaa_aaaa_ReadRegister bit is set 1 indicating a read operation.
whismanoid 53:3d5a3d241a5e 646 //
whismanoid 53:3d5a3d241a5e 647 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 648 //
whismanoid 53:3d5a3d241a5e 649 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 650 //
whismanoid 53:3d5a3d241a5e 651 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 652 //
whismanoid 53:3d5a3d241a5e 653 // SPI MOSI = 1aaa_aaaa_0000_0000
whismanoid 53:3d5a3d241a5e 654 //
whismanoid 53:3d5a3d241a5e 655 // SPI MISO = xxxx_xxxx_dddd_dddd
whismanoid 53:3d5a3d241a5e 656 //
whismanoid 53:3d5a3d241a5e 657 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 658 //
whismanoid 53:3d5a3d241a5e 659 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 660 //
whismanoid 53:3d5a3d241a5e 661 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 662 //
whismanoid 53:3d5a3d241a5e 663 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 664 //
whismanoid 53:3d5a3d241a5e 665 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 666 //
whismanoid 53:3d5a3d241a5e 667 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 668 //
whismanoid 53:3d5a3d241a5e 669 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 670 //
whismanoid 53:3d5a3d241a5e 671 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 672 //
whismanoid 53:3d5a3d241a5e 673 //
whismanoid 53:3d5a3d241a5e 674 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 675 uint8_t MAX11043::RegRead(MAX11043_CMD_enum_t commandByte, uint32_t* ptrRegData)
whismanoid 53:3d5a3d241a5e 676 {
whismanoid 53:3d5a3d241a5e 677
whismanoid 53:3d5a3d241a5e 678 //----------------------------------------
whismanoid 53:3d5a3d241a5e 679 // switch based on register address szie RegSize(regAddress)
whismanoid 57:1c9da8e90737 680 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 681 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 682 {
whismanoid 53:3d5a3d241a5e 683 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 684 {
whismanoid 60:d1d1eaa90fb7 685 // SPI 8+8 = 16-bit transfer
whismanoid 62:8223a7253c90 686 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 687 // SPI MOSI = 1aaa_aaaa_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 688 // SPI MISO = xxxx_xxxx_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 689 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 690 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 691 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 692 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 693 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 694 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 695 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 696 if (ptrRegData) { (*ptrRegData) = misoData[1]; }
whismanoid 59:47538bcf6cda 697 if (commandByte == CMD_0001_1110_d8_Rd07_Status) {
whismanoid 59:47538bcf6cda 698 // TODO1: update status
whismanoid 63:8f39d21d6157 699 status = misoData[1];
whismanoid 59:47538bcf6cda 700 }
whismanoid 53:3d5a3d241a5e 701 }
whismanoid 53:3d5a3d241a5e 702 break;
whismanoid 53:3d5a3d241a5e 703 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 704 #warning "Not Verified Yet: MAX11043::RegRead 16-bit"
whismanoid 53:3d5a3d241a5e 705 {
whismanoid 60:d1d1eaa90fb7 706 // SPI 8+16 = 24-bit transfer
whismanoid 62:8223a7253c90 707 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 60:d1d1eaa90fb7 708 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 709 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 710 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 711 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 712 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 713 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 714 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 715 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 716 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 717 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 718 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 59:47538bcf6cda 719 if (commandByte == CMD_0010_0010_d16_Rd08_Configuration) {
whismanoid 59:47538bcf6cda 720 // TODO1: update config
whismanoid 63:8f39d21d6157 721 config = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 722 }
whismanoid 59:47538bcf6cda 723 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 724 // TODO1: update adca
whismanoid 63:8f39d21d6157 725 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 726 }
whismanoid 59:47538bcf6cda 727 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 728 // TODO1: update adcb
whismanoid 63:8f39d21d6157 729 adcb = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 730 }
whismanoid 59:47538bcf6cda 731 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 732 // TODO1: update adcc
whismanoid 63:8f39d21d6157 733 adcc = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 734 }
whismanoid 59:47538bcf6cda 735 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 736 // TODO1: update adcd
whismanoid 63:8f39d21d6157 737 adcd = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 738 }
whismanoid 53:3d5a3d241a5e 739 }
whismanoid 53:3d5a3d241a5e 740 break;
whismanoid 53:3d5a3d241a5e 741 case 24: // 24-bit register size
whismanoid 53:3d5a3d241a5e 742 {
whismanoid 60:d1d1eaa90fb7 743 // SPI 8+24 = 32-bit transfer
whismanoid 62:8223a7253c90 744 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32
whismanoid 63:8f39d21d6157 745 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 746 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 747 size_t byteCount = 1 + 3;
whismanoid 63:8f39d21d6157 748 uint8_t mosiData[4];
whismanoid 63:8f39d21d6157 749 uint8_t misoData[4];
whismanoid 63:8f39d21d6157 750 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 751 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 752 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 753 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 754 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 755 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 756 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 59:47538bcf6cda 757 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 758 // TODO1: update adca
whismanoid 63:8f39d21d6157 759 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 760 }
whismanoid 59:47538bcf6cda 761 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 762 // TODO1: update adcb
whismanoid 63:8f39d21d6157 763 adcb = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 764 }
whismanoid 59:47538bcf6cda 765 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 766 // TODO1: update adcc
whismanoid 63:8f39d21d6157 767 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 768 }
whismanoid 59:47538bcf6cda 769 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 770 // TODO1: update adcd
whismanoid 63:8f39d21d6157 771 adcd = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 772 }
whismanoid 59:47538bcf6cda 773 }
whismanoid 59:47538bcf6cda 774 break;
whismanoid 63:8f39d21d6157 775 case 32: // 32-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 776 //
whismanoid 63:8f39d21d6157 777 #warning "Not Implemented Yet: MAX11043::RegRead 32-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 778 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 779 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 780 // update adca, adcb
whismanoid 59:47538bcf6cda 781 //
whismanoid 63:8f39d21d6157 782 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 783 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 784 // update adcc, adcd
whismanoid 59:47538bcf6cda 785 //
whismanoid 59:47538bcf6cda 786 {
whismanoid 60:d1d1eaa90fb7 787 // SPI 8+32 = 40-bit transfer
whismanoid 62:8223a7253c90 788 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 60:d1d1eaa90fb7 789 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 790 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 791 size_t byteCount = 1 + (2 * 2);
whismanoid 62:8223a7253c90 792 uint8_t mosiData[5];
whismanoid 62:8223a7253c90 793 uint8_t misoData[5];
whismanoid 62:8223a7253c90 794 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 795 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 796 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 797 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 798 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 799 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 800 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 801 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 802 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 803 // TODO1: update adca
whismanoid 62:8223a7253c90 804 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 805 // TODO1: update adcb
whismanoid 62:8223a7253c90 806 adcb = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 807 }
whismanoid 63:8f39d21d6157 808 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 809 // TODO1: update adcc
whismanoid 62:8223a7253c90 810 adcc = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 811 // TODO1: update adcd
whismanoid 62:8223a7253c90 812 adcd = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 813 }
whismanoid 59:47538bcf6cda 814 }
whismanoid 59:47538bcf6cda 815 break;
whismanoid 63:8f39d21d6157 816 case 48: // 48-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 817 //
whismanoid 63:8f39d21d6157 818 #warning "Not Verified Yet: MAX11043::RegRead 48-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 819 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 820 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 821 // update adca, adcb
whismanoid 59:47538bcf6cda 822 //
whismanoid 63:8f39d21d6157 823 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 824 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 825 // update adcc, adcd
whismanoid 59:47538bcf6cda 826 //
whismanoid 59:47538bcf6cda 827 {
whismanoid 60:d1d1eaa90fb7 828 // SPI 8+48 = 56-bit transfer
whismanoid 62:8223a7253c90 829 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56
whismanoid 60:d1d1eaa90fb7 830 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 831 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 832 size_t byteCount = 1 + (3 * 2);
whismanoid 62:8223a7253c90 833 uint8_t mosiData[7];
whismanoid 62:8223a7253c90 834 uint8_t misoData[7];
whismanoid 62:8223a7253c90 835 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 836 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 837 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 838 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 839 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 840 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 841 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 842 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 843 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 844 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 845 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 846 // TODO1: update adca
whismanoid 62:8223a7253c90 847 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 848 // TODO1: update adcb
whismanoid 62:8223a7253c90 849 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 850 }
whismanoid 63:8f39d21d6157 851 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 852 // TODO1: update adcc
whismanoid 62:8223a7253c90 853 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 854 // TODO1: update adcd
whismanoid 62:8223a7253c90 855 adcd = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 856 }
whismanoid 59:47538bcf6cda 857 }
whismanoid 59:47538bcf6cda 858 break;
whismanoid 63:8f39d21d6157 859 case 64: // 64-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 860 //
whismanoid 63:8f39d21d6157 861 #warning "Not Verified Yet: MAX11043::RegRead 64-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 862 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 863 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 864 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 865 //
whismanoid 59:47538bcf6cda 866 {
whismanoid 60:d1d1eaa90fb7 867 // SPI 8+64 = 72-bit transfer
whismanoid 62:8223a7253c90 868 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72
whismanoid 60:d1d1eaa90fb7 869 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 870 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 871 size_t byteCount = 1 + (2 * 4);
whismanoid 62:8223a7253c90 872 uint8_t mosiData[9];
whismanoid 62:8223a7253c90 873 uint8_t misoData[9];
whismanoid 62:8223a7253c90 874 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 875 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 876 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 877 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 878 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 879 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 880 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 881 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 882 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 883 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 884 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 885 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 886 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 887 // TODO1: update adca
whismanoid 62:8223a7253c90 888 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 889 // TODO1: update adcb
whismanoid 62:8223a7253c90 890 adcb = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 891 // TODO1: update adcc
whismanoid 62:8223a7253c90 892 adcc = (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 893 // TODO1: update adcd
whismanoid 62:8223a7253c90 894 adcd = (misoData[7] << 8) | misoData[8];
whismanoid 59:47538bcf6cda 895 }
whismanoid 59:47538bcf6cda 896 }
whismanoid 59:47538bcf6cda 897 break;
whismanoid 63:8f39d21d6157 898 case 96: // 96-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 899 //
whismanoid 63:8f39d21d6157 900 #warning "Not Verified Yet: MAX11043::RegRead 96-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 901 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 902 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 903 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 904 //
whismanoid 59:47538bcf6cda 905 {
whismanoid 60:d1d1eaa90fb7 906 // SPI 8+96 = 104-bit transfer
whismanoid 62:8223a7253c90 907 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72 ___[9]_80 __[10]_88 __[11]_96 __[12]104
whismanoid 60:d1d1eaa90fb7 908 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 909 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 910 size_t byteCount = 1 + (3 * 4);
whismanoid 62:8223a7253c90 911 uint8_t mosiData[13];
whismanoid 62:8223a7253c90 912 uint8_t misoData[13];
whismanoid 62:8223a7253c90 913 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 914 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 915 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 916 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 917 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 918 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 919 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 920 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 921 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 922 mosiData[9] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 923 mosiData[10] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 924 mosiData[11] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 925 mosiData[12] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 926 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 927 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 928 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 929 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 930 // TODO1: update adca
whismanoid 62:8223a7253c90 931 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 932 // TODO1: update adcb
whismanoid 62:8223a7253c90 933 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 934 // TODO1: update adcc
whismanoid 62:8223a7253c90 935 adcc = (misoData[7] << 16) | (misoData[8] << 8) | misoData[9];
whismanoid 59:47538bcf6cda 936 // TODO1: update adcd
whismanoid 62:8223a7253c90 937 adcd = (misoData[10] << 16) | (misoData[11] << 8) | misoData[12];
whismanoid 59:47538bcf6cda 938 }
whismanoid 53:3d5a3d241a5e 939 }
whismanoid 53:3d5a3d241a5e 940 break;
whismanoid 53:3d5a3d241a5e 941 }
whismanoid 53:3d5a3d241a5e 942
whismanoid 53:3d5a3d241a5e 943 //----------------------------------------
whismanoid 53:3d5a3d241a5e 944 // success
whismanoid 53:3d5a3d241a5e 945 return 1;
whismanoid 53:3d5a3d241a5e 946 }
whismanoid 53:3d5a3d241a5e 947
whismanoid 53:3d5a3d241a5e 948 //----------------------------------------
whismanoid 53:3d5a3d241a5e 949 // Return the size of a MAX11043 register
whismanoid 53:3d5a3d241a5e 950 //
whismanoid 53:3d5a3d241a5e 951 // @return 8 for 8-bit, 16 for 16-bit, 24 for 24-bit, else 0 for undefined register size
whismanoid 53:3d5a3d241a5e 952 uint8_t MAX11043::RegSize(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 953 {
whismanoid 53:3d5a3d241a5e 954
whismanoid 53:3d5a3d241a5e 955 //----------------------------------------
whismanoid 53:3d5a3d241a5e 956 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 957 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 958 switch(commandByte)
whismanoid 53:3d5a3d241a5e 959 {
whismanoid 53:3d5a3d241a5e 960 default:
whismanoid 57:1c9da8e90737 961 // case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 962 // case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 963 // case CMDOP_1111_1111_NoOperationMOSIidleHigh:
whismanoid 53:3d5a3d241a5e 964 return 0; // undefined register size
whismanoid 53:3d5a3d241a5e 965 case CMD_0001_1110_d8_Rd07_Status:
whismanoid 53:3d5a3d241a5e 966 case CMD_0101_0100_d8_Wr15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 967 case CMD_0101_0110_d8_Rd15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 968 case CMD_0110_0000_d8_Wr18_FlashMode:
whismanoid 53:3d5a3d241a5e 969 case CMD_0110_0010_d8_Rd18_FlashMode:
whismanoid 53:3d5a3d241a5e 970 return 8; // 8-bit register size
whismanoid 53:3d5a3d241a5e 971 case CMD_0010_0000_d16_Wr08_Configuration:
whismanoid 53:3d5a3d241a5e 972 case CMD_0010_0010_d16_Rd08_Configuration:
whismanoid 53:3d5a3d241a5e 973 case CMD_0010_0100_d16_Wr09_DAC:
whismanoid 53:3d5a3d241a5e 974 case CMD_0010_0110_d16_Rd09_DAC:
whismanoid 53:3d5a3d241a5e 975 case CMD_0010_1000_d16_Wr0A_DACStep:
whismanoid 53:3d5a3d241a5e 976 case CMD_0010_1010_d16_Rd0A_DACStep:
whismanoid 53:3d5a3d241a5e 977 case CMD_0010_1100_d16_Wr0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 978 case CMD_0010_1110_d16_Rd0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 979 case CMD_0011_0000_d16_Wr0C_ConfigA:
whismanoid 53:3d5a3d241a5e 980 case CMD_0011_0010_d16_Rd0C_ConfigA:
whismanoid 53:3d5a3d241a5e 981 case CMD_0011_0100_d16_Wr0D_ConfigB:
whismanoid 53:3d5a3d241a5e 982 case CMD_0011_0110_d16_Rd0D_ConfigB:
whismanoid 53:3d5a3d241a5e 983 case CMD_0011_1000_d16_Wr0E_ConfigC:
whismanoid 53:3d5a3d241a5e 984 case CMD_0011_1010_d16_Rd0E_ConfigC:
whismanoid 53:3d5a3d241a5e 985 case CMD_0011_1100_d16_Wr0F_ConfigD:
whismanoid 53:3d5a3d241a5e 986 case CMD_0011_1110_d16_Rd0F_ConfigD:
whismanoid 53:3d5a3d241a5e 987 case CMD_0100_0000_d16_Wr10_Reference:
whismanoid 53:3d5a3d241a5e 988 case CMD_0100_0010_d16_Rd10_Reference:
whismanoid 53:3d5a3d241a5e 989 case CMD_0100_0100_d16_Wr11_AGain:
whismanoid 53:3d5a3d241a5e 990 case CMD_0100_0110_d16_Rd11_AGain:
whismanoid 53:3d5a3d241a5e 991 case CMD_0100_1000_d16_Wr12_BGain:
whismanoid 53:3d5a3d241a5e 992 case CMD_0100_1010_d16_Rd12_BGain:
whismanoid 53:3d5a3d241a5e 993 case CMD_0100_1100_d16_Wr13_CGain:
whismanoid 53:3d5a3d241a5e 994 case CMD_0100_1110_d16_Rd13_CGain:
whismanoid 53:3d5a3d241a5e 995 case CMD_0101_0000_d16_Wr14_DGain:
whismanoid 53:3d5a3d241a5e 996 case CMD_0101_0010_d16_Rd14_DGain:
whismanoid 53:3d5a3d241a5e 997 case CMD_0110_0100_d16_Wr19_FlashAddr:
whismanoid 53:3d5a3d241a5e 998 case CMD_0110_0110_d16_Rd19_FlashAddr:
whismanoid 53:3d5a3d241a5e 999 case CMD_0110_1000_d16_Wr1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 1000 case CMD_0110_1010_d16_Rd1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 1001 case CMD_0110_1110_d16_Rd1B_FlashDataOut:
whismanoid 53:3d5a3d241a5e 1002 return 16; // 16-bit register size
whismanoid 59:47538bcf6cda 1003 case CMD_0000_0010_d16o8_Rd00_ADCa:
whismanoid 59:47538bcf6cda 1004 case CMD_0000_0110_d16o8_Rd01_ADCb:
whismanoid 59:47538bcf6cda 1005 case CMD_0000_1010_d16o8_Rd02_ADCc:
whismanoid 59:47538bcf6cda 1006 case CMD_0000_1110_d16o8_Rd03_ADCd:
whismanoid 59:47538bcf6cda 1007 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1008 {
whismanoid 59:47538bcf6cda 1009 // %SW 0x02 (0 0 0) -- for 24-bit read
whismanoid 59:47538bcf6cda 1010 return 24; // 24-bit register size
whismanoid 59:47538bcf6cda 1011 }
whismanoid 59:47538bcf6cda 1012 // %SW 0x02 (0 0) -- for 16-bit read
whismanoid 59:47538bcf6cda 1013 //
whismanoid 59:47538bcf6cda 1014 return 16; // 16-bit register size
whismanoid 63:8f39d21d6157 1015 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab:
whismanoid 63:8f39d21d6157 1016 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd:
whismanoid 59:47538bcf6cda 1017 //
whismanoid 59:47538bcf6cda 1018 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 1019 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1020 {
whismanoid 59:47538bcf6cda 1021 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 1022 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 1023 return 48; // 48-bit register size: 2*(24)
whismanoid 59:47538bcf6cda 1024 }
whismanoid 59:47538bcf6cda 1025 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 1026 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 1027 //
whismanoid 59:47538bcf6cda 1028 return 32; // 32-bit register size: 2*(16)
whismanoid 63:8f39d21d6157 1029 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd:
whismanoid 59:47538bcf6cda 1030 //
whismanoid 59:47538bcf6cda 1031 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 1032 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1033 {
whismanoid 59:47538bcf6cda 1034 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1035 return 96; // 96-bit register size: 4*(24)
whismanoid 59:47538bcf6cda 1036 }
whismanoid 59:47538bcf6cda 1037 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1038 //
whismanoid 59:47538bcf6cda 1039 return 64; // 64-bit register size: 4*(16)
whismanoid 53:3d5a3d241a5e 1040 case CMD_0101_1000_d32_Wr16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 1041 case CMD_0101_1010_d32_Rd16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 1042 case CMD_0101_1100_d32_Wr17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 1043 case CMD_0101_1110_d32_Rd17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 1044 return 32; // 32-bit register size
whismanoid 53:3d5a3d241a5e 1045 }
whismanoid 53:3d5a3d241a5e 1046 }
whismanoid 53:3d5a3d241a5e 1047
whismanoid 53:3d5a3d241a5e 1048 //----------------------------------------
whismanoid 57:1c9da8e90737 1049 // Decode operation from commandByte
whismanoid 57:1c9da8e90737 1050 //
whismanoid 57:1c9da8e90737 1051 // @return operation such as idle, read register, write register, etc.
whismanoid 57:1c9da8e90737 1052 MAX11043::MAX11043_CMDOP_enum_t MAX11043::DecodeCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 57:1c9da8e90737 1053 {
whismanoid 57:1c9da8e90737 1054
whismanoid 57:1c9da8e90737 1055 //----------------------------------------
whismanoid 57:1c9da8e90737 1056 // decode operation from command byte
whismanoid 57:1c9da8e90737 1057 switch (commandByte & 0x83)
whismanoid 57:1c9da8e90737 1058 {
whismanoid 57:1c9da8e90737 1059 case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 1060 return CMDOP_0aaa_aa10_ReadRegister;
whismanoid 57:1c9da8e90737 1061 case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 1062 return CMDOP_0aaa_aa00_WriteRegister;
whismanoid 57:1c9da8e90737 1063 default:
whismanoid 57:1c9da8e90737 1064 return CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 57:1c9da8e90737 1065 }
whismanoid 57:1c9da8e90737 1066 }
whismanoid 57:1c9da8e90737 1067
whismanoid 57:1c9da8e90737 1068 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1069 // Return the address field of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1070 //
whismanoid 53:3d5a3d241a5e 1071 // @return register address field as given in datasheet
whismanoid 53:3d5a3d241a5e 1072 uint8_t MAX11043::RegAddrOfCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1073 {
whismanoid 53:3d5a3d241a5e 1074
whismanoid 53:3d5a3d241a5e 1075 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1076 // extract register address value from command byte
whismanoid 57:1c9da8e90737 1077 return (uint8_t)((commandByte &~ 0x83) >> 2); // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 1078 }
whismanoid 53:3d5a3d241a5e 1079
whismanoid 53:3d5a3d241a5e 1080 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1081 // Test whether a command byte is a register read command
whismanoid 53:3d5a3d241a5e 1082 //
whismanoid 53:3d5a3d241a5e 1083 // @return true if command byte is a register read command
whismanoid 53:3d5a3d241a5e 1084 uint8_t MAX11043::IsRegReadCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1085 {
whismanoid 53:3d5a3d241a5e 1086
whismanoid 53:3d5a3d241a5e 1087 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1088 // Test whether a command byte is a register read command
whismanoid 57:1c9da8e90737 1089 return (commandByte &~ 0x02) ? 1 : 0; // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 1090 }
whismanoid 53:3d5a3d241a5e 1091
whismanoid 53:3d5a3d241a5e 1092 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1093 // Return the name of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1094 //
whismanoid 53:3d5a3d241a5e 1095 // @return null-terminated constant C string containing register name or empty string
whismanoid 53:3d5a3d241a5e 1096 const char* MAX11043::RegName(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1097 {
whismanoid 53:3d5a3d241a5e 1098
whismanoid 53:3d5a3d241a5e 1099 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1100 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 1101 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 1102 switch(commandByte)
whismanoid 53:3d5a3d241a5e 1103 {
whismanoid 53:3d5a3d241a5e 1104 default:
whismanoid 53:3d5a3d241a5e 1105 return ""; // undefined register
whismanoid 57:1c9da8e90737 1106 // case CMDOP_0aaa_aa00_WriteRegister: return "_______";
whismanoid 57:1c9da8e90737 1107 // case CMDOP_0aaa_aa10_ReadRegister: return "_______";
whismanoid 57:1c9da8e90737 1108 // case CMDOP_1111_1111_NoOperationMOSIidleHigh: return "_______";
whismanoid 59:47538bcf6cda 1109 case CMD_0000_0010_d16o8_Rd00_ADCa: return "ADCa";
whismanoid 59:47538bcf6cda 1110 case CMD_0000_0110_d16o8_Rd01_ADCb: return "ADCb";
whismanoid 59:47538bcf6cda 1111 case CMD_0000_1010_d16o8_Rd02_ADCc: return "ADCc";
whismanoid 59:47538bcf6cda 1112 case CMD_0000_1110_d16o8_Rd03_ADCd: return "ADCd";
whismanoid 63:8f39d21d6157 1113 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab: return "ADCab";
whismanoid 63:8f39d21d6157 1114 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd: return "ADCcd";
whismanoid 63:8f39d21d6157 1115 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd: return "ADCabcd";
whismanoid 53:3d5a3d241a5e 1116 case CMD_0001_1110_d8_Rd07_Status: return "Status";
whismanoid 53:3d5a3d241a5e 1117 case CMD_0010_0000_d16_Wr08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1118 case CMD_0010_0010_d16_Rd08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1119 case CMD_0010_0100_d16_Wr09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1120 case CMD_0010_0110_d16_Rd09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1121 case CMD_0010_1000_d16_Wr0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1122 case CMD_0010_1010_d16_Rd0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1123 case CMD_0010_1100_d16_Wr0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1124 case CMD_0010_1110_d16_Rd0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1125 case CMD_0011_0000_d16_Wr0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1126 case CMD_0011_0010_d16_Rd0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1127 case CMD_0011_0100_d16_Wr0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1128 case CMD_0011_0110_d16_Rd0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1129 case CMD_0011_1000_d16_Wr0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1130 case CMD_0011_1010_d16_Rd0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1131 case CMD_0011_1100_d16_Wr0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1132 case CMD_0011_1110_d16_Rd0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1133 case CMD_0100_0000_d16_Wr10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1134 case CMD_0100_0010_d16_Rd10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1135 case CMD_0100_0100_d16_Wr11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1136 case CMD_0100_0110_d16_Rd11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1137 case CMD_0100_1000_d16_Wr12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1138 case CMD_0100_1010_d16_Rd12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1139 case CMD_0100_1100_d16_Wr13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1140 case CMD_0100_1110_d16_Rd13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1141 case CMD_0101_0000_d16_Wr14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1142 case CMD_0101_0010_d16_Rd14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1143 case CMD_0101_0100_d8_Wr15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1144 case CMD_0101_0110_d8_Rd15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1145 case CMD_0101_1000_d32_Wr16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1146 case CMD_0101_1010_d32_Rd16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1147 case CMD_0101_1100_d32_Wr17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1148 case CMD_0101_1110_d32_Rd17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1149 case CMD_0110_0000_d8_Wr18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1150 case CMD_0110_0010_d8_Rd18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1151 case CMD_0110_0100_d16_Wr19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1152 case CMD_0110_0110_d16_Rd19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1153 case CMD_0110_1000_d16_Wr1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1154 case CMD_0110_1010_d16_Rd1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1155 case CMD_0110_1110_d16_Rd1B_FlashDataOut: return "FlashDataOut";
whismanoid 53:3d5a3d241a5e 1156 }
whismanoid 53:3d5a3d241a5e 1157 }
whismanoid 53:3d5a3d241a5e 1158
whismanoid 59:47538bcf6cda 1159 //----------------------------------------
whismanoid 64:a667cfd83492 1160 // Menu item '$' -> adca, adcb, adcc, adcd
whismanoid 64:a667cfd83492 1161 // Read ADCabcd
whismanoid 64:a667cfd83492 1162 //
whismanoid 64:a667cfd83492 1163 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1164 uint8_t MAX11043::Read_ADCabcd(void)
whismanoid 64:a667cfd83492 1165 {
whismanoid 64:a667cfd83492 1166
whismanoid 64:a667cfd83492 1167 //----------------------------------------
whismanoid 64:a667cfd83492 1168 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1169 #warning "Not Tested Yet: MAX11043::Read_ADCabcd..."
whismanoid 64:a667cfd83492 1170
whismanoid 69:989e392cf635 1171 //--------------------------------------------------
whismanoid 69:989e392cf635 1172 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 1173 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 1174 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 1175 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1176 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 1177 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 1178 // 2020-02-20 MAX11043_EOC_INTERRUPT_POLLING works on MAX32625MBED at 9us conversion rate, with 1us timing margin
whismanoid 69:989e392cf635 1179 // TODO: poll m_EOC_pin if CONVRUN is high
whismanoid 69:989e392cf635 1180 if (m_CONVRUN_pin)
whismanoid 69:989e392cf635 1181 {
whismanoid 69:989e392cf635 1182 #warning "MAX11043::Read_ADCabcd() Potential infinite loop if EOC pin not connected"
whismanoid 69:989e392cf635 1183 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 69:989e392cf635 1184 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 1185 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 1186 (m_EOC_pin != 1));
whismanoid 69:989e392cf635 1187 futility_countdown--)
whismanoid 69:989e392cf635 1188 {
whismanoid 69:989e392cf635 1189 // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 69:989e392cf635 1190 }
whismanoid 69:989e392cf635 1191 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 1192 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 1193 (m_EOC_pin != 0));
whismanoid 69:989e392cf635 1194 futility_countdown--)
whismanoid 69:989e392cf635 1195 {
whismanoid 69:989e392cf635 1196 // spinlock waiting for logic low pin state (new data is available)
whismanoid 69:989e392cf635 1197 }
whismanoid 69:989e392cf635 1198 }
whismanoid 69:989e392cf635 1199 else
whismanoid 69:989e392cf635 1200 {
whismanoid 69:989e392cf635 1201 // CONVRUN pin is being driven low, so conversion result will not change, EOC# remains high
whismanoid 69:989e392cf635 1202 }
whismanoid 69:989e392cf635 1203 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1204 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 1205 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1206 //--------------------------------------------------
whismanoid 69:989e392cf635 1207
whismanoid 64:a667cfd83492 1208 //----------------------------------------
whismanoid 64:a667cfd83492 1209 // read register ADCabcd -> &adca, &adcb, &adcc, &adcd
whismanoid 64:a667cfd83492 1210 RegRead(CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd, 0);
whismanoid 64:a667cfd83492 1211
whismanoid 64:a667cfd83492 1212 //----------------------------------------
whismanoid 64:a667cfd83492 1213 // success
whismanoid 64:a667cfd83492 1214 return 1;
whismanoid 64:a667cfd83492 1215 }
whismanoid 64:a667cfd83492 1216
whismanoid 64:a667cfd83492 1217 //----------------------------------------
whismanoid 66:3fe92f6f1cfa 1218 // Menu item 'GA'
whismanoid 64:a667cfd83492 1219 // Write AGain register
whismanoid 64:a667cfd83492 1220 //
whismanoid 64:a667cfd83492 1221 // @param[in] gain 2's complement, 0x800=0.25V/V, 0x1000=0.5V/V, 0x2000=1VV/V, 0x4000=2V/V, default=0x2000
whismanoid 64:a667cfd83492 1222 //
whismanoid 64:a667cfd83492 1223 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1224 uint8_t MAX11043::Write_AGain(uint32_t gain)
whismanoid 64:a667cfd83492 1225 {
whismanoid 64:a667cfd83492 1226
whismanoid 64:a667cfd83492 1227 //----------------------------------------
whismanoid 64:a667cfd83492 1228 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1229 #warning "Not Tested Yet: MAX11043::Write_AGain..."
whismanoid 64:a667cfd83492 1230
whismanoid 64:a667cfd83492 1231 //----------------------------------------
whismanoid 64:a667cfd83492 1232 // write register
whismanoid 64:a667cfd83492 1233 RegWrite(CMD_0100_0100_d16_Wr11_AGain, gain);
whismanoid 64:a667cfd83492 1234
whismanoid 64:a667cfd83492 1235 //----------------------------------------
whismanoid 64:a667cfd83492 1236 // success
whismanoid 64:a667cfd83492 1237 return 1;
whismanoid 64:a667cfd83492 1238 }
whismanoid 64:a667cfd83492 1239
whismanoid 64:a667cfd83492 1240 //----------------------------------------
whismanoid 59:47538bcf6cda 1241 // Menu item 'XX'
whismanoid 59:47538bcf6cda 1242 //
whismanoid 59:47538bcf6cda 1243 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1244 uint8_t MAX11043::Configure_XXXXX(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1245 {
whismanoid 59:47538bcf6cda 1246
whismanoid 59:47538bcf6cda 1247 //----------------------------------------
whismanoid 59:47538bcf6cda 1248 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1249 #warning "Not Tested Yet: MAX11043::Configure_XXXXX..."
whismanoid 59:47538bcf6cda 1250
whismanoid 59:47538bcf6cda 1251 //----------------------------------------
whismanoid 59:47538bcf6cda 1252 // read register
whismanoid 59:47538bcf6cda 1253 RegRead(CMD_0000_0010_d16o8_Rd00_ADCa, &adca);
whismanoid 59:47538bcf6cda 1254
whismanoid 59:47538bcf6cda 1255 //----------------------------------------
whismanoid 59:47538bcf6cda 1256 // success
whismanoid 59:47538bcf6cda 1257 return 1;
whismanoid 59:47538bcf6cda 1258 }
whismanoid 59:47538bcf6cda 1259
whismanoid 59:47538bcf6cda 1260 //----------------------------------------
whismanoid 59:47538bcf6cda 1261 // Menu item 'XY'
whismanoid 59:47538bcf6cda 1262 //
whismanoid 59:47538bcf6cda 1263 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1264 uint8_t MAX11043::Configure_XXXXY(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1265 {
whismanoid 59:47538bcf6cda 1266
whismanoid 59:47538bcf6cda 1267 //----------------------------------------
whismanoid 59:47538bcf6cda 1268 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1269 #warning "Not Tested Yet: MAX11043::Configure_XXXXY..."
whismanoid 59:47538bcf6cda 1270
whismanoid 59:47538bcf6cda 1271 //----------------------------------------
whismanoid 59:47538bcf6cda 1272 // read register
whismanoid 59:47538bcf6cda 1273 RegRead(CMD_0001_1110_d8_Rd07_Status, &status);
whismanoid 59:47538bcf6cda 1274
whismanoid 59:47538bcf6cda 1275 //----------------------------------------
whismanoid 59:47538bcf6cda 1276 // success
whismanoid 59:47538bcf6cda 1277 return 1;
whismanoid 59:47538bcf6cda 1278 }
whismanoid 59:47538bcf6cda 1279
whismanoid 53:3d5a3d241a5e 1280
whismanoid 53:3d5a3d241a5e 1281 // End of file