Mark Underwood / Mbed OS MAX11043_Serial_Tester

Test program running on MAX32625MBED. Control through USB Serial commands using a terminal emulator such as teraterm or putty.

Dependencies:   MaximTinyTester CmdLine MAX541 USBDevice

MAX11043/MAX11043.cpp@67:5b8a495dda1c, 2020-02-20 (annotated)

Committer:
whismanoid
Date:
Thu Feb 20 01:16:25 2020 +0000
Revision:
67:5b8a495dda1c
Parent:
66:3fe92f6f1cfa
Child:
69:989e392cf635
MAX11043 support SPI hardware-controlled CS instead of GPIO CS (mbed); avoid mbed runtime error if pin is NC not connected

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 53:3d5a3d241a5e 1 // /*******************************************************************************
whismanoid 53:3d5a3d241a5e 2 // * Copyright (C) 2020 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 53:3d5a3d241a5e 3 // *
whismanoid 53:3d5a3d241a5e 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 53:3d5a3d241a5e 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 53:3d5a3d241a5e 6 // * to deal in the Software without restriction, including without limitation
whismanoid 53:3d5a3d241a5e 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 53:3d5a3d241a5e 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 53:3d5a3d241a5e 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 53:3d5a3d241a5e 10 // *
whismanoid 53:3d5a3d241a5e 11 // * The above copyright notice and this permission notice shall be included
whismanoid 53:3d5a3d241a5e 12 // * in all copies or substantial portions of the Software.
whismanoid 53:3d5a3d241a5e 13 // *
whismanoid 53:3d5a3d241a5e 14 // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid 53:3d5a3d241a5e 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 53:3d5a3d241a5e 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 53:3d5a3d241a5e 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 53:3d5a3d241a5e 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 53:3d5a3d241a5e 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 53:3d5a3d241a5e 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 53:3d5a3d241a5e 21 // *
whismanoid 53:3d5a3d241a5e 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 53:3d5a3d241a5e 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 53:3d5a3d241a5e 24 // * Products, Inc. Branding Policy.
whismanoid 53:3d5a3d241a5e 25 // *
whismanoid 53:3d5a3d241a5e 26 // * The mere transfer of this software does not imply any licenses
whismanoid 53:3d5a3d241a5e 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 53:3d5a3d241a5e 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 53:3d5a3d241a5e 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 53:3d5a3d241a5e 30 // * ownership rights.
whismanoid 53:3d5a3d241a5e 31 // *******************************************************************************
whismanoid 53:3d5a3d241a5e 32 // */
whismanoid 53:3d5a3d241a5e 33 // *********************************************************************
whismanoid 53:3d5a3d241a5e 34 // @file MAX11043.cpp
whismanoid 53:3d5a3d241a5e 35 // *********************************************************************
whismanoid 53:3d5a3d241a5e 36 // Device Driver file
whismanoid 53:3d5a3d241a5e 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid 53:3d5a3d241a5e 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 53:3d5a3d241a5e 39 // System Name = ExampleSystem
whismanoid 53:3d5a3d241a5e 40 // System Description = Device driver example
whismanoid 53:3d5a3d241a5e 41
whismanoid 53:3d5a3d241a5e 42 #include "MAX11043.h"
whismanoid 53:3d5a3d241a5e 43
whismanoid 53:3d5a3d241a5e 44 // Device Name = MAX11043
whismanoid 53:3d5a3d241a5e 45 // Device Description = 200ksps, Low-Power, Serial SPI 24-Bit, 4-Channel, Differential/Single-Ended Input, Simultaneous-Sampling SD ADC
whismanoid 53:3d5a3d241a5e 46 // Device DeviceBriefDescription = 24-bit 200ksps Delta-Sigma ADC
whismanoid 53:3d5a3d241a5e 47 // Device Manufacturer = Maxim Integrated
whismanoid 53:3d5a3d241a5e 48 // Device PartNumber = MAX11043ATL+
whismanoid 53:3d5a3d241a5e 49 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 53:3d5a3d241a5e 50 //
whismanoid 53:3d5a3d241a5e 51 // ADC MaxOutputDataRate = 200ksps
whismanoid 53:3d5a3d241a5e 52 // ADC NumChannels = 4
whismanoid 53:3d5a3d241a5e 53 // ADC ResolutionBits = 24
whismanoid 53:3d5a3d241a5e 54 //
whismanoid 53:3d5a3d241a5e 55 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 56 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 57 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 58 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 59 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 60 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 61 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 62 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 63 //
whismanoid 53:3d5a3d241a5e 64 // InputPin Name = CONVRUN
whismanoid 53:3d5a3d241a5e 65 // InputPin Description = CONVRUN (digital input). Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 53:3d5a3d241a5e 66 // CONVRUN is low.
whismanoid 53:3d5a3d241a5e 67 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 68 //
whismanoid 53:3d5a3d241a5e 69 // InputPin Name = SHDN
whismanoid 53:3d5a3d241a5e 70 // InputPin Description = Shutdown (digital input). Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 53:3d5a3d241a5e 71 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 72 //
whismanoid 53:3d5a3d241a5e 73 // InputPin Name = DACSTEP
whismanoid 53:3d5a3d241a5e 74 // InputPin Description = DACSTEP (digital input). DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 53:3d5a3d241a5e 75 // edge of the system clock.
whismanoid 53:3d5a3d241a5e 76 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 77 //
whismanoid 53:3d5a3d241a5e 78 // InputPin Name = UP/DWN#
whismanoid 53:3d5a3d241a5e 79 // InputPin Description = UP/DWN# (digital input). DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 53:3d5a3d241a5e 80 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 81 //
whismanoid 53:3d5a3d241a5e 82 // OutputPin Name = EOC
whismanoid 53:3d5a3d241a5e 83 // OutputPin Description = End of Conversion Output. Active-Low End-of-Conversion Indicator. EOC asserts low to indicate that new data is ready.
whismanoid 53:3d5a3d241a5e 84 // OutputPin Function = Event
whismanoid 53:3d5a3d241a5e 85 //
whismanoid 58:2fea32db466b 86 // SupplyPin Name = AVDD
whismanoid 58:2fea32db466b 87 // SupplyPin Description = Analog Power-Supply Input. Bypass each AVDD with a nominal 1uF capacitor to AGND.
whismanoid 58:2fea32db466b 88 // SupplyPin VinMax = 3.60
whismanoid 58:2fea32db466b 89 // SupplyPin VinMin = 3.00
whismanoid 58:2fea32db466b 90 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 91 //
whismanoid 58:2fea32db466b 92 // SupplyPin Name = AGND
whismanoid 58:2fea32db466b 93 // SupplyPin Description = Analog Ground. Connect all AGND inputs together.
whismanoid 58:2fea32db466b 94 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 95 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 96 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 97 //
whismanoid 58:2fea32db466b 98 // SupplyPin Name = DGND
whismanoid 58:2fea32db466b 99 // SupplyPin Description = Digital Ground. Connect all DGND inputs together.
whismanoid 58:2fea32db466b 100 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 101 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 102 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 103 //
whismanoid 58:2fea32db466b 104 // SupplyPin Name = DVDD
whismanoid 58:2fea32db466b 105 // SupplyPin Description = Digital Power-Supply Input. Bypass each DVDD with a nominal 1uF capacitor to DGND.
whismanoid 58:2fea32db466b 106 // SupplyPin VinMax = 3.60 (*TODO PENDING VERIFICATION*)
whismanoid 58:2fea32db466b 107 // SupplyPin VinMin = 3.00 (*TODO PENDING VERIFICATION*)
whismanoid 58:2fea32db466b 108 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 109 //
whismanoid 58:2fea32db466b 110 // SupplyPin Name = DVREG
whismanoid 58:2fea32db466b 111 // SupplyPin Description = Regulated Digital Core Supply (from internal +2.5V regulator). Bypass DVREG to DGND with a 10uF capacitor.
whismanoid 58:2fea32db466b 112 // SupplyPin VinMax = 2.50
whismanoid 58:2fea32db466b 113 // SupplyPin VinMin = 2.50
whismanoid 58:2fea32db466b 114 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 115 //
whismanoid 53:3d5a3d241a5e 116
whismanoid 53:3d5a3d241a5e 117 // CODE GENERATOR: class constructor definition
whismanoid 53:3d5a3d241a5e 118 MAX11043::MAX11043(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 53:3d5a3d241a5e 119 // CODE GENERATOR: class constructor definition gpio InputPin pins
whismanoid 53:3d5a3d241a5e 120 DigitalOut &CONVRUN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 121 DigitalOut &SHDN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 122 DigitalOut &DACSTEP_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 123 DigitalOut &UP_slash_DWNb_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 124 // CODE GENERATOR: class constructor definition gpio OutputPin pins
whismanoid 53:3d5a3d241a5e 125 DigitalIn &EOC_pin, // Digital Event Output from MAX11043 device
whismanoid 53:3d5a3d241a5e 126 // CODE GENERATOR: class constructor definition ic_variant
whismanoid 53:3d5a3d241a5e 127 MAX11043_ic_t ic_variant)
whismanoid 53:3d5a3d241a5e 128 // CODE GENERATOR: class constructor initializer list
whismanoid 53:3d5a3d241a5e 129 : m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid 53:3d5a3d241a5e 130 // CODE GENERATOR: class constructor initializer list gpio InputPin pins
whismanoid 53:3d5a3d241a5e 131 m_CONVRUN_pin(CONVRUN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 132 m_SHDN_pin(SHDN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 133 m_DACSTEP_pin(DACSTEP_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 134 m_UP_slash_DWNb_pin(UP_slash_DWNb_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 135 // CODE GENERATOR: class constructor initializer list gpio OutputPin pins
whismanoid 53:3d5a3d241a5e 136 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11043 device
whismanoid 53:3d5a3d241a5e 137 // CODE GENERATOR: class constructor initializer list ic_variant
whismanoid 53:3d5a3d241a5e 138 m_ic_variant(ic_variant)
whismanoid 53:3d5a3d241a5e 139 {
whismanoid 53:3d5a3d241a5e 140 // CODE GENERATOR: class constructor definition SPI interface initialization
whismanoid 53:3d5a3d241a5e 141 //
whismanoid 53:3d5a3d241a5e 142 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 143 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 144 m_SPI_cs_state = 1;
whismanoid 67:5b8a495dda1c 145 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 146 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 147 }
whismanoid 53:3d5a3d241a5e 148
whismanoid 53:3d5a3d241a5e 149 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 150 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 151 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 152 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 153 m_SPI_dataMode = 0; //SPI_MODE0; // CPOL=0,CPHA=0: Rising Edge stable; SCLK idle Low
whismanoid 53:3d5a3d241a5e 154 m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid 53:3d5a3d241a5e 155
whismanoid 53:3d5a3d241a5e 156 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 157 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 158 //#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid 53:3d5a3d241a5e 159 //#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid 53:3d5a3d241a5e 160 //#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid 53:3d5a3d241a5e 161 //#define SPI_SCLK_Hz 6000000 // 6MHz
whismanoid 53:3d5a3d241a5e 162 //#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid 53:3d5a3d241a5e 163 //#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid 53:3d5a3d241a5e 164 //#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid 61:b4f3051578ef 165 m_SPI_SCLK_Hz = 24000000; // platform limit 24MHz; MAX11043 limit is 40MHz
whismanoid 53:3d5a3d241a5e 166 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 167
whismanoid 53:3d5a3d241a5e 168 //
whismanoid 53:3d5a3d241a5e 169 // CODE GENERATOR: class constructor definition gpio InputPin (Input to device) initialization
whismanoid 53:3d5a3d241a5e 170 //
whismanoid 53:3d5a3d241a5e 171 // CONVRUN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 172 m_CONVRUN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 173 //
whismanoid 53:3d5a3d241a5e 174 // SHDN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 175 m_SHDN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 176 //
whismanoid 53:3d5a3d241a5e 177 // DACSTEP Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 178 m_DACSTEP_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 179 //
whismanoid 53:3d5a3d241a5e 180 // UP_slash_DWNb Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 181 m_UP_slash_DWNb_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 182 //
whismanoid 53:3d5a3d241a5e 183 // CODE GENERATOR: class constructor definition gpio OutputPin (Output from MAX11043 device) initialization
whismanoid 53:3d5a3d241a5e 184 //
whismanoid 53:3d5a3d241a5e 185 // EOC Event Output from device
whismanoid 53:3d5a3d241a5e 186 }
whismanoid 53:3d5a3d241a5e 187
whismanoid 53:3d5a3d241a5e 188 // CODE GENERATOR: class destructor definition
whismanoid 53:3d5a3d241a5e 189 MAX11043::~MAX11043()
whismanoid 53:3d5a3d241a5e 190 {
whismanoid 53:3d5a3d241a5e 191 // do nothing
whismanoid 53:3d5a3d241a5e 192 }
whismanoid 53:3d5a3d241a5e 193
whismanoid 53:3d5a3d241a5e 194 // CODE GENERATOR: spi_frequency setter definition
whismanoid 53:3d5a3d241a5e 195 /// set SPI SCLK frequency
whismanoid 53:3d5a3d241a5e 196 void MAX11043::spi_frequency(int spi_sclk_Hz)
whismanoid 53:3d5a3d241a5e 197 {
whismanoid 53:3d5a3d241a5e 198 m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid 53:3d5a3d241a5e 199 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 200 }
whismanoid 53:3d5a3d241a5e 201
whismanoid 53:3d5a3d241a5e 202 // CODE GENERATOR: omit global g_MAX11043_device
whismanoid 53:3d5a3d241a5e 203 // CODE GENERATOR: extern function declarations
whismanoid 53:3d5a3d241a5e 204 // CODE GENERATOR: extern function requirement MAX11043::SPIoutputCS
whismanoid 53:3d5a3d241a5e 205 // Assert SPI Chip Select
whismanoid 53:3d5a3d241a5e 206 // SPI chip-select for MAX11043
whismanoid 53:3d5a3d241a5e 207 //
whismanoid 62:8223a7253c90 208 inline void MAX11043::SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 209 {
whismanoid 53:3d5a3d241a5e 210 // CODE GENERATOR: extern function definition for function SPIoutputCS
whismanoid 53:3d5a3d241a5e 211 // CODE GENERATOR: extern function definition for standard SPI interface function SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 212 m_SPI_cs_state = isLogicHigh;
whismanoid 67:5b8a495dda1c 213 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 214 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 215 }
whismanoid 53:3d5a3d241a5e 216 }
whismanoid 53:3d5a3d241a5e 217
whismanoid 62:8223a7253c90 218 // CODE GENERATOR: extern function requirement MAX11043::SPIreadWriteWithLowCS
whismanoid 62:8223a7253c90 219 // SPI read and write arbitrary number of 8-bit bytes
whismanoid 62:8223a7253c90 220 // SPI interface to MAX11043 shift mosiData into MAX11043 DIN
whismanoid 62:8223a7253c90 221 // while simultaneously capturing miso data from MAX11043 DOUT
whismanoid 62:8223a7253c90 222 //
whismanoid 62:8223a7253c90 223 int MAX11043::SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 224 {
whismanoid 62:8223a7253c90 225 // CODE GENERATOR: extern function definition for function SPIreadWriteWithLowCS
whismanoid 63:8f39d21d6157 226 // TODO1: CODE GENERATOR: extern function definition for standard SPI interface function SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 227 //size_t byteCount = 4;
whismanoid 62:8223a7253c90 228 //static char mosiData[4];
whismanoid 62:8223a7253c90 229 //static char misoData[4];
whismanoid 62:8223a7253c90 230 //
whismanoid 62:8223a7253c90 231 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 232 //~ noInterrupts();
whismanoid 62:8223a7253c90 233 //
whismanoid 62:8223a7253c90 234 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 235 //
whismanoid 67:5b8a495dda1c 236 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 237 m_cs_pin = 0;
whismanoid 67:5b8a495dda1c 238 }
whismanoid 62:8223a7253c90 239 unsigned int numBytesTransferred = m_spi.write((char*)mosiData, byteCount, (char*)misoData, byteCount);
whismanoid 67:5b8a495dda1c 240 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 241 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 242 }
whismanoid 62:8223a7253c90 243 //
whismanoid 62:8223a7253c90 244 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 245 //
whismanoid 62:8223a7253c90 246 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 247 //~ interrupts();
whismanoid 62:8223a7253c90 248 // Optional Diagnostic function to print SPI transactions
whismanoid 62:8223a7253c90 249 if (onSPIprint)
whismanoid 62:8223a7253c90 250 {
whismanoid 62:8223a7253c90 251 onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
whismanoid 62:8223a7253c90 252 }
whismanoid 62:8223a7253c90 253 return numBytesTransferred;
whismanoid 62:8223a7253c90 254 }
whismanoid 62:8223a7253c90 255
whismanoid 53:3d5a3d241a5e 256 // TODO1: CODE GENERATOR: extern function GPIOoutputSHDN alias SHDNoutputValue
whismanoid 53:3d5a3d241a5e 257 // CODE GENERATOR: extern function requirement MAX11043::SHDNoutputValue
whismanoid 58:2fea32db466b 258 // Assert MAX11043 SHDN pin : High = Shut Down, Low = Normal Operation.
whismanoid 53:3d5a3d241a5e 259 //
whismanoid 53:3d5a3d241a5e 260 void MAX11043::SHDNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 261 {
whismanoid 53:3d5a3d241a5e 262 // CODE GENERATOR: extern function definition for function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 263 // TODO1: CODE GENERATOR: extern function definition for gpio interface function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 264 // TODO1: CODE GENERATOR: gpio pin SHDN assuming member function m_SHDN_pin
whismanoid 53:3d5a3d241a5e 265 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 266 // m_SHDN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 267 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 268 m_SHDN_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 269 }
whismanoid 52:607010f0c54e 270
whismanoid 53:3d5a3d241a5e 271 // TODO1: CODE GENERATOR: extern function GPIOoutputCONVRUN alias CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 272 // CODE GENERATOR: extern function requirement MAX11043::CONVRUNoutputValue
whismanoid 58:2fea32db466b 273 // Assert MAX11043 CONVRUN pin : High = start continuous conversions on all 4 channels, Low = Idle.
whismanoid 53:3d5a3d241a5e 274 //
whismanoid 53:3d5a3d241a5e 275 void MAX11043::CONVRUNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 276 {
whismanoid 53:3d5a3d241a5e 277 // CODE GENERATOR: extern function definition for function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 278 // TODO1: CODE GENERATOR: extern function definition for gpio interface function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 279 // TODO1: CODE GENERATOR: gpio pin CONVRUN assuming member function m_CONVRUN_pin
whismanoid 53:3d5a3d241a5e 280 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 281 // m_CONVRUN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 282 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 283 m_CONVRUN_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 284 }
whismanoid 53:3d5a3d241a5e 285
whismanoid 53:3d5a3d241a5e 286 // TODO1: CODE GENERATOR: extern function GPIOoutputDACSTEP alias DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 287 // CODE GENERATOR: extern function requirement MAX11043::DACSTEPoutputValue
whismanoid 58:2fea32db466b 288 // Assert MAX11043 DACSTEP pin : High = Active, Low = Idle.
whismanoid 53:3d5a3d241a5e 289 //
whismanoid 53:3d5a3d241a5e 290 void MAX11043::DACSTEPoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 291 {
whismanoid 53:3d5a3d241a5e 292 // CODE GENERATOR: extern function definition for function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 293 // TODO1: CODE GENERATOR: extern function definition for gpio interface function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 294 // TODO1: CODE GENERATOR: gpio pin DACSTEP assuming member function m_DACSTEP_pin
whismanoid 53:3d5a3d241a5e 295 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 296 // m_DACSTEP_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 297 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 298 m_DACSTEP_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 299 }
whismanoid 53:3d5a3d241a5e 300
whismanoid 53:3d5a3d241a5e 301 // TODO1: CODE GENERATOR: extern function GPIOoutputUP_slash_DWNb alias UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 302 // CODE GENERATOR: extern function requirement MAX11043::UP_slash_DWNboutputValue
whismanoid 58:2fea32db466b 303 // Assert MAX11043 UP_slash_DWNb pin : High = Up, Low = Down.
whismanoid 53:3d5a3d241a5e 304 //
whismanoid 53:3d5a3d241a5e 305 void MAX11043::UP_slash_DWNboutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 306 {
whismanoid 53:3d5a3d241a5e 307 // CODE GENERATOR: extern function definition for function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 308 // TODO1: CODE GENERATOR: extern function definition for gpio interface function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 309 // TODO1: CODE GENERATOR: gpio pin UP_slash_DWNb assuming member function m_UP_slash_DWNb_pin
whismanoid 53:3d5a3d241a5e 310 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 311 // m_UP_slash_DWNb_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 312 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 313 m_UP_slash_DWNb_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 314 }
whismanoid 53:3d5a3d241a5e 315
whismanoid 53:3d5a3d241a5e 316 // CODE GENERATOR: extern function requirement MAX11043::EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 317 // Wait for MAX11043 EOC pin low, indicating end of conversion.
whismanoid 53:3d5a3d241a5e 318 // Required when using any of the InternalClock modes.
whismanoid 53:3d5a3d241a5e 319 //
whismanoid 53:3d5a3d241a5e 320 void MAX11043::EOCinputWaitUntilLow()
whismanoid 53:3d5a3d241a5e 321 {
whismanoid 53:3d5a3d241a5e 322 // CODE GENERATOR: extern function definition for function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 323 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 324 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 325 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 326 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 327 // TODO1: CODE GENERATOR: gpio function WaitUntilLow
whismanoid 53:3d5a3d241a5e 328 while (m_EOC_pin != 0)
whismanoid 53:3d5a3d241a5e 329 {
whismanoid 53:3d5a3d241a5e 330 // spinlock waiting for logic low pin state
whismanoid 53:3d5a3d241a5e 331 }
whismanoid 53:3d5a3d241a5e 332 }
whismanoid 53:3d5a3d241a5e 333
whismanoid 53:3d5a3d241a5e 334 // CODE GENERATOR: extern function requirement MAX11043::EOCinputValue
whismanoid 53:3d5a3d241a5e 335 // Return the status of the MAX11043 EOC pin.
whismanoid 53:3d5a3d241a5e 336 //
whismanoid 53:3d5a3d241a5e 337 int MAX11043::EOCinputValue()
whismanoid 53:3d5a3d241a5e 338 {
whismanoid 53:3d5a3d241a5e 339 // CODE GENERATOR: extern function definition for function EOCinputValue
whismanoid 53:3d5a3d241a5e 340 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputValue
whismanoid 53:3d5a3d241a5e 341 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 342 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 343 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 344 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 345 return m_EOC_pin.read();
whismanoid 53:3d5a3d241a5e 346 }
whismanoid 53:3d5a3d241a5e 347
whismanoid 53:3d5a3d241a5e 348 // CODE GENERATOR: class member function definitions
whismanoid 53:3d5a3d241a5e 349 //----------------------------------------
whismanoid 53:3d5a3d241a5e 350 // Menu item '!'
whismanoid 53:3d5a3d241a5e 351 // Initialize device
whismanoid 53:3d5a3d241a5e 352 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 353 uint8_t MAX11043::Init(void)
whismanoid 53:3d5a3d241a5e 354 {
whismanoid 53:3d5a3d241a5e 355
whismanoid 53:3d5a3d241a5e 356 //----------------------------------------
whismanoid 59:47538bcf6cda 357 // reference voltage, in Volts
whismanoid 59:47538bcf6cda 358 VRef = 2.500;
whismanoid 59:47538bcf6cda 359
whismanoid 59:47538bcf6cda 360 //----------------------------------------
whismanoid 59:47538bcf6cda 361 // shadow of register config CMD_0010_0010_d16_Rd08_Configuration
whismanoid 59:47538bcf6cda 362 config = 0x6000;
whismanoid 59:47538bcf6cda 363
whismanoid 59:47538bcf6cda 364 //----------------------------------------
whismanoid 59:47538bcf6cda 365 // shadow of register status CMD_0001_1110_d8_Rd07_Status
whismanoid 59:47538bcf6cda 366 status = 0x00;
whismanoid 53:3d5a3d241a5e 367
whismanoid 53:3d5a3d241a5e 368 //----------------------------------------
whismanoid 59:47538bcf6cda 369 // shadow of register ADCa CMD_0000_0010_d16o8_Rd00_ADCa
whismanoid 59:47538bcf6cda 370 adca = 0x0000;
whismanoid 53:3d5a3d241a5e 371
whismanoid 53:3d5a3d241a5e 372 //----------------------------------------
whismanoid 59:47538bcf6cda 373 // shadow of register ADCb CMD_0000_0110_d16o8_Rd01_ADCb
whismanoid 59:47538bcf6cda 374 adcb = 0x0000;
whismanoid 59:47538bcf6cda 375
whismanoid 59:47538bcf6cda 376 //----------------------------------------
whismanoid 59:47538bcf6cda 377 // shadow of register ADCc CMD_0000_1010_d16o8_Rd02_ADCc
whismanoid 59:47538bcf6cda 378 adcc = 0x0000;
whismanoid 59:47538bcf6cda 379
whismanoid 59:47538bcf6cda 380 //----------------------------------------
whismanoid 59:47538bcf6cda 381 // shadow of register ADCd CMD_0000_1110_d16o8_Rd03_ADCd
whismanoid 59:47538bcf6cda 382 adcd = 0x0000;
whismanoid 53:3d5a3d241a5e 383
whismanoid 53:3d5a3d241a5e 384 //----------------------------------------
whismanoid 53:3d5a3d241a5e 385 // init (based on old EV kit GUI)
whismanoid 53:3d5a3d241a5e 386 #warning "Not Implemented Yet: MAX11043::Init init..."
whismanoid 53:3d5a3d241a5e 387 // bool bOpResult = false;
whismanoid 53:3d5a3d241a5e 388 // String FWVersionString = "00";
whismanoid 53:3d5a3d241a5e 389 // bool bDemoMode = true;
whismanoid 53:3d5a3d241a5e 390 // int scan_resolution = 0;
whismanoid 53:3d5a3d241a5e 391 // int scan_channels = 0;
whismanoid 53:3d5a3d241a5e 392 // int scan_bits = 0;
whismanoid 53:3d5a3d241a5e 393 // int sampleRateFactore = 0;
whismanoid 53:3d5a3d241a5e 394 // double sampleRate = 0;
whismanoid 53:3d5a3d241a5e 395 // unsigned long banks_requested = 0;
whismanoid 53:3d5a3d241a5e 396 // bool bScanMode = 0;
whismanoid 53:3d5a3d241a5e 397
whismanoid 53:3d5a3d241a5e 398 //----------------------------------------
whismanoid 59:47538bcf6cda 399 // Device ID Validation -- not used, no device ID register
whismanoid 53:3d5a3d241a5e 400 #warning "Not Implemented Yet: MAX11043::Init Device ID Validation..."
whismanoid 53:3d5a3d241a5e 401 // const uint32_t part_id_expect = 0x000F02;
whismanoid 53:3d5a3d241a5e 402 // uint32_t part_id_readback;
whismanoid 53:3d5a3d241a5e 403 // RegRead(xxxxxxxxxxxxCMD_r001_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xddd_PART_ID, &part_id_readback);
whismanoid 53:3d5a3d241a5e 404 // if (part_id_readback != part_id_expect) return 0;
whismanoid 53:3d5a3d241a5e 405
whismanoid 53:3d5a3d241a5e 406 //----------------------------------------
whismanoid 58:2fea32db466b 407 // Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 58:2fea32db466b 408 SHDNoutputValue(0); // SHDN Inactive
whismanoid 58:2fea32db466b 409
whismanoid 58:2fea32db466b 410 //----------------------------------------
whismanoid 58:2fea32db466b 411 // Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 58:2fea32db466b 412 // CONVRUN is low.
whismanoid 58:2fea32db466b 413 CONVRUNoutputValue(0); // CONVRUN Idle
whismanoid 58:2fea32db466b 414
whismanoid 58:2fea32db466b 415 //----------------------------------------
whismanoid 58:2fea32db466b 416 // DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 58:2fea32db466b 417 // edge of the system clock.
whismanoid 58:2fea32db466b 418 DACSTEPoutputValue(0); // DACSTEP Idle
whismanoid 58:2fea32db466b 419
whismanoid 58:2fea32db466b 420 //----------------------------------------
whismanoid 58:2fea32db466b 421 // DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 58:2fea32db466b 422 UP_slash_DWNboutputValue(0); // UP/DWN# Down
whismanoid 58:2fea32db466b 423
whismanoid 58:2fea32db466b 424 //----------------------------------------
whismanoid 53:3d5a3d241a5e 425 // success
whismanoid 53:3d5a3d241a5e 426 return 1;
whismanoid 53:3d5a3d241a5e 427 }
whismanoid 53:3d5a3d241a5e 428
whismanoid 53:3d5a3d241a5e 429 //----------------------------------------
whismanoid 53:3d5a3d241a5e 430 // Write a MAX11043 register.
whismanoid 53:3d5a3d241a5e 431 //
whismanoid 57:1c9da8e90737 432 // CMDOP_1aaa_aaaa_ReadRegister bit is cleared 0 indicating a write operation.
whismanoid 53:3d5a3d241a5e 433 //
whismanoid 53:3d5a3d241a5e 434 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 435 //
whismanoid 53:3d5a3d241a5e 436 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 437 //
whismanoid 53:3d5a3d241a5e 438 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 439 //
whismanoid 53:3d5a3d241a5e 440 // SPI MOSI = 0aaa_aaaa_dddd_dddd
whismanoid 53:3d5a3d241a5e 441 //
whismanoid 53:3d5a3d241a5e 442 // SPI MISO = xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 443 //
whismanoid 53:3d5a3d241a5e 444 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 445 //
whismanoid 53:3d5a3d241a5e 446 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 447 //
whismanoid 53:3d5a3d241a5e 448 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 449 //
whismanoid 53:3d5a3d241a5e 450 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 451 //
whismanoid 53:3d5a3d241a5e 452 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 453 //
whismanoid 53:3d5a3d241a5e 454 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 455 //
whismanoid 53:3d5a3d241a5e 456 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 457 //
whismanoid 53:3d5a3d241a5e 458 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 459 //
whismanoid 53:3d5a3d241a5e 460 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 461 uint8_t MAX11043::RegWrite(MAX11043_CMD_enum_t commandByte, uint32_t regData)
whismanoid 53:3d5a3d241a5e 462 {
whismanoid 53:3d5a3d241a5e 463
whismanoid 53:3d5a3d241a5e 464 //----------------------------------------
whismanoid 53:3d5a3d241a5e 465 // switch based on register address szie RegSize(commandByte)
whismanoid 57:1c9da8e90737 466 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 467 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 468 {
whismanoid 53:3d5a3d241a5e 469 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 470 {
whismanoid 63:8f39d21d6157 471 // SPI 8+8 = 16-bit transfer
whismanoid 63:8f39d21d6157 472 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 473 // SPI MOSI = 0aaa_aaaa_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 474 // SPI MISO = xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 475 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 476 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 477 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 478 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 479 mosiData[1] = regData;
whismanoid 63:8f39d21d6157 480 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 481 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 482 // TODO: cache CMD_0101_0100_d8_Wr15_FilterCAddress
whismanoid 63:8f39d21d6157 483 // if (commandByte == CMD_0101_0100_d8_Wr15_FilterCAddress) {
whismanoid 63:8f39d21d6157 484 // FilterCAddress = regData;
whismanoid 63:8f39d21d6157 485 // }
whismanoid 63:8f39d21d6157 486 // TODO: cache CMD_0110_0000_d8_Wr18_FlashMode
whismanoid 63:8f39d21d6157 487 // if (commandByte == CMD_0110_0000_d8_Wr18_FlashMode) {
whismanoid 63:8f39d21d6157 488 // FlashMode = regData;
whismanoid 63:8f39d21d6157 489 // }
whismanoid 53:3d5a3d241a5e 490 }
whismanoid 53:3d5a3d241a5e 491 break;
whismanoid 53:3d5a3d241a5e 492 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 493 #warning "Not Verified Yet: MAX11043::RegWrite 16-bit"
whismanoid 53:3d5a3d241a5e 494 {
whismanoid 63:8f39d21d6157 495 // SPI 8+16 = 24-bit transfer
whismanoid 63:8f39d21d6157 496 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 63:8f39d21d6157 497 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 498 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 499 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 500 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 501 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 502 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 503 mosiData[1] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 504 mosiData[2] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 505 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 506 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 507 // cache CMD_0010_0000_d16_Wr08_Configuration
whismanoid 63:8f39d21d6157 508 if (commandByte == CMD_0010_0000_d16_Wr08_Configuration) {
whismanoid 63:8f39d21d6157 509 config = regData;
whismanoid 63:8f39d21d6157 510 }
whismanoid 63:8f39d21d6157 511 // TODO: cache CMD_0010_0100_d16_Wr09_DAC
whismanoid 63:8f39d21d6157 512 // TODO: cache CMD_0010_1000_d16_Wr0A_DACStep
whismanoid 63:8f39d21d6157 513 // TODO: cache CMD_0010_1100_d16_Wr0B_DACHDACL
whismanoid 63:8f39d21d6157 514 // TODO: cache CMD_0011_0000_d16_Wr0C_ConfigA
whismanoid 63:8f39d21d6157 515 // TODO: cache CMD_0011_0100_d16_Wr0D_ConfigB
whismanoid 63:8f39d21d6157 516 // TODO: cache CMD_0011_1000_d16_Wr0E_ConfigC
whismanoid 63:8f39d21d6157 517 // TODO: cache CMD_0011_1100_d16_Wr0F_ConfigD
whismanoid 63:8f39d21d6157 518 // TODO: cache CMD_0100_0000_d16_Wr10_Reference
whismanoid 63:8f39d21d6157 519 // TODO: cache CMD_0100_0100_d16_Wr11_AGain
whismanoid 63:8f39d21d6157 520 // TODO: cache CMD_0100_1000_d16_Wr12_BGain
whismanoid 63:8f39d21d6157 521 // TODO: cache CMD_0100_1100_d16_Wr13_CGain
whismanoid 63:8f39d21d6157 522 // TODO: cache CMD_0101_0000_d16_Wr14_DGain
whismanoid 63:8f39d21d6157 523 // TODO: cache CMD_0110_0100_d16_Wr19_FlashAddr
whismanoid 63:8f39d21d6157 524 // TODO: cache CMD_0110_1000_d16_Wr1A_FlashDataIn
whismanoid 53:3d5a3d241a5e 525 }
whismanoid 53:3d5a3d241a5e 526 break;
whismanoid 63:8f39d21d6157 527 case 32: // 32-bit register size
whismanoid 63:8f39d21d6157 528 #warning "Not Verified Yet: MAX11043::RegWrite 32-bit"
whismanoid 53:3d5a3d241a5e 529 {
whismanoid 63:8f39d21d6157 530 // SPI 8+32 = 40-bit transfer
whismanoid 63:8f39d21d6157 531 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 63:8f39d21d6157 532 // SPI MOSI = 1aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 533 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 534 //
whismanoid 63:8f39d21d6157 535 size_t byteCount = 1 + (2 * 2);
whismanoid 63:8f39d21d6157 536 uint8_t mosiData[5];
whismanoid 63:8f39d21d6157 537 uint8_t misoData[5];
whismanoid 63:8f39d21d6157 538 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 539 mosiData[1] = (uint8_t)((regData >> 24) & 0xFF);
whismanoid 63:8f39d21d6157 540 mosiData[2] = (uint8_t)((regData >> 16) & 0xFF);
whismanoid 63:8f39d21d6157 541 mosiData[3] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 542 mosiData[4] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 543 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 544 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 545 // TODO: cache CMD_0101_1000_d32_Wr16_FilterCDataOut
whismanoid 63:8f39d21d6157 546 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 547 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 548 // }
whismanoid 63:8f39d21d6157 549 // TODO: cache CMD_0101_1100_d32_Wr17_FilterCDataIn
whismanoid 63:8f39d21d6157 550 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 551 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 552 // }
whismanoid 53:3d5a3d241a5e 553 }
whismanoid 53:3d5a3d241a5e 554 break;
whismanoid 53:3d5a3d241a5e 555 }
whismanoid 53:3d5a3d241a5e 556
whismanoid 53:3d5a3d241a5e 557 //----------------------------------------
whismanoid 53:3d5a3d241a5e 558 // success
whismanoid 53:3d5a3d241a5e 559 return 1;
whismanoid 53:3d5a3d241a5e 560 }
whismanoid 53:3d5a3d241a5e 561
whismanoid 53:3d5a3d241a5e 562 //----------------------------------------
whismanoid 53:3d5a3d241a5e 563 // Read an 8-bit MAX11043 register
whismanoid 53:3d5a3d241a5e 564 //
whismanoid 57:1c9da8e90737 565 // CMDOP_1aaa_aaaa_ReadRegister bit is set 1 indicating a read operation.
whismanoid 53:3d5a3d241a5e 566 //
whismanoid 53:3d5a3d241a5e 567 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 568 //
whismanoid 53:3d5a3d241a5e 569 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 570 //
whismanoid 53:3d5a3d241a5e 571 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 572 //
whismanoid 53:3d5a3d241a5e 573 // SPI MOSI = 1aaa_aaaa_0000_0000
whismanoid 53:3d5a3d241a5e 574 //
whismanoid 53:3d5a3d241a5e 575 // SPI MISO = xxxx_xxxx_dddd_dddd
whismanoid 53:3d5a3d241a5e 576 //
whismanoid 53:3d5a3d241a5e 577 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 578 //
whismanoid 53:3d5a3d241a5e 579 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 580 //
whismanoid 53:3d5a3d241a5e 581 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 582 //
whismanoid 53:3d5a3d241a5e 583 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 584 //
whismanoid 53:3d5a3d241a5e 585 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 586 //
whismanoid 53:3d5a3d241a5e 587 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 588 //
whismanoid 53:3d5a3d241a5e 589 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 590 //
whismanoid 53:3d5a3d241a5e 591 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 592 //
whismanoid 53:3d5a3d241a5e 593 //
whismanoid 53:3d5a3d241a5e 594 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 595 uint8_t MAX11043::RegRead(MAX11043_CMD_enum_t commandByte, uint32_t* ptrRegData)
whismanoid 53:3d5a3d241a5e 596 {
whismanoid 53:3d5a3d241a5e 597
whismanoid 53:3d5a3d241a5e 598 //----------------------------------------
whismanoid 53:3d5a3d241a5e 599 // switch based on register address szie RegSize(regAddress)
whismanoid 57:1c9da8e90737 600 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 601 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 602 {
whismanoid 53:3d5a3d241a5e 603 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 604 {
whismanoid 60:d1d1eaa90fb7 605 // SPI 8+8 = 16-bit transfer
whismanoid 62:8223a7253c90 606 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 607 // SPI MOSI = 1aaa_aaaa_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 608 // SPI MISO = xxxx_xxxx_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 609 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 610 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 611 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 612 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 613 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 614 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 615 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 616 if (ptrRegData) { (*ptrRegData) = misoData[1]; }
whismanoid 59:47538bcf6cda 617 if (commandByte == CMD_0001_1110_d8_Rd07_Status) {
whismanoid 59:47538bcf6cda 618 // TODO1: update status
whismanoid 63:8f39d21d6157 619 status = misoData[1];
whismanoid 59:47538bcf6cda 620 }
whismanoid 53:3d5a3d241a5e 621 }
whismanoid 53:3d5a3d241a5e 622 break;
whismanoid 53:3d5a3d241a5e 623 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 624 #warning "Not Verified Yet: MAX11043::RegRead 16-bit"
whismanoid 53:3d5a3d241a5e 625 {
whismanoid 60:d1d1eaa90fb7 626 // SPI 8+16 = 24-bit transfer
whismanoid 62:8223a7253c90 627 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 60:d1d1eaa90fb7 628 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 629 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 630 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 631 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 632 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 633 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 634 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 635 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 636 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 637 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 638 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 59:47538bcf6cda 639 if (commandByte == CMD_0010_0010_d16_Rd08_Configuration) {
whismanoid 59:47538bcf6cda 640 // TODO1: update config
whismanoid 63:8f39d21d6157 641 config = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 642 }
whismanoid 59:47538bcf6cda 643 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 644 // TODO1: update adca
whismanoid 63:8f39d21d6157 645 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 646 }
whismanoid 59:47538bcf6cda 647 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 648 // TODO1: update adcb
whismanoid 63:8f39d21d6157 649 adcb = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 650 }
whismanoid 59:47538bcf6cda 651 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 652 // TODO1: update adcc
whismanoid 63:8f39d21d6157 653 adcc = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 654 }
whismanoid 59:47538bcf6cda 655 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 656 // TODO1: update adcd
whismanoid 63:8f39d21d6157 657 adcd = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 658 }
whismanoid 53:3d5a3d241a5e 659 }
whismanoid 53:3d5a3d241a5e 660 break;
whismanoid 53:3d5a3d241a5e 661 case 24: // 24-bit register size
whismanoid 53:3d5a3d241a5e 662 {
whismanoid 60:d1d1eaa90fb7 663 // SPI 8+24 = 32-bit transfer
whismanoid 62:8223a7253c90 664 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32
whismanoid 63:8f39d21d6157 665 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 666 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 667 size_t byteCount = 1 + 3;
whismanoid 63:8f39d21d6157 668 uint8_t mosiData[4];
whismanoid 63:8f39d21d6157 669 uint8_t misoData[4];
whismanoid 63:8f39d21d6157 670 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 671 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 672 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 673 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 674 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 675 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 676 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 59:47538bcf6cda 677 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 678 // TODO1: update adca
whismanoid 63:8f39d21d6157 679 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 680 }
whismanoid 59:47538bcf6cda 681 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 682 // TODO1: update adcb
whismanoid 63:8f39d21d6157 683 adcb = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 684 }
whismanoid 59:47538bcf6cda 685 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 686 // TODO1: update adcc
whismanoid 63:8f39d21d6157 687 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 688 }
whismanoid 59:47538bcf6cda 689 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 690 // TODO1: update adcd
whismanoid 63:8f39d21d6157 691 adcd = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 692 }
whismanoid 59:47538bcf6cda 693 }
whismanoid 59:47538bcf6cda 694 break;
whismanoid 63:8f39d21d6157 695 case 32: // 32-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 696 //
whismanoid 63:8f39d21d6157 697 #warning "Not Implemented Yet: MAX11043::RegRead 32-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 698 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 699 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 700 // update adca, adcb
whismanoid 59:47538bcf6cda 701 //
whismanoid 63:8f39d21d6157 702 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 703 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 704 // update adcc, adcd
whismanoid 59:47538bcf6cda 705 //
whismanoid 59:47538bcf6cda 706 {
whismanoid 60:d1d1eaa90fb7 707 // SPI 8+32 = 40-bit transfer
whismanoid 62:8223a7253c90 708 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 60:d1d1eaa90fb7 709 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 710 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 711 size_t byteCount = 1 + (2 * 2);
whismanoid 62:8223a7253c90 712 uint8_t mosiData[5];
whismanoid 62:8223a7253c90 713 uint8_t misoData[5];
whismanoid 62:8223a7253c90 714 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 715 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 716 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 717 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 718 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 719 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 720 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 721 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 722 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 723 // TODO1: update adca
whismanoid 62:8223a7253c90 724 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 725 // TODO1: update adcb
whismanoid 62:8223a7253c90 726 adcb = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 727 }
whismanoid 63:8f39d21d6157 728 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 729 // TODO1: update adcc
whismanoid 62:8223a7253c90 730 adcc = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 731 // TODO1: update adcd
whismanoid 62:8223a7253c90 732 adcd = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 733 }
whismanoid 59:47538bcf6cda 734 }
whismanoid 59:47538bcf6cda 735 break;
whismanoid 63:8f39d21d6157 736 case 48: // 48-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 737 //
whismanoid 63:8f39d21d6157 738 #warning "Not Verified Yet: MAX11043::RegRead 48-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 739 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 740 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 741 // update adca, adcb
whismanoid 59:47538bcf6cda 742 //
whismanoid 63:8f39d21d6157 743 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 744 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 745 // update adcc, adcd
whismanoid 59:47538bcf6cda 746 //
whismanoid 59:47538bcf6cda 747 {
whismanoid 60:d1d1eaa90fb7 748 // SPI 8+48 = 56-bit transfer
whismanoid 62:8223a7253c90 749 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56
whismanoid 60:d1d1eaa90fb7 750 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 751 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 752 size_t byteCount = 1 + (3 * 2);
whismanoid 62:8223a7253c90 753 uint8_t mosiData[7];
whismanoid 62:8223a7253c90 754 uint8_t misoData[7];
whismanoid 62:8223a7253c90 755 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 756 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 757 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 758 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 759 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 760 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 761 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 762 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 763 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 764 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 765 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 766 // TODO1: update adca
whismanoid 62:8223a7253c90 767 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 768 // TODO1: update adcb
whismanoid 62:8223a7253c90 769 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 770 }
whismanoid 63:8f39d21d6157 771 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 772 // TODO1: update adcc
whismanoid 62:8223a7253c90 773 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 774 // TODO1: update adcd
whismanoid 62:8223a7253c90 775 adcd = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 776 }
whismanoid 59:47538bcf6cda 777 }
whismanoid 59:47538bcf6cda 778 break;
whismanoid 63:8f39d21d6157 779 case 64: // 64-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 780 //
whismanoid 63:8f39d21d6157 781 #warning "Not Verified Yet: MAX11043::RegRead 64-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 782 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 783 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 784 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 785 //
whismanoid 59:47538bcf6cda 786 {
whismanoid 60:d1d1eaa90fb7 787 // SPI 8+64 = 72-bit transfer
whismanoid 62:8223a7253c90 788 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72
whismanoid 60:d1d1eaa90fb7 789 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 790 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 791 size_t byteCount = 1 + (2 * 4);
whismanoid 62:8223a7253c90 792 uint8_t mosiData[9];
whismanoid 62:8223a7253c90 793 uint8_t misoData[9];
whismanoid 62:8223a7253c90 794 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 795 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 796 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 797 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 798 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 799 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 800 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 801 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 802 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 803 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 804 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 805 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 806 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 807 // TODO1: update adca
whismanoid 62:8223a7253c90 808 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 809 // TODO1: update adcb
whismanoid 62:8223a7253c90 810 adcb = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 811 // TODO1: update adcc
whismanoid 62:8223a7253c90 812 adcc = (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 813 // TODO1: update adcd
whismanoid 62:8223a7253c90 814 adcd = (misoData[7] << 8) | misoData[8];
whismanoid 59:47538bcf6cda 815 }
whismanoid 59:47538bcf6cda 816 }
whismanoid 59:47538bcf6cda 817 break;
whismanoid 63:8f39d21d6157 818 case 96: // 96-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 819 //
whismanoid 63:8f39d21d6157 820 #warning "Not Verified Yet: MAX11043::RegRead 96-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 821 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 822 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 823 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 824 //
whismanoid 59:47538bcf6cda 825 {
whismanoid 60:d1d1eaa90fb7 826 // SPI 8+96 = 104-bit transfer
whismanoid 62:8223a7253c90 827 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72 ___[9]_80 __[10]_88 __[11]_96 __[12]104
whismanoid 60:d1d1eaa90fb7 828 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 829 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 830 size_t byteCount = 1 + (3 * 4);
whismanoid 62:8223a7253c90 831 uint8_t mosiData[13];
whismanoid 62:8223a7253c90 832 uint8_t misoData[13];
whismanoid 62:8223a7253c90 833 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 834 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 835 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 836 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 837 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 838 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 839 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 840 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 841 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 842 mosiData[9] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 843 mosiData[10] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 844 mosiData[11] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 845 mosiData[12] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 846 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 847 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 848 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 849 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 850 // TODO1: update adca
whismanoid 62:8223a7253c90 851 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 852 // TODO1: update adcb
whismanoid 62:8223a7253c90 853 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 854 // TODO1: update adcc
whismanoid 62:8223a7253c90 855 adcc = (misoData[7] << 16) | (misoData[8] << 8) | misoData[9];
whismanoid 59:47538bcf6cda 856 // TODO1: update adcd
whismanoid 62:8223a7253c90 857 adcd = (misoData[10] << 16) | (misoData[11] << 8) | misoData[12];
whismanoid 59:47538bcf6cda 858 }
whismanoid 53:3d5a3d241a5e 859 }
whismanoid 53:3d5a3d241a5e 860 break;
whismanoid 53:3d5a3d241a5e 861 }
whismanoid 53:3d5a3d241a5e 862
whismanoid 53:3d5a3d241a5e 863 //----------------------------------------
whismanoid 53:3d5a3d241a5e 864 // success
whismanoid 53:3d5a3d241a5e 865 return 1;
whismanoid 53:3d5a3d241a5e 866 }
whismanoid 53:3d5a3d241a5e 867
whismanoid 53:3d5a3d241a5e 868 //----------------------------------------
whismanoid 53:3d5a3d241a5e 869 // Return the size of a MAX11043 register
whismanoid 53:3d5a3d241a5e 870 //
whismanoid 53:3d5a3d241a5e 871 // @return 8 for 8-bit, 16 for 16-bit, 24 for 24-bit, else 0 for undefined register size
whismanoid 53:3d5a3d241a5e 872 uint8_t MAX11043::RegSize(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 873 {
whismanoid 53:3d5a3d241a5e 874
whismanoid 53:3d5a3d241a5e 875 //----------------------------------------
whismanoid 53:3d5a3d241a5e 876 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 877 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 878 switch(commandByte)
whismanoid 53:3d5a3d241a5e 879 {
whismanoid 53:3d5a3d241a5e 880 default:
whismanoid 57:1c9da8e90737 881 // case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 882 // case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 883 // case CMDOP_1111_1111_NoOperationMOSIidleHigh:
whismanoid 53:3d5a3d241a5e 884 return 0; // undefined register size
whismanoid 53:3d5a3d241a5e 885 case CMD_0001_1110_d8_Rd07_Status:
whismanoid 53:3d5a3d241a5e 886 case CMD_0101_0100_d8_Wr15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 887 case CMD_0101_0110_d8_Rd15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 888 case CMD_0110_0000_d8_Wr18_FlashMode:
whismanoid 53:3d5a3d241a5e 889 case CMD_0110_0010_d8_Rd18_FlashMode:
whismanoid 53:3d5a3d241a5e 890 return 8; // 8-bit register size
whismanoid 53:3d5a3d241a5e 891 case CMD_0010_0000_d16_Wr08_Configuration:
whismanoid 53:3d5a3d241a5e 892 case CMD_0010_0010_d16_Rd08_Configuration:
whismanoid 53:3d5a3d241a5e 893 case CMD_0010_0100_d16_Wr09_DAC:
whismanoid 53:3d5a3d241a5e 894 case CMD_0010_0110_d16_Rd09_DAC:
whismanoid 53:3d5a3d241a5e 895 case CMD_0010_1000_d16_Wr0A_DACStep:
whismanoid 53:3d5a3d241a5e 896 case CMD_0010_1010_d16_Rd0A_DACStep:
whismanoid 53:3d5a3d241a5e 897 case CMD_0010_1100_d16_Wr0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 898 case CMD_0010_1110_d16_Rd0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 899 case CMD_0011_0000_d16_Wr0C_ConfigA:
whismanoid 53:3d5a3d241a5e 900 case CMD_0011_0010_d16_Rd0C_ConfigA:
whismanoid 53:3d5a3d241a5e 901 case CMD_0011_0100_d16_Wr0D_ConfigB:
whismanoid 53:3d5a3d241a5e 902 case CMD_0011_0110_d16_Rd0D_ConfigB:
whismanoid 53:3d5a3d241a5e 903 case CMD_0011_1000_d16_Wr0E_ConfigC:
whismanoid 53:3d5a3d241a5e 904 case CMD_0011_1010_d16_Rd0E_ConfigC:
whismanoid 53:3d5a3d241a5e 905 case CMD_0011_1100_d16_Wr0F_ConfigD:
whismanoid 53:3d5a3d241a5e 906 case CMD_0011_1110_d16_Rd0F_ConfigD:
whismanoid 53:3d5a3d241a5e 907 case CMD_0100_0000_d16_Wr10_Reference:
whismanoid 53:3d5a3d241a5e 908 case CMD_0100_0010_d16_Rd10_Reference:
whismanoid 53:3d5a3d241a5e 909 case CMD_0100_0100_d16_Wr11_AGain:
whismanoid 53:3d5a3d241a5e 910 case CMD_0100_0110_d16_Rd11_AGain:
whismanoid 53:3d5a3d241a5e 911 case CMD_0100_1000_d16_Wr12_BGain:
whismanoid 53:3d5a3d241a5e 912 case CMD_0100_1010_d16_Rd12_BGain:
whismanoid 53:3d5a3d241a5e 913 case CMD_0100_1100_d16_Wr13_CGain:
whismanoid 53:3d5a3d241a5e 914 case CMD_0100_1110_d16_Rd13_CGain:
whismanoid 53:3d5a3d241a5e 915 case CMD_0101_0000_d16_Wr14_DGain:
whismanoid 53:3d5a3d241a5e 916 case CMD_0101_0010_d16_Rd14_DGain:
whismanoid 53:3d5a3d241a5e 917 case CMD_0110_0100_d16_Wr19_FlashAddr:
whismanoid 53:3d5a3d241a5e 918 case CMD_0110_0110_d16_Rd19_FlashAddr:
whismanoid 53:3d5a3d241a5e 919 case CMD_0110_1000_d16_Wr1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 920 case CMD_0110_1010_d16_Rd1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 921 case CMD_0110_1110_d16_Rd1B_FlashDataOut:
whismanoid 53:3d5a3d241a5e 922 return 16; // 16-bit register size
whismanoid 59:47538bcf6cda 923 case CMD_0000_0010_d16o8_Rd00_ADCa:
whismanoid 59:47538bcf6cda 924 case CMD_0000_0110_d16o8_Rd01_ADCb:
whismanoid 59:47538bcf6cda 925 case CMD_0000_1010_d16o8_Rd02_ADCc:
whismanoid 59:47538bcf6cda 926 case CMD_0000_1110_d16o8_Rd03_ADCd:
whismanoid 59:47538bcf6cda 927 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 928 {
whismanoid 59:47538bcf6cda 929 // %SW 0x02 (0 0 0) -- for 24-bit read
whismanoid 59:47538bcf6cda 930 return 24; // 24-bit register size
whismanoid 59:47538bcf6cda 931 }
whismanoid 59:47538bcf6cda 932 // %SW 0x02 (0 0) -- for 16-bit read
whismanoid 59:47538bcf6cda 933 //
whismanoid 59:47538bcf6cda 934 return 16; // 16-bit register size
whismanoid 63:8f39d21d6157 935 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab:
whismanoid 63:8f39d21d6157 936 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd:
whismanoid 59:47538bcf6cda 937 //
whismanoid 59:47538bcf6cda 938 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 939 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 940 {
whismanoid 59:47538bcf6cda 941 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 942 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 943 return 48; // 48-bit register size: 2*(24)
whismanoid 59:47538bcf6cda 944 }
whismanoid 59:47538bcf6cda 945 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 946 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 947 //
whismanoid 59:47538bcf6cda 948 return 32; // 32-bit register size: 2*(16)
whismanoid 63:8f39d21d6157 949 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd:
whismanoid 59:47538bcf6cda 950 //
whismanoid 59:47538bcf6cda 951 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 952 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 953 {
whismanoid 59:47538bcf6cda 954 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 955 return 96; // 96-bit register size: 4*(24)
whismanoid 59:47538bcf6cda 956 }
whismanoid 59:47538bcf6cda 957 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 958 //
whismanoid 59:47538bcf6cda 959 return 64; // 64-bit register size: 4*(16)
whismanoid 53:3d5a3d241a5e 960 case CMD_0101_1000_d32_Wr16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 961 case CMD_0101_1010_d32_Rd16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 962 case CMD_0101_1100_d32_Wr17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 963 case CMD_0101_1110_d32_Rd17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 964 return 32; // 32-bit register size
whismanoid 53:3d5a3d241a5e 965 }
whismanoid 53:3d5a3d241a5e 966 }
whismanoid 53:3d5a3d241a5e 967
whismanoid 53:3d5a3d241a5e 968 //----------------------------------------
whismanoid 57:1c9da8e90737 969 // Decode operation from commandByte
whismanoid 57:1c9da8e90737 970 //
whismanoid 57:1c9da8e90737 971 // @return operation such as idle, read register, write register, etc.
whismanoid 57:1c9da8e90737 972 MAX11043::MAX11043_CMDOP_enum_t MAX11043::DecodeCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 57:1c9da8e90737 973 {
whismanoid 57:1c9da8e90737 974
whismanoid 57:1c9da8e90737 975 //----------------------------------------
whismanoid 57:1c9da8e90737 976 // decode operation from command byte
whismanoid 57:1c9da8e90737 977 switch (commandByte & 0x83)
whismanoid 57:1c9da8e90737 978 {
whismanoid 57:1c9da8e90737 979 case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 980 return CMDOP_0aaa_aa10_ReadRegister;
whismanoid 57:1c9da8e90737 981 case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 982 return CMDOP_0aaa_aa00_WriteRegister;
whismanoid 57:1c9da8e90737 983 default:
whismanoid 57:1c9da8e90737 984 return CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 57:1c9da8e90737 985 }
whismanoid 57:1c9da8e90737 986 }
whismanoid 57:1c9da8e90737 987
whismanoid 57:1c9da8e90737 988 //----------------------------------------
whismanoid 53:3d5a3d241a5e 989 // Return the address field of a MAX11043 register
whismanoid 53:3d5a3d241a5e 990 //
whismanoid 53:3d5a3d241a5e 991 // @return register address field as given in datasheet
whismanoid 53:3d5a3d241a5e 992 uint8_t MAX11043::RegAddrOfCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 993 {
whismanoid 53:3d5a3d241a5e 994
whismanoid 53:3d5a3d241a5e 995 //----------------------------------------
whismanoid 53:3d5a3d241a5e 996 // extract register address value from command byte
whismanoid 57:1c9da8e90737 997 return (uint8_t)((commandByte &~ 0x83) >> 2); // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 998 }
whismanoid 53:3d5a3d241a5e 999
whismanoid 53:3d5a3d241a5e 1000 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1001 // Test whether a command byte is a register read command
whismanoid 53:3d5a3d241a5e 1002 //
whismanoid 53:3d5a3d241a5e 1003 // @return true if command byte is a register read command
whismanoid 53:3d5a3d241a5e 1004 uint8_t MAX11043::IsRegReadCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1005 {
whismanoid 53:3d5a3d241a5e 1006
whismanoid 53:3d5a3d241a5e 1007 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1008 // Test whether a command byte is a register read command
whismanoid 57:1c9da8e90737 1009 return (commandByte &~ 0x02) ? 1 : 0; // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 1010 }
whismanoid 53:3d5a3d241a5e 1011
whismanoid 53:3d5a3d241a5e 1012 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1013 // Return the name of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1014 //
whismanoid 53:3d5a3d241a5e 1015 // @return null-terminated constant C string containing register name or empty string
whismanoid 53:3d5a3d241a5e 1016 const char* MAX11043::RegName(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1017 {
whismanoid 53:3d5a3d241a5e 1018
whismanoid 53:3d5a3d241a5e 1019 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1020 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 1021 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 1022 switch(commandByte)
whismanoid 53:3d5a3d241a5e 1023 {
whismanoid 53:3d5a3d241a5e 1024 default:
whismanoid 53:3d5a3d241a5e 1025 return ""; // undefined register
whismanoid 57:1c9da8e90737 1026 // case CMDOP_0aaa_aa00_WriteRegister: return "_______";
whismanoid 57:1c9da8e90737 1027 // case CMDOP_0aaa_aa10_ReadRegister: return "_______";
whismanoid 57:1c9da8e90737 1028 // case CMDOP_1111_1111_NoOperationMOSIidleHigh: return "_______";
whismanoid 59:47538bcf6cda 1029 case CMD_0000_0010_d16o8_Rd00_ADCa: return "ADCa";
whismanoid 59:47538bcf6cda 1030 case CMD_0000_0110_d16o8_Rd01_ADCb: return "ADCb";
whismanoid 59:47538bcf6cda 1031 case CMD_0000_1010_d16o8_Rd02_ADCc: return "ADCc";
whismanoid 59:47538bcf6cda 1032 case CMD_0000_1110_d16o8_Rd03_ADCd: return "ADCd";
whismanoid 63:8f39d21d6157 1033 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab: return "ADCab";
whismanoid 63:8f39d21d6157 1034 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd: return "ADCcd";
whismanoid 63:8f39d21d6157 1035 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd: return "ADCabcd";
whismanoid 53:3d5a3d241a5e 1036 case CMD_0001_1110_d8_Rd07_Status: return "Status";
whismanoid 53:3d5a3d241a5e 1037 case CMD_0010_0000_d16_Wr08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1038 case CMD_0010_0010_d16_Rd08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1039 case CMD_0010_0100_d16_Wr09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1040 case CMD_0010_0110_d16_Rd09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1041 case CMD_0010_1000_d16_Wr0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1042 case CMD_0010_1010_d16_Rd0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1043 case CMD_0010_1100_d16_Wr0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1044 case CMD_0010_1110_d16_Rd0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1045 case CMD_0011_0000_d16_Wr0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1046 case CMD_0011_0010_d16_Rd0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1047 case CMD_0011_0100_d16_Wr0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1048 case CMD_0011_0110_d16_Rd0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1049 case CMD_0011_1000_d16_Wr0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1050 case CMD_0011_1010_d16_Rd0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1051 case CMD_0011_1100_d16_Wr0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1052 case CMD_0011_1110_d16_Rd0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1053 case CMD_0100_0000_d16_Wr10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1054 case CMD_0100_0010_d16_Rd10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1055 case CMD_0100_0100_d16_Wr11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1056 case CMD_0100_0110_d16_Rd11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1057 case CMD_0100_1000_d16_Wr12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1058 case CMD_0100_1010_d16_Rd12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1059 case CMD_0100_1100_d16_Wr13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1060 case CMD_0100_1110_d16_Rd13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1061 case CMD_0101_0000_d16_Wr14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1062 case CMD_0101_0010_d16_Rd14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1063 case CMD_0101_0100_d8_Wr15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1064 case CMD_0101_0110_d8_Rd15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1065 case CMD_0101_1000_d32_Wr16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1066 case CMD_0101_1010_d32_Rd16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1067 case CMD_0101_1100_d32_Wr17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1068 case CMD_0101_1110_d32_Rd17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1069 case CMD_0110_0000_d8_Wr18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1070 case CMD_0110_0010_d8_Rd18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1071 case CMD_0110_0100_d16_Wr19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1072 case CMD_0110_0110_d16_Rd19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1073 case CMD_0110_1000_d16_Wr1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1074 case CMD_0110_1010_d16_Rd1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1075 case CMD_0110_1110_d16_Rd1B_FlashDataOut: return "FlashDataOut";
whismanoid 53:3d5a3d241a5e 1076 }
whismanoid 53:3d5a3d241a5e 1077 }
whismanoid 53:3d5a3d241a5e 1078
whismanoid 59:47538bcf6cda 1079 //----------------------------------------
whismanoid 64:a667cfd83492 1080 // Menu item '$' -> adca, adcb, adcc, adcd
whismanoid 64:a667cfd83492 1081 // Read ADCabcd
whismanoid 64:a667cfd83492 1082 //
whismanoid 64:a667cfd83492 1083 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1084 uint8_t MAX11043::Read_ADCabcd(void)
whismanoid 64:a667cfd83492 1085 {
whismanoid 64:a667cfd83492 1086
whismanoid 64:a667cfd83492 1087 //----------------------------------------
whismanoid 64:a667cfd83492 1088 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1089 #warning "Not Tested Yet: MAX11043::Read_ADCabcd..."
whismanoid 64:a667cfd83492 1090
whismanoid 64:a667cfd83492 1091 //----------------------------------------
whismanoid 64:a667cfd83492 1092 // read register ADCabcd -> &adca, &adcb, &adcc, &adcd
whismanoid 64:a667cfd83492 1093 RegRead(CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd, 0);
whismanoid 64:a667cfd83492 1094
whismanoid 64:a667cfd83492 1095 //----------------------------------------
whismanoid 64:a667cfd83492 1096 // success
whismanoid 64:a667cfd83492 1097 return 1;
whismanoid 64:a667cfd83492 1098 }
whismanoid 64:a667cfd83492 1099
whismanoid 64:a667cfd83492 1100 //----------------------------------------
whismanoid 66:3fe92f6f1cfa 1101 // Menu item 'GA'
whismanoid 64:a667cfd83492 1102 // Write AGain register
whismanoid 64:a667cfd83492 1103 //
whismanoid 64:a667cfd83492 1104 // @param[in] gain 2's complement, 0x800=0.25V/V, 0x1000=0.5V/V, 0x2000=1VV/V, 0x4000=2V/V, default=0x2000
whismanoid 64:a667cfd83492 1105 //
whismanoid 64:a667cfd83492 1106 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1107 uint8_t MAX11043::Write_AGain(uint32_t gain)
whismanoid 64:a667cfd83492 1108 {
whismanoid 64:a667cfd83492 1109
whismanoid 64:a667cfd83492 1110 //----------------------------------------
whismanoid 64:a667cfd83492 1111 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1112 #warning "Not Tested Yet: MAX11043::Write_AGain..."
whismanoid 64:a667cfd83492 1113
whismanoid 64:a667cfd83492 1114 //----------------------------------------
whismanoid 64:a667cfd83492 1115 // write register
whismanoid 64:a667cfd83492 1116 RegWrite(CMD_0100_0100_d16_Wr11_AGain, gain);
whismanoid 64:a667cfd83492 1117
whismanoid 64:a667cfd83492 1118 //----------------------------------------
whismanoid 64:a667cfd83492 1119 // success
whismanoid 64:a667cfd83492 1120 return 1;
whismanoid 64:a667cfd83492 1121 }
whismanoid 64:a667cfd83492 1122
whismanoid 64:a667cfd83492 1123 //----------------------------------------
whismanoid 59:47538bcf6cda 1124 // Menu item 'XX'
whismanoid 59:47538bcf6cda 1125 //
whismanoid 59:47538bcf6cda 1126 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1127 uint8_t MAX11043::Configure_XXXXX(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1128 {
whismanoid 59:47538bcf6cda 1129
whismanoid 59:47538bcf6cda 1130 //----------------------------------------
whismanoid 59:47538bcf6cda 1131 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1132 #warning "Not Tested Yet: MAX11043::Configure_XXXXX..."
whismanoid 59:47538bcf6cda 1133
whismanoid 59:47538bcf6cda 1134 //----------------------------------------
whismanoid 59:47538bcf6cda 1135 // read register
whismanoid 59:47538bcf6cda 1136 RegRead(CMD_0000_0010_d16o8_Rd00_ADCa, &adca);
whismanoid 59:47538bcf6cda 1137
whismanoid 59:47538bcf6cda 1138 //----------------------------------------
whismanoid 59:47538bcf6cda 1139 // success
whismanoid 59:47538bcf6cda 1140 return 1;
whismanoid 59:47538bcf6cda 1141 }
whismanoid 59:47538bcf6cda 1142
whismanoid 59:47538bcf6cda 1143 //----------------------------------------
whismanoid 59:47538bcf6cda 1144 // Menu item 'XY'
whismanoid 59:47538bcf6cda 1145 //
whismanoid 59:47538bcf6cda 1146 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1147 uint8_t MAX11043::Configure_XXXXY(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1148 {
whismanoid 59:47538bcf6cda 1149
whismanoid 59:47538bcf6cda 1150 //----------------------------------------
whismanoid 59:47538bcf6cda 1151 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1152 #warning "Not Tested Yet: MAX11043::Configure_XXXXY..."
whismanoid 59:47538bcf6cda 1153
whismanoid 59:47538bcf6cda 1154 //----------------------------------------
whismanoid 59:47538bcf6cda 1155 // read register
whismanoid 59:47538bcf6cda 1156 RegRead(CMD_0001_1110_d8_Rd07_Status, &status);
whismanoid 59:47538bcf6cda 1157
whismanoid 59:47538bcf6cda 1158 //----------------------------------------
whismanoid 59:47538bcf6cda 1159 // success
whismanoid 59:47538bcf6cda 1160 return 1;
whismanoid 59:47538bcf6cda 1161 }
whismanoid 59:47538bcf6cda 1162
whismanoid 53:3d5a3d241a5e 1163
whismanoid 53:3d5a3d241a5e 1164 // End of file