Mark Underwood / Mbed OS MAX11043_Serial_Tester

Test program running on MAX32625MBED. Control through USB Serial commands using a terminal emulator such as teraterm or putty.

Dependencies:   MaximTinyTester CmdLine MAX541 USBDevice

MAX11043/MAX11043.cpp@77:3a6e2a5cd7d9, 2020-02-24 (annotated)

Committer:
whismanoid
Date:
Mon Feb 24 08:27:39 2020 +0000
Revision:
77:3a6e2a5cd7d9
Parent:
76:0397493d7baf
Child:
80:96bc693e0f79
Waiting for EOC# fall to signal EventQueue is too slow, ~25us to handle event but events happen every 9us.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 53:3d5a3d241a5e 1 // /*******************************************************************************
whismanoid 53:3d5a3d241a5e 2 // * Copyright (C) 2020 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 53:3d5a3d241a5e 3 // *
whismanoid 53:3d5a3d241a5e 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 53:3d5a3d241a5e 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 53:3d5a3d241a5e 6 // * to deal in the Software without restriction, including without limitation
whismanoid 53:3d5a3d241a5e 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 53:3d5a3d241a5e 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 53:3d5a3d241a5e 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 53:3d5a3d241a5e 10 // *
whismanoid 53:3d5a3d241a5e 11 // * The above copyright notice and this permission notice shall be included
whismanoid 53:3d5a3d241a5e 12 // * in all copies or substantial portions of the Software.
whismanoid 53:3d5a3d241a5e 13 // *
whismanoid 53:3d5a3d241a5e 14 // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid 53:3d5a3d241a5e 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 53:3d5a3d241a5e 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 53:3d5a3d241a5e 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 53:3d5a3d241a5e 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 53:3d5a3d241a5e 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 53:3d5a3d241a5e 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 53:3d5a3d241a5e 21 // *
whismanoid 53:3d5a3d241a5e 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 53:3d5a3d241a5e 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 53:3d5a3d241a5e 24 // * Products, Inc. Branding Policy.
whismanoid 53:3d5a3d241a5e 25 // *
whismanoid 53:3d5a3d241a5e 26 // * The mere transfer of this software does not imply any licenses
whismanoid 53:3d5a3d241a5e 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 53:3d5a3d241a5e 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 53:3d5a3d241a5e 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 53:3d5a3d241a5e 30 // * ownership rights.
whismanoid 53:3d5a3d241a5e 31 // *******************************************************************************
whismanoid 53:3d5a3d241a5e 32 // */
whismanoid 53:3d5a3d241a5e 33 // *********************************************************************
whismanoid 53:3d5a3d241a5e 34 // @file MAX11043.cpp
whismanoid 53:3d5a3d241a5e 35 // *********************************************************************
whismanoid 53:3d5a3d241a5e 36 // Device Driver file
whismanoid 53:3d5a3d241a5e 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid 53:3d5a3d241a5e 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 53:3d5a3d241a5e 39 // System Name = ExampleSystem
whismanoid 53:3d5a3d241a5e 40 // System Description = Device driver example
whismanoid 53:3d5a3d241a5e 41
whismanoid 53:3d5a3d241a5e 42 #include "MAX11043.h"
whismanoid 69:989e392cf635 43 //--------------------------------------------------
whismanoid 69:989e392cf635 44 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 45 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 46 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 47 #ifndef MAX11043_EOC_INTERRUPT_POLLING
whismanoid 71:62bcd01ea87f 48 #define MAX11043_EOC_INTERRUPT_POLLING 0
whismanoid 69:989e392cf635 49 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 73:879578472009 50 //--------------------------------------------------
whismanoid 76:0397493d7baf 51 // SPI is not interrupt-safe, so use EventQueue to defer execution to user context.
whismanoid 76:0397493d7baf 52 #ifndef MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 53 #define MAX11043_EOC_INTERRUPT_EVENTQUEUE 1
whismanoid 76:0397493d7baf 54 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 55 #if MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 56 #else // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 57 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 58 #if MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 59 // SPI is not interrupt-safe, so use EventQueue to defer execution to user context.
whismanoid 76:0397493d7baf 60 #include "mbed_events.h"
whismanoid 76:0397493d7baf 61 #define MYONEOCTHREADEVENTFLAG_ENABLE_SPI (1UL << 0)
whismanoid 76:0397493d7baf 62 EventFlags myOnEOCThread_event_flags;
whismanoid 76:0397493d7baf 63 Thread myOnEOCThread;
whismanoid 76:0397493d7baf 64 extern void myOnEOCThread_handler();
whismanoid 76:0397493d7baf 65 #else // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 66 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 67 //--------------------------------------------------
whismanoid 73:879578472009 68 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 73:879578472009 69 #ifndef MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 70 #define MAX11043_ScopeTrigger_MAX32625MBED_D5 1
whismanoid 73:879578472009 71 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 72 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 73 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 73:879578472009 74 // WIP MAX11043 interrupt EOC echo - moving DigitalOut ScopeTrigger to global scope, it compiles but there is no activity on scope
whismanoid 74:f4f969c9a7a9 75 extern DigitalInOut digitalInOut5; // declared in Test_Main_MAX11043.cpp (D5, PIN_INPUT, PullUp, 1)
whismanoid 75:0900a57f2e5d 76 const size_t byteCount_onEOCFallingEdge = 1 + (2 * 4);
whismanoid 75:0900a57f2e5d 77 const uint8_t mosiData_onEOCFallingEdge[9] = {
whismanoid 75:0900a57f2e5d 78 MAX11043::CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd,
whismanoid 75:0900a57f2e5d 79 0, 0, 0, 0, 0, 0, 0, 0
whismanoid 75:0900a57f2e5d 80 };
whismanoid 75:0900a57f2e5d 81 uint8_t misoData_onEOCFallingEdge[9];
whismanoid 73:879578472009 82 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 53:3d5a3d241a5e 83
whismanoid 53:3d5a3d241a5e 84 // Device Name = MAX11043
whismanoid 53:3d5a3d241a5e 85 // Device Description = 200ksps, Low-Power, Serial SPI 24-Bit, 4-Channel, Differential/Single-Ended Input, Simultaneous-Sampling SD ADC
whismanoid 53:3d5a3d241a5e 86 // Device DeviceBriefDescription = 24-bit 200ksps Delta-Sigma ADC
whismanoid 53:3d5a3d241a5e 87 // Device Manufacturer = Maxim Integrated
whismanoid 53:3d5a3d241a5e 88 // Device PartNumber = MAX11043ATL+
whismanoid 53:3d5a3d241a5e 89 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 53:3d5a3d241a5e 90 //
whismanoid 53:3d5a3d241a5e 91 // ADC MaxOutputDataRate = 200ksps
whismanoid 53:3d5a3d241a5e 92 // ADC NumChannels = 4
whismanoid 53:3d5a3d241a5e 93 // ADC ResolutionBits = 24
whismanoid 53:3d5a3d241a5e 94 //
whismanoid 53:3d5a3d241a5e 95 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 96 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 97 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 98 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 99 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 100 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 101 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 102 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 103 //
whismanoid 53:3d5a3d241a5e 104 // InputPin Name = CONVRUN
whismanoid 53:3d5a3d241a5e 105 // InputPin Description = CONVRUN (digital input). Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 53:3d5a3d241a5e 106 // CONVRUN is low.
whismanoid 53:3d5a3d241a5e 107 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 108 //
whismanoid 53:3d5a3d241a5e 109 // InputPin Name = SHDN
whismanoid 53:3d5a3d241a5e 110 // InputPin Description = Shutdown (digital input). Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 53:3d5a3d241a5e 111 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 112 //
whismanoid 53:3d5a3d241a5e 113 // InputPin Name = DACSTEP
whismanoid 53:3d5a3d241a5e 114 // InputPin Description = DACSTEP (digital input). DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 53:3d5a3d241a5e 115 // edge of the system clock.
whismanoid 53:3d5a3d241a5e 116 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 117 //
whismanoid 53:3d5a3d241a5e 118 // InputPin Name = UP/DWN#
whismanoid 53:3d5a3d241a5e 119 // InputPin Description = UP/DWN# (digital input). DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 53:3d5a3d241a5e 120 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 121 //
whismanoid 53:3d5a3d241a5e 122 // OutputPin Name = EOC
whismanoid 53:3d5a3d241a5e 123 // OutputPin Description = End of Conversion Output. Active-Low End-of-Conversion Indicator. EOC asserts low to indicate that new data is ready.
whismanoid 53:3d5a3d241a5e 124 // OutputPin Function = Event
whismanoid 53:3d5a3d241a5e 125 //
whismanoid 58:2fea32db466b 126 // SupplyPin Name = AVDD
whismanoid 58:2fea32db466b 127 // SupplyPin Description = Analog Power-Supply Input. Bypass each AVDD with a nominal 1uF capacitor to AGND.
whismanoid 58:2fea32db466b 128 // SupplyPin VinMax = 3.60
whismanoid 58:2fea32db466b 129 // SupplyPin VinMin = 3.00
whismanoid 58:2fea32db466b 130 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 131 //
whismanoid 58:2fea32db466b 132 // SupplyPin Name = AGND
whismanoid 58:2fea32db466b 133 // SupplyPin Description = Analog Ground. Connect all AGND inputs together.
whismanoid 58:2fea32db466b 134 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 135 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 136 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 137 //
whismanoid 58:2fea32db466b 138 // SupplyPin Name = DGND
whismanoid 58:2fea32db466b 139 // SupplyPin Description = Digital Ground. Connect all DGND inputs together.
whismanoid 58:2fea32db466b 140 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 141 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 142 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 143 //
whismanoid 58:2fea32db466b 144 // SupplyPin Name = DVDD
whismanoid 58:2fea32db466b 145 // SupplyPin Description = Digital Power-Supply Input. Bypass each DVDD with a nominal 1uF capacitor to DGND.
whismanoid 58:2fea32db466b 146 // SupplyPin VinMax = 3.60 (*TODO PENDING VERIFICATION*)
whismanoid 58:2fea32db466b 147 // SupplyPin VinMin = 3.00 (*TODO PENDING VERIFICATION*)
whismanoid 58:2fea32db466b 148 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 149 //
whismanoid 58:2fea32db466b 150 // SupplyPin Name = DVREG
whismanoid 58:2fea32db466b 151 // SupplyPin Description = Regulated Digital Core Supply (from internal +2.5V regulator). Bypass DVREG to DGND with a 10uF capacitor.
whismanoid 58:2fea32db466b 152 // SupplyPin VinMax = 2.50
whismanoid 58:2fea32db466b 153 // SupplyPin VinMin = 2.50
whismanoid 58:2fea32db466b 154 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 155 //
whismanoid 53:3d5a3d241a5e 156
whismanoid 53:3d5a3d241a5e 157 // CODE GENERATOR: class constructor definition
whismanoid 53:3d5a3d241a5e 158 MAX11043::MAX11043(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 53:3d5a3d241a5e 159 // CODE GENERATOR: class constructor definition gpio InputPin pins
whismanoid 53:3d5a3d241a5e 160 DigitalOut &CONVRUN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 161 DigitalOut &SHDN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 162 DigitalOut &DACSTEP_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 163 DigitalOut &UP_slash_DWNb_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 164 // CODE GENERATOR: class constructor definition gpio OutputPin pins
whismanoid 69:989e392cf635 165 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 166 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 167 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 168 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 169 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 53:3d5a3d241a5e 170 DigitalIn &EOC_pin, // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 171 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 172 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 173 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 69:989e392cf635 174 InterruptIn &EOC_pin, // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 175 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 176 // CODE GENERATOR: class constructor definition ic_variant
whismanoid 53:3d5a3d241a5e 177 MAX11043_ic_t ic_variant)
whismanoid 53:3d5a3d241a5e 178 // CODE GENERATOR: class constructor initializer list
whismanoid 53:3d5a3d241a5e 179 : m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid 53:3d5a3d241a5e 180 // CODE GENERATOR: class constructor initializer list gpio InputPin pins
whismanoid 53:3d5a3d241a5e 181 m_CONVRUN_pin(CONVRUN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 182 m_SHDN_pin(SHDN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 183 m_DACSTEP_pin(DACSTEP_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 184 m_UP_slash_DWNb_pin(UP_slash_DWNb_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 185 // CODE GENERATOR: class constructor initializer list gpio OutputPin pins
whismanoid 69:989e392cf635 186 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 187 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 188 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 189 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 53:3d5a3d241a5e 190 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 191 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 192 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 70:f44a577c9e59 193 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 194 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 195 // CODE GENERATOR: class constructor initializer list ic_variant
whismanoid 53:3d5a3d241a5e 196 m_ic_variant(ic_variant)
whismanoid 53:3d5a3d241a5e 197 {
whismanoid 53:3d5a3d241a5e 198 // CODE GENERATOR: class constructor definition SPI interface initialization
whismanoid 53:3d5a3d241a5e 199 //
whismanoid 53:3d5a3d241a5e 200 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 201 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 202 m_SPI_cs_state = 1;
whismanoid 67:5b8a495dda1c 203 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 204 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 205 }
whismanoid 53:3d5a3d241a5e 206
whismanoid 53:3d5a3d241a5e 207 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 208 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 209 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 210 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 211 m_SPI_dataMode = 0; //SPI_MODE0; // CPOL=0,CPHA=0: Rising Edge stable; SCLK idle Low
whismanoid 53:3d5a3d241a5e 212 m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid 53:3d5a3d241a5e 213
whismanoid 53:3d5a3d241a5e 214 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 215 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 216 //#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid 53:3d5a3d241a5e 217 //#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid 53:3d5a3d241a5e 218 //#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid 53:3d5a3d241a5e 219 //#define SPI_SCLK_Hz 6000000 // 6MHz
whismanoid 53:3d5a3d241a5e 220 //#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid 53:3d5a3d241a5e 221 //#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid 53:3d5a3d241a5e 222 //#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid 61:b4f3051578ef 223 m_SPI_SCLK_Hz = 24000000; // platform limit 24MHz; MAX11043 limit is 40MHz
whismanoid 53:3d5a3d241a5e 224 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 225
whismanoid 53:3d5a3d241a5e 226 //
whismanoid 53:3d5a3d241a5e 227 // CODE GENERATOR: class constructor definition gpio InputPin (Input to device) initialization
whismanoid 53:3d5a3d241a5e 228 //
whismanoid 53:3d5a3d241a5e 229 // CONVRUN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 230 m_CONVRUN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 231 //
whismanoid 53:3d5a3d241a5e 232 // SHDN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 233 m_SHDN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 234 //
whismanoid 53:3d5a3d241a5e 235 // DACSTEP Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 236 m_DACSTEP_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 237 //
whismanoid 53:3d5a3d241a5e 238 // UP_slash_DWNb Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 239 m_UP_slash_DWNb_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 240 //
whismanoid 53:3d5a3d241a5e 241 // CODE GENERATOR: class constructor definition gpio OutputPin (Output from MAX11043 device) initialization
whismanoid 53:3d5a3d241a5e 242 //
whismanoid 53:3d5a3d241a5e 243 // EOC Event Output from device
whismanoid 69:989e392cf635 244 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 76:0397493d7baf 245 #if MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 246 // SPI is not interrupt-safe, so use EventQueue to defer execution to user context.
whismanoid 76:0397493d7baf 247 myOnEOCThread.start(myOnEOCThread_handler);
whismanoid 76:0397493d7baf 248 #else // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 249 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 250 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 251 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 252 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 253 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 254 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 255 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 256 // TODO: onEOCFallingEdge: interrupt handler requires global object extern MAX11043 g_MAX11043_device
whismanoid 71:62bcd01ea87f 257 // InterruptIn interruptEOC(EOC_pin); // InterruptIn constructor requires PinName, not DigitalIn -- Error: No instance of constructor "mbed::InterruptIn::InterruptIn" matches the argument list in "MAX11043/MAX11043.cpp", Line: 187, Col: 31
whismanoid 69:989e392cf635 258 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 74:f4f969c9a7a9 259 digitalInOut5.output(); // ScopeTrigger
whismanoid 70:f44a577c9e59 260 extern void onEOCFallingEdge(void);
whismanoid 71:62bcd01ea87f 261 // interruptEOC.fall(&onEOCFallingEdge);
whismanoid 71:62bcd01ea87f 262 EOC_pin.fall(&onEOCFallingEdge);
whismanoid 69:989e392cf635 263 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 76:0397493d7baf 264 }
whismanoid 69:989e392cf635 265
whismanoid 76:0397493d7baf 266 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 76:0397493d7baf 267 // SPI is not interrupt-safe, so use EventQueue to defer execution to user context.
whismanoid 77:3a6e2a5cd7d9 268 // Waiting for EOC# fall to signal EventQueue is too slow, ~25us to handle event but events happen every 9us.
whismanoid 76:0397493d7baf 269 #if MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 270 void myOnEOCThread_handler()
whismanoid 76:0397493d7baf 271 {
whismanoid 76:0397493d7baf 272 while (true) {
whismanoid 76:0397493d7baf 273 //signal_wait(int32_t signals, uint32_t millisec=osWaitForever)
whismanoid 76:0397493d7baf 274 //flags_read = myOnEOCThread_event_flags.wait_any(MYONEOCTHREADEVENTFLAG_ENABLE_SPI);
whismanoid 76:0397493d7baf 275 // myOnEOCThread_event_flags.wait_any(MYONEOCTHREADEVENTFLAG_ENABLE_SPI, osWaitForever, false); // clear=false: don't auto clear the flag
whismanoid 76:0397493d7baf 276 myOnEOCThread_event_flags.wait_any(MYONEOCTHREADEVENTFLAG_ENABLE_SPI, osWaitForever, true); // clear=true: auto clear the flag
whismanoid 76:0397493d7baf 277 //
whismanoid 76:0397493d7baf 278 extern MAX11043 g_MAX11043_device;
whismanoid 76:0397493d7baf 279 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 76:0397493d7baf 280 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 77:3a6e2a5cd7d9 281 digitalInOut5.write(0); // ScopeTrigger happens at 1.8us after EOC# falling edge
whismanoid 76:0397493d7baf 282 digitalInOut5.write(1); // ScopeTrigger
whismanoid 76:0397493d7baf 283 digitalInOut5.write(0); // ScopeTrigger
whismanoid 76:0397493d7baf 284 digitalInOut5.write(1); // ScopeTrigger
whismanoid 76:0397493d7baf 285 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 76:0397493d7baf 286 extern SPI spi; // declared in Test_Main_MAX11043.cpp
whismanoid 76:0397493d7baf 287 spi.write((char*)mosiData_onEOCFallingEdge, byteCount_onEOCFallingEdge, (char*)misoData_onEOCFallingEdge, byteCount_onEOCFallingEdge);
whismanoid 77:3a6e2a5cd7d9 288 // SPI timing: CS low 13.30us after EOC# falling edge
whismanoid 77:3a6e2a5cd7d9 289 // SPI timing: SCLK first 14.60us after EOC# falling edge
whismanoid 77:3a6e2a5cd7d9 290 // SPI timing: SCLK last 17.70us after EOC# falling edge
whismanoid 77:3a6e2a5cd7d9 291 // SPI timing: CS high 17.70us after EOC# falling edge
whismanoid 77:3a6e2a5cd7d9 292 //
whismanoid 76:0397493d7baf 293 // TODO1: update adca
whismanoid 76:0397493d7baf 294 //g_MAX11043_device.adca = (misoData_onEOCFallingEdge[1] << 8) | misoData_onEOCFallingEdge[2];
whismanoid 76:0397493d7baf 295 // TODO1: update adcb
whismanoid 76:0397493d7baf 296 //g_MAX11043_device.adcb = (misoData_onEOCFallingEdge[3] << 8) | misoData_onEOCFallingEdge[4];
whismanoid 76:0397493d7baf 297 // TODO1: update adcc
whismanoid 76:0397493d7baf 298 //g_MAX11043_device.adcc = (misoData_onEOCFallingEdge[5] << 8) | misoData_onEOCFallingEdge[6];
whismanoid 76:0397493d7baf 299 // TODO1: update adcd
whismanoid 76:0397493d7baf 300 //g_MAX11043_device.adcd = (misoData_onEOCFallingEdge[7] << 8) | misoData_onEOCFallingEdge[8];
whismanoid 77:3a6e2a5cd7d9 301 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 77:3a6e2a5cd7d9 302 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 77:3a6e2a5cd7d9 303 digitalInOut5.write(0); // ScopeTrigger happens at 22.5us after EOC# falling edge
whismanoid 77:3a6e2a5cd7d9 304 digitalInOut5.write(1); // ScopeTrigger
whismanoid 77:3a6e2a5cd7d9 305 digitalInOut5.write(0); // ScopeTrigger
whismanoid 77:3a6e2a5cd7d9 306 digitalInOut5.write(1); // ScopeTrigger
whismanoid 77:3a6e2a5cd7d9 307 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 76:0397493d7baf 308 }
whismanoid 53:3d5a3d241a5e 309 }
whismanoid 76:0397493d7baf 310 #else // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 311 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 53:3d5a3d241a5e 312
whismanoid 69:989e392cf635 313 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 314 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 315 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 316 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 317 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 318 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 319 // Interrupt Handler: EOC Event Output from device
whismanoid 69:989e392cf635 320 void onEOCFallingEdge(void)
whismanoid 69:989e392cf635 321 {
whismanoid 72:40feab5fd579 322 // VERIFIED: if DO NOTHING inside interrupt service routine, no crash
whismanoid 72:40feab5fd579 323 #if 1
whismanoid 72:40feab5fd579 324 // VERIFIED: GPIO PIN pulse in response to EOC# falling edge, no crash on HH, no missed pulses
whismanoid 73:879578472009 325 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 326 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 74:f4f969c9a7a9 327 digitalInOut5.write(0); // ScopeTrigger 1.8us after EOC# falling edge
whismanoid 74:f4f969c9a7a9 328 digitalInOut5.write(1); // ScopeTrigger
whismanoid 74:f4f969c9a7a9 329 digitalInOut5.write(0); // ScopeTrigger
whismanoid 74:f4f969c9a7a9 330 digitalInOut5.write(1); // ScopeTrigger
whismanoid 73:879578472009 331 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 72:40feab5fd579 332 #endif
whismanoid 76:0397493d7baf 333 #if MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 334 // SPI is not interrupt-safe, so use EventQueue to defer execution to user context.
whismanoid 76:0397493d7baf 335 myOnEOCThread_event_flags.set(MYONEOCTHREADEVENTFLAG_ENABLE_SPI);
whismanoid 76:0397493d7baf 336 #else // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 337 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 338 #if 0
whismanoid 72:40feab5fd579 339 // TODO: read 4 channels in response to EOC# falling edge
whismanoid 72:40feab5fd579 340 // WIP MAX11043 interrupt CRASH on Menu item HH CONVRUN High
whismanoid 72:40feab5fd579 341 //
whismanoid 72:40feab5fd579 342 // ++ MbedOS Error Info ++
whismanoid 72:40feab5fd579 343 // Error Status: 0x80020115 Code: 277 Module: 2
whismanoid 72:40feab5fd579 344 // Error Message: Mutex lock failed
whismanoid 72:40feab5fd579 345 // Location: 0xBA33
whismanoid 72:40feab5fd579 346 // Error Value: 0xFFFFFFFA
whismanoid 72:40feab5fd579 347 // Current Thread: main Id: 0x20002CD0 Entry: 0xBD17 StackSize: 0x1000 StackMem: 0x20001CD0 SP: 0x20027ED0
whismanoid 72:40feab5fd579 348 // For more info, visit: https://armmbed.github.io/mbedos-error/?error=0x80020115
whismanoid 72:40feab5fd579 349 // -- MbedOS Error Info --
whismanoid 69:989e392cf635 350 extern MAX11043 g_MAX11043_device;
whismanoid 75:0900a57f2e5d 351 //~ g_MAX11043_device.Read_ADCabcd();
whismanoid 74:f4f969c9a7a9 352 // read register ADCabcd -> &adca, &adcb, &adcc, &adcd
whismanoid 74:f4f969c9a7a9 353 // g_MAX11043_device.RegRead(CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd, 0);
whismanoid 75:0900a57f2e5d 354 // SPI 8+64 = 72-bit transfer
whismanoid 75:0900a57f2e5d 355 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72
whismanoid 75:0900a57f2e5d 356 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 75:0900a57f2e5d 357 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 75:0900a57f2e5d 358 // global const size_t byteCount_onEOCFallingEdge = 1 + (2 * 4);
whismanoid 75:0900a57f2e5d 359 // global const uint8_t mosiData_onEOCFallingEdge[9] = {
whismanoid 75:0900a57f2e5d 360 // global CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd,
whismanoid 75:0900a57f2e5d 361 // global 0, 0, 0, 0, 0, 0, 0, 0
whismanoid 75:0900a57f2e5d 362 // global };
whismanoid 75:0900a57f2e5d 363 // global uint8_t misoData_onEOCFallingEdge[9];
whismanoid 75:0900a57f2e5d 364 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 75:0900a57f2e5d 365 // SPIreadWriteWithLowCS(byteCount_onEOCFallingEdge, mosiData_onEOCFallingEdge, misoData_onEOCFallingEdge);
whismanoid 75:0900a57f2e5d 366 // onSPIprint() is not interrupt-safe
whismanoid 75:0900a57f2e5d 367 // unsigned int numBytesTransferred = m_spi.write((char*)mosiData, byteCount, (char*)misoData, byteCount);
whismanoid 75:0900a57f2e5d 368 // g_MAX11043_device.m_spi is inaccessible
whismanoid 75:0900a57f2e5d 369 extern SPI spi; // declared in Test_Main_MAX11043.cpp
whismanoid 75:0900a57f2e5d 370 spi.write((char*)mosiData_onEOCFallingEdge, byteCount_onEOCFallingEdge, (char*)misoData_onEOCFallingEdge, byteCount_onEOCFallingEdge);
whismanoid 75:0900a57f2e5d 371 //
whismanoid 75:0900a57f2e5d 372 // ++ MbedOS Error Info ++
whismanoid 75:0900a57f2e5d 373 // Error Status: 0x80020115 Code: 277 Module: 2
whismanoid 75:0900a57f2e5d 374 // Error Message: Mutex lock failed
whismanoid 75:0900a57f2e5d 375 // Location: 0xBABB
whismanoid 75:0900a57f2e5d 376 // Error Value: 0xFFFFFFFA
whismanoid 75:0900a57f2e5d 377 // Current Thread: main Id: 0x20002CD0 Entry: 0xBD9F StackSize: 0x1000 StackMem: 0x20001CD0 SP: 0x20027F10
whismanoid 75:0900a57f2e5d 378 // For more info, visit: https://armmbed.github.io/mbedos-error/?error=0x80020115
whismanoid 75:0900a57f2e5d 379 // -- MbedOS Error Info --
whismanoid 75:0900a57f2e5d 380 //
whismanoid 75:0900a57f2e5d 381 //if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 75:0900a57f2e5d 382 //if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 75:0900a57f2e5d 383 // TODO1: update adca
whismanoid 75:0900a57f2e5d 384 //g_MAX11043_device.adca = (misoData_onEOCFallingEdge[1] << 8) | misoData_onEOCFallingEdge[2];
whismanoid 75:0900a57f2e5d 385 // TODO1: update adcb
whismanoid 75:0900a57f2e5d 386 //g_MAX11043_device.adcb = (misoData_onEOCFallingEdge[3] << 8) | misoData_onEOCFallingEdge[4];
whismanoid 75:0900a57f2e5d 387 // TODO1: update adcc
whismanoid 75:0900a57f2e5d 388 //g_MAX11043_device.adcc = (misoData_onEOCFallingEdge[5] << 8) | misoData_onEOCFallingEdge[6];
whismanoid 75:0900a57f2e5d 389 // TODO1: update adcd
whismanoid 75:0900a57f2e5d 390 //g_MAX11043_device.adcd = (misoData_onEOCFallingEdge[7] << 8) | misoData_onEOCFallingEdge[8];
whismanoid 75:0900a57f2e5d 391 //}
whismanoid 72:40feab5fd579 392 #endif
whismanoid 76:0397493d7baf 393 #if 0 // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 75:0900a57f2e5d 394 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 75:0900a57f2e5d 395 digitalInOut5.write(0); // ScopeTrigger
whismanoid 75:0900a57f2e5d 396 digitalInOut5.write(1); // ScopeTrigger
whismanoid 75:0900a57f2e5d 397 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 69:989e392cf635 398 }
whismanoid 69:989e392cf635 399 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 400
whismanoid 53:3d5a3d241a5e 401 // CODE GENERATOR: class destructor definition
whismanoid 53:3d5a3d241a5e 402 MAX11043::~MAX11043()
whismanoid 53:3d5a3d241a5e 403 {
whismanoid 53:3d5a3d241a5e 404 // do nothing
whismanoid 53:3d5a3d241a5e 405 }
whismanoid 53:3d5a3d241a5e 406
whismanoid 53:3d5a3d241a5e 407 // CODE GENERATOR: spi_frequency setter definition
whismanoid 53:3d5a3d241a5e 408 /// set SPI SCLK frequency
whismanoid 53:3d5a3d241a5e 409 void MAX11043::spi_frequency(int spi_sclk_Hz)
whismanoid 53:3d5a3d241a5e 410 {
whismanoid 53:3d5a3d241a5e 411 m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid 53:3d5a3d241a5e 412 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 413 }
whismanoid 53:3d5a3d241a5e 414
whismanoid 53:3d5a3d241a5e 415 // CODE GENERATOR: omit global g_MAX11043_device
whismanoid 53:3d5a3d241a5e 416 // CODE GENERATOR: extern function declarations
whismanoid 53:3d5a3d241a5e 417 // CODE GENERATOR: extern function requirement MAX11043::SPIoutputCS
whismanoid 53:3d5a3d241a5e 418 // Assert SPI Chip Select
whismanoid 53:3d5a3d241a5e 419 // SPI chip-select for MAX11043
whismanoid 53:3d5a3d241a5e 420 //
whismanoid 62:8223a7253c90 421 inline void MAX11043::SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 422 {
whismanoid 53:3d5a3d241a5e 423 // CODE GENERATOR: extern function definition for function SPIoutputCS
whismanoid 53:3d5a3d241a5e 424 // CODE GENERATOR: extern function definition for standard SPI interface function SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 425 m_SPI_cs_state = isLogicHigh;
whismanoid 67:5b8a495dda1c 426 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 427 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 428 }
whismanoid 53:3d5a3d241a5e 429 }
whismanoid 53:3d5a3d241a5e 430
whismanoid 62:8223a7253c90 431 // CODE GENERATOR: extern function requirement MAX11043::SPIreadWriteWithLowCS
whismanoid 62:8223a7253c90 432 // SPI read and write arbitrary number of 8-bit bytes
whismanoid 62:8223a7253c90 433 // SPI interface to MAX11043 shift mosiData into MAX11043 DIN
whismanoid 62:8223a7253c90 434 // while simultaneously capturing miso data from MAX11043 DOUT
whismanoid 62:8223a7253c90 435 //
whismanoid 62:8223a7253c90 436 int MAX11043::SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 437 {
whismanoid 62:8223a7253c90 438 // CODE GENERATOR: extern function definition for function SPIreadWriteWithLowCS
whismanoid 63:8f39d21d6157 439 // TODO1: CODE GENERATOR: extern function definition for standard SPI interface function SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 440 //size_t byteCount = 4;
whismanoid 62:8223a7253c90 441 //static char mosiData[4];
whismanoid 62:8223a7253c90 442 //static char misoData[4];
whismanoid 62:8223a7253c90 443 //
whismanoid 62:8223a7253c90 444 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 445 //~ noInterrupts();
whismanoid 62:8223a7253c90 446 //
whismanoid 62:8223a7253c90 447 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 448 //
whismanoid 67:5b8a495dda1c 449 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 450 m_cs_pin = 0;
whismanoid 67:5b8a495dda1c 451 }
whismanoid 62:8223a7253c90 452 unsigned int numBytesTransferred = m_spi.write((char*)mosiData, byteCount, (char*)misoData, byteCount);
whismanoid 67:5b8a495dda1c 453 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 454 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 455 }
whismanoid 62:8223a7253c90 456 //
whismanoid 62:8223a7253c90 457 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 458 //
whismanoid 62:8223a7253c90 459 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 460 //~ interrupts();
whismanoid 62:8223a7253c90 461 // Optional Diagnostic function to print SPI transactions
whismanoid 62:8223a7253c90 462 if (onSPIprint)
whismanoid 62:8223a7253c90 463 {
whismanoid 62:8223a7253c90 464 onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
whismanoid 62:8223a7253c90 465 }
whismanoid 62:8223a7253c90 466 return numBytesTransferred;
whismanoid 62:8223a7253c90 467 }
whismanoid 62:8223a7253c90 468
whismanoid 53:3d5a3d241a5e 469 // TODO1: CODE GENERATOR: extern function GPIOoutputSHDN alias SHDNoutputValue
whismanoid 53:3d5a3d241a5e 470 // CODE GENERATOR: extern function requirement MAX11043::SHDNoutputValue
whismanoid 58:2fea32db466b 471 // Assert MAX11043 SHDN pin : High = Shut Down, Low = Normal Operation.
whismanoid 53:3d5a3d241a5e 472 //
whismanoid 53:3d5a3d241a5e 473 void MAX11043::SHDNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 474 {
whismanoid 53:3d5a3d241a5e 475 // CODE GENERATOR: extern function definition for function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 476 // TODO1: CODE GENERATOR: extern function definition for gpio interface function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 477 // TODO1: CODE GENERATOR: gpio pin SHDN assuming member function m_SHDN_pin
whismanoid 53:3d5a3d241a5e 478 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 479 // m_SHDN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 480 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 481 m_SHDN_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 482 }
whismanoid 52:607010f0c54e 483
whismanoid 53:3d5a3d241a5e 484 // TODO1: CODE GENERATOR: extern function GPIOoutputCONVRUN alias CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 485 // CODE GENERATOR: extern function requirement MAX11043::CONVRUNoutputValue
whismanoid 58:2fea32db466b 486 // Assert MAX11043 CONVRUN pin : High = start continuous conversions on all 4 channels, Low = Idle.
whismanoid 53:3d5a3d241a5e 487 //
whismanoid 53:3d5a3d241a5e 488 void MAX11043::CONVRUNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 489 {
whismanoid 53:3d5a3d241a5e 490 // CODE GENERATOR: extern function definition for function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 491 // TODO1: CODE GENERATOR: extern function definition for gpio interface function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 492 // TODO1: CODE GENERATOR: gpio pin CONVRUN assuming member function m_CONVRUN_pin
whismanoid 53:3d5a3d241a5e 493 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 494 // m_CONVRUN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 495 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 496 m_CONVRUN_pin = isLogicHigh;
whismanoid 69:989e392cf635 497 //--------------------------------------------------
whismanoid 69:989e392cf635 498 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 499 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 500 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 501 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 502 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 503 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 504 if (m_CONVRUN_pin)
whismanoid 69:989e392cf635 505 {
whismanoid 69:989e392cf635 506 // CONVRUN was switched high, EOC# will now begin toggling
whismanoid 69:989e392cf635 507 }
whismanoid 69:989e392cf635 508 else
whismanoid 69:989e392cf635 509 {
whismanoid 69:989e392cf635 510 // CONVRUN was switched low, so wait until EOC# returns high
whismanoid 69:989e392cf635 511 #warning "MAX11043::Read_ADCabcd() Potential infinite loop if EOC pin not connected"
whismanoid 69:989e392cf635 512 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 69:989e392cf635 513 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 514 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 515 (m_EOC_pin != 1));
whismanoid 69:989e392cf635 516 futility_countdown--)
whismanoid 69:989e392cf635 517 {
whismanoid 69:989e392cf635 518 // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 69:989e392cf635 519 }
whismanoid 69:989e392cf635 520 }
whismanoid 69:989e392cf635 521 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 522 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 523 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 524 //--------------------------------------------------
whismanoid 53:3d5a3d241a5e 525 }
whismanoid 53:3d5a3d241a5e 526
whismanoid 53:3d5a3d241a5e 527 // TODO1: CODE GENERATOR: extern function GPIOoutputDACSTEP alias DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 528 // CODE GENERATOR: extern function requirement MAX11043::DACSTEPoutputValue
whismanoid 58:2fea32db466b 529 // Assert MAX11043 DACSTEP pin : High = Active, Low = Idle.
whismanoid 53:3d5a3d241a5e 530 //
whismanoid 53:3d5a3d241a5e 531 void MAX11043::DACSTEPoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 532 {
whismanoid 53:3d5a3d241a5e 533 // CODE GENERATOR: extern function definition for function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 534 // TODO1: CODE GENERATOR: extern function definition for gpio interface function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 535 // TODO1: CODE GENERATOR: gpio pin DACSTEP assuming member function m_DACSTEP_pin
whismanoid 53:3d5a3d241a5e 536 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 537 // m_DACSTEP_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 538 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 539 m_DACSTEP_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 540 }
whismanoid 53:3d5a3d241a5e 541
whismanoid 53:3d5a3d241a5e 542 // TODO1: CODE GENERATOR: extern function GPIOoutputUP_slash_DWNb alias UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 543 // CODE GENERATOR: extern function requirement MAX11043::UP_slash_DWNboutputValue
whismanoid 58:2fea32db466b 544 // Assert MAX11043 UP_slash_DWNb pin : High = Up, Low = Down.
whismanoid 53:3d5a3d241a5e 545 //
whismanoid 53:3d5a3d241a5e 546 void MAX11043::UP_slash_DWNboutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 547 {
whismanoid 53:3d5a3d241a5e 548 // CODE GENERATOR: extern function definition for function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 549 // TODO1: CODE GENERATOR: extern function definition for gpio interface function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 550 // TODO1: CODE GENERATOR: gpio pin UP_slash_DWNb assuming member function m_UP_slash_DWNb_pin
whismanoid 53:3d5a3d241a5e 551 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 552 // m_UP_slash_DWNb_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 553 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 554 m_UP_slash_DWNb_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 555 }
whismanoid 53:3d5a3d241a5e 556
whismanoid 53:3d5a3d241a5e 557 // CODE GENERATOR: extern function requirement MAX11043::EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 558 // Wait for MAX11043 EOC pin low, indicating end of conversion.
whismanoid 53:3d5a3d241a5e 559 // Required when using any of the InternalClock modes.
whismanoid 53:3d5a3d241a5e 560 //
whismanoid 53:3d5a3d241a5e 561 void MAX11043::EOCinputWaitUntilLow()
whismanoid 53:3d5a3d241a5e 562 {
whismanoid 53:3d5a3d241a5e 563 // CODE GENERATOR: extern function definition for function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 564 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 565 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 566 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 567 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 568 // TODO1: CODE GENERATOR: gpio function WaitUntilLow
whismanoid 53:3d5a3d241a5e 569 while (m_EOC_pin != 0)
whismanoid 53:3d5a3d241a5e 570 {
whismanoid 53:3d5a3d241a5e 571 // spinlock waiting for logic low pin state
whismanoid 53:3d5a3d241a5e 572 }
whismanoid 53:3d5a3d241a5e 573 }
whismanoid 53:3d5a3d241a5e 574
whismanoid 53:3d5a3d241a5e 575 // CODE GENERATOR: extern function requirement MAX11043::EOCinputValue
whismanoid 53:3d5a3d241a5e 576 // Return the status of the MAX11043 EOC pin.
whismanoid 53:3d5a3d241a5e 577 //
whismanoid 53:3d5a3d241a5e 578 int MAX11043::EOCinputValue()
whismanoid 53:3d5a3d241a5e 579 {
whismanoid 53:3d5a3d241a5e 580 // CODE GENERATOR: extern function definition for function EOCinputValue
whismanoid 53:3d5a3d241a5e 581 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputValue
whismanoid 53:3d5a3d241a5e 582 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 583 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 584 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 585 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 586 return m_EOC_pin.read();
whismanoid 53:3d5a3d241a5e 587 }
whismanoid 53:3d5a3d241a5e 588
whismanoid 53:3d5a3d241a5e 589 // CODE GENERATOR: class member function definitions
whismanoid 53:3d5a3d241a5e 590 //----------------------------------------
whismanoid 53:3d5a3d241a5e 591 // Menu item '!'
whismanoid 53:3d5a3d241a5e 592 // Initialize device
whismanoid 53:3d5a3d241a5e 593 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 594 uint8_t MAX11043::Init(void)
whismanoid 53:3d5a3d241a5e 595 {
whismanoid 53:3d5a3d241a5e 596
whismanoid 53:3d5a3d241a5e 597 //----------------------------------------
whismanoid 59:47538bcf6cda 598 // reference voltage, in Volts
whismanoid 59:47538bcf6cda 599 VRef = 2.500;
whismanoid 59:47538bcf6cda 600
whismanoid 59:47538bcf6cda 601 //----------------------------------------
whismanoid 59:47538bcf6cda 602 // shadow of register config CMD_0010_0010_d16_Rd08_Configuration
whismanoid 59:47538bcf6cda 603 config = 0x6000;
whismanoid 59:47538bcf6cda 604
whismanoid 59:47538bcf6cda 605 //----------------------------------------
whismanoid 59:47538bcf6cda 606 // shadow of register status CMD_0001_1110_d8_Rd07_Status
whismanoid 59:47538bcf6cda 607 status = 0x00;
whismanoid 53:3d5a3d241a5e 608
whismanoid 53:3d5a3d241a5e 609 //----------------------------------------
whismanoid 59:47538bcf6cda 610 // shadow of register ADCa CMD_0000_0010_d16o8_Rd00_ADCa
whismanoid 59:47538bcf6cda 611 adca = 0x0000;
whismanoid 53:3d5a3d241a5e 612
whismanoid 53:3d5a3d241a5e 613 //----------------------------------------
whismanoid 59:47538bcf6cda 614 // shadow of register ADCb CMD_0000_0110_d16o8_Rd01_ADCb
whismanoid 59:47538bcf6cda 615 adcb = 0x0000;
whismanoid 59:47538bcf6cda 616
whismanoid 59:47538bcf6cda 617 //----------------------------------------
whismanoid 59:47538bcf6cda 618 // shadow of register ADCc CMD_0000_1010_d16o8_Rd02_ADCc
whismanoid 59:47538bcf6cda 619 adcc = 0x0000;
whismanoid 59:47538bcf6cda 620
whismanoid 59:47538bcf6cda 621 //----------------------------------------
whismanoid 59:47538bcf6cda 622 // shadow of register ADCd CMD_0000_1110_d16o8_Rd03_ADCd
whismanoid 59:47538bcf6cda 623 adcd = 0x0000;
whismanoid 53:3d5a3d241a5e 624
whismanoid 53:3d5a3d241a5e 625 //----------------------------------------
whismanoid 53:3d5a3d241a5e 626 // init (based on old EV kit GUI)
whismanoid 53:3d5a3d241a5e 627 #warning "Not Implemented Yet: MAX11043::Init init..."
whismanoid 53:3d5a3d241a5e 628 // bool bOpResult = false;
whismanoid 53:3d5a3d241a5e 629 // String FWVersionString = "00";
whismanoid 53:3d5a3d241a5e 630 // bool bDemoMode = true;
whismanoid 53:3d5a3d241a5e 631 // int scan_resolution = 0;
whismanoid 53:3d5a3d241a5e 632 // int scan_channels = 0;
whismanoid 53:3d5a3d241a5e 633 // int scan_bits = 0;
whismanoid 53:3d5a3d241a5e 634 // int sampleRateFactore = 0;
whismanoid 53:3d5a3d241a5e 635 // double sampleRate = 0;
whismanoid 53:3d5a3d241a5e 636 // unsigned long banks_requested = 0;
whismanoid 53:3d5a3d241a5e 637 // bool bScanMode = 0;
whismanoid 53:3d5a3d241a5e 638
whismanoid 53:3d5a3d241a5e 639 //----------------------------------------
whismanoid 59:47538bcf6cda 640 // Device ID Validation -- not used, no device ID register
whismanoid 53:3d5a3d241a5e 641 #warning "Not Implemented Yet: MAX11043::Init Device ID Validation..."
whismanoid 53:3d5a3d241a5e 642 // const uint32_t part_id_expect = 0x000F02;
whismanoid 53:3d5a3d241a5e 643 // uint32_t part_id_readback;
whismanoid 53:3d5a3d241a5e 644 // RegRead(xxxxxxxxxxxxCMD_r001_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xddd_PART_ID, &part_id_readback);
whismanoid 53:3d5a3d241a5e 645 // if (part_id_readback != part_id_expect) return 0;
whismanoid 53:3d5a3d241a5e 646
whismanoid 53:3d5a3d241a5e 647 //----------------------------------------
whismanoid 58:2fea32db466b 648 // Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 58:2fea32db466b 649 SHDNoutputValue(0); // SHDN Inactive
whismanoid 58:2fea32db466b 650
whismanoid 58:2fea32db466b 651 //----------------------------------------
whismanoid 58:2fea32db466b 652 // Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 58:2fea32db466b 653 // CONVRUN is low.
whismanoid 58:2fea32db466b 654 CONVRUNoutputValue(0); // CONVRUN Idle
whismanoid 58:2fea32db466b 655
whismanoid 58:2fea32db466b 656 //----------------------------------------
whismanoid 58:2fea32db466b 657 // DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 58:2fea32db466b 658 // edge of the system clock.
whismanoid 58:2fea32db466b 659 DACSTEPoutputValue(0); // DACSTEP Idle
whismanoid 58:2fea32db466b 660
whismanoid 58:2fea32db466b 661 //----------------------------------------
whismanoid 58:2fea32db466b 662 // DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 58:2fea32db466b 663 UP_slash_DWNboutputValue(0); // UP/DWN# Down
whismanoid 58:2fea32db466b 664
whismanoid 58:2fea32db466b 665 //----------------------------------------
whismanoid 53:3d5a3d241a5e 666 // success
whismanoid 53:3d5a3d241a5e 667 return 1;
whismanoid 53:3d5a3d241a5e 668 }
whismanoid 53:3d5a3d241a5e 669
whismanoid 53:3d5a3d241a5e 670 //----------------------------------------
whismanoid 53:3d5a3d241a5e 671 // Write a MAX11043 register.
whismanoid 53:3d5a3d241a5e 672 //
whismanoid 57:1c9da8e90737 673 // CMDOP_1aaa_aaaa_ReadRegister bit is cleared 0 indicating a write operation.
whismanoid 53:3d5a3d241a5e 674 //
whismanoid 53:3d5a3d241a5e 675 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 676 //
whismanoid 53:3d5a3d241a5e 677 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 678 //
whismanoid 53:3d5a3d241a5e 679 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 680 //
whismanoid 53:3d5a3d241a5e 681 // SPI MOSI = 0aaa_aaaa_dddd_dddd
whismanoid 53:3d5a3d241a5e 682 //
whismanoid 53:3d5a3d241a5e 683 // SPI MISO = xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 684 //
whismanoid 53:3d5a3d241a5e 685 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 686 //
whismanoid 53:3d5a3d241a5e 687 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 688 //
whismanoid 53:3d5a3d241a5e 689 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 690 //
whismanoid 53:3d5a3d241a5e 691 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 692 //
whismanoid 53:3d5a3d241a5e 693 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 694 //
whismanoid 53:3d5a3d241a5e 695 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 696 //
whismanoid 53:3d5a3d241a5e 697 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 698 //
whismanoid 53:3d5a3d241a5e 699 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 700 //
whismanoid 53:3d5a3d241a5e 701 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 702 uint8_t MAX11043::RegWrite(MAX11043_CMD_enum_t commandByte, uint32_t regData)
whismanoid 53:3d5a3d241a5e 703 {
whismanoid 53:3d5a3d241a5e 704
whismanoid 53:3d5a3d241a5e 705 //----------------------------------------
whismanoid 53:3d5a3d241a5e 706 // switch based on register address szie RegSize(commandByte)
whismanoid 57:1c9da8e90737 707 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 708 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 709 {
whismanoid 53:3d5a3d241a5e 710 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 711 {
whismanoid 63:8f39d21d6157 712 // SPI 8+8 = 16-bit transfer
whismanoid 63:8f39d21d6157 713 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 714 // SPI MOSI = 0aaa_aaaa_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 715 // SPI MISO = xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 716 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 717 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 718 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 719 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 720 mosiData[1] = regData;
whismanoid 63:8f39d21d6157 721 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 722 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 723 // TODO: cache CMD_0101_0100_d8_Wr15_FilterCAddress
whismanoid 63:8f39d21d6157 724 // if (commandByte == CMD_0101_0100_d8_Wr15_FilterCAddress) {
whismanoid 63:8f39d21d6157 725 // FilterCAddress = regData;
whismanoid 63:8f39d21d6157 726 // }
whismanoid 63:8f39d21d6157 727 // TODO: cache CMD_0110_0000_d8_Wr18_FlashMode
whismanoid 63:8f39d21d6157 728 // if (commandByte == CMD_0110_0000_d8_Wr18_FlashMode) {
whismanoid 63:8f39d21d6157 729 // FlashMode = regData;
whismanoid 63:8f39d21d6157 730 // }
whismanoid 53:3d5a3d241a5e 731 }
whismanoid 53:3d5a3d241a5e 732 break;
whismanoid 53:3d5a3d241a5e 733 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 734 #warning "Not Verified Yet: MAX11043::RegWrite 16-bit"
whismanoid 53:3d5a3d241a5e 735 {
whismanoid 63:8f39d21d6157 736 // SPI 8+16 = 24-bit transfer
whismanoid 63:8f39d21d6157 737 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 63:8f39d21d6157 738 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 739 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 740 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 741 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 742 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 743 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 744 mosiData[1] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 745 mosiData[2] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 746 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 747 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 748 // cache CMD_0010_0000_d16_Wr08_Configuration
whismanoid 63:8f39d21d6157 749 if (commandByte == CMD_0010_0000_d16_Wr08_Configuration) {
whismanoid 63:8f39d21d6157 750 config = regData;
whismanoid 63:8f39d21d6157 751 }
whismanoid 63:8f39d21d6157 752 // TODO: cache CMD_0010_0100_d16_Wr09_DAC
whismanoid 63:8f39d21d6157 753 // TODO: cache CMD_0010_1000_d16_Wr0A_DACStep
whismanoid 63:8f39d21d6157 754 // TODO: cache CMD_0010_1100_d16_Wr0B_DACHDACL
whismanoid 63:8f39d21d6157 755 // TODO: cache CMD_0011_0000_d16_Wr0C_ConfigA
whismanoid 63:8f39d21d6157 756 // TODO: cache CMD_0011_0100_d16_Wr0D_ConfigB
whismanoid 63:8f39d21d6157 757 // TODO: cache CMD_0011_1000_d16_Wr0E_ConfigC
whismanoid 63:8f39d21d6157 758 // TODO: cache CMD_0011_1100_d16_Wr0F_ConfigD
whismanoid 63:8f39d21d6157 759 // TODO: cache CMD_0100_0000_d16_Wr10_Reference
whismanoid 63:8f39d21d6157 760 // TODO: cache CMD_0100_0100_d16_Wr11_AGain
whismanoid 63:8f39d21d6157 761 // TODO: cache CMD_0100_1000_d16_Wr12_BGain
whismanoid 63:8f39d21d6157 762 // TODO: cache CMD_0100_1100_d16_Wr13_CGain
whismanoid 63:8f39d21d6157 763 // TODO: cache CMD_0101_0000_d16_Wr14_DGain
whismanoid 63:8f39d21d6157 764 // TODO: cache CMD_0110_0100_d16_Wr19_FlashAddr
whismanoid 63:8f39d21d6157 765 // TODO: cache CMD_0110_1000_d16_Wr1A_FlashDataIn
whismanoid 53:3d5a3d241a5e 766 }
whismanoid 53:3d5a3d241a5e 767 break;
whismanoid 63:8f39d21d6157 768 case 32: // 32-bit register size
whismanoid 63:8f39d21d6157 769 #warning "Not Verified Yet: MAX11043::RegWrite 32-bit"
whismanoid 53:3d5a3d241a5e 770 {
whismanoid 63:8f39d21d6157 771 // SPI 8+32 = 40-bit transfer
whismanoid 63:8f39d21d6157 772 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 63:8f39d21d6157 773 // SPI MOSI = 1aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 774 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 775 //
whismanoid 63:8f39d21d6157 776 size_t byteCount = 1 + (2 * 2);
whismanoid 63:8f39d21d6157 777 uint8_t mosiData[5];
whismanoid 63:8f39d21d6157 778 uint8_t misoData[5];
whismanoid 63:8f39d21d6157 779 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 780 mosiData[1] = (uint8_t)((regData >> 24) & 0xFF);
whismanoid 63:8f39d21d6157 781 mosiData[2] = (uint8_t)((regData >> 16) & 0xFF);
whismanoid 63:8f39d21d6157 782 mosiData[3] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 783 mosiData[4] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 784 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 785 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 786 // TODO: cache CMD_0101_1000_d32_Wr16_FilterCDataOut
whismanoid 63:8f39d21d6157 787 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 788 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 789 // }
whismanoid 63:8f39d21d6157 790 // TODO: cache CMD_0101_1100_d32_Wr17_FilterCDataIn
whismanoid 63:8f39d21d6157 791 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 792 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 793 // }
whismanoid 53:3d5a3d241a5e 794 }
whismanoid 53:3d5a3d241a5e 795 break;
whismanoid 53:3d5a3d241a5e 796 }
whismanoid 53:3d5a3d241a5e 797
whismanoid 53:3d5a3d241a5e 798 //----------------------------------------
whismanoid 53:3d5a3d241a5e 799 // success
whismanoid 53:3d5a3d241a5e 800 return 1;
whismanoid 53:3d5a3d241a5e 801 }
whismanoid 53:3d5a3d241a5e 802
whismanoid 53:3d5a3d241a5e 803 //----------------------------------------
whismanoid 53:3d5a3d241a5e 804 // Read an 8-bit MAX11043 register
whismanoid 53:3d5a3d241a5e 805 //
whismanoid 57:1c9da8e90737 806 // CMDOP_1aaa_aaaa_ReadRegister bit is set 1 indicating a read operation.
whismanoid 53:3d5a3d241a5e 807 //
whismanoid 53:3d5a3d241a5e 808 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 809 //
whismanoid 53:3d5a3d241a5e 810 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 811 //
whismanoid 53:3d5a3d241a5e 812 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 813 //
whismanoid 53:3d5a3d241a5e 814 // SPI MOSI = 1aaa_aaaa_0000_0000
whismanoid 53:3d5a3d241a5e 815 //
whismanoid 53:3d5a3d241a5e 816 // SPI MISO = xxxx_xxxx_dddd_dddd
whismanoid 53:3d5a3d241a5e 817 //
whismanoid 53:3d5a3d241a5e 818 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 819 //
whismanoid 53:3d5a3d241a5e 820 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 821 //
whismanoid 53:3d5a3d241a5e 822 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 823 //
whismanoid 53:3d5a3d241a5e 824 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 825 //
whismanoid 53:3d5a3d241a5e 826 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 827 //
whismanoid 53:3d5a3d241a5e 828 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 829 //
whismanoid 53:3d5a3d241a5e 830 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 831 //
whismanoid 53:3d5a3d241a5e 832 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 833 //
whismanoid 53:3d5a3d241a5e 834 //
whismanoid 53:3d5a3d241a5e 835 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 836 uint8_t MAX11043::RegRead(MAX11043_CMD_enum_t commandByte, uint32_t* ptrRegData)
whismanoid 53:3d5a3d241a5e 837 {
whismanoid 53:3d5a3d241a5e 838
whismanoid 53:3d5a3d241a5e 839 //----------------------------------------
whismanoid 53:3d5a3d241a5e 840 // switch based on register address szie RegSize(regAddress)
whismanoid 57:1c9da8e90737 841 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 842 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 843 {
whismanoid 53:3d5a3d241a5e 844 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 845 {
whismanoid 60:d1d1eaa90fb7 846 // SPI 8+8 = 16-bit transfer
whismanoid 62:8223a7253c90 847 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 848 // SPI MOSI = 1aaa_aaaa_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 849 // SPI MISO = xxxx_xxxx_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 850 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 851 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 852 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 853 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 854 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 855 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 856 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 857 if (ptrRegData) { (*ptrRegData) = misoData[1]; }
whismanoid 59:47538bcf6cda 858 if (commandByte == CMD_0001_1110_d8_Rd07_Status) {
whismanoid 59:47538bcf6cda 859 // TODO1: update status
whismanoid 63:8f39d21d6157 860 status = misoData[1];
whismanoid 59:47538bcf6cda 861 }
whismanoid 53:3d5a3d241a5e 862 }
whismanoid 53:3d5a3d241a5e 863 break;
whismanoid 53:3d5a3d241a5e 864 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 865 #warning "Not Verified Yet: MAX11043::RegRead 16-bit"
whismanoid 53:3d5a3d241a5e 866 {
whismanoid 60:d1d1eaa90fb7 867 // SPI 8+16 = 24-bit transfer
whismanoid 62:8223a7253c90 868 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 60:d1d1eaa90fb7 869 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 870 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 871 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 872 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 873 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 874 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 875 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 876 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 877 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 878 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 879 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 59:47538bcf6cda 880 if (commandByte == CMD_0010_0010_d16_Rd08_Configuration) {
whismanoid 59:47538bcf6cda 881 // TODO1: update config
whismanoid 63:8f39d21d6157 882 config = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 883 }
whismanoid 59:47538bcf6cda 884 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 885 // TODO1: update adca
whismanoid 63:8f39d21d6157 886 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 887 }
whismanoid 59:47538bcf6cda 888 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 889 // TODO1: update adcb
whismanoid 63:8f39d21d6157 890 adcb = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 891 }
whismanoid 59:47538bcf6cda 892 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 893 // TODO1: update adcc
whismanoid 63:8f39d21d6157 894 adcc = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 895 }
whismanoid 59:47538bcf6cda 896 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 897 // TODO1: update adcd
whismanoid 63:8f39d21d6157 898 adcd = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 899 }
whismanoid 53:3d5a3d241a5e 900 }
whismanoid 53:3d5a3d241a5e 901 break;
whismanoid 53:3d5a3d241a5e 902 case 24: // 24-bit register size
whismanoid 53:3d5a3d241a5e 903 {
whismanoid 60:d1d1eaa90fb7 904 // SPI 8+24 = 32-bit transfer
whismanoid 62:8223a7253c90 905 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32
whismanoid 63:8f39d21d6157 906 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 907 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 908 size_t byteCount = 1 + 3;
whismanoid 63:8f39d21d6157 909 uint8_t mosiData[4];
whismanoid 63:8f39d21d6157 910 uint8_t misoData[4];
whismanoid 63:8f39d21d6157 911 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 912 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 913 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 914 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 915 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 916 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 917 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 59:47538bcf6cda 918 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 919 // TODO1: update adca
whismanoid 63:8f39d21d6157 920 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 921 }
whismanoid 59:47538bcf6cda 922 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 923 // TODO1: update adcb
whismanoid 63:8f39d21d6157 924 adcb = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 925 }
whismanoid 59:47538bcf6cda 926 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 927 // TODO1: update adcc
whismanoid 63:8f39d21d6157 928 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 929 }
whismanoid 59:47538bcf6cda 930 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 931 // TODO1: update adcd
whismanoid 63:8f39d21d6157 932 adcd = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 933 }
whismanoid 59:47538bcf6cda 934 }
whismanoid 59:47538bcf6cda 935 break;
whismanoid 63:8f39d21d6157 936 case 32: // 32-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 937 //
whismanoid 63:8f39d21d6157 938 #warning "Not Implemented Yet: MAX11043::RegRead 32-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 939 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 940 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 941 // update adca, adcb
whismanoid 59:47538bcf6cda 942 //
whismanoid 63:8f39d21d6157 943 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 944 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 945 // update adcc, adcd
whismanoid 59:47538bcf6cda 946 //
whismanoid 59:47538bcf6cda 947 {
whismanoid 60:d1d1eaa90fb7 948 // SPI 8+32 = 40-bit transfer
whismanoid 62:8223a7253c90 949 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 60:d1d1eaa90fb7 950 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 951 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 952 size_t byteCount = 1 + (2 * 2);
whismanoid 62:8223a7253c90 953 uint8_t mosiData[5];
whismanoid 62:8223a7253c90 954 uint8_t misoData[5];
whismanoid 62:8223a7253c90 955 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 956 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 957 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 958 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 959 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 960 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 961 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 962 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 963 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 964 // TODO1: update adca
whismanoid 62:8223a7253c90 965 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 966 // TODO1: update adcb
whismanoid 62:8223a7253c90 967 adcb = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 968 }
whismanoid 63:8f39d21d6157 969 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 970 // TODO1: update adcc
whismanoid 62:8223a7253c90 971 adcc = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 972 // TODO1: update adcd
whismanoid 62:8223a7253c90 973 adcd = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 974 }
whismanoid 59:47538bcf6cda 975 }
whismanoid 59:47538bcf6cda 976 break;
whismanoid 63:8f39d21d6157 977 case 48: // 48-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 978 //
whismanoid 63:8f39d21d6157 979 #warning "Not Verified Yet: MAX11043::RegRead 48-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 980 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 981 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 982 // update adca, adcb
whismanoid 59:47538bcf6cda 983 //
whismanoid 63:8f39d21d6157 984 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 985 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 986 // update adcc, adcd
whismanoid 59:47538bcf6cda 987 //
whismanoid 59:47538bcf6cda 988 {
whismanoid 60:d1d1eaa90fb7 989 // SPI 8+48 = 56-bit transfer
whismanoid 62:8223a7253c90 990 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56
whismanoid 60:d1d1eaa90fb7 991 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 992 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 993 size_t byteCount = 1 + (3 * 2);
whismanoid 62:8223a7253c90 994 uint8_t mosiData[7];
whismanoid 62:8223a7253c90 995 uint8_t misoData[7];
whismanoid 62:8223a7253c90 996 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 997 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 998 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 999 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1000 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1001 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1002 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1003 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 1004 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 1005 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 1006 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 1007 // TODO1: update adca
whismanoid 62:8223a7253c90 1008 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 1009 // TODO1: update adcb
whismanoid 62:8223a7253c90 1010 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 1011 }
whismanoid 63:8f39d21d6157 1012 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 1013 // TODO1: update adcc
whismanoid 62:8223a7253c90 1014 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 1015 // TODO1: update adcd
whismanoid 62:8223a7253c90 1016 adcd = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 1017 }
whismanoid 59:47538bcf6cda 1018 }
whismanoid 59:47538bcf6cda 1019 break;
whismanoid 63:8f39d21d6157 1020 case 64: // 64-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 1021 //
whismanoid 63:8f39d21d6157 1022 #warning "Not Verified Yet: MAX11043::RegRead 64-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 1023 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 1024 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1025 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 1026 //
whismanoid 59:47538bcf6cda 1027 {
whismanoid 60:d1d1eaa90fb7 1028 // SPI 8+64 = 72-bit transfer
whismanoid 62:8223a7253c90 1029 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72
whismanoid 60:d1d1eaa90fb7 1030 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 1031 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 1032 size_t byteCount = 1 + (2 * 4);
whismanoid 62:8223a7253c90 1033 uint8_t mosiData[9];
whismanoid 62:8223a7253c90 1034 uint8_t misoData[9];
whismanoid 62:8223a7253c90 1035 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 1036 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1037 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1038 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1039 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1040 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1041 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1042 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1043 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1044 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 1045 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 1046 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 1047 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 1048 // TODO1: update adca
whismanoid 62:8223a7253c90 1049 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 1050 // TODO1: update adcb
whismanoid 62:8223a7253c90 1051 adcb = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 1052 // TODO1: update adcc
whismanoid 62:8223a7253c90 1053 adcc = (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 1054 // TODO1: update adcd
whismanoid 62:8223a7253c90 1055 adcd = (misoData[7] << 8) | misoData[8];
whismanoid 59:47538bcf6cda 1056 }
whismanoid 59:47538bcf6cda 1057 }
whismanoid 59:47538bcf6cda 1058 break;
whismanoid 63:8f39d21d6157 1059 case 96: // 96-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 1060 //
whismanoid 63:8f39d21d6157 1061 #warning "Not Verified Yet: MAX11043::RegRead 96-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 1062 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 1063 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1064 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 1065 //
whismanoid 59:47538bcf6cda 1066 {
whismanoid 60:d1d1eaa90fb7 1067 // SPI 8+96 = 104-bit transfer
whismanoid 62:8223a7253c90 1068 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72 ___[9]_80 __[10]_88 __[11]_96 __[12]104
whismanoid 60:d1d1eaa90fb7 1069 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 1070 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 1071 size_t byteCount = 1 + (3 * 4);
whismanoid 62:8223a7253c90 1072 uint8_t mosiData[13];
whismanoid 62:8223a7253c90 1073 uint8_t misoData[13];
whismanoid 62:8223a7253c90 1074 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 1075 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1076 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1077 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1078 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1079 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1080 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1081 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1082 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1083 mosiData[9] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1084 mosiData[10] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1085 mosiData[11] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1086 mosiData[12] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1087 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 1088 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 1089 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 1090 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 1091 // TODO1: update adca
whismanoid 62:8223a7253c90 1092 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 1093 // TODO1: update adcb
whismanoid 62:8223a7253c90 1094 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 1095 // TODO1: update adcc
whismanoid 62:8223a7253c90 1096 adcc = (misoData[7] << 16) | (misoData[8] << 8) | misoData[9];
whismanoid 59:47538bcf6cda 1097 // TODO1: update adcd
whismanoid 62:8223a7253c90 1098 adcd = (misoData[10] << 16) | (misoData[11] << 8) | misoData[12];
whismanoid 59:47538bcf6cda 1099 }
whismanoid 53:3d5a3d241a5e 1100 }
whismanoid 53:3d5a3d241a5e 1101 break;
whismanoid 53:3d5a3d241a5e 1102 }
whismanoid 53:3d5a3d241a5e 1103
whismanoid 53:3d5a3d241a5e 1104 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1105 // success
whismanoid 53:3d5a3d241a5e 1106 return 1;
whismanoid 53:3d5a3d241a5e 1107 }
whismanoid 53:3d5a3d241a5e 1108
whismanoid 53:3d5a3d241a5e 1109 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1110 // Return the size of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1111 //
whismanoid 53:3d5a3d241a5e 1112 // @return 8 for 8-bit, 16 for 16-bit, 24 for 24-bit, else 0 for undefined register size
whismanoid 53:3d5a3d241a5e 1113 uint8_t MAX11043::RegSize(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1114 {
whismanoid 53:3d5a3d241a5e 1115
whismanoid 53:3d5a3d241a5e 1116 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1117 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 1118 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 1119 switch(commandByte)
whismanoid 53:3d5a3d241a5e 1120 {
whismanoid 53:3d5a3d241a5e 1121 default:
whismanoid 57:1c9da8e90737 1122 // case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 1123 // case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 1124 // case CMDOP_1111_1111_NoOperationMOSIidleHigh:
whismanoid 53:3d5a3d241a5e 1125 return 0; // undefined register size
whismanoid 53:3d5a3d241a5e 1126 case CMD_0001_1110_d8_Rd07_Status:
whismanoid 53:3d5a3d241a5e 1127 case CMD_0101_0100_d8_Wr15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 1128 case CMD_0101_0110_d8_Rd15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 1129 case CMD_0110_0000_d8_Wr18_FlashMode:
whismanoid 53:3d5a3d241a5e 1130 case CMD_0110_0010_d8_Rd18_FlashMode:
whismanoid 53:3d5a3d241a5e 1131 return 8; // 8-bit register size
whismanoid 53:3d5a3d241a5e 1132 case CMD_0010_0000_d16_Wr08_Configuration:
whismanoid 53:3d5a3d241a5e 1133 case CMD_0010_0010_d16_Rd08_Configuration:
whismanoid 53:3d5a3d241a5e 1134 case CMD_0010_0100_d16_Wr09_DAC:
whismanoid 53:3d5a3d241a5e 1135 case CMD_0010_0110_d16_Rd09_DAC:
whismanoid 53:3d5a3d241a5e 1136 case CMD_0010_1000_d16_Wr0A_DACStep:
whismanoid 53:3d5a3d241a5e 1137 case CMD_0010_1010_d16_Rd0A_DACStep:
whismanoid 53:3d5a3d241a5e 1138 case CMD_0010_1100_d16_Wr0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 1139 case CMD_0010_1110_d16_Rd0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 1140 case CMD_0011_0000_d16_Wr0C_ConfigA:
whismanoid 53:3d5a3d241a5e 1141 case CMD_0011_0010_d16_Rd0C_ConfigA:
whismanoid 53:3d5a3d241a5e 1142 case CMD_0011_0100_d16_Wr0D_ConfigB:
whismanoid 53:3d5a3d241a5e 1143 case CMD_0011_0110_d16_Rd0D_ConfigB:
whismanoid 53:3d5a3d241a5e 1144 case CMD_0011_1000_d16_Wr0E_ConfigC:
whismanoid 53:3d5a3d241a5e 1145 case CMD_0011_1010_d16_Rd0E_ConfigC:
whismanoid 53:3d5a3d241a5e 1146 case CMD_0011_1100_d16_Wr0F_ConfigD:
whismanoid 53:3d5a3d241a5e 1147 case CMD_0011_1110_d16_Rd0F_ConfigD:
whismanoid 53:3d5a3d241a5e 1148 case CMD_0100_0000_d16_Wr10_Reference:
whismanoid 53:3d5a3d241a5e 1149 case CMD_0100_0010_d16_Rd10_Reference:
whismanoid 53:3d5a3d241a5e 1150 case CMD_0100_0100_d16_Wr11_AGain:
whismanoid 53:3d5a3d241a5e 1151 case CMD_0100_0110_d16_Rd11_AGain:
whismanoid 53:3d5a3d241a5e 1152 case CMD_0100_1000_d16_Wr12_BGain:
whismanoid 53:3d5a3d241a5e 1153 case CMD_0100_1010_d16_Rd12_BGain:
whismanoid 53:3d5a3d241a5e 1154 case CMD_0100_1100_d16_Wr13_CGain:
whismanoid 53:3d5a3d241a5e 1155 case CMD_0100_1110_d16_Rd13_CGain:
whismanoid 53:3d5a3d241a5e 1156 case CMD_0101_0000_d16_Wr14_DGain:
whismanoid 53:3d5a3d241a5e 1157 case CMD_0101_0010_d16_Rd14_DGain:
whismanoid 53:3d5a3d241a5e 1158 case CMD_0110_0100_d16_Wr19_FlashAddr:
whismanoid 53:3d5a3d241a5e 1159 case CMD_0110_0110_d16_Rd19_FlashAddr:
whismanoid 53:3d5a3d241a5e 1160 case CMD_0110_1000_d16_Wr1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 1161 case CMD_0110_1010_d16_Rd1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 1162 case CMD_0110_1110_d16_Rd1B_FlashDataOut:
whismanoid 53:3d5a3d241a5e 1163 return 16; // 16-bit register size
whismanoid 59:47538bcf6cda 1164 case CMD_0000_0010_d16o8_Rd00_ADCa:
whismanoid 59:47538bcf6cda 1165 case CMD_0000_0110_d16o8_Rd01_ADCb:
whismanoid 59:47538bcf6cda 1166 case CMD_0000_1010_d16o8_Rd02_ADCc:
whismanoid 59:47538bcf6cda 1167 case CMD_0000_1110_d16o8_Rd03_ADCd:
whismanoid 59:47538bcf6cda 1168 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1169 {
whismanoid 59:47538bcf6cda 1170 // %SW 0x02 (0 0 0) -- for 24-bit read
whismanoid 59:47538bcf6cda 1171 return 24; // 24-bit register size
whismanoid 59:47538bcf6cda 1172 }
whismanoid 59:47538bcf6cda 1173 // %SW 0x02 (0 0) -- for 16-bit read
whismanoid 59:47538bcf6cda 1174 //
whismanoid 59:47538bcf6cda 1175 return 16; // 16-bit register size
whismanoid 63:8f39d21d6157 1176 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab:
whismanoid 63:8f39d21d6157 1177 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd:
whismanoid 59:47538bcf6cda 1178 //
whismanoid 59:47538bcf6cda 1179 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 1180 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1181 {
whismanoid 59:47538bcf6cda 1182 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 1183 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 1184 return 48; // 48-bit register size: 2*(24)
whismanoid 59:47538bcf6cda 1185 }
whismanoid 59:47538bcf6cda 1186 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 1187 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 1188 //
whismanoid 59:47538bcf6cda 1189 return 32; // 32-bit register size: 2*(16)
whismanoid 63:8f39d21d6157 1190 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd:
whismanoid 59:47538bcf6cda 1191 //
whismanoid 59:47538bcf6cda 1192 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 1193 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1194 {
whismanoid 59:47538bcf6cda 1195 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1196 return 96; // 96-bit register size: 4*(24)
whismanoid 59:47538bcf6cda 1197 }
whismanoid 59:47538bcf6cda 1198 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1199 //
whismanoid 59:47538bcf6cda 1200 return 64; // 64-bit register size: 4*(16)
whismanoid 53:3d5a3d241a5e 1201 case CMD_0101_1000_d32_Wr16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 1202 case CMD_0101_1010_d32_Rd16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 1203 case CMD_0101_1100_d32_Wr17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 1204 case CMD_0101_1110_d32_Rd17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 1205 return 32; // 32-bit register size
whismanoid 53:3d5a3d241a5e 1206 }
whismanoid 53:3d5a3d241a5e 1207 }
whismanoid 53:3d5a3d241a5e 1208
whismanoid 53:3d5a3d241a5e 1209 //----------------------------------------
whismanoid 57:1c9da8e90737 1210 // Decode operation from commandByte
whismanoid 57:1c9da8e90737 1211 //
whismanoid 57:1c9da8e90737 1212 // @return operation such as idle, read register, write register, etc.
whismanoid 57:1c9da8e90737 1213 MAX11043::MAX11043_CMDOP_enum_t MAX11043::DecodeCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 57:1c9da8e90737 1214 {
whismanoid 57:1c9da8e90737 1215
whismanoid 57:1c9da8e90737 1216 //----------------------------------------
whismanoid 57:1c9da8e90737 1217 // decode operation from command byte
whismanoid 57:1c9da8e90737 1218 switch (commandByte & 0x83)
whismanoid 57:1c9da8e90737 1219 {
whismanoid 57:1c9da8e90737 1220 case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 1221 return CMDOP_0aaa_aa10_ReadRegister;
whismanoid 57:1c9da8e90737 1222 case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 1223 return CMDOP_0aaa_aa00_WriteRegister;
whismanoid 57:1c9da8e90737 1224 default:
whismanoid 57:1c9da8e90737 1225 return CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 57:1c9da8e90737 1226 }
whismanoid 57:1c9da8e90737 1227 }
whismanoid 57:1c9da8e90737 1228
whismanoid 57:1c9da8e90737 1229 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1230 // Return the address field of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1231 //
whismanoid 53:3d5a3d241a5e 1232 // @return register address field as given in datasheet
whismanoid 53:3d5a3d241a5e 1233 uint8_t MAX11043::RegAddrOfCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1234 {
whismanoid 53:3d5a3d241a5e 1235
whismanoid 53:3d5a3d241a5e 1236 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1237 // extract register address value from command byte
whismanoid 57:1c9da8e90737 1238 return (uint8_t)((commandByte &~ 0x83) >> 2); // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 1239 }
whismanoid 53:3d5a3d241a5e 1240
whismanoid 53:3d5a3d241a5e 1241 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1242 // Test whether a command byte is a register read command
whismanoid 53:3d5a3d241a5e 1243 //
whismanoid 53:3d5a3d241a5e 1244 // @return true if command byte is a register read command
whismanoid 53:3d5a3d241a5e 1245 uint8_t MAX11043::IsRegReadCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1246 {
whismanoid 53:3d5a3d241a5e 1247
whismanoid 53:3d5a3d241a5e 1248 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1249 // Test whether a command byte is a register read command
whismanoid 57:1c9da8e90737 1250 return (commandByte &~ 0x02) ? 1 : 0; // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 1251 }
whismanoid 53:3d5a3d241a5e 1252
whismanoid 53:3d5a3d241a5e 1253 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1254 // Return the name of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1255 //
whismanoid 53:3d5a3d241a5e 1256 // @return null-terminated constant C string containing register name or empty string
whismanoid 53:3d5a3d241a5e 1257 const char* MAX11043::RegName(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1258 {
whismanoid 53:3d5a3d241a5e 1259
whismanoid 53:3d5a3d241a5e 1260 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1261 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 1262 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 1263 switch(commandByte)
whismanoid 53:3d5a3d241a5e 1264 {
whismanoid 53:3d5a3d241a5e 1265 default:
whismanoid 53:3d5a3d241a5e 1266 return ""; // undefined register
whismanoid 57:1c9da8e90737 1267 // case CMDOP_0aaa_aa00_WriteRegister: return "_______";
whismanoid 57:1c9da8e90737 1268 // case CMDOP_0aaa_aa10_ReadRegister: return "_______";
whismanoid 57:1c9da8e90737 1269 // case CMDOP_1111_1111_NoOperationMOSIidleHigh: return "_______";
whismanoid 59:47538bcf6cda 1270 case CMD_0000_0010_d16o8_Rd00_ADCa: return "ADCa";
whismanoid 59:47538bcf6cda 1271 case CMD_0000_0110_d16o8_Rd01_ADCb: return "ADCb";
whismanoid 59:47538bcf6cda 1272 case CMD_0000_1010_d16o8_Rd02_ADCc: return "ADCc";
whismanoid 59:47538bcf6cda 1273 case CMD_0000_1110_d16o8_Rd03_ADCd: return "ADCd";
whismanoid 63:8f39d21d6157 1274 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab: return "ADCab";
whismanoid 63:8f39d21d6157 1275 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd: return "ADCcd";
whismanoid 63:8f39d21d6157 1276 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd: return "ADCabcd";
whismanoid 53:3d5a3d241a5e 1277 case CMD_0001_1110_d8_Rd07_Status: return "Status";
whismanoid 53:3d5a3d241a5e 1278 case CMD_0010_0000_d16_Wr08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1279 case CMD_0010_0010_d16_Rd08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1280 case CMD_0010_0100_d16_Wr09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1281 case CMD_0010_0110_d16_Rd09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1282 case CMD_0010_1000_d16_Wr0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1283 case CMD_0010_1010_d16_Rd0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1284 case CMD_0010_1100_d16_Wr0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1285 case CMD_0010_1110_d16_Rd0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1286 case CMD_0011_0000_d16_Wr0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1287 case CMD_0011_0010_d16_Rd0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1288 case CMD_0011_0100_d16_Wr0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1289 case CMD_0011_0110_d16_Rd0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1290 case CMD_0011_1000_d16_Wr0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1291 case CMD_0011_1010_d16_Rd0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1292 case CMD_0011_1100_d16_Wr0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1293 case CMD_0011_1110_d16_Rd0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1294 case CMD_0100_0000_d16_Wr10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1295 case CMD_0100_0010_d16_Rd10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1296 case CMD_0100_0100_d16_Wr11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1297 case CMD_0100_0110_d16_Rd11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1298 case CMD_0100_1000_d16_Wr12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1299 case CMD_0100_1010_d16_Rd12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1300 case CMD_0100_1100_d16_Wr13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1301 case CMD_0100_1110_d16_Rd13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1302 case CMD_0101_0000_d16_Wr14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1303 case CMD_0101_0010_d16_Rd14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1304 case CMD_0101_0100_d8_Wr15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1305 case CMD_0101_0110_d8_Rd15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1306 case CMD_0101_1000_d32_Wr16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1307 case CMD_0101_1010_d32_Rd16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1308 case CMD_0101_1100_d32_Wr17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1309 case CMD_0101_1110_d32_Rd17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1310 case CMD_0110_0000_d8_Wr18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1311 case CMD_0110_0010_d8_Rd18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1312 case CMD_0110_0100_d16_Wr19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1313 case CMD_0110_0110_d16_Rd19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1314 case CMD_0110_1000_d16_Wr1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1315 case CMD_0110_1010_d16_Rd1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1316 case CMD_0110_1110_d16_Rd1B_FlashDataOut: return "FlashDataOut";
whismanoid 53:3d5a3d241a5e 1317 }
whismanoid 53:3d5a3d241a5e 1318 }
whismanoid 53:3d5a3d241a5e 1319
whismanoid 59:47538bcf6cda 1320 //----------------------------------------
whismanoid 64:a667cfd83492 1321 // Menu item '$' -> adca, adcb, adcc, adcd
whismanoid 64:a667cfd83492 1322 // Read ADCabcd
whismanoid 64:a667cfd83492 1323 //
whismanoid 64:a667cfd83492 1324 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1325 uint8_t MAX11043::Read_ADCabcd(void)
whismanoid 64:a667cfd83492 1326 {
whismanoid 64:a667cfd83492 1327
whismanoid 64:a667cfd83492 1328 //----------------------------------------
whismanoid 64:a667cfd83492 1329 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1330 #warning "Not Tested Yet: MAX11043::Read_ADCabcd..."
whismanoid 64:a667cfd83492 1331
whismanoid 69:989e392cf635 1332 //--------------------------------------------------
whismanoid 69:989e392cf635 1333 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 1334 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 1335 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 1336 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1337 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 1338 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 1339 // 2020-02-20 MAX11043_EOC_INTERRUPT_POLLING works on MAX32625MBED at 9us conversion rate, with 1us timing margin
whismanoid 69:989e392cf635 1340 // TODO: poll m_EOC_pin if CONVRUN is high
whismanoid 69:989e392cf635 1341 if (m_CONVRUN_pin)
whismanoid 69:989e392cf635 1342 {
whismanoid 69:989e392cf635 1343 #warning "MAX11043::Read_ADCabcd() Potential infinite loop if EOC pin not connected"
whismanoid 69:989e392cf635 1344 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 69:989e392cf635 1345 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 1346 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 1347 (m_EOC_pin != 1));
whismanoid 69:989e392cf635 1348 futility_countdown--)
whismanoid 69:989e392cf635 1349 {
whismanoid 69:989e392cf635 1350 // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 69:989e392cf635 1351 }
whismanoid 69:989e392cf635 1352 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 1353 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 1354 (m_EOC_pin != 0));
whismanoid 69:989e392cf635 1355 futility_countdown--)
whismanoid 69:989e392cf635 1356 {
whismanoid 69:989e392cf635 1357 // spinlock waiting for logic low pin state (new data is available)
whismanoid 69:989e392cf635 1358 }
whismanoid 69:989e392cf635 1359 }
whismanoid 69:989e392cf635 1360 else
whismanoid 69:989e392cf635 1361 {
whismanoid 69:989e392cf635 1362 // CONVRUN pin is being driven low, so conversion result will not change, EOC# remains high
whismanoid 69:989e392cf635 1363 }
whismanoid 69:989e392cf635 1364 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1365 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 1366 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1367 //--------------------------------------------------
whismanoid 69:989e392cf635 1368
whismanoid 64:a667cfd83492 1369 //----------------------------------------
whismanoid 64:a667cfd83492 1370 // read register ADCabcd -> &adca, &adcb, &adcc, &adcd
whismanoid 64:a667cfd83492 1371 RegRead(CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd, 0);
whismanoid 64:a667cfd83492 1372
whismanoid 64:a667cfd83492 1373 //----------------------------------------
whismanoid 64:a667cfd83492 1374 // success
whismanoid 64:a667cfd83492 1375 return 1;
whismanoid 64:a667cfd83492 1376 }
whismanoid 64:a667cfd83492 1377
whismanoid 64:a667cfd83492 1378 //----------------------------------------
whismanoid 66:3fe92f6f1cfa 1379 // Menu item 'GA'
whismanoid 64:a667cfd83492 1380 // Write AGain register
whismanoid 64:a667cfd83492 1381 //
whismanoid 64:a667cfd83492 1382 // @param[in] gain 2's complement, 0x800=0.25V/V, 0x1000=0.5V/V, 0x2000=1VV/V, 0x4000=2V/V, default=0x2000
whismanoid 64:a667cfd83492 1383 //
whismanoid 64:a667cfd83492 1384 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1385 uint8_t MAX11043::Write_AGain(uint32_t gain)
whismanoid 64:a667cfd83492 1386 {
whismanoid 64:a667cfd83492 1387
whismanoid 64:a667cfd83492 1388 //----------------------------------------
whismanoid 64:a667cfd83492 1389 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1390 #warning "Not Tested Yet: MAX11043::Write_AGain..."
whismanoid 64:a667cfd83492 1391
whismanoid 64:a667cfd83492 1392 //----------------------------------------
whismanoid 64:a667cfd83492 1393 // write register
whismanoid 64:a667cfd83492 1394 RegWrite(CMD_0100_0100_d16_Wr11_AGain, gain);
whismanoid 64:a667cfd83492 1395
whismanoid 64:a667cfd83492 1396 //----------------------------------------
whismanoid 64:a667cfd83492 1397 // success
whismanoid 64:a667cfd83492 1398 return 1;
whismanoid 64:a667cfd83492 1399 }
whismanoid 64:a667cfd83492 1400
whismanoid 64:a667cfd83492 1401 //----------------------------------------
whismanoid 59:47538bcf6cda 1402 // Menu item 'XX'
whismanoid 59:47538bcf6cda 1403 //
whismanoid 59:47538bcf6cda 1404 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1405 uint8_t MAX11043::Configure_XXXXX(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1406 {
whismanoid 59:47538bcf6cda 1407
whismanoid 59:47538bcf6cda 1408 //----------------------------------------
whismanoid 59:47538bcf6cda 1409 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1410 #warning "Not Tested Yet: MAX11043::Configure_XXXXX..."
whismanoid 59:47538bcf6cda 1411
whismanoid 59:47538bcf6cda 1412 //----------------------------------------
whismanoid 59:47538bcf6cda 1413 // read register
whismanoid 59:47538bcf6cda 1414 RegRead(CMD_0000_0010_d16o8_Rd00_ADCa, &adca);
whismanoid 59:47538bcf6cda 1415
whismanoid 59:47538bcf6cda 1416 //----------------------------------------
whismanoid 59:47538bcf6cda 1417 // success
whismanoid 59:47538bcf6cda 1418 return 1;
whismanoid 59:47538bcf6cda 1419 }
whismanoid 59:47538bcf6cda 1420
whismanoid 59:47538bcf6cda 1421 //----------------------------------------
whismanoid 59:47538bcf6cda 1422 // Menu item 'XY'
whismanoid 59:47538bcf6cda 1423 //
whismanoid 59:47538bcf6cda 1424 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1425 uint8_t MAX11043::Configure_XXXXY(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1426 {
whismanoid 59:47538bcf6cda 1427
whismanoid 59:47538bcf6cda 1428 //----------------------------------------
whismanoid 59:47538bcf6cda 1429 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1430 #warning "Not Tested Yet: MAX11043::Configure_XXXXY..."
whismanoid 59:47538bcf6cda 1431
whismanoid 59:47538bcf6cda 1432 //----------------------------------------
whismanoid 59:47538bcf6cda 1433 // read register
whismanoid 59:47538bcf6cda 1434 RegRead(CMD_0001_1110_d8_Rd07_Status, &status);
whismanoid 59:47538bcf6cda 1435
whismanoid 59:47538bcf6cda 1436 //----------------------------------------
whismanoid 59:47538bcf6cda 1437 // success
whismanoid 59:47538bcf6cda 1438 return 1;
whismanoid 59:47538bcf6cda 1439 }
whismanoid 59:47538bcf6cda 1440
whismanoid 53:3d5a3d241a5e 1441
whismanoid 53:3d5a3d241a5e 1442 // End of file