Mark Underwood / Mbed OS MAX11043_Serial_Tester

Test program running on MAX32625MBED. Control through USB Serial commands using a terminal emulator such as teraterm or putty.

Dependencies:   MaximTinyTester CmdLine MAX541 USBDevice

MAX11043/MAX11043.cpp@74:f4f969c9a7a9, 2020-02-23 (annotated)

Committer:
whismanoid
Date:
Sun Feb 23 11:38:40 2020 +0000
Revision:
74:f4f969c9a7a9
Parent:
73:879578472009
Child:
75:0900a57f2e5d
MAX11043 ScopeTrigger D5 1.8us after EOC# falling edge; WIP Read_ADCabcd on EOC

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 53:3d5a3d241a5e 1 // /*******************************************************************************
whismanoid 53:3d5a3d241a5e 2 // * Copyright (C) 2020 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 53:3d5a3d241a5e 3 // *
whismanoid 53:3d5a3d241a5e 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 53:3d5a3d241a5e 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 53:3d5a3d241a5e 6 // * to deal in the Software without restriction, including without limitation
whismanoid 53:3d5a3d241a5e 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 53:3d5a3d241a5e 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 53:3d5a3d241a5e 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 53:3d5a3d241a5e 10 // *
whismanoid 53:3d5a3d241a5e 11 // * The above copyright notice and this permission notice shall be included
whismanoid 53:3d5a3d241a5e 12 // * in all copies or substantial portions of the Software.
whismanoid 53:3d5a3d241a5e 13 // *
whismanoid 53:3d5a3d241a5e 14 // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid 53:3d5a3d241a5e 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 53:3d5a3d241a5e 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 53:3d5a3d241a5e 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 53:3d5a3d241a5e 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 53:3d5a3d241a5e 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 53:3d5a3d241a5e 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 53:3d5a3d241a5e 21 // *
whismanoid 53:3d5a3d241a5e 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 53:3d5a3d241a5e 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 53:3d5a3d241a5e 24 // * Products, Inc. Branding Policy.
whismanoid 53:3d5a3d241a5e 25 // *
whismanoid 53:3d5a3d241a5e 26 // * The mere transfer of this software does not imply any licenses
whismanoid 53:3d5a3d241a5e 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 53:3d5a3d241a5e 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 53:3d5a3d241a5e 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 53:3d5a3d241a5e 30 // * ownership rights.
whismanoid 53:3d5a3d241a5e 31 // *******************************************************************************
whismanoid 53:3d5a3d241a5e 32 // */
whismanoid 53:3d5a3d241a5e 33 // *********************************************************************
whismanoid 53:3d5a3d241a5e 34 // @file MAX11043.cpp
whismanoid 53:3d5a3d241a5e 35 // *********************************************************************
whismanoid 53:3d5a3d241a5e 36 // Device Driver file
whismanoid 53:3d5a3d241a5e 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid 53:3d5a3d241a5e 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 53:3d5a3d241a5e 39 // System Name = ExampleSystem
whismanoid 53:3d5a3d241a5e 40 // System Description = Device driver example
whismanoid 53:3d5a3d241a5e 41
whismanoid 53:3d5a3d241a5e 42 #include "MAX11043.h"
whismanoid 69:989e392cf635 43 //--------------------------------------------------
whismanoid 69:989e392cf635 44 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 45 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 46 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 47 #ifndef MAX11043_EOC_INTERRUPT_POLLING
whismanoid 71:62bcd01ea87f 48 #define MAX11043_EOC_INTERRUPT_POLLING 0
whismanoid 69:989e392cf635 49 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 73:879578472009 50 //--------------------------------------------------
whismanoid 73:879578472009 51 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 73:879578472009 52 #ifndef MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 53 #define MAX11043_ScopeTrigger_MAX32625MBED_D5 1
whismanoid 73:879578472009 54 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 55 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 56 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 73:879578472009 57 // WIP MAX11043 interrupt EOC echo - moving DigitalOut ScopeTrigger to global scope, it compiles but there is no activity on scope
whismanoid 74:f4f969c9a7a9 58 extern DigitalInOut digitalInOut5; // declared in Test_Main_MAX11043.cpp (D5, PIN_INPUT, PullUp, 1)
whismanoid 73:879578472009 59 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 53:3d5a3d241a5e 60
whismanoid 53:3d5a3d241a5e 61 // Device Name = MAX11043
whismanoid 53:3d5a3d241a5e 62 // Device Description = 200ksps, Low-Power, Serial SPI 24-Bit, 4-Channel, Differential/Single-Ended Input, Simultaneous-Sampling SD ADC
whismanoid 53:3d5a3d241a5e 63 // Device DeviceBriefDescription = 24-bit 200ksps Delta-Sigma ADC
whismanoid 53:3d5a3d241a5e 64 // Device Manufacturer = Maxim Integrated
whismanoid 53:3d5a3d241a5e 65 // Device PartNumber = MAX11043ATL+
whismanoid 53:3d5a3d241a5e 66 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 53:3d5a3d241a5e 67 //
whismanoid 53:3d5a3d241a5e 68 // ADC MaxOutputDataRate = 200ksps
whismanoid 53:3d5a3d241a5e 69 // ADC NumChannels = 4
whismanoid 53:3d5a3d241a5e 70 // ADC ResolutionBits = 24
whismanoid 53:3d5a3d241a5e 71 //
whismanoid 53:3d5a3d241a5e 72 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 73 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 74 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 75 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 76 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 77 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 78 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 79 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 80 //
whismanoid 53:3d5a3d241a5e 81 // InputPin Name = CONVRUN
whismanoid 53:3d5a3d241a5e 82 // InputPin Description = CONVRUN (digital input). Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 53:3d5a3d241a5e 83 // CONVRUN is low.
whismanoid 53:3d5a3d241a5e 84 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 85 //
whismanoid 53:3d5a3d241a5e 86 // InputPin Name = SHDN
whismanoid 53:3d5a3d241a5e 87 // InputPin Description = Shutdown (digital input). Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 53:3d5a3d241a5e 88 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 89 //
whismanoid 53:3d5a3d241a5e 90 // InputPin Name = DACSTEP
whismanoid 53:3d5a3d241a5e 91 // InputPin Description = DACSTEP (digital input). DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 53:3d5a3d241a5e 92 // edge of the system clock.
whismanoid 53:3d5a3d241a5e 93 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 94 //
whismanoid 53:3d5a3d241a5e 95 // InputPin Name = UP/DWN#
whismanoid 53:3d5a3d241a5e 96 // InputPin Description = UP/DWN# (digital input). DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 53:3d5a3d241a5e 97 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 98 //
whismanoid 53:3d5a3d241a5e 99 // OutputPin Name = EOC
whismanoid 53:3d5a3d241a5e 100 // OutputPin Description = End of Conversion Output. Active-Low End-of-Conversion Indicator. EOC asserts low to indicate that new data is ready.
whismanoid 53:3d5a3d241a5e 101 // OutputPin Function = Event
whismanoid 53:3d5a3d241a5e 102 //
whismanoid 58:2fea32db466b 103 // SupplyPin Name = AVDD
whismanoid 58:2fea32db466b 104 // SupplyPin Description = Analog Power-Supply Input. Bypass each AVDD with a nominal 1uF capacitor to AGND.
whismanoid 58:2fea32db466b 105 // SupplyPin VinMax = 3.60
whismanoid 58:2fea32db466b 106 // SupplyPin VinMin = 3.00
whismanoid 58:2fea32db466b 107 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 108 //
whismanoid 58:2fea32db466b 109 // SupplyPin Name = AGND
whismanoid 58:2fea32db466b 110 // SupplyPin Description = Analog Ground. Connect all AGND inputs together.
whismanoid 58:2fea32db466b 111 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 112 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 113 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 114 //
whismanoid 58:2fea32db466b 115 // SupplyPin Name = DGND
whismanoid 58:2fea32db466b 116 // SupplyPin Description = Digital Ground. Connect all DGND inputs together.
whismanoid 58:2fea32db466b 117 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 118 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 119 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 120 //
whismanoid 58:2fea32db466b 121 // SupplyPin Name = DVDD
whismanoid 58:2fea32db466b 122 // SupplyPin Description = Digital Power-Supply Input. Bypass each DVDD with a nominal 1uF capacitor to DGND.
whismanoid 58:2fea32db466b 123 // SupplyPin VinMax = 3.60 (*TODO PENDING VERIFICATION*)
whismanoid 58:2fea32db466b 124 // SupplyPin VinMin = 3.00 (*TODO PENDING VERIFICATION*)
whismanoid 58:2fea32db466b 125 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 126 //
whismanoid 58:2fea32db466b 127 // SupplyPin Name = DVREG
whismanoid 58:2fea32db466b 128 // SupplyPin Description = Regulated Digital Core Supply (from internal +2.5V regulator). Bypass DVREG to DGND with a 10uF capacitor.
whismanoid 58:2fea32db466b 129 // SupplyPin VinMax = 2.50
whismanoid 58:2fea32db466b 130 // SupplyPin VinMin = 2.50
whismanoid 58:2fea32db466b 131 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 132 //
whismanoid 53:3d5a3d241a5e 133
whismanoid 53:3d5a3d241a5e 134 // CODE GENERATOR: class constructor definition
whismanoid 53:3d5a3d241a5e 135 MAX11043::MAX11043(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 53:3d5a3d241a5e 136 // CODE GENERATOR: class constructor definition gpio InputPin pins
whismanoid 53:3d5a3d241a5e 137 DigitalOut &CONVRUN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 138 DigitalOut &SHDN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 139 DigitalOut &DACSTEP_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 140 DigitalOut &UP_slash_DWNb_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 141 // CODE GENERATOR: class constructor definition gpio OutputPin pins
whismanoid 69:989e392cf635 142 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 143 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 144 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 145 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 146 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 53:3d5a3d241a5e 147 DigitalIn &EOC_pin, // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 148 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 149 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 150 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 69:989e392cf635 151 InterruptIn &EOC_pin, // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 152 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 153 // CODE GENERATOR: class constructor definition ic_variant
whismanoid 53:3d5a3d241a5e 154 MAX11043_ic_t ic_variant)
whismanoid 53:3d5a3d241a5e 155 // CODE GENERATOR: class constructor initializer list
whismanoid 53:3d5a3d241a5e 156 : m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid 53:3d5a3d241a5e 157 // CODE GENERATOR: class constructor initializer list gpio InputPin pins
whismanoid 53:3d5a3d241a5e 158 m_CONVRUN_pin(CONVRUN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 159 m_SHDN_pin(SHDN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 160 m_DACSTEP_pin(DACSTEP_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 161 m_UP_slash_DWNb_pin(UP_slash_DWNb_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 162 // CODE GENERATOR: class constructor initializer list gpio OutputPin pins
whismanoid 69:989e392cf635 163 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 164 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 165 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 166 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 53:3d5a3d241a5e 167 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 168 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 169 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 70:f44a577c9e59 170 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 171 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 172 // CODE GENERATOR: class constructor initializer list ic_variant
whismanoid 53:3d5a3d241a5e 173 m_ic_variant(ic_variant)
whismanoid 53:3d5a3d241a5e 174 {
whismanoid 53:3d5a3d241a5e 175 // CODE GENERATOR: class constructor definition SPI interface initialization
whismanoid 53:3d5a3d241a5e 176 //
whismanoid 53:3d5a3d241a5e 177 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 178 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 179 m_SPI_cs_state = 1;
whismanoid 67:5b8a495dda1c 180 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 181 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 182 }
whismanoid 53:3d5a3d241a5e 183
whismanoid 53:3d5a3d241a5e 184 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 185 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 186 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 187 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 188 m_SPI_dataMode = 0; //SPI_MODE0; // CPOL=0,CPHA=0: Rising Edge stable; SCLK idle Low
whismanoid 53:3d5a3d241a5e 189 m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid 53:3d5a3d241a5e 190
whismanoid 53:3d5a3d241a5e 191 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 192 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 193 //#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid 53:3d5a3d241a5e 194 //#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid 53:3d5a3d241a5e 195 //#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid 53:3d5a3d241a5e 196 //#define SPI_SCLK_Hz 6000000 // 6MHz
whismanoid 53:3d5a3d241a5e 197 //#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid 53:3d5a3d241a5e 198 //#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid 53:3d5a3d241a5e 199 //#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid 61:b4f3051578ef 200 m_SPI_SCLK_Hz = 24000000; // platform limit 24MHz; MAX11043 limit is 40MHz
whismanoid 53:3d5a3d241a5e 201 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 202
whismanoid 53:3d5a3d241a5e 203 //
whismanoid 53:3d5a3d241a5e 204 // CODE GENERATOR: class constructor definition gpio InputPin (Input to device) initialization
whismanoid 53:3d5a3d241a5e 205 //
whismanoid 53:3d5a3d241a5e 206 // CONVRUN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 207 m_CONVRUN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 208 //
whismanoid 53:3d5a3d241a5e 209 // SHDN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 210 m_SHDN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 211 //
whismanoid 53:3d5a3d241a5e 212 // DACSTEP Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 213 m_DACSTEP_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 214 //
whismanoid 53:3d5a3d241a5e 215 // UP_slash_DWNb Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 216 m_UP_slash_DWNb_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 217 //
whismanoid 53:3d5a3d241a5e 218 // CODE GENERATOR: class constructor definition gpio OutputPin (Output from MAX11043 device) initialization
whismanoid 53:3d5a3d241a5e 219 //
whismanoid 53:3d5a3d241a5e 220 // EOC Event Output from device
whismanoid 69:989e392cf635 221 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 222 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 223 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 224 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 225 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 226 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 227 // TODO: onEOCFallingEdge: interrupt handler requires global object extern MAX11043 g_MAX11043_device
whismanoid 71:62bcd01ea87f 228 // InterruptIn interruptEOC(EOC_pin); // InterruptIn constructor requires PinName, not DigitalIn -- Error: No instance of constructor "mbed::InterruptIn::InterruptIn" matches the argument list in "MAX11043/MAX11043.cpp", Line: 187, Col: 31
whismanoid 69:989e392cf635 229 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 74:f4f969c9a7a9 230 digitalInOut5.output(); // ScopeTrigger
whismanoid 70:f44a577c9e59 231 extern void onEOCFallingEdge(void);
whismanoid 71:62bcd01ea87f 232 // interruptEOC.fall(&onEOCFallingEdge);
whismanoid 71:62bcd01ea87f 233 EOC_pin.fall(&onEOCFallingEdge);
whismanoid 69:989e392cf635 234 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 235
whismanoid 53:3d5a3d241a5e 236 }
whismanoid 53:3d5a3d241a5e 237
whismanoid 69:989e392cf635 238 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 239 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 240 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 241 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 242 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 243 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 244 // Interrupt Handler: EOC Event Output from device
whismanoid 69:989e392cf635 245 void onEOCFallingEdge(void)
whismanoid 69:989e392cf635 246 {
whismanoid 72:40feab5fd579 247 // VERIFIED: if DO NOTHING inside interrupt service routine, no crash
whismanoid 72:40feab5fd579 248 #if 1
whismanoid 72:40feab5fd579 249 // VERIFIED: GPIO PIN pulse in response to EOC# falling edge, no crash on HH, no missed pulses
whismanoid 73:879578472009 250 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 251 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 74:f4f969c9a7a9 252 digitalInOut5.write(0); // ScopeTrigger 1.8us after EOC# falling edge
whismanoid 74:f4f969c9a7a9 253 digitalInOut5.write(1); // ScopeTrigger
whismanoid 74:f4f969c9a7a9 254 digitalInOut5.write(0); // ScopeTrigger
whismanoid 74:f4f969c9a7a9 255 digitalInOut5.write(1); // ScopeTrigger
whismanoid 73:879578472009 256 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 72:40feab5fd579 257 #endif
whismanoid 72:40feab5fd579 258 #if 0
whismanoid 72:40feab5fd579 259 // TODO: read 4 channels in response to EOC# falling edge
whismanoid 72:40feab5fd579 260 // WIP MAX11043 interrupt CRASH on Menu item HH CONVRUN High
whismanoid 72:40feab5fd579 261 //
whismanoid 72:40feab5fd579 262 // ++ MbedOS Error Info ++
whismanoid 72:40feab5fd579 263 // Error Status: 0x80020115 Code: 277 Module: 2
whismanoid 72:40feab5fd579 264 // Error Message: Mutex lock failed
whismanoid 72:40feab5fd579 265 // Location: 0xBA33
whismanoid 72:40feab5fd579 266 // Error Value: 0xFFFFFFFA
whismanoid 72:40feab5fd579 267 // Current Thread: main Id: 0x20002CD0 Entry: 0xBD17 StackSize: 0x1000 StackMem: 0x20001CD0 SP: 0x20027ED0
whismanoid 72:40feab5fd579 268 // For more info, visit: https://armmbed.github.io/mbedos-error/?error=0x80020115
whismanoid 72:40feab5fd579 269 // -- MbedOS Error Info --
whismanoid 69:989e392cf635 270 extern MAX11043 g_MAX11043_device;
whismanoid 69:989e392cf635 271 g_MAX11043_device.Read_ADCabcd();
whismanoid 74:f4f969c9a7a9 272 // read register ADCabcd -> &adca, &adcb, &adcc, &adcd
whismanoid 74:f4f969c9a7a9 273 // g_MAX11043_device.RegRead(CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd, 0);
whismanoid 72:40feab5fd579 274 #endif
whismanoid 69:989e392cf635 275 }
whismanoid 69:989e392cf635 276 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 277
whismanoid 53:3d5a3d241a5e 278 // CODE GENERATOR: class destructor definition
whismanoid 53:3d5a3d241a5e 279 MAX11043::~MAX11043()
whismanoid 53:3d5a3d241a5e 280 {
whismanoid 53:3d5a3d241a5e 281 // do nothing
whismanoid 53:3d5a3d241a5e 282 }
whismanoid 53:3d5a3d241a5e 283
whismanoid 53:3d5a3d241a5e 284 // CODE GENERATOR: spi_frequency setter definition
whismanoid 53:3d5a3d241a5e 285 /// set SPI SCLK frequency
whismanoid 53:3d5a3d241a5e 286 void MAX11043::spi_frequency(int spi_sclk_Hz)
whismanoid 53:3d5a3d241a5e 287 {
whismanoid 53:3d5a3d241a5e 288 m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid 53:3d5a3d241a5e 289 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 290 }
whismanoid 53:3d5a3d241a5e 291
whismanoid 53:3d5a3d241a5e 292 // CODE GENERATOR: omit global g_MAX11043_device
whismanoid 53:3d5a3d241a5e 293 // CODE GENERATOR: extern function declarations
whismanoid 53:3d5a3d241a5e 294 // CODE GENERATOR: extern function requirement MAX11043::SPIoutputCS
whismanoid 53:3d5a3d241a5e 295 // Assert SPI Chip Select
whismanoid 53:3d5a3d241a5e 296 // SPI chip-select for MAX11043
whismanoid 53:3d5a3d241a5e 297 //
whismanoid 62:8223a7253c90 298 inline void MAX11043::SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 299 {
whismanoid 53:3d5a3d241a5e 300 // CODE GENERATOR: extern function definition for function SPIoutputCS
whismanoid 53:3d5a3d241a5e 301 // CODE GENERATOR: extern function definition for standard SPI interface function SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 302 m_SPI_cs_state = isLogicHigh;
whismanoid 67:5b8a495dda1c 303 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 304 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 305 }
whismanoid 53:3d5a3d241a5e 306 }
whismanoid 53:3d5a3d241a5e 307
whismanoid 62:8223a7253c90 308 // CODE GENERATOR: extern function requirement MAX11043::SPIreadWriteWithLowCS
whismanoid 62:8223a7253c90 309 // SPI read and write arbitrary number of 8-bit bytes
whismanoid 62:8223a7253c90 310 // SPI interface to MAX11043 shift mosiData into MAX11043 DIN
whismanoid 62:8223a7253c90 311 // while simultaneously capturing miso data from MAX11043 DOUT
whismanoid 62:8223a7253c90 312 //
whismanoid 62:8223a7253c90 313 int MAX11043::SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 314 {
whismanoid 62:8223a7253c90 315 // CODE GENERATOR: extern function definition for function SPIreadWriteWithLowCS
whismanoid 63:8f39d21d6157 316 // TODO1: CODE GENERATOR: extern function definition for standard SPI interface function SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 317 //size_t byteCount = 4;
whismanoid 62:8223a7253c90 318 //static char mosiData[4];
whismanoid 62:8223a7253c90 319 //static char misoData[4];
whismanoid 62:8223a7253c90 320 //
whismanoid 62:8223a7253c90 321 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 322 //~ noInterrupts();
whismanoid 62:8223a7253c90 323 //
whismanoid 62:8223a7253c90 324 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 325 //
whismanoid 67:5b8a495dda1c 326 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 327 m_cs_pin = 0;
whismanoid 67:5b8a495dda1c 328 }
whismanoid 62:8223a7253c90 329 unsigned int numBytesTransferred = m_spi.write((char*)mosiData, byteCount, (char*)misoData, byteCount);
whismanoid 67:5b8a495dda1c 330 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 331 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 332 }
whismanoid 62:8223a7253c90 333 //
whismanoid 62:8223a7253c90 334 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 335 //
whismanoid 62:8223a7253c90 336 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 337 //~ interrupts();
whismanoid 62:8223a7253c90 338 // Optional Diagnostic function to print SPI transactions
whismanoid 62:8223a7253c90 339 if (onSPIprint)
whismanoid 62:8223a7253c90 340 {
whismanoid 62:8223a7253c90 341 onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
whismanoid 62:8223a7253c90 342 }
whismanoid 62:8223a7253c90 343 return numBytesTransferred;
whismanoid 62:8223a7253c90 344 }
whismanoid 62:8223a7253c90 345
whismanoid 53:3d5a3d241a5e 346 // TODO1: CODE GENERATOR: extern function GPIOoutputSHDN alias SHDNoutputValue
whismanoid 53:3d5a3d241a5e 347 // CODE GENERATOR: extern function requirement MAX11043::SHDNoutputValue
whismanoid 58:2fea32db466b 348 // Assert MAX11043 SHDN pin : High = Shut Down, Low = Normal Operation.
whismanoid 53:3d5a3d241a5e 349 //
whismanoid 53:3d5a3d241a5e 350 void MAX11043::SHDNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 351 {
whismanoid 53:3d5a3d241a5e 352 // CODE GENERATOR: extern function definition for function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 353 // TODO1: CODE GENERATOR: extern function definition for gpio interface function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 354 // TODO1: CODE GENERATOR: gpio pin SHDN assuming member function m_SHDN_pin
whismanoid 53:3d5a3d241a5e 355 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 356 // m_SHDN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 357 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 358 m_SHDN_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 359 }
whismanoid 52:607010f0c54e 360
whismanoid 53:3d5a3d241a5e 361 // TODO1: CODE GENERATOR: extern function GPIOoutputCONVRUN alias CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 362 // CODE GENERATOR: extern function requirement MAX11043::CONVRUNoutputValue
whismanoid 58:2fea32db466b 363 // Assert MAX11043 CONVRUN pin : High = start continuous conversions on all 4 channels, Low = Idle.
whismanoid 53:3d5a3d241a5e 364 //
whismanoid 53:3d5a3d241a5e 365 void MAX11043::CONVRUNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 366 {
whismanoid 53:3d5a3d241a5e 367 // CODE GENERATOR: extern function definition for function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 368 // TODO1: CODE GENERATOR: extern function definition for gpio interface function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 369 // TODO1: CODE GENERATOR: gpio pin CONVRUN assuming member function m_CONVRUN_pin
whismanoid 53:3d5a3d241a5e 370 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 371 // m_CONVRUN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 372 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 373 m_CONVRUN_pin = isLogicHigh;
whismanoid 69:989e392cf635 374 //--------------------------------------------------
whismanoid 69:989e392cf635 375 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 376 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 377 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 378 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 379 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 380 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 381 if (m_CONVRUN_pin)
whismanoid 69:989e392cf635 382 {
whismanoid 69:989e392cf635 383 // CONVRUN was switched high, EOC# will now begin toggling
whismanoid 69:989e392cf635 384 }
whismanoid 69:989e392cf635 385 else
whismanoid 69:989e392cf635 386 {
whismanoid 69:989e392cf635 387 // CONVRUN was switched low, so wait until EOC# returns high
whismanoid 69:989e392cf635 388 #warning "MAX11043::Read_ADCabcd() Potential infinite loop if EOC pin not connected"
whismanoid 69:989e392cf635 389 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 69:989e392cf635 390 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 391 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 392 (m_EOC_pin != 1));
whismanoid 69:989e392cf635 393 futility_countdown--)
whismanoid 69:989e392cf635 394 {
whismanoid 69:989e392cf635 395 // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 69:989e392cf635 396 }
whismanoid 69:989e392cf635 397 }
whismanoid 69:989e392cf635 398 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 399 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 400 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 401 //--------------------------------------------------
whismanoid 53:3d5a3d241a5e 402 }
whismanoid 53:3d5a3d241a5e 403
whismanoid 53:3d5a3d241a5e 404 // TODO1: CODE GENERATOR: extern function GPIOoutputDACSTEP alias DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 405 // CODE GENERATOR: extern function requirement MAX11043::DACSTEPoutputValue
whismanoid 58:2fea32db466b 406 // Assert MAX11043 DACSTEP pin : High = Active, Low = Idle.
whismanoid 53:3d5a3d241a5e 407 //
whismanoid 53:3d5a3d241a5e 408 void MAX11043::DACSTEPoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 409 {
whismanoid 53:3d5a3d241a5e 410 // CODE GENERATOR: extern function definition for function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 411 // TODO1: CODE GENERATOR: extern function definition for gpio interface function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 412 // TODO1: CODE GENERATOR: gpio pin DACSTEP assuming member function m_DACSTEP_pin
whismanoid 53:3d5a3d241a5e 413 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 414 // m_DACSTEP_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 415 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 416 m_DACSTEP_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 417 }
whismanoid 53:3d5a3d241a5e 418
whismanoid 53:3d5a3d241a5e 419 // TODO1: CODE GENERATOR: extern function GPIOoutputUP_slash_DWNb alias UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 420 // CODE GENERATOR: extern function requirement MAX11043::UP_slash_DWNboutputValue
whismanoid 58:2fea32db466b 421 // Assert MAX11043 UP_slash_DWNb pin : High = Up, Low = Down.
whismanoid 53:3d5a3d241a5e 422 //
whismanoid 53:3d5a3d241a5e 423 void MAX11043::UP_slash_DWNboutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 424 {
whismanoid 53:3d5a3d241a5e 425 // CODE GENERATOR: extern function definition for function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 426 // TODO1: CODE GENERATOR: extern function definition for gpio interface function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 427 // TODO1: CODE GENERATOR: gpio pin UP_slash_DWNb assuming member function m_UP_slash_DWNb_pin
whismanoid 53:3d5a3d241a5e 428 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 429 // m_UP_slash_DWNb_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 430 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 431 m_UP_slash_DWNb_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 432 }
whismanoid 53:3d5a3d241a5e 433
whismanoid 53:3d5a3d241a5e 434 // CODE GENERATOR: extern function requirement MAX11043::EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 435 // Wait for MAX11043 EOC pin low, indicating end of conversion.
whismanoid 53:3d5a3d241a5e 436 // Required when using any of the InternalClock modes.
whismanoid 53:3d5a3d241a5e 437 //
whismanoid 53:3d5a3d241a5e 438 void MAX11043::EOCinputWaitUntilLow()
whismanoid 53:3d5a3d241a5e 439 {
whismanoid 53:3d5a3d241a5e 440 // CODE GENERATOR: extern function definition for function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 441 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 442 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 443 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 444 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 445 // TODO1: CODE GENERATOR: gpio function WaitUntilLow
whismanoid 53:3d5a3d241a5e 446 while (m_EOC_pin != 0)
whismanoid 53:3d5a3d241a5e 447 {
whismanoid 53:3d5a3d241a5e 448 // spinlock waiting for logic low pin state
whismanoid 53:3d5a3d241a5e 449 }
whismanoid 53:3d5a3d241a5e 450 }
whismanoid 53:3d5a3d241a5e 451
whismanoid 53:3d5a3d241a5e 452 // CODE GENERATOR: extern function requirement MAX11043::EOCinputValue
whismanoid 53:3d5a3d241a5e 453 // Return the status of the MAX11043 EOC pin.
whismanoid 53:3d5a3d241a5e 454 //
whismanoid 53:3d5a3d241a5e 455 int MAX11043::EOCinputValue()
whismanoid 53:3d5a3d241a5e 456 {
whismanoid 53:3d5a3d241a5e 457 // CODE GENERATOR: extern function definition for function EOCinputValue
whismanoid 53:3d5a3d241a5e 458 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputValue
whismanoid 53:3d5a3d241a5e 459 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 460 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 461 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 462 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 463 return m_EOC_pin.read();
whismanoid 53:3d5a3d241a5e 464 }
whismanoid 53:3d5a3d241a5e 465
whismanoid 53:3d5a3d241a5e 466 // CODE GENERATOR: class member function definitions
whismanoid 53:3d5a3d241a5e 467 //----------------------------------------
whismanoid 53:3d5a3d241a5e 468 // Menu item '!'
whismanoid 53:3d5a3d241a5e 469 // Initialize device
whismanoid 53:3d5a3d241a5e 470 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 471 uint8_t MAX11043::Init(void)
whismanoid 53:3d5a3d241a5e 472 {
whismanoid 53:3d5a3d241a5e 473
whismanoid 53:3d5a3d241a5e 474 //----------------------------------------
whismanoid 59:47538bcf6cda 475 // reference voltage, in Volts
whismanoid 59:47538bcf6cda 476 VRef = 2.500;
whismanoid 59:47538bcf6cda 477
whismanoid 59:47538bcf6cda 478 //----------------------------------------
whismanoid 59:47538bcf6cda 479 // shadow of register config CMD_0010_0010_d16_Rd08_Configuration
whismanoid 59:47538bcf6cda 480 config = 0x6000;
whismanoid 59:47538bcf6cda 481
whismanoid 59:47538bcf6cda 482 //----------------------------------------
whismanoid 59:47538bcf6cda 483 // shadow of register status CMD_0001_1110_d8_Rd07_Status
whismanoid 59:47538bcf6cda 484 status = 0x00;
whismanoid 53:3d5a3d241a5e 485
whismanoid 53:3d5a3d241a5e 486 //----------------------------------------
whismanoid 59:47538bcf6cda 487 // shadow of register ADCa CMD_0000_0010_d16o8_Rd00_ADCa
whismanoid 59:47538bcf6cda 488 adca = 0x0000;
whismanoid 53:3d5a3d241a5e 489
whismanoid 53:3d5a3d241a5e 490 //----------------------------------------
whismanoid 59:47538bcf6cda 491 // shadow of register ADCb CMD_0000_0110_d16o8_Rd01_ADCb
whismanoid 59:47538bcf6cda 492 adcb = 0x0000;
whismanoid 59:47538bcf6cda 493
whismanoid 59:47538bcf6cda 494 //----------------------------------------
whismanoid 59:47538bcf6cda 495 // shadow of register ADCc CMD_0000_1010_d16o8_Rd02_ADCc
whismanoid 59:47538bcf6cda 496 adcc = 0x0000;
whismanoid 59:47538bcf6cda 497
whismanoid 59:47538bcf6cda 498 //----------------------------------------
whismanoid 59:47538bcf6cda 499 // shadow of register ADCd CMD_0000_1110_d16o8_Rd03_ADCd
whismanoid 59:47538bcf6cda 500 adcd = 0x0000;
whismanoid 53:3d5a3d241a5e 501
whismanoid 53:3d5a3d241a5e 502 //----------------------------------------
whismanoid 53:3d5a3d241a5e 503 // init (based on old EV kit GUI)
whismanoid 53:3d5a3d241a5e 504 #warning "Not Implemented Yet: MAX11043::Init init..."
whismanoid 53:3d5a3d241a5e 505 // bool bOpResult = false;
whismanoid 53:3d5a3d241a5e 506 // String FWVersionString = "00";
whismanoid 53:3d5a3d241a5e 507 // bool bDemoMode = true;
whismanoid 53:3d5a3d241a5e 508 // int scan_resolution = 0;
whismanoid 53:3d5a3d241a5e 509 // int scan_channels = 0;
whismanoid 53:3d5a3d241a5e 510 // int scan_bits = 0;
whismanoid 53:3d5a3d241a5e 511 // int sampleRateFactore = 0;
whismanoid 53:3d5a3d241a5e 512 // double sampleRate = 0;
whismanoid 53:3d5a3d241a5e 513 // unsigned long banks_requested = 0;
whismanoid 53:3d5a3d241a5e 514 // bool bScanMode = 0;
whismanoid 53:3d5a3d241a5e 515
whismanoid 53:3d5a3d241a5e 516 //----------------------------------------
whismanoid 59:47538bcf6cda 517 // Device ID Validation -- not used, no device ID register
whismanoid 53:3d5a3d241a5e 518 #warning "Not Implemented Yet: MAX11043::Init Device ID Validation..."
whismanoid 53:3d5a3d241a5e 519 // const uint32_t part_id_expect = 0x000F02;
whismanoid 53:3d5a3d241a5e 520 // uint32_t part_id_readback;
whismanoid 53:3d5a3d241a5e 521 // RegRead(xxxxxxxxxxxxCMD_r001_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xddd_PART_ID, &part_id_readback);
whismanoid 53:3d5a3d241a5e 522 // if (part_id_readback != part_id_expect) return 0;
whismanoid 53:3d5a3d241a5e 523
whismanoid 53:3d5a3d241a5e 524 //----------------------------------------
whismanoid 58:2fea32db466b 525 // Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 58:2fea32db466b 526 SHDNoutputValue(0); // SHDN Inactive
whismanoid 58:2fea32db466b 527
whismanoid 58:2fea32db466b 528 //----------------------------------------
whismanoid 58:2fea32db466b 529 // Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 58:2fea32db466b 530 // CONVRUN is low.
whismanoid 58:2fea32db466b 531 CONVRUNoutputValue(0); // CONVRUN Idle
whismanoid 58:2fea32db466b 532
whismanoid 58:2fea32db466b 533 //----------------------------------------
whismanoid 58:2fea32db466b 534 // DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 58:2fea32db466b 535 // edge of the system clock.
whismanoid 58:2fea32db466b 536 DACSTEPoutputValue(0); // DACSTEP Idle
whismanoid 58:2fea32db466b 537
whismanoid 58:2fea32db466b 538 //----------------------------------------
whismanoid 58:2fea32db466b 539 // DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 58:2fea32db466b 540 UP_slash_DWNboutputValue(0); // UP/DWN# Down
whismanoid 58:2fea32db466b 541
whismanoid 58:2fea32db466b 542 //----------------------------------------
whismanoid 53:3d5a3d241a5e 543 // success
whismanoid 53:3d5a3d241a5e 544 return 1;
whismanoid 53:3d5a3d241a5e 545 }
whismanoid 53:3d5a3d241a5e 546
whismanoid 53:3d5a3d241a5e 547 //----------------------------------------
whismanoid 53:3d5a3d241a5e 548 // Write a MAX11043 register.
whismanoid 53:3d5a3d241a5e 549 //
whismanoid 57:1c9da8e90737 550 // CMDOP_1aaa_aaaa_ReadRegister bit is cleared 0 indicating a write operation.
whismanoid 53:3d5a3d241a5e 551 //
whismanoid 53:3d5a3d241a5e 552 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 553 //
whismanoid 53:3d5a3d241a5e 554 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 555 //
whismanoid 53:3d5a3d241a5e 556 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 557 //
whismanoid 53:3d5a3d241a5e 558 // SPI MOSI = 0aaa_aaaa_dddd_dddd
whismanoid 53:3d5a3d241a5e 559 //
whismanoid 53:3d5a3d241a5e 560 // SPI MISO = xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 561 //
whismanoid 53:3d5a3d241a5e 562 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 563 //
whismanoid 53:3d5a3d241a5e 564 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 565 //
whismanoid 53:3d5a3d241a5e 566 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 567 //
whismanoid 53:3d5a3d241a5e 568 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 569 //
whismanoid 53:3d5a3d241a5e 570 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 571 //
whismanoid 53:3d5a3d241a5e 572 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 573 //
whismanoid 53:3d5a3d241a5e 574 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 575 //
whismanoid 53:3d5a3d241a5e 576 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 577 //
whismanoid 53:3d5a3d241a5e 578 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 579 uint8_t MAX11043::RegWrite(MAX11043_CMD_enum_t commandByte, uint32_t regData)
whismanoid 53:3d5a3d241a5e 580 {
whismanoid 53:3d5a3d241a5e 581
whismanoid 53:3d5a3d241a5e 582 //----------------------------------------
whismanoid 53:3d5a3d241a5e 583 // switch based on register address szie RegSize(commandByte)
whismanoid 57:1c9da8e90737 584 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 585 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 586 {
whismanoid 53:3d5a3d241a5e 587 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 588 {
whismanoid 63:8f39d21d6157 589 // SPI 8+8 = 16-bit transfer
whismanoid 63:8f39d21d6157 590 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 591 // SPI MOSI = 0aaa_aaaa_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 592 // SPI MISO = xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 593 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 594 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 595 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 596 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 597 mosiData[1] = regData;
whismanoid 63:8f39d21d6157 598 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 599 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 600 // TODO: cache CMD_0101_0100_d8_Wr15_FilterCAddress
whismanoid 63:8f39d21d6157 601 // if (commandByte == CMD_0101_0100_d8_Wr15_FilterCAddress) {
whismanoid 63:8f39d21d6157 602 // FilterCAddress = regData;
whismanoid 63:8f39d21d6157 603 // }
whismanoid 63:8f39d21d6157 604 // TODO: cache CMD_0110_0000_d8_Wr18_FlashMode
whismanoid 63:8f39d21d6157 605 // if (commandByte == CMD_0110_0000_d8_Wr18_FlashMode) {
whismanoid 63:8f39d21d6157 606 // FlashMode = regData;
whismanoid 63:8f39d21d6157 607 // }
whismanoid 53:3d5a3d241a5e 608 }
whismanoid 53:3d5a3d241a5e 609 break;
whismanoid 53:3d5a3d241a5e 610 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 611 #warning "Not Verified Yet: MAX11043::RegWrite 16-bit"
whismanoid 53:3d5a3d241a5e 612 {
whismanoid 63:8f39d21d6157 613 // SPI 8+16 = 24-bit transfer
whismanoid 63:8f39d21d6157 614 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 63:8f39d21d6157 615 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 616 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 617 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 618 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 619 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 620 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 621 mosiData[1] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 622 mosiData[2] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 623 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 624 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 625 // cache CMD_0010_0000_d16_Wr08_Configuration
whismanoid 63:8f39d21d6157 626 if (commandByte == CMD_0010_0000_d16_Wr08_Configuration) {
whismanoid 63:8f39d21d6157 627 config = regData;
whismanoid 63:8f39d21d6157 628 }
whismanoid 63:8f39d21d6157 629 // TODO: cache CMD_0010_0100_d16_Wr09_DAC
whismanoid 63:8f39d21d6157 630 // TODO: cache CMD_0010_1000_d16_Wr0A_DACStep
whismanoid 63:8f39d21d6157 631 // TODO: cache CMD_0010_1100_d16_Wr0B_DACHDACL
whismanoid 63:8f39d21d6157 632 // TODO: cache CMD_0011_0000_d16_Wr0C_ConfigA
whismanoid 63:8f39d21d6157 633 // TODO: cache CMD_0011_0100_d16_Wr0D_ConfigB
whismanoid 63:8f39d21d6157 634 // TODO: cache CMD_0011_1000_d16_Wr0E_ConfigC
whismanoid 63:8f39d21d6157 635 // TODO: cache CMD_0011_1100_d16_Wr0F_ConfigD
whismanoid 63:8f39d21d6157 636 // TODO: cache CMD_0100_0000_d16_Wr10_Reference
whismanoid 63:8f39d21d6157 637 // TODO: cache CMD_0100_0100_d16_Wr11_AGain
whismanoid 63:8f39d21d6157 638 // TODO: cache CMD_0100_1000_d16_Wr12_BGain
whismanoid 63:8f39d21d6157 639 // TODO: cache CMD_0100_1100_d16_Wr13_CGain
whismanoid 63:8f39d21d6157 640 // TODO: cache CMD_0101_0000_d16_Wr14_DGain
whismanoid 63:8f39d21d6157 641 // TODO: cache CMD_0110_0100_d16_Wr19_FlashAddr
whismanoid 63:8f39d21d6157 642 // TODO: cache CMD_0110_1000_d16_Wr1A_FlashDataIn
whismanoid 53:3d5a3d241a5e 643 }
whismanoid 53:3d5a3d241a5e 644 break;
whismanoid 63:8f39d21d6157 645 case 32: // 32-bit register size
whismanoid 63:8f39d21d6157 646 #warning "Not Verified Yet: MAX11043::RegWrite 32-bit"
whismanoid 53:3d5a3d241a5e 647 {
whismanoid 63:8f39d21d6157 648 // SPI 8+32 = 40-bit transfer
whismanoid 63:8f39d21d6157 649 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 63:8f39d21d6157 650 // SPI MOSI = 1aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 651 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 652 //
whismanoid 63:8f39d21d6157 653 size_t byteCount = 1 + (2 * 2);
whismanoid 63:8f39d21d6157 654 uint8_t mosiData[5];
whismanoid 63:8f39d21d6157 655 uint8_t misoData[5];
whismanoid 63:8f39d21d6157 656 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 657 mosiData[1] = (uint8_t)((regData >> 24) & 0xFF);
whismanoid 63:8f39d21d6157 658 mosiData[2] = (uint8_t)((regData >> 16) & 0xFF);
whismanoid 63:8f39d21d6157 659 mosiData[3] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 660 mosiData[4] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 661 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 662 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 663 // TODO: cache CMD_0101_1000_d32_Wr16_FilterCDataOut
whismanoid 63:8f39d21d6157 664 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 665 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 666 // }
whismanoid 63:8f39d21d6157 667 // TODO: cache CMD_0101_1100_d32_Wr17_FilterCDataIn
whismanoid 63:8f39d21d6157 668 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 669 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 670 // }
whismanoid 53:3d5a3d241a5e 671 }
whismanoid 53:3d5a3d241a5e 672 break;
whismanoid 53:3d5a3d241a5e 673 }
whismanoid 53:3d5a3d241a5e 674
whismanoid 53:3d5a3d241a5e 675 //----------------------------------------
whismanoid 53:3d5a3d241a5e 676 // success
whismanoid 53:3d5a3d241a5e 677 return 1;
whismanoid 53:3d5a3d241a5e 678 }
whismanoid 53:3d5a3d241a5e 679
whismanoid 53:3d5a3d241a5e 680 //----------------------------------------
whismanoid 53:3d5a3d241a5e 681 // Read an 8-bit MAX11043 register
whismanoid 53:3d5a3d241a5e 682 //
whismanoid 57:1c9da8e90737 683 // CMDOP_1aaa_aaaa_ReadRegister bit is set 1 indicating a read operation.
whismanoid 53:3d5a3d241a5e 684 //
whismanoid 53:3d5a3d241a5e 685 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 686 //
whismanoid 53:3d5a3d241a5e 687 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 688 //
whismanoid 53:3d5a3d241a5e 689 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 690 //
whismanoid 53:3d5a3d241a5e 691 // SPI MOSI = 1aaa_aaaa_0000_0000
whismanoid 53:3d5a3d241a5e 692 //
whismanoid 53:3d5a3d241a5e 693 // SPI MISO = xxxx_xxxx_dddd_dddd
whismanoid 53:3d5a3d241a5e 694 //
whismanoid 53:3d5a3d241a5e 695 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 696 //
whismanoid 53:3d5a3d241a5e 697 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 698 //
whismanoid 53:3d5a3d241a5e 699 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 700 //
whismanoid 53:3d5a3d241a5e 701 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 702 //
whismanoid 53:3d5a3d241a5e 703 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 704 //
whismanoid 53:3d5a3d241a5e 705 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 706 //
whismanoid 53:3d5a3d241a5e 707 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 708 //
whismanoid 53:3d5a3d241a5e 709 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 710 //
whismanoid 53:3d5a3d241a5e 711 //
whismanoid 53:3d5a3d241a5e 712 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 713 uint8_t MAX11043::RegRead(MAX11043_CMD_enum_t commandByte, uint32_t* ptrRegData)
whismanoid 53:3d5a3d241a5e 714 {
whismanoid 53:3d5a3d241a5e 715
whismanoid 53:3d5a3d241a5e 716 //----------------------------------------
whismanoid 53:3d5a3d241a5e 717 // switch based on register address szie RegSize(regAddress)
whismanoid 57:1c9da8e90737 718 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 719 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 720 {
whismanoid 53:3d5a3d241a5e 721 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 722 {
whismanoid 60:d1d1eaa90fb7 723 // SPI 8+8 = 16-bit transfer
whismanoid 62:8223a7253c90 724 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 725 // SPI MOSI = 1aaa_aaaa_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 726 // SPI MISO = xxxx_xxxx_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 727 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 728 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 729 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 730 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 731 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 732 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 733 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 734 if (ptrRegData) { (*ptrRegData) = misoData[1]; }
whismanoid 59:47538bcf6cda 735 if (commandByte == CMD_0001_1110_d8_Rd07_Status) {
whismanoid 59:47538bcf6cda 736 // TODO1: update status
whismanoid 63:8f39d21d6157 737 status = misoData[1];
whismanoid 59:47538bcf6cda 738 }
whismanoid 53:3d5a3d241a5e 739 }
whismanoid 53:3d5a3d241a5e 740 break;
whismanoid 53:3d5a3d241a5e 741 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 742 #warning "Not Verified Yet: MAX11043::RegRead 16-bit"
whismanoid 53:3d5a3d241a5e 743 {
whismanoid 60:d1d1eaa90fb7 744 // SPI 8+16 = 24-bit transfer
whismanoid 62:8223a7253c90 745 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 60:d1d1eaa90fb7 746 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 747 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 748 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 749 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 750 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 751 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 752 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 753 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 754 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 755 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 756 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 59:47538bcf6cda 757 if (commandByte == CMD_0010_0010_d16_Rd08_Configuration) {
whismanoid 59:47538bcf6cda 758 // TODO1: update config
whismanoid 63:8f39d21d6157 759 config = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 760 }
whismanoid 59:47538bcf6cda 761 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 762 // TODO1: update adca
whismanoid 63:8f39d21d6157 763 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 764 }
whismanoid 59:47538bcf6cda 765 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 766 // TODO1: update adcb
whismanoid 63:8f39d21d6157 767 adcb = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 768 }
whismanoid 59:47538bcf6cda 769 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 770 // TODO1: update adcc
whismanoid 63:8f39d21d6157 771 adcc = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 772 }
whismanoid 59:47538bcf6cda 773 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 774 // TODO1: update adcd
whismanoid 63:8f39d21d6157 775 adcd = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 776 }
whismanoid 53:3d5a3d241a5e 777 }
whismanoid 53:3d5a3d241a5e 778 break;
whismanoid 53:3d5a3d241a5e 779 case 24: // 24-bit register size
whismanoid 53:3d5a3d241a5e 780 {
whismanoid 60:d1d1eaa90fb7 781 // SPI 8+24 = 32-bit transfer
whismanoid 62:8223a7253c90 782 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32
whismanoid 63:8f39d21d6157 783 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 784 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 785 size_t byteCount = 1 + 3;
whismanoid 63:8f39d21d6157 786 uint8_t mosiData[4];
whismanoid 63:8f39d21d6157 787 uint8_t misoData[4];
whismanoid 63:8f39d21d6157 788 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 789 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 790 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 791 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 792 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 793 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 794 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 59:47538bcf6cda 795 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 796 // TODO1: update adca
whismanoid 63:8f39d21d6157 797 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 798 }
whismanoid 59:47538bcf6cda 799 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 800 // TODO1: update adcb
whismanoid 63:8f39d21d6157 801 adcb = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 802 }
whismanoid 59:47538bcf6cda 803 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 804 // TODO1: update adcc
whismanoid 63:8f39d21d6157 805 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 806 }
whismanoid 59:47538bcf6cda 807 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 808 // TODO1: update adcd
whismanoid 63:8f39d21d6157 809 adcd = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 810 }
whismanoid 59:47538bcf6cda 811 }
whismanoid 59:47538bcf6cda 812 break;
whismanoid 63:8f39d21d6157 813 case 32: // 32-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 814 //
whismanoid 63:8f39d21d6157 815 #warning "Not Implemented Yet: MAX11043::RegRead 32-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 816 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 817 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 818 // update adca, adcb
whismanoid 59:47538bcf6cda 819 //
whismanoid 63:8f39d21d6157 820 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 821 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 822 // update adcc, adcd
whismanoid 59:47538bcf6cda 823 //
whismanoid 59:47538bcf6cda 824 {
whismanoid 60:d1d1eaa90fb7 825 // SPI 8+32 = 40-bit transfer
whismanoid 62:8223a7253c90 826 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 60:d1d1eaa90fb7 827 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 828 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 829 size_t byteCount = 1 + (2 * 2);
whismanoid 62:8223a7253c90 830 uint8_t mosiData[5];
whismanoid 62:8223a7253c90 831 uint8_t misoData[5];
whismanoid 62:8223a7253c90 832 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 833 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 834 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 835 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 836 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 837 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 838 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 839 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 840 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 841 // TODO1: update adca
whismanoid 62:8223a7253c90 842 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 843 // TODO1: update adcb
whismanoid 62:8223a7253c90 844 adcb = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 845 }
whismanoid 63:8f39d21d6157 846 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 847 // TODO1: update adcc
whismanoid 62:8223a7253c90 848 adcc = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 849 // TODO1: update adcd
whismanoid 62:8223a7253c90 850 adcd = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 851 }
whismanoid 59:47538bcf6cda 852 }
whismanoid 59:47538bcf6cda 853 break;
whismanoid 63:8f39d21d6157 854 case 48: // 48-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 855 //
whismanoid 63:8f39d21d6157 856 #warning "Not Verified Yet: MAX11043::RegRead 48-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 857 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 858 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 859 // update adca, adcb
whismanoid 59:47538bcf6cda 860 //
whismanoid 63:8f39d21d6157 861 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 862 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 863 // update adcc, adcd
whismanoid 59:47538bcf6cda 864 //
whismanoid 59:47538bcf6cda 865 {
whismanoid 60:d1d1eaa90fb7 866 // SPI 8+48 = 56-bit transfer
whismanoid 62:8223a7253c90 867 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56
whismanoid 60:d1d1eaa90fb7 868 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 869 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 870 size_t byteCount = 1 + (3 * 2);
whismanoid 62:8223a7253c90 871 uint8_t mosiData[7];
whismanoid 62:8223a7253c90 872 uint8_t misoData[7];
whismanoid 62:8223a7253c90 873 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 874 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 875 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 876 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 877 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 878 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 879 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 880 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 881 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 882 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 883 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 884 // TODO1: update adca
whismanoid 62:8223a7253c90 885 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 886 // TODO1: update adcb
whismanoid 62:8223a7253c90 887 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 888 }
whismanoid 63:8f39d21d6157 889 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 890 // TODO1: update adcc
whismanoid 62:8223a7253c90 891 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 892 // TODO1: update adcd
whismanoid 62:8223a7253c90 893 adcd = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 894 }
whismanoid 59:47538bcf6cda 895 }
whismanoid 59:47538bcf6cda 896 break;
whismanoid 63:8f39d21d6157 897 case 64: // 64-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 898 //
whismanoid 63:8f39d21d6157 899 #warning "Not Verified Yet: MAX11043::RegRead 64-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 900 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 901 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 902 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 903 //
whismanoid 59:47538bcf6cda 904 {
whismanoid 60:d1d1eaa90fb7 905 // SPI 8+64 = 72-bit transfer
whismanoid 62:8223a7253c90 906 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72
whismanoid 60:d1d1eaa90fb7 907 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 908 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 909 size_t byteCount = 1 + (2 * 4);
whismanoid 62:8223a7253c90 910 uint8_t mosiData[9];
whismanoid 62:8223a7253c90 911 uint8_t misoData[9];
whismanoid 62:8223a7253c90 912 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 913 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 914 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 915 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 916 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 917 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 918 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 919 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 920 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 921 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 922 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 923 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 924 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 925 // TODO1: update adca
whismanoid 62:8223a7253c90 926 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 927 // TODO1: update adcb
whismanoid 62:8223a7253c90 928 adcb = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 929 // TODO1: update adcc
whismanoid 62:8223a7253c90 930 adcc = (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 931 // TODO1: update adcd
whismanoid 62:8223a7253c90 932 adcd = (misoData[7] << 8) | misoData[8];
whismanoid 59:47538bcf6cda 933 }
whismanoid 59:47538bcf6cda 934 }
whismanoid 59:47538bcf6cda 935 break;
whismanoid 63:8f39d21d6157 936 case 96: // 96-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 937 //
whismanoid 63:8f39d21d6157 938 #warning "Not Verified Yet: MAX11043::RegRead 96-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 939 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 940 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 941 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 942 //
whismanoid 59:47538bcf6cda 943 {
whismanoid 60:d1d1eaa90fb7 944 // SPI 8+96 = 104-bit transfer
whismanoid 62:8223a7253c90 945 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72 ___[9]_80 __[10]_88 __[11]_96 __[12]104
whismanoid 60:d1d1eaa90fb7 946 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 947 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 948 size_t byteCount = 1 + (3 * 4);
whismanoid 62:8223a7253c90 949 uint8_t mosiData[13];
whismanoid 62:8223a7253c90 950 uint8_t misoData[13];
whismanoid 62:8223a7253c90 951 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 952 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 953 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 954 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 955 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 956 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 957 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 958 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 959 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 960 mosiData[9] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 961 mosiData[10] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 962 mosiData[11] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 963 mosiData[12] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 964 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 965 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 966 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 967 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 968 // TODO1: update adca
whismanoid 62:8223a7253c90 969 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 970 // TODO1: update adcb
whismanoid 62:8223a7253c90 971 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 972 // TODO1: update adcc
whismanoid 62:8223a7253c90 973 adcc = (misoData[7] << 16) | (misoData[8] << 8) | misoData[9];
whismanoid 59:47538bcf6cda 974 // TODO1: update adcd
whismanoid 62:8223a7253c90 975 adcd = (misoData[10] << 16) | (misoData[11] << 8) | misoData[12];
whismanoid 59:47538bcf6cda 976 }
whismanoid 53:3d5a3d241a5e 977 }
whismanoid 53:3d5a3d241a5e 978 break;
whismanoid 53:3d5a3d241a5e 979 }
whismanoid 53:3d5a3d241a5e 980
whismanoid 53:3d5a3d241a5e 981 //----------------------------------------
whismanoid 53:3d5a3d241a5e 982 // success
whismanoid 53:3d5a3d241a5e 983 return 1;
whismanoid 53:3d5a3d241a5e 984 }
whismanoid 53:3d5a3d241a5e 985
whismanoid 53:3d5a3d241a5e 986 //----------------------------------------
whismanoid 53:3d5a3d241a5e 987 // Return the size of a MAX11043 register
whismanoid 53:3d5a3d241a5e 988 //
whismanoid 53:3d5a3d241a5e 989 // @return 8 for 8-bit, 16 for 16-bit, 24 for 24-bit, else 0 for undefined register size
whismanoid 53:3d5a3d241a5e 990 uint8_t MAX11043::RegSize(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 991 {
whismanoid 53:3d5a3d241a5e 992
whismanoid 53:3d5a3d241a5e 993 //----------------------------------------
whismanoid 53:3d5a3d241a5e 994 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 995 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 996 switch(commandByte)
whismanoid 53:3d5a3d241a5e 997 {
whismanoid 53:3d5a3d241a5e 998 default:
whismanoid 57:1c9da8e90737 999 // case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 1000 // case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 1001 // case CMDOP_1111_1111_NoOperationMOSIidleHigh:
whismanoid 53:3d5a3d241a5e 1002 return 0; // undefined register size
whismanoid 53:3d5a3d241a5e 1003 case CMD_0001_1110_d8_Rd07_Status:
whismanoid 53:3d5a3d241a5e 1004 case CMD_0101_0100_d8_Wr15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 1005 case CMD_0101_0110_d8_Rd15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 1006 case CMD_0110_0000_d8_Wr18_FlashMode:
whismanoid 53:3d5a3d241a5e 1007 case CMD_0110_0010_d8_Rd18_FlashMode:
whismanoid 53:3d5a3d241a5e 1008 return 8; // 8-bit register size
whismanoid 53:3d5a3d241a5e 1009 case CMD_0010_0000_d16_Wr08_Configuration:
whismanoid 53:3d5a3d241a5e 1010 case CMD_0010_0010_d16_Rd08_Configuration:
whismanoid 53:3d5a3d241a5e 1011 case CMD_0010_0100_d16_Wr09_DAC:
whismanoid 53:3d5a3d241a5e 1012 case CMD_0010_0110_d16_Rd09_DAC:
whismanoid 53:3d5a3d241a5e 1013 case CMD_0010_1000_d16_Wr0A_DACStep:
whismanoid 53:3d5a3d241a5e 1014 case CMD_0010_1010_d16_Rd0A_DACStep:
whismanoid 53:3d5a3d241a5e 1015 case CMD_0010_1100_d16_Wr0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 1016 case CMD_0010_1110_d16_Rd0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 1017 case CMD_0011_0000_d16_Wr0C_ConfigA:
whismanoid 53:3d5a3d241a5e 1018 case CMD_0011_0010_d16_Rd0C_ConfigA:
whismanoid 53:3d5a3d241a5e 1019 case CMD_0011_0100_d16_Wr0D_ConfigB:
whismanoid 53:3d5a3d241a5e 1020 case CMD_0011_0110_d16_Rd0D_ConfigB:
whismanoid 53:3d5a3d241a5e 1021 case CMD_0011_1000_d16_Wr0E_ConfigC:
whismanoid 53:3d5a3d241a5e 1022 case CMD_0011_1010_d16_Rd0E_ConfigC:
whismanoid 53:3d5a3d241a5e 1023 case CMD_0011_1100_d16_Wr0F_ConfigD:
whismanoid 53:3d5a3d241a5e 1024 case CMD_0011_1110_d16_Rd0F_ConfigD:
whismanoid 53:3d5a3d241a5e 1025 case CMD_0100_0000_d16_Wr10_Reference:
whismanoid 53:3d5a3d241a5e 1026 case CMD_0100_0010_d16_Rd10_Reference:
whismanoid 53:3d5a3d241a5e 1027 case CMD_0100_0100_d16_Wr11_AGain:
whismanoid 53:3d5a3d241a5e 1028 case CMD_0100_0110_d16_Rd11_AGain:
whismanoid 53:3d5a3d241a5e 1029 case CMD_0100_1000_d16_Wr12_BGain:
whismanoid 53:3d5a3d241a5e 1030 case CMD_0100_1010_d16_Rd12_BGain:
whismanoid 53:3d5a3d241a5e 1031 case CMD_0100_1100_d16_Wr13_CGain:
whismanoid 53:3d5a3d241a5e 1032 case CMD_0100_1110_d16_Rd13_CGain:
whismanoid 53:3d5a3d241a5e 1033 case CMD_0101_0000_d16_Wr14_DGain:
whismanoid 53:3d5a3d241a5e 1034 case CMD_0101_0010_d16_Rd14_DGain:
whismanoid 53:3d5a3d241a5e 1035 case CMD_0110_0100_d16_Wr19_FlashAddr:
whismanoid 53:3d5a3d241a5e 1036 case CMD_0110_0110_d16_Rd19_FlashAddr:
whismanoid 53:3d5a3d241a5e 1037 case CMD_0110_1000_d16_Wr1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 1038 case CMD_0110_1010_d16_Rd1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 1039 case CMD_0110_1110_d16_Rd1B_FlashDataOut:
whismanoid 53:3d5a3d241a5e 1040 return 16; // 16-bit register size
whismanoid 59:47538bcf6cda 1041 case CMD_0000_0010_d16o8_Rd00_ADCa:
whismanoid 59:47538bcf6cda 1042 case CMD_0000_0110_d16o8_Rd01_ADCb:
whismanoid 59:47538bcf6cda 1043 case CMD_0000_1010_d16o8_Rd02_ADCc:
whismanoid 59:47538bcf6cda 1044 case CMD_0000_1110_d16o8_Rd03_ADCd:
whismanoid 59:47538bcf6cda 1045 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1046 {
whismanoid 59:47538bcf6cda 1047 // %SW 0x02 (0 0 0) -- for 24-bit read
whismanoid 59:47538bcf6cda 1048 return 24; // 24-bit register size
whismanoid 59:47538bcf6cda 1049 }
whismanoid 59:47538bcf6cda 1050 // %SW 0x02 (0 0) -- for 16-bit read
whismanoid 59:47538bcf6cda 1051 //
whismanoid 59:47538bcf6cda 1052 return 16; // 16-bit register size
whismanoid 63:8f39d21d6157 1053 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab:
whismanoid 63:8f39d21d6157 1054 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd:
whismanoid 59:47538bcf6cda 1055 //
whismanoid 59:47538bcf6cda 1056 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 1057 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1058 {
whismanoid 59:47538bcf6cda 1059 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 1060 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 1061 return 48; // 48-bit register size: 2*(24)
whismanoid 59:47538bcf6cda 1062 }
whismanoid 59:47538bcf6cda 1063 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 1064 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 1065 //
whismanoid 59:47538bcf6cda 1066 return 32; // 32-bit register size: 2*(16)
whismanoid 63:8f39d21d6157 1067 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd:
whismanoid 59:47538bcf6cda 1068 //
whismanoid 59:47538bcf6cda 1069 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 1070 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1071 {
whismanoid 59:47538bcf6cda 1072 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1073 return 96; // 96-bit register size: 4*(24)
whismanoid 59:47538bcf6cda 1074 }
whismanoid 59:47538bcf6cda 1075 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1076 //
whismanoid 59:47538bcf6cda 1077 return 64; // 64-bit register size: 4*(16)
whismanoid 53:3d5a3d241a5e 1078 case CMD_0101_1000_d32_Wr16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 1079 case CMD_0101_1010_d32_Rd16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 1080 case CMD_0101_1100_d32_Wr17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 1081 case CMD_0101_1110_d32_Rd17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 1082 return 32; // 32-bit register size
whismanoid 53:3d5a3d241a5e 1083 }
whismanoid 53:3d5a3d241a5e 1084 }
whismanoid 53:3d5a3d241a5e 1085
whismanoid 53:3d5a3d241a5e 1086 //----------------------------------------
whismanoid 57:1c9da8e90737 1087 // Decode operation from commandByte
whismanoid 57:1c9da8e90737 1088 //
whismanoid 57:1c9da8e90737 1089 // @return operation such as idle, read register, write register, etc.
whismanoid 57:1c9da8e90737 1090 MAX11043::MAX11043_CMDOP_enum_t MAX11043::DecodeCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 57:1c9da8e90737 1091 {
whismanoid 57:1c9da8e90737 1092
whismanoid 57:1c9da8e90737 1093 //----------------------------------------
whismanoid 57:1c9da8e90737 1094 // decode operation from command byte
whismanoid 57:1c9da8e90737 1095 switch (commandByte & 0x83)
whismanoid 57:1c9da8e90737 1096 {
whismanoid 57:1c9da8e90737 1097 case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 1098 return CMDOP_0aaa_aa10_ReadRegister;
whismanoid 57:1c9da8e90737 1099 case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 1100 return CMDOP_0aaa_aa00_WriteRegister;
whismanoid 57:1c9da8e90737 1101 default:
whismanoid 57:1c9da8e90737 1102 return CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 57:1c9da8e90737 1103 }
whismanoid 57:1c9da8e90737 1104 }
whismanoid 57:1c9da8e90737 1105
whismanoid 57:1c9da8e90737 1106 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1107 // Return the address field of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1108 //
whismanoid 53:3d5a3d241a5e 1109 // @return register address field as given in datasheet
whismanoid 53:3d5a3d241a5e 1110 uint8_t MAX11043::RegAddrOfCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1111 {
whismanoid 53:3d5a3d241a5e 1112
whismanoid 53:3d5a3d241a5e 1113 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1114 // extract register address value from command byte
whismanoid 57:1c9da8e90737 1115 return (uint8_t)((commandByte &~ 0x83) >> 2); // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 1116 }
whismanoid 53:3d5a3d241a5e 1117
whismanoid 53:3d5a3d241a5e 1118 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1119 // Test whether a command byte is a register read command
whismanoid 53:3d5a3d241a5e 1120 //
whismanoid 53:3d5a3d241a5e 1121 // @return true if command byte is a register read command
whismanoid 53:3d5a3d241a5e 1122 uint8_t MAX11043::IsRegReadCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1123 {
whismanoid 53:3d5a3d241a5e 1124
whismanoid 53:3d5a3d241a5e 1125 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1126 // Test whether a command byte is a register read command
whismanoid 57:1c9da8e90737 1127 return (commandByte &~ 0x02) ? 1 : 0; // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 1128 }
whismanoid 53:3d5a3d241a5e 1129
whismanoid 53:3d5a3d241a5e 1130 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1131 // Return the name of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1132 //
whismanoid 53:3d5a3d241a5e 1133 // @return null-terminated constant C string containing register name or empty string
whismanoid 53:3d5a3d241a5e 1134 const char* MAX11043::RegName(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1135 {
whismanoid 53:3d5a3d241a5e 1136
whismanoid 53:3d5a3d241a5e 1137 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1138 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 1139 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 1140 switch(commandByte)
whismanoid 53:3d5a3d241a5e 1141 {
whismanoid 53:3d5a3d241a5e 1142 default:
whismanoid 53:3d5a3d241a5e 1143 return ""; // undefined register
whismanoid 57:1c9da8e90737 1144 // case CMDOP_0aaa_aa00_WriteRegister: return "_______";
whismanoid 57:1c9da8e90737 1145 // case CMDOP_0aaa_aa10_ReadRegister: return "_______";
whismanoid 57:1c9da8e90737 1146 // case CMDOP_1111_1111_NoOperationMOSIidleHigh: return "_______";
whismanoid 59:47538bcf6cda 1147 case CMD_0000_0010_d16o8_Rd00_ADCa: return "ADCa";
whismanoid 59:47538bcf6cda 1148 case CMD_0000_0110_d16o8_Rd01_ADCb: return "ADCb";
whismanoid 59:47538bcf6cda 1149 case CMD_0000_1010_d16o8_Rd02_ADCc: return "ADCc";
whismanoid 59:47538bcf6cda 1150 case CMD_0000_1110_d16o8_Rd03_ADCd: return "ADCd";
whismanoid 63:8f39d21d6157 1151 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab: return "ADCab";
whismanoid 63:8f39d21d6157 1152 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd: return "ADCcd";
whismanoid 63:8f39d21d6157 1153 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd: return "ADCabcd";
whismanoid 53:3d5a3d241a5e 1154 case CMD_0001_1110_d8_Rd07_Status: return "Status";
whismanoid 53:3d5a3d241a5e 1155 case CMD_0010_0000_d16_Wr08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1156 case CMD_0010_0010_d16_Rd08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1157 case CMD_0010_0100_d16_Wr09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1158 case CMD_0010_0110_d16_Rd09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1159 case CMD_0010_1000_d16_Wr0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1160 case CMD_0010_1010_d16_Rd0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1161 case CMD_0010_1100_d16_Wr0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1162 case CMD_0010_1110_d16_Rd0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1163 case CMD_0011_0000_d16_Wr0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1164 case CMD_0011_0010_d16_Rd0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1165 case CMD_0011_0100_d16_Wr0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1166 case CMD_0011_0110_d16_Rd0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1167 case CMD_0011_1000_d16_Wr0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1168 case CMD_0011_1010_d16_Rd0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1169 case CMD_0011_1100_d16_Wr0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1170 case CMD_0011_1110_d16_Rd0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1171 case CMD_0100_0000_d16_Wr10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1172 case CMD_0100_0010_d16_Rd10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1173 case CMD_0100_0100_d16_Wr11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1174 case CMD_0100_0110_d16_Rd11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1175 case CMD_0100_1000_d16_Wr12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1176 case CMD_0100_1010_d16_Rd12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1177 case CMD_0100_1100_d16_Wr13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1178 case CMD_0100_1110_d16_Rd13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1179 case CMD_0101_0000_d16_Wr14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1180 case CMD_0101_0010_d16_Rd14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1181 case CMD_0101_0100_d8_Wr15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1182 case CMD_0101_0110_d8_Rd15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1183 case CMD_0101_1000_d32_Wr16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1184 case CMD_0101_1010_d32_Rd16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1185 case CMD_0101_1100_d32_Wr17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1186 case CMD_0101_1110_d32_Rd17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1187 case CMD_0110_0000_d8_Wr18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1188 case CMD_0110_0010_d8_Rd18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1189 case CMD_0110_0100_d16_Wr19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1190 case CMD_0110_0110_d16_Rd19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1191 case CMD_0110_1000_d16_Wr1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1192 case CMD_0110_1010_d16_Rd1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1193 case CMD_0110_1110_d16_Rd1B_FlashDataOut: return "FlashDataOut";
whismanoid 53:3d5a3d241a5e 1194 }
whismanoid 53:3d5a3d241a5e 1195 }
whismanoid 53:3d5a3d241a5e 1196
whismanoid 59:47538bcf6cda 1197 //----------------------------------------
whismanoid 64:a667cfd83492 1198 // Menu item '$' -> adca, adcb, adcc, adcd
whismanoid 64:a667cfd83492 1199 // Read ADCabcd
whismanoid 64:a667cfd83492 1200 //
whismanoid 64:a667cfd83492 1201 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1202 uint8_t MAX11043::Read_ADCabcd(void)
whismanoid 64:a667cfd83492 1203 {
whismanoid 64:a667cfd83492 1204
whismanoid 64:a667cfd83492 1205 //----------------------------------------
whismanoid 64:a667cfd83492 1206 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1207 #warning "Not Tested Yet: MAX11043::Read_ADCabcd..."
whismanoid 64:a667cfd83492 1208
whismanoid 69:989e392cf635 1209 //--------------------------------------------------
whismanoid 69:989e392cf635 1210 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 1211 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 1212 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 1213 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1214 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 1215 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 1216 // 2020-02-20 MAX11043_EOC_INTERRUPT_POLLING works on MAX32625MBED at 9us conversion rate, with 1us timing margin
whismanoid 69:989e392cf635 1217 // TODO: poll m_EOC_pin if CONVRUN is high
whismanoid 69:989e392cf635 1218 if (m_CONVRUN_pin)
whismanoid 69:989e392cf635 1219 {
whismanoid 69:989e392cf635 1220 #warning "MAX11043::Read_ADCabcd() Potential infinite loop if EOC pin not connected"
whismanoid 69:989e392cf635 1221 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 69:989e392cf635 1222 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 1223 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 1224 (m_EOC_pin != 1));
whismanoid 69:989e392cf635 1225 futility_countdown--)
whismanoid 69:989e392cf635 1226 {
whismanoid 69:989e392cf635 1227 // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 69:989e392cf635 1228 }
whismanoid 69:989e392cf635 1229 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 1230 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 1231 (m_EOC_pin != 0));
whismanoid 69:989e392cf635 1232 futility_countdown--)
whismanoid 69:989e392cf635 1233 {
whismanoid 69:989e392cf635 1234 // spinlock waiting for logic low pin state (new data is available)
whismanoid 69:989e392cf635 1235 }
whismanoid 69:989e392cf635 1236 }
whismanoid 69:989e392cf635 1237 else
whismanoid 69:989e392cf635 1238 {
whismanoid 69:989e392cf635 1239 // CONVRUN pin is being driven low, so conversion result will not change, EOC# remains high
whismanoid 69:989e392cf635 1240 }
whismanoid 69:989e392cf635 1241 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1242 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 1243 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1244 //--------------------------------------------------
whismanoid 69:989e392cf635 1245
whismanoid 64:a667cfd83492 1246 //----------------------------------------
whismanoid 64:a667cfd83492 1247 // read register ADCabcd -> &adca, &adcb, &adcc, &adcd
whismanoid 64:a667cfd83492 1248 RegRead(CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd, 0);
whismanoid 64:a667cfd83492 1249
whismanoid 64:a667cfd83492 1250 //----------------------------------------
whismanoid 64:a667cfd83492 1251 // success
whismanoid 64:a667cfd83492 1252 return 1;
whismanoid 64:a667cfd83492 1253 }
whismanoid 64:a667cfd83492 1254
whismanoid 64:a667cfd83492 1255 //----------------------------------------
whismanoid 66:3fe92f6f1cfa 1256 // Menu item 'GA'
whismanoid 64:a667cfd83492 1257 // Write AGain register
whismanoid 64:a667cfd83492 1258 //
whismanoid 64:a667cfd83492 1259 // @param[in] gain 2's complement, 0x800=0.25V/V, 0x1000=0.5V/V, 0x2000=1VV/V, 0x4000=2V/V, default=0x2000
whismanoid 64:a667cfd83492 1260 //
whismanoid 64:a667cfd83492 1261 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1262 uint8_t MAX11043::Write_AGain(uint32_t gain)
whismanoid 64:a667cfd83492 1263 {
whismanoid 64:a667cfd83492 1264
whismanoid 64:a667cfd83492 1265 //----------------------------------------
whismanoid 64:a667cfd83492 1266 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1267 #warning "Not Tested Yet: MAX11043::Write_AGain..."
whismanoid 64:a667cfd83492 1268
whismanoid 64:a667cfd83492 1269 //----------------------------------------
whismanoid 64:a667cfd83492 1270 // write register
whismanoid 64:a667cfd83492 1271 RegWrite(CMD_0100_0100_d16_Wr11_AGain, gain);
whismanoid 64:a667cfd83492 1272
whismanoid 64:a667cfd83492 1273 //----------------------------------------
whismanoid 64:a667cfd83492 1274 // success
whismanoid 64:a667cfd83492 1275 return 1;
whismanoid 64:a667cfd83492 1276 }
whismanoid 64:a667cfd83492 1277
whismanoid 64:a667cfd83492 1278 //----------------------------------------
whismanoid 59:47538bcf6cda 1279 // Menu item 'XX'
whismanoid 59:47538bcf6cda 1280 //
whismanoid 59:47538bcf6cda 1281 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1282 uint8_t MAX11043::Configure_XXXXX(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1283 {
whismanoid 59:47538bcf6cda 1284
whismanoid 59:47538bcf6cda 1285 //----------------------------------------
whismanoid 59:47538bcf6cda 1286 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1287 #warning "Not Tested Yet: MAX11043::Configure_XXXXX..."
whismanoid 59:47538bcf6cda 1288
whismanoid 59:47538bcf6cda 1289 //----------------------------------------
whismanoid 59:47538bcf6cda 1290 // read register
whismanoid 59:47538bcf6cda 1291 RegRead(CMD_0000_0010_d16o8_Rd00_ADCa, &adca);
whismanoid 59:47538bcf6cda 1292
whismanoid 59:47538bcf6cda 1293 //----------------------------------------
whismanoid 59:47538bcf6cda 1294 // success
whismanoid 59:47538bcf6cda 1295 return 1;
whismanoid 59:47538bcf6cda 1296 }
whismanoid 59:47538bcf6cda 1297
whismanoid 59:47538bcf6cda 1298 //----------------------------------------
whismanoid 59:47538bcf6cda 1299 // Menu item 'XY'
whismanoid 59:47538bcf6cda 1300 //
whismanoid 59:47538bcf6cda 1301 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1302 uint8_t MAX11043::Configure_XXXXY(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1303 {
whismanoid 59:47538bcf6cda 1304
whismanoid 59:47538bcf6cda 1305 //----------------------------------------
whismanoid 59:47538bcf6cda 1306 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1307 #warning "Not Tested Yet: MAX11043::Configure_XXXXY..."
whismanoid 59:47538bcf6cda 1308
whismanoid 59:47538bcf6cda 1309 //----------------------------------------
whismanoid 59:47538bcf6cda 1310 // read register
whismanoid 59:47538bcf6cda 1311 RegRead(CMD_0001_1110_d8_Rd07_Status, &status);
whismanoid 59:47538bcf6cda 1312
whismanoid 59:47538bcf6cda 1313 //----------------------------------------
whismanoid 59:47538bcf6cda 1314 // success
whismanoid 59:47538bcf6cda 1315 return 1;
whismanoid 59:47538bcf6cda 1316 }
whismanoid 59:47538bcf6cda 1317
whismanoid 53:3d5a3d241a5e 1318
whismanoid 53:3d5a3d241a5e 1319 // End of file