Mark Underwood / Mbed OS MAX11043_Serial_Tester

Test program running on MAX32625MBED. Control through USB Serial commands using a terminal emulator such as teraterm or putty.

Dependencies:   MaximTinyTester CmdLine MAX541 USBDevice

MAX11043/MAX11043.cpp@72:40feab5fd579, 2020-02-22 (annotated)

Committer:
whismanoid
Date:
Sat Feb 22 00:10:47 2020 +0000
Revision:
72:40feab5fd579
Parent:
71:62bcd01ea87f
Child:
73:879578472009
WIP MAX11043 EOC interrupt - scope trigger pulse success; but crash when try Read_ADCabcd()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 53:3d5a3d241a5e 1 // /*******************************************************************************
whismanoid 53:3d5a3d241a5e 2 // * Copyright (C) 2020 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 53:3d5a3d241a5e 3 // *
whismanoid 53:3d5a3d241a5e 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 53:3d5a3d241a5e 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 53:3d5a3d241a5e 6 // * to deal in the Software without restriction, including without limitation
whismanoid 53:3d5a3d241a5e 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 53:3d5a3d241a5e 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 53:3d5a3d241a5e 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 53:3d5a3d241a5e 10 // *
whismanoid 53:3d5a3d241a5e 11 // * The above copyright notice and this permission notice shall be included
whismanoid 53:3d5a3d241a5e 12 // * in all copies or substantial portions of the Software.
whismanoid 53:3d5a3d241a5e 13 // *
whismanoid 53:3d5a3d241a5e 14 // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid 53:3d5a3d241a5e 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 53:3d5a3d241a5e 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 53:3d5a3d241a5e 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 53:3d5a3d241a5e 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 53:3d5a3d241a5e 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 53:3d5a3d241a5e 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 53:3d5a3d241a5e 21 // *
whismanoid 53:3d5a3d241a5e 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 53:3d5a3d241a5e 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 53:3d5a3d241a5e 24 // * Products, Inc. Branding Policy.
whismanoid 53:3d5a3d241a5e 25 // *
whismanoid 53:3d5a3d241a5e 26 // * The mere transfer of this software does not imply any licenses
whismanoid 53:3d5a3d241a5e 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 53:3d5a3d241a5e 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 53:3d5a3d241a5e 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 53:3d5a3d241a5e 30 // * ownership rights.
whismanoid 53:3d5a3d241a5e 31 // *******************************************************************************
whismanoid 53:3d5a3d241a5e 32 // */
whismanoid 53:3d5a3d241a5e 33 // *********************************************************************
whismanoid 53:3d5a3d241a5e 34 // @file MAX11043.cpp
whismanoid 53:3d5a3d241a5e 35 // *********************************************************************
whismanoid 53:3d5a3d241a5e 36 // Device Driver file
whismanoid 53:3d5a3d241a5e 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid 53:3d5a3d241a5e 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 53:3d5a3d241a5e 39 // System Name = ExampleSystem
whismanoid 53:3d5a3d241a5e 40 // System Description = Device driver example
whismanoid 53:3d5a3d241a5e 41
whismanoid 53:3d5a3d241a5e 42 #include "MAX11043.h"
whismanoid 69:989e392cf635 43 //--------------------------------------------------
whismanoid 69:989e392cf635 44 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 45 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 46 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 47 #ifndef MAX11043_EOC_INTERRUPT_POLLING
whismanoid 71:62bcd01ea87f 48 #define MAX11043_EOC_INTERRUPT_POLLING 0
whismanoid 69:989e392cf635 49 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 50
whismanoid 53:3d5a3d241a5e 51 // Device Name = MAX11043
whismanoid 53:3d5a3d241a5e 52 // Device Description = 200ksps, Low-Power, Serial SPI 24-Bit, 4-Channel, Differential/Single-Ended Input, Simultaneous-Sampling SD ADC
whismanoid 53:3d5a3d241a5e 53 // Device DeviceBriefDescription = 24-bit 200ksps Delta-Sigma ADC
whismanoid 53:3d5a3d241a5e 54 // Device Manufacturer = Maxim Integrated
whismanoid 53:3d5a3d241a5e 55 // Device PartNumber = MAX11043ATL+
whismanoid 53:3d5a3d241a5e 56 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 53:3d5a3d241a5e 57 //
whismanoid 53:3d5a3d241a5e 58 // ADC MaxOutputDataRate = 200ksps
whismanoid 53:3d5a3d241a5e 59 // ADC NumChannels = 4
whismanoid 53:3d5a3d241a5e 60 // ADC ResolutionBits = 24
whismanoid 53:3d5a3d241a5e 61 //
whismanoid 53:3d5a3d241a5e 62 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 63 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 64 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 65 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 66 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 67 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 68 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 69 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 70 //
whismanoid 53:3d5a3d241a5e 71 // InputPin Name = CONVRUN
whismanoid 53:3d5a3d241a5e 72 // InputPin Description = CONVRUN (digital input). Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 53:3d5a3d241a5e 73 // CONVRUN is low.
whismanoid 53:3d5a3d241a5e 74 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 75 //
whismanoid 53:3d5a3d241a5e 76 // InputPin Name = SHDN
whismanoid 53:3d5a3d241a5e 77 // InputPin Description = Shutdown (digital input). Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 53:3d5a3d241a5e 78 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 79 //
whismanoid 53:3d5a3d241a5e 80 // InputPin Name = DACSTEP
whismanoid 53:3d5a3d241a5e 81 // InputPin Description = DACSTEP (digital input). DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 53:3d5a3d241a5e 82 // edge of the system clock.
whismanoid 53:3d5a3d241a5e 83 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 84 //
whismanoid 53:3d5a3d241a5e 85 // InputPin Name = UP/DWN#
whismanoid 53:3d5a3d241a5e 86 // InputPin Description = UP/DWN# (digital input). DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 53:3d5a3d241a5e 87 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 88 //
whismanoid 53:3d5a3d241a5e 89 // OutputPin Name = EOC
whismanoid 53:3d5a3d241a5e 90 // OutputPin Description = End of Conversion Output. Active-Low End-of-Conversion Indicator. EOC asserts low to indicate that new data is ready.
whismanoid 53:3d5a3d241a5e 91 // OutputPin Function = Event
whismanoid 53:3d5a3d241a5e 92 //
whismanoid 58:2fea32db466b 93 // SupplyPin Name = AVDD
whismanoid 58:2fea32db466b 94 // SupplyPin Description = Analog Power-Supply Input. Bypass each AVDD with a nominal 1uF capacitor to AGND.
whismanoid 58:2fea32db466b 95 // SupplyPin VinMax = 3.60
whismanoid 58:2fea32db466b 96 // SupplyPin VinMin = 3.00
whismanoid 58:2fea32db466b 97 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 98 //
whismanoid 58:2fea32db466b 99 // SupplyPin Name = AGND
whismanoid 58:2fea32db466b 100 // SupplyPin Description = Analog Ground. Connect all AGND inputs together.
whismanoid 58:2fea32db466b 101 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 102 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 103 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 104 //
whismanoid 58:2fea32db466b 105 // SupplyPin Name = DGND
whismanoid 58:2fea32db466b 106 // SupplyPin Description = Digital Ground. Connect all DGND inputs together.
whismanoid 58:2fea32db466b 107 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 108 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 109 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 110 //
whismanoid 58:2fea32db466b 111 // SupplyPin Name = DVDD
whismanoid 58:2fea32db466b 112 // SupplyPin Description = Digital Power-Supply Input. Bypass each DVDD with a nominal 1uF capacitor to DGND.
whismanoid 58:2fea32db466b 113 // SupplyPin VinMax = 3.60 (*TODO PENDING VERIFICATION*)
whismanoid 58:2fea32db466b 114 // SupplyPin VinMin = 3.00 (*TODO PENDING VERIFICATION*)
whismanoid 58:2fea32db466b 115 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 116 //
whismanoid 58:2fea32db466b 117 // SupplyPin Name = DVREG
whismanoid 58:2fea32db466b 118 // SupplyPin Description = Regulated Digital Core Supply (from internal +2.5V regulator). Bypass DVREG to DGND with a 10uF capacitor.
whismanoid 58:2fea32db466b 119 // SupplyPin VinMax = 2.50
whismanoid 58:2fea32db466b 120 // SupplyPin VinMin = 2.50
whismanoid 58:2fea32db466b 121 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 122 //
whismanoid 53:3d5a3d241a5e 123
whismanoid 53:3d5a3d241a5e 124 // CODE GENERATOR: class constructor definition
whismanoid 53:3d5a3d241a5e 125 MAX11043::MAX11043(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 53:3d5a3d241a5e 126 // CODE GENERATOR: class constructor definition gpio InputPin pins
whismanoid 53:3d5a3d241a5e 127 DigitalOut &CONVRUN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 128 DigitalOut &SHDN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 129 DigitalOut &DACSTEP_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 130 DigitalOut &UP_slash_DWNb_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 131 // CODE GENERATOR: class constructor definition gpio OutputPin pins
whismanoid 69:989e392cf635 132 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 133 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 134 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 135 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 136 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 53:3d5a3d241a5e 137 DigitalIn &EOC_pin, // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 138 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 139 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 140 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 69:989e392cf635 141 InterruptIn &EOC_pin, // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 142 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 143 // CODE GENERATOR: class constructor definition ic_variant
whismanoid 53:3d5a3d241a5e 144 MAX11043_ic_t ic_variant)
whismanoid 53:3d5a3d241a5e 145 // CODE GENERATOR: class constructor initializer list
whismanoid 53:3d5a3d241a5e 146 : m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid 53:3d5a3d241a5e 147 // CODE GENERATOR: class constructor initializer list gpio InputPin pins
whismanoid 53:3d5a3d241a5e 148 m_CONVRUN_pin(CONVRUN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 149 m_SHDN_pin(SHDN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 150 m_DACSTEP_pin(DACSTEP_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 151 m_UP_slash_DWNb_pin(UP_slash_DWNb_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 152 // CODE GENERATOR: class constructor initializer list gpio OutputPin pins
whismanoid 69:989e392cf635 153 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 154 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 155 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 156 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 53:3d5a3d241a5e 157 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 158 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 159 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 70:f44a577c9e59 160 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 161 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 162 // CODE GENERATOR: class constructor initializer list ic_variant
whismanoid 53:3d5a3d241a5e 163 m_ic_variant(ic_variant)
whismanoid 53:3d5a3d241a5e 164 {
whismanoid 53:3d5a3d241a5e 165 // CODE GENERATOR: class constructor definition SPI interface initialization
whismanoid 53:3d5a3d241a5e 166 //
whismanoid 53:3d5a3d241a5e 167 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 168 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 169 m_SPI_cs_state = 1;
whismanoid 67:5b8a495dda1c 170 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 171 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 172 }
whismanoid 53:3d5a3d241a5e 173
whismanoid 53:3d5a3d241a5e 174 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 175 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 176 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 177 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 178 m_SPI_dataMode = 0; //SPI_MODE0; // CPOL=0,CPHA=0: Rising Edge stable; SCLK idle Low
whismanoid 53:3d5a3d241a5e 179 m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid 53:3d5a3d241a5e 180
whismanoid 53:3d5a3d241a5e 181 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 182 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 183 //#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid 53:3d5a3d241a5e 184 //#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid 53:3d5a3d241a5e 185 //#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid 53:3d5a3d241a5e 186 //#define SPI_SCLK_Hz 6000000 // 6MHz
whismanoid 53:3d5a3d241a5e 187 //#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid 53:3d5a3d241a5e 188 //#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid 53:3d5a3d241a5e 189 //#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid 61:b4f3051578ef 190 m_SPI_SCLK_Hz = 24000000; // platform limit 24MHz; MAX11043 limit is 40MHz
whismanoid 53:3d5a3d241a5e 191 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 192
whismanoid 53:3d5a3d241a5e 193 //
whismanoid 53:3d5a3d241a5e 194 // CODE GENERATOR: class constructor definition gpio InputPin (Input to device) initialization
whismanoid 53:3d5a3d241a5e 195 //
whismanoid 53:3d5a3d241a5e 196 // CONVRUN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 197 m_CONVRUN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 198 //
whismanoid 53:3d5a3d241a5e 199 // SHDN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 200 m_SHDN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 201 //
whismanoid 53:3d5a3d241a5e 202 // DACSTEP Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 203 m_DACSTEP_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 204 //
whismanoid 53:3d5a3d241a5e 205 // UP_slash_DWNb Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 206 m_UP_slash_DWNb_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 207 //
whismanoid 53:3d5a3d241a5e 208 // CODE GENERATOR: class constructor definition gpio OutputPin (Output from MAX11043 device) initialization
whismanoid 53:3d5a3d241a5e 209 //
whismanoid 53:3d5a3d241a5e 210 // EOC Event Output from device
whismanoid 69:989e392cf635 211 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 212 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 213 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 214 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 215 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 216 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 217 // TODO: onEOCFallingEdge: interrupt handler requires global object extern MAX11043 g_MAX11043_device
whismanoid 71:62bcd01ea87f 218 // InterruptIn interruptEOC(EOC_pin); // InterruptIn constructor requires PinName, not DigitalIn -- Error: No instance of constructor "mbed::InterruptIn::InterruptIn" matches the argument list in "MAX11043/MAX11043.cpp", Line: 187, Col: 31
whismanoid 69:989e392cf635 219 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 70:f44a577c9e59 220 extern void onEOCFallingEdge(void);
whismanoid 71:62bcd01ea87f 221 // interruptEOC.fall(&onEOCFallingEdge);
whismanoid 71:62bcd01ea87f 222 EOC_pin.fall(&onEOCFallingEdge);
whismanoid 69:989e392cf635 223 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 224
whismanoid 53:3d5a3d241a5e 225 }
whismanoid 53:3d5a3d241a5e 226
whismanoid 69:989e392cf635 227 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 228 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 229 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 230 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 231 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 232 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 233 // Interrupt Handler: EOC Event Output from device
whismanoid 69:989e392cf635 234 void onEOCFallingEdge(void)
whismanoid 69:989e392cf635 235 {
whismanoid 72:40feab5fd579 236 // VERIFIED: if DO NOTHING inside interrupt service routine, no crash
whismanoid 72:40feab5fd579 237 #if 1
whismanoid 72:40feab5fd579 238 // VERIFIED: GPIO PIN pulse in response to EOC# falling edge, no crash on HH, no missed pulses
whismanoid 72:40feab5fd579 239 // Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 72:40feab5fd579 240 #define D5 P0_5
whismanoid 72:40feab5fd579 241 DigitalOut ScopeTrigger(D5);
whismanoid 72:40feab5fd579 242 ScopeTrigger = 0;
whismanoid 72:40feab5fd579 243 ScopeTrigger = 1;
whismanoid 72:40feab5fd579 244 ScopeTrigger = 0;
whismanoid 72:40feab5fd579 245 ScopeTrigger = 1;
whismanoid 72:40feab5fd579 246 #endif
whismanoid 72:40feab5fd579 247 #if 0
whismanoid 72:40feab5fd579 248 // TODO: read 4 channels in response to EOC# falling edge
whismanoid 72:40feab5fd579 249 // WIP MAX11043 interrupt CRASH on Menu item HH CONVRUN High
whismanoid 72:40feab5fd579 250 //
whismanoid 72:40feab5fd579 251 // ++ MbedOS Error Info ++
whismanoid 72:40feab5fd579 252 // Error Status: 0x80020115 Code: 277 Module: 2
whismanoid 72:40feab5fd579 253 // Error Message: Mutex lock failed
whismanoid 72:40feab5fd579 254 // Location: 0xBA33
whismanoid 72:40feab5fd579 255 // Error Value: 0xFFFFFFFA
whismanoid 72:40feab5fd579 256 // Current Thread: main Id: 0x20002CD0 Entry: 0xBD17 StackSize: 0x1000 StackMem: 0x20001CD0 SP: 0x20027ED0
whismanoid 72:40feab5fd579 257 // For more info, visit: https://armmbed.github.io/mbedos-error/?error=0x80020115
whismanoid 72:40feab5fd579 258 // -- MbedOS Error Info --
whismanoid 69:989e392cf635 259 extern MAX11043 g_MAX11043_device;
whismanoid 69:989e392cf635 260 g_MAX11043_device.Read_ADCabcd();
whismanoid 72:40feab5fd579 261 #endif
whismanoid 69:989e392cf635 262 }
whismanoid 69:989e392cf635 263 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 264
whismanoid 53:3d5a3d241a5e 265 // CODE GENERATOR: class destructor definition
whismanoid 53:3d5a3d241a5e 266 MAX11043::~MAX11043()
whismanoid 53:3d5a3d241a5e 267 {
whismanoid 53:3d5a3d241a5e 268 // do nothing
whismanoid 53:3d5a3d241a5e 269 }
whismanoid 53:3d5a3d241a5e 270
whismanoid 53:3d5a3d241a5e 271 // CODE GENERATOR: spi_frequency setter definition
whismanoid 53:3d5a3d241a5e 272 /// set SPI SCLK frequency
whismanoid 53:3d5a3d241a5e 273 void MAX11043::spi_frequency(int spi_sclk_Hz)
whismanoid 53:3d5a3d241a5e 274 {
whismanoid 53:3d5a3d241a5e 275 m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid 53:3d5a3d241a5e 276 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 277 }
whismanoid 53:3d5a3d241a5e 278
whismanoid 53:3d5a3d241a5e 279 // CODE GENERATOR: omit global g_MAX11043_device
whismanoid 53:3d5a3d241a5e 280 // CODE GENERATOR: extern function declarations
whismanoid 53:3d5a3d241a5e 281 // CODE GENERATOR: extern function requirement MAX11043::SPIoutputCS
whismanoid 53:3d5a3d241a5e 282 // Assert SPI Chip Select
whismanoid 53:3d5a3d241a5e 283 // SPI chip-select for MAX11043
whismanoid 53:3d5a3d241a5e 284 //
whismanoid 62:8223a7253c90 285 inline void MAX11043::SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 286 {
whismanoid 53:3d5a3d241a5e 287 // CODE GENERATOR: extern function definition for function SPIoutputCS
whismanoid 53:3d5a3d241a5e 288 // CODE GENERATOR: extern function definition for standard SPI interface function SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 289 m_SPI_cs_state = isLogicHigh;
whismanoid 67:5b8a495dda1c 290 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 291 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 292 }
whismanoid 53:3d5a3d241a5e 293 }
whismanoid 53:3d5a3d241a5e 294
whismanoid 62:8223a7253c90 295 // CODE GENERATOR: extern function requirement MAX11043::SPIreadWriteWithLowCS
whismanoid 62:8223a7253c90 296 // SPI read and write arbitrary number of 8-bit bytes
whismanoid 62:8223a7253c90 297 // SPI interface to MAX11043 shift mosiData into MAX11043 DIN
whismanoid 62:8223a7253c90 298 // while simultaneously capturing miso data from MAX11043 DOUT
whismanoid 62:8223a7253c90 299 //
whismanoid 62:8223a7253c90 300 int MAX11043::SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 301 {
whismanoid 62:8223a7253c90 302 // CODE GENERATOR: extern function definition for function SPIreadWriteWithLowCS
whismanoid 63:8f39d21d6157 303 // TODO1: CODE GENERATOR: extern function definition for standard SPI interface function SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 304 //size_t byteCount = 4;
whismanoid 62:8223a7253c90 305 //static char mosiData[4];
whismanoid 62:8223a7253c90 306 //static char misoData[4];
whismanoid 62:8223a7253c90 307 //
whismanoid 62:8223a7253c90 308 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 309 //~ noInterrupts();
whismanoid 62:8223a7253c90 310 //
whismanoid 62:8223a7253c90 311 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 312 //
whismanoid 67:5b8a495dda1c 313 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 314 m_cs_pin = 0;
whismanoid 67:5b8a495dda1c 315 }
whismanoid 62:8223a7253c90 316 unsigned int numBytesTransferred = m_spi.write((char*)mosiData, byteCount, (char*)misoData, byteCount);
whismanoid 67:5b8a495dda1c 317 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 318 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 319 }
whismanoid 62:8223a7253c90 320 //
whismanoid 62:8223a7253c90 321 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 322 //
whismanoid 62:8223a7253c90 323 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 324 //~ interrupts();
whismanoid 62:8223a7253c90 325 // Optional Diagnostic function to print SPI transactions
whismanoid 62:8223a7253c90 326 if (onSPIprint)
whismanoid 62:8223a7253c90 327 {
whismanoid 62:8223a7253c90 328 onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
whismanoid 62:8223a7253c90 329 }
whismanoid 62:8223a7253c90 330 return numBytesTransferred;
whismanoid 62:8223a7253c90 331 }
whismanoid 62:8223a7253c90 332
whismanoid 53:3d5a3d241a5e 333 // TODO1: CODE GENERATOR: extern function GPIOoutputSHDN alias SHDNoutputValue
whismanoid 53:3d5a3d241a5e 334 // CODE GENERATOR: extern function requirement MAX11043::SHDNoutputValue
whismanoid 58:2fea32db466b 335 // Assert MAX11043 SHDN pin : High = Shut Down, Low = Normal Operation.
whismanoid 53:3d5a3d241a5e 336 //
whismanoid 53:3d5a3d241a5e 337 void MAX11043::SHDNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 338 {
whismanoid 53:3d5a3d241a5e 339 // CODE GENERATOR: extern function definition for function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 340 // TODO1: CODE GENERATOR: extern function definition for gpio interface function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 341 // TODO1: CODE GENERATOR: gpio pin SHDN assuming member function m_SHDN_pin
whismanoid 53:3d5a3d241a5e 342 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 343 // m_SHDN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 344 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 345 m_SHDN_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 346 }
whismanoid 52:607010f0c54e 347
whismanoid 53:3d5a3d241a5e 348 // TODO1: CODE GENERATOR: extern function GPIOoutputCONVRUN alias CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 349 // CODE GENERATOR: extern function requirement MAX11043::CONVRUNoutputValue
whismanoid 58:2fea32db466b 350 // Assert MAX11043 CONVRUN pin : High = start continuous conversions on all 4 channels, Low = Idle.
whismanoid 53:3d5a3d241a5e 351 //
whismanoid 53:3d5a3d241a5e 352 void MAX11043::CONVRUNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 353 {
whismanoid 53:3d5a3d241a5e 354 // CODE GENERATOR: extern function definition for function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 355 // TODO1: CODE GENERATOR: extern function definition for gpio interface function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 356 // TODO1: CODE GENERATOR: gpio pin CONVRUN assuming member function m_CONVRUN_pin
whismanoid 53:3d5a3d241a5e 357 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 358 // m_CONVRUN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 359 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 360 m_CONVRUN_pin = isLogicHigh;
whismanoid 69:989e392cf635 361 //--------------------------------------------------
whismanoid 69:989e392cf635 362 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 363 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 364 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 365 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 366 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 367 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 368 if (m_CONVRUN_pin)
whismanoid 69:989e392cf635 369 {
whismanoid 69:989e392cf635 370 // CONVRUN was switched high, EOC# will now begin toggling
whismanoid 69:989e392cf635 371 }
whismanoid 69:989e392cf635 372 else
whismanoid 69:989e392cf635 373 {
whismanoid 69:989e392cf635 374 // CONVRUN was switched low, so wait until EOC# returns high
whismanoid 69:989e392cf635 375 #warning "MAX11043::Read_ADCabcd() Potential infinite loop if EOC pin not connected"
whismanoid 69:989e392cf635 376 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 69:989e392cf635 377 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 378 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 379 (m_EOC_pin != 1));
whismanoid 69:989e392cf635 380 futility_countdown--)
whismanoid 69:989e392cf635 381 {
whismanoid 69:989e392cf635 382 // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 69:989e392cf635 383 }
whismanoid 69:989e392cf635 384 }
whismanoid 69:989e392cf635 385 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 386 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 387 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 388 //--------------------------------------------------
whismanoid 53:3d5a3d241a5e 389 }
whismanoid 53:3d5a3d241a5e 390
whismanoid 53:3d5a3d241a5e 391 // TODO1: CODE GENERATOR: extern function GPIOoutputDACSTEP alias DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 392 // CODE GENERATOR: extern function requirement MAX11043::DACSTEPoutputValue
whismanoid 58:2fea32db466b 393 // Assert MAX11043 DACSTEP pin : High = Active, Low = Idle.
whismanoid 53:3d5a3d241a5e 394 //
whismanoid 53:3d5a3d241a5e 395 void MAX11043::DACSTEPoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 396 {
whismanoid 53:3d5a3d241a5e 397 // CODE GENERATOR: extern function definition for function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 398 // TODO1: CODE GENERATOR: extern function definition for gpio interface function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 399 // TODO1: CODE GENERATOR: gpio pin DACSTEP assuming member function m_DACSTEP_pin
whismanoid 53:3d5a3d241a5e 400 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 401 // m_DACSTEP_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 402 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 403 m_DACSTEP_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 404 }
whismanoid 53:3d5a3d241a5e 405
whismanoid 53:3d5a3d241a5e 406 // TODO1: CODE GENERATOR: extern function GPIOoutputUP_slash_DWNb alias UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 407 // CODE GENERATOR: extern function requirement MAX11043::UP_slash_DWNboutputValue
whismanoid 58:2fea32db466b 408 // Assert MAX11043 UP_slash_DWNb pin : High = Up, Low = Down.
whismanoid 53:3d5a3d241a5e 409 //
whismanoid 53:3d5a3d241a5e 410 void MAX11043::UP_slash_DWNboutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 411 {
whismanoid 53:3d5a3d241a5e 412 // CODE GENERATOR: extern function definition for function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 413 // TODO1: CODE GENERATOR: extern function definition for gpio interface function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 414 // TODO1: CODE GENERATOR: gpio pin UP_slash_DWNb assuming member function m_UP_slash_DWNb_pin
whismanoid 53:3d5a3d241a5e 415 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 416 // m_UP_slash_DWNb_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 417 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 418 m_UP_slash_DWNb_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 419 }
whismanoid 53:3d5a3d241a5e 420
whismanoid 53:3d5a3d241a5e 421 // CODE GENERATOR: extern function requirement MAX11043::EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 422 // Wait for MAX11043 EOC pin low, indicating end of conversion.
whismanoid 53:3d5a3d241a5e 423 // Required when using any of the InternalClock modes.
whismanoid 53:3d5a3d241a5e 424 //
whismanoid 53:3d5a3d241a5e 425 void MAX11043::EOCinputWaitUntilLow()
whismanoid 53:3d5a3d241a5e 426 {
whismanoid 53:3d5a3d241a5e 427 // CODE GENERATOR: extern function definition for function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 428 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 429 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 430 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 431 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 432 // TODO1: CODE GENERATOR: gpio function WaitUntilLow
whismanoid 53:3d5a3d241a5e 433 while (m_EOC_pin != 0)
whismanoid 53:3d5a3d241a5e 434 {
whismanoid 53:3d5a3d241a5e 435 // spinlock waiting for logic low pin state
whismanoid 53:3d5a3d241a5e 436 }
whismanoid 53:3d5a3d241a5e 437 }
whismanoid 53:3d5a3d241a5e 438
whismanoid 53:3d5a3d241a5e 439 // CODE GENERATOR: extern function requirement MAX11043::EOCinputValue
whismanoid 53:3d5a3d241a5e 440 // Return the status of the MAX11043 EOC pin.
whismanoid 53:3d5a3d241a5e 441 //
whismanoid 53:3d5a3d241a5e 442 int MAX11043::EOCinputValue()
whismanoid 53:3d5a3d241a5e 443 {
whismanoid 53:3d5a3d241a5e 444 // CODE GENERATOR: extern function definition for function EOCinputValue
whismanoid 53:3d5a3d241a5e 445 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputValue
whismanoid 53:3d5a3d241a5e 446 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 447 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 448 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 449 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 450 return m_EOC_pin.read();
whismanoid 53:3d5a3d241a5e 451 }
whismanoid 53:3d5a3d241a5e 452
whismanoid 53:3d5a3d241a5e 453 // CODE GENERATOR: class member function definitions
whismanoid 53:3d5a3d241a5e 454 //----------------------------------------
whismanoid 53:3d5a3d241a5e 455 // Menu item '!'
whismanoid 53:3d5a3d241a5e 456 // Initialize device
whismanoid 53:3d5a3d241a5e 457 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 458 uint8_t MAX11043::Init(void)
whismanoid 53:3d5a3d241a5e 459 {
whismanoid 53:3d5a3d241a5e 460
whismanoid 53:3d5a3d241a5e 461 //----------------------------------------
whismanoid 59:47538bcf6cda 462 // reference voltage, in Volts
whismanoid 59:47538bcf6cda 463 VRef = 2.500;
whismanoid 59:47538bcf6cda 464
whismanoid 59:47538bcf6cda 465 //----------------------------------------
whismanoid 59:47538bcf6cda 466 // shadow of register config CMD_0010_0010_d16_Rd08_Configuration
whismanoid 59:47538bcf6cda 467 config = 0x6000;
whismanoid 59:47538bcf6cda 468
whismanoid 59:47538bcf6cda 469 //----------------------------------------
whismanoid 59:47538bcf6cda 470 // shadow of register status CMD_0001_1110_d8_Rd07_Status
whismanoid 59:47538bcf6cda 471 status = 0x00;
whismanoid 53:3d5a3d241a5e 472
whismanoid 53:3d5a3d241a5e 473 //----------------------------------------
whismanoid 59:47538bcf6cda 474 // shadow of register ADCa CMD_0000_0010_d16o8_Rd00_ADCa
whismanoid 59:47538bcf6cda 475 adca = 0x0000;
whismanoid 53:3d5a3d241a5e 476
whismanoid 53:3d5a3d241a5e 477 //----------------------------------------
whismanoid 59:47538bcf6cda 478 // shadow of register ADCb CMD_0000_0110_d16o8_Rd01_ADCb
whismanoid 59:47538bcf6cda 479 adcb = 0x0000;
whismanoid 59:47538bcf6cda 480
whismanoid 59:47538bcf6cda 481 //----------------------------------------
whismanoid 59:47538bcf6cda 482 // shadow of register ADCc CMD_0000_1010_d16o8_Rd02_ADCc
whismanoid 59:47538bcf6cda 483 adcc = 0x0000;
whismanoid 59:47538bcf6cda 484
whismanoid 59:47538bcf6cda 485 //----------------------------------------
whismanoid 59:47538bcf6cda 486 // shadow of register ADCd CMD_0000_1110_d16o8_Rd03_ADCd
whismanoid 59:47538bcf6cda 487 adcd = 0x0000;
whismanoid 53:3d5a3d241a5e 488
whismanoid 53:3d5a3d241a5e 489 //----------------------------------------
whismanoid 53:3d5a3d241a5e 490 // init (based on old EV kit GUI)
whismanoid 53:3d5a3d241a5e 491 #warning "Not Implemented Yet: MAX11043::Init init..."
whismanoid 53:3d5a3d241a5e 492 // bool bOpResult = false;
whismanoid 53:3d5a3d241a5e 493 // String FWVersionString = "00";
whismanoid 53:3d5a3d241a5e 494 // bool bDemoMode = true;
whismanoid 53:3d5a3d241a5e 495 // int scan_resolution = 0;
whismanoid 53:3d5a3d241a5e 496 // int scan_channels = 0;
whismanoid 53:3d5a3d241a5e 497 // int scan_bits = 0;
whismanoid 53:3d5a3d241a5e 498 // int sampleRateFactore = 0;
whismanoid 53:3d5a3d241a5e 499 // double sampleRate = 0;
whismanoid 53:3d5a3d241a5e 500 // unsigned long banks_requested = 0;
whismanoid 53:3d5a3d241a5e 501 // bool bScanMode = 0;
whismanoid 53:3d5a3d241a5e 502
whismanoid 53:3d5a3d241a5e 503 //----------------------------------------
whismanoid 59:47538bcf6cda 504 // Device ID Validation -- not used, no device ID register
whismanoid 53:3d5a3d241a5e 505 #warning "Not Implemented Yet: MAX11043::Init Device ID Validation..."
whismanoid 53:3d5a3d241a5e 506 // const uint32_t part_id_expect = 0x000F02;
whismanoid 53:3d5a3d241a5e 507 // uint32_t part_id_readback;
whismanoid 53:3d5a3d241a5e 508 // RegRead(xxxxxxxxxxxxCMD_r001_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xddd_PART_ID, &part_id_readback);
whismanoid 53:3d5a3d241a5e 509 // if (part_id_readback != part_id_expect) return 0;
whismanoid 53:3d5a3d241a5e 510
whismanoid 53:3d5a3d241a5e 511 //----------------------------------------
whismanoid 58:2fea32db466b 512 // Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 58:2fea32db466b 513 SHDNoutputValue(0); // SHDN Inactive
whismanoid 58:2fea32db466b 514
whismanoid 58:2fea32db466b 515 //----------------------------------------
whismanoid 58:2fea32db466b 516 // Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 58:2fea32db466b 517 // CONVRUN is low.
whismanoid 58:2fea32db466b 518 CONVRUNoutputValue(0); // CONVRUN Idle
whismanoid 58:2fea32db466b 519
whismanoid 58:2fea32db466b 520 //----------------------------------------
whismanoid 58:2fea32db466b 521 // DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 58:2fea32db466b 522 // edge of the system clock.
whismanoid 58:2fea32db466b 523 DACSTEPoutputValue(0); // DACSTEP Idle
whismanoid 58:2fea32db466b 524
whismanoid 58:2fea32db466b 525 //----------------------------------------
whismanoid 58:2fea32db466b 526 // DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 58:2fea32db466b 527 UP_slash_DWNboutputValue(0); // UP/DWN# Down
whismanoid 58:2fea32db466b 528
whismanoid 58:2fea32db466b 529 //----------------------------------------
whismanoid 53:3d5a3d241a5e 530 // success
whismanoid 53:3d5a3d241a5e 531 return 1;
whismanoid 53:3d5a3d241a5e 532 }
whismanoid 53:3d5a3d241a5e 533
whismanoid 53:3d5a3d241a5e 534 //----------------------------------------
whismanoid 53:3d5a3d241a5e 535 // Write a MAX11043 register.
whismanoid 53:3d5a3d241a5e 536 //
whismanoid 57:1c9da8e90737 537 // CMDOP_1aaa_aaaa_ReadRegister bit is cleared 0 indicating a write operation.
whismanoid 53:3d5a3d241a5e 538 //
whismanoid 53:3d5a3d241a5e 539 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 540 //
whismanoid 53:3d5a3d241a5e 541 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 542 //
whismanoid 53:3d5a3d241a5e 543 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 544 //
whismanoid 53:3d5a3d241a5e 545 // SPI MOSI = 0aaa_aaaa_dddd_dddd
whismanoid 53:3d5a3d241a5e 546 //
whismanoid 53:3d5a3d241a5e 547 // SPI MISO = xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 548 //
whismanoid 53:3d5a3d241a5e 549 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 550 //
whismanoid 53:3d5a3d241a5e 551 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 552 //
whismanoid 53:3d5a3d241a5e 553 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 554 //
whismanoid 53:3d5a3d241a5e 555 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 556 //
whismanoid 53:3d5a3d241a5e 557 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 558 //
whismanoid 53:3d5a3d241a5e 559 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 560 //
whismanoid 53:3d5a3d241a5e 561 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 562 //
whismanoid 53:3d5a3d241a5e 563 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 564 //
whismanoid 53:3d5a3d241a5e 565 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 566 uint8_t MAX11043::RegWrite(MAX11043_CMD_enum_t commandByte, uint32_t regData)
whismanoid 53:3d5a3d241a5e 567 {
whismanoid 53:3d5a3d241a5e 568
whismanoid 53:3d5a3d241a5e 569 //----------------------------------------
whismanoid 53:3d5a3d241a5e 570 // switch based on register address szie RegSize(commandByte)
whismanoid 57:1c9da8e90737 571 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 572 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 573 {
whismanoid 53:3d5a3d241a5e 574 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 575 {
whismanoid 63:8f39d21d6157 576 // SPI 8+8 = 16-bit transfer
whismanoid 63:8f39d21d6157 577 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 578 // SPI MOSI = 0aaa_aaaa_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 579 // SPI MISO = xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 580 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 581 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 582 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 583 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 584 mosiData[1] = regData;
whismanoid 63:8f39d21d6157 585 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 586 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 587 // TODO: cache CMD_0101_0100_d8_Wr15_FilterCAddress
whismanoid 63:8f39d21d6157 588 // if (commandByte == CMD_0101_0100_d8_Wr15_FilterCAddress) {
whismanoid 63:8f39d21d6157 589 // FilterCAddress = regData;
whismanoid 63:8f39d21d6157 590 // }
whismanoid 63:8f39d21d6157 591 // TODO: cache CMD_0110_0000_d8_Wr18_FlashMode
whismanoid 63:8f39d21d6157 592 // if (commandByte == CMD_0110_0000_d8_Wr18_FlashMode) {
whismanoid 63:8f39d21d6157 593 // FlashMode = regData;
whismanoid 63:8f39d21d6157 594 // }
whismanoid 53:3d5a3d241a5e 595 }
whismanoid 53:3d5a3d241a5e 596 break;
whismanoid 53:3d5a3d241a5e 597 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 598 #warning "Not Verified Yet: MAX11043::RegWrite 16-bit"
whismanoid 53:3d5a3d241a5e 599 {
whismanoid 63:8f39d21d6157 600 // SPI 8+16 = 24-bit transfer
whismanoid 63:8f39d21d6157 601 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 63:8f39d21d6157 602 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 603 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 604 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 605 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 606 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 607 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 608 mosiData[1] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 609 mosiData[2] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 610 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 611 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 612 // cache CMD_0010_0000_d16_Wr08_Configuration
whismanoid 63:8f39d21d6157 613 if (commandByte == CMD_0010_0000_d16_Wr08_Configuration) {
whismanoid 63:8f39d21d6157 614 config = regData;
whismanoid 63:8f39d21d6157 615 }
whismanoid 63:8f39d21d6157 616 // TODO: cache CMD_0010_0100_d16_Wr09_DAC
whismanoid 63:8f39d21d6157 617 // TODO: cache CMD_0010_1000_d16_Wr0A_DACStep
whismanoid 63:8f39d21d6157 618 // TODO: cache CMD_0010_1100_d16_Wr0B_DACHDACL
whismanoid 63:8f39d21d6157 619 // TODO: cache CMD_0011_0000_d16_Wr0C_ConfigA
whismanoid 63:8f39d21d6157 620 // TODO: cache CMD_0011_0100_d16_Wr0D_ConfigB
whismanoid 63:8f39d21d6157 621 // TODO: cache CMD_0011_1000_d16_Wr0E_ConfigC
whismanoid 63:8f39d21d6157 622 // TODO: cache CMD_0011_1100_d16_Wr0F_ConfigD
whismanoid 63:8f39d21d6157 623 // TODO: cache CMD_0100_0000_d16_Wr10_Reference
whismanoid 63:8f39d21d6157 624 // TODO: cache CMD_0100_0100_d16_Wr11_AGain
whismanoid 63:8f39d21d6157 625 // TODO: cache CMD_0100_1000_d16_Wr12_BGain
whismanoid 63:8f39d21d6157 626 // TODO: cache CMD_0100_1100_d16_Wr13_CGain
whismanoid 63:8f39d21d6157 627 // TODO: cache CMD_0101_0000_d16_Wr14_DGain
whismanoid 63:8f39d21d6157 628 // TODO: cache CMD_0110_0100_d16_Wr19_FlashAddr
whismanoid 63:8f39d21d6157 629 // TODO: cache CMD_0110_1000_d16_Wr1A_FlashDataIn
whismanoid 53:3d5a3d241a5e 630 }
whismanoid 53:3d5a3d241a5e 631 break;
whismanoid 63:8f39d21d6157 632 case 32: // 32-bit register size
whismanoid 63:8f39d21d6157 633 #warning "Not Verified Yet: MAX11043::RegWrite 32-bit"
whismanoid 53:3d5a3d241a5e 634 {
whismanoid 63:8f39d21d6157 635 // SPI 8+32 = 40-bit transfer
whismanoid 63:8f39d21d6157 636 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 63:8f39d21d6157 637 // SPI MOSI = 1aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 638 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 639 //
whismanoid 63:8f39d21d6157 640 size_t byteCount = 1 + (2 * 2);
whismanoid 63:8f39d21d6157 641 uint8_t mosiData[5];
whismanoid 63:8f39d21d6157 642 uint8_t misoData[5];
whismanoid 63:8f39d21d6157 643 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 644 mosiData[1] = (uint8_t)((regData >> 24) & 0xFF);
whismanoid 63:8f39d21d6157 645 mosiData[2] = (uint8_t)((regData >> 16) & 0xFF);
whismanoid 63:8f39d21d6157 646 mosiData[3] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 647 mosiData[4] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 648 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 649 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 650 // TODO: cache CMD_0101_1000_d32_Wr16_FilterCDataOut
whismanoid 63:8f39d21d6157 651 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 652 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 653 // }
whismanoid 63:8f39d21d6157 654 // TODO: cache CMD_0101_1100_d32_Wr17_FilterCDataIn
whismanoid 63:8f39d21d6157 655 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 656 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 657 // }
whismanoid 53:3d5a3d241a5e 658 }
whismanoid 53:3d5a3d241a5e 659 break;
whismanoid 53:3d5a3d241a5e 660 }
whismanoid 53:3d5a3d241a5e 661
whismanoid 53:3d5a3d241a5e 662 //----------------------------------------
whismanoid 53:3d5a3d241a5e 663 // success
whismanoid 53:3d5a3d241a5e 664 return 1;
whismanoid 53:3d5a3d241a5e 665 }
whismanoid 53:3d5a3d241a5e 666
whismanoid 53:3d5a3d241a5e 667 //----------------------------------------
whismanoid 53:3d5a3d241a5e 668 // Read an 8-bit MAX11043 register
whismanoid 53:3d5a3d241a5e 669 //
whismanoid 57:1c9da8e90737 670 // CMDOP_1aaa_aaaa_ReadRegister bit is set 1 indicating a read operation.
whismanoid 53:3d5a3d241a5e 671 //
whismanoid 53:3d5a3d241a5e 672 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 673 //
whismanoid 53:3d5a3d241a5e 674 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 675 //
whismanoid 53:3d5a3d241a5e 676 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 677 //
whismanoid 53:3d5a3d241a5e 678 // SPI MOSI = 1aaa_aaaa_0000_0000
whismanoid 53:3d5a3d241a5e 679 //
whismanoid 53:3d5a3d241a5e 680 // SPI MISO = xxxx_xxxx_dddd_dddd
whismanoid 53:3d5a3d241a5e 681 //
whismanoid 53:3d5a3d241a5e 682 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 683 //
whismanoid 53:3d5a3d241a5e 684 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 685 //
whismanoid 53:3d5a3d241a5e 686 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 687 //
whismanoid 53:3d5a3d241a5e 688 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 689 //
whismanoid 53:3d5a3d241a5e 690 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 691 //
whismanoid 53:3d5a3d241a5e 692 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 693 //
whismanoid 53:3d5a3d241a5e 694 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 695 //
whismanoid 53:3d5a3d241a5e 696 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 697 //
whismanoid 53:3d5a3d241a5e 698 //
whismanoid 53:3d5a3d241a5e 699 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 700 uint8_t MAX11043::RegRead(MAX11043_CMD_enum_t commandByte, uint32_t* ptrRegData)
whismanoid 53:3d5a3d241a5e 701 {
whismanoid 53:3d5a3d241a5e 702
whismanoid 53:3d5a3d241a5e 703 //----------------------------------------
whismanoid 53:3d5a3d241a5e 704 // switch based on register address szie RegSize(regAddress)
whismanoid 57:1c9da8e90737 705 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 706 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 707 {
whismanoid 53:3d5a3d241a5e 708 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 709 {
whismanoid 60:d1d1eaa90fb7 710 // SPI 8+8 = 16-bit transfer
whismanoid 62:8223a7253c90 711 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 712 // SPI MOSI = 1aaa_aaaa_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 713 // SPI MISO = xxxx_xxxx_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 714 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 715 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 716 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 717 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 718 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 719 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 720 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 721 if (ptrRegData) { (*ptrRegData) = misoData[1]; }
whismanoid 59:47538bcf6cda 722 if (commandByte == CMD_0001_1110_d8_Rd07_Status) {
whismanoid 59:47538bcf6cda 723 // TODO1: update status
whismanoid 63:8f39d21d6157 724 status = misoData[1];
whismanoid 59:47538bcf6cda 725 }
whismanoid 53:3d5a3d241a5e 726 }
whismanoid 53:3d5a3d241a5e 727 break;
whismanoid 53:3d5a3d241a5e 728 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 729 #warning "Not Verified Yet: MAX11043::RegRead 16-bit"
whismanoid 53:3d5a3d241a5e 730 {
whismanoid 60:d1d1eaa90fb7 731 // SPI 8+16 = 24-bit transfer
whismanoid 62:8223a7253c90 732 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 60:d1d1eaa90fb7 733 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 734 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 735 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 736 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 737 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 738 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 739 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 740 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 741 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 742 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 743 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 59:47538bcf6cda 744 if (commandByte == CMD_0010_0010_d16_Rd08_Configuration) {
whismanoid 59:47538bcf6cda 745 // TODO1: update config
whismanoid 63:8f39d21d6157 746 config = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 747 }
whismanoid 59:47538bcf6cda 748 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 749 // TODO1: update adca
whismanoid 63:8f39d21d6157 750 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 751 }
whismanoid 59:47538bcf6cda 752 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 753 // TODO1: update adcb
whismanoid 63:8f39d21d6157 754 adcb = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 755 }
whismanoid 59:47538bcf6cda 756 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 757 // TODO1: update adcc
whismanoid 63:8f39d21d6157 758 adcc = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 759 }
whismanoid 59:47538bcf6cda 760 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 761 // TODO1: update adcd
whismanoid 63:8f39d21d6157 762 adcd = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 763 }
whismanoid 53:3d5a3d241a5e 764 }
whismanoid 53:3d5a3d241a5e 765 break;
whismanoid 53:3d5a3d241a5e 766 case 24: // 24-bit register size
whismanoid 53:3d5a3d241a5e 767 {
whismanoid 60:d1d1eaa90fb7 768 // SPI 8+24 = 32-bit transfer
whismanoid 62:8223a7253c90 769 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32
whismanoid 63:8f39d21d6157 770 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 771 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 772 size_t byteCount = 1 + 3;
whismanoid 63:8f39d21d6157 773 uint8_t mosiData[4];
whismanoid 63:8f39d21d6157 774 uint8_t misoData[4];
whismanoid 63:8f39d21d6157 775 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 776 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 777 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 778 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 779 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 780 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 781 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 59:47538bcf6cda 782 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 783 // TODO1: update adca
whismanoid 63:8f39d21d6157 784 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 785 }
whismanoid 59:47538bcf6cda 786 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 787 // TODO1: update adcb
whismanoid 63:8f39d21d6157 788 adcb = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 789 }
whismanoid 59:47538bcf6cda 790 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 791 // TODO1: update adcc
whismanoid 63:8f39d21d6157 792 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 793 }
whismanoid 59:47538bcf6cda 794 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 795 // TODO1: update adcd
whismanoid 63:8f39d21d6157 796 adcd = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 797 }
whismanoid 59:47538bcf6cda 798 }
whismanoid 59:47538bcf6cda 799 break;
whismanoid 63:8f39d21d6157 800 case 32: // 32-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 801 //
whismanoid 63:8f39d21d6157 802 #warning "Not Implemented Yet: MAX11043::RegRead 32-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 803 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 804 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 805 // update adca, adcb
whismanoid 59:47538bcf6cda 806 //
whismanoid 63:8f39d21d6157 807 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 808 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 809 // update adcc, adcd
whismanoid 59:47538bcf6cda 810 //
whismanoid 59:47538bcf6cda 811 {
whismanoid 60:d1d1eaa90fb7 812 // SPI 8+32 = 40-bit transfer
whismanoid 62:8223a7253c90 813 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 60:d1d1eaa90fb7 814 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 815 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 816 size_t byteCount = 1 + (2 * 2);
whismanoid 62:8223a7253c90 817 uint8_t mosiData[5];
whismanoid 62:8223a7253c90 818 uint8_t misoData[5];
whismanoid 62:8223a7253c90 819 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 820 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 821 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 822 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 823 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 824 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 825 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 826 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 827 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 828 // TODO1: update adca
whismanoid 62:8223a7253c90 829 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 830 // TODO1: update adcb
whismanoid 62:8223a7253c90 831 adcb = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 832 }
whismanoid 63:8f39d21d6157 833 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 834 // TODO1: update adcc
whismanoid 62:8223a7253c90 835 adcc = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 836 // TODO1: update adcd
whismanoid 62:8223a7253c90 837 adcd = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 838 }
whismanoid 59:47538bcf6cda 839 }
whismanoid 59:47538bcf6cda 840 break;
whismanoid 63:8f39d21d6157 841 case 48: // 48-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 842 //
whismanoid 63:8f39d21d6157 843 #warning "Not Verified Yet: MAX11043::RegRead 48-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 844 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 845 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 846 // update adca, adcb
whismanoid 59:47538bcf6cda 847 //
whismanoid 63:8f39d21d6157 848 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 849 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 850 // update adcc, adcd
whismanoid 59:47538bcf6cda 851 //
whismanoid 59:47538bcf6cda 852 {
whismanoid 60:d1d1eaa90fb7 853 // SPI 8+48 = 56-bit transfer
whismanoid 62:8223a7253c90 854 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56
whismanoid 60:d1d1eaa90fb7 855 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 856 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 857 size_t byteCount = 1 + (3 * 2);
whismanoid 62:8223a7253c90 858 uint8_t mosiData[7];
whismanoid 62:8223a7253c90 859 uint8_t misoData[7];
whismanoid 62:8223a7253c90 860 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 861 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 862 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 863 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 864 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 865 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 866 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 867 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 868 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 869 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 870 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 871 // TODO1: update adca
whismanoid 62:8223a7253c90 872 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 873 // TODO1: update adcb
whismanoid 62:8223a7253c90 874 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 875 }
whismanoid 63:8f39d21d6157 876 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 877 // TODO1: update adcc
whismanoid 62:8223a7253c90 878 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 879 // TODO1: update adcd
whismanoid 62:8223a7253c90 880 adcd = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 881 }
whismanoid 59:47538bcf6cda 882 }
whismanoid 59:47538bcf6cda 883 break;
whismanoid 63:8f39d21d6157 884 case 64: // 64-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 885 //
whismanoid 63:8f39d21d6157 886 #warning "Not Verified Yet: MAX11043::RegRead 64-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 887 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 888 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 889 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 890 //
whismanoid 59:47538bcf6cda 891 {
whismanoid 60:d1d1eaa90fb7 892 // SPI 8+64 = 72-bit transfer
whismanoid 62:8223a7253c90 893 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72
whismanoid 60:d1d1eaa90fb7 894 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 895 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 896 size_t byteCount = 1 + (2 * 4);
whismanoid 62:8223a7253c90 897 uint8_t mosiData[9];
whismanoid 62:8223a7253c90 898 uint8_t misoData[9];
whismanoid 62:8223a7253c90 899 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 900 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 901 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 902 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 903 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 904 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 905 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 906 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 907 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 908 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 909 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 910 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 911 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 912 // TODO1: update adca
whismanoid 62:8223a7253c90 913 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 914 // TODO1: update adcb
whismanoid 62:8223a7253c90 915 adcb = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 916 // TODO1: update adcc
whismanoid 62:8223a7253c90 917 adcc = (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 918 // TODO1: update adcd
whismanoid 62:8223a7253c90 919 adcd = (misoData[7] << 8) | misoData[8];
whismanoid 59:47538bcf6cda 920 }
whismanoid 59:47538bcf6cda 921 }
whismanoid 59:47538bcf6cda 922 break;
whismanoid 63:8f39d21d6157 923 case 96: // 96-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 924 //
whismanoid 63:8f39d21d6157 925 #warning "Not Verified Yet: MAX11043::RegRead 96-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 926 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 927 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 928 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 929 //
whismanoid 59:47538bcf6cda 930 {
whismanoid 60:d1d1eaa90fb7 931 // SPI 8+96 = 104-bit transfer
whismanoid 62:8223a7253c90 932 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72 ___[9]_80 __[10]_88 __[11]_96 __[12]104
whismanoid 60:d1d1eaa90fb7 933 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 934 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 935 size_t byteCount = 1 + (3 * 4);
whismanoid 62:8223a7253c90 936 uint8_t mosiData[13];
whismanoid 62:8223a7253c90 937 uint8_t misoData[13];
whismanoid 62:8223a7253c90 938 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 939 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 940 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 941 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 942 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 943 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 944 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 945 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 946 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 947 mosiData[9] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 948 mosiData[10] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 949 mosiData[11] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 950 mosiData[12] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 951 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 952 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 953 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 954 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 955 // TODO1: update adca
whismanoid 62:8223a7253c90 956 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 957 // TODO1: update adcb
whismanoid 62:8223a7253c90 958 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 959 // TODO1: update adcc
whismanoid 62:8223a7253c90 960 adcc = (misoData[7] << 16) | (misoData[8] << 8) | misoData[9];
whismanoid 59:47538bcf6cda 961 // TODO1: update adcd
whismanoid 62:8223a7253c90 962 adcd = (misoData[10] << 16) | (misoData[11] << 8) | misoData[12];
whismanoid 59:47538bcf6cda 963 }
whismanoid 53:3d5a3d241a5e 964 }
whismanoid 53:3d5a3d241a5e 965 break;
whismanoid 53:3d5a3d241a5e 966 }
whismanoid 53:3d5a3d241a5e 967
whismanoid 53:3d5a3d241a5e 968 //----------------------------------------
whismanoid 53:3d5a3d241a5e 969 // success
whismanoid 53:3d5a3d241a5e 970 return 1;
whismanoid 53:3d5a3d241a5e 971 }
whismanoid 53:3d5a3d241a5e 972
whismanoid 53:3d5a3d241a5e 973 //----------------------------------------
whismanoid 53:3d5a3d241a5e 974 // Return the size of a MAX11043 register
whismanoid 53:3d5a3d241a5e 975 //
whismanoid 53:3d5a3d241a5e 976 // @return 8 for 8-bit, 16 for 16-bit, 24 for 24-bit, else 0 for undefined register size
whismanoid 53:3d5a3d241a5e 977 uint8_t MAX11043::RegSize(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 978 {
whismanoid 53:3d5a3d241a5e 979
whismanoid 53:3d5a3d241a5e 980 //----------------------------------------
whismanoid 53:3d5a3d241a5e 981 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 982 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 983 switch(commandByte)
whismanoid 53:3d5a3d241a5e 984 {
whismanoid 53:3d5a3d241a5e 985 default:
whismanoid 57:1c9da8e90737 986 // case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 987 // case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 988 // case CMDOP_1111_1111_NoOperationMOSIidleHigh:
whismanoid 53:3d5a3d241a5e 989 return 0; // undefined register size
whismanoid 53:3d5a3d241a5e 990 case CMD_0001_1110_d8_Rd07_Status:
whismanoid 53:3d5a3d241a5e 991 case CMD_0101_0100_d8_Wr15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 992 case CMD_0101_0110_d8_Rd15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 993 case CMD_0110_0000_d8_Wr18_FlashMode:
whismanoid 53:3d5a3d241a5e 994 case CMD_0110_0010_d8_Rd18_FlashMode:
whismanoid 53:3d5a3d241a5e 995 return 8; // 8-bit register size
whismanoid 53:3d5a3d241a5e 996 case CMD_0010_0000_d16_Wr08_Configuration:
whismanoid 53:3d5a3d241a5e 997 case CMD_0010_0010_d16_Rd08_Configuration:
whismanoid 53:3d5a3d241a5e 998 case CMD_0010_0100_d16_Wr09_DAC:
whismanoid 53:3d5a3d241a5e 999 case CMD_0010_0110_d16_Rd09_DAC:
whismanoid 53:3d5a3d241a5e 1000 case CMD_0010_1000_d16_Wr0A_DACStep:
whismanoid 53:3d5a3d241a5e 1001 case CMD_0010_1010_d16_Rd0A_DACStep:
whismanoid 53:3d5a3d241a5e 1002 case CMD_0010_1100_d16_Wr0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 1003 case CMD_0010_1110_d16_Rd0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 1004 case CMD_0011_0000_d16_Wr0C_ConfigA:
whismanoid 53:3d5a3d241a5e 1005 case CMD_0011_0010_d16_Rd0C_ConfigA:
whismanoid 53:3d5a3d241a5e 1006 case CMD_0011_0100_d16_Wr0D_ConfigB:
whismanoid 53:3d5a3d241a5e 1007 case CMD_0011_0110_d16_Rd0D_ConfigB:
whismanoid 53:3d5a3d241a5e 1008 case CMD_0011_1000_d16_Wr0E_ConfigC:
whismanoid 53:3d5a3d241a5e 1009 case CMD_0011_1010_d16_Rd0E_ConfigC:
whismanoid 53:3d5a3d241a5e 1010 case CMD_0011_1100_d16_Wr0F_ConfigD:
whismanoid 53:3d5a3d241a5e 1011 case CMD_0011_1110_d16_Rd0F_ConfigD:
whismanoid 53:3d5a3d241a5e 1012 case CMD_0100_0000_d16_Wr10_Reference:
whismanoid 53:3d5a3d241a5e 1013 case CMD_0100_0010_d16_Rd10_Reference:
whismanoid 53:3d5a3d241a5e 1014 case CMD_0100_0100_d16_Wr11_AGain:
whismanoid 53:3d5a3d241a5e 1015 case CMD_0100_0110_d16_Rd11_AGain:
whismanoid 53:3d5a3d241a5e 1016 case CMD_0100_1000_d16_Wr12_BGain:
whismanoid 53:3d5a3d241a5e 1017 case CMD_0100_1010_d16_Rd12_BGain:
whismanoid 53:3d5a3d241a5e 1018 case CMD_0100_1100_d16_Wr13_CGain:
whismanoid 53:3d5a3d241a5e 1019 case CMD_0100_1110_d16_Rd13_CGain:
whismanoid 53:3d5a3d241a5e 1020 case CMD_0101_0000_d16_Wr14_DGain:
whismanoid 53:3d5a3d241a5e 1021 case CMD_0101_0010_d16_Rd14_DGain:
whismanoid 53:3d5a3d241a5e 1022 case CMD_0110_0100_d16_Wr19_FlashAddr:
whismanoid 53:3d5a3d241a5e 1023 case CMD_0110_0110_d16_Rd19_FlashAddr:
whismanoid 53:3d5a3d241a5e 1024 case CMD_0110_1000_d16_Wr1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 1025 case CMD_0110_1010_d16_Rd1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 1026 case CMD_0110_1110_d16_Rd1B_FlashDataOut:
whismanoid 53:3d5a3d241a5e 1027 return 16; // 16-bit register size
whismanoid 59:47538bcf6cda 1028 case CMD_0000_0010_d16o8_Rd00_ADCa:
whismanoid 59:47538bcf6cda 1029 case CMD_0000_0110_d16o8_Rd01_ADCb:
whismanoid 59:47538bcf6cda 1030 case CMD_0000_1010_d16o8_Rd02_ADCc:
whismanoid 59:47538bcf6cda 1031 case CMD_0000_1110_d16o8_Rd03_ADCd:
whismanoid 59:47538bcf6cda 1032 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1033 {
whismanoid 59:47538bcf6cda 1034 // %SW 0x02 (0 0 0) -- for 24-bit read
whismanoid 59:47538bcf6cda 1035 return 24; // 24-bit register size
whismanoid 59:47538bcf6cda 1036 }
whismanoid 59:47538bcf6cda 1037 // %SW 0x02 (0 0) -- for 16-bit read
whismanoid 59:47538bcf6cda 1038 //
whismanoid 59:47538bcf6cda 1039 return 16; // 16-bit register size
whismanoid 63:8f39d21d6157 1040 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab:
whismanoid 63:8f39d21d6157 1041 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd:
whismanoid 59:47538bcf6cda 1042 //
whismanoid 59:47538bcf6cda 1043 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 1044 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1045 {
whismanoid 59:47538bcf6cda 1046 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 1047 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 1048 return 48; // 48-bit register size: 2*(24)
whismanoid 59:47538bcf6cda 1049 }
whismanoid 59:47538bcf6cda 1050 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 1051 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 1052 //
whismanoid 59:47538bcf6cda 1053 return 32; // 32-bit register size: 2*(16)
whismanoid 63:8f39d21d6157 1054 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd:
whismanoid 59:47538bcf6cda 1055 //
whismanoid 59:47538bcf6cda 1056 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 1057 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1058 {
whismanoid 59:47538bcf6cda 1059 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1060 return 96; // 96-bit register size: 4*(24)
whismanoid 59:47538bcf6cda 1061 }
whismanoid 59:47538bcf6cda 1062 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1063 //
whismanoid 59:47538bcf6cda 1064 return 64; // 64-bit register size: 4*(16)
whismanoid 53:3d5a3d241a5e 1065 case CMD_0101_1000_d32_Wr16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 1066 case CMD_0101_1010_d32_Rd16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 1067 case CMD_0101_1100_d32_Wr17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 1068 case CMD_0101_1110_d32_Rd17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 1069 return 32; // 32-bit register size
whismanoid 53:3d5a3d241a5e 1070 }
whismanoid 53:3d5a3d241a5e 1071 }
whismanoid 53:3d5a3d241a5e 1072
whismanoid 53:3d5a3d241a5e 1073 //----------------------------------------
whismanoid 57:1c9da8e90737 1074 // Decode operation from commandByte
whismanoid 57:1c9da8e90737 1075 //
whismanoid 57:1c9da8e90737 1076 // @return operation such as idle, read register, write register, etc.
whismanoid 57:1c9da8e90737 1077 MAX11043::MAX11043_CMDOP_enum_t MAX11043::DecodeCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 57:1c9da8e90737 1078 {
whismanoid 57:1c9da8e90737 1079
whismanoid 57:1c9da8e90737 1080 //----------------------------------------
whismanoid 57:1c9da8e90737 1081 // decode operation from command byte
whismanoid 57:1c9da8e90737 1082 switch (commandByte & 0x83)
whismanoid 57:1c9da8e90737 1083 {
whismanoid 57:1c9da8e90737 1084 case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 1085 return CMDOP_0aaa_aa10_ReadRegister;
whismanoid 57:1c9da8e90737 1086 case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 1087 return CMDOP_0aaa_aa00_WriteRegister;
whismanoid 57:1c9da8e90737 1088 default:
whismanoid 57:1c9da8e90737 1089 return CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 57:1c9da8e90737 1090 }
whismanoid 57:1c9da8e90737 1091 }
whismanoid 57:1c9da8e90737 1092
whismanoid 57:1c9da8e90737 1093 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1094 // Return the address field of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1095 //
whismanoid 53:3d5a3d241a5e 1096 // @return register address field as given in datasheet
whismanoid 53:3d5a3d241a5e 1097 uint8_t MAX11043::RegAddrOfCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1098 {
whismanoid 53:3d5a3d241a5e 1099
whismanoid 53:3d5a3d241a5e 1100 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1101 // extract register address value from command byte
whismanoid 57:1c9da8e90737 1102 return (uint8_t)((commandByte &~ 0x83) >> 2); // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 1103 }
whismanoid 53:3d5a3d241a5e 1104
whismanoid 53:3d5a3d241a5e 1105 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1106 // Test whether a command byte is a register read command
whismanoid 53:3d5a3d241a5e 1107 //
whismanoid 53:3d5a3d241a5e 1108 // @return true if command byte is a register read command
whismanoid 53:3d5a3d241a5e 1109 uint8_t MAX11043::IsRegReadCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1110 {
whismanoid 53:3d5a3d241a5e 1111
whismanoid 53:3d5a3d241a5e 1112 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1113 // Test whether a command byte is a register read command
whismanoid 57:1c9da8e90737 1114 return (commandByte &~ 0x02) ? 1 : 0; // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 1115 }
whismanoid 53:3d5a3d241a5e 1116
whismanoid 53:3d5a3d241a5e 1117 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1118 // Return the name of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1119 //
whismanoid 53:3d5a3d241a5e 1120 // @return null-terminated constant C string containing register name or empty string
whismanoid 53:3d5a3d241a5e 1121 const char* MAX11043::RegName(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1122 {
whismanoid 53:3d5a3d241a5e 1123
whismanoid 53:3d5a3d241a5e 1124 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1125 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 1126 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 1127 switch(commandByte)
whismanoid 53:3d5a3d241a5e 1128 {
whismanoid 53:3d5a3d241a5e 1129 default:
whismanoid 53:3d5a3d241a5e 1130 return ""; // undefined register
whismanoid 57:1c9da8e90737 1131 // case CMDOP_0aaa_aa00_WriteRegister: return "_______";
whismanoid 57:1c9da8e90737 1132 // case CMDOP_0aaa_aa10_ReadRegister: return "_______";
whismanoid 57:1c9da8e90737 1133 // case CMDOP_1111_1111_NoOperationMOSIidleHigh: return "_______";
whismanoid 59:47538bcf6cda 1134 case CMD_0000_0010_d16o8_Rd00_ADCa: return "ADCa";
whismanoid 59:47538bcf6cda 1135 case CMD_0000_0110_d16o8_Rd01_ADCb: return "ADCb";
whismanoid 59:47538bcf6cda 1136 case CMD_0000_1010_d16o8_Rd02_ADCc: return "ADCc";
whismanoid 59:47538bcf6cda 1137 case CMD_0000_1110_d16o8_Rd03_ADCd: return "ADCd";
whismanoid 63:8f39d21d6157 1138 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab: return "ADCab";
whismanoid 63:8f39d21d6157 1139 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd: return "ADCcd";
whismanoid 63:8f39d21d6157 1140 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd: return "ADCabcd";
whismanoid 53:3d5a3d241a5e 1141 case CMD_0001_1110_d8_Rd07_Status: return "Status";
whismanoid 53:3d5a3d241a5e 1142 case CMD_0010_0000_d16_Wr08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1143 case CMD_0010_0010_d16_Rd08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1144 case CMD_0010_0100_d16_Wr09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1145 case CMD_0010_0110_d16_Rd09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1146 case CMD_0010_1000_d16_Wr0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1147 case CMD_0010_1010_d16_Rd0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1148 case CMD_0010_1100_d16_Wr0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1149 case CMD_0010_1110_d16_Rd0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1150 case CMD_0011_0000_d16_Wr0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1151 case CMD_0011_0010_d16_Rd0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1152 case CMD_0011_0100_d16_Wr0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1153 case CMD_0011_0110_d16_Rd0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1154 case CMD_0011_1000_d16_Wr0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1155 case CMD_0011_1010_d16_Rd0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1156 case CMD_0011_1100_d16_Wr0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1157 case CMD_0011_1110_d16_Rd0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1158 case CMD_0100_0000_d16_Wr10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1159 case CMD_0100_0010_d16_Rd10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1160 case CMD_0100_0100_d16_Wr11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1161 case CMD_0100_0110_d16_Rd11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1162 case CMD_0100_1000_d16_Wr12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1163 case CMD_0100_1010_d16_Rd12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1164 case CMD_0100_1100_d16_Wr13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1165 case CMD_0100_1110_d16_Rd13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1166 case CMD_0101_0000_d16_Wr14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1167 case CMD_0101_0010_d16_Rd14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1168 case CMD_0101_0100_d8_Wr15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1169 case CMD_0101_0110_d8_Rd15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1170 case CMD_0101_1000_d32_Wr16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1171 case CMD_0101_1010_d32_Rd16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1172 case CMD_0101_1100_d32_Wr17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1173 case CMD_0101_1110_d32_Rd17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1174 case CMD_0110_0000_d8_Wr18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1175 case CMD_0110_0010_d8_Rd18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1176 case CMD_0110_0100_d16_Wr19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1177 case CMD_0110_0110_d16_Rd19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1178 case CMD_0110_1000_d16_Wr1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1179 case CMD_0110_1010_d16_Rd1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1180 case CMD_0110_1110_d16_Rd1B_FlashDataOut: return "FlashDataOut";
whismanoid 53:3d5a3d241a5e 1181 }
whismanoid 53:3d5a3d241a5e 1182 }
whismanoid 53:3d5a3d241a5e 1183
whismanoid 59:47538bcf6cda 1184 //----------------------------------------
whismanoid 64:a667cfd83492 1185 // Menu item '$' -> adca, adcb, adcc, adcd
whismanoid 64:a667cfd83492 1186 // Read ADCabcd
whismanoid 64:a667cfd83492 1187 //
whismanoid 64:a667cfd83492 1188 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1189 uint8_t MAX11043::Read_ADCabcd(void)
whismanoid 64:a667cfd83492 1190 {
whismanoid 64:a667cfd83492 1191
whismanoid 64:a667cfd83492 1192 //----------------------------------------
whismanoid 64:a667cfd83492 1193 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1194 #warning "Not Tested Yet: MAX11043::Read_ADCabcd..."
whismanoid 64:a667cfd83492 1195
whismanoid 69:989e392cf635 1196 //--------------------------------------------------
whismanoid 69:989e392cf635 1197 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 1198 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 1199 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 1200 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1201 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 1202 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 1203 // 2020-02-20 MAX11043_EOC_INTERRUPT_POLLING works on MAX32625MBED at 9us conversion rate, with 1us timing margin
whismanoid 69:989e392cf635 1204 // TODO: poll m_EOC_pin if CONVRUN is high
whismanoid 69:989e392cf635 1205 if (m_CONVRUN_pin)
whismanoid 69:989e392cf635 1206 {
whismanoid 69:989e392cf635 1207 #warning "MAX11043::Read_ADCabcd() Potential infinite loop if EOC pin not connected"
whismanoid 69:989e392cf635 1208 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 69:989e392cf635 1209 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 1210 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 1211 (m_EOC_pin != 1));
whismanoid 69:989e392cf635 1212 futility_countdown--)
whismanoid 69:989e392cf635 1213 {
whismanoid 69:989e392cf635 1214 // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 69:989e392cf635 1215 }
whismanoid 69:989e392cf635 1216 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 1217 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 1218 (m_EOC_pin != 0));
whismanoid 69:989e392cf635 1219 futility_countdown--)
whismanoid 69:989e392cf635 1220 {
whismanoid 69:989e392cf635 1221 // spinlock waiting for logic low pin state (new data is available)
whismanoid 69:989e392cf635 1222 }
whismanoid 69:989e392cf635 1223 }
whismanoid 69:989e392cf635 1224 else
whismanoid 69:989e392cf635 1225 {
whismanoid 69:989e392cf635 1226 // CONVRUN pin is being driven low, so conversion result will not change, EOC# remains high
whismanoid 69:989e392cf635 1227 }
whismanoid 69:989e392cf635 1228 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1229 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 1230 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1231 //--------------------------------------------------
whismanoid 69:989e392cf635 1232
whismanoid 64:a667cfd83492 1233 //----------------------------------------
whismanoid 64:a667cfd83492 1234 // read register ADCabcd -> &adca, &adcb, &adcc, &adcd
whismanoid 64:a667cfd83492 1235 RegRead(CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd, 0);
whismanoid 64:a667cfd83492 1236
whismanoid 64:a667cfd83492 1237 //----------------------------------------
whismanoid 64:a667cfd83492 1238 // success
whismanoid 64:a667cfd83492 1239 return 1;
whismanoid 64:a667cfd83492 1240 }
whismanoid 64:a667cfd83492 1241
whismanoid 64:a667cfd83492 1242 //----------------------------------------
whismanoid 66:3fe92f6f1cfa 1243 // Menu item 'GA'
whismanoid 64:a667cfd83492 1244 // Write AGain register
whismanoid 64:a667cfd83492 1245 //
whismanoid 64:a667cfd83492 1246 // @param[in] gain 2's complement, 0x800=0.25V/V, 0x1000=0.5V/V, 0x2000=1VV/V, 0x4000=2V/V, default=0x2000
whismanoid 64:a667cfd83492 1247 //
whismanoid 64:a667cfd83492 1248 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1249 uint8_t MAX11043::Write_AGain(uint32_t gain)
whismanoid 64:a667cfd83492 1250 {
whismanoid 64:a667cfd83492 1251
whismanoid 64:a667cfd83492 1252 //----------------------------------------
whismanoid 64:a667cfd83492 1253 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1254 #warning "Not Tested Yet: MAX11043::Write_AGain..."
whismanoid 64:a667cfd83492 1255
whismanoid 64:a667cfd83492 1256 //----------------------------------------
whismanoid 64:a667cfd83492 1257 // write register
whismanoid 64:a667cfd83492 1258 RegWrite(CMD_0100_0100_d16_Wr11_AGain, gain);
whismanoid 64:a667cfd83492 1259
whismanoid 64:a667cfd83492 1260 //----------------------------------------
whismanoid 64:a667cfd83492 1261 // success
whismanoid 64:a667cfd83492 1262 return 1;
whismanoid 64:a667cfd83492 1263 }
whismanoid 64:a667cfd83492 1264
whismanoid 64:a667cfd83492 1265 //----------------------------------------
whismanoid 59:47538bcf6cda 1266 // Menu item 'XX'
whismanoid 59:47538bcf6cda 1267 //
whismanoid 59:47538bcf6cda 1268 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1269 uint8_t MAX11043::Configure_XXXXX(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1270 {
whismanoid 59:47538bcf6cda 1271
whismanoid 59:47538bcf6cda 1272 //----------------------------------------
whismanoid 59:47538bcf6cda 1273 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1274 #warning "Not Tested Yet: MAX11043::Configure_XXXXX..."
whismanoid 59:47538bcf6cda 1275
whismanoid 59:47538bcf6cda 1276 //----------------------------------------
whismanoid 59:47538bcf6cda 1277 // read register
whismanoid 59:47538bcf6cda 1278 RegRead(CMD_0000_0010_d16o8_Rd00_ADCa, &adca);
whismanoid 59:47538bcf6cda 1279
whismanoid 59:47538bcf6cda 1280 //----------------------------------------
whismanoid 59:47538bcf6cda 1281 // success
whismanoid 59:47538bcf6cda 1282 return 1;
whismanoid 59:47538bcf6cda 1283 }
whismanoid 59:47538bcf6cda 1284
whismanoid 59:47538bcf6cda 1285 //----------------------------------------
whismanoid 59:47538bcf6cda 1286 // Menu item 'XY'
whismanoid 59:47538bcf6cda 1287 //
whismanoid 59:47538bcf6cda 1288 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1289 uint8_t MAX11043::Configure_XXXXY(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1290 {
whismanoid 59:47538bcf6cda 1291
whismanoid 59:47538bcf6cda 1292 //----------------------------------------
whismanoid 59:47538bcf6cda 1293 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1294 #warning "Not Tested Yet: MAX11043::Configure_XXXXY..."
whismanoid 59:47538bcf6cda 1295
whismanoid 59:47538bcf6cda 1296 //----------------------------------------
whismanoid 59:47538bcf6cda 1297 // read register
whismanoid 59:47538bcf6cda 1298 RegRead(CMD_0001_1110_d8_Rd07_Status, &status);
whismanoid 59:47538bcf6cda 1299
whismanoid 59:47538bcf6cda 1300 //----------------------------------------
whismanoid 59:47538bcf6cda 1301 // success
whismanoid 59:47538bcf6cda 1302 return 1;
whismanoid 59:47538bcf6cda 1303 }
whismanoid 59:47538bcf6cda 1304
whismanoid 53:3d5a3d241a5e 1305
whismanoid 53:3d5a3d241a5e 1306 // End of file