Mark Underwood / Mbed OS MAX11043_Serial_Tester

Test program running on MAX32625MBED. Control through USB Serial commands using a terminal emulator such as teraterm or putty.

Dependencies:   MaximTinyTester CmdLine MAX541 USBDevice

MAX11043/MAX11043.cpp@81:167dee56c45b, 2020-02-25 (annotated)

Committer:
whismanoid
Date:
Tue Feb 25 02:14:54 2020 +0000
Revision:
81:167dee56c45b
Parent:
80:96bc693e0f79
Child:
82:9ea067fad5c3
MAX11043_EOC_INTERRUPT_POLLING 1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 53:3d5a3d241a5e 1 // /*******************************************************************************
whismanoid 53:3d5a3d241a5e 2 // * Copyright (C) 2020 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 53:3d5a3d241a5e 3 // *
whismanoid 53:3d5a3d241a5e 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 53:3d5a3d241a5e 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 53:3d5a3d241a5e 6 // * to deal in the Software without restriction, including without limitation
whismanoid 53:3d5a3d241a5e 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 53:3d5a3d241a5e 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 53:3d5a3d241a5e 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 53:3d5a3d241a5e 10 // *
whismanoid 53:3d5a3d241a5e 11 // * The above copyright notice and this permission notice shall be included
whismanoid 53:3d5a3d241a5e 12 // * in all copies or substantial portions of the Software.
whismanoid 53:3d5a3d241a5e 13 // *
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whismanoid 53:3d5a3d241a5e 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 53:3d5a3d241a5e 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 53:3d5a3d241a5e 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 53:3d5a3d241a5e 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 53:3d5a3d241a5e 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 53:3d5a3d241a5e 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 53:3d5a3d241a5e 21 // *
whismanoid 53:3d5a3d241a5e 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 53:3d5a3d241a5e 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 53:3d5a3d241a5e 24 // * Products, Inc. Branding Policy.
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whismanoid 53:3d5a3d241a5e 26 // * The mere transfer of this software does not imply any licenses
whismanoid 53:3d5a3d241a5e 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 53:3d5a3d241a5e 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 53:3d5a3d241a5e 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 53:3d5a3d241a5e 30 // * ownership rights.
whismanoid 53:3d5a3d241a5e 31 // *******************************************************************************
whismanoid 53:3d5a3d241a5e 32 // */
whismanoid 53:3d5a3d241a5e 33 // *********************************************************************
whismanoid 53:3d5a3d241a5e 34 // @file MAX11043.cpp
whismanoid 53:3d5a3d241a5e 35 // *********************************************************************
whismanoid 53:3d5a3d241a5e 36 // Device Driver file
whismanoid 53:3d5a3d241a5e 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid 53:3d5a3d241a5e 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 53:3d5a3d241a5e 39 // System Name = ExampleSystem
whismanoid 53:3d5a3d241a5e 40 // System Description = Device driver example
whismanoid 53:3d5a3d241a5e 41
whismanoid 53:3d5a3d241a5e 42 #include "MAX11043.h"
whismanoid 69:989e392cf635 43 //--------------------------------------------------
whismanoid 69:989e392cf635 44 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 45 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 46 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 47 #ifndef MAX11043_EOC_INTERRUPT_POLLING
whismanoid 81:167dee56c45b 48 #define MAX11043_EOC_INTERRUPT_POLLING 1
whismanoid 69:989e392cf635 49 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 73:879578472009 50 //--------------------------------------------------
whismanoid 76:0397493d7baf 51 // SPI is not interrupt-safe, so use EventQueue to defer execution to user context.
whismanoid 76:0397493d7baf 52 #ifndef MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 53 #define MAX11043_EOC_INTERRUPT_EVENTQUEUE 1
whismanoid 76:0397493d7baf 54 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 55 #if MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 56 #else // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 57 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 58 #if MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 59 // SPI is not interrupt-safe, so use EventQueue to defer execution to user context.
whismanoid 76:0397493d7baf 60 #include "mbed_events.h"
whismanoid 76:0397493d7baf 61 #define MYONEOCTHREADEVENTFLAG_ENABLE_SPI (1UL << 0)
whismanoid 76:0397493d7baf 62 EventFlags myOnEOCThread_event_flags;
whismanoid 76:0397493d7baf 63 Thread myOnEOCThread;
whismanoid 76:0397493d7baf 64 extern void myOnEOCThread_handler();
whismanoid 76:0397493d7baf 65 #else // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 66 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 67 //--------------------------------------------------
whismanoid 73:879578472009 68 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 73:879578472009 69 #ifndef MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 70 #define MAX11043_ScopeTrigger_MAX32625MBED_D5 1
whismanoid 73:879578472009 71 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 72 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 73 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 73:879578472009 74 // WIP MAX11043 interrupt EOC echo - moving DigitalOut ScopeTrigger to global scope, it compiles but there is no activity on scope
whismanoid 74:f4f969c9a7a9 75 extern DigitalInOut digitalInOut5; // declared in Test_Main_MAX11043.cpp (D5, PIN_INPUT, PullUp, 1)
whismanoid 75:0900a57f2e5d 76 const size_t byteCount_onEOCFallingEdge = 1 + (2 * 4);
whismanoid 75:0900a57f2e5d 77 const uint8_t mosiData_onEOCFallingEdge[9] = {
whismanoid 75:0900a57f2e5d 78 MAX11043::CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd,
whismanoid 75:0900a57f2e5d 79 0, 0, 0, 0, 0, 0, 0, 0
whismanoid 75:0900a57f2e5d 80 };
whismanoid 75:0900a57f2e5d 81 uint8_t misoData_onEOCFallingEdge[9];
whismanoid 73:879578472009 82 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 53:3d5a3d241a5e 83
whismanoid 53:3d5a3d241a5e 84 // Device Name = MAX11043
whismanoid 53:3d5a3d241a5e 85 // Device Description = 200ksps, Low-Power, Serial SPI 24-Bit, 4-Channel, Differential/Single-Ended Input, Simultaneous-Sampling SD ADC
whismanoid 53:3d5a3d241a5e 86 // Device DeviceBriefDescription = 24-bit 200ksps Delta-Sigma ADC
whismanoid 53:3d5a3d241a5e 87 // Device Manufacturer = Maxim Integrated
whismanoid 53:3d5a3d241a5e 88 // Device PartNumber = MAX11043ATL+
whismanoid 53:3d5a3d241a5e 89 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 53:3d5a3d241a5e 90 //
whismanoid 53:3d5a3d241a5e 91 // ADC MaxOutputDataRate = 200ksps
whismanoid 53:3d5a3d241a5e 92 // ADC NumChannels = 4
whismanoid 53:3d5a3d241a5e 93 // ADC ResolutionBits = 24
whismanoid 53:3d5a3d241a5e 94 //
whismanoid 53:3d5a3d241a5e 95 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 96 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 97 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 98 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 99 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 100 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 101 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 102 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 103 //
whismanoid 53:3d5a3d241a5e 104 // InputPin Name = CONVRUN
whismanoid 53:3d5a3d241a5e 105 // InputPin Description = CONVRUN (digital input). Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 53:3d5a3d241a5e 106 // CONVRUN is low.
whismanoid 53:3d5a3d241a5e 107 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 108 //
whismanoid 53:3d5a3d241a5e 109 // InputPin Name = SHDN
whismanoid 53:3d5a3d241a5e 110 // InputPin Description = Shutdown (digital input). Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 53:3d5a3d241a5e 111 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 112 //
whismanoid 53:3d5a3d241a5e 113 // InputPin Name = DACSTEP
whismanoid 53:3d5a3d241a5e 114 // InputPin Description = DACSTEP (digital input). DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 53:3d5a3d241a5e 115 // edge of the system clock.
whismanoid 53:3d5a3d241a5e 116 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 117 //
whismanoid 53:3d5a3d241a5e 118 // InputPin Name = UP/DWN#
whismanoid 53:3d5a3d241a5e 119 // InputPin Description = UP/DWN# (digital input). DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 53:3d5a3d241a5e 120 // InputPin Function = Configuration
whismanoid 53:3d5a3d241a5e 121 //
whismanoid 53:3d5a3d241a5e 122 // OutputPin Name = EOC
whismanoid 53:3d5a3d241a5e 123 // OutputPin Description = End of Conversion Output. Active-Low End-of-Conversion Indicator. EOC asserts low to indicate that new data is ready.
whismanoid 53:3d5a3d241a5e 124 // OutputPin Function = Event
whismanoid 53:3d5a3d241a5e 125 //
whismanoid 58:2fea32db466b 126 // SupplyPin Name = AVDD
whismanoid 58:2fea32db466b 127 // SupplyPin Description = Analog Power-Supply Input. Bypass each AVDD with a nominal 1uF capacitor to AGND.
whismanoid 58:2fea32db466b 128 // SupplyPin VinMax = 3.60
whismanoid 58:2fea32db466b 129 // SupplyPin VinMin = 3.00
whismanoid 58:2fea32db466b 130 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 131 //
whismanoid 58:2fea32db466b 132 // SupplyPin Name = AGND
whismanoid 58:2fea32db466b 133 // SupplyPin Description = Analog Ground. Connect all AGND inputs together.
whismanoid 58:2fea32db466b 134 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 135 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 136 // SupplyPin Function = Analog
whismanoid 58:2fea32db466b 137 //
whismanoid 58:2fea32db466b 138 // SupplyPin Name = DGND
whismanoid 58:2fea32db466b 139 // SupplyPin Description = Digital Ground. Connect all DGND inputs together.
whismanoid 58:2fea32db466b 140 // SupplyPin VinMax = 0
whismanoid 58:2fea32db466b 141 // SupplyPin VinMin = 0
whismanoid 58:2fea32db466b 142 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 143 //
whismanoid 58:2fea32db466b 144 // SupplyPin Name = DVDD
whismanoid 58:2fea32db466b 145 // SupplyPin Description = Digital Power-Supply Input. Bypass each DVDD with a nominal 1uF capacitor to DGND.
whismanoid 58:2fea32db466b 146 // SupplyPin VinMax = 3.60 (*TODO PENDING VERIFICATION*)
whismanoid 58:2fea32db466b 147 // SupplyPin VinMin = 3.00 (*TODO PENDING VERIFICATION*)
whismanoid 58:2fea32db466b 148 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 149 //
whismanoid 58:2fea32db466b 150 // SupplyPin Name = DVREG
whismanoid 58:2fea32db466b 151 // SupplyPin Description = Regulated Digital Core Supply (from internal +2.5V regulator). Bypass DVREG to DGND with a 10uF capacitor.
whismanoid 58:2fea32db466b 152 // SupplyPin VinMax = 2.50
whismanoid 58:2fea32db466b 153 // SupplyPin VinMin = 2.50
whismanoid 58:2fea32db466b 154 // SupplyPin Function = Digital
whismanoid 58:2fea32db466b 155 //
whismanoid 53:3d5a3d241a5e 156
whismanoid 53:3d5a3d241a5e 157 // CODE GENERATOR: class constructor definition
whismanoid 53:3d5a3d241a5e 158 MAX11043::MAX11043(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 53:3d5a3d241a5e 159 // CODE GENERATOR: class constructor definition gpio InputPin pins
whismanoid 53:3d5a3d241a5e 160 DigitalOut &CONVRUN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 161 DigitalOut &SHDN_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 162 DigitalOut &DACSTEP_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 163 DigitalOut &UP_slash_DWNb_pin, // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 164 // CODE GENERATOR: class constructor definition gpio OutputPin pins
whismanoid 69:989e392cf635 165 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 166 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 167 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 168 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 169 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 53:3d5a3d241a5e 170 DigitalIn &EOC_pin, // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 171 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 172 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 173 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 69:989e392cf635 174 InterruptIn &EOC_pin, // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 175 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 176 // CODE GENERATOR: class constructor definition ic_variant
whismanoid 53:3d5a3d241a5e 177 MAX11043_ic_t ic_variant)
whismanoid 53:3d5a3d241a5e 178 // CODE GENERATOR: class constructor initializer list
whismanoid 53:3d5a3d241a5e 179 : m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid 53:3d5a3d241a5e 180 // CODE GENERATOR: class constructor initializer list gpio InputPin pins
whismanoid 53:3d5a3d241a5e 181 m_CONVRUN_pin(CONVRUN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 182 m_SHDN_pin(SHDN_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 183 m_DACSTEP_pin(DACSTEP_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 184 m_UP_slash_DWNb_pin(UP_slash_DWNb_pin), // Digital Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 185 // CODE GENERATOR: class constructor initializer list gpio OutputPin pins
whismanoid 69:989e392cf635 186 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 187 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 188 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 189 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 53:3d5a3d241a5e 190 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 191 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 192 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 70:f44a577c9e59 193 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11043 device
whismanoid 69:989e392cf635 194 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 53:3d5a3d241a5e 195 // CODE GENERATOR: class constructor initializer list ic_variant
whismanoid 53:3d5a3d241a5e 196 m_ic_variant(ic_variant)
whismanoid 53:3d5a3d241a5e 197 {
whismanoid 53:3d5a3d241a5e 198 // CODE GENERATOR: class constructor definition SPI interface initialization
whismanoid 53:3d5a3d241a5e 199 //
whismanoid 53:3d5a3d241a5e 200 // SPI CS = ActiveLow
whismanoid 53:3d5a3d241a5e 201 // SPI FrameStart = CS
whismanoid 53:3d5a3d241a5e 202 m_SPI_cs_state = 1;
whismanoid 67:5b8a495dda1c 203 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 204 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 205 }
whismanoid 53:3d5a3d241a5e 206
whismanoid 53:3d5a3d241a5e 207 // SPI CPOL = 0
whismanoid 53:3d5a3d241a5e 208 // SPI CPHA = 0
whismanoid 53:3d5a3d241a5e 209 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 53:3d5a3d241a5e 210 // SPI SCLK Idle Low
whismanoid 53:3d5a3d241a5e 211 m_SPI_dataMode = 0; //SPI_MODE0; // CPOL=0,CPHA=0: Rising Edge stable; SCLK idle Low
whismanoid 53:3d5a3d241a5e 212 m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid 53:3d5a3d241a5e 213
whismanoid 53:3d5a3d241a5e 214 // SPI SCLKMaxMHz = 40
whismanoid 53:3d5a3d241a5e 215 // SPI SCLKMinMHz = 0
whismanoid 53:3d5a3d241a5e 216 //#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid 53:3d5a3d241a5e 217 //#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid 53:3d5a3d241a5e 218 //#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid 53:3d5a3d241a5e 219 //#define SPI_SCLK_Hz 6000000 // 6MHz
whismanoid 53:3d5a3d241a5e 220 //#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid 53:3d5a3d241a5e 221 //#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid 53:3d5a3d241a5e 222 //#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid 61:b4f3051578ef 223 m_SPI_SCLK_Hz = 24000000; // platform limit 24MHz; MAX11043 limit is 40MHz
whismanoid 53:3d5a3d241a5e 224 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 225
whismanoid 53:3d5a3d241a5e 226 //
whismanoid 53:3d5a3d241a5e 227 // CODE GENERATOR: class constructor definition gpio InputPin (Input to device) initialization
whismanoid 53:3d5a3d241a5e 228 //
whismanoid 53:3d5a3d241a5e 229 // CONVRUN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 230 m_CONVRUN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 231 //
whismanoid 53:3d5a3d241a5e 232 // SHDN Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 233 m_SHDN_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 234 //
whismanoid 53:3d5a3d241a5e 235 // DACSTEP Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 236 m_DACSTEP_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 237 //
whismanoid 53:3d5a3d241a5e 238 // UP_slash_DWNb Configuration Input to MAX11043 device
whismanoid 53:3d5a3d241a5e 239 m_UP_slash_DWNb_pin = 1; // output logic high -- initial value in constructor
whismanoid 53:3d5a3d241a5e 240 //
whismanoid 53:3d5a3d241a5e 241 // CODE GENERATOR: class constructor definition gpio OutputPin (Output from MAX11043 device) initialization
whismanoid 53:3d5a3d241a5e 242 //
whismanoid 53:3d5a3d241a5e 243 // EOC Event Output from device
whismanoid 69:989e392cf635 244 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 76:0397493d7baf 245 #if MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 246 // SPI is not interrupt-safe, so use EventQueue to defer execution to user context.
whismanoid 76:0397493d7baf 247 myOnEOCThread.start(myOnEOCThread_handler);
whismanoid 76:0397493d7baf 248 #else // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 249 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 250 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 251 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 252 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 253 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 254 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 255 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 256 // TODO: onEOCFallingEdge: interrupt handler requires global object extern MAX11043 g_MAX11043_device
whismanoid 71:62bcd01ea87f 257 // InterruptIn interruptEOC(EOC_pin); // InterruptIn constructor requires PinName, not DigitalIn -- Error: No instance of constructor "mbed::InterruptIn::InterruptIn" matches the argument list in "MAX11043/MAX11043.cpp", Line: 187, Col: 31
whismanoid 69:989e392cf635 258 // TODO: onEOCFallingEdge: replace DigitalIn &EOC_pin with PinName EOC_pin, so that I can create an InterruptIn(PinName:EOC_pin)
whismanoid 74:f4f969c9a7a9 259 digitalInOut5.output(); // ScopeTrigger
whismanoid 70:f44a577c9e59 260 extern void onEOCFallingEdge(void);
whismanoid 71:62bcd01ea87f 261 // interruptEOC.fall(&onEOCFallingEdge);
whismanoid 71:62bcd01ea87f 262 EOC_pin.fall(&onEOCFallingEdge);
whismanoid 69:989e392cf635 263 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 76:0397493d7baf 264 }
whismanoid 69:989e392cf635 265
whismanoid 76:0397493d7baf 266 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 76:0397493d7baf 267 // SPI is not interrupt-safe, so use EventQueue to defer execution to user context.
whismanoid 77:3a6e2a5cd7d9 268 // Waiting for EOC# fall to signal EventQueue is too slow, ~25us to handle event but events happen every 9us.
whismanoid 76:0397493d7baf 269 #if MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 270 void myOnEOCThread_handler()
whismanoid 76:0397493d7baf 271 {
whismanoid 76:0397493d7baf 272 while (true) {
whismanoid 80:96bc693e0f79 273 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 80:96bc693e0f79 274 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 80:96bc693e0f79 275 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 80:96bc693e0f79 276 // poll m_EOC_pin if CONVRUN is high
whismanoid 80:96bc693e0f79 277 if (m_CONVRUN_pin)
whismanoid 80:96bc693e0f79 278 {
whismanoid 80:96bc693e0f79 279 #warning "myOnEOCThread_handler() Potential infinite loop if EOC pin not connected"
whismanoid 80:96bc693e0f79 280 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 80:96bc693e0f79 281 for (int futility_countdown = 100;
whismanoid 80:96bc693e0f79 282 ((futility_countdown > 0) &&
whismanoid 80:96bc693e0f79 283 (m_EOC_pin != 1));
whismanoid 80:96bc693e0f79 284 futility_countdown--)
whismanoid 80:96bc693e0f79 285 {
whismanoid 80:96bc693e0f79 286 // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 80:96bc693e0f79 287 }
whismanoid 80:96bc693e0f79 288 for (int futility_countdown = 100;
whismanoid 80:96bc693e0f79 289 ((futility_countdown > 0) &&
whismanoid 80:96bc693e0f79 290 (m_EOC_pin != 0));
whismanoid 80:96bc693e0f79 291 futility_countdown--)
whismanoid 80:96bc693e0f79 292 {
whismanoid 80:96bc693e0f79 293 // spinlock waiting for logic low pin state (new data is available)
whismanoid 80:96bc693e0f79 294 }
whismanoid 80:96bc693e0f79 295 }
whismanoid 80:96bc693e0f79 296 else
whismanoid 80:96bc693e0f79 297 {
whismanoid 80:96bc693e0f79 298 // CONVRUN pin is being driven low, so conversion result will not change, EOC# remains high
whismanoid 80:96bc693e0f79 299 continue;
whismanoid 80:96bc693e0f79 300 }
whismanoid 80:96bc693e0f79 301 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 80:96bc693e0f79 302 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 80:96bc693e0f79 303 // Interrupt Handler: EOC Event Output from device
whismanoid 80:96bc693e0f79 304 // Wait for MYONEOCTHREADEVENTFLAG_ENABLE_SPI event sent from onEOCFallingEdge interrupt
whismanoid 76:0397493d7baf 305 //signal_wait(int32_t signals, uint32_t millisec=osWaitForever)
whismanoid 76:0397493d7baf 306 //flags_read = myOnEOCThread_event_flags.wait_any(MYONEOCTHREADEVENTFLAG_ENABLE_SPI);
whismanoid 76:0397493d7baf 307 // myOnEOCThread_event_flags.wait_any(MYONEOCTHREADEVENTFLAG_ENABLE_SPI, osWaitForever, false); // clear=false: don't auto clear the flag
whismanoid 76:0397493d7baf 308 myOnEOCThread_event_flags.wait_any(MYONEOCTHREADEVENTFLAG_ENABLE_SPI, osWaitForever, true); // clear=true: auto clear the flag
whismanoid 80:96bc693e0f79 309 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 76:0397493d7baf 310 //
whismanoid 76:0397493d7baf 311 extern MAX11043 g_MAX11043_device;
whismanoid 76:0397493d7baf 312 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 76:0397493d7baf 313 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 77:3a6e2a5cd7d9 314 digitalInOut5.write(0); // ScopeTrigger happens at 1.8us after EOC# falling edge
whismanoid 76:0397493d7baf 315 digitalInOut5.write(1); // ScopeTrigger
whismanoid 76:0397493d7baf 316 digitalInOut5.write(0); // ScopeTrigger
whismanoid 76:0397493d7baf 317 digitalInOut5.write(1); // ScopeTrigger
whismanoid 76:0397493d7baf 318 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 76:0397493d7baf 319 extern SPI spi; // declared in Test_Main_MAX11043.cpp
whismanoid 76:0397493d7baf 320 spi.write((char*)mosiData_onEOCFallingEdge, byteCount_onEOCFallingEdge, (char*)misoData_onEOCFallingEdge, byteCount_onEOCFallingEdge);
whismanoid 77:3a6e2a5cd7d9 321 // SPI timing: CS low 13.30us after EOC# falling edge
whismanoid 77:3a6e2a5cd7d9 322 // SPI timing: SCLK first 14.60us after EOC# falling edge
whismanoid 77:3a6e2a5cd7d9 323 // SPI timing: SCLK last 17.70us after EOC# falling edge
whismanoid 77:3a6e2a5cd7d9 324 // SPI timing: CS high 17.70us after EOC# falling edge
whismanoid 77:3a6e2a5cd7d9 325 //
whismanoid 76:0397493d7baf 326 // TODO1: update adca
whismanoid 76:0397493d7baf 327 //g_MAX11043_device.adca = (misoData_onEOCFallingEdge[1] << 8) | misoData_onEOCFallingEdge[2];
whismanoid 76:0397493d7baf 328 // TODO1: update adcb
whismanoid 76:0397493d7baf 329 //g_MAX11043_device.adcb = (misoData_onEOCFallingEdge[3] << 8) | misoData_onEOCFallingEdge[4];
whismanoid 76:0397493d7baf 330 // TODO1: update adcc
whismanoid 76:0397493d7baf 331 //g_MAX11043_device.adcc = (misoData_onEOCFallingEdge[5] << 8) | misoData_onEOCFallingEdge[6];
whismanoid 76:0397493d7baf 332 // TODO1: update adcd
whismanoid 76:0397493d7baf 333 //g_MAX11043_device.adcd = (misoData_onEOCFallingEdge[7] << 8) | misoData_onEOCFallingEdge[8];
whismanoid 77:3a6e2a5cd7d9 334 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 77:3a6e2a5cd7d9 335 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 77:3a6e2a5cd7d9 336 digitalInOut5.write(0); // ScopeTrigger happens at 22.5us after EOC# falling edge
whismanoid 77:3a6e2a5cd7d9 337 digitalInOut5.write(1); // ScopeTrigger
whismanoid 77:3a6e2a5cd7d9 338 digitalInOut5.write(0); // ScopeTrigger
whismanoid 77:3a6e2a5cd7d9 339 digitalInOut5.write(1); // ScopeTrigger
whismanoid 77:3a6e2a5cd7d9 340 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 80:96bc693e0f79 341 } // while (true)
whismanoid 80:96bc693e0f79 342 } // myOnEOCThread_handler()
whismanoid 76:0397493d7baf 343 #else // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 344 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 53:3d5a3d241a5e 345
whismanoid 69:989e392cf635 346 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 347 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 348 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 349 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 350 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 351 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 352 // Interrupt Handler: EOC Event Output from device
whismanoid 69:989e392cf635 353 void onEOCFallingEdge(void)
whismanoid 69:989e392cf635 354 {
whismanoid 72:40feab5fd579 355 // VERIFIED: if DO NOTHING inside interrupt service routine, no crash
whismanoid 72:40feab5fd579 356 #if 1
whismanoid 72:40feab5fd579 357 // VERIFIED: GPIO PIN pulse in response to EOC# falling edge, no crash on HH, no missed pulses
whismanoid 73:879578472009 358 #if MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 73:879578472009 359 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 74:f4f969c9a7a9 360 digitalInOut5.write(0); // ScopeTrigger 1.8us after EOC# falling edge
whismanoid 74:f4f969c9a7a9 361 digitalInOut5.write(1); // ScopeTrigger
whismanoid 74:f4f969c9a7a9 362 digitalInOut5.write(0); // ScopeTrigger
whismanoid 74:f4f969c9a7a9 363 digitalInOut5.write(1); // ScopeTrigger
whismanoid 73:879578472009 364 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 72:40feab5fd579 365 #endif
whismanoid 76:0397493d7baf 366 #if MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 367 // SPI is not interrupt-safe, so use EventQueue to defer execution to user context.
whismanoid 76:0397493d7baf 368 myOnEOCThread_event_flags.set(MYONEOCTHREADEVENTFLAG_ENABLE_SPI);
whismanoid 76:0397493d7baf 369 #else // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 370 #endif // MAX11043_EOC_INTERRUPT_EVENTQUEUE
whismanoid 76:0397493d7baf 371 #if 0
whismanoid 72:40feab5fd579 372 // TODO: read 4 channels in response to EOC# falling edge
whismanoid 72:40feab5fd579 373 // WIP MAX11043 interrupt CRASH on Menu item HH CONVRUN High
whismanoid 72:40feab5fd579 374 //
whismanoid 72:40feab5fd579 375 // ++ MbedOS Error Info ++
whismanoid 72:40feab5fd579 376 // Error Status: 0x80020115 Code: 277 Module: 2
whismanoid 72:40feab5fd579 377 // Error Message: Mutex lock failed
whismanoid 72:40feab5fd579 378 // Location: 0xBA33
whismanoid 72:40feab5fd579 379 // Error Value: 0xFFFFFFFA
whismanoid 72:40feab5fd579 380 // Current Thread: main Id: 0x20002CD0 Entry: 0xBD17 StackSize: 0x1000 StackMem: 0x20001CD0 SP: 0x20027ED0
whismanoid 72:40feab5fd579 381 // For more info, visit: https://armmbed.github.io/mbedos-error/?error=0x80020115
whismanoid 72:40feab5fd579 382 // -- MbedOS Error Info --
whismanoid 69:989e392cf635 383 extern MAX11043 g_MAX11043_device;
whismanoid 75:0900a57f2e5d 384 //~ g_MAX11043_device.Read_ADCabcd();
whismanoid 74:f4f969c9a7a9 385 // read register ADCabcd -> &adca, &adcb, &adcc, &adcd
whismanoid 74:f4f969c9a7a9 386 // g_MAX11043_device.RegRead(CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd, 0);
whismanoid 75:0900a57f2e5d 387 // SPI 8+64 = 72-bit transfer
whismanoid 75:0900a57f2e5d 388 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72
whismanoid 75:0900a57f2e5d 389 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 75:0900a57f2e5d 390 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 75:0900a57f2e5d 391 // global const size_t byteCount_onEOCFallingEdge = 1 + (2 * 4);
whismanoid 75:0900a57f2e5d 392 // global const uint8_t mosiData_onEOCFallingEdge[9] = {
whismanoid 75:0900a57f2e5d 393 // global CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd,
whismanoid 75:0900a57f2e5d 394 // global 0, 0, 0, 0, 0, 0, 0, 0
whismanoid 75:0900a57f2e5d 395 // global };
whismanoid 75:0900a57f2e5d 396 // global uint8_t misoData_onEOCFallingEdge[9];
whismanoid 75:0900a57f2e5d 397 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 75:0900a57f2e5d 398 // SPIreadWriteWithLowCS(byteCount_onEOCFallingEdge, mosiData_onEOCFallingEdge, misoData_onEOCFallingEdge);
whismanoid 75:0900a57f2e5d 399 // onSPIprint() is not interrupt-safe
whismanoid 75:0900a57f2e5d 400 // unsigned int numBytesTransferred = m_spi.write((char*)mosiData, byteCount, (char*)misoData, byteCount);
whismanoid 75:0900a57f2e5d 401 // g_MAX11043_device.m_spi is inaccessible
whismanoid 75:0900a57f2e5d 402 extern SPI spi; // declared in Test_Main_MAX11043.cpp
whismanoid 75:0900a57f2e5d 403 spi.write((char*)mosiData_onEOCFallingEdge, byteCount_onEOCFallingEdge, (char*)misoData_onEOCFallingEdge, byteCount_onEOCFallingEdge);
whismanoid 75:0900a57f2e5d 404 //
whismanoid 75:0900a57f2e5d 405 // ++ MbedOS Error Info ++
whismanoid 75:0900a57f2e5d 406 // Error Status: 0x80020115 Code: 277 Module: 2
whismanoid 75:0900a57f2e5d 407 // Error Message: Mutex lock failed
whismanoid 75:0900a57f2e5d 408 // Location: 0xBABB
whismanoid 75:0900a57f2e5d 409 // Error Value: 0xFFFFFFFA
whismanoid 75:0900a57f2e5d 410 // Current Thread: main Id: 0x20002CD0 Entry: 0xBD9F StackSize: 0x1000 StackMem: 0x20001CD0 SP: 0x20027F10
whismanoid 75:0900a57f2e5d 411 // For more info, visit: https://armmbed.github.io/mbedos-error/?error=0x80020115
whismanoid 75:0900a57f2e5d 412 // -- MbedOS Error Info --
whismanoid 75:0900a57f2e5d 413 //
whismanoid 75:0900a57f2e5d 414 //if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 75:0900a57f2e5d 415 //if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 75:0900a57f2e5d 416 // TODO1: update adca
whismanoid 75:0900a57f2e5d 417 //g_MAX11043_device.adca = (misoData_onEOCFallingEdge[1] << 8) | misoData_onEOCFallingEdge[2];
whismanoid 75:0900a57f2e5d 418 // TODO1: update adcb
whismanoid 75:0900a57f2e5d 419 //g_MAX11043_device.adcb = (misoData_onEOCFallingEdge[3] << 8) | misoData_onEOCFallingEdge[4];
whismanoid 75:0900a57f2e5d 420 // TODO1: update adcc
whismanoid 75:0900a57f2e5d 421 //g_MAX11043_device.adcc = (misoData_onEOCFallingEdge[5] << 8) | misoData_onEOCFallingEdge[6];
whismanoid 75:0900a57f2e5d 422 // TODO1: update adcd
whismanoid 75:0900a57f2e5d 423 //g_MAX11043_device.adcd = (misoData_onEOCFallingEdge[7] << 8) | misoData_onEOCFallingEdge[8];
whismanoid 75:0900a57f2e5d 424 //}
whismanoid 72:40feab5fd579 425 #endif
whismanoid 76:0397493d7baf 426 #if 0 // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 75:0900a57f2e5d 427 // Diagnostic: Use MAX32625MBED pin D5 as DigitalOut EOC#-detected
whismanoid 75:0900a57f2e5d 428 digitalInOut5.write(0); // ScopeTrigger
whismanoid 75:0900a57f2e5d 429 digitalInOut5.write(1); // ScopeTrigger
whismanoid 75:0900a57f2e5d 430 #endif // MAX11043_ScopeTrigger_MAX32625MBED_D5
whismanoid 69:989e392cf635 431 }
whismanoid 69:989e392cf635 432 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 433
whismanoid 53:3d5a3d241a5e 434 // CODE GENERATOR: class destructor definition
whismanoid 53:3d5a3d241a5e 435 MAX11043::~MAX11043()
whismanoid 53:3d5a3d241a5e 436 {
whismanoid 53:3d5a3d241a5e 437 // do nothing
whismanoid 53:3d5a3d241a5e 438 }
whismanoid 53:3d5a3d241a5e 439
whismanoid 53:3d5a3d241a5e 440 // CODE GENERATOR: spi_frequency setter definition
whismanoid 53:3d5a3d241a5e 441 /// set SPI SCLK frequency
whismanoid 53:3d5a3d241a5e 442 void MAX11043::spi_frequency(int spi_sclk_Hz)
whismanoid 53:3d5a3d241a5e 443 {
whismanoid 53:3d5a3d241a5e 444 m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid 53:3d5a3d241a5e 445 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 53:3d5a3d241a5e 446 }
whismanoid 53:3d5a3d241a5e 447
whismanoid 53:3d5a3d241a5e 448 // CODE GENERATOR: omit global g_MAX11043_device
whismanoid 53:3d5a3d241a5e 449 // CODE GENERATOR: extern function declarations
whismanoid 53:3d5a3d241a5e 450 // CODE GENERATOR: extern function requirement MAX11043::SPIoutputCS
whismanoid 53:3d5a3d241a5e 451 // Assert SPI Chip Select
whismanoid 53:3d5a3d241a5e 452 // SPI chip-select for MAX11043
whismanoid 53:3d5a3d241a5e 453 //
whismanoid 62:8223a7253c90 454 inline void MAX11043::SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 455 {
whismanoid 53:3d5a3d241a5e 456 // CODE GENERATOR: extern function definition for function SPIoutputCS
whismanoid 53:3d5a3d241a5e 457 // CODE GENERATOR: extern function definition for standard SPI interface function SPIoutputCS(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 458 m_SPI_cs_state = isLogicHigh;
whismanoid 67:5b8a495dda1c 459 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 460 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 461 }
whismanoid 53:3d5a3d241a5e 462 }
whismanoid 53:3d5a3d241a5e 463
whismanoid 62:8223a7253c90 464 // CODE GENERATOR: extern function requirement MAX11043::SPIreadWriteWithLowCS
whismanoid 62:8223a7253c90 465 // SPI read and write arbitrary number of 8-bit bytes
whismanoid 62:8223a7253c90 466 // SPI interface to MAX11043 shift mosiData into MAX11043 DIN
whismanoid 62:8223a7253c90 467 // while simultaneously capturing miso data from MAX11043 DOUT
whismanoid 62:8223a7253c90 468 //
whismanoid 62:8223a7253c90 469 int MAX11043::SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 470 {
whismanoid 62:8223a7253c90 471 // CODE GENERATOR: extern function definition for function SPIreadWriteWithLowCS
whismanoid 63:8f39d21d6157 472 // TODO1: CODE GENERATOR: extern function definition for standard SPI interface function SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[])
whismanoid 62:8223a7253c90 473 //size_t byteCount = 4;
whismanoid 62:8223a7253c90 474 //static char mosiData[4];
whismanoid 62:8223a7253c90 475 //static char misoData[4];
whismanoid 62:8223a7253c90 476 //
whismanoid 62:8223a7253c90 477 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 478 //~ noInterrupts();
whismanoid 62:8223a7253c90 479 //
whismanoid 62:8223a7253c90 480 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 481 //
whismanoid 67:5b8a495dda1c 482 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 483 m_cs_pin = 0;
whismanoid 67:5b8a495dda1c 484 }
whismanoid 62:8223a7253c90 485 unsigned int numBytesTransferred = m_spi.write((char*)mosiData, byteCount, (char*)misoData, byteCount);
whismanoid 67:5b8a495dda1c 486 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 67:5b8a495dda1c 487 m_cs_pin = m_SPI_cs_state;
whismanoid 67:5b8a495dda1c 488 }
whismanoid 62:8223a7253c90 489 //
whismanoid 62:8223a7253c90 490 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 62:8223a7253c90 491 //
whismanoid 62:8223a7253c90 492 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 62:8223a7253c90 493 //~ interrupts();
whismanoid 62:8223a7253c90 494 // Optional Diagnostic function to print SPI transactions
whismanoid 62:8223a7253c90 495 if (onSPIprint)
whismanoid 62:8223a7253c90 496 {
whismanoid 62:8223a7253c90 497 onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
whismanoid 62:8223a7253c90 498 }
whismanoid 62:8223a7253c90 499 return numBytesTransferred;
whismanoid 62:8223a7253c90 500 }
whismanoid 62:8223a7253c90 501
whismanoid 53:3d5a3d241a5e 502 // TODO1: CODE GENERATOR: extern function GPIOoutputSHDN alias SHDNoutputValue
whismanoid 53:3d5a3d241a5e 503 // CODE GENERATOR: extern function requirement MAX11043::SHDNoutputValue
whismanoid 58:2fea32db466b 504 // Assert MAX11043 SHDN pin : High = Shut Down, Low = Normal Operation.
whismanoid 53:3d5a3d241a5e 505 //
whismanoid 53:3d5a3d241a5e 506 void MAX11043::SHDNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 507 {
whismanoid 53:3d5a3d241a5e 508 // CODE GENERATOR: extern function definition for function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 509 // TODO1: CODE GENERATOR: extern function definition for gpio interface function SHDNoutputValue
whismanoid 53:3d5a3d241a5e 510 // TODO1: CODE GENERATOR: gpio pin SHDN assuming member function m_SHDN_pin
whismanoid 53:3d5a3d241a5e 511 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 512 // m_SHDN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 513 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 514 m_SHDN_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 515 }
whismanoid 52:607010f0c54e 516
whismanoid 53:3d5a3d241a5e 517 // TODO1: CODE GENERATOR: extern function GPIOoutputCONVRUN alias CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 518 // CODE GENERATOR: extern function requirement MAX11043::CONVRUNoutputValue
whismanoid 58:2fea32db466b 519 // Assert MAX11043 CONVRUN pin : High = start continuous conversions on all 4 channels, Low = Idle.
whismanoid 53:3d5a3d241a5e 520 //
whismanoid 53:3d5a3d241a5e 521 void MAX11043::CONVRUNoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 522 {
whismanoid 53:3d5a3d241a5e 523 // CODE GENERATOR: extern function definition for function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 524 // TODO1: CODE GENERATOR: extern function definition for gpio interface function CONVRUNoutputValue
whismanoid 53:3d5a3d241a5e 525 // TODO1: CODE GENERATOR: gpio pin CONVRUN assuming member function m_CONVRUN_pin
whismanoid 53:3d5a3d241a5e 526 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 527 // m_CONVRUN_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 528 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 529 m_CONVRUN_pin = isLogicHigh;
whismanoid 69:989e392cf635 530 //--------------------------------------------------
whismanoid 69:989e392cf635 531 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 532 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 533 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 534 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 535 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 536 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 537 if (m_CONVRUN_pin)
whismanoid 69:989e392cf635 538 {
whismanoid 69:989e392cf635 539 // CONVRUN was switched high, EOC# will now begin toggling
whismanoid 69:989e392cf635 540 }
whismanoid 69:989e392cf635 541 else
whismanoid 69:989e392cf635 542 {
whismanoid 69:989e392cf635 543 // CONVRUN was switched low, so wait until EOC# returns high
whismanoid 69:989e392cf635 544 #warning "MAX11043::Read_ADCabcd() Potential infinite loop if EOC pin not connected"
whismanoid 69:989e392cf635 545 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 69:989e392cf635 546 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 547 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 548 (m_EOC_pin != 1));
whismanoid 69:989e392cf635 549 futility_countdown--)
whismanoid 69:989e392cf635 550 {
whismanoid 69:989e392cf635 551 // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 69:989e392cf635 552 }
whismanoid 69:989e392cf635 553 }
whismanoid 69:989e392cf635 554 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 555 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 556 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 557 //--------------------------------------------------
whismanoid 53:3d5a3d241a5e 558 }
whismanoid 53:3d5a3d241a5e 559
whismanoid 53:3d5a3d241a5e 560 // TODO1: CODE GENERATOR: extern function GPIOoutputDACSTEP alias DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 561 // CODE GENERATOR: extern function requirement MAX11043::DACSTEPoutputValue
whismanoid 58:2fea32db466b 562 // Assert MAX11043 DACSTEP pin : High = Active, Low = Idle.
whismanoid 53:3d5a3d241a5e 563 //
whismanoid 53:3d5a3d241a5e 564 void MAX11043::DACSTEPoutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 565 {
whismanoid 53:3d5a3d241a5e 566 // CODE GENERATOR: extern function definition for function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 567 // TODO1: CODE GENERATOR: extern function definition for gpio interface function DACSTEPoutputValue
whismanoid 53:3d5a3d241a5e 568 // TODO1: CODE GENERATOR: gpio pin DACSTEP assuming member function m_DACSTEP_pin
whismanoid 53:3d5a3d241a5e 569 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 570 // m_DACSTEP_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 571 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 572 m_DACSTEP_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 573 }
whismanoid 53:3d5a3d241a5e 574
whismanoid 53:3d5a3d241a5e 575 // TODO1: CODE GENERATOR: extern function GPIOoutputUP_slash_DWNb alias UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 576 // CODE GENERATOR: extern function requirement MAX11043::UP_slash_DWNboutputValue
whismanoid 58:2fea32db466b 577 // Assert MAX11043 UP_slash_DWNb pin : High = Up, Low = Down.
whismanoid 53:3d5a3d241a5e 578 //
whismanoid 53:3d5a3d241a5e 579 void MAX11043::UP_slash_DWNboutputValue(int isLogicHigh)
whismanoid 53:3d5a3d241a5e 580 {
whismanoid 53:3d5a3d241a5e 581 // CODE GENERATOR: extern function definition for function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 582 // TODO1: CODE GENERATOR: extern function definition for gpio interface function UP_slash_DWNboutputValue
whismanoid 53:3d5a3d241a5e 583 // TODO1: CODE GENERATOR: gpio pin UP_slash_DWNb assuming member function m_UP_slash_DWNb_pin
whismanoid 53:3d5a3d241a5e 584 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 53:3d5a3d241a5e 585 // m_UP_slash_DWNb_pin.output(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 586 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 587 m_UP_slash_DWNb_pin = isLogicHigh;
whismanoid 53:3d5a3d241a5e 588 }
whismanoid 53:3d5a3d241a5e 589
whismanoid 53:3d5a3d241a5e 590 // CODE GENERATOR: extern function requirement MAX11043::EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 591 // Wait for MAX11043 EOC pin low, indicating end of conversion.
whismanoid 53:3d5a3d241a5e 592 // Required when using any of the InternalClock modes.
whismanoid 53:3d5a3d241a5e 593 //
whismanoid 53:3d5a3d241a5e 594 void MAX11043::EOCinputWaitUntilLow()
whismanoid 53:3d5a3d241a5e 595 {
whismanoid 53:3d5a3d241a5e 596 // CODE GENERATOR: extern function definition for function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 597 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputWaitUntilLow
whismanoid 53:3d5a3d241a5e 598 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 599 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 600 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 601 // TODO1: CODE GENERATOR: gpio function WaitUntilLow
whismanoid 53:3d5a3d241a5e 602 while (m_EOC_pin != 0)
whismanoid 53:3d5a3d241a5e 603 {
whismanoid 53:3d5a3d241a5e 604 // spinlock waiting for logic low pin state
whismanoid 53:3d5a3d241a5e 605 }
whismanoid 53:3d5a3d241a5e 606 }
whismanoid 53:3d5a3d241a5e 607
whismanoid 53:3d5a3d241a5e 608 // CODE GENERATOR: extern function requirement MAX11043::EOCinputValue
whismanoid 53:3d5a3d241a5e 609 // Return the status of the MAX11043 EOC pin.
whismanoid 53:3d5a3d241a5e 610 //
whismanoid 53:3d5a3d241a5e 611 int MAX11043::EOCinputValue()
whismanoid 53:3d5a3d241a5e 612 {
whismanoid 53:3d5a3d241a5e 613 // CODE GENERATOR: extern function definition for function EOCinputValue
whismanoid 53:3d5a3d241a5e 614 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputValue
whismanoid 53:3d5a3d241a5e 615 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 53:3d5a3d241a5e 616 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 53:3d5a3d241a5e 617 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 53:3d5a3d241a5e 618 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 53:3d5a3d241a5e 619 return m_EOC_pin.read();
whismanoid 53:3d5a3d241a5e 620 }
whismanoid 53:3d5a3d241a5e 621
whismanoid 53:3d5a3d241a5e 622 // CODE GENERATOR: class member function definitions
whismanoid 53:3d5a3d241a5e 623 //----------------------------------------
whismanoid 53:3d5a3d241a5e 624 // Menu item '!'
whismanoid 53:3d5a3d241a5e 625 // Initialize device
whismanoid 53:3d5a3d241a5e 626 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 627 uint8_t MAX11043::Init(void)
whismanoid 53:3d5a3d241a5e 628 {
whismanoid 53:3d5a3d241a5e 629
whismanoid 53:3d5a3d241a5e 630 //----------------------------------------
whismanoid 59:47538bcf6cda 631 // reference voltage, in Volts
whismanoid 59:47538bcf6cda 632 VRef = 2.500;
whismanoid 59:47538bcf6cda 633
whismanoid 59:47538bcf6cda 634 //----------------------------------------
whismanoid 59:47538bcf6cda 635 // shadow of register config CMD_0010_0010_d16_Rd08_Configuration
whismanoid 59:47538bcf6cda 636 config = 0x6000;
whismanoid 59:47538bcf6cda 637
whismanoid 59:47538bcf6cda 638 //----------------------------------------
whismanoid 59:47538bcf6cda 639 // shadow of register status CMD_0001_1110_d8_Rd07_Status
whismanoid 59:47538bcf6cda 640 status = 0x00;
whismanoid 53:3d5a3d241a5e 641
whismanoid 53:3d5a3d241a5e 642 //----------------------------------------
whismanoid 59:47538bcf6cda 643 // shadow of register ADCa CMD_0000_0010_d16o8_Rd00_ADCa
whismanoid 59:47538bcf6cda 644 adca = 0x0000;
whismanoid 53:3d5a3d241a5e 645
whismanoid 53:3d5a3d241a5e 646 //----------------------------------------
whismanoid 59:47538bcf6cda 647 // shadow of register ADCb CMD_0000_0110_d16o8_Rd01_ADCb
whismanoid 59:47538bcf6cda 648 adcb = 0x0000;
whismanoid 59:47538bcf6cda 649
whismanoid 59:47538bcf6cda 650 //----------------------------------------
whismanoid 59:47538bcf6cda 651 // shadow of register ADCc CMD_0000_1010_d16o8_Rd02_ADCc
whismanoid 59:47538bcf6cda 652 adcc = 0x0000;
whismanoid 59:47538bcf6cda 653
whismanoid 59:47538bcf6cda 654 //----------------------------------------
whismanoid 59:47538bcf6cda 655 // shadow of register ADCd CMD_0000_1110_d16o8_Rd03_ADCd
whismanoid 59:47538bcf6cda 656 adcd = 0x0000;
whismanoid 53:3d5a3d241a5e 657
whismanoid 53:3d5a3d241a5e 658 //----------------------------------------
whismanoid 53:3d5a3d241a5e 659 // init (based on old EV kit GUI)
whismanoid 53:3d5a3d241a5e 660 #warning "Not Implemented Yet: MAX11043::Init init..."
whismanoid 53:3d5a3d241a5e 661 // bool bOpResult = false;
whismanoid 53:3d5a3d241a5e 662 // String FWVersionString = "00";
whismanoid 53:3d5a3d241a5e 663 // bool bDemoMode = true;
whismanoid 53:3d5a3d241a5e 664 // int scan_resolution = 0;
whismanoid 53:3d5a3d241a5e 665 // int scan_channels = 0;
whismanoid 53:3d5a3d241a5e 666 // int scan_bits = 0;
whismanoid 53:3d5a3d241a5e 667 // int sampleRateFactore = 0;
whismanoid 53:3d5a3d241a5e 668 // double sampleRate = 0;
whismanoid 53:3d5a3d241a5e 669 // unsigned long banks_requested = 0;
whismanoid 53:3d5a3d241a5e 670 // bool bScanMode = 0;
whismanoid 53:3d5a3d241a5e 671
whismanoid 53:3d5a3d241a5e 672 //----------------------------------------
whismanoid 59:47538bcf6cda 673 // Device ID Validation -- not used, no device ID register
whismanoid 53:3d5a3d241a5e 674 #warning "Not Implemented Yet: MAX11043::Init Device ID Validation..."
whismanoid 53:3d5a3d241a5e 675 // const uint32_t part_id_expect = 0x000F02;
whismanoid 53:3d5a3d241a5e 676 // uint32_t part_id_readback;
whismanoid 53:3d5a3d241a5e 677 // RegRead(xxxxxxxxxxxxCMD_r001_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xddd_PART_ID, &part_id_readback);
whismanoid 53:3d5a3d241a5e 678 // if (part_id_readback != part_id_expect) return 0;
whismanoid 53:3d5a3d241a5e 679
whismanoid 53:3d5a3d241a5e 680 //----------------------------------------
whismanoid 58:2fea32db466b 681 // Active-High Shutdown Input. Drive high to shut down the MAX11043.
whismanoid 58:2fea32db466b 682 SHDNoutputValue(0); // SHDN Inactive
whismanoid 58:2fea32db466b 683
whismanoid 58:2fea32db466b 684 //----------------------------------------
whismanoid 58:2fea32db466b 685 // Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
whismanoid 58:2fea32db466b 686 // CONVRUN is low.
whismanoid 58:2fea32db466b 687 CONVRUNoutputValue(0); // CONVRUN Idle
whismanoid 58:2fea32db466b 688
whismanoid 58:2fea32db466b 689 //----------------------------------------
whismanoid 58:2fea32db466b 690 // DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
whismanoid 58:2fea32db466b 691 // edge of the system clock.
whismanoid 58:2fea32db466b 692 DACSTEPoutputValue(0); // DACSTEP Idle
whismanoid 58:2fea32db466b 693
whismanoid 58:2fea32db466b 694 //----------------------------------------
whismanoid 58:2fea32db466b 695 // DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
whismanoid 58:2fea32db466b 696 UP_slash_DWNboutputValue(0); // UP/DWN# Down
whismanoid 58:2fea32db466b 697
whismanoid 58:2fea32db466b 698 //----------------------------------------
whismanoid 53:3d5a3d241a5e 699 // success
whismanoid 53:3d5a3d241a5e 700 return 1;
whismanoid 53:3d5a3d241a5e 701 }
whismanoid 53:3d5a3d241a5e 702
whismanoid 53:3d5a3d241a5e 703 //----------------------------------------
whismanoid 53:3d5a3d241a5e 704 // Write a MAX11043 register.
whismanoid 53:3d5a3d241a5e 705 //
whismanoid 57:1c9da8e90737 706 // CMDOP_1aaa_aaaa_ReadRegister bit is cleared 0 indicating a write operation.
whismanoid 53:3d5a3d241a5e 707 //
whismanoid 53:3d5a3d241a5e 708 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 709 //
whismanoid 53:3d5a3d241a5e 710 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 711 //
whismanoid 53:3d5a3d241a5e 712 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 713 //
whismanoid 53:3d5a3d241a5e 714 // SPI MOSI = 0aaa_aaaa_dddd_dddd
whismanoid 53:3d5a3d241a5e 715 //
whismanoid 53:3d5a3d241a5e 716 // SPI MISO = xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 717 //
whismanoid 53:3d5a3d241a5e 718 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 719 //
whismanoid 53:3d5a3d241a5e 720 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 721 //
whismanoid 53:3d5a3d241a5e 722 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 723 //
whismanoid 53:3d5a3d241a5e 724 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 725 //
whismanoid 53:3d5a3d241a5e 726 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 727 //
whismanoid 53:3d5a3d241a5e 728 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 729 //
whismanoid 53:3d5a3d241a5e 730 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 731 //
whismanoid 53:3d5a3d241a5e 732 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 53:3d5a3d241a5e 733 //
whismanoid 53:3d5a3d241a5e 734 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 735 uint8_t MAX11043::RegWrite(MAX11043_CMD_enum_t commandByte, uint32_t regData)
whismanoid 53:3d5a3d241a5e 736 {
whismanoid 53:3d5a3d241a5e 737
whismanoid 53:3d5a3d241a5e 738 //----------------------------------------
whismanoid 53:3d5a3d241a5e 739 // switch based on register address szie RegSize(commandByte)
whismanoid 57:1c9da8e90737 740 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 741 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 742 {
whismanoid 53:3d5a3d241a5e 743 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 744 {
whismanoid 63:8f39d21d6157 745 // SPI 8+8 = 16-bit transfer
whismanoid 63:8f39d21d6157 746 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 747 // SPI MOSI = 0aaa_aaaa_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 748 // SPI MISO = xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 749 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 750 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 751 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 752 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 753 mosiData[1] = regData;
whismanoid 63:8f39d21d6157 754 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 755 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 756 // TODO: cache CMD_0101_0100_d8_Wr15_FilterCAddress
whismanoid 63:8f39d21d6157 757 // if (commandByte == CMD_0101_0100_d8_Wr15_FilterCAddress) {
whismanoid 63:8f39d21d6157 758 // FilterCAddress = regData;
whismanoid 63:8f39d21d6157 759 // }
whismanoid 63:8f39d21d6157 760 // TODO: cache CMD_0110_0000_d8_Wr18_FlashMode
whismanoid 63:8f39d21d6157 761 // if (commandByte == CMD_0110_0000_d8_Wr18_FlashMode) {
whismanoid 63:8f39d21d6157 762 // FlashMode = regData;
whismanoid 63:8f39d21d6157 763 // }
whismanoid 53:3d5a3d241a5e 764 }
whismanoid 53:3d5a3d241a5e 765 break;
whismanoid 53:3d5a3d241a5e 766 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 767 #warning "Not Verified Yet: MAX11043::RegWrite 16-bit"
whismanoid 53:3d5a3d241a5e 768 {
whismanoid 63:8f39d21d6157 769 // SPI 8+16 = 24-bit transfer
whismanoid 63:8f39d21d6157 770 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 63:8f39d21d6157 771 // SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 772 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 773 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 774 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 775 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 776 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 777 mosiData[1] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 778 mosiData[2] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 779 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 780 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 781 // cache CMD_0010_0000_d16_Wr08_Configuration
whismanoid 63:8f39d21d6157 782 if (commandByte == CMD_0010_0000_d16_Wr08_Configuration) {
whismanoid 63:8f39d21d6157 783 config = regData;
whismanoid 63:8f39d21d6157 784 }
whismanoid 63:8f39d21d6157 785 // TODO: cache CMD_0010_0100_d16_Wr09_DAC
whismanoid 63:8f39d21d6157 786 // TODO: cache CMD_0010_1000_d16_Wr0A_DACStep
whismanoid 63:8f39d21d6157 787 // TODO: cache CMD_0010_1100_d16_Wr0B_DACHDACL
whismanoid 63:8f39d21d6157 788 // TODO: cache CMD_0011_0000_d16_Wr0C_ConfigA
whismanoid 63:8f39d21d6157 789 // TODO: cache CMD_0011_0100_d16_Wr0D_ConfigB
whismanoid 63:8f39d21d6157 790 // TODO: cache CMD_0011_1000_d16_Wr0E_ConfigC
whismanoid 63:8f39d21d6157 791 // TODO: cache CMD_0011_1100_d16_Wr0F_ConfigD
whismanoid 63:8f39d21d6157 792 // TODO: cache CMD_0100_0000_d16_Wr10_Reference
whismanoid 63:8f39d21d6157 793 // TODO: cache CMD_0100_0100_d16_Wr11_AGain
whismanoid 63:8f39d21d6157 794 // TODO: cache CMD_0100_1000_d16_Wr12_BGain
whismanoid 63:8f39d21d6157 795 // TODO: cache CMD_0100_1100_d16_Wr13_CGain
whismanoid 63:8f39d21d6157 796 // TODO: cache CMD_0101_0000_d16_Wr14_DGain
whismanoid 63:8f39d21d6157 797 // TODO: cache CMD_0110_0100_d16_Wr19_FlashAddr
whismanoid 63:8f39d21d6157 798 // TODO: cache CMD_0110_1000_d16_Wr1A_FlashDataIn
whismanoid 53:3d5a3d241a5e 799 }
whismanoid 53:3d5a3d241a5e 800 break;
whismanoid 63:8f39d21d6157 801 case 32: // 32-bit register size
whismanoid 63:8f39d21d6157 802 #warning "Not Verified Yet: MAX11043::RegWrite 32-bit"
whismanoid 53:3d5a3d241a5e 803 {
whismanoid 63:8f39d21d6157 804 // SPI 8+32 = 40-bit transfer
whismanoid 63:8f39d21d6157 805 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 63:8f39d21d6157 806 // SPI MOSI = 1aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _0000
whismanoid 63:8f39d21d6157 807 // SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ... _xxxx
whismanoid 63:8f39d21d6157 808 //
whismanoid 63:8f39d21d6157 809 size_t byteCount = 1 + (2 * 2);
whismanoid 63:8f39d21d6157 810 uint8_t mosiData[5];
whismanoid 63:8f39d21d6157 811 uint8_t misoData[5];
whismanoid 63:8f39d21d6157 812 mosiData[0] = commandByte;
whismanoid 63:8f39d21d6157 813 mosiData[1] = (uint8_t)((regData >> 24) & 0xFF);
whismanoid 63:8f39d21d6157 814 mosiData[2] = (uint8_t)((regData >> 16) & 0xFF);
whismanoid 63:8f39d21d6157 815 mosiData[3] = (uint8_t)((regData >> 8) & 0xFF);
whismanoid 63:8f39d21d6157 816 mosiData[4] = (uint8_t)((regData >> 0) & 0xFF);
whismanoid 63:8f39d21d6157 817 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 818 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 819 // TODO: cache CMD_0101_1000_d32_Wr16_FilterCDataOut
whismanoid 63:8f39d21d6157 820 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 821 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 822 // }
whismanoid 63:8f39d21d6157 823 // TODO: cache CMD_0101_1100_d32_Wr17_FilterCDataIn
whismanoid 63:8f39d21d6157 824 // if (commandByte == CMD_0101_1000_d32_Wr16_FilterCDataOut) {
whismanoid 63:8f39d21d6157 825 // FilterCDataOut = regData;
whismanoid 63:8f39d21d6157 826 // }
whismanoid 53:3d5a3d241a5e 827 }
whismanoid 53:3d5a3d241a5e 828 break;
whismanoid 53:3d5a3d241a5e 829 }
whismanoid 53:3d5a3d241a5e 830
whismanoid 53:3d5a3d241a5e 831 //----------------------------------------
whismanoid 53:3d5a3d241a5e 832 // success
whismanoid 53:3d5a3d241a5e 833 return 1;
whismanoid 53:3d5a3d241a5e 834 }
whismanoid 53:3d5a3d241a5e 835
whismanoid 53:3d5a3d241a5e 836 //----------------------------------------
whismanoid 53:3d5a3d241a5e 837 // Read an 8-bit MAX11043 register
whismanoid 53:3d5a3d241a5e 838 //
whismanoid 57:1c9da8e90737 839 // CMDOP_1aaa_aaaa_ReadRegister bit is set 1 indicating a read operation.
whismanoid 53:3d5a3d241a5e 840 //
whismanoid 53:3d5a3d241a5e 841 // MAX11043 register length can be determined by function RegSize.
whismanoid 53:3d5a3d241a5e 842 //
whismanoid 53:3d5a3d241a5e 843 // For 8-bit register size:
whismanoid 53:3d5a3d241a5e 844 //
whismanoid 53:3d5a3d241a5e 845 // SPI 16-bit transfer
whismanoid 53:3d5a3d241a5e 846 //
whismanoid 53:3d5a3d241a5e 847 // SPI MOSI = 1aaa_aaaa_0000_0000
whismanoid 53:3d5a3d241a5e 848 //
whismanoid 53:3d5a3d241a5e 849 // SPI MISO = xxxx_xxxx_dddd_dddd
whismanoid 53:3d5a3d241a5e 850 //
whismanoid 53:3d5a3d241a5e 851 // For 16-bit register size:
whismanoid 53:3d5a3d241a5e 852 //
whismanoid 53:3d5a3d241a5e 853 // SPI 24-bit or 32-bit transfer
whismanoid 53:3d5a3d241a5e 854 //
whismanoid 53:3d5a3d241a5e 855 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 856 //
whismanoid 53:3d5a3d241a5e 857 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 858 //
whismanoid 53:3d5a3d241a5e 859 // For 24-bit register size:
whismanoid 53:3d5a3d241a5e 860 //
whismanoid 53:3d5a3d241a5e 861 // SPI 32-bit transfer
whismanoid 53:3d5a3d241a5e 862 //
whismanoid 53:3d5a3d241a5e 863 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000
whismanoid 53:3d5a3d241a5e 864 //
whismanoid 53:3d5a3d241a5e 865 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 53:3d5a3d241a5e 866 //
whismanoid 53:3d5a3d241a5e 867 //
whismanoid 53:3d5a3d241a5e 868 // @return 1 on success; 0 on failure
whismanoid 53:3d5a3d241a5e 869 uint8_t MAX11043::RegRead(MAX11043_CMD_enum_t commandByte, uint32_t* ptrRegData)
whismanoid 53:3d5a3d241a5e 870 {
whismanoid 53:3d5a3d241a5e 871
whismanoid 53:3d5a3d241a5e 872 //----------------------------------------
whismanoid 53:3d5a3d241a5e 873 // switch based on register address szie RegSize(regAddress)
whismanoid 57:1c9da8e90737 874 //commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 875 switch(RegSize(commandByte))
whismanoid 53:3d5a3d241a5e 876 {
whismanoid 53:3d5a3d241a5e 877 case 8: // 8-bit register size
whismanoid 53:3d5a3d241a5e 878 {
whismanoid 60:d1d1eaa90fb7 879 // SPI 8+8 = 16-bit transfer
whismanoid 62:8223a7253c90 880 // 1234 5678 ___[1]_16
whismanoid 63:8f39d21d6157 881 // SPI MOSI = 1aaa_aaaa_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 882 // SPI MISO = xxxx_xxxx_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 883 size_t byteCount = 1 + 1;
whismanoid 63:8f39d21d6157 884 uint8_t mosiData[2];
whismanoid 63:8f39d21d6157 885 uint8_t misoData[2];
whismanoid 63:8f39d21d6157 886 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 887 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 888 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 889 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 890 if (ptrRegData) { (*ptrRegData) = misoData[1]; }
whismanoid 59:47538bcf6cda 891 if (commandByte == CMD_0001_1110_d8_Rd07_Status) {
whismanoid 59:47538bcf6cda 892 // TODO1: update status
whismanoid 63:8f39d21d6157 893 status = misoData[1];
whismanoid 59:47538bcf6cda 894 }
whismanoid 53:3d5a3d241a5e 895 }
whismanoid 53:3d5a3d241a5e 896 break;
whismanoid 53:3d5a3d241a5e 897 case 16: // 16-bit register size
whismanoid 63:8f39d21d6157 898 #warning "Not Verified Yet: MAX11043::RegRead 16-bit"
whismanoid 53:3d5a3d241a5e 899 {
whismanoid 60:d1d1eaa90fb7 900 // SPI 8+16 = 24-bit transfer
whismanoid 62:8223a7253c90 901 // 1234 5678 ___[1]_16 ___[2]_24
whismanoid 60:d1d1eaa90fb7 902 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 903 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 904 size_t byteCount = 1 + 2;
whismanoid 63:8f39d21d6157 905 uint8_t mosiData[3];
whismanoid 63:8f39d21d6157 906 uint8_t misoData[3];
whismanoid 63:8f39d21d6157 907 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 908 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 909 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 910 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 911 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 912 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 59:47538bcf6cda 913 if (commandByte == CMD_0010_0010_d16_Rd08_Configuration) {
whismanoid 59:47538bcf6cda 914 // TODO1: update config
whismanoid 63:8f39d21d6157 915 config = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 916 }
whismanoid 59:47538bcf6cda 917 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 918 // TODO1: update adca
whismanoid 63:8f39d21d6157 919 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 920 }
whismanoid 59:47538bcf6cda 921 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 922 // TODO1: update adcb
whismanoid 63:8f39d21d6157 923 adcb = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 924 }
whismanoid 59:47538bcf6cda 925 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 926 // TODO1: update adcc
whismanoid 63:8f39d21d6157 927 adcc = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 928 }
whismanoid 59:47538bcf6cda 929 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 930 // TODO1: update adcd
whismanoid 63:8f39d21d6157 931 adcd = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 932 }
whismanoid 53:3d5a3d241a5e 933 }
whismanoid 53:3d5a3d241a5e 934 break;
whismanoid 53:3d5a3d241a5e 935 case 24: // 24-bit register size
whismanoid 53:3d5a3d241a5e 936 {
whismanoid 60:d1d1eaa90fb7 937 // SPI 8+24 = 32-bit transfer
whismanoid 62:8223a7253c90 938 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32
whismanoid 63:8f39d21d6157 939 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 63:8f39d21d6157 940 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 63:8f39d21d6157 941 size_t byteCount = 1 + 3;
whismanoid 63:8f39d21d6157 942 uint8_t mosiData[4];
whismanoid 63:8f39d21d6157 943 uint8_t misoData[4];
whismanoid 63:8f39d21d6157 944 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 63:8f39d21d6157 945 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 946 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 947 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 63:8f39d21d6157 948 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 63:8f39d21d6157 949 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 63:8f39d21d6157 950 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 59:47538bcf6cda 951 if (commandByte == CMD_0000_0010_d16o8_Rd00_ADCa) {
whismanoid 59:47538bcf6cda 952 // TODO1: update adca
whismanoid 63:8f39d21d6157 953 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 954 }
whismanoid 59:47538bcf6cda 955 if (commandByte == CMD_0000_0110_d16o8_Rd01_ADCb) {
whismanoid 59:47538bcf6cda 956 // TODO1: update adcb
whismanoid 63:8f39d21d6157 957 adcb = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 958 }
whismanoid 59:47538bcf6cda 959 if (commandByte == CMD_0000_1010_d16o8_Rd02_ADCc) {
whismanoid 59:47538bcf6cda 960 // TODO1: update adcc
whismanoid 63:8f39d21d6157 961 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 962 }
whismanoid 59:47538bcf6cda 963 if (commandByte == CMD_0000_1110_d16o8_Rd03_ADCd) {
whismanoid 59:47538bcf6cda 964 // TODO1: update adcd
whismanoid 63:8f39d21d6157 965 adcd = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 966 }
whismanoid 59:47538bcf6cda 967 }
whismanoid 59:47538bcf6cda 968 break;
whismanoid 63:8f39d21d6157 969 case 32: // 32-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 970 //
whismanoid 63:8f39d21d6157 971 #warning "Not Implemented Yet: MAX11043::RegRead 32-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 972 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 973 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 974 // update adca, adcb
whismanoid 59:47538bcf6cda 975 //
whismanoid 63:8f39d21d6157 976 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 977 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 978 // update adcc, adcd
whismanoid 59:47538bcf6cda 979 //
whismanoid 59:47538bcf6cda 980 {
whismanoid 60:d1d1eaa90fb7 981 // SPI 8+32 = 40-bit transfer
whismanoid 62:8223a7253c90 982 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40
whismanoid 60:d1d1eaa90fb7 983 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 984 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 985 size_t byteCount = 1 + (2 * 2);
whismanoid 62:8223a7253c90 986 uint8_t mosiData[5];
whismanoid 62:8223a7253c90 987 uint8_t misoData[5];
whismanoid 62:8223a7253c90 988 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 989 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 990 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 991 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 992 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 993 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 994 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 995 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 996 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 997 // TODO1: update adca
whismanoid 62:8223a7253c90 998 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 999 // TODO1: update adcb
whismanoid 62:8223a7253c90 1000 adcb = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 1001 }
whismanoid 63:8f39d21d6157 1002 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 1003 // TODO1: update adcc
whismanoid 62:8223a7253c90 1004 adcc = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 1005 // TODO1: update adcd
whismanoid 62:8223a7253c90 1006 adcd = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 1007 }
whismanoid 59:47538bcf6cda 1008 }
whismanoid 59:47538bcf6cda 1009 break;
whismanoid 63:8f39d21d6157 1010 case 48: // 48-bit register size CMD_0001_0010_d16o8_d16o8_Rd04_ADCab, CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 1011 //
whismanoid 63:8f39d21d6157 1012 #warning "Not Verified Yet: MAX11043::RegRead 48-bit CMD_0001_0010_d16o8_d16o8_Rd04_ADCab"
whismanoid 63:8f39d21d6157 1013 // TODO: support long SPI read CMD_0001_0010_d16o8_d16o8_Rd04_ADCab
whismanoid 59:47538bcf6cda 1014 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 1015 // update adca, adcb
whismanoid 59:47538bcf6cda 1016 //
whismanoid 63:8f39d21d6157 1017 // TODO: support long SPI read CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd
whismanoid 59:47538bcf6cda 1018 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 1019 // update adcc, adcd
whismanoid 59:47538bcf6cda 1020 //
whismanoid 59:47538bcf6cda 1021 {
whismanoid 60:d1d1eaa90fb7 1022 // SPI 8+48 = 56-bit transfer
whismanoid 62:8223a7253c90 1023 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56
whismanoid 60:d1d1eaa90fb7 1024 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 1025 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 1026 size_t byteCount = 1 + (3 * 2);
whismanoid 62:8223a7253c90 1027 uint8_t mosiData[7];
whismanoid 62:8223a7253c90 1028 uint8_t misoData[7];
whismanoid 62:8223a7253c90 1029 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 1030 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1031 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1032 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1033 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1034 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1035 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1036 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 1037 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 1038 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 1039 if (commandByte == CMD_0001_0010_d16o8_d16o8_Rd04_ADCab) {
whismanoid 59:47538bcf6cda 1040 // TODO1: update adca
whismanoid 62:8223a7253c90 1041 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 1042 // TODO1: update adcb
whismanoid 62:8223a7253c90 1043 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 1044 }
whismanoid 63:8f39d21d6157 1045 if (commandByte == CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd) {
whismanoid 59:47538bcf6cda 1046 // TODO1: update adcc
whismanoid 62:8223a7253c90 1047 adcc = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 1048 // TODO1: update adcd
whismanoid 62:8223a7253c90 1049 adcd = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 1050 }
whismanoid 59:47538bcf6cda 1051 }
whismanoid 59:47538bcf6cda 1052 break;
whismanoid 63:8f39d21d6157 1053 case 64: // 64-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 1054 //
whismanoid 63:8f39d21d6157 1055 #warning "Not Verified Yet: MAX11043::RegRead 64-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 1056 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 1057 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1058 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 1059 //
whismanoid 59:47538bcf6cda 1060 {
whismanoid 60:d1d1eaa90fb7 1061 // SPI 8+64 = 72-bit transfer
whismanoid 62:8223a7253c90 1062 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72
whismanoid 60:d1d1eaa90fb7 1063 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 1064 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 1065 size_t byteCount = 1 + (2 * 4);
whismanoid 62:8223a7253c90 1066 uint8_t mosiData[9];
whismanoid 62:8223a7253c90 1067 uint8_t misoData[9];
whismanoid 62:8223a7253c90 1068 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 1069 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1070 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1071 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1072 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1073 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1074 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1075 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1076 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1077 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 1078 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 1079 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 8) | misoData[2]; }
whismanoid 63:8f39d21d6157 1080 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 1081 // TODO1: update adca
whismanoid 62:8223a7253c90 1082 adca = (misoData[1] << 8) | misoData[2];
whismanoid 59:47538bcf6cda 1083 // TODO1: update adcb
whismanoid 62:8223a7253c90 1084 adcb = (misoData[3] << 8) | misoData[4];
whismanoid 59:47538bcf6cda 1085 // TODO1: update adcc
whismanoid 62:8223a7253c90 1086 adcc = (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 1087 // TODO1: update adcd
whismanoid 62:8223a7253c90 1088 adcd = (misoData[7] << 8) | misoData[8];
whismanoid 59:47538bcf6cda 1089 }
whismanoid 59:47538bcf6cda 1090 }
whismanoid 59:47538bcf6cda 1091 break;
whismanoid 63:8f39d21d6157 1092 case 96: // 96-bit register size CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 1093 //
whismanoid 63:8f39d21d6157 1094 #warning "Not Verified Yet: MAX11043::RegRead 96-bit CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd"
whismanoid 63:8f39d21d6157 1095 // TODO: support long SPI read CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd
whismanoid 59:47538bcf6cda 1096 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1097 // update adca, adcb, adcc, adcd
whismanoid 59:47538bcf6cda 1098 //
whismanoid 59:47538bcf6cda 1099 {
whismanoid 60:d1d1eaa90fb7 1100 // SPI 8+96 = 104-bit transfer
whismanoid 62:8223a7253c90 1101 // 1234 5678 ___[1]_16 ___[2]_24 ___[3]_32 ___[4]_40 ___[5]_48 ___[6]_56 ___[7]_64 ___[8]_72 ___[9]_80 __[10]_88 __[11]_96 __[12]104
whismanoid 60:d1d1eaa90fb7 1102 // SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ... _0000
whismanoid 60:d1d1eaa90fb7 1103 // SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd_dddd ... _xxxx
whismanoid 62:8223a7253c90 1104 size_t byteCount = 1 + (3 * 4);
whismanoid 62:8223a7253c90 1105 uint8_t mosiData[13];
whismanoid 62:8223a7253c90 1106 uint8_t misoData[13];
whismanoid 62:8223a7253c90 1107 mosiData[0] = CMDOP_0aaa_aa10_ReadRegister | commandByte;
whismanoid 62:8223a7253c90 1108 mosiData[1] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1109 mosiData[2] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1110 mosiData[3] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1111 mosiData[4] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1112 mosiData[5] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1113 mosiData[6] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1114 mosiData[7] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1115 mosiData[8] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1116 mosiData[9] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1117 mosiData[10] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1118 mosiData[11] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1119 mosiData[12] = 0; // CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 62:8223a7253c90 1120 // SPIreadWriteWithLowCS(size_t byteCount, uint8_t mosiData[], uint8_t misoData[]);
whismanoid 62:8223a7253c90 1121 SPIreadWriteWithLowCS(byteCount, mosiData, misoData);
whismanoid 62:8223a7253c90 1122 if (ptrRegData) { (*ptrRegData) = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3]; }
whismanoid 63:8f39d21d6157 1123 if (commandByte == CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd) {
whismanoid 59:47538bcf6cda 1124 // TODO1: update adca
whismanoid 62:8223a7253c90 1125 adca = (misoData[1] << 16) | (misoData[2] << 8) | misoData[3];
whismanoid 59:47538bcf6cda 1126 // TODO1: update adcb
whismanoid 62:8223a7253c90 1127 adcb = (misoData[4] << 16) | (misoData[5] << 8) | misoData[6];
whismanoid 59:47538bcf6cda 1128 // TODO1: update adcc
whismanoid 62:8223a7253c90 1129 adcc = (misoData[7] << 16) | (misoData[8] << 8) | misoData[9];
whismanoid 59:47538bcf6cda 1130 // TODO1: update adcd
whismanoid 62:8223a7253c90 1131 adcd = (misoData[10] << 16) | (misoData[11] << 8) | misoData[12];
whismanoid 59:47538bcf6cda 1132 }
whismanoid 53:3d5a3d241a5e 1133 }
whismanoid 53:3d5a3d241a5e 1134 break;
whismanoid 53:3d5a3d241a5e 1135 }
whismanoid 53:3d5a3d241a5e 1136
whismanoid 53:3d5a3d241a5e 1137 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1138 // success
whismanoid 53:3d5a3d241a5e 1139 return 1;
whismanoid 53:3d5a3d241a5e 1140 }
whismanoid 53:3d5a3d241a5e 1141
whismanoid 53:3d5a3d241a5e 1142 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1143 // Return the size of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1144 //
whismanoid 53:3d5a3d241a5e 1145 // @return 8 for 8-bit, 16 for 16-bit, 24 for 24-bit, else 0 for undefined register size
whismanoid 53:3d5a3d241a5e 1146 uint8_t MAX11043::RegSize(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1147 {
whismanoid 53:3d5a3d241a5e 1148
whismanoid 53:3d5a3d241a5e 1149 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1150 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 1151 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 1152 switch(commandByte)
whismanoid 53:3d5a3d241a5e 1153 {
whismanoid 53:3d5a3d241a5e 1154 default:
whismanoid 57:1c9da8e90737 1155 // case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 1156 // case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 1157 // case CMDOP_1111_1111_NoOperationMOSIidleHigh:
whismanoid 53:3d5a3d241a5e 1158 return 0; // undefined register size
whismanoid 53:3d5a3d241a5e 1159 case CMD_0001_1110_d8_Rd07_Status:
whismanoid 53:3d5a3d241a5e 1160 case CMD_0101_0100_d8_Wr15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 1161 case CMD_0101_0110_d8_Rd15_FilterCAddress:
whismanoid 53:3d5a3d241a5e 1162 case CMD_0110_0000_d8_Wr18_FlashMode:
whismanoid 53:3d5a3d241a5e 1163 case CMD_0110_0010_d8_Rd18_FlashMode:
whismanoid 53:3d5a3d241a5e 1164 return 8; // 8-bit register size
whismanoid 53:3d5a3d241a5e 1165 case CMD_0010_0000_d16_Wr08_Configuration:
whismanoid 53:3d5a3d241a5e 1166 case CMD_0010_0010_d16_Rd08_Configuration:
whismanoid 53:3d5a3d241a5e 1167 case CMD_0010_0100_d16_Wr09_DAC:
whismanoid 53:3d5a3d241a5e 1168 case CMD_0010_0110_d16_Rd09_DAC:
whismanoid 53:3d5a3d241a5e 1169 case CMD_0010_1000_d16_Wr0A_DACStep:
whismanoid 53:3d5a3d241a5e 1170 case CMD_0010_1010_d16_Rd0A_DACStep:
whismanoid 53:3d5a3d241a5e 1171 case CMD_0010_1100_d16_Wr0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 1172 case CMD_0010_1110_d16_Rd0B_DACHDACL:
whismanoid 53:3d5a3d241a5e 1173 case CMD_0011_0000_d16_Wr0C_ConfigA:
whismanoid 53:3d5a3d241a5e 1174 case CMD_0011_0010_d16_Rd0C_ConfigA:
whismanoid 53:3d5a3d241a5e 1175 case CMD_0011_0100_d16_Wr0D_ConfigB:
whismanoid 53:3d5a3d241a5e 1176 case CMD_0011_0110_d16_Rd0D_ConfigB:
whismanoid 53:3d5a3d241a5e 1177 case CMD_0011_1000_d16_Wr0E_ConfigC:
whismanoid 53:3d5a3d241a5e 1178 case CMD_0011_1010_d16_Rd0E_ConfigC:
whismanoid 53:3d5a3d241a5e 1179 case CMD_0011_1100_d16_Wr0F_ConfigD:
whismanoid 53:3d5a3d241a5e 1180 case CMD_0011_1110_d16_Rd0F_ConfigD:
whismanoid 53:3d5a3d241a5e 1181 case CMD_0100_0000_d16_Wr10_Reference:
whismanoid 53:3d5a3d241a5e 1182 case CMD_0100_0010_d16_Rd10_Reference:
whismanoid 53:3d5a3d241a5e 1183 case CMD_0100_0100_d16_Wr11_AGain:
whismanoid 53:3d5a3d241a5e 1184 case CMD_0100_0110_d16_Rd11_AGain:
whismanoid 53:3d5a3d241a5e 1185 case CMD_0100_1000_d16_Wr12_BGain:
whismanoid 53:3d5a3d241a5e 1186 case CMD_0100_1010_d16_Rd12_BGain:
whismanoid 53:3d5a3d241a5e 1187 case CMD_0100_1100_d16_Wr13_CGain:
whismanoid 53:3d5a3d241a5e 1188 case CMD_0100_1110_d16_Rd13_CGain:
whismanoid 53:3d5a3d241a5e 1189 case CMD_0101_0000_d16_Wr14_DGain:
whismanoid 53:3d5a3d241a5e 1190 case CMD_0101_0010_d16_Rd14_DGain:
whismanoid 53:3d5a3d241a5e 1191 case CMD_0110_0100_d16_Wr19_FlashAddr:
whismanoid 53:3d5a3d241a5e 1192 case CMD_0110_0110_d16_Rd19_FlashAddr:
whismanoid 53:3d5a3d241a5e 1193 case CMD_0110_1000_d16_Wr1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 1194 case CMD_0110_1010_d16_Rd1A_FlashDataIn:
whismanoid 53:3d5a3d241a5e 1195 case CMD_0110_1110_d16_Rd1B_FlashDataOut:
whismanoid 53:3d5a3d241a5e 1196 return 16; // 16-bit register size
whismanoid 59:47538bcf6cda 1197 case CMD_0000_0010_d16o8_Rd00_ADCa:
whismanoid 59:47538bcf6cda 1198 case CMD_0000_0110_d16o8_Rd01_ADCb:
whismanoid 59:47538bcf6cda 1199 case CMD_0000_1010_d16o8_Rd02_ADCc:
whismanoid 59:47538bcf6cda 1200 case CMD_0000_1110_d16o8_Rd03_ADCd:
whismanoid 59:47538bcf6cda 1201 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1202 {
whismanoid 59:47538bcf6cda 1203 // %SW 0x02 (0 0 0) -- for 24-bit read
whismanoid 59:47538bcf6cda 1204 return 24; // 24-bit register size
whismanoid 59:47538bcf6cda 1205 }
whismanoid 59:47538bcf6cda 1206 // %SW 0x02 (0 0) -- for 16-bit read
whismanoid 59:47538bcf6cda 1207 //
whismanoid 59:47538bcf6cda 1208 return 16; // 16-bit register size
whismanoid 63:8f39d21d6157 1209 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab:
whismanoid 63:8f39d21d6157 1210 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd:
whismanoid 59:47538bcf6cda 1211 //
whismanoid 59:47538bcf6cda 1212 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 1213 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1214 {
whismanoid 59:47538bcf6cda 1215 // %SW 0x12 (0 0 0) (0 0 0) -- for 24-bit read A,B
whismanoid 59:47538bcf6cda 1216 // %SW 0x16 (0 0 0) (0 0 0) -- for 24-bit read C,D
whismanoid 59:47538bcf6cda 1217 return 48; // 48-bit register size: 2*(24)
whismanoid 59:47538bcf6cda 1218 }
whismanoid 59:47538bcf6cda 1219 // %SW 0x12 (0 0) (0 0) -- for 16-bit read A,B
whismanoid 59:47538bcf6cda 1220 // %SW 0x16 (0 0) (0 0) -- for 16-bit read C,D
whismanoid 59:47538bcf6cda 1221 //
whismanoid 59:47538bcf6cda 1222 return 32; // 32-bit register size: 2*(16)
whismanoid 63:8f39d21d6157 1223 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd:
whismanoid 59:47538bcf6cda 1224 //
whismanoid 59:47538bcf6cda 1225 // TODO: support long SPI read
whismanoid 59:47538bcf6cda 1226 if (config & CONFIG_xxxx_xxxx_xx1x_xxxx_24BIT)
whismanoid 59:47538bcf6cda 1227 {
whismanoid 59:47538bcf6cda 1228 // %SW 0x1A (0 0 0) (0 0 0) (0 0 0) (0 0 0) -- for 24-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1229 return 96; // 96-bit register size: 4*(24)
whismanoid 59:47538bcf6cda 1230 }
whismanoid 59:47538bcf6cda 1231 // %SW 0x1A (0 0) (0 0) (0 0) (0 0) -- for 16-bit read A,B,C,D
whismanoid 59:47538bcf6cda 1232 //
whismanoid 59:47538bcf6cda 1233 return 64; // 64-bit register size: 4*(16)
whismanoid 53:3d5a3d241a5e 1234 case CMD_0101_1000_d32_Wr16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 1235 case CMD_0101_1010_d32_Rd16_FilterCDataOut:
whismanoid 53:3d5a3d241a5e 1236 case CMD_0101_1100_d32_Wr17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 1237 case CMD_0101_1110_d32_Rd17_FilterCDataIn:
whismanoid 53:3d5a3d241a5e 1238 return 32; // 32-bit register size
whismanoid 53:3d5a3d241a5e 1239 }
whismanoid 53:3d5a3d241a5e 1240 }
whismanoid 53:3d5a3d241a5e 1241
whismanoid 53:3d5a3d241a5e 1242 //----------------------------------------
whismanoid 57:1c9da8e90737 1243 // Decode operation from commandByte
whismanoid 57:1c9da8e90737 1244 //
whismanoid 57:1c9da8e90737 1245 // @return operation such as idle, read register, write register, etc.
whismanoid 57:1c9da8e90737 1246 MAX11043::MAX11043_CMDOP_enum_t MAX11043::DecodeCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 57:1c9da8e90737 1247 {
whismanoid 57:1c9da8e90737 1248
whismanoid 57:1c9da8e90737 1249 //----------------------------------------
whismanoid 57:1c9da8e90737 1250 // decode operation from command byte
whismanoid 57:1c9da8e90737 1251 switch (commandByte & 0x83)
whismanoid 57:1c9da8e90737 1252 {
whismanoid 57:1c9da8e90737 1253 case CMDOP_0aaa_aa10_ReadRegister:
whismanoid 57:1c9da8e90737 1254 return CMDOP_0aaa_aa10_ReadRegister;
whismanoid 57:1c9da8e90737 1255 case CMDOP_0aaa_aa00_WriteRegister:
whismanoid 57:1c9da8e90737 1256 return CMDOP_0aaa_aa00_WriteRegister;
whismanoid 57:1c9da8e90737 1257 default:
whismanoid 57:1c9da8e90737 1258 return CMDOP_1111_1111_NoOperationMOSIidleHigh;
whismanoid 57:1c9da8e90737 1259 }
whismanoid 57:1c9da8e90737 1260 }
whismanoid 57:1c9da8e90737 1261
whismanoid 57:1c9da8e90737 1262 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1263 // Return the address field of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1264 //
whismanoid 53:3d5a3d241a5e 1265 // @return register address field as given in datasheet
whismanoid 53:3d5a3d241a5e 1266 uint8_t MAX11043::RegAddrOfCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1267 {
whismanoid 53:3d5a3d241a5e 1268
whismanoid 53:3d5a3d241a5e 1269 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1270 // extract register address value from command byte
whismanoid 57:1c9da8e90737 1271 return (uint8_t)((commandByte &~ 0x83) >> 2); // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 1272 }
whismanoid 53:3d5a3d241a5e 1273
whismanoid 53:3d5a3d241a5e 1274 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1275 // Test whether a command byte is a register read command
whismanoid 53:3d5a3d241a5e 1276 //
whismanoid 53:3d5a3d241a5e 1277 // @return true if command byte is a register read command
whismanoid 53:3d5a3d241a5e 1278 uint8_t MAX11043::IsRegReadCommand(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1279 {
whismanoid 53:3d5a3d241a5e 1280
whismanoid 53:3d5a3d241a5e 1281 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1282 // Test whether a command byte is a register read command
whismanoid 57:1c9da8e90737 1283 return (commandByte &~ 0x02) ? 1 : 0; // CMDOP_0aaa_aa10_ReadRegister
whismanoid 53:3d5a3d241a5e 1284 }
whismanoid 53:3d5a3d241a5e 1285
whismanoid 53:3d5a3d241a5e 1286 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1287 // Return the name of a MAX11043 register
whismanoid 53:3d5a3d241a5e 1288 //
whismanoid 53:3d5a3d241a5e 1289 // @return null-terminated constant C string containing register name or empty string
whismanoid 53:3d5a3d241a5e 1290 const char* MAX11043::RegName(MAX11043_CMD_enum_t commandByte)
whismanoid 53:3d5a3d241a5e 1291 {
whismanoid 53:3d5a3d241a5e 1292
whismanoid 53:3d5a3d241a5e 1293 //----------------------------------------
whismanoid 53:3d5a3d241a5e 1294 // switch based on register address value regAddress
whismanoid 57:1c9da8e90737 1295 // commandByte = (MAX11043_CMD_enum_t)((commandByte &~ CMDOP_0aaa_aa10_ReadRegister) & 0xFF);
whismanoid 53:3d5a3d241a5e 1296 switch(commandByte)
whismanoid 53:3d5a3d241a5e 1297 {
whismanoid 53:3d5a3d241a5e 1298 default:
whismanoid 53:3d5a3d241a5e 1299 return ""; // undefined register
whismanoid 57:1c9da8e90737 1300 // case CMDOP_0aaa_aa00_WriteRegister: return "_______";
whismanoid 57:1c9da8e90737 1301 // case CMDOP_0aaa_aa10_ReadRegister: return "_______";
whismanoid 57:1c9da8e90737 1302 // case CMDOP_1111_1111_NoOperationMOSIidleHigh: return "_______";
whismanoid 59:47538bcf6cda 1303 case CMD_0000_0010_d16o8_Rd00_ADCa: return "ADCa";
whismanoid 59:47538bcf6cda 1304 case CMD_0000_0110_d16o8_Rd01_ADCb: return "ADCb";
whismanoid 59:47538bcf6cda 1305 case CMD_0000_1010_d16o8_Rd02_ADCc: return "ADCc";
whismanoid 59:47538bcf6cda 1306 case CMD_0000_1110_d16o8_Rd03_ADCd: return "ADCd";
whismanoid 63:8f39d21d6157 1307 case CMD_0001_0010_d16o8_d16o8_Rd04_ADCab: return "ADCab";
whismanoid 63:8f39d21d6157 1308 case CMD_0001_0110_d16o8_d16o8_Rd05_ADCcd: return "ADCcd";
whismanoid 63:8f39d21d6157 1309 case CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd: return "ADCabcd";
whismanoid 53:3d5a3d241a5e 1310 case CMD_0001_1110_d8_Rd07_Status: return "Status";
whismanoid 53:3d5a3d241a5e 1311 case CMD_0010_0000_d16_Wr08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1312 case CMD_0010_0010_d16_Rd08_Configuration: return "Configuration";
whismanoid 53:3d5a3d241a5e 1313 case CMD_0010_0100_d16_Wr09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1314 case CMD_0010_0110_d16_Rd09_DAC: return "DAC";
whismanoid 53:3d5a3d241a5e 1315 case CMD_0010_1000_d16_Wr0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1316 case CMD_0010_1010_d16_Rd0A_DACStep: return "DACStep";
whismanoid 53:3d5a3d241a5e 1317 case CMD_0010_1100_d16_Wr0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1318 case CMD_0010_1110_d16_Rd0B_DACHDACL: return "DACHDACL";
whismanoid 53:3d5a3d241a5e 1319 case CMD_0011_0000_d16_Wr0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1320 case CMD_0011_0010_d16_Rd0C_ConfigA: return "ConfigA";
whismanoid 53:3d5a3d241a5e 1321 case CMD_0011_0100_d16_Wr0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1322 case CMD_0011_0110_d16_Rd0D_ConfigB: return "ConfigB";
whismanoid 53:3d5a3d241a5e 1323 case CMD_0011_1000_d16_Wr0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1324 case CMD_0011_1010_d16_Rd0E_ConfigC: return "ConfigC";
whismanoid 53:3d5a3d241a5e 1325 case CMD_0011_1100_d16_Wr0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1326 case CMD_0011_1110_d16_Rd0F_ConfigD: return "ConfigD";
whismanoid 53:3d5a3d241a5e 1327 case CMD_0100_0000_d16_Wr10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1328 case CMD_0100_0010_d16_Rd10_Reference: return "Reference";
whismanoid 53:3d5a3d241a5e 1329 case CMD_0100_0100_d16_Wr11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1330 case CMD_0100_0110_d16_Rd11_AGain: return "AGain";
whismanoid 53:3d5a3d241a5e 1331 case CMD_0100_1000_d16_Wr12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1332 case CMD_0100_1010_d16_Rd12_BGain: return "BGain";
whismanoid 53:3d5a3d241a5e 1333 case CMD_0100_1100_d16_Wr13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1334 case CMD_0100_1110_d16_Rd13_CGain: return "CGain";
whismanoid 53:3d5a3d241a5e 1335 case CMD_0101_0000_d16_Wr14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1336 case CMD_0101_0010_d16_Rd14_DGain: return "DGain";
whismanoid 53:3d5a3d241a5e 1337 case CMD_0101_0100_d8_Wr15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1338 case CMD_0101_0110_d8_Rd15_FilterCAddress: return "FilterCAddress";
whismanoid 53:3d5a3d241a5e 1339 case CMD_0101_1000_d32_Wr16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1340 case CMD_0101_1010_d32_Rd16_FilterCDataOut: return "FilterCDataOut";
whismanoid 53:3d5a3d241a5e 1341 case CMD_0101_1100_d32_Wr17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1342 case CMD_0101_1110_d32_Rd17_FilterCDataIn: return "FilterCDataIn";
whismanoid 53:3d5a3d241a5e 1343 case CMD_0110_0000_d8_Wr18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1344 case CMD_0110_0010_d8_Rd18_FlashMode: return "FlashMode";
whismanoid 53:3d5a3d241a5e 1345 case CMD_0110_0100_d16_Wr19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1346 case CMD_0110_0110_d16_Rd19_FlashAddr: return "FlashAddr";
whismanoid 53:3d5a3d241a5e 1347 case CMD_0110_1000_d16_Wr1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1348 case CMD_0110_1010_d16_Rd1A_FlashDataIn: return "FlashDataIn";
whismanoid 53:3d5a3d241a5e 1349 case CMD_0110_1110_d16_Rd1B_FlashDataOut: return "FlashDataOut";
whismanoid 53:3d5a3d241a5e 1350 }
whismanoid 53:3d5a3d241a5e 1351 }
whismanoid 53:3d5a3d241a5e 1352
whismanoid 59:47538bcf6cda 1353 //----------------------------------------
whismanoid 64:a667cfd83492 1354 // Menu item '$' -> adca, adcb, adcc, adcd
whismanoid 64:a667cfd83492 1355 // Read ADCabcd
whismanoid 64:a667cfd83492 1356 //
whismanoid 64:a667cfd83492 1357 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1358 uint8_t MAX11043::Read_ADCabcd(void)
whismanoid 64:a667cfd83492 1359 {
whismanoid 64:a667cfd83492 1360
whismanoid 64:a667cfd83492 1361 //----------------------------------------
whismanoid 64:a667cfd83492 1362 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1363 #warning "Not Tested Yet: MAX11043::Read_ADCabcd..."
whismanoid 64:a667cfd83492 1364
whismanoid 69:989e392cf635 1365 //--------------------------------------------------
whismanoid 69:989e392cf635 1366 // MAX11043 ADC Read operations must be synchronized to EOC End Of Conversion
whismanoid 69:989e392cf635 1367 // EOC# asserts low when new data is available.
whismanoid 69:989e392cf635 1368 // Initiate a data read prior to the next rising edge of EOC# or the result is overwritten.
whismanoid 69:989e392cf635 1369 #if MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1370 // MAX11043 EOC End Of Conversion input should be InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 1371 // Workaround using DigitalIn(PinName:EOC_pin) polled to sync with EOC falling edge for ADC reads
whismanoid 69:989e392cf635 1372 // 2020-02-20 MAX11043_EOC_INTERRUPT_POLLING works on MAX32625MBED at 9us conversion rate, with 1us timing margin
whismanoid 69:989e392cf635 1373 // TODO: poll m_EOC_pin if CONVRUN is high
whismanoid 69:989e392cf635 1374 if (m_CONVRUN_pin)
whismanoid 69:989e392cf635 1375 {
whismanoid 69:989e392cf635 1376 #warning "MAX11043::Read_ADCabcd() Potential infinite loop if EOC pin not connected"
whismanoid 69:989e392cf635 1377 // possible infinite loop; need a timeout or futility countdown to escape
whismanoid 69:989e392cf635 1378 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 1379 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 1380 (m_EOC_pin != 1));
whismanoid 69:989e392cf635 1381 futility_countdown--)
whismanoid 69:989e392cf635 1382 {
whismanoid 69:989e392cf635 1383 // spinlock waiting for logic high pin state (start of new conversion)
whismanoid 69:989e392cf635 1384 }
whismanoid 69:989e392cf635 1385 for (int futility_countdown = 100;
whismanoid 69:989e392cf635 1386 ((futility_countdown > 0) &&
whismanoid 69:989e392cf635 1387 (m_EOC_pin != 0));
whismanoid 69:989e392cf635 1388 futility_countdown--)
whismanoid 69:989e392cf635 1389 {
whismanoid 69:989e392cf635 1390 // spinlock waiting for logic low pin state (new data is available)
whismanoid 69:989e392cf635 1391 }
whismanoid 69:989e392cf635 1392 }
whismanoid 69:989e392cf635 1393 else
whismanoid 69:989e392cf635 1394 {
whismanoid 69:989e392cf635 1395 // CONVRUN pin is being driven low, so conversion result will not change, EOC# remains high
whismanoid 69:989e392cf635 1396 }
whismanoid 69:989e392cf635 1397 #else // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1398 // MAX11043 EOC End Of Conversion input is InterruptIn(PinName:EOC_pin).fall(onEOCFallingEdge);
whismanoid 69:989e392cf635 1399 #endif // MAX11043_EOC_INTERRUPT_POLLING
whismanoid 69:989e392cf635 1400 //--------------------------------------------------
whismanoid 69:989e392cf635 1401
whismanoid 64:a667cfd83492 1402 //----------------------------------------
whismanoid 64:a667cfd83492 1403 // read register ADCabcd -> &adca, &adcb, &adcc, &adcd
whismanoid 64:a667cfd83492 1404 RegRead(CMD_0001_1010_d16o8_d16o8_d16o8_d16o8_Rd06_ADCabcd, 0);
whismanoid 64:a667cfd83492 1405
whismanoid 64:a667cfd83492 1406 //----------------------------------------
whismanoid 64:a667cfd83492 1407 // success
whismanoid 64:a667cfd83492 1408 return 1;
whismanoid 64:a667cfd83492 1409 }
whismanoid 64:a667cfd83492 1410
whismanoid 64:a667cfd83492 1411 //----------------------------------------
whismanoid 66:3fe92f6f1cfa 1412 // Menu item 'GA'
whismanoid 64:a667cfd83492 1413 // Write AGain register
whismanoid 64:a667cfd83492 1414 //
whismanoid 64:a667cfd83492 1415 // @param[in] gain 2's complement, 0x800=0.25V/V, 0x1000=0.5V/V, 0x2000=1VV/V, 0x4000=2V/V, default=0x2000
whismanoid 64:a667cfd83492 1416 //
whismanoid 64:a667cfd83492 1417 // @return 1 on success; 0 on failure
whismanoid 64:a667cfd83492 1418 uint8_t MAX11043::Write_AGain(uint32_t gain)
whismanoid 64:a667cfd83492 1419 {
whismanoid 64:a667cfd83492 1420
whismanoid 64:a667cfd83492 1421 //----------------------------------------
whismanoid 64:a667cfd83492 1422 // warning -- WIP work in progress
whismanoid 64:a667cfd83492 1423 #warning "Not Tested Yet: MAX11043::Write_AGain..."
whismanoid 64:a667cfd83492 1424
whismanoid 64:a667cfd83492 1425 //----------------------------------------
whismanoid 64:a667cfd83492 1426 // write register
whismanoid 64:a667cfd83492 1427 RegWrite(CMD_0100_0100_d16_Wr11_AGain, gain);
whismanoid 64:a667cfd83492 1428
whismanoid 64:a667cfd83492 1429 //----------------------------------------
whismanoid 64:a667cfd83492 1430 // success
whismanoid 64:a667cfd83492 1431 return 1;
whismanoid 64:a667cfd83492 1432 }
whismanoid 64:a667cfd83492 1433
whismanoid 64:a667cfd83492 1434 //----------------------------------------
whismanoid 59:47538bcf6cda 1435 // Menu item 'XX'
whismanoid 59:47538bcf6cda 1436 //
whismanoid 59:47538bcf6cda 1437 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1438 uint8_t MAX11043::Configure_XXXXX(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1439 {
whismanoid 59:47538bcf6cda 1440
whismanoid 59:47538bcf6cda 1441 //----------------------------------------
whismanoid 59:47538bcf6cda 1442 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1443 #warning "Not Tested Yet: MAX11043::Configure_XXXXX..."
whismanoid 59:47538bcf6cda 1444
whismanoid 59:47538bcf6cda 1445 //----------------------------------------
whismanoid 59:47538bcf6cda 1446 // read register
whismanoid 59:47538bcf6cda 1447 RegRead(CMD_0000_0010_d16o8_Rd00_ADCa, &adca);
whismanoid 59:47538bcf6cda 1448
whismanoid 59:47538bcf6cda 1449 //----------------------------------------
whismanoid 59:47538bcf6cda 1450 // success
whismanoid 59:47538bcf6cda 1451 return 1;
whismanoid 59:47538bcf6cda 1452 }
whismanoid 59:47538bcf6cda 1453
whismanoid 59:47538bcf6cda 1454 //----------------------------------------
whismanoid 59:47538bcf6cda 1455 // Menu item 'XY'
whismanoid 59:47538bcf6cda 1456 //
whismanoid 59:47538bcf6cda 1457 // @return 1 on success; 0 on failure
whismanoid 59:47538bcf6cda 1458 uint8_t MAX11043::Configure_XXXXY(uint8_t linef, uint8_t rate)
whismanoid 59:47538bcf6cda 1459 {
whismanoid 59:47538bcf6cda 1460
whismanoid 59:47538bcf6cda 1461 //----------------------------------------
whismanoid 59:47538bcf6cda 1462 // warning -- WIP work in progress
whismanoid 59:47538bcf6cda 1463 #warning "Not Tested Yet: MAX11043::Configure_XXXXY..."
whismanoid 59:47538bcf6cda 1464
whismanoid 59:47538bcf6cda 1465 //----------------------------------------
whismanoid 59:47538bcf6cda 1466 // read register
whismanoid 59:47538bcf6cda 1467 RegRead(CMD_0001_1110_d8_Rd07_Status, &status);
whismanoid 59:47538bcf6cda 1468
whismanoid 59:47538bcf6cda 1469 //----------------------------------------
whismanoid 59:47538bcf6cda 1470 // success
whismanoid 59:47538bcf6cda 1471 return 1;
whismanoid 59:47538bcf6cda 1472 }
whismanoid 59:47538bcf6cda 1473
whismanoid 53:3d5a3d241a5e 1474
whismanoid 53:3d5a3d241a5e 1475 // End of file