Rajath Ravi
/
ravi_blinkycode
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Revision 0:34ee385f4d2d, committed 2021-10-23
- Comitter:
- rajathr
- Date:
- Sat Oct 23 05:49:09 2021 +0000
- Commit message:
- At 23rd Oct 21 - All Code
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/gpio.c Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,194 @@
+#include "gpio.h"
+#include "main_Lec9.h"
+#include "stm32f4xx_rcc_mort.h"
+
+
+/* Below are defined Address of Port B and corresponding registers*/
+#define PORTB_BASE_ADDRESS ((uint32_t)0x40020400)
+#define PORTB_MODER_REGISTER (PORTB_BASE_ADDRESS + 0x00)
+#define PORTB_OTYPER_REGISTER (PORTB_BASE_ADDRESS + 0x04)
+#define PORTB_OSPEEDR_REGISTER (PORTB_BASE_ADDRESS + 0x08)
+#define PORTB_PUPDR_REGISTER (PORTB_BASE_ADDRESS + 0x0C)
+#define PORTB_IDR_REGISTER (PORTB_BASE_ADDRESS + 0x10)
+#define PORTB_ODR_REGISTER (PORTB_BASE_ADDRESS + 0x14)
+#define PORTB_AFR1_REGISTER (PORTB_BASE_ADDRESS + 0x20)
+
+/* Below are defined Address of Port C and corresponding registers*/
+#define PORTC_BASE_ADDRESS ((uint32_t)0x40020800)
+#define PORTC_MODER_REGISTER (PORTC_BASE_ADDRESS + 0x00)
+#define PORTC_OTYPER_REGISTER (PORTC_BASE_ADDRESS + 0x04)
+#define PORTC_OSPEEDR_REGISTER (PORTC_BASE_ADDRESS + 0x08)
+#define PORTC_PUPDR_REGISTER (PORTC_BASE_ADDRESS + 0x0C)
+#define PORTC_IDR_REGISTER (PORTC_BASE_ADDRESS + 0x10)
+#define PORTC_ODR_REGISTER (PORTC_BASE_ADDRESS + 0x14)
+#define PORTC_AFR1_REGISTER (PORTC_BASE_ADDRESS + 0x20)
+
+void InitPortBPin0asOutput(void)
+{
+ uint32_t *reg; /*Define Pointer*/
+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); /* Enable the clock */
+
+ reg = (uint32_t *)PORTB_MODER_REGISTER;
+ *reg = *reg & (~((uint32_t)0x03)); /*Clear last two bits of Moder Register*/
+ *reg = *reg | ((uint32_t)0x01); /* Set the last two pins corresponding to Pin0 as Output Mode - 01 */
+
+ reg = (uint32_t *)PORTB_OTYPER_REGISTER;
+ *reg = *reg & (~((uint32_t)0x01)); /* Clear the last bit of OTYPER REGISTER*/
+ *reg = *reg | ((uint32_t)0x00);/*Statement is to set the OTYPER REGISTER TO 0 - Push Pull Type*/
+
+ reg = (uint32_t *)PORTB_PUPDR_REGISTER;
+ *reg = *reg & (~((uint32_t)0x03)); /* Clear the last two bits of PUPDR REGISTER*/
+ *reg = *reg | ((uint32_t)0x00);/*Statement is to set the PUPDR REGISTER TO 00 - No Pull Up No Pull Down Type*/
+
+ //reg=(uint32_t *)PORTB_OSPEEDR_REGISTER;
+ //*reg=*reg&(~((uint32_t)0x11)); /* Clear the last two bits of OSPEEDR REGISTER*/
+ //*reg=*reg|((uint32_t)0x11); /* Set the last two bits of OSPEEDR REGISTER to High Speed*/
+
+ reg = (uint32_t *)PORTB_ODR_REGISTER;
+ *reg = *reg | ((uint32_t)0x01); /* Setting the ODR REGISTER TO HIGH TO START WITH - Last bit is 1*/
+}
+
+
+
+void toggleGPIOB0(void)
+{
+ uint32_t value;
+ uint32_t *reg; /* Defining the variables*/
+
+ reg = (uint32_t *)PORTB_ODR_REGISTER; /*Initializing the current value of ODR REGISTER*/
+ value = *reg & ((uint32_t)0x1); /* Reading the value of last bit of current ODR REGISTER - Stored in reg*/
+
+ if (value > 0)
+ {
+ /* The bit is high initially*/
+ /*Need to set it to low now*/
+ *reg = *reg & (~((uint32_t)0x1));
+ }
+
+ else
+ {
+ /* The bit is low initially*/
+ /* Need to set it to high now*/
+ *reg = *reg | ((uint32_t)0x01);
+ }
+}
+
+
+
+
+void InitGPIOBPin0asOutputCompare(void)
+{
+ uint32_t *reg; //Initialize register pointer variable
+
+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); /* Enable the clock */
+
+ reg = (uint32_t *)PORTB_MODER_REGISTER;
+ *reg = *reg & (~((uint32_t)0x03)); //Clear last two bits of MODER REGISTER
+ *reg = *reg | ((uint32_t)0b10); //Write 10 to last two bits of MODER REGISTER
+
+ reg = (uint32_t *)PORTB_OTYPER_REGISTER;
+ *reg = *reg & (~((uint32_t)0x01)); //Clear last bit of OTYPER REGISTER
+ *reg = *reg | ((uint32_t)0x00); //Setting 0 to last bit of OTYPER REGISTER
+
+ reg = (uint32_t *)PORTB_PUPDR_REGISTER;
+ *reg = *reg & (~((uint32_t)0x03)); //Clear last two bits of PUPDR REGISTER - NO PULL UP/DOWN
+
+ //reg = (uint32_t *)PORTB_OSPEEDR_REGISTER;
+ //*reg = *reg & (~((uint32_t)0x03)); //Clear last two bits of OSPEEDR REGISTER
+ //*reg = *reg | ((uint32_t)0x03); //Setting of 11 to last two bits of OSPEEDR REGISTER - HIGH SPEED
+
+ reg = (uint32_t *)PORTB_AFR1_REGISTER;
+ *reg = *reg & (~((uint32_t)0xF)); //Clear last four bits of AFRL0 - GPIOB_AFRL REGISTER
+ *reg=*reg|((uint32_t)0x2); //Set last four digits of AFRL0 to 0010 - AF2 Alternate Function
+}
+
+
+
+void InitGPIOCPin6asInputCapture(void)
+{
+ uint32_t *reg; //Initialize register pointer variable
+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); /* Enable the clock */
+
+ reg = (uint32_t *)PORTC_MODER_REGISTER;
+ *reg = *reg & (~((uint32_t)0x3000)); //Clear last two bits of MODER REGISTER
+ *reg = *reg | ((uint32_t)0x2000); //Write 10 to last two bits of MODER REGISTER
+
+ reg = (uint32_t *)PORTC_OTYPER_REGISTER;
+ *reg = *reg & (~((uint32_t)0x40)); //Clear last bit of OTYPER REGISTER
+ *reg = *reg | ((uint32_t)0x00); //Setting 0 to last bit of OTYPER REGISTER
+
+ reg = (uint32_t *)PORTC_OSPEEDR_REGISTER;
+ *reg = *reg & (~((uint32_t)0x3000)); //Clear last two bits of OSPEEDR REGISTER
+ *reg = *reg | ((uint32_t)0x3000); //Setting of 11 to last two bits of OSPEEDR REGISTER - HIGH SPEED
+
+ reg = (uint32_t *)PORTC_PUPDR_REGISTER;
+ *reg = *reg & (~((uint32_t)0x3000)); //Clear last two bits of PUPDR REGISTER - NO PULL UP/DOWN
+ *reg = *reg | 0x00; //Setting two bits of PUPDR REGISTER - NO PULL UP/DOWN
+
+ reg = (uint32_t *)PORTC_AFR1_REGISTER;
+ *reg= *reg & (~((uint32_t)0xF000000)); //Clear last four bits of AFRL0 - GPIOB_AFRL REGISTER
+ *reg= *reg | ((uint32_t)0x2000000); //Set last four digits of AFRL0 to 0010 - AF2 Alternate Function
+}
+
+void InitGPIOBPin0asPWMMode1(void)
+{
+ uint32_t *reg; //Initialize register pointer variable
+
+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); /* Enable the clock */
+
+ reg = (uint32_t *)PORTB_MODER_REGISTER;
+ *reg = *reg & (~((uint32_t)0x03)); //Clear last two bits of MODER REGISTER
+ *reg = *reg | ((uint32_t)0b10); //Write 10 to last two bits of MODER REGISTER
+
+ reg = (uint32_t *)PORTB_OTYPER_REGISTER;
+ *reg = *reg & (~((uint32_t)0x01)); //Clear last bit of OTYPER REGISTER
+ *reg = *reg | ((uint32_t)0x00); //Setting 0 to last bit of OTYPER REGISTER
+
+ reg = (uint32_t *)PORTB_PUPDR_REGISTER;
+ *reg = *reg & (~((uint32_t)0x03)); //Clear last two bits of PUPDR REGISTER - NO PULL UP/DOWN
+
+ reg = (uint32_t *)PORTB_OSPEEDR_REGISTER;
+ *reg = *reg & (~((uint32_t)0x03)); //Clear last two bits of OSPEEDR REGISTER
+ *reg = *reg | ((uint32_t)0x03); //Setting of 11 to last two bits of OSPEEDR REGISTER - HIGH SPEED
+
+ reg = (uint32_t *)PORTB_AFR1_REGISTER;
+ *reg = *reg & (~((uint32_t)0xF)); //Clear last four bits of AFRL0 - GPIOB_AFRL REGISTER
+ *reg=*reg|((uint32_t)0x2); //Set last four digits of AFRL0 to 0010 - AF2 Alternate Function
+}
+
+void setGPIOB0( void )
+{
+ uint32_t * reg;
+ reg = (uint32_t *)PORTB_ODR_REGISTER;
+ *reg = *reg | 0b01;
+}
+
+void clearGPIOB0( void )
+{
+ uint32_t * reg;
+ reg = (uint32_t *)PORTB_ODR_REGISTER;
+ *reg = *reg & (~(uint32_t)0b01);
+}
+
+void initGpioC6AsInput( void )
+{
+ uint32_t * reg;
+ /* GPIOC Peripheral clock enable */
+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
+ /* GPIOC Pin 6 as input*/
+ reg = (uint32_t *)PORTC_MODER_REGISTER;
+ *reg = *reg & (~((uint32_t)0x3000));
+ *reg= *reg | 0x0000;
+ /*PUSH-PULL Pin*/
+ reg = (uint32_t *)PORTC_OTYPER_REGISTER;
+ *reg = *reg & (~((uint32_t)0x40));
+ *reg = *reg | 0x00;
+ /*GPIOC pin 6 high speed */
+ reg = (uint32_t *)PORTC_OSPEEDR_REGISTER;
+ *reg= *reg| 0x3000;
+ /*Configure pulled-down*/
+ reg = (uint32_t *)PORTC_PUPDR_REGISTER;
+ *reg = *reg & (~((uint32_t)0x3000));
+ *reg= *reg | 0x2000;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/gpio.h Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,40 @@
+#ifndef __GPIO_H_
+#define __GPIO_H_
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "main_Lec9.h"
+
+/*Defining function that initializes the Port B Pin 0 as Output*/
+void InitPortBPin0asOutput(void);
+
+/*Defining function that toggles the LED Switch*/
+void toggleGPIOB0(void);
+
+/*Defining function that initializes PortB Pin0 as Output Compare*/
+void InitGPIOBPin0asOutputCompare(void);
+
+/*Defining function that initializes PortC Pin6 as Input Capture*/
+void InitGPIOCPin6asInputCapture(void);
+
+/*Defining function that initializes PortB Pin0 as Output - PWM Mode 1*/
+void InitGPIOBPin0asPWMMode1(void);
+
+/*Defining function that initializes PortB Pin0 as Output - ODR HIGH*/
+void setGPIOB0(void);
+
+/*Defining function that initializes PortB Pin0 as Output - CLEARS ODR*/
+void clearGPIOB0(void);
+
+/*Defining function that initializes PortC Pin6 as Input - For Toggling LED when you see an interrupt*/
+void initGpioC6AsInput(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__GPIO_H */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hardware_timer3.c Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,198 @@
+#include "hardware_timer3.h"
+#include "gpio.h"
+#include "stm32f4xx_rcc_mort.h"
+#include "interrupt.h"
+
+
+/*Below are defined all Timers and flags required */ //Mort: These should be in a timer.c or something like that file
+#define TIM3_BASE_ADDRESS ((uint32_t)0x40000400)
+#define TIM3_STATUS_REGISTER (TIM3_BASE_ADDRESS + 0x10)
+#define TIM3_PSC_REGISTER (TIM3_BASE_ADDRESS + 0x28)
+#define TIM3_AUTORELOAD_REGISTER (TIM3_BASE_ADDRESS + 0x2C)
+#define TIM3_COUNTER_REGISTER (TIM3_BASE_ADDRESS + 0x24)
+#define TIM3_CAPTURE_COMPARE_MODE_2_REGISTER (TIM3_BASE_ADDRESS + 0x1C)
+#define TIM_CCMR13_OC1M_0 (0b00010000)
+#define TIM_CCMR13_OC1M_1 (0b00100000)
+#define TIM_CCMR13_OC1M_2 (0b01000000)
+#define TIM_CCMR13_OCPE (0b00001000)
+#define TIM_CCMR23_
+#define TIM_CCMR13_OUTPUT 0x00
+#define TIM3_COMPARE3_REGISTER (TIM3_BASE_ADDRESS + 0x3C)
+#define TIM3_CAPTURE_COMPARE_ENABLE_REGISTER (TIM3_BASE_ADDRESS + 0x20)
+#define TIM3_CR1_REGISTER1 (TIM3_BASE_ADDRESS + 0x00)
+#define TIM3_CAPTURE_COMPARE_MODE_1_REGISTER (TIM3_BASE_ADDRESS + 0x18)
+#define TIM3_CAPTURE_COMPARE_REGISTER_1 (TIM3_BASE_ADDRESS + 0x34)
+
+#define TIM3_CCMR2_CC3S_OUTPUT (0b11111100)
+#define TIM3_CCMR2_OC3FE (0b11111011)
+#define TIM3_CCMR2_OC3PE (0b00001000)
+#define TIM3_CCMR2_OC3M1 (0b11101111)
+#define TIM3_CCMR2_OC3M2 (0b01100000)
+
+#define TIM3_INTERRUPT_ENABLE_REGISTER (TIM3_BASE_ADDRESS + 0x0C)
+
+
+void TMR3CH3OutputCompare(void)
+{
+ uint16_t * reg;
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);//Enable Clock - SEE THE BUS UNDER WHICH THE REGISTER OR PERIPHERAL IS PRESENT
+
+ reg = (uint16_t *)TIM3_STATUS_REGISTER; //Read flag value of STATUS REGISTER
+ *reg = (~((uint16_t)0x01)); //Clear update event flag in STATUS REGISTER
+
+ reg = (uint16_t *)TIM3_PSC_REGISTER; //Read value of PRESCALER REGISTER
+ *reg = 8999; //Setting the PRESCALER VALUE TO 899999, CALCULATE BY 90MHz/(Prescale + 1) --> ARR * 1/freq = 1Hz ---> freqcounter = 90MHz/(prescale +1)
+
+ reg = (uint16_t *)TIM3_AUTORELOAD_REGISTER; //Read value of AUTORELOAD REGISTER
+ *reg = 10000; //Count till 65535 or 2^16-1, DEFINES LIMIT UPTO WHICH COUNTER SHOULD COUNT,POST THIS IT WILL RESET ITSELF
+
+ /*Setup mode resgister 2 to output compare and enable output*/ //(0b00000000 00110000)
+ reg = (uint16_t *)TIM3_CAPTURE_COMPARE_MODE_2_REGISTER; //READ CAPTURE COMPARE MODE REGISTER
+ *reg = *reg | TIM_CCMR13_OC1M_1 | TIM_CCMR13_OC1M_0 | TIM_CCMR13_OUTPUT;//Setting the Output Compare to the OC3M bit fields and enabling it as an output
+
+ reg = (uint16_t *)TIM3_COMPARE3_REGISTER; //READ VALUE OF COMPARE REGISTER
+ *reg = 2000; //Any value to count between two cycles- this is the value that we want to compare
+
+ reg = (uint16_t *)TIM3_CAPTURE_COMPARE_ENABLE_REGISTER; //READ VALUE OF CAPTURE COMPARE ENABLE REGISTER
+ *reg = *reg | 0x0100; // Enabling TIM3 Channel3 - Setting the CC3E (Enable) bit in the CCER REGISTER
+
+ //Also keeping the default configuration for channel polarity
+ reg = (uint16_t *)TIM3_CR1_REGISTER1;
+ *reg = *reg | ((uint16_t)0x01);//Enabling the Timer3 subsystem by setting the CEN bit in TIM3_CR1
+}
+
+
+void TMR3CH1GPIOCPin6asInputCapture(void)
+{
+ uint16_t *reg;
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); //Enable Clock
+
+ /*Clear Status register*/
+ reg = (uint16_t *)TIM3_STATUS_REGISTER; //Read flag value of STATUS REGISTER
+ *reg = (~((uint16_t)0x1)); //Clear update event flag in STATUS REGISTER
+
+ reg = (uint16_t *)TIM3_PSC_REGISTER; //Read value of PRESCALER REGISTER
+ *reg = 9999; //Setting the PRESCALER VALUE TO 9999, CALCULATE BY 90MHz/(Prescale + 1)
+
+ reg = (uint16_t *)TIM3_AUTORELOAD_REGISTER; //Read value of AUTORELOAD REGISTER
+ *reg = 0xFFFF; //Count till 65535 or 2^16-1, DEFINES LIMIT UPTO WHICH COUNTER SHOULD COUNT,POST THIS IT WILL RESET ITSELF
+
+ reg = (uint16_t *)TIM3_CAPTURE_COMPARE_MODE_1_REGISTER; //READ CAPTURE COMPARE MODE REGISTER
+ *reg = *reg | 0x01;//Configuring CC1 Channel as Input
+ //IC1 is mapped on TI1 - Configuring the REGISTER TO INPUT CAPTURE - CC1S BIT - 01
+ //ALL OTHER BITS TO BE SET FOR INPUT CAPTURE ARE 00's
+ //IC1PSC - 00 - NO PRESCALER
+ //IC1F - 0000 - No filter, sampling is done at fDTS - Input Capture 1 Filter
+
+ reg = (uint16_t *)TIM3_CAPTURE_COMPARE_ENABLE_REGISTER; //READ VALUE OF CAPTURE COMPARE ENABLE REGISTER
+ *reg = *reg | 0x01; // Enabling TIM3 Channel1 - Setting the CC3E bit in the CCER REGISTER
+ //BY DEFAULT TIMER IS SENSITIVE TO RISING EDGE - ENABLE AND KEEP IT AS IT IS
+
+ reg = (uint16_t *)TIM3_CR1_REGISTER1;
+ *reg = *reg | ((uint16_t)0x01);//Enabling the Timer3 subsystem by setting the CEN bit in TIM3_CR1
+}
+
+/* Question - Why dont we initialize or set bits of IC1PSC, IC1F AND IC1
+WHY CAN'T IT BE *reg=0b00000001*/
+
+uint16_t readCounterValueIfFlagIsSet(void)
+{
+ uint16_t * reg1;
+ uint16_t * reg2;
+ uint16_t value;
+ value=0;
+
+ reg1 = (uint16_t *)TIM3_STATUS_REGISTER;
+
+ if( *reg1 & (uint16_t)0b10 == 0b10 )
+ {
+ reg2 = (uint16_t *)TIM3_CAPTURE_COMPARE_REGISTER_1;
+ value = *reg2;
+ //Do we need to clear the flag? - The TIM3_STATUS_REGISTER
+ }
+
+ return value;
+
+}
+
+ //read status reguster,
+ //check if CCIF1 flag is set, if it is, you clear it rc_w0
+ //Statusregister = ~(CCIF1)
+ //and also you read the INput caputre register and return the value.
+
+
+
+
+uint16_t readCounterRegister(void)
+{
+ uint16_t *reg;
+ reg = (uint16_t *)TIM3_COUNTER_REGISTER;
+ return *reg;
+}
+
+void TMR3CH3OutputPWMMode1(void)
+{
+ uint16_t *reg;
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);//Enable Clock - SEE THE BUS UNDER WHICH THE REGISTER OR PERIPHERAL IS PRESENT
+
+ reg = (uint16_t *)TIM3_STATUS_REGISTER; //Read flag value of STATUS REGISTER
+ *reg = (~((uint16_t)0x01)); //Clear update event flag in STATUS REGISTER
+
+ reg = (uint16_t *)TIM3_PSC_REGISTER; //Read value of PRESCALER REGISTER
+ *reg = 35999; //Setting the PRESCALER VALUE TO 35999
+
+ reg = (uint16_t *)TIM3_AUTORELOAD_REGISTER; //Read value of AUTORELOAD REGISTER
+ *reg = 10000; //Count till 65535 or 2^16-1, DEFINES LIMIT UPTO WHICH COUNTER SHOULD COUNT,POST THIS IT WILL RESET ITSELF
+
+ /*Setup mode resgister 2 to output compare and enable output*/ //(0b00000000 01101000)
+ reg = (uint16_t *)TIM3_CAPTURE_COMPARE_MODE_2_REGISTER; //READ CAPTURE COMPARE MODE REGISTER
+ *reg = *reg | TIM3_CCMR2_OC3M2 & TIM3_CCMR2_OC3M1 | TIM3_CCMR2_OC3PE & TIM3_CCMR2_OC3FE & TIM3_CCMR2_CC3S_OUTPUT ;//Setting the PWM Mode 1 to the OC3M bit fields and enabling it as an output
+
+ reg = (uint16_t *)TIM3_COMPARE3_REGISTER; //READ VALUE OF COMPARE REGISTER
+ *reg = 5000; //We want half of 0.5Hz - Autoreload Register is 0.5Hz and Compare Value is at 0.25Hz
+
+ reg = (uint16_t *)TIM3_CAPTURE_COMPARE_ENABLE_REGISTER; //READ VALUE OF CAPTURE COMPARE ENABLE REGISTER
+ *reg = *reg | 0x0100; // Enabling TIM3 Channel3 - Setting the CC3E (Enable) bit in the CCER REGISTER
+
+ //Also keeping the default configuration for channel polarity
+ reg = (uint16_t *)TIM3_CR1_REGISTER1;
+ *reg = *reg | ((uint16_t)0x01);//Enabling the Timer3 subsystem by setting the CEN bit in TIM3_CR1
+}
+
+void initTimer3ToInterrupt(void)
+{
+ uint16_t * reg;
+ uint16_t prescalervalue2, autoreloadvalue;
+ /* Timer 3 APB clock enable */
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
+ /*enable the interrupt that would go to timer 3*/
+ enableNVIC_Timer3();
+ /* Compute Prescale and Autorreload */
+ prescalervalue2 = 35999; //Frequency of clock is 90 MHz
+ autoreloadvalue = 10000;
+ /* Clear any pending flags in the status register */
+ reg = (uint16_t *)TIM3_STATUS_REGISTER;
+ *reg = 0;
+ /* Set Prescale and Autorreload */
+ reg = (uint16_t *)TIM3_PSC_REGISTER;
+ *reg = prescalervalue2;
+ reg = (uint16_t *)TIM3_AUTORELOAD_REGISTER;
+ *reg = autoreloadvalue;
+ /* Set Compare Value */
+ reg = (uint16_t *)TIM3_COMPARE3_REGISTER;
+ *reg = autoreloadvalue/2;
+ /* Enable Preload Register (Don’t HAVE to, but good practice) */
+ reg = (uint16_t *)TIM3_CAPTURE_COMPARE_MODE_2_REGISTER;
+ *reg = *reg | 0b00001000;
+ /*enable the TIM3 channel 3 counter and keep the default configuration for channel polarity*/
+ reg = (uint16_t *)TIM3_CAPTURE_COMPARE_ENABLE_REGISTER;
+ *reg = *reg | 0x0100;
+ /*enable interrupt on capture compare channel 3*/
+ reg = (uint16_t *)TIM3_INTERRUPT_ENABLE_REGISTER;
+ *reg = (0x8 | 0x1);
+ /*enable timer 3*/
+ reg = (uint16_t *)TIM3_CR1_REGISTER1;
+ *reg = *reg | (uint16_t)0x01;
+}
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hardware_timer3.h Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,35 @@
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_TIMER_3_H_
+#define __HARDWARE_TIMER_3_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main_Lec9.h"
+
+
+
+/*Function definitions---------------------------------------------------------*/
+
+/*Defining funtion that initializes Timer3 Channel3 as Output Compare*/
+void TMR3CH3OutputCompare(void);
+
+/*Defining funtion that initializes Timer3 Channel1 as Input Capture*/
+void TMR3CH1GPIOCPin6asInputCapture(void);
+
+/*Defining funtion that reads countervalue when Timer3 Channel1 as an Input Capture*/
+uint16_t readCounterValueIfFlagIsSet(void);
+
+/*Defining funtion that Initializes Timer3 Channel3 as an Output - PWM Mode 1*/
+void TMR3CH3OutputPWMMode1(void);
+
+///*Defining funtion that Initializes Timer3 Channel3 to Interrupt - Output Compare Interrupt Mode*/
+void initTimer3ToInterrupt(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__HARDWARE_TIMER_3_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/interrupt.c Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,141 @@
+#include "hardware_timer3.h"
+#include "gpio.h"
+#include "stm32f4xx_rcc_mort.h"
+#include "interrupt.h"
+
+/*Below are defined all Timers and flags required */ //COPYING ALL VALUES AND DEFINITIONS FROM HARDWARE_TIMER3.C
+#define TIM3_BASE_ADDRESS ((uint32_t)0x40000400)
+#define TIM3_STATUS_REGISTER (TIM3_BASE_ADDRESS + 0x10)
+#define TIM3_PSC_REGISTER (TIM3_BASE_ADDRESS + 0x28)
+#define TIM3_AUTORELOAD_REGISTER (TIM3_BASE_ADDRESS + 0x2C)
+#define TIM3_COUNTER_REGISTER (TIM3_BASE_ADDRESS + 0x24)
+#define TIM3_CAPTURE_COMPARE_MODE_2_REGISTER (TIM3_BASE_ADDRESS + 0x1C)
+#define TIM_CCMR13_OC1M_0 (0b00010000)
+#define TIM_CCMR13_OC1M_1 (0b00100000)
+#define TIM_CCMR13_OC1M_2 (0b01000000)
+#define TIM_CCMR13_OCPE (0b00001000)
+#define TIM_CCMR23_
+#define TIM_CCMR13_OUTPUT 0x00
+#define TIM3_COMPARE3_REGISTER (TIM3_BASE_ADDRESS + 0x3C)
+#define TIM3_CAPTURE_COMPARE_ENABLE_REGISTER (TIM3_BASE_ADDRESS + 0x20)
+#define TIM3_CR1_REGISTER1 (TIM3_BASE_ADDRESS + 0x00)
+#define TIM3_CAPTURE_COMPARE_MODE_1_REGISTER (TIM3_BASE_ADDRESS + 0x18)
+#define TIM3_CAPTURE_COMPARE_REGISTER_1 (TIM3_BASE_ADDRESS + 0x34)
+
+#define TIM3_CCMR2_CC3S_OUTPUT (0b11111100)
+#define TIM3_CCMR2_OC3FE (0b11111011)
+#define TIM3_CCMR2_OC3PE (0b00001000)
+#define TIM3_CCMR2_OC3M1 (0b11101111)
+#define TIM3_CCMR2_OC3M2 (0b01100000)
+
+# define TIM3_INTERRUPT_ENABLE_REGISTER (TIM3_BASE_ADDRESS + 0x0C)
+
+/* MACRO definitions----------------------------------------------------------*/
+#define SYSTEM_CONTROL_BASE_ADDRESS (0xE000E000)
+#define NVIC_BASE_ADDRESS (SYSTEM_CONTROL_BASE_ADDRESS + 0x100)
+#define NVIC_INTERRUPT_SET_ENABLE_REGISTER_0_31 (NVIC_BASE_ADDRESS)
+#define NVIC_INTERRUPT_SET_ENABLE_REGISTER_32_63 (NVIC_BASE_ADDRESS+0x4)
+#define NVIC_INTERRUPT_SET_ENABLE_REGISTER_64_95 (NVIC_BASE_ADDRESS+0x8)
+#define TIM3_INTERRUPT_BIT (0x20000000)
+
+#define NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_0_31 (NVIC_BASE_ADDRESS + 0x80)
+#define NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_32_63 (NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_0_31 + 0x4)
+#define NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_64_95 (NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_0_31 + 0x8)
+#define NVIC_INTERRUPT_SET_PENDING_REGISTER_0_31 (NVIC_BASE_ADDRESS + 0x100)
+#define NVIC_INTERRUPT_SET_PENDING_REGISTER_32_63 (NVIC_INTERRUPT_SET_PENDING_REGISTER_0_31 + 0x4)
+#define NVIC_INTERRUPT_SET_PENDING_REGISTER_64_95 (NVIC_INTERRUPT_SET_PENDING_REGISTER_0_31 + 0x8)
+#define NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_0_31 (NVIC_BASE_ADDRESS + 0x180)
+#define NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_32_63 (NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_0_31 + 0x4)
+#define NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_64_95 (NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_0_31 + 0x8)
+#define EXTI9_5_INTERRUPT_BIT (0x800000)
+
+//For external interrupts:
+#define SYSCFG_BASE_ADDRESS ((uint32_t)(0x40013800))
+#define SYSCFG_EXTERNAL_INTERRUPT_REGISTER_2 (SYSCFG_BASE_ADDRESS + 0x0C)
+#define SYSCFG_EXTERNAL_INTERRUPT_6_BITS ((uint32_t)0xF00) //flags for External interrupt register 2
+#define SYSCFG_EXTERNAL_INTERRUPT_6_PORTC ((uint32_t)0x200)
+//External interrupt controller :
+#define EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS ((uint32_t)(0x40013C00))
+#define EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS)
+#define EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER_EXTI6 ((uint32_t)0x40) //flags for external interrupt controller mask register
+#define EXTERNAL_INTERRUPT_CONTROLLER_RTSR (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS+0x08)
+#define EXTERNAL_INTERRUPT_CONTROLLER_RTSR_EXTI6 ((uint32_t)0x40)
+#define EXTERNAL_INTERRUPT_CONTROLLER_FTSR (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS+0x0C)
+#define EXTERNAL_INTERRUPT_CONTROLLER_FTSR_EXTI6 ((uint32_t)0x40)
+#define EXTERNAL_INTERRUPT_CONTROLLER_PENDING_REGISTER (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS+0x14)
+#define EXTERNAL_INTERRUPT_CONTROLLER_PENDING_EXTI6 ((uint32_t)0x40)
+
+
+void enableNVIC_Timer3(void)
+{
+ uint32_t * reg;
+ reg = (uint32_t *)NVIC_INTERRUPT_SET_ENABLE_REGISTER_0_31;
+ *reg = TIM3_INTERRUPT_BIT;
+}
+
+void TIM3_IRQHandler(void)
+{
+ uint16_t * reg_pointer_16_sr;
+ uint16_t * reg_pointer_16_dier;
+ reg_pointer_16_sr = (uint16_t *)TIM3_STATUS_REGISTER;
+ reg_pointer_16_dier = (uint16_t *)TIM3_INTERRUPT_ENABLE_REGISTER;
+ //check which interrupts fired and if they were supposed to fire, then clear the flags so they don’t keep firing,
+// then perform actions according to these interrupts
+//check if Output Compare 3 triggered the interrupt:
+ if (( (*reg_pointer_16_sr & 0x8) >0) && ( (*reg_pointer_16_dier & 0x8) >0))
+ {
+ //clear interrupt
+ *reg_pointer_16_sr = ~((uint16_t)0x8);
+ //perform action
+ clearGPIOB0();
+ }
+//check if Overflow triggered the interrupt: I.e. Timer Counter 3 >= Autorreload value
+ if (( (*reg_pointer_16_sr & 0x01) >0) && ( (*reg_pointer_16_dier & 0x1) >0))
+ {
+ //clear interrupt
+ *reg_pointer_16_sr = ~((uint16_t)0x01);
+ //perform action
+ setGPIOB0();
+ }
+}
+
+void enableEXTI6OnPortC(void)
+{
+ uint32_t * reg;
+ /*Init GPIO 6 C as input*/
+ initGpioC6AsInput();
+ /*As a test, Init GPIO B0 as output for debugging*/
+ InitPortBPin0asOutput();
+ /* Enable SYSCFG clock */
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+ /*map EXTI6 to port C bit 6*/
+ reg = (uint32_t *)SYSCFG_EXTERNAL_INTERRUPT_REGISTER_2;
+ //clear EXTI6
+ *reg = *reg & ~SYSCFG_EXTERNAL_INTERRUPT_6_BITS;
+ //set EXTI6 to Port C
+ *reg = *reg | SYSCFG_EXTERNAL_INTERRUPT_6_PORTC;
+ /*un-mask EXTI6*/
+ reg = (uint32_t *)EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER;
+ *reg = *reg | EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER_EXTI6;
+ /*trigger on rising edge*/
+ reg = (uint32_t *)EXTERNAL_INTERRUPT_CONTROLLER_RTSR;
+ *reg = *reg | EXTERNAL_INTERRUPT_CONTROLLER_RTSR_EXTI6;
+ /* set the NVIC to respond to EXTI9_5*/
+ reg = (uint32_t *)NVIC_INTERRUPT_SET_ENABLE_REGISTER_0_31;
+ *reg = EXTI9_5_INTERRUPT_BIT;
+}
+
+void EXTI9_5_IRQHandler(void)
+{
+ uint32_t * reg;
+ reg = (uint32_t *)EXTERNAL_INTERRUPT_CONTROLLER_PENDING_REGISTER;
+ //check which interrupt fired:
+ if ((*reg & EXTERNAL_INTERRUPT_CONTROLLER_PENDING_EXTI6)>0)
+ {
+ //clear the interrupt:
+ *reg = EXTERNAL_INTERRUPT_CONTROLLER_PENDING_EXTI6;
+ //toggle the LED
+ toggleGPIOB0();
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/interrupt.h Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,22 @@
+#ifndef __INTERRUPT_H_
+#define __INTERRUPT_H_
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "main_Lec9.h"
+
+/*Defining function that enables Interrupt corresponding to TIMER 3 IN NVIC*/
+void enableNVIC_Timer3(void);
+
+/*Defining function that enables Interrupt configuration and handling:*/
+void enableEXTI6OnPortC(void)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__INTERRUPT_H */
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/led1.c Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,43 @@
+#include "led1.h"
+#include "gpio.h"
+#include "main_Lec9.h"
+#include "stm32f4xx_rcc_mort.h"
+#include "hardware_timer3.h"
+
+
+//LECTURE 9 PROBLEM 1
+//void init_LED1(void)
+//{
+// InitPortBPin0asOutput();
+//}
+//
+//void toggle_LED1(void)
+//{
+// toggleGPIOB0();
+//}
+
+//Lecture 10 Problem 1 - BEGIN
+
+void init_LED1(void)
+{
+ InitGPIOBPin0asOutputCompare();
+}
+
+void toggle_LED1(void)
+{
+ toggleGPIOB0();
+}
+
+//Lecture 10 Problem 1 - END
+
+//Lecture 10 Problem 2 - BEGIN
+
+void init_GPIOCPort6AsInputCompare(void)
+{
+ InitGPIOCPin6asInputCapture();
+ TMR3CH1GPIOCPin6asInputCapture();
+}
+
+//Lecture 10 Problem 2 - END
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/led1.h Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,22 @@
+#ifndef __LED1_H_
+#define __LED1_H_
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "main_Lec9.h"
+
+/*Defining Function that initializes the LED*/
+void init_LED1(void);
+
+/*Defining function that toggles the LED Switch*/
+void toggle_LED1(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__LED1_H */
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/main_Lec9.cpp Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,74 @@
+#include "gpio.h"
+#include "led1.h"
+#include "main_Lec9.h" //Mort: including main_Lec9.h
+#include "mbed.h"
+#include "hardware_timer3.h"
+#include "interrupt.h"
+
+Serial pc(USBTX, USBRX);
+
+
+int main(void)
+{
+ uint32_t i,j;
+ //uint16_t countervalue;
+ //uint16_t checkvalue;
+
+ /* All of your init functions need to be here */
+
+ //This is for first LED function
+ //init_LED1(); //Calling the initialization function - To initialize PortB as its corresponding functionality //Mort: Do not need to say void here
+
+ //This is for Probelm 10 Exercises - START
+// //This is for Output Compare:
+// InitGPIOBPin0asOutputCompare();
+// TMR3CH3OutputCompare();
+//
+// //This is for Input Capture:
+// InitGPIOCPin6asInputCapture();
+// TMR3CH1GPIOCPin6asInputCapture();
+ //This is for Probelm 10 Exercises - END
+
+
+// //Exercise 11 PWM MODE - 1st Problem - START
+// //Initializing PortB Pin 0 as a Output Pin
+// InitGPIOBPin0asPWMMode1();
+// TMR3CH3OutputPWMMode1();
+// //Exercise 11 PWM MODE - 1st Problem - END
+
+// //Exercise 11 PWM MODE - 2nd Problem - START
+// //Initializing PortB Pin 0 as a Output Pin
+// InitPortBPin0asOutput();
+// initTimer3ToInterrupt();
+// //Exercise 11 PWM MODE - 2nd Problem - END
+
+ //Exercise 11 PWM MODE - 3rd Problem - START
+ //Initializing PortB Pin 0 as a Output Pin
+ enableEXTI6OnPortC();
+ //Exercise 11 PWM MODE - 3rd Problem - END
+
+
+ while(true)
+ {
+ //Create FOR Loop to have some delay between toggling
+ for(i=1; i<100; i++) //Mort: Your code was fine, just your delay was too large.
+ {
+ //pc.printf("hi hi hi \n");
+ j=j+1;
+ }
+ toggle_LED1(); //Function Call to toggle LED
+
+// countervalue = readCounterValueIfFlagIsSet();
+// if (countervalue > 0 & checkvalue != countervalue)
+// {
+// pc.printf("\nCounter Value is = %d", countervalue);
+// checkvalue = countervalue;
+ }
+ }
+}
+
+void debugPrint(uint32_t what)
+{
+ pc.printf("The value is %u\n",what);
+}
+
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/main_Lec9.h Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,22 @@
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_LEC9_H_
+#define __MAIN__LEC9_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_mort2.h"
+
+
+
+/*Function definitions---------------------------------------------------------*/
+void debugPrint(uint32_t what);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__MAIN_LEC9_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed.bld Sat Oct 23 05:49:09 2021 +0000 @@ -0,0 +1,1 @@ +https://os.mbed.com/users/mbed_official/code/mbed/builds/65be27845400 \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/misc_mort.c Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,254 @@
+/**
+ ******************************************************************************
+ * @file misc.c
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file provides all the miscellaneous firmware functions (add-on
+ * to CMSIS functions).
+ *
+ * @verbatim
+ *
+ * ===================================================================
+ * How to configure Interrupts using driver
+ * ===================================================================
+ *
+ * This section provide functions allowing to configure the NVIC interrupts (IRQ).
+ * The Cortex-M4 exceptions are managed by CMSIS functions.
+ *
+ * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig_mort()
+ * function according to the following table.
+
+ * The table below gives the allowed values of the pre-emption priority and subpriority according
+ * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig_mort function
+ * ==========================================================================================================================
+ * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ * ==========================================================================================================================
+ * NVIC_PriorityGroup_0_MORT | 0 | 0-15 | 0 bits for pre-emption priority
+ * | | | 4 bits for subpriority
+ * --------------------------------------------------------------------------------------------------------------------------
+ * NVIC_PriorityGroup_1_MORT | 0-1 | 0-7 | 1 bits for pre-emption priority
+ * | | | 3 bits for subpriority
+ * --------------------------------------------------------------------------------------------------------------------------
+ * NVIC_PriorityGroup_2_MORT | 0-3 | 0-3 | 2 bits for pre-emption priority
+ * | | | 2 bits for subpriority
+ * --------------------------------------------------------------------------------------------------------------------------
+ * NVIC_PriorityGroup_3_MORT | 0-7 | 0-1 | 3 bits for pre-emption priority
+ * | | | 1 bits for subpriority
+ * --------------------------------------------------------------------------------------------------------------------------
+ * NVIC_PriorityGroup_4_MORT | 0-15 | 0 | 4 bits for pre-emption priority
+ * | | | 0 bits for subpriority
+ * ==========================================================================================================================
+ *
+ * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init_mort()
+ *
+ * @note When the NVIC_PriorityGroup_0_MORT is selected, IRQ pre-emption is no more possible.
+ * The pending IRQ priority will be managed only by the subpriority.
+ *
+ * @note IRQ priority order (sorted by highest to lowest priority):
+ * - Lowest pre-emption priority
+ * - Lowest subpriority
+ * - Lowest hardware priority (IRQ number)
+ *
+ * @endverbatim
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "misc_mort.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup MISC
+ * @brief MISC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup MISC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.
+ * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PriorityGroup_0_MORT: 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PriorityGroup_1_MORT: 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PriorityGroup_2_MORT: 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PriorityGroup_3_MORT: 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PriorityGroup_4_MORT: 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ * @note When the NVIC_PriorityGroup_0_MORT is selected, IRQ pre-emption is no more possible.
+ * The pending IRQ priority will be managed only by the subpriority.
+ * @retval None
+ */
+void NVIC_PriorityGroupConfig_mort(uint32_t NVIC_PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP_MORT(NVIC_PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+ * @brief Initializes the NVIC peripheral according to the specified
+ * parameters in the NVIC_InitStruct.
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig_mort()
+ * function should be called before.
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef_mort structure that contains
+ * the configuration information for the specified NVIC peripheral.
+ * @retval None
+ */
+void NVIC_Init_mort(NVIC_InitTypeDef_mort* NVIC_InitStruct)
+{
+ uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY_MORT(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+ {
+ /* Compute the Corresponding IRQ Priority --------------------------------*/
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+ tmppre = (0x4 - tmppriority);
+ tmpsub = tmpsub >> tmppriority;
+
+ tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+ tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
+
+ tmppriority = tmppriority << 0x04;
+
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+ /* Enable the Selected IRQ Channels --------------------------------------*/
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+ else
+ {
+ /* Disable the Selected IRQ Channels -------------------------------------*/
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+}
+
+/**
+ * @brief Sets the vector table location and Offset.
+ * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+ * This parameter can be one of the following values:
+ * @arg NVIC_VectTab_RAM_MORT: Vector Table in internal SRAM.
+ * @arg NVIC_VectTab_FLASH_MORT: Vector Table in internal FLASH.
+ * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
+ * @retval None
+ */
+void NVIC_SetVectorTable_mort(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_VECTTAB_MORT(NVIC_VectTab));
+ assert_param(IS_NVIC_OFFSET_MORT(Offset));
+
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+ * @brief Selects the condition for the system to enter low power mode.
+ * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
+ * This parameter can be one of the following values:
+ * @arg NVIC_LP_SEVONPEND_MORT: Low Power SEV on Pend.
+ * @arg NVIC_LP_SLEEPDEEP_MORT: Low Power DEEPSLEEP request.
+ * @arg NVIC_LP_SLEEPONEXIT_MORT: Low Power Sleep on Exit.
+ * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void NVIC_SystemLPConfig_mort(uint8_t LowPowerMode, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_LP_MORT(LowPowerMode));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ SCB->SCR |= LowPowerMode;
+ }
+ else
+ {
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+ }
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param SysTick_CLKSource: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SysTick_CLKSource_HCLK_Div8_MORT: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SysTick_CLKSource_HCLK_MORT: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void SysTick_CLKSourceConfig_mort(uint32_t SysTick_CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE_MORT(SysTick_CLKSource));
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK_MORT)
+ {
+ SysTick->CTRL |= SysTick_CLKSource_HCLK_MORT;
+ }
+ else
+ {
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8_MORT;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/misc_mort.h Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,183 @@
+/**
+ ******************************************************************************
+ * @file misc.h
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file contains all the functions prototypes for the miscellaneous
+ * firmware library functions (add-on to CMSIS functions).
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_MORT_H
+#define __MISC_MORT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_mort2.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief NVIC Init Structure definition
+ */
+
+typedef struct
+{
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
+ This parameter can be an enumerator of @ref IRQn_Type_MORT
+ enumeration (For the complete STM32 Devices IRQ Channels
+ list, please refer to stm32f4xx.h file) */
+
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
+ specified in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
+ A lower priority value indicates a higher priority */
+
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
+ in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
+ A lower priority value indicates a higher priority */
+
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+ will be enabled or disabled.
+ This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitTypeDef_mort;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MISC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup MISC_Vector_Table_Base
+ * @{
+ */
+
+#define NVIC_VectTab_RAM_MORT ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH_MORT ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB_MORT(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM_MORT) || \
+ ((VECTTAB) == NVIC_VectTab_FLASH_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup MISC_System_Low_Power
+ * @{
+ */
+
+#define NVIC_LP_SEVONPEND_MORT ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP_MORT ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT_MORT ((uint8_t)0x02)
+#define IS_NVIC_LP_MORT(LP) (((LP) == NVIC_LP_SEVONPEND_MORT) || \
+ ((LP) == NVIC_LP_SLEEPDEEP_MORT) || \
+ ((LP) == NVIC_LP_SLEEPONEXIT_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Preemption_Priority_Group
+ * @{
+ */
+
+#define NVIC_PriorityGroup_0_MORT ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PriorityGroup_1_MORT ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_2_MORT ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_3_MORT ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_4_MORT ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP_MORT(GROUP) (((GROUP) == NVIC_PriorityGroup_0_MORT) || \
+ ((GROUP) == NVIC_PriorityGroup_1_MORT) || \
+ ((GROUP) == NVIC_PriorityGroup_2_MORT) || \
+ ((GROUP) == NVIC_PriorityGroup_3_MORT) || \
+ ((GROUP) == NVIC_PriorityGroup_4_MORT))
+
+#define IS_NVIC_PREEMPTION_PRIORITY_MORT(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY_MORT(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET_MORT(OFFSET) ((OFFSET) < 0x000FFFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_SysTick_clock_source
+ * @{
+ */
+
+#define SysTick_CLKSource_HCLK_Div8_MORT ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK_MORT ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE_MORT(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK_MORT) || \
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8_MORT))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+void NVIC_PriorityGroupConfig_mort(uint32_t NVIC_PriorityGroup);
+void NVIC_Init_mort(NVIC_InitTypeDef_mort* NVIC_InitStruct);
+void NVIC_SetVectorTable_mort(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig_mort(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig_mort(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/stm32f4xx_adc_mort.c Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,1750 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_adc_mort.c
+ * @author MCD Application Team (with some modifications by melisao@stanford.edu)
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Convertor (ADC) peripheral:
+ * + Initialization and Configuration (in addition to ADC multi mode
+ * selection)
+ * + Analog Watchdog configuration
+ * + Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT
+ * management
+ * + Regular Channels Configuration
+ * + Regular Channels DMA Configuration
+ * + Injected channels Configuration
+ * + Interrupts and flags management
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (#) Enable the ADC interface clock using
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE);
+
+ (#) ADC pins configuration
+ (++) Enable the clock for the ADC GPIOs using the following function:
+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+ (++) Configure these ADC pins in analog mode using GPIO_Init();
+
+ (#) Configure the ADC Prescaler, conversion resolution and data
+ alignment using the ADC_Init() function.
+ (#) Activate the ADC peripheral using ADC_Cmd() function.
+
+ *** Regular channels group configuration ***
+ ============================================
+ [..]
+ (+) To configure the ADC regular channels group features, use
+ ADC_Init() and ADC_RegularChannelConfig() functions.
+ (+) To activate the continuous mode, use the ADC_continuousModeCmd()
+ function.
+ (+) To configurate and activate the Discontinuous mode, use the
+ ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
+ (+) To read the ADC converted values, use the ADC_GetConversionValue()
+ function.
+
+ *** Multi mode ADCs Regular channels configuration ***
+ ======================================================
+ [..]
+ (+) Refer to "Regular channels group configuration" description to
+ configure the ADC1, ADC2 and ADC3 regular channels.
+ (+) Select the Multi mode ADC regular channels features (dual or
+ triple mode) using ADC_CommonInit() function and configure
+ the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd()
+ functions.
+ (+) Read the ADCs converted values using the
+ ADC_GetMultiModeConversionValue() function.
+
+ *** DMA for Regular channels group features configuration ***
+ =============================================================
+ [..]
+ (+) To enable the DMA mode for regular channels group, use the
+ ADC_DMACmd() function.
+ (+) To enable the generation of DMA requests continuously at the end
+ of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd()
+ function.
+
+ *** Injected channels group configuration ***
+ =============================================
+ [..]
+ (+) To configure the ADC Injected channels group features, use
+ ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()
+ functions.
+ (+) To activate the continuous mode, use the ADC_continuousModeCmd()
+ function.
+ (+) To activate the Injected Discontinuous mode, use the
+ ADC_InjectedDiscModeCmd() function.
+ (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd()
+ function.
+ (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue()
+ function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_adc_mort.h"
+#include "stm32f4xx_rcc_mort.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup ADC
+ * @brief ADC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* ADC DISCNUM mask */
+#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)
+
+/* ADC AWDCH mask */
+#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF)
+
+/* CR1 register Mask */
+#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF)
+
+/* ADC EXTEN mask */
+#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF)
+
+/* ADC JEXTEN mask */
+#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)
+
+/* ADC JEXTSEL mask */
+#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)
+
+/* CR2 register Mask */
+#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)
+
+/* ADC SQx mask */
+#define SQR3_SQ_SET ((uint32_t)0x0000001F)
+#define SQR2_SQ_SET ((uint32_t)0x0000001F)
+#define SQR1_SQ_SET ((uint32_t)0x0000001F)
+
+/* ADC L Mask */
+#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define JSQR_JSQ_SET ((uint32_t)0x0000001F)
+
+/* ADC JL mask */
+#define JSQR_JL_SET ((uint32_t)0x00300000)
+#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SMPR1_SMP_SET ((uint32_t)0x00000007)
+#define SMPR2_SMP_SET ((uint32_t)0x00000007)
+
+/* ADC JDRx registers offset */
+#define JDR_OFFSET ((uint8_t)0x28)
+
+/* ADC CDR register base address */
+#define CDR_ADDRESS ((uint32_t)0x40012308)
+
+/* ADC CCR register Mask */
+#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Functions
+ * @{
+ */
+
+/** @defgroup ADC_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the ADC Prescaler
+ (+) ADC Conversion Resolution (12bit..6bit)
+ (+) Scan Conversion Mode (multichannel or one channel) for regular group
+ (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for
+ regular group
+ (+) External trigger Edge and source of regular group,
+ (+) Converted data alignment (left or right)
+ (+) The number of ADC conversions that will be done using the sequencer for
+ regular channel group
+ (+) Multi ADC mode selection
+ (+) Direct memory access mode selection for multi ADC mode
+ (+) Delay between 2 sampling phases (used in dual or triple interleaved modes)
+ (+) Enable or disable the ADC peripheral
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes all ADCs peripherals registers to their default reset
+ * values.
+ * @param None
+ * @retval None
+ */
+void ADC_DeInit_mort(void)
+{
+ /* Enable all ADCs reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE);
+
+ /* Release all ADCs from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE);
+}
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStruct.
+ * @note This function is used to configure the global features of the ADC (
+ * Resolution and Data Alignment), however, the rest of the configuration
+ * parameters are specific to the regular channels group (scan mode
+ * activation, continuous mode activation, External trigger source and
+ * edge, number of conversion in the regular channels group sequencer).
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
+ * the configuration information for the specified ADC peripheral.
+ * @retval None
+ */
+void ADC_Init_mort(ADC_TypeDef_mort* ADCx, ADC_InitTypeDef_mort* ADC_InitStruct)
+{
+ uint32_t tmpreg1 = 0;
+ uint8_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_RESOLUTION_MORT(ADC_InitStruct->ADC_Resolution));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
+ assert_param(IS_ADC_EXT_TRIG_EDGE_MORT(ADC_InitStruct->ADC_ExternalTrigConvEdge));
+ assert_param(IS_ADC_EXT_TRIG_MORT(ADC_InitStruct->ADC_ExternalTrigConv));
+ assert_param(IS_ADC_DATA_ALIGN_MORT(ADC_InitStruct->ADC_DataAlign));
+ assert_param(IS_ADC_REGULAR_LENGTH_MORT(ADC_InitStruct->ADC_NbrOfConversion));
+
+ /*---------------------------- ADCx CR1 Configuration -----------------*/
+ /* Get the ADCx CR1 value */
+ tmpreg1 = ADCx->CR1;
+
+ /* Clear RES and SCAN bits */
+ tmpreg1 &= CR1_CLEAR_MASK;
+
+ /* Configure ADCx: scan conversion mode and resolution */
+ /* Set SCAN bit according to ADC_ScanConvMode value */
+ /* Set RES bit according to ADC_Resolution value */
+ tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \
+ ADC_InitStruct->ADC_Resolution);
+ /* Write to ADCx CR1 */
+ ADCx->CR1 = tmpreg1;
+ /*---------------------------- ADCx CR2 Configuration -----------------*/
+ /* Get the ADCx CR2 value */
+ tmpreg1 = ADCx->CR2;
+
+ /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */
+ tmpreg1 &= CR2_CLEAR_MASK;
+
+ /* Configure ADCx: external trigger event and edge, data alignment and
+ continuous conversion mode */
+ /* Set ALIGN bit according to ADC_DataAlign value */
+ /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */
+ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
+ /* Set CONT bit according to ADC_ContinuousConvMode value */
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \
+ ADC_InitStruct->ADC_ExternalTrigConv |
+ ADC_InitStruct->ADC_ExternalTrigConvEdge | \
+ ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+
+ /* Write to ADCx CR2 */
+ ADCx->CR2 = tmpreg1;
+ /*---------------------------- ADCx SQR1 Configuration -----------------*/
+ /* Get the ADCx SQR1 value */
+ tmpreg1 = ADCx->SQR1;
+
+ /* Clear L bits */
+ tmpreg1 &= SQR1_L_RESET;
+
+ /* Configure ADCx: regular channel sequence length */
+ /* Set L bits according to ADC_NbrOfConversion value */
+ tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);
+ tmpreg1 |= ((uint32_t)tmpreg2 << 20);
+
+ /* Write to ADCx SQR1 */
+ ADCx->SQR1 = tmpreg1;
+}
+
+/**
+ * @brief Fills each ADC_InitStruct member with its default value.
+ * @note This function is used to initialize the global features of the ADC (
+ * Resolution and Data Alignment), however, the rest of the configuration
+ * parameters are specific to the regular channels group (scan mode
+ * activation, continuous mode activation, External trigger source and
+ * edge, number of conversion in the regular channels group sequencer).
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void ADC_StructInit_mort(ADC_InitTypeDef_mort* ADC_InitStruct)
+{
+ /* Initialize the ADC_Mode member */
+ ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
+
+ /* initialize the ADC_ScanConvMode member */
+ ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+
+ /* Initialize the ADC_ContinuousConvMode member */
+ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+
+ /* Initialize the ADC_ExternalTrigConvEdge member */
+ ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
+
+ /* Initialize the ADC_ExternalTrigConv member */
+ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
+
+ /* Initialize the ADC_DataAlign member */
+ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+
+ /* Initialize the ADC_NbrOfConversion member */
+ ADC_InitStruct->ADC_NbrOfConversion = 1;
+}
+
+/**
+ * @brief Initializes the ADCs peripherals according to the specified parameters
+ * in the ADC_CommonInitStruct.
+ * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
+ * that contains the configuration information for All ADCs peripherals.
+ * @retval None
+ */
+void ADC_CommonInit_mort(ADC_CommonInitTypeDef_mort* ADC_CommonInitStruct)
+{
+ uint32_t tmpreg1 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_MODE_MORT(ADC_CommonInitStruct->ADC_Mode));
+ assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));
+ assert_param(IS_ADC_DMA_ACCESS_MODE_MORT(ADC_CommonInitStruct->ADC_DMAAccessMode));
+ assert_param(IS_ADC_SAMPLING_DELAY_MORT(ADC_CommonInitStruct->ADC_TwoSamplingDelay));
+ /*---------------------------- ADC CCR Configuration -----------------*/
+ /* Get the ADC CCR value */
+ tmpreg1 = ADC->CCR;
+
+ /* Clear MULTI, DELAY, DMA and ADCPRE bits */
+ tmpreg1 &= CR_CLEAR_MASK;
+
+ /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler,
+ and DMA access mode for multimode */
+ /* Set MULTI bits according to ADC_Mode value */
+ /* Set ADCPRE bits according to ADC_Prescaler value */
+ /* Set DMA bits according to ADC_DMAAccessMode value */
+ /* Set DELAY bits according to ADC_TwoSamplingDelay value */
+ tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode |
+ ADC_CommonInitStruct->ADC_Prescaler |
+ ADC_CommonInitStruct->ADC_DMAAccessMode |
+ ADC_CommonInitStruct->ADC_TwoSamplingDelay);
+
+ /* Write to ADC CCR */
+ ADC->CCR = tmpreg1;
+}
+
+/**
+ * @brief Fills each ADC_CommonInitStruct member with its default value.
+ * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
+ * which will be initialized.
+ * @retval None
+ */
+void ADC_CommonStructInit_mort(ADC_CommonInitTypeDef_mort* ADC_CommonInitStruct)
+{
+ /* Initialize the ADC_Mode member */
+ ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;
+
+ /* initialize the ADC_Prescaler member */
+ ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2;
+
+ /* Initialize the ADC_DMAAccessMode member */
+ ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
+
+ /* Initialize the ADC_TwoSamplingDelay member */
+ ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
+}
+
+/**
+ * @brief Enables or disables the specified ADC peripheral.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the ADCx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_Cmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the ADON bit to wake up the ADC from power down mode */
+ ADCx->CR2 |= (uint32_t)ADC_CR2_ADON_MORT;
+ }
+ else
+ {
+ /* Disable the selected ADC peripheral */
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON_MORT);
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Group2 Analog Watchdog configuration functions
+ * @brief Analog Watchdog configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Analog Watchdog configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to configure the Analog Watchdog
+ (AWD) feature in the ADC.
+
+ [..] A typical configuration Analog Watchdog is done following these steps :
+ (#) the ADC guarded channel(s) is (are) selected using the
+ ADC_AnalogWatchdogSingleChannelConfig() function.
+ (#) The Analog watchdog lower and higher threshold are configured using the
+ ADC_AnalogWatchdogThresholdsConfig() function.
+ (#) The Analog watchdog is enabled and configured to enable the check, on one
+ or more channels, using the ADC_AnalogWatchdogCmd() function.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the analog watchdog on single/all regular or
+ * injected channels
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+ * This parameter can be one of the following values:
+ * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
+ * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
+ * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
+ * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
+ * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
+ * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
+ * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
+ * @retval None
+ */
+void ADC_AnalogWatchdogCmd_mort(ADC_TypeDef_mort* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_MORT(ADC_AnalogWatchdog));
+
+ /* Get the old register value */
+ tmpreg = ADCx->CR1;
+
+ /* Clear AWDEN, JAWDEN and AWDSGL bits */
+ tmpreg &= CR1_AWDMode_RESET;
+
+ /* Set the analog watchdog enable mode */
+ tmpreg |= ADC_AnalogWatchdog;
+
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg;
+}
+
+/**
+ * @brief Configures the high and low thresholds of the analog watchdog.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param HighThreshold: the ADC analog watchdog High threshold value.
+ * This parameter must be a 12-bit value.
+ * @param LowThreshold: the ADC analog watchdog Low threshold value.
+ * This parameter must be a 12-bit value.
+ * @retval None
+ */
+void ADC_AnalogWatchdogThresholdsConfig_mort(ADC_TypeDef_mort* ADCx, uint16_t HighThreshold,
+ uint16_t LowThreshold)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_THRESHOLD_MORT(HighThreshold));
+ assert_param(IS_ADC_THRESHOLD_MORT(LowThreshold));
+
+ /* Set the ADCx high threshold */
+ ADCx->HTR = HighThreshold;
+
+ /* Set the ADCx low threshold */
+ ADCx->LTR = LowThreshold;
+}
+
+/**
+ * @brief Configures the analog watchdog guarded single channel
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_0: ADC Channel0 selected
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @arg ADC_Channel_18: ADC Channel18 selected
+ * @retval None
+ */
+void ADC_AnalogWatchdogSingleChannelConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_Channel)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+
+ /* Get the old register value */
+ tmpreg = ADCx->CR1;
+
+ /* Clear the Analog watchdog channel select bits */
+ tmpreg &= CR1_AWDCH_RESET;
+
+ /* Set the Analog watchdog channel */
+ tmpreg |= ADC_Channel;
+
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg;
+}
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal)
+ * and VBAT (Voltage BATtery) management functions
+ * @brief Temperature Sensor, Vrefint and VBAT management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Temperature Sensor, Vrefint and VBAT management functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to enable/ disable the internal
+ connections between the ADC and the Temperature Sensor, the Vrefint and
+ the Vbat sources.
+
+ [..] A typical configuration to get the Temperature sensor and Vrefint channels
+ voltages is done following these steps :
+ (#) Enable the internal connection of Temperature sensor and Vrefint sources
+ with the ADC channels using ADC_TempSensorVrefintCmd() function.
+ (#) Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using
+ ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions
+ (#) Get the voltage values, using ADC_GetConversionValue() or
+ ADC_GetInjectedConversionValue().
+
+ [..] A typical configuration to get the VBAT channel voltage is done following
+ these steps :
+ (#) Enable the internal connection of VBAT source with the ADC channel using
+ ADC_VBATCmd() function.
+ (#) Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or
+ ADC_InjectedChannelConfig() functions
+ (#) Get the voltage value, using ADC_GetConversionValue() or
+ ADC_GetInjectedConversionValue().
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enables or disables the temperature sensor and Vrefint channels.
+ * @param NewState: new state of the temperature sensor and Vrefint channels.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_TempSensorVrefintCmd_mort(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the temperature sensor and Vrefint channel*/
+ ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE_MORT;
+ }
+ else
+ {
+ /* Disable the temperature sensor and Vrefint channel*/
+ ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE_MORT);
+ }
+}
+
+/**
+ * @brief Enables or disables the VBAT (Voltage Battery) channel.
+ *
+ * @note the Battery voltage measured is equal to VBAT/2 on STM32F40xx and
+ * STM32F41xx devices and equal to VBAT/4 on STM32F42xx and STM32F43xx devices
+ *
+ * @param NewState: new state of the VBAT channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_VBATCmd_mort(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the VBAT channel*/
+ ADC->CCR |= (uint32_t)ADC_CCR_VBATE_MORT;
+ }
+ else
+ {
+ /* Disable the VBAT channel*/
+ ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE_MORT);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Group4 Regular Channels Configuration functions
+ * @brief Regular Channels Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Regular Channels Configuration functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to manage the ADC's regular channels,
+ it is composed of 2 sub sections :
+
+ (#) Configuration and management functions for regular channels: This subsection
+ provides functions allowing to configure the ADC regular channels :
+ (++) Configure the rank in the regular group sequencer for each channel
+ (++) Configure the sampling time for each channel
+ (++) select the conversion Trigger for regular channels
+ (++) select the desired EOC event behavior configuration
+ (++) Activate the continuous Mode (*)
+ (++) Activate the Discontinuous Mode
+ -@@- Please Note that the following features for regular channels
+ are configured using the ADC_Init() function :
+ (+@@) scan mode activation
+ (+@@) continuous mode activation (**)
+ (+@@) External trigger source
+ (+@@) External trigger edge
+ (+@@) number of conversion in the regular channels group sequencer.
+
+ -@@- (*) and (**) are performing the same configuration
+
+ (#) Get the conversion data: This subsection provides an important function in
+ the ADC peripheral since it returns the converted data of the current
+ regular channel. When the Conversion value is read, the EOC Flag is
+ automatically cleared.
+
+ -@- For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions
+ results data (in the selected multi mode) can be returned in the same
+ time using ADC_GetMultiModeConversionValue() function.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Configures for the selected ADC regular channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_0: ADC Channel0 selected
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @arg ADC_Channel_18: ADC Channel18 selected
+ * @param Rank: The rank in the regular group sequencer.
+ * This parameter must be between 1 to 16.
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
+ * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
+ * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
+ * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
+ * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
+ * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
+ * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
+ * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
+ * @retval None
+ */
+void ADC_RegularChannelConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ assert_param(IS_ADC_REGULAR_RANK_MORT(Rank));
+ assert_param(IS_ADC_SAMPLE_TIME_MORT(ADC_SampleTime));
+
+ /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+ if (ADC_Channel > ADC_Channel_9)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR1;
+
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10));
+
+ /* Clear the old sample time */
+ tmpreg1 &= ~tmpreg2;
+
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+
+ /* Set the new sample time */
+ tmpreg1 |= tmpreg2;
+
+ /* Store the new register value */
+ ADCx->SMPR1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR2;
+
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
+
+ /* Clear the old sample time */
+ tmpreg1 &= ~tmpreg2;
+
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+
+ /* Set the new sample time */
+ tmpreg1 |= tmpreg2;
+
+ /* Store the new register value */
+ ADCx->SMPR2 = tmpreg1;
+ }
+ /* For Rank 1 to 6 */
+ if (Rank < 7)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR3;
+
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1));
+
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+
+ /* Store the new register value */
+ ADCx->SQR3 = tmpreg1;
+ }
+ /* For Rank 7 to 12 */
+ else if (Rank < 13)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR2;
+
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7));
+
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+
+ /* Store the new register value */
+ ADCx->SQR2 = tmpreg1;
+ }
+ /* For Rank 13 to 16 */
+ else
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR1;
+
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13));
+
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+
+ /* Store the new register value */
+ ADCx->SQR1 = tmpreg1;
+ }
+}
+
+/**
+ * @brief Enables the selected ADC software start conversion of the regular channels.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_SoftwareStartConv_mort(ADC_TypeDef_mort* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Enable the selected ADC conversion for regular group */
+ ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART_MORT;
+}
+
+/**
+ * @brief Gets the selected ADC Software start regular conversion Status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC software start conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartConvStatus_mort(ADC_TypeDef_mort* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Check the status of SWSTART bit */
+ if ((ADCx->CR2 & ADC_CR2_SWSTART_MORT) != (uint32_t)RESET)
+ {
+ /* SWSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SWSTART bit is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the SWSTART bit status */
+ return bitstatus;
+}
+
+
+/**
+ * @brief Enables or disables the EOC on each regular channel conversion
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC EOC flag rising
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_EOCOnEachRegularChannelCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC EOC rising on each regular channel conversion */
+ ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS_MORT;
+ }
+ else
+ {
+ /* Disable the selected ADC EOC rising on each regular channel conversion */
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS_MORT);
+ }
+}
+
+/**
+ * @brief Enables or disables the ADC continuous conversion mode
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC continuous conversion mode
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ContinuousModeCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC continuous conversion mode */
+ ADCx->CR2 |= (uint32_t)ADC_CR2_CONT_MORT;
+ }
+ else
+ {
+ /* Disable the selected ADC continuous conversion mode */
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT_MORT);
+ }
+}
+
+/**
+ * @brief Configures the discontinuous mode for the selected ADC regular group
+ * channel.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param Number: specifies the discontinuous mode regular channel count value.
+ * This number must be between 1 and 8.
+ * @retval None
+ */
+void ADC_DiscModeChannelCountConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t Number)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_REGULAR_DISC_NUMBER_MORT(Number));
+
+ /* Get the old register value */
+ tmpreg1 = ADCx->CR1;
+
+ /* Clear the old discontinuous mode channel count */
+ tmpreg1 &= CR1_DISCNUM_RESET;
+
+ /* Set the discontinuous mode channel count */
+ tmpreg2 = Number - 1;
+ tmpreg1 |= tmpreg2 << 13;
+
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg1;
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode on regular group channel
+ * for the specified ADC
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC discontinuous mode on
+ * regular group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_DiscModeCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN_MORT;
+ }
+ else
+ {
+ /* Disable the selected ADC regular discontinuous mode */
+ ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN_MORT);
+ }
+}
+
+/**
+ * @brief Returns the last ADCx conversion result data for regular channel.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The Data conversion value.
+ */
+uint16_t ADC_GetConversionValue_mort(ADC_TypeDef_mort* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Return the selected ADC conversion value */
+ return (uint16_t) ADCx->DR;
+}
+
+/**
+ * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results
+ * data in the selected multi mode.
+ * @param None
+ * @retval The Data conversion value.
+ * @note In dual mode, the value returned by this function is as following
+ * Data[15:0] : these bits contain the regular data of ADC1.
+ * Data[31:16]: these bits contain the regular data of ADC2.
+ * @note In triple mode, the value returned by this function is as following
+ * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2.
+ * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3.
+ */
+uint32_t ADC_GetMultiModeConversionValue_mort(void)
+{
+ /* Return the multi mode conversion value */
+ return (*(__IO uint32_t *) CDR_ADDRESS);
+}
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions
+ * @brief Regular Channels DMA Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Regular Channels DMA Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to configure the DMA for ADC
+ regular channels.
+ Since converted regular channel values are stored into a unique data
+ register, it is useful to use DMA for conversion of more than one regular
+ channel. This avoids the loss of the data already stored in the ADC
+ Data register.
+ When the DMA mode is enabled (using the ADC_DMACmd() function), after each
+ conversion of a regular channel, a DMA request is generated.
+ [..] Depending on the "DMA disable selection for Independent ADC mode"
+ configuration (using the ADC_DMARequestAfterLastTransferCmd() function),
+ at the end of the last DMA transfer, two possibilities are allowed:
+ (+) No new DMA request is issued to the DMA controller (feature DISABLED)
+ (+) Requests can continue to be generated (feature ENABLED).
+ [..] Depending on the "DMA disable selection for multi ADC mode" configuration
+ (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function),
+ at the end of the last DMA transfer, two possibilities are allowed:
+ (+) No new DMA request is issued to the DMA controller (feature DISABLED)
+ (+) Requests can continue to be generated (feature ENABLED).
+
+@endverbatim
+ * @{
+ */
+
+ /**
+ * @brief Enables or disables the specified ADC DMA request.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_DMACmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC DMA request */
+ ADCx->CR2 |= (uint32_t)ADC_CR2_DMA_MORT;
+ }
+ else
+ {
+ /* Disable the selected ADC DMA request */
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA_MORT);
+ }
+}
+
+/**
+ * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC DMA request after last transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_DMARequestAfterLastTransferCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC DMA request after last transfer */
+ ADCx->CR2 |= (uint32_t)ADC_CR2_DDS_MORT;
+ }
+ else
+ {
+ /* Disable the selected ADC DMA request after last transfer */
+ ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS_MORT);
+ }
+}
+
+/**
+ * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode
+ * @param NewState: new state of the selected ADC DMA request after last transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note if Enabled, DMA requests are issued as long as data are converted and
+ * DMA mode for multi ADC mode (selected using ADC_CommonInit() function
+ * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is
+ * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3.
+ * @retval None
+ */
+void ADC_MultiModeDMARequestAfterLastTransferCmd_mort(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC DMA request after last transfer */
+ ADC->CCR |= (uint32_t)ADC_CCR_DDS_MORT;
+ }
+ else
+ {
+ /* Disable the selected ADC DMA request after last transfer */
+ ADC->CCR &= (uint32_t)(~ADC_CCR_DDS_MORT);
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Group6 Injected channels Configuration functions
+ * @brief Injected channels Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Injected channels Configuration functions #####
+ ===============================================================================
+
+ [..] This section provide functions allowing to configure the ADC Injected channels,
+ it is composed of 2 sub sections :
+
+ (#) Configuration functions for Injected channels: This subsection provides
+ functions allowing to configure the ADC injected channels :
+ (++) Configure the rank in the injected group sequencer for each channel
+ (++) Configure the sampling time for each channel
+ (++) Activate the Auto injected Mode
+ (++) Activate the Discontinuous Mode
+ (++) scan mode activation
+ (++) External/software trigger source
+ (++) External trigger edge
+ (++) injected channels sequencer.
+
+ (#) Get the Specified Injected channel conversion data: This subsection
+ provides an important function in the ADC peripheral since it returns the
+ converted data of the specific injected channel.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Configures for the selected ADC injected channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_0: ADC Channel0 selected
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @arg ADC_Channel_18: ADC Channel18 selected
+ * @param Rank: The rank in the injected group sequencer.
+ * This parameter must be between 1 to 4.
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
+ * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
+ * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
+ * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
+ * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
+ * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
+ * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
+ * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
+ * @retval None
+ */
+void ADC_InjectedChannelConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ assert_param(IS_ADC_INJECTED_RANK_MORT(Rank));
+ assert_param(IS_ADC_SAMPLE_TIME_MORT(ADC_SampleTime));
+ /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+ if (ADC_Channel > ADC_Channel_9)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10));
+ /* Clear the old sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
+ /* Set the new sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
+ /* Clear the old sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR2 = tmpreg1;
+ }
+ /* Rank configuration */
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSQR;
+ /* Get JL value: Number = JL+1 */
+ tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;
+ /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
+ tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Clear the old JSQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Set the JSQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->JSQR = tmpreg1;
+}
+
+/**
+ * @brief Configures the sequencer length for injected channels
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param Length: The sequencer length.
+ * This parameter must be a number between 1 to 4.
+ * @retval None
+ */
+void ADC_InjectedSequencerLengthConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t Length)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_LENGTH_MORT(Length));
+
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSQR;
+
+ /* Clear the old injected sequence length JL bits */
+ tmpreg1 &= JSQR_JL_RESET;
+
+ /* Set the injected sequence length JL bits */
+ tmpreg2 = Length - 1;
+ tmpreg1 |= tmpreg2 << 20;
+
+ /* Store the new register value */
+ ADCx->JSQR = tmpreg1;
+}
+
+/**
+ * @brief Set the injected channels conversion value offset
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_InjectedChannel: the ADC injected channel to set its offset.
+ * This parameter can be one of the following values:
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected
+ * @param Offset: the offset value for the selected ADC injected channel
+ * This parameter must be a 12bit value.
+ * @retval None
+ */
+void ADC_SetInjectedOffset_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+ __IO uint32_t tmp = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+ assert_param(IS_ADC_OFFSET(Offset));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel;
+
+ /* Set the selected injected channel data offset */
+ *(__IO uint32_t *) tmp = (uint32_t)Offset;
+}
+
+ /**
+ * @brief Configures the ADCx external trigger for injected channels conversion.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
+ * This parameter can be one of the following values:
+ * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected
+ * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected
+ * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected
+ * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected
+ * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected
+ * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected
+ * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected
+ * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected
+ * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected
+ * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected
+ * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected
+ * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected
+ * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected
+ * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected
+ * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected
+ * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected
+ * @retval None
+ */
+void ADC_ExternalTrigInjectedConvConfig_mort(ADC_TypeDef_mort* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
+
+ /* Get the old register value */
+ tmpreg = ADCx->CR2;
+
+ /* Clear the old external event selection for injected group */
+ tmpreg &= CR2_JEXTSEL_RESET;
+
+ /* Set the external event selection for injected group */
+ tmpreg |= ADC_ExternalTrigInjecConv;
+
+ /* Store the new register value */
+ ADCx->CR2 = tmpreg;
+}
+
+/**
+ * @brief Configures the ADCx external trigger edge for injected channels conversion.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge
+ * to start injected conversion.
+ * This parameter can be one of the following values:
+ * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for
+ * injected conversion
+ * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge
+ * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge
+ * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising
+ * and falling edge
+ * @retval None
+ */
+void ADC_ExternalTrigInjectedConvEdgeConfig_mort(ADC_TypeDef_mort* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE_MORT(ADC_ExternalTrigInjecConvEdge));
+ /* Get the old register value */
+ tmpreg = ADCx->CR2;
+ /* Clear the old external trigger edge for injected group */
+ tmpreg &= CR2_JEXTEN_RESET;
+ /* Set the new external trigger edge for injected group */
+ tmpreg |= ADC_ExternalTrigInjecConvEdge;
+ /* Store the new register value */
+ ADCx->CR2 = tmpreg;
+}
+
+/**
+ * @brief Enables the selected ADC software start conversion of the injected channels.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_SoftwareStartInjectedConv_mort(ADC_TypeDef_mort* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Enable the selected ADC conversion for injected group */
+ ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART_MORT;
+}
+
+/**
+ * @brief Gets the selected ADC Software start injected conversion Status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC software start injected conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus_mort(ADC_TypeDef_mort* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ /* Check the status of JSWSTART bit */
+ if ((ADCx->CR2 & ADC_CR2_JSWSTART_MORT) != (uint32_t)RESET)
+ {
+ /* JSWSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* JSWSTART bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the JSWSTART bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the selected ADC automatic injected group
+ * conversion after regular one.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC auto injected conversion
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_AutoInjectedConvCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC automatic injected group conversion */
+ ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO_MORT;
+ }
+ else
+ {
+ /* Disable the selected ADC automatic injected group conversion */
+ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO_MORT);
+ }
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode for injected group
+ * channel for the specified ADC
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC discontinuous mode on injected
+ * group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_InjectedDiscModeCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC injected discontinuous mode */
+ ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN_MORT;
+ }
+ else
+ {
+ /* Disable the selected ADC injected discontinuous mode */
+ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN_MORT);
+ }
+}
+
+/**
+ * @brief Returns the ADC injected channel conversion result
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_InjectedChannel: the converted ADC injected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected
+ * @retval The Data conversion value.
+ */
+uint16_t ADC_GetInjectedConversionValue_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_InjectedChannel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel + JDR_OFFSET;
+
+ /* Returns the selected injected channel conversion data value */
+ return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Group7 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure the ADC Interrupts
+ and to get the status and clear flags and Interrupts pending bits.
+
+ [..] Each ADC provides 4 Interrupts sources and 6 Flags which can be divided
+ into 3 groups:
+
+ *** Flags and Interrupts for ADC regular channels ***
+ =====================================================
+ [..]
+ (+) Flags :
+ (##) ADC_FLAG_OVR_MORT : Overrun detection when regular converted data are lost
+
+ (##) ADC_FLAG_EOC_MORT : Regular channel end of conversion ==> to indicate
+ (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() )
+ the end of:
+ (+++) a regular CHANNEL conversion
+ (+++) sequence of regular GROUP conversions .
+
+ (##) ADC_FLAG_STRT_MORT: Regular channel start ==> to indicate when regular
+ CHANNEL conversion starts.
+ [..]
+ (+) Interrupts :
+ (##) ADC_IT_OVR_MORT : specifies the interrupt source for Overrun detection
+ event.
+ (##) ADC_IT_EOC_MORT : specifies the interrupt source for Regular channel end
+ of conversion event.
+
+
+ *** Flags and Interrupts for ADC Injected channels ***
+ ======================================================
+ [..]
+ (+) Flags :
+ (##) ADC_FLAG_JEOC_MORT : Injected channel end of conversion ==> to indicate
+ at the end of injected GROUP conversion
+
+ (##) ADC_FLAG_JSTRT_MORT: Injected channel start ==> to indicate hardware when
+ injected GROUP conversion starts.
+ [..]
+ (+) Interrupts :
+ (##) ADC_IT_JEOC_MORT : specifies the interrupt source for Injected channel
+ end of conversion event.
+
+ *** General Flags and Interrupts for the ADC ***
+ ================================================
+ [..]
+ (+)Flags :
+ (##) ADC_FLAG_AWD_MORT: Analog watchdog ==> to indicate if the converted voltage
+ crosses the programmed thresholds values.
+ [..]
+ (+) Interrupts :
+ (##) ADC_IT_AWD_MORT : specifies the interrupt source for Analog watchdog event.
+
+
+ [..] The user should identify which mode will be used in his application to
+ manage the ADC controller events: Polling mode or Interrupt mode.
+
+ [..] In the Polling Mode it is advised to use the following functions:
+ (+) ADC_GetFlagStatus() : to check if flags events occur.
+ (+) ADC_ClearFlag() : to clear the flags events.
+
+ [..] In the Interrupt Mode it is advised to use the following functions:
+ (+) ADC_ITConfig() : to enable or disable the interrupt source.
+ (+) ADC_GetITStatus() : to check if Interrupt occurs.
+ (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
+ (corresponding Flag).
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Enables or disables the specified ADC interrupts.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ADC_IT_EOC_MORT: End of conversion interrupt mask
+ * @arg ADC_IT_AWD_MORT: Analog watchdog interrupt mask
+ * @arg ADC_IT_JEOC_MORT: End of injected conversion interrupt mask
+ * @arg ADC_IT_OVR_MORT: Overrun interrupt enable
+ * @param NewState: new state of the specified ADC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ITConfig_mort(ADC_TypeDef_mort* ADCx, uint16_t ADC_IT, FunctionalState NewState)
+{
+ uint32_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_ADC_IT(ADC_IT));
+
+ /* Get the ADC IT index */
+ itmask = (uint8_t)ADC_IT;
+ itmask = (uint32_t)0x01 << itmask;
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC interrupts */
+ ADCx->CR1 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected ADC interrupts */
+ ADCx->CR1 &= (~(uint32_t)itmask);
+ }
+}
+
+/**
+ * @brief Checks whether the specified ADC flag is set or not.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_AWD_MORT: Analog watchdog flag
+ * @arg ADC_FLAG_EOC_MORT: End of conversion flag
+ * @arg ADC_FLAG_JEOC_MORT: End of injected group conversion flag
+ * @arg ADC_FLAG_JSTRT_MORT: Start of injected group conversion flag
+ * @arg ADC_FLAG_STRT_MORT: Start of regular group conversion flag
+ * @arg ADC_FLAG_OVR_MORT: Overrun flag
+ * @retval The new state of ADC_FLAG (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatus_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+
+ /* Check the status of the specified ADC flag */
+ if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
+ {
+ /* ADC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's pending flags.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_AWD_MORT: Analog watchdog flag
+ * @arg ADC_FLAG_EOC_MORT: End of conversion flag
+ * @arg ADC_FLAG_JEOC_MORT: End of injected group conversion flag
+ * @arg ADC_FLAG_JSTRT_MORT: Start of injected group conversion flag
+ * @arg ADC_FLAG_STRT_MORT: Start of regular group conversion flag
+ * @arg ADC_FLAG_OVR_MORT: Overrun flag
+ * @retval None
+ */
+void ADC_ClearFlag_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+
+ /* Clear the selected ADC flags */
+ ADCx->SR = ~(uint32_t)ADC_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified ADC interrupt has occurred or not.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_IT_EOC_MORT: End of conversion interrupt mask
+ * @arg ADC_IT_AWD_MORT: Analog watchdog interrupt mask
+ * @arg ADC_IT_JEOC_MORT: End of injected conversion interrupt mask
+ * @arg ADC_IT_OVR_MORT: Overrun interrupt mask
+ * @retval The new state of ADC_IT (SET or RESET).
+ */
+ITStatus ADC_GetITStatus_mort(ADC_TypeDef_mort* ADCx, uint16_t ADC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t itmask = 0, enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_IT(ADC_IT));
+
+ /* Get the ADC IT index */
+ itmask = ADC_IT >> 8;
+
+ /* Get the ADC_IT enable bit status */
+ enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ;
+
+ /* Check the status of the specified ADC interrupt */
+ if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
+ {
+ /* ADC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's interrupt pending bits.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg ADC_IT_EOC_MORT: End of conversion interrupt mask
+ * @arg ADC_IT_AWD_MORT: Analog watchdog interrupt mask
+ * @arg ADC_IT_JEOC_MORT: End of injected conversion interrupt mask
+ * @arg ADC_IT_OVR_MORT: Overrun interrupt mask
+ * @retval None
+ */
+void ADC_ClearITPendingBit_mort(ADC_TypeDef_mort* ADCx, uint16_t ADC_IT)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_IT(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)(ADC_IT >> 8);
+ /* Clear the selected ADC interrupt pending bits */
+ ADCx->SR = ~(uint32_t)itmask;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/stm32f4xx_adc_mort.h Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,661 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_adc_mort.h
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file contains all the functions prototypes for the ADC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_ADC_H_MORT
+#define __STM32F4xx_ADC_H_MORT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_mort2.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief ADC Init structure definition
+ */
+typedef struct
+{
+ uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode.
+ This parameter can be a value of @ref ADC_resolution */
+ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion
+ is performed in Scan (multichannels)
+ or Single (one channel) mode.
+ This parameter can be set to ENABLE or DISABLE */
+ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion
+ is performed in Continuous or Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and
+ enable the trigger of a regular group.
+ This parameter can be a value of
+ @ref ADC_external_trigger_edge_for_regular_channels_conversion */
+ uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger
+ the start of conversion of a regular group.
+ This parameter can be a value of
+ @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment
+ is left or right. This parameter can be
+ a value of @ref ADC_data_align */
+ uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions
+ that will be done using the sequencer for
+ regular channel group.
+ This parameter must range from 1 to 16. */
+}ADC_InitTypeDef_mort;
+
+/**
+ * @brief ADC Common Init structure definition
+ */
+typedef struct
+{
+ uint32_t ADC_Mode; /*!< Configures the ADC to operate in
+ independent or multi mode.
+ This parameter can be a value of @ref ADC_Common_mode */
+ uint32_t ADC_Prescaler; /*!< Select the frequency of the clock
+ to the ADC. The clock is common for all the ADCs.
+ This parameter can be a value of @ref ADC_Prescaler */
+ uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access
+ mode for multi ADC mode.
+ This parameter can be a value of
+ @ref ADC_Direct_memory_access_mode_for_multi_mode */
+ uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
+ This parameter can be a value of
+ @ref ADC_delay_between_2_sampling_phases */
+
+}ADC_CommonInitTypeDef_mort;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants
+ * @{
+ */
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+ ((PERIPH) == ADC2) || \
+ ((PERIPH) == ADC3))
+
+/** @defgroup ADC_Common_mode
+ * @{
+ */
+#define ADC_Mode_Independent ((uint32_t)0x00000000)
+#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001)
+#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002)
+#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005)
+#define ADC_DualMode_RegSimult ((uint32_t)0x00000006)
+#define ADC_DualMode_Interl ((uint32_t)0x00000007)
+#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009)
+#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011)
+#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012)
+#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015)
+#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016)
+#define ADC_TripleMode_Interl ((uint32_t)0x00000017)
+#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019)
+#define IS_ADC_MODE_MORT(MODE) (((MODE) == ADC_Mode_Independent) || \
+ ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
+ ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
+ ((MODE) == ADC_DualMode_InjecSimult) || \
+ ((MODE) == ADC_DualMode_RegSimult) || \
+ ((MODE) == ADC_DualMode_Interl) || \
+ ((MODE) == ADC_DualMode_AlterTrig) || \
+ ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
+ ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
+ ((MODE) == ADC_TripleMode_InjecSimult) || \
+ ((MODE) == ADC_TripleMode_RegSimult) || \
+ ((MODE) == ADC_TripleMode_Interl) || \
+ ((MODE) == ADC_TripleMode_AlterTrig))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_Prescaler
+ * @{
+ */
+#define ADC_Prescaler_Div2 ((uint32_t)0x00000000)
+#define ADC_Prescaler_Div4 ((uint32_t)0x00010000)
+#define ADC_Prescaler_Div6 ((uint32_t)0x00020000)
+#define ADC_Prescaler_Div8 ((uint32_t)0x00030000)
+#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
+ ((PRESCALER) == ADC_Prescaler_Div4) || \
+ ((PRESCALER) == ADC_Prescaler_Div6) || \
+ ((PRESCALER) == ADC_Prescaler_Div8))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
+ * @{
+ */
+#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */
+#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
+#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
+#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
+#define IS_ADC_DMA_ACCESS_MODE_MORT(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
+ ((MODE) == ADC_DMAAccessMode_1) || \
+ ((MODE) == ADC_DMAAccessMode_2) || \
+ ((MODE) == ADC_DMAAccessMode_3))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_delay_between_2_sampling_phases
+ * @{
+ */
+#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000)
+#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100)
+#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200)
+#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300)
+#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400)
+#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500)
+#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600)
+#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700)
+#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800)
+#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900)
+#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00)
+#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00)
+#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00)
+#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00)
+#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00)
+#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00)
+#define IS_ADC_SAMPLING_DELAY_MORT(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
+ ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
+ ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
+ ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
+ ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
+ ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
+ ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
+ ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
+ ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
+ ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
+ ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
+ ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
+ ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
+ ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
+ ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
+ ((DELAY) == ADC_TwoSamplingDelay_20Cycles))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_resolution
+ * @{
+ */
+#define ADC_Resolution_12b ((uint32_t)0x00000000)
+#define ADC_Resolution_10b ((uint32_t)0x01000000)
+#define ADC_Resolution_8b ((uint32_t)0x02000000)
+#define ADC_Resolution_6b ((uint32_t)0x03000000)
+#define IS_ADC_RESOLUTION_MORT(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
+ ((RESOLUTION) == ADC_Resolution_10b) || \
+ ((RESOLUTION) == ADC_Resolution_8b) || \
+ ((RESOLUTION) == ADC_Resolution_6b))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
+ * @{
+ */
+#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
+#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
+#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
+#define IS_ADC_EXT_TRIG_EDGE_MORT(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
+ ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
+ ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
+ ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion
+ * @{
+ */
+#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000)
+#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000)
+#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
+#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000)
+#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000)
+#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
+#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
+#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000)
+#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000)
+#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000)
+#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000)
+#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000)
+#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000)
+#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000)
+#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
+#define IS_ADC_EXT_TRIG_MORT(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_data_align
+ * @{
+ */
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left ((uint32_t)0x00000800)
+#define IS_ADC_DATA_ALIGN_MORT(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+ ((ALIGN) == ADC_DataAlign_Left))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_channels
+ * @{
+ */
+#define ADC_Channel_0 ((uint8_t)0x00)
+#define ADC_Channel_1 ((uint8_t)0x01)
+#define ADC_Channel_2 ((uint8_t)0x02)
+#define ADC_Channel_3 ((uint8_t)0x03)
+#define ADC_Channel_4 ((uint8_t)0x04)
+#define ADC_Channel_5 ((uint8_t)0x05)
+#define ADC_Channel_6 ((uint8_t)0x06)
+#define ADC_Channel_7 ((uint8_t)0x07)
+#define ADC_Channel_8 ((uint8_t)0x08)
+#define ADC_Channel_9 ((uint8_t)0x09)
+#define ADC_Channel_10 ((uint8_t)0x0A)
+#define ADC_Channel_11 ((uint8_t)0x0B)
+#define ADC_Channel_12 ((uint8_t)0x0C)
+#define ADC_Channel_13 ((uint8_t)0x0D)
+#define ADC_Channel_14 ((uint8_t)0x0E)
+#define ADC_Channel_15 ((uint8_t)0x0F)
+#define ADC_Channel_16 ((uint8_t)0x10)
+#define ADC_Channel_17 ((uint8_t)0x11)
+#define ADC_Channel_18 ((uint8_t)0x12)
+
+#if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
+
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE)
+#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18)
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE */
+
+#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
+#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18)
+
+#define IS_ADC_CHANNEL_MORT(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
+ ((CHANNEL) == ADC_Channel_1) || \
+ ((CHANNEL) == ADC_Channel_2) || \
+ ((CHANNEL) == ADC_Channel_3) || \
+ ((CHANNEL) == ADC_Channel_4) || \
+ ((CHANNEL) == ADC_Channel_5) || \
+ ((CHANNEL) == ADC_Channel_6) || \
+ ((CHANNEL) == ADC_Channel_7) || \
+ ((CHANNEL) == ADC_Channel_8) || \
+ ((CHANNEL) == ADC_Channel_9) || \
+ ((CHANNEL) == ADC_Channel_10) || \
+ ((CHANNEL) == ADC_Channel_11) || \
+ ((CHANNEL) == ADC_Channel_12) || \
+ ((CHANNEL) == ADC_Channel_13) || \
+ ((CHANNEL) == ADC_Channel_14) || \
+ ((CHANNEL) == ADC_Channel_15) || \
+ ((CHANNEL) == ADC_Channel_16) || \
+ ((CHANNEL) == ADC_Channel_17) || \
+ ((CHANNEL) == ADC_Channel_18))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_sampling_times
+ * @{
+ */
+#define ADC_SampleTime_3Cycles ((uint8_t)0x00)
+#define ADC_SampleTime_15Cycles ((uint8_t)0x01)
+#define ADC_SampleTime_28Cycles ((uint8_t)0x02)
+#define ADC_SampleTime_56Cycles ((uint8_t)0x03)
+#define ADC_SampleTime_84Cycles ((uint8_t)0x04)
+#define ADC_SampleTime_112Cycles ((uint8_t)0x05)
+#define ADC_SampleTime_144Cycles ((uint8_t)0x06)
+#define ADC_SampleTime_480Cycles ((uint8_t)0x07)
+#define IS_ADC_SAMPLE_TIME_MORT(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
+ ((TIME) == ADC_SampleTime_15Cycles) || \
+ ((TIME) == ADC_SampleTime_28Cycles) || \
+ ((TIME) == ADC_SampleTime_56Cycles) || \
+ ((TIME) == ADC_SampleTime_84Cycles) || \
+ ((TIME) == ADC_SampleTime_112Cycles) || \
+ ((TIME) == ADC_SampleTime_144Cycles) || \
+ ((TIME) == ADC_SampleTime_480Cycles))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
+ * @{
+ */
+#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
+#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
+#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
+#define IS_ADC_EXT_INJEC_TRIG_EDGE_MORT(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
+ ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion
+ * @{
+ */
+#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000)
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000)
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000)
+#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000)
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000)
+#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
+#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
+#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000)
+#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000)
+#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000)
+#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000)
+#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000)
+#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000)
+#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
+#define IS_ADC_EXT_INJEC_TRIG_MORT(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_injected_channel_selection
+ * @{
+ */
+#define ADC_InjectedChannel_1 ((uint8_t)0x14)
+#define ADC_InjectedChannel_2 ((uint8_t)0x18)
+#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4 ((uint8_t)0x20)
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+ ((CHANNEL) == ADC_InjectedChannel_2) || \
+ ((CHANNEL) == ADC_InjectedChannel_3) || \
+ ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_analog_watchdog_selection
+ * @{
+ */
+#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
+#define IS_ADC_ANALOG_WATCHDOG_MORT(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_interrupts_definition
+ * @{
+ */
+#define ADC_IT_EOC_MORT ((uint16_t)0x0205)
+#define ADC_IT_AWD_MORT ((uint16_t)0x0106)
+#define ADC_IT_JEOC_MORT ((uint16_t)0x0407)
+#define ADC_IT_OVR_MORT ((uint16_t)0x201A)
+#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC_MORT) || ((IT) == ADC_IT_AWD_MORT) || \
+ ((IT) == ADC_IT_JEOC_MORT)|| ((IT) == ADC_IT_OVR_MORT))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_flags_definition
+ * @{
+ */
+#define ADC_FLAG_AWD_MORT ((uint8_t)0x01)
+#define ADC_FLAG_EOC_MORT ((uint8_t)0x02)
+#define ADC_FLAG_JEOC_MORT ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT_MORT ((uint8_t)0x08)
+#define ADC_FLAG_STRT_MORT ((uint8_t)0x10)
+#define ADC_FLAG_OVR_MORT ((uint8_t)0x20)
+
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD_MORT) || \
+ ((FLAG) == ADC_FLAG_EOC_MORT) || \
+ ((FLAG) == ADC_FLAG_JEOC_MORT) || \
+ ((FLAG)== ADC_FLAG_JSTRT_MORT) || \
+ ((FLAG) == ADC_FLAG_STRT_MORT) || \
+ ((FLAG)== ADC_FLAG_OVR_MORT))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_thresholds
+ * @{
+ */
+#define IS_ADC_THRESHOLD_MORT(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_injected_offset
+ * @{
+ */
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_injected_length
+ * @{
+ */
+#define IS_ADC_INJECTED_LENGTH_MORT(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_injected_rank
+ * @{
+ */
+#define IS_ADC_INJECTED_RANK_MORT(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_regular_length
+ * @{
+ */
+#define IS_ADC_REGULAR_LENGTH_MORT(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_regular_rank
+ * @{
+ */
+#define IS_ADC_REGULAR_RANK_MORT(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_regular_discontinuous_mode_number
+ * @{
+ */
+#define IS_ADC_REGULAR_DISC_NUMBER_MORT(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Function used to set the ADC configuration to the default reset state *****/
+void ADC_DeInit_mort(void);
+
+/* Initialization and Configuration functions *********************************/
+void ADC_Init_mort(ADC_TypeDef_mort* ADCx, ADC_InitTypeDef_mort* ADC_InitStruct);
+void ADC_StructInit_mort(ADC_InitTypeDef_mort* ADC_InitStruct);
+void ADC_CommonInit_mort(ADC_CommonInitTypeDef_mort* ADC_CommonInitStruct);
+void ADC_CommonStructInit_mort(ADC_CommonInitTypeDef_mort* ADC_CommonInitStruct);
+void ADC_Cmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState);
+
+/* Analog Watchdog configuration functions ************************************/
+void ADC_AnalogWatchdogCmd_mort(ADC_TypeDef_mort* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig_mort(ADC_TypeDef_mort* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_Channel);
+
+/* Temperature Sensor, Vrefint and VBAT management functions ******************/
+void ADC_TempSensorVrefintCmd_mort(FunctionalState NewState);
+void ADC_VBATCmd_mort(FunctionalState NewState);
+
+/* Regular Channels Configuration functions ***********************************/
+void ADC_RegularChannelConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_SoftwareStartConv_mort(ADC_TypeDef_mort* ADCx);
+FlagStatus ADC_GetSoftwareStartConvStatus_mort(ADC_TypeDef_mort* ADCx);
+void ADC_EOCOnEachRegularChannelCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState);
+void ADC_ContinuousModeCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState);
+void ADC_DiscModeChannelCountConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t Number);
+void ADC_DiscModeCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue_mort(ADC_TypeDef_mort* ADCx);
+uint32_t ADC_GetMultiModeConversionValue_mort(void);
+
+/* Regular Channels DMA Configuration functions *******************************/
+void ADC_DMACmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState);
+void ADC_DMARequestAfterLastTransferCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState);
+void ADC_MultiModeDMARequestAfterLastTransferCmd_mort(FunctionalState NewState);
+
+/* Injected channels Configuration functions **********************************/
+void ADC_InjectedChannelConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+void ADC_ExternalTrigInjectedConvConfig_mort(ADC_TypeDef_mort* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvEdgeConfig_mort(ADC_TypeDef_mort* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
+void ADC_SoftwareStartInjectedConv_mort(ADC_TypeDef_mort* ADCx);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus_mort(ADC_TypeDef_mort* ADCx);
+void ADC_AutoInjectedConvCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState);
+uint16_t ADC_GetInjectedConversionValue_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_InjectedChannel);
+
+/* Interrupts and flags management functions **********************************/
+void ADC_ITConfig_mort(ADC_TypeDef_mort* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus_mort(ADC_TypeDef_mort* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit_mort(ADC_TypeDef_mort* ADCx, uint16_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_ADC_H_MORT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/stm32f4xx_dma_mort.c Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,1306 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_dma.c
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Direct Memory Access controller (DMA):
+ * + Initialization and Configuration
+ * + Data Counter
+ * + Double Buffer mode configuration and command
+ * + Interrupts and flags management
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (#) Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE)
+ function for DMA1_MORT or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE)
+ function for DMA2_MORT.
+
+ (#) Enable and configure the peripheral to be connected to the DMA Stream
+ (except for internal SRAM / FLASH memories: no initialization is
+ necessary).
+
+ (#) For a given Stream, program the required configuration through following parameters:
+ Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination
+ data formats, Circular or Normal mode, Stream Priority level, Source and Destination
+ Incrementation mode, FIFO mode and its Threshold (if needed), Burst
+ mode for Source and/or Destination (if needed) using the DMA_Init() function.
+ To avoid filling unnecessary fields, you can call DMA_StructInit() function
+ to initialize a given structure with default values (reset values), the modify
+ only necessary fields
+ (ie. Source and Destination addresses, Transfer size and Data Formats).
+
+ (#) Enable the NVIC and the corresponding interrupt(s) using the function
+ DMA_ITConfig() if you need to use DMA interrupts.
+
+ (#) Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring
+ the second Memory address and the first Memory to be used through the function
+ DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function
+ DMA_DoubleBufferModeCmd(). These operations must be done before step 6.
+
+ (#) Enable the DMA stream using the DMA_Cmd() function.
+
+ (#) Activate the needed Stream Request using PPP_DMACmd() function for
+ any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
+ The function allowing this operation is provided in each PPP peripheral
+ driver (ie. SPI_DMACmd for SPI peripheral).
+ Once the Stream is enabled, it is not possible to modify its configuration
+ unless the stream is stopped and disabled.
+ After enabling the Stream, it is advised to monitor the EN bit status using
+ the function DMA_GetCmdStatus(). In case of configuration errors or bus errors
+ this bit will remain reset and all transfers on this Stream will remain on hold.
+
+ (#) Optionally, you can configure the number of data to be transferred
+ when the Stream is disabled (ie. after each Transfer Complete event
+ or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
+ And you can get the number of remaining data to be transferred using
+ the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is
+ enabled and running).
+
+ (#) To control DMA events you can use one of the following two methods:
+ (##) Check on DMA Stream flags using the function DMA_GetFlagStatus().
+ (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
+ phase and DMA_GetITStatus() function into interrupt routines in
+ communication phase.
+ [..]
+ After checking on a flag you should clear it using DMA_ClearFlag()
+ function. And after checking on an interrupt event you should
+ clear it using DMA_ClearITPendingBit() function.
+
+ (#) Optionally, if Circular mode and Double Buffer mode are enabled, you can modify
+ the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that
+ the Memory Address to be modified is not the one currently in use by DMA Stream.
+ This condition can be monitored using the function DMA_GetCurrentMemoryTarget().
+
+ (#) Optionally, Pause-Resume operations may be performed:
+ The DMA_Cmd() function may be used to perform Pause-Resume operation.
+ When a transfer is ongoing, calling this function to disable the
+ Stream will cause the transfer to be paused. All configuration registers
+ and the number of remaining data will be preserved. When calling again
+ this function to re-enable the Stream, the transfer will be resumed from
+ the point where it was paused.
+
+ -@- Memory-to-Memory transfer is possible by setting the address of the memory into
+ the Peripheral registers. In this mode, Circular mode and Double Buffer mode
+ are not allowed.
+
+ -@- The FIFO is used mainly to reduce bus usage and to allow data
+ packing/unpacking: it is possible to set different Data Sizes for
+ the Peripheral and the Memory (ie. you can set Half-Word data size
+ for the peripheral to access its data register and set Word data size
+ for the Memory to gain in access time. Each two Half-words will be
+ packed and written in a single access to a Word in the Memory).
+
+ -@- When FIFO is disabled, it is not allowed to configure different
+ Data Sizes for Source and Destination. In this case the Peripheral
+ Data Size will be applied to both Source and Destination.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_dma_mort.h"
+#include "stm32f4xx_rcc_mort.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DMA
+ * @brief DMA driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Masks Definition */
+#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE_MORT | DMA_SxCR_HTIE_MORT | \
+ DMA_SxCR_TEIE_MORT | DMA_SxCR_DMEIE_MORT)
+
+#define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0_MORT | DMA_LISR_DMEIF0_MORT | \
+ DMA_LISR_TEIF0_MORT | DMA_LISR_HTIF0_MORT | \
+ DMA_LISR_TCIF0_MORT)
+
+#define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6)
+#define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16)
+#define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22)
+#define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000)
+#define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000)
+#define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000)
+#define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000)
+#define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C
+#define HIGH_ISR_MASK (uint32_t)0x20000000
+#define RESERVED_MASK (uint32_t)0x0F7D0F7D
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/** @defgroup DMA_Private_Functions
+ * @{
+ */
+
+/** @defgroup DMA_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to initialize the DMA Stream source
+ and destination addresses, incrementation and data sizes, transfer direction,
+ buffer size, circular/normal mode selection, memory-to-memory mode selection
+ and Stream priority value.
+ [..]
+ The DMA_Init() function follows the DMA configuration procedures as described in
+ reference manual (RM0090) except the first point: waiting on EN bit to be reset.
+ This condition should be checked by user application using the function DMA_GetCmdStatus()
+ before calling the DMA_Init() function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitialize the DMAy Streamx registers to their default reset values.
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @retval None
+ */
+void DMA_DeInit_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+
+ /* Disable the selected DMAy Streamx */
+ DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN_MORT);
+
+ /* Reset DMAy Streamx control register */
+ DMAy_Streamx->CR = 0;
+
+ /* Reset DMAy Streamx Number of Data to Transfer register */
+ DMAy_Streamx->NDTR = 0;
+
+ /* Reset DMAy Streamx peripheral address register */
+ DMAy_Streamx->PAR = 0;
+
+ /* Reset DMAy Streamx memory 0 address register */
+ DMAy_Streamx->M0AR = 0;
+
+ /* Reset DMAy Streamx memory 1 address register */
+ DMAy_Streamx->M1AR = 0;
+
+ /* Reset DMAy Streamx FIFO control register */
+ DMAy_Streamx->FCR = (uint32_t)0x00000021;
+
+ /* Reset interrupt pending bits for the selected stream */
+ if (DMAy_Streamx == DMA1_Stream0_MORT)
+ {
+ /* Reset interrupt pending bits for DMA1_MORT Stream0 */
+ DMA1_MORT->LIFCR = DMA_Stream0_IT_MASK;
+ }
+ else if (DMAy_Streamx == DMA1_Stream1_MORT)
+ {
+ /* Reset interrupt pending bits for DMA1_MORT Stream1 */
+ DMA1_MORT->LIFCR = DMA_Stream1_IT_MASK;
+ }
+ else if (DMAy_Streamx == DMA1_Stream2_MORT)
+ {
+ /* Reset interrupt pending bits for DMA1_MORT Stream2 */
+ DMA1_MORT->LIFCR = DMA_Stream2_IT_MASK;
+ }
+ else if (DMAy_Streamx == DMA1_Stream3_MORT)
+ {
+ /* Reset interrupt pending bits for DMA1_MORT Stream3 */
+ DMA1_MORT->LIFCR = DMA_Stream3_IT_MASK;
+ }
+ else if (DMAy_Streamx == DMA1_Stream4_MORT)
+ {
+ /* Reset interrupt pending bits for DMA1_MORT Stream4 */
+ DMA1_MORT->HIFCR = DMA_Stream4_IT_MASK;
+ }
+ else if (DMAy_Streamx == DMA1_Stream5_MORT)
+ {
+ /* Reset interrupt pending bits for DMA1_MORT Stream5 */
+ DMA1_MORT->HIFCR = DMA_Stream5_IT_MASK;
+ }
+ else if (DMAy_Streamx == DMA1_Stream6_MORT)
+ {
+ /* Reset interrupt pending bits for DMA1_MORT Stream6 */
+ DMA1_MORT->HIFCR = (uint32_t)DMA_Stream6_IT_MASK;
+ }
+ else if (DMAy_Streamx == DMA1_Stream7_MORT)
+ {
+ /* Reset interrupt pending bits for DMA1_MORT Stream7 */
+ DMA1_MORT->HIFCR = DMA_Stream7_IT_MASK;
+ }
+ else if (DMAy_Streamx == DMA2_Stream0_MORT)
+ {
+ /* Reset interrupt pending bits for DMA2_MORT Stream0 */
+ DMA2_MORT->LIFCR = DMA_Stream0_IT_MASK;
+ }
+ else if (DMAy_Streamx == DMA2_Stream1_MORT)
+ {
+ /* Reset interrupt pending bits for DMA2_MORT Stream1 */
+ DMA2_MORT->LIFCR = DMA_Stream1_IT_MASK;
+ }
+ else if (DMAy_Streamx == DMA2_Stream2_MORT)
+ {
+ /* Reset interrupt pending bits for DMA2_MORT Stream2 */
+ DMA2_MORT->LIFCR = DMA_Stream2_IT_MASK;
+ }
+ else if (DMAy_Streamx == DMA2_Stream3_MORT)
+ {
+ /* Reset interrupt pending bits for DMA2_MORT Stream3 */
+ DMA2_MORT->LIFCR = DMA_Stream3_IT_MASK;
+ }
+ else if (DMAy_Streamx == DMA2_Stream4_MORT)
+ {
+ /* Reset interrupt pending bits for DMA2_MORT Stream4 */
+ DMA2_MORT->HIFCR = DMA_Stream4_IT_MASK;
+ }
+ else if (DMAy_Streamx == DMA2_Stream5_MORT)
+ {
+ /* Reset interrupt pending bits for DMA2_MORT Stream5 */
+ DMA2_MORT->HIFCR = DMA_Stream5_IT_MASK;
+ }
+ else if (DMAy_Streamx == DMA2_Stream6_MORT)
+ {
+ /* Reset interrupt pending bits for DMA2_MORT Stream6 */
+ DMA2_MORT->HIFCR = DMA_Stream6_IT_MASK;
+ }
+ else
+ {
+ if (DMAy_Streamx == DMA2_Stream7_MORT)
+ {
+ /* Reset interrupt pending bits for DMA2_MORT Stream7 */
+ DMA2_MORT->HIFCR = DMA_Stream7_IT_MASK;
+ }
+ }
+}
+
+/**
+ * @brief Initializes the DMAy Streamx according to the specified parameters in
+ * the DMA_InitStruct structure.
+ * @note Before calling this function, it is recommended to check that the Stream
+ * is actually disabled using the function DMA_GetCmdStatus().
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval None
+ */
+void DMA_Init_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, DMA_InitTypeDef_mort* DMA_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+ assert_param(IS_DMA_CHANNEL_MORT(DMA_InitStruct->DMA_Channel));
+ assert_param(IS_DMA_DIRECTION_MORT(DMA_InitStruct->DMA_DIR));
+ assert_param(IS_DMA_BUFFER_SIZE_MORT(DMA_InitStruct->DMA_BufferSize));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE_MORT(DMA_InitStruct->DMA_PeripheralInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE_MORT(DMA_InitStruct->DMA_MemoryInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE_MORT(DMA_InitStruct->DMA_PeripheralDataSize));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE_MORT(DMA_InitStruct->DMA_MemoryDataSize));
+ assert_param(IS_DMA_MODE_MORT(DMA_InitStruct->DMA_Mode));
+ assert_param(IS_DMA_PRIORITY_MORT(DMA_InitStruct->DMA_Priority));
+ assert_param(IS_DMA_FIFO_MODE_STATE_MORT(DMA_InitStruct->DMA_FIFOMode));
+ assert_param(IS_DMA_FIFO_THRESHOLD_MORT(DMA_InitStruct->DMA_FIFOThreshold));
+ assert_param(IS_DMA_MEMORY_BURST_MORT(DMA_InitStruct->DMA_MemoryBurst));
+ assert_param(IS_DMA_PERIPHERAL_BURST_MORT(DMA_InitStruct->DMA_PeripheralBurst));
+
+ /*------------------------- DMAy Streamx CR Configuration ------------------*/
+ /* Get the DMAy_Streamx CR value */
+ tmpreg = DMAy_Streamx->CR;
+
+ /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+ tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL_MORT | DMA_SxCR_MBURST_MORT | DMA_SxCR_PBURST_MORT | \
+ DMA_SxCR_PL_MORT | DMA_SxCR_MSIZE_MORT | DMA_SxCR_PSIZE_MORT | \
+ DMA_SxCR_MINC_MORT | DMA_SxCR_PINC_MORT | DMA_SxCR_CIRC_MORT | \
+ DMA_SxCR_DIR_MORT));
+
+ /* Configure DMAy Streamx: */
+ /* Set CHSEL bits according to DMA_CHSEL value */
+ /* Set DIR bits according to DMA_DIR value */
+ /* Set PINC bit according to DMA_PeripheralInc value */
+ /* Set MINC bit according to DMA_MemoryInc value */
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */
+ /* Set CIRC bit according to DMA_Mode value */
+ /* Set PL bits according to DMA_Priority value */
+ /* Set MBURST bits according to DMA_MemoryBurst value */
+ /* Set PBURST bits according to DMA_PeripheralBurst value */
+ tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR |
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+ DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority |
+ DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst;
+
+ /* Write to DMAy Streamx CR register */
+ DMAy_Streamx->CR = tmpreg;
+
+ /*------------------------- DMAy Streamx FCR Configuration -----------------*/
+ /* Get the DMAy_Streamx FCR value */
+ tmpreg = DMAy_Streamx->FCR;
+
+ /* Clear DMDIS and FTH bits */
+ tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS_MORT | DMA_SxFCR_FTH_MORT);
+
+ /* Configure DMAy Streamx FIFO:
+ Set DMDIS bits according to DMA_FIFOMode value
+ Set FTH bits according to DMA_FIFOThreshold value */
+ tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold;
+
+ /* Write to DMAy Streamx CR */
+ DMAy_Streamx->FCR = tmpreg;
+
+ /*------------------------- DMAy Streamx NDTR Configuration ----------------*/
+ /* Write to DMAy Streamx NDTR register */
+ DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize;
+
+ /*------------------------- DMAy Streamx PAR Configuration -----------------*/
+ /* Write to DMAy Streamx PAR */
+ DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+ /*------------------------- DMAy Streamx M0AR Configuration ----------------*/
+ /* Write to DMAy Streamx M0AR */
+ DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr;
+}
+
+/**
+ * @brief Fills each DMA_InitStruct member with its default value.
+ * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void DMA_StructInit_mort(DMA_InitTypeDef_mort* DMA_InitStruct)
+{
+ /*-------------- Reset DMA init structure parameters values ----------------*/
+ /* Initialize the DMA_Channel member */
+ DMA_InitStruct->DMA_Channel = 0;
+
+ /* Initialize the DMA_PeripheralBaseAddr member */
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+
+ /* Initialize the DMA_Memory0BaseAddr member */
+ DMA_InitStruct->DMA_Memory0BaseAddr = 0;
+
+ /* Initialize the DMA_DIR member */
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory;
+
+ /* Initialize the DMA_BufferSize member */
+ DMA_InitStruct->DMA_BufferSize = 0;
+
+ /* Initialize the DMA_PeripheralInc member */
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+
+ /* Initialize the DMA_MemoryInc member */
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+
+ /* Initialize the DMA_PeripheralDataSize member */
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+
+ /* Initialize the DMA_MemoryDataSize member */
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+
+ /* Initialize the DMA_Mode member */
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+
+ /* Initialize the DMA_Priority member */
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+
+ /* Initialize the DMA_FIFOMode member */
+ DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable;
+
+ /* Initialize the DMA_FIFOThreshold member */
+ DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
+
+ /* Initialize the DMA_MemoryBurst member */
+ DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single;
+
+ /* Initialize the DMA_PeripheralBurst member */
+ DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Streamx.
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @param NewState: new state of the DMAy Streamx.
+ * This parameter can be: ENABLE or DISABLE.
+ *
+ * @note This function may be used to perform Pause-Resume operation. When a
+ * transfer is ongoing, calling this function to disable the Stream will
+ * cause the transfer to be paused. All configuration registers and the
+ * number of remaining data will be preserved. When calling again this
+ * function to re-enable the Stream, the transfer will be resumed from
+ * the point where it was paused.
+ *
+ * @note After configuring the DMA Stream (DMA_Init() function) and enabling the
+ * stream, it is recommended to check (or wait until) the DMA Stream is
+ * effectively enabled. A Stream may remain disabled if a configuration
+ * parameter is wrong.
+ * After disabling a DMA Stream, it is also recommended to check (or wait
+ * until) the DMA Stream is effectively disabled. If a Stream is disabled
+ * while a data transfer is ongoing, the current data will be transferred
+ * and the Stream will be effectively disabled only after the transfer of
+ * this single data is finished.
+ *
+ * @retval None
+ */
+void DMA_Cmd_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMAy Streamx by setting EN bit */
+ DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN_MORT;
+ }
+ else
+ {
+ /* Disable the selected DMAy Streamx by clearing EN bit */
+ DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN_MORT;
+ }
+}
+
+/**
+ * @brief Configures, when the PINC (Peripheral Increment address mode) bit is
+ * set, if the peripheral address should be incremented with the data
+ * size (configured with PSIZE bits) or by a fixed offset equal to 4
+ * (32-bit aligned addresses).
+ *
+ * @note This function has no effect if the Peripheral Increment mode is disabled.
+ *
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @param DMA_Pincos: specifies the Peripheral increment offset size.
+ * This parameter can be one of the following values:
+ * @arg DMA_PINCOS_Psize: Peripheral address increment is done
+ * accordingly to PSIZE parameter.
+ * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is
+ * fixed to 4 (32-bit aligned addresses).
+ * @retval None
+ */
+void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_Pincos)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+ assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos));
+
+ /* Check the needed Peripheral increment offset */
+ if(DMA_Pincos != DMA_PINCOS_Psize)
+ {
+ /* Configure DMA_SxCR_PINCOS_MORT bit with the input parameter */
+ DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS_MORT;
+ }
+ else
+ {
+ /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */
+ DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS_MORT;
+ }
+}
+
+/**
+ * @brief Configures, when the DMAy Streamx is disabled, the flow controller for
+ * the next transactions (Peripheral or Memory).
+ *
+ * @note Before enabling this feature, check if the used peripheral supports
+ * the Flow Controller mode or not.
+ *
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @param DMA_FlowCtrl: specifies the DMA flow controller.
+ * This parameter can be one of the following values:
+ * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is
+ * the DMA controller.
+ * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller
+ * is the peripheral.
+ * @retval None
+ */
+void DMA_FlowControllerConfig(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FlowCtrl)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+ assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl));
+
+ /* Check the needed flow controller */
+ if(DMA_FlowCtrl != DMA_FlowCtrl_Memory)
+ {
+ /* Configure DMA_SxCR_PFCTRL_MORT bit with the input parameter */
+ DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL_MORT;
+ }
+ else
+ {
+ /* Clear the PFCTRL bit: Memory is the flow controller */
+ DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL_MORT;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Group2 Data Counter functions
+ * @brief Data Counter functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Data Counter functions #####
+ ===============================================================================
+ [..]
+ This subsection provides function allowing to configure and read the buffer size
+ (number of data to be transferred).
+ [..]
+ The DMA data counter can be written only when the DMA Stream is disabled
+ (ie. after transfer complete event).
+ [..]
+ The following function can be used to write the Stream data counter value:
+ (+) void DMA_SetCurrDataCounter(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint16_t Counter);
+ -@- It is advised to use this function rather than DMA_Init() in situations
+ where only the Data buffer needs to be reloaded.
+ -@- If the Source and Destination Data Sizes are different, then the value
+ written in data counter, expressing the number of transfers, is relative
+ to the number of transfers from the Peripheral point of view.
+ ie. If Memory data size is Word, Peripheral data size is Half-Words,
+ then the value to be configured in the data counter is the number
+ of Half-Words to be transferred from/to the peripheral.
+ [..]
+ The DMA data counter can be read to indicate the number of remaining transfers for
+ the relative DMA Stream. This counter is decremented at the end of each data
+ transfer and when the transfer is complete:
+ (+) If Normal mode is selected: the counter is set to 0.
+ (+) If Circular mode is selected: the counter is reloaded with the initial value
+ (configured before enabling the DMA Stream)
+ [..]
+ The following function can be used to read the Stream data counter value:
+ (+) uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef_mort* DMAy_Streamx);
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Writes the number of data units to be transferred on the DMAy Streamx.
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @param Counter: Number of data units to be transferred (from 0 to 65535)
+ * Number of data items depends only on the Peripheral data format.
+ *
+ * @note If Peripheral data format is Bytes: number of data units is equal
+ * to total number of bytes to be transferred.
+ *
+ * @note If Peripheral data format is Half-Word: number of data units is
+ * equal to total number of bytes to be transferred / 2.
+ *
+ * @note If Peripheral data format is Word: number of data units is equal
+ * to total number of bytes to be transferred / 4.
+ *
+ * @note In Memory-to-Memory transfer mode, the memory buffer pointed by
+ * DMAy_SxPAR register is considered as Peripheral.
+ *
+ * @retval The number of remaining data units in the current DMAy Streamx transfer.
+ */
+void DMA_SetCurrDataCounter(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint16_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+
+ /* Write the number of data units to be transferred */
+ DMAy_Streamx->NDTR = (uint16_t)Counter;
+}
+
+/**
+ * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @retval The number of remaining data units in the current DMAy Streamx transfer.
+ */
+uint16_t DMA_GetCurrDataCounter_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+
+ /* Return the number of remaining data units for DMAy Streamx */
+ return ((uint16_t)(DMAy_Streamx->NDTR));
+}
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Group3 Double Buffer mode functions
+ * @brief Double Buffer mode functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Double Buffer mode functions #####
+ ===============================================================================
+ [..]
+ This subsection provides function allowing to configure and control the double
+ buffer mode parameters.
+
+ [..]
+ The Double Buffer mode can be used only when Circular mode is enabled.
+ The Double Buffer mode cannot be used when transferring data from Memory to Memory.
+
+ [..]
+ The Double Buffer mode allows to set two different Memory addresses from/to which
+ the DMA controller will access alternatively (after completing transfer to/from
+ target memory 0, it will start transfer to/from target memory 1).
+ This allows to reduce software overhead for double buffering and reduce the CPU
+ access time.
+
+ [..]
+ Two functions must be called before calling the DMA_Init() function:
+ (+) void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef_mort* DMAy_Streamx,
+ uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory);
+ (+) void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef_mort* DMAy_Streamx, FunctionalState NewState);
+
+ [..]
+ DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address
+ and the first Memory target from/to which the transfer will start after
+ enabling the DMA Stream. Then DMA_DoubleBufferModeCmd() must be called
+ to enable the Double Buffer mode (or disable it when it should not be used).
+
+ [..]
+ Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is
+ stopped) to modify on of the target Memories addresses or to check which Memory target is currently
+ used:
+ (+) void DMA_MemoryTargetConfig(DMA_Stream_TypeDef_mort* DMAy_Streamx,
+ uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget);
+ (+) uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef_mort* DMAy_Streamx);
+
+ [..]
+ DMA_MemoryTargetConfig() can be called to modify the base address of one of
+ the two target Memories.
+ The Memory of which the base address will be modified must not be currently
+ be used by the DMA Stream (ie. if the DMA Stream is currently transferring
+ from Memory 1 then you can only modify base address of target Memory 0 and vice versa).
+ To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which
+ returns the index of the Memory target currently in use by the DMA Stream.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode
+ * and the current memory target.
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @param Memory1BaseAddr: the base address of the second buffer (Memory 1)
+ * @param DMA_CurrentMemory: specifies which memory will be first buffer for
+ * the transactions when the Stream will be enabled.
+ * This parameter can be one of the following values:
+ * @arg DMA_Memory_0: Memory 0 is the current buffer.
+ * @arg DMA_Memory_1: Memory 1 is the current buffer.
+ *
+ * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init().
+ *
+ * @retval None
+ */
+void DMA_DoubleBufferModeConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t Memory1BaseAddr,
+ uint32_t DMA_CurrentMemory)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+ assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory));
+
+ if (DMA_CurrentMemory != DMA_Memory_0)
+ {
+ /* Set Memory 1 as current memory address */
+ DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT_MORT);
+ }
+ else
+ {
+ /* Set Memory 0 as current memory address */
+ DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT_MORT);
+ }
+
+ /* Write to DMAy Streamx M1AR */
+ DMAy_Streamx->M1AR = Memory1BaseAddr;
+}
+
+/**
+ * @brief Enables or disables the double buffer mode for the selected DMA stream.
+ * @note This function can be called only when the DMA Stream is disabled.
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @param NewState: new state of the DMAy Streamx double buffer mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DMA_DoubleBufferModeCmd_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* Configure the Double Buffer mode */
+ if (NewState != DISABLE)
+ {
+ /* Enable the Double buffer mode */
+ DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM_MORT;
+ }
+ else
+ {
+ /* Disable the Double buffer mode */
+ DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM_MORT;
+ }
+}
+
+/**
+ * @brief Configures the Memory address for the next buffer transfer in double
+ * buffer mode (for dynamic use). This function can be called when the
+ * DMA Stream is enabled and when the transfer is ongoing.
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @param MemoryBaseAddr: The base address of the target memory buffer
+ * @param DMA_MemoryTarget: Next memory target to be used.
+ * This parameter can be one of the following values:
+ * @arg DMA_Memory_0: To use the memory address 0
+ * @arg DMA_Memory_1: To use the memory address 1
+ *
+ * @note It is not allowed to modify the Base Address of a target Memory when
+ * this target is involved in the current transfer. ie. If the DMA Stream
+ * is currently transferring to/from Memory 1, then it not possible to
+ * modify Base address of Memory 1, but it is possible to modify Base
+ * address of Memory 0.
+ * To know which Memory is currently used, you can use the function
+ * DMA_GetCurrentMemoryTarget().
+ *
+ * @retval None
+ */
+void DMA_MemoryTargetConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t MemoryBaseAddr,
+ uint32_t DMA_MemoryTarget)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+ assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget));
+
+ /* Check the Memory target to be configured */
+ if (DMA_MemoryTarget != DMA_Memory_0)
+ {
+ /* Write to DMAy Streamx M1AR */
+ DMAy_Streamx->M1AR = MemoryBaseAddr;
+ }
+ else
+ {
+ /* Write to DMAy Streamx M0AR */
+ DMAy_Streamx->M0AR = MemoryBaseAddr;
+ }
+}
+
+/**
+ * @brief Returns the current memory target used by double buffer transfer.
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @retval The memory target number: 0 for Memory0 or 1 for Memory1.
+ */
+uint32_t DMA_GetCurrentMemoryTarget_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+
+ /* Get the current memory target */
+ if ((DMAy_Streamx->CR & DMA_SxCR_CT_MORT) != 0)
+ {
+ /* Current memory buffer used is Memory 1 */
+ tmp = 1;
+ }
+ else
+ {
+ /* Current memory buffer used is Memory 0 */
+ tmp = 0;
+ }
+ return tmp;
+}
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Group4 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DMA enable status
+ (+) Check the FIFO status
+ (+) Configure the DMA Interrupts sources and check or clear the flags or
+ pending bits status.
+
+ [..]
+ (#) DMA Enable status:
+ After configuring the DMA Stream (DMA_Init() function) and enabling
+ the stream, it is recommended to check (or wait until) the DMA Stream
+ is effectively enabled. A Stream may remain disabled if a configuration
+ parameter is wrong. After disabling a DMA Stream, it is also recommended
+ to check (or wait until) the DMA Stream is effectively disabled.
+ If a Stream is disabled while a data transfer is ongoing, the current
+ data will be transferred and the Stream will be effectively disabled
+ only after this data transfer completion.
+ To monitor this state it is possible to use the following function:
+ (++) FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef_mort* DMAy_Streamx);
+
+ (#) FIFO Status:
+ It is possible to monitor the FIFO status when a transfer is ongoing
+ using the following function:
+ (++) uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef_mort* DMAy_Streamx);
+
+ (#) DMA Interrupts and Flags:
+ The user should identify which mode will be used in his application
+ to manage the DMA controller events: Polling mode or Interrupt mode.
+
+ *** Polling Mode ***
+ ====================
+ [..]
+ Each DMA stream can be managed through 4 event Flags:
+ (x : DMA Stream number )
+ (#) DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred.
+ (#) DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred.
+ (#) DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred.
+ (#) DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred.
+ (#) DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred .
+ [..]
+ In this Mode it is advised to use the following functions:
+ (+) FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FLAG);
+ (+) void DMA_ClearFlag(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FLAG);
+
+ *** Interrupt Mode ***
+ ======================
+ [..]
+ Each DMA Stream can be managed through 4 Interrupts:
+
+ *** Interrupt Source ***
+ ========================
+ [..]
+ (#) DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event.
+ (#) DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event.
+ (#) DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event.
+ (#) DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event.
+ (#) DMA_IT_TC_MORTIFx : specifies the interrupt source for the a Transfer Complete event.
+ [..]
+ In this Mode it is advised to use the following functions:
+ (+) void DMA_ITConfig(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
+ (+) ITStatus DMA_GetITStatus(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT);
+ (+) void DMA_ClearITPendingBit(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT);
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the status of EN bit for the specified DMAy Streamx.
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ *
+ * @note After configuring the DMA Stream (DMA_Init() function) and enabling
+ * the stream, it is recommended to check (or wait until) the DMA Stream
+ * is effectively enabled. A Stream may remain disabled if a configuration
+ * parameter is wrong.
+ * After disabling a DMA Stream, it is also recommended to check (or wait
+ * until) the DMA Stream is effectively disabled. If a Stream is disabled
+ * while a data transfer is ongoing, the current data will be transferred
+ * and the Stream will be effectively disabled only after the transfer
+ * of this single data is finished.
+ *
+ * @retval Current state of the DMAy Streamx (ENABLE or DISABLE).
+ */
+FunctionalState DMA_GetCmdStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx)
+{
+ FunctionalState state = DISABLE;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+
+ if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN_MORT) != 0)
+ {
+ /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */
+ state = ENABLE;
+ }
+ else
+ {
+ /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and
+ all transfers are complete) */
+ state = DISABLE;
+ }
+ return state;
+}
+
+/**
+ * @brief Returns the current DMAy Streamx FIFO filled level.
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @retval The FIFO filling state.
+ * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
+ * and not empty.
+ * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
+ * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
+ * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
+ * - DMA_FIFOStatus_Empty: when FIFO is empty
+ * - DMA_FIFOStatus_Full: when FIFO is full
+ */
+uint32_t DMA_GetFIFOStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+
+ /* Get the FIFO level bits */
+ tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS_MORT));
+
+ return tmpreg;
+}
+
+/**
+ * @brief Checks whether the specified DMAy Streamx flag is set or not.
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @param DMA_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag
+ * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag
+ * @arg DMA_FLAG_TEIFx: Streamx transfer error flag
+ * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
+ * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag
+ * Where x can be 0 to 7 to select the DMA Stream.
+ * @retval The new state of DMA_FLAG (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ DMA_TypeDef_mort* DMAy;
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+ assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
+
+ /* Determine the DMA to which belongs the stream */
+ if (DMAy_Streamx < DMA2_Stream0_MORT)
+ {
+ /* DMAy_Streamx belongs to DMA1_MORT */
+ DMAy = DMA1_MORT;
+ }
+ else
+ {
+ /* DMAy_Streamx belongs to DMA2_MORT */
+ DMAy = DMA2_MORT;
+ }
+
+ /* Check if the flag is in HISR or LISR */
+ if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
+ {
+ /* Get DMAy HISR register value */
+ tmpreg = DMAy->HISR;
+ }
+ else
+ {
+ /* Get DMAy LISR register value */
+ tmpreg = DMAy->LISR;
+ }
+
+ /* Mask the reserved bits */
+ tmpreg &= (uint32_t)RESERVED_MASK;
+
+ /* Check the status of the specified DMA flag */
+ if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
+ {
+ /* DMA_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMA_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the DMA_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Streamx's pending flags.
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @param DMA_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag
+ * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag
+ * @arg DMA_FLAG_TEIFx: Streamx transfer error flag
+ * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
+ * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag
+ * Where x can be 0 to 7 to select the DMA Stream.
+ * @retval None
+ */
+void DMA_ClearFlag_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FLAG)
+{
+ DMA_TypeDef_mort* DMAy;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+ assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
+
+ /* Determine the DMA to which belongs the stream */
+ if (DMAy_Streamx < DMA2_Stream0_MORT)
+ {
+ /* DMAy_Streamx belongs to DMA1_MORT */
+ DMAy = DMA1_MORT;
+ }
+ else
+ {
+ /* DMAy_Streamx belongs to DMA2_MORT */
+ DMAy = DMA2_MORT;
+ }
+
+ /* Check if LIFCR or HIFCR register is targeted */
+ if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
+ {
+ /* Set DMAy HIFCR register clear flag bits */
+ DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
+ }
+ else
+ {
+ /* Set DMAy LIFCR register clear flag bits */
+ DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Streamx interrupts.
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC_MORT_MORT: Transfer complete interrupt mask
+ * @arg DMA_IT_HT_MORT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE_MORT: Transfer error interrupt mask
+ * @arg DMA_IT_FE_MORT: FIFO error interrupt mask
+ * @param NewState: new state of the specified DMA interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DMA_ITConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+ assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* Check if the DMA_IT parameter contains a FIFO interrupt */
+ if ((DMA_IT & DMA_IT_FE_MORT) != 0)
+ {
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA FIFO interrupts */
+ DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE_MORT;
+ }
+ else
+ {
+ /* Disable the selected DMA FIFO interrupts */
+ DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE_MORT;
+ }
+ }
+
+ /* Check if the DMA_IT parameter contains a Transfer interrupt */
+ if (DMA_IT != DMA_IT_FE_MORT)
+ {
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA transfer interrupts */
+ DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
+ }
+ else
+ {
+ /* Disable the selected DMA transfer interrupts */
+ DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
+ }
+ }
+}
+
+/**
+ * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not.
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @param DMA_IT: specifies the DMA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_IT_TC_MORT_MORTIFx: Streamx transfer complete interrupt
+ * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt
+ * @arg DMA_IT_TEIFx: Streamx transfer error interrupt
+ * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
+ * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt
+ * Where x can be 0 to 7 to select the DMA Stream.
+ * @retval The new state of DMA_IT (SET or RESET).
+ */
+ITStatus DMA_GetITStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT)
+{
+ ITStatus bitstatus = RESET;
+ DMA_TypeDef_mort* DMAy;
+ uint32_t tmpreg = 0, enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+ assert_param(IS_DMA_GET_IT(DMA_IT));
+
+ /* Determine the DMA to which belongs the stream */
+ if (DMAy_Streamx < DMA2_Stream0_MORT)
+ {
+ /* DMAy_Streamx belongs to DMA1_MORT */
+ DMAy = DMA1_MORT;
+ }
+ else
+ {
+ /* DMAy_Streamx belongs to DMA2_MORT */
+ DMAy = DMA2_MORT;
+ }
+
+ /* Check if the interrupt enable bit is in the CR or FCR register */
+ if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET)
+ {
+ /* Get the interrupt enable position mask in CR register */
+ tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK);
+
+ /* Check the enable bit in CR register */
+ enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg);
+ }
+ else
+ {
+ /* Check the enable bit in FCR register */
+ enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE_MORT);
+ }
+
+ /* Check if the interrupt pending flag is in LISR or HISR */
+ if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
+ {
+ /* Get DMAy HISR register value */
+ tmpreg = DMAy->HISR ;
+ }
+ else
+ {
+ /* Get DMAy LISR register value */
+ tmpreg = DMAy->LISR ;
+ }
+
+ /* mask all reserved bits */
+ tmpreg &= (uint32_t)RESERVED_MASK;
+
+ /* Check the status of the specified DMA interrupt */
+ if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+ {
+ /* DMA_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMA_IT is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the DMA_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Streamx's interrupt pending bits.
+ * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+ * to 7 to select the DMA Stream.
+ * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC_MORT_MORTIFx: Streamx transfer complete interrupt
+ * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt
+ * @arg DMA_IT_TEIFx: Streamx transfer error interrupt
+ * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
+ * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt
+ * Where x can be 0 to 7 to select the DMA Stream.
+ * @retval None
+ */
+void DMA_ClearITPendingBit_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT)
+{
+ DMA_TypeDef_mort* DMAy;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+ assert_param(IS_DMA_CLEAR_IT(DMA_IT));
+
+ /* Determine the DMA to which belongs the stream */
+ if (DMAy_Streamx < DMA2_Stream0_MORT)
+ {
+ /* DMAy_Streamx belongs to DMA1_MORT */
+ DMAy = DMA1_MORT;
+ }
+ else
+ {
+ /* DMAy_Streamx belongs to DMA2_MORT */
+ DMAy = DMA2_MORT;
+ }
+
+ /* Check if LIFCR or HIFCR register is targeted */
+ if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
+ {
+ /* Set DMAy HIFCR register clear interrupt bits */
+ DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
+ }
+ else
+ {
+ /* Set DMAy LIFCR register clear interrupt bits */
+ DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/stm32f4xx_dma_mort.h Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,614 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_dma_mort.h
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file contains all the functions prototypes for the DMA firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_DMA_H_MORT
+#define __STM32F4xx_DMA_H_MORT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_mort2.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief DMA Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream.
+ This parameter can be a value of @ref DMA_channel */
+
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
+
+ uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx.
+ This memory is the default memory used when double buffer mode is
+ not enabled. */
+
+ uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_data_transfer_direction */
+
+ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream.
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize
+ or DMA_MemoryDataSize members depending in the transfer direction. */
+
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not.
+ This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_peripheral_data_size */
+
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_memory_data_size */
+
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx.
+ This parameter can be a value of @ref DMA_circular_normal_mode
+ @note The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Stream */
+
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx.
+ This parameter can be a value of @ref DMA_priority_level */
+
+ uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
+ This parameter can be a value of @ref DMA_fifo_direct_mode
+ @note The Direct mode (FIFO mode disabled) cannot be used if the
+ memory-to-memory data transfer is configured on the selected Stream */
+
+ uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level.
+ This parameter can be a value of @ref DMA_fifo_threshold_level */
+
+ uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
+ It specifies the amount of data to be transferred in a single non interruptable
+ transaction. This parameter can be a value of @ref DMA_memory_burst
+ @note The burst mode is possible only if the address Increment mode is enabled. */
+
+ uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
+ It specifies the amount of data to be transferred in a single non interruptable
+ transaction. This parameter can be a value of @ref DMA_peripheral_burst
+ @note The burst mode is possible only if the address Increment mode is enabled. */
+}DMA_InitTypeDef_mort;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+ * @{
+ */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
+ ((PERIPH) == DMA1_Stream1) || \
+ ((PERIPH) == DMA1_Stream2) || \
+ ((PERIPH) == DMA1_Stream3) || \
+ ((PERIPH) == DMA1_Stream4) || \
+ ((PERIPH) == DMA1_Stream5) || \
+ ((PERIPH) == DMA1_Stream6) || \
+ ((PERIPH) == DMA1_Stream7) || \
+ ((PERIPH) == DMA2_Stream0) || \
+ ((PERIPH) == DMA2_Stream1) || \
+ ((PERIPH) == DMA2_Stream2) || \
+ ((PERIPH) == DMA2_Stream3) || \
+ ((PERIPH) == DMA2_Stream4) || \
+ ((PERIPH) == DMA2_Stream5) || \
+ ((PERIPH) == DMA2_Stream6) || \
+ ((PERIPH) == DMA2_Stream7))
+
+#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1_MORT) || \
+ ((CONTROLLER) == DMA2_MORT))
+
+/** @defgroup DMA_channel
+ * @{
+ */
+#define DMA_Channel_0 ((uint32_t)0x00000000)
+#define DMA_Channel_1 ((uint32_t)0x02000000)
+#define DMA_Channel_2 ((uint32_t)0x04000000)
+#define DMA_Channel_3 ((uint32_t)0x06000000)
+#define DMA_Channel_4 ((uint32_t)0x08000000)
+#define DMA_Channel_5 ((uint32_t)0x0A000000)
+#define DMA_Channel_6 ((uint32_t)0x0C000000)
+#define DMA_Channel_7 ((uint32_t)0x0E000000)
+
+#define IS_DMA_CHANNEL_MORT(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
+ ((CHANNEL) == DMA_Channel_1) || \
+ ((CHANNEL) == DMA_Channel_2) || \
+ ((CHANNEL) == DMA_Channel_3) || \
+ ((CHANNEL) == DMA_Channel_4) || \
+ ((CHANNEL) == DMA_Channel_5) || \
+ ((CHANNEL) == DMA_Channel_6) || \
+ ((CHANNEL) == DMA_Channel_7))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_data_transfer_direction
+ * @{
+ */
+#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000)
+#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040)
+#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080)
+
+#define IS_DMA_DIRECTION_MORT(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
+ ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \
+ ((DIRECTION) == DMA_DIR_MemoryToMemory))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_data_buffer_size
+ * @{
+ */
+#define IS_DMA_BUFFER_SIZE_MORT(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_peripheral_incremented_mode
+ * @{
+ */
+#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200)
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
+
+#define IS_DMA_PERIPHERAL_INC_STATE_MORT(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
+ ((STATE) == DMA_PeripheralInc_Disable))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_memory_incremented_mode
+ * @{
+ */
+#define DMA_MemoryInc_Enable ((uint32_t)0x00000400)
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
+
+#define IS_DMA_MEMORY_INC_STATE_MORT(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
+ ((STATE) == DMA_MemoryInc_Disable))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_peripheral_data_size
+ * @{
+ */
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800)
+#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000)
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE_MORT(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+ ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_memory_data_size
+ * @{
+ */
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000)
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000)
+
+#define IS_DMA_MEMORY_DATA_SIZE_MORT(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+ ((SIZE) == DMA_MemoryDataSize_Word ))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_circular_normal_mode
+ * @{
+ */
+#define DMA_Mode_Normal ((uint32_t)0x00000000)
+#define DMA_Mode_Circular ((uint32_t)0x00000100)
+
+#define IS_DMA_MODE_MORT(MODE) (((MODE) == DMA_Mode_Normal ) || \
+ ((MODE) == DMA_Mode_Circular))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_priority_level
+ * @{
+ */
+#define DMA_Priority_Low ((uint32_t)0x00000000)
+#define DMA_Priority_Medium ((uint32_t)0x00010000)
+#define DMA_Priority_High ((uint32_t)0x00020000)
+#define DMA_Priority_VeryHigh ((uint32_t)0x00030000)
+
+#define IS_DMA_PRIORITY_MORT(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \
+ ((PRIORITY) == DMA_Priority_Medium) || \
+ ((PRIORITY) == DMA_Priority_High) || \
+ ((PRIORITY) == DMA_Priority_VeryHigh))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_fifo_direct_mode
+ * @{
+ */
+#define DMA_FIFOMode_Disable ((uint32_t)0x00000000)
+#define DMA_FIFOMode_Enable ((uint32_t)0x00000004)
+
+#define IS_DMA_FIFO_MODE_STATE_MORT(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
+ ((STATE) == DMA_FIFOMode_Enable))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_fifo_threshold_level
+ * @{
+ */
+#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000)
+#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001)
+#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002)
+#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003)
+
+#define IS_DMA_FIFO_THRESHOLD_MORT(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
+ ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \
+ ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
+ ((THRESHOLD) == DMA_FIFOThreshold_Full))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_memory_burst
+ * @{
+ */
+#define DMA_MemoryBurst_Single ((uint32_t)0x00000000)
+#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000)
+#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000)
+#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000)
+
+#define IS_DMA_MEMORY_BURST_MORT(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
+ ((BURST) == DMA_MemoryBurst_INC4) || \
+ ((BURST) == DMA_MemoryBurst_INC8) || \
+ ((BURST) == DMA_MemoryBurst_INC16))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_peripheral_burst
+ * @{
+ */
+#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000)
+#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000)
+#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000)
+#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000)
+
+#define IS_DMA_PERIPHERAL_BURST_MORT(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
+ ((BURST) == DMA_PeripheralBurst_INC4) || \
+ ((BURST) == DMA_PeripheralBurst_INC8) || \
+ ((BURST) == DMA_PeripheralBurst_INC16))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_fifo_status_level
+ * @{
+ */
+#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3)
+#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3)
+#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3)
+#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3)
+#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3)
+#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3)
+
+#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
+ ((STATUS) == DMA_FIFOStatus_HalfFull) || \
+ ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \
+ ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \
+ ((STATUS) == DMA_FIFOStatus_Full) || \
+ ((STATUS) == DMA_FIFOStatus_Empty))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flags_definition
+ * @{
+ */
+#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001)
+#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004)
+#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008)
+#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010)
+#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020)
+#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040)
+#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100)
+#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200)
+#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400)
+#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800)
+#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000)
+#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000)
+#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000)
+#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000)
+#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000)
+#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000)
+#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000)
+#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000)
+#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000)
+#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000)
+#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001)
+#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004)
+#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008)
+#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010)
+#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020)
+#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040)
+#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100)
+#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200)
+#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400)
+#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800)
+#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000)
+#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000)
+#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000)
+#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000)
+#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000)
+#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000)
+#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000)
+#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000)
+#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000)
+#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
+ (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
+ ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \
+ ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \
+ ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \
+ ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \
+ ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \
+ ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \
+ ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \
+ ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \
+ ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \
+ ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \
+ ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \
+ ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \
+ ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \
+ ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \
+ ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \
+ ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \
+ ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \
+ ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \
+ ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_interrupt_enable_definitions
+ * @{
+ */
+#define DMA_IT_TC_MORT ((uint32_t)0x00000010)
+#define DMA_IT_HT_MORT ((uint32_t)0x00000008)
+#define DMA_IT_TE_MORT ((uint32_t)0x00000004)
+#define DMA_IT_DME_MORT ((uint32_t)0x00000002)
+#define DMA_IT_FE_MORT ((uint32_t)0x00000080)
+
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_interrupts_definitions
+ * @{
+ */
+#define DMA_IT_FEIF0 ((uint32_t)0x90000001)
+#define DMA_IT_DMEIF0 ((uint32_t)0x10001004)
+#define DMA_IT_TEIF0 ((uint32_t)0x10002008)
+#define DMA_IT_HTIF0 ((uint32_t)0x10004010)
+#define DMA_IT_TC_MORTIF0 ((uint32_t)0x10008020)
+#define DMA_IT_FEIF1 ((uint32_t)0x90000040)
+#define DMA_IT_DMEIF1 ((uint32_t)0x10001100)
+#define DMA_IT_TEIF1 ((uint32_t)0x10002200)
+#define DMA_IT_HTIF1 ((uint32_t)0x10004400)
+#define DMA_IT_TC_MORTIF1 ((uint32_t)0x10008800)
+#define DMA_IT_FEIF2 ((uint32_t)0x90010000)
+#define DMA_IT_DMEIF2 ((uint32_t)0x10041000)
+#define DMA_IT_TEIF2 ((uint32_t)0x10082000)
+#define DMA_IT_HTIF2 ((uint32_t)0x10104000)
+#define DMA_IT_TC_MORTIF2 ((uint32_t)0x10208000)
+#define DMA_IT_FEIF3 ((uint32_t)0x90400000)
+#define DMA_IT_DMEIF3 ((uint32_t)0x11001000)
+#define DMA_IT_TEIF3 ((uint32_t)0x12002000)
+#define DMA_IT_HTIF3 ((uint32_t)0x14004000)
+#define DMA_IT_TC_MORTIF3 ((uint32_t)0x18008000)
+#define DMA_IT_FEIF4 ((uint32_t)0xA0000001)
+#define DMA_IT_DMEIF4 ((uint32_t)0x20001004)
+#define DMA_IT_TEIF4 ((uint32_t)0x20002008)
+#define DMA_IT_HTIF4 ((uint32_t)0x20004010)
+#define DMA_IT_TC_MORTIF4 ((uint32_t)0x20008020)
+#define DMA_IT_FEIF5 ((uint32_t)0xA0000040)
+#define DMA_IT_DMEIF5 ((uint32_t)0x20001100)
+#define DMA_IT_TEIF5 ((uint32_t)0x20002200)
+#define DMA_IT_HTIF5 ((uint32_t)0x20004400)
+#define DMA_IT_TC_MORTIF5 ((uint32_t)0x20008800)
+#define DMA_IT_FEIF6 ((uint32_t)0xA0010000)
+#define DMA_IT_DMEIF6 ((uint32_t)0x20041000)
+#define DMA_IT_TEIF6 ((uint32_t)0x20082000)
+#define DMA_IT_HTIF6 ((uint32_t)0x20104000)
+#define DMA_IT_TC_MORTIF6 ((uint32_t)0x20208000)
+#define DMA_IT_FEIF7 ((uint32_t)0xA0400000)
+#define DMA_IT_DMEIF7 ((uint32_t)0x21001000)
+#define DMA_IT_TEIF7 ((uint32_t)0x22002000)
+#define DMA_IT_HTIF7 ((uint32_t)0x24004000)
+#define DMA_IT_TC_MORTIF7 ((uint32_t)0x28008000)
+
+#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
+ (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
+ (((IT) & 0x40820082) == 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TC_MORT_MORT_MORTIF0) || ((IT) == DMA_IT_HTIF0) || \
+ ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
+ ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TC_MORT_MORT_MORT_MORT_MORTIF1) || \
+ ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \
+ ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \
+ ((IT) == DMA_IT_TC_MORT_MORT_MORTIF2) || ((IT) == DMA_IT_HTIF2) || \
+ ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
+ ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TC_MORT_MORT_MORT_MORT_MORTIF3) || \
+ ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \
+ ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \
+ ((IT) == DMA_IT_TC_MORT_MORT_MORTIF4) || ((IT) == DMA_IT_HTIF4) || \
+ ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
+ ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TC_MORT_MORT_MORT_MORT_MORTIF5) || \
+ ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \
+ ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \
+ ((IT) == DMA_IT_TC_MORT_MORT_MORTIF6) || ((IT) == DMA_IT_HTIF6) || \
+ ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
+ ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TC_MORT_MORT_MORT_MORT_MORTIF7) || \
+ ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \
+ ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_peripheral_increment_offset
+ * @{
+ */
+#define DMA_PINCOS_Psize ((uint32_t)0x00000000)
+#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000)
+
+#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
+ ((SIZE) == DMA_PINCOS_WordAligned))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_flow_controller_definitions
+ * @{
+ */
+#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000)
+#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020)
+
+#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
+ ((CTRL) == DMA_FlowCtrl_Peripheral))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_memory_targets_definitions
+ * @{
+ */
+#define DMA_Memory_0 ((uint32_t)0x00000000)
+#define DMA_Memory_1 ((uint32_t)0x00080000)
+
+#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Function used to set the DMA configuration to the default reset state *****/
+void DMA_DeInit_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx);
+
+/* Initialization and Configuration functions *********************************/
+void DMA_Init_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, DMA_InitTypeDef_mort* DMA_InitStruct);
+void DMA_StructInit_mort(DMA_InitTypeDef_mort* DMA_InitStruct);
+void DMA_Cmd_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, FunctionalState NewState);
+
+/* Optional Configuration functions *******************************************/
+void DMA_PeriphIncOffsetSizeConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_Pincos);
+void DMA_FlowControllerConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FlowCtrl);
+
+/* Data Counter functions *****************************************************/
+void DMA_SetCurrDataCounter_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint16_t Counter);
+uint16_t DMA_GetCurrDataCounter_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx);
+
+/* Double Buffer mode functions ***********************************************/
+void DMA_DoubleBufferModeConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t Memory1BaseAddr,
+ uint32_t DMA_CurrentMemory);
+void DMA_DoubleBufferModeCmd_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, FunctionalState NewState);
+void DMA_MemoryTargetConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t MemoryBaseAddr,
+ uint32_t DMA_MemoryTarget);
+uint32_t DMA_GetCurrentMemoryTarget_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx);
+
+/* Interrupts and flags management functions **********************************/
+FunctionalState DMA_GetCmdStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx);
+uint32_t DMA_GetFIFOStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx);
+FlagStatus DMA_GetFlagStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FLAG);
+void DMA_ClearFlag_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FLAG);
+void DMA_ITConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
+ITStatus DMA_GetITStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT);
+void DMA_ClearITPendingBit_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_DMA_H_MORT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/stm32f4xx_exti_mort.c Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,318 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_exti.c
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the EXTI_MORT peripheral:
+ * + Initialization and Configuration
+ * + Interrupts and flags management
+ *
+@verbatim
+
+ ===============================================================================
+ ##### EXTI_MORT features #####
+ ===============================================================================
+
+ [..] External interrupt/event lines are mapped as following:
+ (#) All available GPIO pins are connected to the 16 external
+ interrupt/event lines from EXTI0 to EXTI15.
+ (#) EXTI_MORT line 16 is connected to the PVD Output
+ (#) EXTI_MORT line 17 is connected to the RTC Alarm event
+ (#) EXTI_MORT line 18 is connected to the USB OTG FS Wakeup from suspend event
+ (#) EXTI_MORT line 19 is connected to the Ethernet Wakeup event
+ (#) EXTI_MORT line 20 is connected to the USB OTG HS (configured in FS) Wakeup event
+ (#) EXTI_MORT line 21 is connected to the RTC Tamper and Time Stamp events
+ (#) EXTI_MORT line 22 is connected to the RTC Wakeup event
+ (#) EXTI_MORT line 23 is connected to the LPTIM Wakeup event
+
+ ##### How to use this driver #####
+ ===============================================================================
+
+ [..] In order to use an I/O pin as an external interrupt source, follow steps
+ below:
+ (#) Configure the I/O in input mode using GPIO_Init()
+ (#) Select the input source pin for the EXTI_MORT line using SYSCFG_EXTILineConfig()
+ (#) Select the mode(interrupt, event) and configure the trigger
+ selection (Rising, falling or both) using EXTI_Init_mort()
+ (#) Configure NVIC IRQ channel mapped to the EXTI_MORT line using NVIC_Init()
+
+ [..]
+ (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
+ registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+
+@endverbatim
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_exti_mort.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup EXTI_MORT
+ * @brief EXTI_MORT driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define EXTI_LINENONE_MORT ((uint32_t)0x00000) /* No interrupt selected */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup EXTI_Private_Functions
+ * @{
+ */
+
+/** @defgroup EXTI_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the EXTI_MORT peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void EXTI_DeInit_mort(void)
+{
+ EXTI_MORT->IMR = 0x00000000;
+ EXTI_MORT->EMR = 0x00000000;
+ EXTI_MORT->RTSR = 0x00000000;
+ EXTI_MORT->FTSR = 0x00000000;
+ EXTI_MORT->PR = 0x007FFFFF;
+}
+
+/**
+ * @brief Initializes the EXTI_MORT peripheral according to the specified
+ * parameters in the EXTI_InitStruct.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef_mort structure
+ * that contains the configuration information for the EXTI_MORT peripheral.
+ * @retval None
+ */
+void EXTI_Init_mort(EXTI_InitTypeDef_mort* EXTI_InitStruct)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_MODE_MORT(EXTI_InitStruct->EXTI_Mode));
+ assert_param(IS_EXTI_TRIGGER_MORT(EXTI_InitStruct->EXTI_Trigger));
+ assert_param(IS_EXTI_LINE_MORT(EXTI_InitStruct->EXTI_Line));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+ tmp = (uint32_t)EXTI_BASE_MORT;
+
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+ {
+ /* Clear EXTI_MORT line configuration */
+ EXTI_MORT->IMR &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI_MORT->EMR &= ~EXTI_InitStruct->EXTI_Line;
+
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+
+ /* Clear Rising Falling edge configuration */
+ EXTI_MORT->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI_MORT->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+
+ /* Select the trigger for the selected external interrupts */
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+ {
+ /* Rising Falling edge */
+ EXTI_MORT->RTSR |= EXTI_InitStruct->EXTI_Line;
+ EXTI_MORT->FTSR |= EXTI_InitStruct->EXTI_Line;
+ }
+ else
+ {
+ tmp = (uint32_t)EXTI_BASE_MORT;
+ tmp += EXTI_InitStruct->EXTI_Trigger;
+
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+ }
+ }
+ else
+ {
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ /* Disable the selected external lines */
+ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
+ }
+}
+
+/**
+ * @brief Fills each EXTI_InitStruct member with its reset value.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef_mort structure which will
+ * be initialized.
+ * @retval None
+ */
+void EXTI_StructInit_mort(EXTI_InitTypeDef_mort* EXTI_InitStruct)
+{
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE_MORT;
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+ * @brief Generates a Software interrupt on selected EXTI_MORT line.
+ * @param EXTI_Line: specifies the EXTI_MORT line on which the software interrupt
+ * will be generated.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..22)
+ * @retval None
+ */
+void EXTI_GenerateSWInterrupt_mort(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE_MORT(EXTI_Line));
+
+ EXTI_MORT->SWIER |= EXTI_Line;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Group2 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Checks whether the specified EXTI_MORT line flag is set or not.
+ * @param EXTI_Line: specifies the EXTI_MORT line flag to check.
+ * This parameter can be EXTI_Linex where x can be(0..22)
+ * @retval The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetFlagStatus_mort(uint32_t EXTI_Line)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE_MORT(EXTI_Line));
+
+ if ((EXTI_MORT->PR & EXTI_Line) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI_MORT's line pending flags.
+ * @param EXTI_Line: specifies the EXTI_MORT lines flags to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..22)
+ * @retval None
+ */
+void EXTI_ClearFlag_mort(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE_MORT(EXTI_Line));
+
+ EXTI_MORT->PR = EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI_MORT line is asserted or not.
+ * @param EXTI_Line: specifies the EXTI_MORT line to check.
+ * This parameter can be EXTI_Linex where x can be(0..22)
+ * @retval The new state of EXTI_Line (SET or RESET).
+ */
+ITStatus EXTI_GetITStatus_mort(uint32_t EXTI_Line)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE_MORT(EXTI_Line));
+
+ if ((EXTI_MORT->PR & EXTI_Line) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+
+}
+
+/**
+ * @brief Clears the EXTI_MORT's line pending bits.
+ * @param EXTI_Line: specifies the EXTI_MORT lines to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..22)
+ * @retval None
+ */
+void EXTI_ClearITPendingBit_mort(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE_MORT(EXTI_Line));
+
+ EXTI_MORT->PR = EXTI_Line;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/stm32f4xx_exti_mort.h Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,191 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_exti_mort.h
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file contains all the functions prototypes for the EXTI_MORT firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_EXTI_MORT_H
+#define __STM32F4xx_EXTI_MORT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_mort2.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI_MORT
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief EXTI_MORT mode enumeration
+ */
+
+typedef enum
+{
+ EXTI_Mode_Interrupt = 0x00,
+ EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef_mort;
+
+#define IS_EXTI_MODE_MORT(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+ * @brief EXTI_MORT Trigger enumeration
+ */
+
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x08,
+ EXTI_Trigger_Falling = 0x0C,
+ EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef_mort;
+
+#define IS_EXTI_TRIGGER_MORT(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+ ((TRIGGER) == EXTI_Trigger_Falling) || \
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+ * @brief EXTI_MORT Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EXTI_Line; /*!< Specifies the EXTI_MORT lines to be enabled or disabled.
+ This parameter can be any combination value of @ref EXTI_Lines */
+
+ EXTIMode_TypeDef_mort EXTI_Mode; /*!< Specifies the mode for the EXTI_MORT lines.
+ This parameter can be a value of @ref EXTIMode_TypeDef_mort */
+
+ EXTITrigger_TypeDef_mort EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI_MORT lines.
+ This parameter can be a value of @ref EXTITrigger_TypeDef_mort */
+
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI_MORT lines.
+ This parameter can be set either to ENABLE or DISABLE */
+}EXTI_InitTypeDef_mort;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Constants
+ * @{
+ */
+
+/** @defgroup EXTI_Lines
+ * @{
+ */
+
+#define EXTI_Line0_MORT ((uint32_t)0x00001) /*!< External interrupt line 0 */
+#define EXTI_Line1_MORT ((uint32_t)0x00002) /*!< External interrupt line 1 */
+#define EXTI_Line2_MORT ((uint32_t)0x00004) /*!< External interrupt line 2 */
+#define EXTI_Line3_MORT ((uint32_t)0x00008) /*!< External interrupt line 3 */
+#define EXTI_Line4_MORT ((uint32_t)0x00010) /*!< External interrupt line 4 */
+#define EXTI_Line5_MORT ((uint32_t)0x00020) /*!< External interrupt line 5 */
+#define EXTI_Line6_MORT ((uint32_t)0x00040) /*!< External interrupt line 6 */
+#define EXTI_Line7_MORT ((uint32_t)0x00080) /*!< External interrupt line 7 */
+#define EXTI_Line8_MORT ((uint32_t)0x00100) /*!< External interrupt line 8 */
+#define EXTI_Line9_MORT ((uint32_t)0x00200) /*!< External interrupt line 9 */
+#define EXTI_Line10_MORT ((uint32_t)0x00400) /*!< External interrupt line 10 */
+#define EXTI_Line11_MORT ((uint32_t)0x00800) /*!< External interrupt line 11 */
+#define EXTI_Line12_MORT ((uint32_t)0x01000) /*!< External interrupt line 12 */
+#define EXTI_Line13_MORT ((uint32_t)0x02000) /*!< External interrupt line 13 */
+#define EXTI_Line14_MORT ((uint32_t)0x04000) /*!< External interrupt line 14 */
+#define EXTI_Line15_MORT ((uint32_t)0x08000) /*!< External interrupt line 15 */
+#define EXTI_Line16_MORT ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17_MORT ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18_MORT ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
+#define EXTI_Line19_MORT ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+#define EXTI_Line20_MORT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
+#define EXTI_Line21_MORT ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define EXTI_Line22_MORT ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+#define EXTI_Line23_MORT ((uint32_t)0x00800000) /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */
+
+
+#define IS_EXTI_LINE_MORT(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
+
+#define IS_GET_EXTI_LINE_MORT(LINE) (((LINE) == EXTI_Line0_MORT) || ((LINE) == EXTI_Line1_MORT) || \
+ ((LINE) == EXTI_Line2_MORT) || ((LINE) == EXTI_Line3_MORT) || \
+ ((LINE) == EXTI_Line4_MORT) || ((LINE) == EXTI_Line5_MORT) || \
+ ((LINE) == EXTI_Line6_MORT) || ((LINE) == EXTI_Line7_MORT) || \
+ ((LINE) == EXTI_Line8_MORT) || ((LINE) == EXTI_Line9_MORT) || \
+ ((LINE) == EXTI_Line10_MORT) || ((LINE) == EXTI_Line11_MORT) || \
+ ((LINE) == EXTI_Line12_MORT) || ((LINE) == EXTI_Line13_MORT) || \
+ ((LINE) == EXTI_Line14_MORT) || ((LINE) == EXTI_Line15_MORT) || \
+ ((LINE) == EXTI_Line16_MORT) || ((LINE) == EXTI_Line17_MORT) || \
+ ((LINE) == EXTI_Line18_MORT) || ((LINE) == EXTI_Line19_MORT) || \
+ ((LINE) == EXTI_Line20_MORT) || ((LINE) == EXTI_Line21_MORT) ||\
+ ((LINE) == EXTI_Line22_MORT) || ((LINE) == EXTI_Line23_MORT))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Function used to set the EXTI_MORT configuration to the default reset state *****/
+void EXTI_DeInit_mort(void);
+
+/* Initialization and Configuration functions *********************************/
+void EXTI_Init_mort(EXTI_InitTypeDef_mort* EXTI_InitStruct);
+void EXTI_StructInit_mort(EXTI_InitTypeDef_mort* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt_mort(uint32_t EXTI_Line);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus EXTI_GetFlagStatus_mort(uint32_t EXTI_Line);
+void EXTI_ClearFlag_mort(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus_mort(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit_mort(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_EXTI_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/stm32f4xx_gpio_mort.c Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,616 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_gpio_mort.c
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the GPIO peripheral:
+ * + Initialization and Configuration
+ * + GPIO Read and Write
+ * + GPIO Alternate functions configuration
+ *
+@verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (#) Enable the GPIO AHB clock using the following function
+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+
+ (#) Configure the GPIO pin(s) using GPIO_Init()
+ Four possible configuration are available for each pin:
+ (++) Input: Floating, Pull-up, Pull-down.
+ (++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
+ Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed
+ is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz.
+ (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open
+ Drain (Pull-up, Pull-down or no Pull).
+ (++) Analog: required mode when a pin is to be used as ADC channel or DAC
+ output.
+
+ (#) Peripherals alternate function:
+ (++) For ADC and DAC, configure the desired pin in analog mode using
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
+ (+++) For other peripherals (TIM, USART...):
+ (+++) Connect the pin to the desired peripherals' Alternate
+ Function (AF) using GPIO_PinAFConfig() function
+ (+++) Configure the desired pin in alternate function mode using
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+ (+++) Select the type, pull-up/pull-down and output speed via
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members
+ (+++) Call GPIO_Init() function
+
+ (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
+
+ (#) To set/reset the level of a pin configured in output mode use
+ GPIO_SetBits()/GPIO_ResetBits()
+
+ (#) During and just after reset, the alternate functions are not
+ active and the GPIO pins are configured in input floating mode (except JTAG
+ pins).
+
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+ (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+ priority over the GPIO function.
+
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+ general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
+ The HSE has priority over the GPIO function.
+
+@endverbatim
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_gpio_mort.h"
+#include "stm32f4xx_rcc_mort.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup GPIO_Private_Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Group1 Initialization and Configuration
+ * @brief Initialization and Configuration
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief De-initializes the GPIOx peripheral registers to their default reset values.
+ * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+ * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+ * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+ * @retval None
+ */
+void GPIO_DeInit_mort(GPIO_TypeDef_mort* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ if (GPIOx == GPIOA_MORT)
+ {
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
+ }
+ else if (GPIOx == GPIOB_MORT)
+ {
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
+ }
+ else if (GPIOx == GPIOC_MORT)
+ {
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
+ }
+ else if (GPIOx == GPIOD_MORT)
+ {
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
+ }
+ else if (GPIOx == GPIOE_MORT)
+ {
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
+ }
+ else if (GPIOx == GPIOF_MORT)
+ {
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
+ }
+ else if (GPIOx == GPIOG_MORT)
+ {
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
+ }
+ else if(GPIOx == GPIOH_MORT)
+ {
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
+ }
+
+ /*else if (GPIOx == GPIOI)
+ {
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
+ }
+ else if (GPIOx == GPIOJ)
+ {
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE);
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, DISABLE);
+ }
+ else
+ {
+ if (GPIOx == GPIOK)
+ {
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, ENABLE);
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, DISABLE);
+ }
+ }*/
+}
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+ * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+ * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void GPIO_Init_mort(GPIO_TypeDef_mort* GPIOx, GPIO_InitTypeDef_mort* GPIO_InitStruct)
+{
+ uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN_MORT(GPIO_InitStruct->GPIO_Pin));
+ assert_param(IS_GPIO_MODE_MORT(GPIO_InitStruct->GPIO_Mode));
+ assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
+
+ /* ------------------------- Configure the port pins ---------------- */
+ /*-- GPIO Mode Configuration --*/
+ for (pinpos = 0x00; pinpos < 0x10; pinpos++)
+ {
+ pos = ((uint32_t)0x01) << pinpos;
+ /* Get the port pins position */
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+ if (currentpin == pos)
+ {
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0_MORT << (pinpos * 2));
+ GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
+
+ if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
+ {
+ /* Check Speed mode parameters */
+ assert_param(IS_GPIO_SPEED_MORT_MORT(GPIO_InitStruct->GPIO_Speed));
+
+ /* Speed mode configuration */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0_MORT << (pinpos * 2));
+ GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
+
+ /* Check Output mode parameters */
+ assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
+
+ /* Output mode configuration*/
+ GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0_MORT) << ((uint16_t)pinpos)) ;
+ GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
+ }
+
+ /* Pull-up Pull down resistor configuration*/
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0_MORT << ((uint16_t)pinpos * 2));
+ GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
+ }
+ }
+}
+
+/**
+ * @brief Fills each GPIO_InitStruct member with its default value.
+ * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void GPIO_StructInit_mort(GPIO_InitTypeDef_mort* GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+ GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
+ GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
+}
+
+/**
+ * @brief Locks GPIO Pins configuration registers.
+ * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+ * @note The configuration of the locked GPIO pins can no longer be modified
+ * until the next reset.
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+ * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+ * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+ * @param GPIO_Pin: specifies the port bit to be locked.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_PinLockConfig_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_Pin)
+{
+ __IO uint32_t tmp = 0x00010000;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN_MORT(GPIO_Pin));
+
+ tmp |= GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKK bit */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Group2 GPIO Read and Write
+ * @brief GPIO Read and Write
+ *
+@verbatim
+ ===============================================================================
+ ##### GPIO Read and Write #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+ * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+ * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @retval The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO input data port.
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+ * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+ * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+ * @retval GPIO input data port value.
+ */
+uint16_t GPIO_ReadInputData_mort(GPIO_TypeDef_mort* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+ * @brief Reads the specified output data port bit.
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+ * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+ * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @retval The output port pin value.
+ */
+uint8_t GPIO_ReadOutputDataBit_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO output data port.
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+ * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+ * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+ * @retval GPIO output data port value.
+ */
+uint16_t GPIO_ReadOutputData_mort(GPIO_TypeDef_mort* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+ * @brief Sets the selected data port bits.
+ * @note This functions uses GPIOx_BSRR register to allow atomic read/modify
+ * accesses. In this way, there is no risk of an IRQ occurring between
+ * the read and the modify access.
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+ * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+ * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_SetBits_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN_MORT(GPIO_Pin));
+
+ GPIOx->BSRRL = GPIO_Pin;
+}
+
+/**
+ * @brief Clears the selected data port bits.
+ * @note This functions uses GPIOx_BSRR register to allow atomic read/modify
+ * accesses. In this way, there is no risk of an IRQ occurring between
+ * the read and the modify access.
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+ * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+ * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_ResetBits_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN_MORT(GPIO_Pin));
+
+ GPIOx->BSRRH = GPIO_Pin;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+ * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+ * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).
+ * @param BitVal: specifies the value to be written to the selected bit.
+ * This parameter can be one of the BitAction enum values:
+ * @arg Bit_RESET: to clear the port pin
+ * @arg Bit_SET: to set the port pin
+ * @retval None
+ */
+void GPIO_WriteBit_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+ if (BitVal != Bit_RESET)
+ {
+ GPIOx->BSRRL = GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BSRRH = GPIO_Pin ;
+ }
+}
+
+/**
+ * @brief Writes data to the specified GPIO data port.
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+ * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+ * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+ * @param PortVal: specifies the value to be written to the port output data register.
+ * @retval None
+ */
+void GPIO_Write_mort(GPIO_TypeDef_mort* GPIOx, uint16_t PortVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ GPIOx->ODR = PortVal;
+}
+
+/**
+ * @brief Toggles the specified GPIO pins..
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+ * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+ * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+ * @param GPIO_Pin: Specifies the pins to be toggled.
+ * @retval None
+ */
+void GPIO_ToggleBits_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ GPIOx->ODR ^= GPIO_Pin;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
+ * @brief GPIO Alternate functions configuration function
+ *
+@verbatim
+ ===============================================================================
+ ##### GPIO Alternate functions configuration function #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Changes the mapping of the specified pin.
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
+ * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
+ * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+ * @param GPIO_PinSource: specifies the pin for the Alternate function.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @param GPIO_AFSelection: selects the pin to used as Alternate function.
+ * This parameter can be one of the following values:
+ * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset)
+ * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset)
+ * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset)
+ * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset)
+ * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
+ * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
+ * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
+ * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
+ * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
+ * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
+ * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
+ * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
+ * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
+ * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
+ * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
+ * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
+ * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
+ * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
+ * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
+ * @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5
+ * @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5
+ * @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5
+ * @arg GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices.
+ * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
+ * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
+ * @arg GPIO_AF_USART1: Connect USART1 pins to AF7
+ * @arg GPIO_AF_USART2: Connect USART2 pins to AF7
+ * @arg GPIO_AF_USART3: Connect USART3 pins to AF7
+ * @arg GPIO_AF_UART4: Connect UART4 pins to AF8
+ * @arg GPIO_AF_UART5: Connect UART5 pins to AF8
+ * @arg GPIO_AF_USART6: Connect USART6 pins to AF8
+ * @arg GPIO_AF_UART7: Connect UART7 pins to AF8
+ * @arg GPIO_AF_UART8: Connect UART8 pins to AF8
+ * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
+ * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
+ * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
+ * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
+ * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
+ * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
+ * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
+ * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
+ * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
+ * @arg GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices.
+ * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
+ * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
+ * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
+ * @arg GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices.
+ * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
+ * @retval None
+ */
+void GPIO_PinAFConfig_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
+{
+ uint32_t temp = 0x00;
+ uint32_t temp_2 = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+ assert_param(IS_GPIO_AF(GPIO_AF));
+
+ temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
+ GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
+ temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
+ GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/stm32f4xx_gpio_mort.h Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,597 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_gpio.h
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file contains all the functions prototypes for the GPIO firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_GPIO_H_MORT
+#define __STM32F4xx_GPIO_H_MORT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_mort2.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+ ((PERIPH) == GPIOB) || \
+ ((PERIPH) == GPIOC) || \
+ ((PERIPH) == GPIOD) || \
+ ((PERIPH) == GPIOE) || \
+ ((PERIPH) == GPIOF) || \
+ ((PERIPH) == GPIOG) || \
+ ((PERIPH) == GPIOH) || \
+ ((PERIPH) == GPIOI) || \
+ ((PERIPH) == GPIOJ) || \
+ ((PERIPH) == GPIOK))
+
+/**
+ * @brief GPIO Configuration Mode enumeration
+ */
+typedef enum
+{
+ GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
+ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
+ GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
+ GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */
+}GPIOMode_TypeDef_mort;
+#define IS_GPIO_MODE_MORT(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \
+ ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+
+/**
+ * @brief GPIO Output type enumeration
+ */
+typedef enum
+{
+ GPIO_OType_PP = 0x00,
+ GPIO_OType_OD = 0x01
+}GPIOOType_TypeDef_mort;
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
+
+
+/**
+ * @brief GPIO Output Maximum frequency enumeration
+ */
+typedef enum
+{
+ GPIO_Low_Speed = 0x00, /*!< Low speed */
+ GPIO_Medium_Speed = 0x01, /*!< Medium speed */
+ GPIO_Fast_Speed = 0x02, /*!< Fast speed */
+ GPIO_High_Speed = 0x03 /*!< High speed */
+}GPIOSpeed_TypeDef_mort;
+
+/* Add legacy definition */
+#define GPIO_Speed_2MHz GPIO_Low_Speed
+#define GPIO_Speed_25MHz GPIO_Medium_Speed
+#define GPIO_Speed_50MHz GPIO_Fast_Speed
+#define GPIO_Speed_100MHz GPIO_High_Speed
+
+#define IS_GPIO_SPEED_MORT(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \
+ ((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed))
+
+/**
+ * @brief GPIO Configuration PullUp PullDown enumeration
+ */
+typedef enum
+{
+ GPIO_PuPd_NOPULL = 0x00,
+ GPIO_PuPd_UP = 0x01,
+ GPIO_PuPd_DOWN = 0x02
+}GPIOPuPd_TypeDef_mort;
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+ ((PUPD) == GPIO_PuPd_DOWN))
+
+/**
+ * @brief GPIO Bit SET and Bit RESET enumeration
+ */
+typedef enum
+{
+ Bit_RESET = 0,
+ Bit_SET
+}BitAction;
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ GPIOMode_TypeDef_mort GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIOMode_TypeDef */
+
+ GPIOSpeed_TypeDef_mort GPIO_Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+ GPIOOType_TypeDef_mort GPIO_OType; /*!< Specifies the operating output type for the selected pins.
+ This parameter can be a value of @ref GPIOOType_TypeDef */
+
+ GPIOPuPd_TypeDef_mort GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+ This parameter can be a value of @ref GPIOPuPd_TypeDef */
+}GPIO_InitTypeDef_mort;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define
+ * @{
+ */
+#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
+#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
+#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
+#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
+#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
+#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
+#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
+#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
+#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
+#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
+#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
+#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
+#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
+#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
+#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
+#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
+
+#define GPIO_PIN_MASK_MORT ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
+#define IS_GPIO_PIN_MORT(PIN) (((PIN) & GPIO_PIN_MASK_MORT ) != (uint32_t)0x00)
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+ ((PIN) == GPIO_Pin_1) || \
+ ((PIN) == GPIO_Pin_2) || \
+ ((PIN) == GPIO_Pin_3) || \
+ ((PIN) == GPIO_Pin_4) || \
+ ((PIN) == GPIO_Pin_5) || \
+ ((PIN) == GPIO_Pin_6) || \
+ ((PIN) == GPIO_Pin_7) || \
+ ((PIN) == GPIO_Pin_8) || \
+ ((PIN) == GPIO_Pin_9) || \
+ ((PIN) == GPIO_Pin_10) || \
+ ((PIN) == GPIO_Pin_11) || \
+ ((PIN) == GPIO_Pin_12) || \
+ ((PIN) == GPIO_Pin_13) || \
+ ((PIN) == GPIO_Pin_14) || \
+ ((PIN) == GPIO_Pin_15))
+/**
+ * @}
+ */
+
+
+/** @defgroup GPIO_Pin_sources
+ * @{
+ */
+#define GPIO_PinSource0 ((uint8_t)0x00)
+#define GPIO_PinSource1 ((uint8_t)0x01)
+#define GPIO_PinSource2 ((uint8_t)0x02)
+#define GPIO_PinSource3 ((uint8_t)0x03)
+#define GPIO_PinSource4 ((uint8_t)0x04)
+#define GPIO_PinSource5 ((uint8_t)0x05)
+#define GPIO_PinSource6 ((uint8_t)0x06)
+#define GPIO_PinSource7 ((uint8_t)0x07)
+#define GPIO_PinSource8 ((uint8_t)0x08)
+#define GPIO_PinSource9 ((uint8_t)0x09)
+#define GPIO_PinSource10 ((uint8_t)0x0A)
+#define GPIO_PinSource11 ((uint8_t)0x0B)
+#define GPIO_PinSource12 ((uint8_t)0x0C)
+#define GPIO_PinSource13 ((uint8_t)0x0D)
+#define GPIO_PinSource14 ((uint8_t)0x0E)
+#define GPIO_PinSource15 ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_MORT_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+ ((PINSOURCE) == GPIO_PinSource1) || \
+ ((PINSOURCE) == GPIO_PinSource2) || \
+ ((PINSOURCE) == GPIO_PinSource3) || \
+ ((PINSOURCE) == GPIO_PinSource4) || \
+ ((PINSOURCE) == GPIO_PinSource5) || \
+ ((PINSOURCE) == GPIO_PinSource6) || \
+ ((PINSOURCE) == GPIO_PinSource7) || \
+ ((PINSOURCE) == GPIO_PinSource8) || \
+ ((PINSOURCE) == GPIO_PinSource9) || \
+ ((PINSOURCE) == GPIO_PinSource10) || \
+ ((PINSOURCE) == GPIO_PinSource11) || \
+ ((PINSOURCE) == GPIO_PinSource12) || \
+ ((PINSOURCE) == GPIO_PinSource13) || \
+ ((PINSOURCE) == GPIO_PinSource14) || \
+ ((PINSOURCE) == GPIO_PinSource15))
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Alternat_function_selection_define
+ * @{
+ */
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#if defined(STM32F446xx)
+#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */
+#endif /* STM32F446xx */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+#define GPIO_AF_LPTIM ((uint8_t)0x01) /* LPTIM Alternate Function mapping */
+#endif /* STM32F410xx || STM32F413_423xx */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+#if defined(STM32F446xx)
+#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */
+#endif /* STM32F446xx */
+#if defined(STM32F413_423xx)
+#define GPIO_AF3_DFSDM2 ((uint8_t)0x03) /* DFSDM2 Alternate Function mapping */
+#endif /* STM32F413_423xx */
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+#if defined(STM32F446xx)
+#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
+#endif /* STM32F446xx */
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+#define GPIO_AF_FMPI2C ((uint8_t)0x04) /* FMPI2C Alternate Function mapping */
+#endif /* STM32F410xx || STM32F446xx */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE and STM32F413_423xx Devices) */
+#define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */
+#define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
+#define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping (Only for STM32F410xx Devices) */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
+#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */
+#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
+#define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
+#define GPIO_AF_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping (only for STM32F412xG and STM32F413_423xx Devices) */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
+#endif /* STM32F412xG || STM32F413_423xx */
+#if defined(STM32F413_423xx)
+#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */
+#endif /* STM32F413_423xx */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3ext Alternate Function mapping */
+#if defined(STM32F413_423xx)
+#define GPIO_AF7_DFSDM2 ((uint8_t)0x07) /* DFSDM2 Alternate Function mapping */
+#define GPIO_AF7_SAI1 ((uint8_t)0x07) /* SAI1 Alternate Function mapping */
+#endif /* STM32F413_423xx */
+
+/**
+ * @brief AF 7 selection Legacy
+ */
+#define GPIO_AF_I2S3ext GPIO_AF7_SPI3
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+#define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
+#define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */
+#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM Alternate Function mapping */
+#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */
+#endif /* STM32F412xG || STM32F413_423xx */
+#if defined(STM32F446xx)
+#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
+#define GPIO_AF_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
+#endif /* STM32F446xx */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F410xx/STM32F411xE/STM32F412xG/STM32F413_423xx Devices) */
+#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE/STM32F412xG and STM32F413_423xx Devices) */
+#if defined(STM32F446xx)
+#define GPIO_AF9_SAI2 ((uint8_t)0x09) /* SAI2 Alternate Function mapping */
+#endif /* STM32F446xx */
+#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QuadSPI Alternate Function mapping */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+#define GPIO_AF9_FMPI2C ((uint8_t)0x09) /* FMPI2C Alternate Function mapping (Only for STM32F410xx Devices) */
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
+#if defined(STM32F446xx)
+#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
+#endif /* STM32F446xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QuadSPI Alternate Function mapping */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define GPIO_AF10_FMC ((uint8_t)0xA) /* FMC Alternate Function mapping */
+#define GPIO_AF10_DFSDM1 ((uint8_t)0xA) /* DFSDM Alternate Function mapping */
+#endif /* STM32F412xG || STM32F413_423xx */
+#if defined(STM32F413_423xx)
+#define GPIO_AF10_DFSDM2 ((uint8_t)0x0A) /* DFSDM2 Alternate Function mapping */
+#define GPIO_AF10_SAI1 ((uint8_t)0x0A) /* SAI1 Alternate Function mapping */
+#endif /* STM32F413_423xx */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+#if defined(STM32F413_423xx)
+#define GPIO_AF11_UART4 ((uint8_t)0x0B) /* UART4 Alternate Function mapping */
+#define GPIO_AF11_UART5 ((uint8_t)0x0B) /* UART5 Alternate Function mapping */
+#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */
+#define GPIO_AF11_UART10 ((uint8_t)0x0B) /* UART10 Alternate Function mapping */
+#define GPIO_AF11_CAN3 ((uint8_t)0x0B) /* CAN3 Alternate Function mapping */
+#endif /* STM32F413_423xx */
+
+/**
+ * @brief AF 12 selection
+ */
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+#define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
+
+#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+#if defined(STM32F469_479xx)
+#define GPIO_AF_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
+#endif /* STM32F469_479xx */
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
+#if defined(STM32F413_423xx)
+#define GPIO_AF14_RNG ((uint8_t)0x0E) /* RNG Alternate Function mapping */
+#endif /* STM32F413_423xx */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#if defined(STM32F40_41xxx)
+#define IS_GPIO_AF_MORT(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
+ ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
+ ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
+ ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
+ ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
+ ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
+ ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
+ ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
+ ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
+ ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
+ ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
+ ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
+ ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
+ ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
+ ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
+ ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
+ ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
+ ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC))
+#endif /* STM32F40_41xxx */
+
+#if defined(STM32F401xx)
+#define IS_GPIO_AF_MORT(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
+ ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
+ ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
+ ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
+ ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
+ ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
+ ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
+ ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
+ ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
+ ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
+ ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
+ ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_USART6) || \
+ ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
+ ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4))
+#endif /* STM32F401xx */
+
+#if defined(STM32F411xE)
+#define IS_GPIO_AF_MORT(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14))
+#endif /* STM32F411xE */
+
+#if defined(STM32F410xx)
+#define IS_GPIO_AF_MORT(AF) (((AF) < 10) || ((AF) == 15))
+#endif /* STM32F410xx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
+#define IS_GPIO_AF_MORT(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
+ ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
+ ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
+ ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
+ ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
+ ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
+ ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
+ ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
+ ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
+ ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
+ ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
+ ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
+ ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
+ ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
+ ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
+ ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
+ ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
+ ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \
+ ((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \
+ ((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \
+ ((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \
+ ((AF) == GPIO_AF_LTDC))
+#endif /* STM32F427_437xx || STM32F429_439xx */
+
+#if defined(STM32F412xG)
+#define IS_GPIO_AF_MORT(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
+#endif /* STM32F412xG */
+
+#if defined(STM32F413_423xx)
+#define IS_GPIO_AF_MORT(AF) (((AF) < 16) && ((AF) != 13))
+#endif /* STM32F413_423xx */
+
+#if defined(STM32F446xx)
+#define IS_GPIO_AF_MORT(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
+#endif /* STM32F446xx */
+
+#if defined(STM32F469_479xx)
+#define IS_GPIO_AF_MORT(AF) ((AF) < 16)
+#endif /* STM32F469_479xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Legacy
+ * @{
+ */
+
+#define GPIO_Mode_AIN GPIO_Mode_AN
+
+#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS
+#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS
+#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Function used to set the GPIO configuration to the default reset state ****/
+void GPIO_DeInit_mort(GPIO_TypeDef_mort* GPIOx);
+
+/* Initialization and Configuration functions *********************************/
+void GPIO_Init_mort(GPIO_TypeDef_mort* GPIOx, GPIO_InitTypeDef_mort* GPIO_InitStruct);
+void GPIO_StructInit_mort(GPIO_InitTypeDef_mort* GPIO_InitStruct);
+void GPIO_PinLockConfig_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Read and Write functions **********************************************/
+uint8_t GPIO_ReadInputDataBit_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData_mort(GPIO_TypeDef_mort* GPIOx);
+uint8_t GPIO_ReadOutputDataBit_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData_mort(GPIO_TypeDef_mort* GPIOx);
+void GPIO_SetBits_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write_mort(GPIO_TypeDef_mort* GPIOx, uint16_t PortVal);
+void GPIO_ToggleBits_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Alternate functions configuration function ****************************/
+void GPIO_PinAFConfig_mort(GPIO_TypeDef_mort* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_GPIO_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/stm32f4xx_mort2.h Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,5895 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 09-November-2016
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F4xx devices.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The device used in the target application
+ * - To use or not the peripherals drivers in application code(i.e.
+ * code will be based on direct access to peripherals registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_STDPERIPH_DRIVER"
+ * - To change few application-specific parameters such as the HSE
+ * crystal frequency
+ * - Data structures and the address mapping for all peripherals
+ * - Peripherals registers declarations and bits definition
+ * - Macros to access peripherals registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H_MORT2_
+#define __STM32F4xx_H_MORT2_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \
+ !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F413_423xx) && !defined(STM32F446xx_MORT) && !defined(STM32F469_479xx)
+ /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG,
+ STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE,
+ STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+
+ /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II,
+ STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */
+
+ /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI,
+ STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI,
+ STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI,
+ STM32F439IG and STM32F439II Devices */
+
+ /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC,
+ STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE and STM32F401VE Devices */
+
+ /* #define STM32F410xx */ /*!< STM32F410Tx, STM32F410Cx and STM32F410Rx */
+
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+
+ /* #define STM32F412xG */ /*!< STM32F412CEU, STM32F412CGU, STM32F412ZET, STM32F412ZGT, STM32F412ZEJ, STM32F412ZGJ,
+ STM32F412VET, STM32F412VGT, STM32F412VEH, STM32F412VGH, STM32F412RET, STM32F412RGT,
+ STM32F412REY and STM32F412RGY Devices */
+
+ /* #define STM32F413_423xx */ /*!< STM32F413CGU, STM32F413CHU, STM32F413MGY, STM32F413MHY, STM32F413RGT, STM32F413VGT,
+ STM32F413ZGT, STM32F413RHT, STM32F413VHT, STM32F413ZHT, STM32F413VGH, STM32F413ZGJ,
+ STM32F413VHH, STM32F413ZHJ, STM32F423CHU, STM32F423RHT, STM32F423VHT, STM32F423ZHT,
+ STM32F423VHH and STM32F423ZHJ devices */
+
+ #define STM32F446xx_MORT /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC
+ and STM32F446ZE Devices */
+
+ /* #define STM32F469_479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG,
+ STM32F479NG, STM32F479AE, STM32F479IE, STM32F479BE, STM32F479NE Devices */
+
+#endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F413_423xx && STM32F446xx_MORT && STM32F469_479xx */
+
+/* Old STM32F40XX definition, maintained for legacy purpose */
+#ifdef STM32F40XX
+ #define STM32F40_41xxx
+#endif /* STM32F40XX */
+
+/* Old STM32F427X definition, maintained for legacy purpose */
+#ifdef STM32F427X
+ #define STM32F427_437xx
+#endif /* STM32F427X */
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+
+#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \
+ !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F413_423xx) && !defined(STM32F446xx_MORT) && !defined(STM32F469_479xx)
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F413_23xx && STM32F446xx_MORT && STM32F469_479xx */
+
+#if !defined (USE_STDPERIPH_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_STDPERIPH_DRIVER */
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || \
+ defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
+ #if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+ #endif /* HSE_VALUE */
+#elif defined (STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT)
+ #if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+ #endif /* HSE_VALUE */
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief STM32F4XX Standard Peripherals Library version number V1.8.0
+ */
+#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */
+#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
+ |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
+ |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
+ |(__STM32F4XX_STDPERIPH_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV_MORT 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT_MORT 1 /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS_MORT 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig_MORT 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT_MORT 1 /*!< FPU present */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum IRQn_MORT
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn_MORT = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn_MORT = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn_MORT = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn_MORT = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn_MORT = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn_MORT = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn_MORT = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn_MORT = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn_MORT = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn_MORT = 1, /*!< PVD through EXTI_MORT Line detection Interrupt */
+ TAMP_STAMP_IRQn_MORT = 2, /*!< Tamper and TimeStamp interrupts through the EXTI_MORT line */
+ RTC_WKUP_IRQn_MORT = 3, /*!< RTC_MORT Wakeup interrupt through the EXTI_MORT line */
+ FLASH_IRQn_MORT = 4, /*!< FLASH_MORT global Interrupt */
+ RCC_IRQn_MORT = 5, /*!< RCC_MORT global Interrupt */
+ EXTI0_IRQn_MORT = 6, /*!< EXTI_MORT Line0 Interrupt */
+ EXTI1_IRQn_MORT = 7, /*!< EXTI_MORT Line1 Interrupt */
+ EXTI2_IRQn_MORT = 8, /*!< EXTI_MORT Line2 Interrupt */
+ EXTI3_IRQn_MORT = 9, /*!< EXTI_MORT Line3 Interrupt */
+ EXTI4_IRQn_MORT = 10, /*!< EXTI_MORT Line4 Interrupt */
+ DMA1_Stream0_IRQn_MORT = 11, /*!< DMA1_MORT Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn_MORT = 12, /*!< DMA1_MORT Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn_MORT = 13, /*!< DMA1_MORT Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn_MORT = 14, /*!< DMA1_MORT Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn_MORT = 15, /*!< DMA1_MORT Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn_MORT = 16, /*!< DMA1_MORT Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn_MORT = 17, /*!< DMA1_MORT Stream 6 global Interrupt */
+ ADC_IRQn_MORT = 18, /*!< ADC1_MORT, ADC2_MORT and ADC3_MORT global Interrupts */
+
+#if defined(STM32F40_41xxx)
+ */
+#endif /* STM32F40_41xxx */
+
+#if defined(STM32F427_437xx)
+ */
+#endif /* STM32F427_437xx */
+
+#if defined(STM32F429_439xx)
+ */
+#endif /* STM32F429_439xx */
+
+#if defined(STM32F410xx)
+ */
+#endif /* STM32F410xx */
+
+#if defined(STM32F401xx) || defined(STM32F411xE)
+ */
+#if defined(STM32F401xx)
+ */
+#endif /* STM32F411xE */
+#if defined(STM32F411xE)
+ */
+#endif /* STM32F411xE */
+#endif /* STM32F401xx || STM32F411xE */
+
+#if defined(STM32F469_479xx)
+ */
+#endif /* STM32F469_479xx */
+
+#if defined(STM32F446xx_MORT)
+ CAN1_TX_IRQn_MORT = 19, /*!< CAN1_MORT TX Interrupt */
+ CAN1_RX0_IRQn_MORT = 20, /*!< CAN1_MORT RX0 Interrupt */
+ CAN1_RX1_IRQn_MORT = 21, /*!< CAN1_MORT RX1 Interrupt */
+ CAN1_SCE_IRQn_MORT = 22, /*!< CAN1_MORT SCE Interrupt */
+ EXTI9_5_IRQn_MORT = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn_MORT = 24, /*!< TIM1_MORT Break interrupt and TIM9_MORT global interrupt */
+ TIM1_UP_TIM10_IRQn_MORT = 25, /*!< TIM1_MORT Update Interrupt and TIM10_MORT global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn_MORT = 26, /*!< TIM1_MORT Trigger and Commutation Interrupt and TIM11_MORT global interrupt */
+ TIM1_CC_IRQn_MORT = 27, /*!< TIM1_MORT Capture Compare Interrupt */
+ TIM2_IRQn_MORT = 28, /*!< TIM2_MORT global Interrupt */
+ TIM3_IRQn_MORT = 29, /*!< TIM3_MORT global Interrupt */
+ TIM4_IRQn_MORT = 30, /*!< TIM4_MORT global Interrupt */
+ I2C1_EV_IRQn_MORT = 31, /*!< I2C1_MORT Event Interrupt */
+ I2C1_ER_IRQn_MORT = 32, /*!< I2C1_MORT Error Interrupt */
+ I2C2_EV_IRQn_MORT = 33, /*!< I2C2_MORT Event Interrupt */
+ I2C2_ER_IRQn_MORT = 34, /*!< I2C2_MORT Error Interrupt */
+ SPI1_IRQn_MORT = 35, /*!< SPI1_MORT global Interrupt */
+ SPI2_IRQn_MORT = 36, /*!< SPI2_MORT global Interrupt */
+ USART1_IRQn_MORT = 37, /*!< USART1_MORT global Interrupt */
+ USART2_IRQn_MORT = 38, /*!< USART2_MORT global Interrupt */
+ USART3_IRQn_MORT = 39, /*!< USART3_MORT global Interrupt */
+ EXTI15_10_IRQn_MORT = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn_MORT = 41, /*!< RTC_MORT Alarm (A and B) through EXTI_MORT Line Interrupt */
+ OTG_FS_WKUP_IRQn_MORT = 42, /*!< USB OTG FS Wakeup through EXTI_MORT line interrupt */
+ TIM8_BRK_IRQn_MORT = 43, /*!< TIM8_MORT Break Interrupt */
+ TIM8_BRK_TIM12_IRQn_MORT = 43, /*!< TIM8_MORT Break Interrupt and TIM12_MORT global interrupt */
+ TIM8_UP_TIM13_IRQn_MORT = 44, /*!< TIM8_MORT Update Interrupt and TIM13_MORT global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn_MORT = 45, /*!< TIM8_MORT Trigger and Commutation Interrupt and TIM14_MORT global interrupt */
+ DMA1_Stream7_IRQn_MORT = 47, /*!< DMA1_MORT Stream7 Interrupt */
+ FMC_IRQn_MORT = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn_MORT = 49, /*!< SDIO_MORT global Interrupt */
+ TIM5_IRQn_MORT = 50, /*!< TIM5_MORT global Interrupt */
+ SPI3_IRQn_MORT = 51, /*!< SPI3_MORT global Interrupt */
+ UART4_IRQn_MORT = 52, /*!< UART4_MORT global Interrupt */
+ UART5_IRQn_MORT = 53, /*!< UART5_MORT global Interrupt */
+ TIM6_DAC_IRQn_MORT = 54, /*!< TIM6_MORT global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn_MORT = 55, /*!< TIM7_MORT global interrupt */
+ DMA2_Stream0_IRQn_MORT = 56, /*!< DMA2_MORT Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn_MORT = 57, /*!< DMA2_MORT Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn_MORT = 58, /*!< DMA2_MORT Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn_MORT = 59, /*!< DMA2_MORT Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn_MORT = 60, /*!< DMA2_MORT Stream 4 global Interrupt */
+ CAN2_TX_IRQn_MORT = 63, /*!< CAN2_MORT TX Interrupt */
+ CAN2_RX0_IRQn_MORT = 64, /*!< CAN2_MORT RX0 Interrupt */
+ CAN2_RX1_IRQn_MORT = 65, /*!< CAN2_MORT RX1 Interrupt */
+ CAN2_SCE_IRQn_MORT = 66, /*!< CAN2_MORT SCE Interrupt */
+ OTG_FS_IRQn_MORT = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn_MORT = 68, /*!< DMA2_MORT Stream 5 global interrupt */
+ DMA2_Stream6_IRQn_MORT = 69, /*!< DMA2_MORT Stream 6 global interrupt */
+ DMA2_Stream7_IRQn_MORT = 70, /*!< DMA2_MORT Stream 7 global interrupt */
+ USART6_IRQn_MORT = 71, /*!< USART6_MORT global interrupt */
+ I2C3_EV_IRQn_MORT = 72, /*!< I2C3_MORT event interrupt */
+ I2C3_ER_IRQn_MORT = 73, /*!< I2C3_MORT error interrupt */
+ OTG_HS_EP1_OUT_IRQn_MORT = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn_MORT = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn_MORT = 76, /*!< USB OTG HS Wakeup through EXTI_MORT interrupt */
+ OTG_HS_IRQn_MORT = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn_MORT = 78, /*!< DCMI_MORT global interrupt */
+ FPU_IRQn_MORT = 81, /*!< FPU global interrupt */
+ SPI4_IRQn_MORT = 84, /*!< SPI4_MORT global Interrupt */
+ SAI1_IRQn_MORT = 87, /*!< SAI1_MORT global Interrupt */
+ SAI2_IRQn_MORT = 91, /*!< SAI2_MORT global Interrupt */
+ QUADSPI_IRQn_MORT = 92, /*!< QUADSPI_MORT global Interrupt */
+ CEC_IRQn_MORT = 93, /*!< QUADSPI_MORT global Interrupt */
+ SPDIF_RX_IRQn_MORT = 94, /*!< QUADSPI_MORT global Interrupt */
+ FMPI2C1_EV_IRQn_MORT = 95, /*!< FMPI2C Event Interrupt */
+ FMPI2C1_ER_IRQn_MORT = 96 /*!< FMPCI2C Error Interrupt */
+#endif /* STM32F446xx_MORT */
+
+#if defined(STM32F412xG)
+ */
+#endif /* STM32F412xG */
+
+#if defined(STM32F413_423xx)
+ */
+ */
+#endif /* STM32F413_423xx */
+} IRQn_Type_MORT;
+
+/**
+ * @}
+ */
+#include "stm32f4xx.h"
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+ * @{
+ */
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+//typedef int32_t_mort s32;
+//typedef int16_t_mort s16;
+//typedef int8_t_mort s8;
+
+//typedef const int32_t_mort sc32; /*!< Read Only */
+//typedef const int16_t_mort sc16; /*!< Read Only */
+//typedef const int8_t_mort sc8; /*!< Read Only */
+
+//typedef __IO int32_t_mort vs32;
+//typedef __IO int16_t_mort vs16;
+//typedef __IO int8_t_mort vs8;
+
+//typedef __I int32_t_mort vsc32; /*!< Read Only */
+//typedef __I int16_t_mort vsc16; /*!< Read Only */
+//typedef __I int8_t_mort vsc8; /*!< Read Only */
+
+//typedef uint32_t_mort u32;
+//typedef uint16_t_mort u16;
+//typedef uint8_t_mort u8;
+
+//typedef const uint32_t_mort uc32; /*!< Read Only */
+//typedef const uint16_t_mort uc16; /*!< Read Only */
+//typedef const uint8_t_mort uc8; /*!< Read Only */
+
+//typedef __IO uint32_t_mort vu32;
+//typedef __IO uint16_t_mort vu16;
+//typedef __IO uint8_t_mort vu8;
+
+//typedef __I uint32_t_mort vuc32; /*!< Read Only */
+//typedef __I uint16_t_mort vuc16; /*!< Read Only */
+//typedef __I uint8_t_mort vuc8; /*!< Read Only */
+
+typedef enum {RESET_MORT = 0, SET_MORT = !RESET_MORT} FlagStatus_MORT, ITStatus_MORT;
+
+typedef enum {DISABLE_MORT = 0, ENABLE_MORT = !DISABLE_MORT} FunctionalState_MORT;
+#define IS_FUNCTIONAL_STATE_MORT(STATE) (((STATE) == DISABLE_MORT) || ((STATE) == ENABLE_MORT))
+
+typedef enum {ERROR_MORT = 0, SUCCESS_MORT = !ERROR} ErrorStatus_MORT;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC_MORT status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC_MORT control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC_MORT control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC_MORT sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC_MORT sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC_MORT injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC_MORT injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC_MORT injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC_MORT injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC_MORT watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC_MORT watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC_MORT regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC_MORT regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC_MORT regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC_MORT injected sequence register, Address offset: 0x38 */
+ __IO uint32_t JDR1; /*!< ADC_MORT injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC_MORT injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC_MORT injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC_MORT injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC_MORT regular data register, Address offset: 0x4C */
+} ADC_TypeDef_mort;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC_MORT Common status register, Address offset: ADC1_MORT base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC_MORT common control register, Address offset: ADC1_MORT base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC_MORT common regular data register for dual
+ AND triple modes, Address offset: ADC1_MORT base address + 0x308 */
+} ADC_Common_TypeDef_mort;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef_mort;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef_mort;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef_mort;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef_mort sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef_mort sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef_mort sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef_mort;
+
+#if defined(STM32F446xx_MORT)
+/**
+ * @brief Consumer Electronics Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< CEC_MORT control register, Address offset:0x00 */
+ __IO uint32_t CFGR; /*!< CEC_MORT configuration register, Address offset:0x04 */
+ __IO uint32_t TXDR; /*!< CEC_MORT Tx data register , Address offset:0x08 */
+ __IO uint32_t RXDR; /*!< CEC_MORT Rx Data Register, Address offset:0x0C */
+ __IO uint32_t ISR; /*!< CEC_MORT Interrupt and Status Register, Address offset:0x10 */
+ __IO uint32_t IER; /*!< CEC_MORT interrupt enable register, Address offset:0x14 */
+}CEC_TypeDef_mort;
+#endif /* STM32F446xx_MORT */
+
+/**
+ * @brief CRC_MORT calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC_MORT Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC_MORT Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC_MORT Control register, Address offset: 0x08 */
+} CRC_TypeDef_mort;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC_MORT control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC_MORT software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC_MORT channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC_MORT channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC_MORT channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC_MORT channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC_MORT channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC_MORT channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC_MORT 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC_MORT 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC_MORT 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC_MORT channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC_MORT channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC_MORT status register, Address offset: 0x34 */
+} DAC_TypeDef_mort;
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+/**
+ * @brief DFSDM module registers
+ */
+typedef struct
+{
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
+} DFSDM_Filter_TypeDef_mort;
+
+/**
+ * @brief DFSDM channel configuration registers
+ */
+typedef struct
+{
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
+ short circuit detector register, Address offset: 0x08 */
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
+} DFSDM_Channel_TypeDef_mort;
+
+/* Legacy Defines */
+#define DFSDM_TypeDef DFSDM_Filter_TypeDef_mort
+#endif /* STM32F412xG || STM32F413_423xx */
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef_mort;
+
+/**
+ * @brief DCMI_MORT
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI_MORT control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI_MORT status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI_MORT raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI_MORT interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI_MORT masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI_MORT interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI_MORT embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI_MORT embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI_MORT crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI_MORT crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI_MORT data register, Address offset: 0x28 */
+} DCMI_TypeDef_mort;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef_mort;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef_mort;
+
+/**
+ * @brief DMA2D_MORT Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D_MORT Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D_MORT Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D_MORT Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D_MORT Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D_MORT Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D_MORT Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D_MORT Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D_MORT Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D_MORT Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D_MORT Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D_MORT Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D_MORT Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D_MORT Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D_MORT Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D_MORT Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D_MORT Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D_MORT Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D_MORT Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D_MORT Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D_MORT AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D_MORT Foreground CLUT, Address offset:400-7FF */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D_MORT Background CLUT, Address offset:800-BFF */
+} DMA2D_TypeDef_mort;
+
+#if defined(STM32F469_479xx)
+/**
+ * @brief DSI_MORT Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t VR; /*!< DSI_MORT Host Version Register, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< DSI_MORT Host Control Register, Address offset: 0x04 */
+ __IO uint32_t CCR; /*!< DSI_MORT HOST Clock Control Register, Address offset: 0x08 */
+ __IO uint32_t LVCIDR; /*!< DSI_MORT Host LTDC_MORT VCID Register, Address offset: 0x0C */
+ __IO uint32_t LCOLCR; /*!< DSI_MORT Host LTDC_MORT Color Coding Register, Address offset: 0x10 */
+ __IO uint32_t LPCR; /*!< DSI_MORT Host LTDC_MORT Polarity Configuration Register, Address offset: 0x14 */
+ __IO uint32_t LPMCR; /*!< DSI_MORT Host Low-Power Mode Configuration Register, Address offset: 0x18 */
+ uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
+ __IO uint32_t PCR; /*!< DSI_MORT Host Protocol Configuration Register, Address offset: 0x2C */
+ __IO uint32_t GVCIDR; /*!< DSI_MORT Host Generic VCID Register, Address offset: 0x30 */
+ __IO uint32_t MCR; /*!< DSI_MORT Host Mode Configuration Register, Address offset: 0x34 */
+ __IO uint32_t VMCR; /*!< DSI_MORT Host Video Mode Configuration Register, Address offset: 0x38 */
+ __IO uint32_t VPCR; /*!< DSI_MORT Host Video Packet Configuration Register, Address offset: 0x3C */
+ __IO uint32_t VCCR; /*!< DSI_MORT Host Video Chunks Configuration Register, Address offset: 0x40 */
+ __IO uint32_t VNPCR; /*!< DSI_MORT Host Video Null Packet Configuration Register, Address offset: 0x44 */
+ __IO uint32_t VHSACR; /*!< DSI_MORT Host Video HSA Configuration Register, Address offset: 0x48 */
+ __IO uint32_t VHBPCR; /*!< DSI_MORT Host Video HBP Configuration Register, Address offset: 0x4C */
+ __IO uint32_t VLCR; /*!< DSI_MORT Host Video Line Configuration Register, Address offset: 0x50 */
+ __IO uint32_t VVSACR; /*!< DSI_MORT Host Video VSA Configuration Register, Address offset: 0x54 */
+ __IO uint32_t VVBPCR; /*!< DSI_MORT Host Video VBP Configuration Register, Address offset: 0x58 */
+ __IO uint32_t VVFPCR; /*!< DSI_MORT Host Video VFP Configuration Register, Address offset: 0x5C */
+ __IO uint32_t VVACR; /*!< DSI_MORT Host Video VA Configuration Register, Address offset: 0x60 */
+ __IO uint32_t LCCR; /*!< DSI_MORT Host LTDC_MORT Command Configuration Register, Address offset: 0x64 */
+ __IO uint32_t CMCR; /*!< DSI_MORT Host Command Mode Configuration Register, Address offset: 0x68 */
+ __IO uint32_t GHCR; /*!< DSI_MORT Host Generic Header Configuration Register, Address offset: 0x6C */
+ __IO uint32_t GPDR; /*!< DSI_MORT Host Generic Payload Data Register, Address offset: 0x70 */
+ __IO uint32_t GPSR; /*!< DSI_MORT Host Generic Packet Status Register, Address offset: 0x74 */
+ __IO uint32_t TCCR[6]; /*!< DSI_MORT Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
+ __IO uint32_t TDCR; /*!< DSI_MORT Host 3D Configuration Register, Address offset: 0x90 */
+ __IO uint32_t CLCR; /*!< DSI_MORT Host Clock Lane Configuration Register, Address offset: 0x94 */
+ __IO uint32_t CLTCR; /*!< DSI_MORT Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
+ __IO uint32_t DLTCR; /*!< DSI_MORT Host Data Lane Timer Configuration Register, Address offset: 0x9C */
+ __IO uint32_t PCTLR; /*!< DSI_MORT Host PHY Control Register, Address offset: 0xA0 */
+ __IO uint32_t PCONFR; /*!< DSI_MORT Host PHY Configuration Register, Address offset: 0xA4 */
+ __IO uint32_t PUCR; /*!< DSI_MORT Host PHY ULPS Control Register, Address offset: 0xA8 */
+ __IO uint32_t PTTCR; /*!< DSI_MORT Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
+ __IO uint32_t PSR; /*!< DSI_MORT Host PHY Status Register, Address offset: 0xB0 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
+ __IO uint32_t ISR[2]; /*!< DSI_MORT Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
+ __IO uint32_t IER[2]; /*!< DSI_MORT Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
+ __IO uint32_t FIR[2]; /*!< DSI_MORT Host Force Interrupt Register, Address offset: 0xD8-0xDF */
+ uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
+ __IO uint32_t VSCR; /*!< DSI_MORT Host Video Shadow Control Register, Address offset: 0x100 */
+ uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
+ __IO uint32_t LCVCIDR; /*!< DSI_MORT Host LTDC_MORT Current VCID Register, Address offset: 0x10C */
+ __IO uint32_t LCCCR; /*!< DSI_MORT Host LTDC_MORT Current Color Coding Register, Address offset: 0x110 */
+ uint32_t RESERVED5; /*!< Reserved, 0x114 */
+ __IO uint32_t LPMCCR; /*!< DSI_MORT Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
+ uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
+ __IO uint32_t VMCCR; /*!< DSI_MORT Host Video Mode Current Configuration Register, Address offset: 0x138 */
+ __IO uint32_t VPCCR; /*!< DSI_MORT Host Video Packet Current Configuration Register, Address offset: 0x13C */
+ __IO uint32_t VCCCR; /*!< DSI_MORT Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
+ __IO uint32_t VNPCCR; /*!< DSI_MORT Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
+ __IO uint32_t VHSACCR; /*!< DSI_MORT Host Video HSA Current Configuration Register, Address offset: 0x148 */
+ __IO uint32_t VHBPCCR; /*!< DSI_MORT Host Video HBP Current Configuration Register, Address offset: 0x14C */
+ __IO uint32_t VLCCR; /*!< DSI_MORT Host Video Line Current Configuration Register, Address offset: 0x150 */
+ __IO uint32_t VVSACCR; /*!< DSI_MORT Host Video VSA Current Configuration Register, Address offset: 0x154 */
+ __IO uint32_t VVBPCCR; /*!< DSI_MORT Host Video VBP Current Configuration Register, Address offset: 0x158 */
+ __IO uint32_t VVFPCCR; /*!< DSI_MORT Host Video VFP Current Configuration Register, Address offset: 0x15C */
+ __IO uint32_t VVACCR; /*!< DSI_MORT Host Video VA Current Configuration Register, Address offset: 0x160 */
+ uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
+ __IO uint32_t TDCCR; /*!< DSI_MORT Host 3D Current Configuration Register, Address offset: 0x190 */
+ uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
+ __IO uint32_t WCFGR; /*!< DSI_MORT Wrapper Configuration Register, Address offset: 0x400 */
+ __IO uint32_t WCR; /*!< DSI_MORT Wrapper Control Register, Address offset: 0x404 */
+ __IO uint32_t WIER; /*!< DSI_MORT Wrapper Interrupt Enable Register, Address offset: 0x408 */
+ __IO uint32_t WISR; /*!< DSI_MORT Wrapper Interrupt and Status Register, Address offset: 0x40C */
+ __IO uint32_t WIFCR; /*!< DSI_MORT Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
+ uint32_t RESERVED9; /*!< Reserved, 0x414 */
+ __IO uint32_t WPCR[5]; /*!< DSI_MORT Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
+ uint32_t RESERVED10; /*!< Reserved, 0x42C */
+ __IO uint32_t WRPCR; /*!< DSI_MORT Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
+} DSI_TypeDef_mort;
+#endif /* STM32F469_479xx */
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef_mort;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI_MORT Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI_MORT Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI_MORT Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI_MORT Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI_MORT Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI_MORT Pending register, Address offset: 0x14 */
+} EXTI_TypeDef_mort;
+
+/**
+ * @brief FLASH_MORT Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH_MORT access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH_MORT key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH_MORT option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH_MORT status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH_MORT control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH_MORT option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH_MORT option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef_mort;
+
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef_mort;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef_mort;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND FLASH_MORT control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND FLASH_MORT FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND FLASH_MORT Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND FLASH_MORT Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND FLASH_MORT ECC result registers 2, Address offset: 0x74 */
+} FSMC_Bank2_TypeDef_mort;
+
+/**
+ * @brief Flexible Static Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR3; /*!< NAND FLASH_MORT control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND FLASH_MORT FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND FLASH_MORT Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND FLASH_MORT Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED0; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND FLASH_MORT ECC result registers 3, Address offset: 0x94 */
+} FSMC_Bank3_TypeDef_mort;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FSMC_Bank4_TypeDef_mort;
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef_mort;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef_mort;
+
+/**
+ * @brief Flexible Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND FLASH_MORT control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND FLASH_MORT FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND FLASH_MORT Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND FLASH_MORT Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND FLASH_MORT ECC result registers 2, Address offset: 0x74 */
+} FMC_Bank2_TypeDef_mort;
+
+/**
+ * @brief Flexible Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR3; /*!< NAND FLASH_MORT control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND FLASH_MORT FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND FLASH_MORT Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND FLASH_MORT Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED0; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND FLASH_MORT ECC result registers 3, Address offset: 0x94 */
+} FMC_Bank3_TypeDef_mort;
+
+/**
+ * @brief Flexible Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FMC_Bank4_TypeDef_mort;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef_mort;
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
+ __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef_mort;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG_MORT memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG_MORT peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG_MORT external interrupt configuration registers, Address offset: 0x08-0x14 */
+#if defined (STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t CFGR2; /*!< Reserved, 0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG_MORT Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG_MORT Configuration register, Address offset: 0x2C */
+#else /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx_MORT || STM32F469_479xx */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG_MORT Compensation cell control register, Address offset: 0x20 */
+#endif /* STM32F410xx || defined(STM32F412xG) || defined(STM32F413_423xx) */
+#if defined(STM32F413_423xx)
+ __IO uint32_t MCHDLYCR; /*!< SYSCFG_MORT multi-channel delay register, Address offset: 0x30 */
+#endif /* STM32F413_423xx */
+} SYSCFG_TypeDef_mort;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+ __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */
+ __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */
+ __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+ uint16_t RESERVED9; /*!< Reserved, 0x26 */
+} I2C_TypeDef_mort;
+
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT)
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+}FMPI2C_TypeDef_mort;
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG_MORT Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG_MORT Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG_MORT Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG_MORT Status register, Address offset: 0x0C */
+} IWDG_TypeDef_mort;
+
+/**
+ * @brief LCD-TFT Display Controller
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
+ __IO uint32_t SSCR; /*!< LTDC_MORT Synchronization Size Configuration Register, Address offset: 0x08 */
+ __IO uint32_t BPCR; /*!< LTDC_MORT Back Porch Configuration Register, Address offset: 0x0C */
+ __IO uint32_t AWCR; /*!< LTDC_MORT Active Width Configuration Register, Address offset: 0x10 */
+ __IO uint32_t TWCR; /*!< LTDC_MORT Total Width Configuration Register, Address offset: 0x14 */
+ __IO uint32_t GCR; /*!< LTDC_MORT Global Control Register, Address offset: 0x18 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
+ __IO uint32_t SRCR; /*!< LTDC_MORT Shadow Reload Configuration Register, Address offset: 0x24 */
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
+ __IO uint32_t BCCR; /*!< LTDC_MORT Background Color Configuration Register, Address offset: 0x2C */
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
+ __IO uint32_t IER; /*!< LTDC_MORT Interrupt Enable Register, Address offset: 0x34 */
+ __IO uint32_t ISR; /*!< LTDC_MORT Interrupt Status Register, Address offset: 0x38 */
+ __IO uint32_t ICR; /*!< LTDC_MORT Interrupt Clear Register, Address offset: 0x3C */
+ __IO uint32_t LIPCR; /*!< LTDC_MORT Line Interrupt Position Configuration Register, Address offset: 0x40 */
+ __IO uint32_t CPSR; /*!< LTDC_MORT Current Position Status Register, Address offset: 0x44 */
+ __IO uint32_t CDSR; /*!< LTDC_MORT Current Display Status Register, Address offset: 0x48 */
+} LTDC_TypeDef_mort;
+
+/**
+ * @brief LCD-TFT Display layer x Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< LTDC_MORT Layerx Control Register Address offset: 0x84 */
+ __IO uint32_t WHPCR; /*!< LTDC_MORT Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+ __IO uint32_t WVPCR; /*!< LTDC_MORT Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
+ __IO uint32_t CKCR; /*!< LTDC_MORT Layerx Color Keying Configuration Register Address offset: 0x90 */
+ __IO uint32_t PFCR; /*!< LTDC_MORT Layerx Pixel Format Configuration Register Address offset: 0x94 */
+ __IO uint32_t CACR; /*!< LTDC_MORT Layerx Constant Alpha Configuration Register Address offset: 0x98 */
+ __IO uint32_t DCCR; /*!< LTDC_MORT Layerx Default Color Configuration Register Address offset: 0x9C */
+ __IO uint32_t BFCR; /*!< LTDC_MORT Layerx Blending Factors Configuration Register Address offset: 0xA0 */
+ uint32_t RESERVED0[2]; /*!< Reserved */
+ __IO uint32_t CFBAR; /*!< LTDC_MORT Layerx Color Frame Buffer Address Register Address offset: 0xAC */
+ __IO uint32_t CFBLR; /*!< LTDC_MORT Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
+ __IO uint32_t CFBLNR; /*!< LTDC_MORT Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
+ uint32_t RESERVED1[3]; /*!< Reserved */
+ __IO uint32_t CLUTWR; /*!< LTDC_MORT Layerx CLUT Write Register Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef_mort;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR_MORT power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR_MORT power control/status register, Address offset: 0x04 */
+} PWR_TypeDef_mort;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC_MORT clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC_MORT PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC_MORT clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC_MORT clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC_MORT AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC_MORT AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC_MORT AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC_MORT APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC_MORT APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC_MORT AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC_MORT AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC_MORT AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC_MORT APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC_MORT APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC_MORT AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC_MORT AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC_MORT AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC_MORT APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC_MORT APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC_MORT Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC_MORT clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC_MORT spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC_MORT PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC_MORT PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC_MORT Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC_MORT Clocks Gated Enable Register, Address offset: 0x90 */ /* Only for STM32F412xG, STM32413_423xx and STM32F446xx_MORT devices */
+ __IO uint32_t DCKCFGR2; /*!< RCC_MORT Dedicated Clocks configuration register 2, Address offset: 0x94 */ /* Only for STM32F410xx, STM32F412xG, STM32413_423xx and STM32F446xx_MORT devices */
+
+} RCC_TypeDef_mort;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC_MORT time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC_MORT date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC_MORT control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC_MORT initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC_MORT prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC_MORT wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC_MORT calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC_MORT alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC_MORT alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC_MORT write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC_MORT sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC_MORT shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC_MORT time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC_MORT time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC_MORT time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC_MORT calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC_MORT tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC_MORT alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC_MORT alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC_MORT backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC_MORT backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC_MORT backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC_MORT backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC_MORT backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC_MORT backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC_MORT backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC_MORT backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC_MORT backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC_MORT backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC_MORT backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC_MORT backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC_MORT backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC_MORT backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC_MORT backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC_MORT backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC_MORT backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC_MORT backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC_MORT backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC_MORT backup register 19, Address offset: 0x9C */
+} RTC_TypeDef_mort;
+
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef_mort;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef_mort;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO_MORT power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO_MORT argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO_MORT command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO_MORT command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO_MORT response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO_MORT response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO_MORT response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO_MORT response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO_MORT data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO_MORT data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO_MORT data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO_MORT data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO_MORT status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO_MORT interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO_MORT mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO_MORT FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO_MORT data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef_mort;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t CRCPR; /*!< SPI CRC_MORT polynomial register (not used in I2S mode), Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t RXCRCR; /*!< SPI RX CRC_MORT register (not used in I2S mode), Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t TXCRCR; /*!< SPI TX CRC_MORT register (not used in I2S mode), Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+ __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */
+ __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */
+} SPI_TypeDef_mort;
+
+#if defined(STM32F446xx_MORT)
+/**
+ * @brief SPDIFRX_MORT Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
+ __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
+ uint16_t RESERVED0; /*!< Reserved, 0x06 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
+ __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
+ uint16_t RESERVED1; /*!< Reserved, 0x0E */
+ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
+ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
+ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
+ uint16_t RESERVED2; /*!< Reserved, 0x1A */
+} SPDIFRX_TypeDef_mort;
+#endif /* STM32F446xx_MORT */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI_MORT Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI_MORT Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI_MORT Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI_MORT Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI_MORT Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI_MORT Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI_MORT Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI_MORT Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI_MORT Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI_MORT Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI_MORT Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI_MORT Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI_MORT Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef_mort;
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */
+
+#if defined(STM32F446xx_MORT)
+/**
+ * @brief SPDIF-RX Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
+ __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
+ uint16_t RESERVED0; /*!< Reserved, 0x06 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
+ __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
+ uint16_t RESERVED1; /*!< Reserved, 0x0E */
+ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
+ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
+ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
+ uint16_t RESERVED2; /*!< Reserved, 0x1A */
+} SPDIF_TypeDef_mort;
+#endif /* STM32F446xx_MORT */
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+ __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */
+ __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ uint16_t RESERVED9; /*!< Reserved, 0x2A */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ uint16_t RESERVED10; /*!< Reserved, 0x32 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ uint16_t RESERVED11; /*!< Reserved, 0x46 */
+ __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ uint16_t RESERVED12; /*!< Reserved, 0x4A */
+ __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ uint16_t RESERVED13; /*!< Reserved, 0x4E */
+ __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
+ uint16_t RESERVED14; /*!< Reserved, 0x52 */
+} TIM_TypeDef_mort;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+} USART_TypeDef_mort;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG_MORT Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG_MORT Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG_MORT Status register, Address offset: 0x08 */
+} WWDG_TypeDef_mort;
+
+/**
+ * @brief Crypto Processor
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CRYP_MORT control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< CRYP_MORT status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< CRYP_MORT data input register, Address offset: 0x08 */
+ __IO uint32_t DOUT; /*!< CRYP_MORT data output register, Address offset: 0x0C */
+ __IO uint32_t DMACR; /*!< CRYP_MORT DMA control register, Address offset: 0x10 */
+ __IO uint32_t IMSCR; /*!< CRYP_MORT interrupt mask set/clear register, Address offset: 0x14 */
+ __IO uint32_t RISR; /*!< CRYP_MORT raw interrupt status register, Address offset: 0x18 */
+ __IO uint32_t MISR; /*!< CRYP_MORT masked interrupt status register, Address offset: 0x1C */
+ __IO uint32_t K0LR; /*!< CRYP_MORT key left register 0, Address offset: 0x20 */
+ __IO uint32_t K0RR; /*!< CRYP_MORT key right register 0, Address offset: 0x24 */
+ __IO uint32_t K1LR; /*!< CRYP_MORT key left register 1, Address offset: 0x28 */
+ __IO uint32_t K1RR; /*!< CRYP_MORT key right register 1, Address offset: 0x2C */
+ __IO uint32_t K2LR; /*!< CRYP_MORT key left register 2, Address offset: 0x30 */
+ __IO uint32_t K2RR; /*!< CRYP_MORT key right register 2, Address offset: 0x34 */
+ __IO uint32_t K3LR; /*!< CRYP_MORT key left register 3, Address offset: 0x38 */
+ __IO uint32_t K3RR; /*!< CRYP_MORT key right register 3, Address offset: 0x3C */
+ __IO uint32_t IV0LR; /*!< CRYP_MORT initialization vector left-word register 0, Address offset: 0x40 */
+ __IO uint32_t IV0RR; /*!< CRYP_MORT initialization vector right-word register 0, Address offset: 0x44 */
+ __IO uint32_t IV1LR; /*!< CRYP_MORT initialization vector left-word register 1, Address offset: 0x48 */
+ __IO uint32_t IV1RR; /*!< CRYP_MORT initialization vector right-word register 1, Address offset: 0x4C */
+ __IO uint32_t CSGCMCCM0R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
+ __IO uint32_t CSGCMCCM1R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
+ __IO uint32_t CSGCMCCM2R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
+ __IO uint32_t CSGCMCCM3R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
+ __IO uint32_t CSGCMCCM4R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
+ __IO uint32_t CSGCMCCM5R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
+ __IO uint32_t CSGCMCCM6R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
+ __IO uint32_t CSGCMCCM7R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
+ __IO uint32_t CSGCM0R; /*!< CRYP_MORT GCM/GMAC context swap register 0, Address offset: 0x70 */
+ __IO uint32_t CSGCM1R; /*!< CRYP_MORT GCM/GMAC context swap register 1, Address offset: 0x74 */
+ __IO uint32_t CSGCM2R; /*!< CRYP_MORT GCM/GMAC context swap register 2, Address offset: 0x78 */
+ __IO uint32_t CSGCM3R; /*!< CRYP_MORT GCM/GMAC context swap register 3, Address offset: 0x7C */
+ __IO uint32_t CSGCM4R; /*!< CRYP_MORT GCM/GMAC context swap register 4, Address offset: 0x80 */
+ __IO uint32_t CSGCM5R; /*!< CRYP_MORT GCM/GMAC context swap register 5, Address offset: 0x84 */
+ __IO uint32_t CSGCM6R; /*!< CRYP_MORT GCM/GMAC context swap register 6, Address offset: 0x88 */
+ __IO uint32_t CSGCM7R; /*!< CRYP_MORT GCM/GMAC context swap register 7, Address offset: 0x8C */
+} CRYP_TypeDef_mort;
+
+/**
+ * @brief HASH_MORT
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< HASH_MORT control register, Address offset: 0x00 */
+ __IO uint32_t DIN; /*!< HASH_MORT data input register, Address offset: 0x04 */
+ __IO uint32_t STR; /*!< HASH_MORT start register, Address offset: 0x08 */
+ __IO uint32_t HR[5]; /*!< HASH_MORT digest registers, Address offset: 0x0C-0x1C */
+ __IO uint32_t IMR; /*!< HASH_MORT interrupt enable register, Address offset: 0x20 */
+ __IO uint32_t SR; /*!< HASH_MORT status register, Address offset: 0x24 */
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
+ __IO uint32_t CSR[54]; /*!< HASH_MORT context swap registers, Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef_mort;
+
+/**
+ * @brief HASH_DIGEST_MORT
+ */
+
+typedef struct
+{
+ __IO uint32_t HR[8]; /*!< HASH_MORT digest registers, Address offset: 0x310-0x32C */
+} HASH_DIGEST_TypeDef_mort;
+
+/**
+ * @brief RNG_MORT
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG_MORT control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG_MORT status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG_MORT data register, Address offset: 0x08 */
+} RNG_TypeDef_mort;
+
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+/**
+ * @brief LPTIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
+} LPTIM_TypeDef_mort;
+#endif /* STM32F410xx || STM32F413_423xx */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE_MORT ((uint32_t)0x08000000) /*!< FLASH_MORT(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE_MORT ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE_MORT ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT)
+#define SRAM2_BASE_MORT ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
+#define SRAM3_BASE_MORT ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
+#elif defined(STM32F469_479xx)
+#define SRAM2_BASE_MORT ((uint32_t)0x20028000) /*!< SRAM2(16 KB) base address in the alias region */
+#define SRAM3_BASE_MORT ((uint32_t)0x20030000) /*!< SRAM3(64 KB) base address in the alias region */
+#elif defined(STM32F413_423xx)
+#define SRAM2_BASE_MORT ((uint32_t)0x20040000) /*!< SRAM2(16 KB) base address in the alias region */
+#else /* STM32F411xE || STM32F410xx || STM32F412xG */
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT */
+#define PERIPH_BASE_MORT ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE_MORT ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
+
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+#define FSMC_R_BASE_MORT ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+#define FMC_R_BASE_MORT ((uint32_t)0xA0000000) /*!< FMC registers base address */
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+#define QSPI_R_BASE_MORT ((uint32_t)0xA0001000) /*!< QUADSPI_MORT registers base address */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */
+
+#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
+#define SRAM1_BB_BASE_MORT ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT)
+#define SRAM2_BB_BASE_MORT ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE_MORT ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#elif defined(STM32F469_479xx)
+#define SRAM2_BB_BASE_MORT ((uint32_t)0x22500000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE_MORT ((uint32_t)0x22600000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#elif defined(STM32F413_423xx)
+#define SRAM2_BB_BASE_MORT ((uint32_t)0x22800000) /*!< SRAM2(64 KB) base address in the bit-band region */
+#else /* STM32F411xE || STM32F410xx || STM32F412xG */
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT */
+#define PERIPH_BB_BASE_MORT ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE_MORT ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+
+/* Legacy defines */
+#define SRAM_BASE_MORT SRAM1_BASE_MORT
+#define SRAM_BB_BASE_MORT SRAM1_BB_BASE_MORT
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE_MORT PERIPH_BASE_MORT
+#define APB2PERIPH_BASE_MORT (PERIPH_BASE_MORT + 0x00010000)
+#define AHB1PERIPH_BASE_MORT (PERIPH_BASE_MORT + 0x00020000)
+#define AHB2PERIPH_BASE_MORT (PERIPH_BASE_MORT + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE_MORT (APB1PERIPH_BASE_MORT + 0x0000)
+#define TIM3_BASE_MORT (APB1PERIPH_BASE_MORT + 0x0400)
+#define TIM4_BASE_MORT (APB1PERIPH_BASE_MORT + 0x0800)
+#define TIM5_BASE_MORT (APB1PERIPH_BASE_MORT + 0x0C00)
+#define TIM6_BASE_MORT (APB1PERIPH_BASE_MORT + 0x1000)
+#define TIM7_BASE_MORT (APB1PERIPH_BASE_MORT + 0x1400)
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+#define LPTIM1_BASE_MORT (APB1PERIPH_BASE_MORT + 0x2400)
+#endif /* STM32F410xx || STM32F413_423xx */
+#define TIM12_BASE_MORT (APB1PERIPH_BASE_MORT + 0x1800)
+#define TIM13_BASE_MORT (APB1PERIPH_BASE_MORT + 0x1C00)
+#define TIM14_BASE_MORT (APB1PERIPH_BASE_MORT + 0x2000)
+#define RTC_BASE_MORT (APB1PERIPH_BASE_MORT + 0x2800)
+#define WWDG_BASE_MORT (APB1PERIPH_BASE_MORT + 0x2C00)
+#define IWDG_BASE_MORT (APB1PERIPH_BASE_MORT + 0x3000)
+#define I2S2ext_BASE_MORT (APB1PERIPH_BASE_MORT + 0x3400)
+#define SPI2_BASE_MORT (APB1PERIPH_BASE_MORT + 0x3800)
+#define SPI3_BASE_MORT (APB1PERIPH_BASE_MORT + 0x3C00)
+#if defined(STM32F446xx_MORT)
+#define SPDIFRX_BASE_MORT (APB1PERIPH_BASE_MORT + 0x4000)
+#endif /* STM32F446xx_MORT */
+#define I2S3ext_BASE_MORT (APB1PERIPH_BASE_MORT + 0x4000)
+#define USART2_BASE_MORT (APB1PERIPH_BASE_MORT + 0x4400)
+#define USART3_BASE_MORT (APB1PERIPH_BASE_MORT + 0x4800)
+#define UART4_BASE_MORT (APB1PERIPH_BASE_MORT + 0x4C00)
+#define UART5_BASE_MORT (APB1PERIPH_BASE_MORT + 0x5000)
+#define I2C1_BASE_MORT (APB1PERIPH_BASE_MORT + 0x5400)
+#define I2C2_BASE_MORT (APB1PERIPH_BASE_MORT + 0x5800)
+#define I2C3_BASE_MORT (APB1PERIPH_BASE_MORT + 0x5C00)
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT)
+#define FMPI2C1_BASE_MORT (APB1PERIPH_BASE_MORT + 0x6000)
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */
+#define CAN1_BASE_MORT (APB1PERIPH_BASE_MORT + 0x6400)
+#define CAN2_BASE_MORT (APB1PERIPH_BASE_MORT + 0x6800)
+#if defined(STM32F413_423xx)
+#define CAN3_BASE_MORT (APB1PERIPH_BASE_MORT + 0x6C00)
+#endif /* STM32F413_423xx */
+#if defined(STM32F446xx_MORT)
+#define CEC_BASE_MORT (APB1PERIPH_BASE_MORT + 0x6C00)
+#endif /* STM32F446xx_MORT */
+#define PWR_BASE_MORT (APB1PERIPH_BASE_MORT + 0x7000)
+#define DAC_BASE_MORT (APB1PERIPH_BASE_MORT + 0x7400)
+#define UART7_BASE_MORT (APB1PERIPH_BASE_MORT + 0x7800)
+#define UART8_BASE_MORT (APB1PERIPH_BASE_MORT + 0x7C00)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x0000)
+#define TIM8_BASE_MORT (APB2PERIPH_BASE_MORT + 0x0400)
+#define USART1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x1000)
+#define USART6_BASE_MORT (APB2PERIPH_BASE_MORT + 0x1400)
+#define UART9_BASE_MORT (APB2PERIPH_BASE_MORT + 0x1800U)
+#define UART10_BASE_MORT (APB2PERIPH_BASE_MORT + 0x1C00U)
+#define ADC1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x2000)
+#define ADC2_BASE_MORT (APB2PERIPH_BASE_MORT + 0x2100)
+#define ADC3_BASE_MORT (APB2PERIPH_BASE_MORT + 0x2200)
+#define ADC_BASE_MORT (APB2PERIPH_BASE_MORT + 0x2300)
+#define SDIO_BASE_MORT (APB2PERIPH_BASE_MORT + 0x2C00)
+#define SPI1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x3000)
+#define SPI4_BASE_MORT (APB2PERIPH_BASE_MORT + 0x3400)
+#define SYSCFG_BASE_MORT (APB2PERIPH_BASE_MORT + 0x3800)
+#define EXTI_BASE_MORT (APB2PERIPH_BASE_MORT + 0x3C00)
+#define TIM9_BASE_MORT (APB2PERIPH_BASE_MORT + 0x4000)
+#define TIM10_BASE_MORT (APB2PERIPH_BASE_MORT + 0x4400)
+#define TIM11_BASE_MORT (APB2PERIPH_BASE_MORT + 0x4800)
+#define SPI5_BASE_MORT (APB2PERIPH_BASE_MORT + 0x5000)
+#define SPI6_BASE_MORT (APB2PERIPH_BASE_MORT + 0x5400)
+#define SAI1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x5800)
+#define SAI1_Block_A_BASE_MORT (SAI1_BASE_MORT + 0x004)
+#define SAI1_Block_B_BASE_MORT (SAI1_BASE_MORT + 0x024)
+#if defined(STM32F446xx_MORT)
+#define SAI2_BASE_MORT (APB2PERIPH_BASE_MORT + 0x5C00)
+#define SAI2_Block_A_BASE_MORT (SAI2_BASE_MORT + 0x004)
+#define SAI2_Block_B_BASE_MORT (SAI2_BASE_MORT + 0x024)
+#endif /* STM32F446xx_MORT */
+#define LTDC_BASE_MORT (APB2PERIPH_BASE_MORT + 0x6800)
+#define LTDC_Layer1_BASE_MORT (LTDC_BASE_MORT + 0x84)
+#define LTDC_Layer2_BASE_MORT (LTDC_BASE_MORT + 0x104)
+#if defined(STM32F469_479xx)
+#define DSI_BASE_MORT (APB2PERIPH_BASE_MORT + 0x6C00)
+#endif /* STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define DFSDM1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x6000)
+#define DFSDM1_Channel0_BASE_MORT (DFSDM1_BASE_MORT + 0x00)
+#define DFSDM1_Channel1_BASE_MORT (DFSDM1_BASE_MORT + 0x20)
+#define DFSDM1_Channel2_BASE_MORT (DFSDM1_BASE_MORT + 0x40)
+#define DFSDM1_Channel3_BASE_MORT (DFSDM1_BASE_MORT + 0x60)
+#define DFSDM1_Filter0_BASE_MORT (DFSDM1_BASE_MORT + 0x100)
+#define DFSDM1_Filter1_BASE_MORT (DFSDM1_BASE_MORT + 0x180)
+#define DFSDM1_0_MORT ((DFSDM_TypeDef *) DFSDM1_Filter0_BASE_MORT)
+#define DFSDM1_1_MORT ((DFSDM_TypeDef *) DFSDM1_Filter1_BASE_MORT)
+/* Legacy Defines */
+#define DFSDM0 DFSDM1_0_MORT
+#define DFSDM1 DFSDM1_1_MORT
+#if defined(STM32F413_423xx)
+#define DFSDM2_BASE_MORT (APB2PERIPH_BASE_MORT + 0x6400U)
+#define DFSDM2_Channel0_BASE_MORT (DFSDM2_BASE_MORT + 0x00U)
+#define DFSDM2_Channel1_BASE_MORT (DFSDM2_BASE_MORT + 0x20U)
+#define DFSDM2_Channel2_BASE_MORT (DFSDM2_BASE_MORT + 0x40U)
+#define DFSDM2_Channel3_BASE_MORT (DFSDM2_BASE_MORT + 0x60U)
+#define DFSDM2_Channel4_BASE_MORT (DFSDM2_BASE_MORT + 0x80U)
+#define DFSDM2_Channel5_BASE_MORT (DFSDM2_BASE_MORT + 0xA0U)
+#define DFSDM2_Channel6_BASE_MORT (DFSDM2_BASE_MORT + 0xC0U)
+#define DFSDM2_Channel7_BASE_MORT (DFSDM2_BASE_MORT + 0xE0U)
+#define DFSDM2_Filter0_BASE_MORT (DFSDM2_BASE_MORT + 0x100U)
+#define DFSDM2_Filter1_BASE_MORT (DFSDM2_BASE_MORT + 0x180U)
+#define DFSDM2_Filter2_BASE_MORT (DFSDM2_BASE_MORT + 0x200U)
+#define DFSDM2_Filter3_BASE_MORT (DFSDM2_BASE_MORT + 0x280U)
+#define DFSDM2_0_MORT ((DFSDM_TypeDef *) DFSDM2_Filter0_BASE_MORT)
+#define DFSDM2_1_MORT ((DFSDM_TypeDef *) DFSDM2_Filter1_BASE_MORT)
+#define DFSDM2_2_MORT ((DFSDM_TypeDef *) DFSDM2_Filter2_BASE_MORT)
+#define DFSDM2_3_MORT ((DFSDM_TypeDef *) DFSDM2_Filter3_BASE_MORT)
+#endif /* STM32F413_423xx */
+#endif /* STM32F412xG || STM32F413_423xx */
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x0000)
+#define GPIOB_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x0400)
+#define GPIOC_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x0800)
+#define GPIOD_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x0C00)
+#define GPIOE_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x1000)
+#define GPIOF_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x1400)
+#define GPIOG_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x1800)
+#define GPIOH_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x1C00)
+#define GPIOI_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x2000)
+#define GPIOJ_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x2400)
+#define GPIOK_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x2800)
+#define CRC_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x3000)
+#define RCC_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x3800)
+#define FLASH_R_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x3C00)
+#define DMA1_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x6000)
+#define DMA1_Stream0_BASE_MORT (DMA1_BASE_MORT + 0x010)
+#define DMA1_Stream1_BASE_MORT (DMA1_BASE_MORT + 0x028)
+#define DMA1_Stream2_BASE_MORT (DMA1_BASE_MORT + 0x040)
+#define DMA1_Stream3_BASE_MORT (DMA1_BASE_MORT + 0x058)
+#define DMA1_Stream4_BASE_MORT (DMA1_BASE_MORT + 0x070)
+#define DMA1_Stream5_BASE_MORT (DMA1_BASE_MORT + 0x088)
+#define DMA1_Stream6_BASE_MORT (DMA1_BASE_MORT + 0x0A0)
+#define DMA1_Stream7_BASE_MORT (DMA1_BASE_MORT + 0x0B8)
+#define DMA2_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x6400)
+#define DMA2_Stream0_BASE_MORT (DMA2_BASE_MORT + 0x010)
+#define DMA2_Stream1_BASE_MORT (DMA2_BASE_MORT + 0x028)
+#define DMA2_Stream2_BASE_MORT (DMA2_BASE_MORT + 0x040)
+#define DMA2_Stream3_BASE_MORT (DMA2_BASE_MORT + 0x058)
+#define DMA2_Stream4_BASE_MORT (DMA2_BASE_MORT + 0x070)
+#define DMA2_Stream5_BASE_MORT (DMA2_BASE_MORT + 0x088)
+#define DMA2_Stream6_BASE_MORT (DMA2_BASE_MORT + 0x0A0)
+#define DMA2_Stream7_BASE_MORT (DMA2_BASE_MORT + 0x0B8)
+#define ETH_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x8000)
+#define ETH_MAC_BASE_MORT (ETH_BASE_MORT)
+#define ETH_MMC_BASE_MORT (ETH_BASE_MORT + 0x0100)
+#define ETH_PTP_BASE_MORT (ETH_BASE_MORT + 0x0700)
+#define ETH_DMA_BASE_MORT (ETH_BASE_MORT + 0x1000)
+#define DMA2D_BASE_MORT (AHB1PERIPH_BASE_MORT + 0xB000)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE_MORT (AHB2PERIPH_BASE_MORT + 0x50000)
+#define CRYP_BASE_MORT (AHB2PERIPH_BASE_MORT + 0x60000)
+#define HASH_BASE_MORT (AHB2PERIPH_BASE_MORT + 0x60400)
+#define HASH_DIGEST_BASE_MORT (AHB2PERIPH_BASE_MORT + 0x60710)
+#define RNG_BASE_MORT (AHB2PERIPH_BASE_MORT + 0x60800)
+
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE_MORT (FSMC_R_BASE_MORT + 0x0000)
+#define FSMC_Bank1E_R_BASE_MORT (FSMC_R_BASE_MORT + 0x0104)
+#define FSMC_Bank2_R_BASE_MORT (FSMC_R_BASE_MORT + 0x0060)
+#define FSMC_Bank3_R_BASE_MORT (FSMC_R_BASE_MORT + 0x0080)
+#define FSMC_Bank4_R_BASE_MORT (FSMC_R_BASE_MORT + 0x00A0)
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE_MORT (FMC_R_BASE_MORT + 0x0000)
+#define FMC_Bank1E_R_BASE_MORT (FMC_R_BASE_MORT + 0x0104)
+#define FMC_Bank2_R_BASE_MORT (FMC_R_BASE_MORT + 0x0060)
+#define FMC_Bank3_R_BASE_MORT (FMC_R_BASE_MORT + 0x0080)
+#define FMC_Bank4_R_BASE_MORT (FMC_R_BASE_MORT + 0x00A0)
+#define FMC_Bank5_6_R_BASE_MORT (FMC_R_BASE_MORT + 0x0140)
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE_MORT ((uint32_t )0xE0042000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+#define QUADSPI_MORT ((QUADSPI_TypeDef_mort *) QSPI_R_BASE_MORT)
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */
+#define TIM2_MORT ((TIM_TypeDef_mort *) TIM2_BASE_MORT)
+#define TIM3_MORT ((TIM_TypeDef_mort *) TIM3_BASE_MORT)
+#define TIM4_MORT ((TIM_TypeDef_mort *) TIM4_BASE_MORT)
+#define TIM5_MORT ((TIM_TypeDef_mort *) TIM5_BASE_MORT)
+#define TIM6_MORT ((TIM_TypeDef_mort *) TIM6_BASE_MORT)
+#define TIM7_MORT ((TIM_TypeDef_mort *) TIM7_BASE_MORT)
+#define TIM12_MORT ((TIM_TypeDef_mort *) TIM12_BASE_MORT)
+#define TIM13_MORT ((TIM_TypeDef_mort *) TIM13_BASE_MORT)
+#define TIM14_MORT ((TIM_TypeDef_mort *) TIM14_BASE_MORT)
+#define RTC_MORT ((RTC_TypeDef_mort *) RTC_BASE_MORT)
+#define WWDG_MORT ((WWDG_TypeDef_mort *) WWDG_BASE_MORT)
+#define IWDG_MORT ((IWDG_TypeDef_mort *) IWDG_BASE_MORT)
+#define I2S2ext_MORT ((SPI_TypeDef_mort *) I2S2ext_BASE_MORT)
+#define SPI2_MORT ((SPI_TypeDef_mort *) SPI2_BASE_MORT)
+#define SPI3_MORT ((SPI_TypeDef_mort *) SPI3_BASE_MORT)
+#if defined(STM32F446xx_MORT)
+#define SPDIFRX_MORT ((SPDIFRX_TypeDef_mort *) SPDIFRX_BASE_MORT)
+#endif /* STM32F446xx_MORT */
+#define I2S3ext_MORT ((SPI_TypeDef_mort *) I2S3ext_BASE_MORT)
+#define USART2_MORT ((USART_TypeDef_mort *) USART2_BASE_MORT)
+#define USART3_MORT ((USART_TypeDef_mort *) USART3_BASE_MORT)
+#define UART4_MORT ((USART_TypeDef_mort *) UART4_BASE_MORT)
+#define UART5_MORT ((USART_TypeDef_mort *) UART5_BASE_MORT)
+#define I2C1_MORT ((I2C_TypeDef_mort *) I2C1_BASE_MORT)
+#define I2C2_MORT ((I2C_TypeDef_mort *) I2C2_BASE_MORT)
+#define I2C3_MORT ((I2C_TypeDef_mort *) I2C3_BASE_MORT)
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT)
+#define FMPI2C1_MORT ((FMPI2C_TypeDef_mort *) FMPI2C1_BASE_MORT)
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+#define LPTIM1_MORT ((LPTIM_TypeDef_mort *) LPTIM1_BASE_MORT)
+#endif /* STM32F410xx || STM32F413_423xx */
+#define CAN1_MORT ((CAN_TypeDef_mort *) CAN1_BASE_MORT)
+#define CAN2_MORT ((CAN_TypeDef_mort *) CAN2_BASE_MORT)
+#if defined(STM32F413_423xx)
+#define CAN3_MORT ((CAN_TypeDef_mort *) CAN3_BASE_MORT)
+#endif /* STM32F413_423xx */
+#if defined(STM32F446xx_MORT)
+#define CEC_MORT ((CEC_TypeDef_mort *) CEC_BASE_MORT)
+#endif /* STM32F446xx_MORT */
+#define PWR_MORT ((PWR_TypeDef_mort *) PWR_BASE_MORT)
+#define DAC_MORT ((DAC_TypeDef_mort *) DAC_BASE_MORT)
+#define UART7_MORT ((USART_TypeDef_mort *) UART7_BASE_MORT)
+#define UART8_MORT ((USART_TypeDef_mort *) UART8_BASE_MORT)
+#define UART9_MORT ((USART_TypeDef_mort *) UART9_BASE_MORT)
+#define UART10_MORT ((USART_TypeDef_mort *) UART10_BASE_MORT)
+#define TIM1_MORT ((TIM_TypeDef_mort *) TIM1_BASE_MORT)
+#define TIM8_MORT ((TIM_TypeDef_mort *) TIM8_BASE_MORT)
+#define USART1_MORT ((USART_TypeDef_mort *) USART1_BASE_MORT)
+#define USART6_MORT ((USART_TypeDef_mort *) USART6_BASE_MORT)
+#define ADC_MORT ((ADC_Common_TypeDef_mort *) ADC_BASE_MORT)
+#define ADC1_MORT ((ADC_TypeDef_mort *) ADC1_BASE_MORT)
+#define ADC2_MORT ((ADC_TypeDef_mort *) ADC2_BASE_MORT)
+#define ADC3_MORT ((ADC_TypeDef_mort *) ADC3_BASE_MORT)
+#define SDIO_MORT ((SDIO_TypeDef_mort *) SDIO_BASE_MORT)
+#define SPI1_MORT ((SPI_TypeDef_mort *) SPI1_BASE_MORT)
+#define SPI4_MORT ((SPI_TypeDef_mort *) SPI4_BASE_MORT)
+#define SYSCFG_MORT ((SYSCFG_TypeDef_mort *) SYSCFG_BASE_MORT)
+#define EXTI_MORT ((EXTI_TypeDef_mort *) EXTI_BASE_MORT)
+#define TIM9_MORT ((TIM_TypeDef_mort *) TIM9_BASE_MORT)
+#define TIM10_MORT ((TIM_TypeDef_mort *) TIM10_BASE_MORT)
+#define TIM11_MORT ((TIM_TypeDef_mort *) TIM11_BASE_MORT)
+#define SPI5_MORT ((SPI_TypeDef_mort *) SPI5_BASE_MORT)
+#define SPI6_MORT ((SPI_TypeDef_mort *) SPI6_BASE_MORT)
+#define SAI1_MORT ((SAI_TypeDef_mort *) SAI1_BASE_MORT)
+#define SAI1_Block_A_MORT ((SAI_Block_TypeDef_mort *)SAI1_Block_A_BASE_MORT)
+#define SAI1_Block_B_MORT ((SAI_Block_TypeDef_mort *)SAI1_Block_B_BASE_MORT)
+#if defined(STM32F446xx_MORT)
+#define SAI2_MORT ((SAI_TypeDef_mort *) SAI2_BASE_MORT)
+#define SAI2_Block_A_MORT ((SAI_Block_TypeDef_mort *)SAI2_Block_A_BASE_MORT)
+#define SAI2_Block_B_MORT ((SAI_Block_TypeDef_mort *)SAI2_Block_B_BASE_MORT)
+#endif /* STM32F446xx_MORT */
+#define LTDC_MORT ((LTDC_TypeDef_mort *)LTDC_BASE_MORT)
+#define LTDC_Layer1_MORT ((LTDC_Layer_TypeDef_mort *)LTDC_Layer1_BASE_MORT)
+#define LTDC_Layer2_MORT ((LTDC_Layer_TypeDef_mort *)LTDC_Layer2_BASE_MORT)
+#if defined(STM32F469_479xx)
+#define DSI_MORT ((DSI_TypeDef_mort *)DSI_BASE_MORT)
+#endif /* STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define DFSDM1_Channel0_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM1_Channel0_BASE_MORT)
+#define DFSDM1_Channel1_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM1_Channel1_BASE_MORT)
+#define DFSDM1_Channel2_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM1_Channel2_BASE_MORT)
+#define DFSDM1_Channel3_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM1_Channel3_BASE_MORT)
+#define DFSDM1_Filter0_MORT ((DFSDM_TypeDef *) DFSDM_Filter0_BASE)
+#define DFSDM1_Filter1_MORT ((DFSDM_TypeDef *) DFSDM_Filter1_BASE)
+#if defined(STM32F413_423xx)
+#define DFSDM2_Channel0_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel0_BASE_MORT)
+#define DFSDM2_Channel1_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel1_BASE_MORT)
+#define DFSDM2_Channel2_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel2_BASE_MORT)
+#define DFSDM2_Channel3_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel3_BASE_MORT)
+#define DFSDM2_Channel4_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel4_BASE_MORT)
+#define DFSDM2_Channel5_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel5_BASE_MORT)
+#define DFSDM2_Channel6_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel6_BASE_MORT)
+#define DFSDM2_Channel7_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel7_BASE_MORT)
+#define DFSDM2_Filter0_MORT ((DFSDM_Filter_TypeDef_mort *) DFSDM2_Filter0_BASE_MORT)
+#define DFSDM2_Filter1_MORT ((DFSDM_Filter_TypeDef_mort *) DFSDM2_Filter1_BASE_MORT)
+#define DFSDM2_Filter2_MORT ((DFSDM_Filter_TypeDef_mort *) DFSDM2_Filter2_BASE_MORT)
+#define DFSDM2_Filter3_MORT ((DFSDM_Filter_TypeDef_mort *) DFSDM2_Filter3_BASE_MORT)
+#endif /* STM32F413_423xx */
+#endif /* STM32F412xG || STM32F413_423xx */
+#define GPIOA_MORT ((GPIO_TypeDef_mort *) GPIOA_BASE_MORT)
+#define GPIOB_MORT ((GPIO_TypeDef_mort *) GPIOB_BASE_MORT)
+#define GPIOC_MORT ((GPIO_TypeDef_mort *) GPIOC_BASE_MORT)
+#define GPIOD_MORT ((GPIO_TypeDef_mort *) GPIOD_BASE_MORT)
+#define GPIOE_MORT ((GPIO_TypeDef_mort *) GPIOE_BASE_MORT)
+#define GPIOF_MORT ((GPIO_TypeDef_mort *) GPIOF_BASE_MORT)
+#define GPIOG_MORT ((GPIO_TypeDef_mort *) GPIOG_BASE_MORT)
+#define GPIOH_MORT ((GPIO_TypeDef_mort *) GPIOH_BASE_MORT)
+#define GPIOI_MORT ((GPIO_TypeDef_mort *) GPIOI_BASE_MORT)
+#define GPIOJ_MORT ((GPIO_TypeDef_mort *) GPIOJ_BASE_MORT)
+#define GPIOK_MORT ((GPIO_TypeDef_mort *) GPIOK_BASE_MORT)
+#define CRC_MORT ((CRC_TypeDef_mort *) CRC_BASE_MORT)
+#define RCC_MORT ((RCC_TypeDef_mort *) RCC_BASE_MORT)
+#define FLASH_MORT ((FLASH_TypeDef_mort *) FLASH_R_BASE_MORT)
+#define DMA1_MORT ((DMA_TypeDef_mort *) DMA1_BASE_MORT)
+#define DMA1_Stream0_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream0_BASE_MORT)
+#define DMA1_Stream1_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream1_BASE_MORT)
+#define DMA1_Stream2_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream2_BASE_MORT)
+#define DMA1_Stream3_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream3_BASE_MORT)
+#define DMA1_Stream4_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream4_BASE_MORT)
+#define DMA1_Stream5_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream5_BASE_MORT)
+#define DMA1_Stream6_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream6_BASE_MORT)
+#define DMA1_Stream7_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream7_BASE_MORT)
+#define DMA2_MORT ((DMA_TypeDef_mort *) DMA2_BASE_MORT)
+#define DMA2_Stream0_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream0_BASE_MORT)
+#define DMA2_Stream1_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream1_BASE_MORT)
+#define DMA2_Stream2_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream2_BASE_MORT)
+#define DMA2_Stream3_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream3_BASE_MORT)
+#define DMA2_Stream4_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream4_BASE_MORT)
+#define DMA2_Stream5_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream5_BASE_MORT)
+#define DMA2_Stream6_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream6_BASE_MORT)
+#define DMA2_Stream7_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream7_BASE_MORT)
+#define ETH_MORT ((ETH_TypeDef_mort *) ETH_BASE_MORT)
+#define DMA2D_MORT ((DMA2D_TypeDef_mort *)DMA2D_BASE_MORT)
+#define DCMI_MORT ((DCMI_TypeDef_mort *) DCMI_BASE_MORT)
+#define CRYP_MORT ((CRYP_TypeDef_mort *) CRYP_BASE_MORT)
+#define HASH_MORT ((HASH_TypeDef_mort *) HASH_BASE_MORT)
+#define HASH_DIGEST_MORT ((HASH_DIGEST_TypeDef_mort *) HASH_DIGEST_BASE_MORT)
+#define RNG_MORT ((RNG_TypeDef_mort *) RNG_BASE_MORT)
+
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+#define FSMC_Bank1_MORT ((FSMC_Bank1_TypeDef_mort *) FSMC_Bank1_R_BASE_MORT)
+#define FSMC_Bank1E_MORT ((FSMC_Bank1E_TypeDef_mort *) FSMC_Bank1E_R_BASE_MORT)
+#define FSMC_Bank2_MORT ((FSMC_Bank2_TypeDef_mort *) FSMC_Bank2_R_BASE_MORT)
+#define FSMC_Bank3_MORT ((FSMC_Bank3_TypeDef_mort *) FSMC_Bank3_R_BASE_MORT)
+#define FSMC_Bank4_MORT ((FSMC_Bank4_TypeDef_mort *) FSMC_Bank4_R_BASE_MORT)
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+#define FMC_Bank1_MORT ((FMC_Bank1_TypeDef_mort *) FMC_Bank1_R_BASE_MORT)
+#define FMC_Bank1E_MORT ((FMC_Bank1E_TypeDef_mort *) FMC_Bank1E_R_BASE_MORT)
+#define FMC_Bank2_MORT ((FMC_Bank2_TypeDef_mort *) FMC_Bank2_R_BASE_MORT)
+#define FMC_Bank3_MORT ((FMC_Bank3_TypeDef_mort *) FMC_Bank3_R_BASE_MORT)
+#define FMC_Bank4_MORT ((FMC_Bank4_TypeDef_mort *) FMC_Bank4_R_BASE_MORT)
+#define FMC_Bank5_6_MORT ((FMC_Bank5_6_TypeDef_mort *) FMC_Bank5_6_R_BASE_MORT)
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */
+
+#define DBGMCU_MORT ((DBGMCU_TypeDef_mort *) DBGMCU_BASE_MORT)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_MORT ((uint8_t)0x01) /*!<Analog watchdog flag */
+#define ADC_SR_EOC_MORT ((uint8_t)0x02) /*!<End of conversion */
+#define ADC_SR_JEOC_MORT ((uint8_t)0x04) /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_MORT ((uint8_t)0x08) /*!<Injected channel Start flag */
+#define ADC_SR_STRT_MORT ((uint8_t)0x10) /*!<Regular channel Start flag */
+#define ADC_SR_OVR_MORT ((uint8_t)0x20) /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_MORT ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CR1_EOCIE_MORT ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_MORT ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_MORT ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_MORT ((uint32_t)0x00000100) /*!<Scan mode */
+#define ADC_CR1_AWDSGL_MORT ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_MORT ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_MORT ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_MORT ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_MORT ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0_MORT ((uint32_t)0x00002000) /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1_MORT ((uint32_t)0x00004000) /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2_MORT ((uint32_t)0x00008000) /*!<Bit 2 */
+#define ADC_CR1_JAWDEN_MORT ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_MORT ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_MORT ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0_MORT ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR1_RES_1_MORT ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR1_OVRIE_MORT ((uint32_t)0x04000000) /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_MORT ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_MORT ((uint32_t)0x00000002) /*!<Continuous Conversion */
+#define ADC_CR2_DMA_MORT ((uint32_t)0x00000100) /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_MORT ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC_MORT) */
+#define ADC_CR2_EOCS_MORT ((uint32_t)0x00000400) /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_MORT ((uint32_t)0x00000800) /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_MORT ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0_MORT ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1_MORT ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2_MORT ((uint32_t)0x00040000) /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3_MORT ((uint32_t)0x00080000) /*!<Bit 3 */
+#define ADC_CR2_JEXTEN_MORT ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0_MORT ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1_MORT ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_CR2_JSWSTART_MORT ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_MORT ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0_MORT ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1_MORT ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2_MORT ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3_MORT ((uint32_t)0x08000000) /*!<Bit 3 */
+#define ADC_CR2_EXTEN_MORT ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0_MORT ((uint32_t)0x10000000) /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1_MORT ((uint32_t)0x20000000) /*!<Bit 1 */
+#define ADC_CR2_SWSTART_MORT ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_MORT ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR1_SMP11_MORT ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0_MORT ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1_MORT ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2_MORT ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR1_SMP12_MORT ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0_MORT ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1_MORT ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2_MORT ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR1_SMP13_MORT ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0_MORT ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1_MORT ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2_MORT ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR1_SMP14_MORT ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0_MORT ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1_MORT ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2_MORT ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP15_MORT ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP16_MORT ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0_MORT ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1_MORT ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2_MORT ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP17_MORT ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0_MORT ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1_MORT ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2_MORT ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP18_MORT ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0_MORT ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1_MORT ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2_MORT ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_MORT ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR2_SMP1_MORT ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0_MORT ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1_MORT ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2_MORT ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR2_SMP2_MORT ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0_MORT ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1_MORT ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2_MORT ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR2_SMP3_MORT ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0_MORT ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1_MORT ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2_MORT ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR2_SMP4_MORT ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0_MORT ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1_MORT ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2_MORT ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP5_MORT ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP6_MORT ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0_MORT ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1_MORT ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2_MORT ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP7_MORT ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0_MORT ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1_MORT ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2_MORT ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP8_MORT ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0_MORT ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1_MORT ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2_MORT ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP9_MORT ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0_MORT ((uint32_t)0x08000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1_MORT ((uint32_t)0x10000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2_MORT ((uint32_t)0x20000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_MORT ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_MORT ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_MORT ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_MORT ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_MORT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_MORT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_MORT ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR1_SQ14_MORT ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0_MORT ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1_MORT ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2_MORT ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3_MORT ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4_MORT ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR1_SQ15_MORT ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0_MORT ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1_MORT ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2_MORT ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3_MORT ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4_MORT ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR1_SQ16_MORT ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3_MORT ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4_MORT ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR1_L_MORT ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L__0_MORT ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR1_L__1_MORT ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR1_L__2_MORT ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR1_L__3_MORT ((uint32_t)0x00800000) /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_MORT ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR2_SQ8_MORT ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0_MORT ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1_MORT ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2_MORT ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3_MORT ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4_MORT ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR2_SQ9_MORT ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0_MORT ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1_MORT ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2_MORT ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3_MORT ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4_MORT ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR2_SQ10_MORT ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3_MORT ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4_MORT ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR2_SQ11_MORT ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0_MORT ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1_MORT ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2_MORT ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3_MORT ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4_MORT ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR2_SQ12_MORT ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0_MORT ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1_MORT ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2_MORT ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3_MORT ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4_MORT ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_MORT ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR3_SQ2_MORT ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0_MORT ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1_MORT ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2_MORT ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3_MORT ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4_MORT ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR3_SQ3_MORT ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0_MORT ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1_MORT ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2_MORT ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3_MORT ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4_MORT ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR3_SQ4_MORT ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3_MORT ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4_MORT ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR3_SQ5_MORT ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0_MORT ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1_MORT ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2_MORT ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3_MORT ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4_MORT ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR3_SQ6_MORT ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0_MORT ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1_MORT ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2_MORT ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3_MORT ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4_MORT ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_MORT ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_JSQR_JSQ2_MORT ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0_MORT ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1_MORT ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2_MORT ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3_MORT ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4_MORT ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_JSQR_JSQ3_MORT ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0_MORT ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1_MORT ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2_MORT ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3_MORT ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4_MORT ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_JSQR_JSQ4_MORT ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3_MORT ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4_MORT ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_JSQR_JL_MORT ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0_MORT ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_JSQR_JL_1_MORT ((uint32_t)0x00200000) /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_MORT ((uint16_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_MORT ((uint16_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_MORT ((uint16_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_MORT ((uint16_t)0xFFFF) /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_MORT ((uint32_t)0x0000FFFF) /*!<Regular data */
+#define ADC_DR_ADC2DATA_MORT ((uint32_t)0xFFFF0000) /*!<ADC2_MORT data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1_MORT ((uint32_t)0x00000001) /*!<ADC1_MORT Analog watchdog flag */
+#define ADC_CSR_EOC1_MORT ((uint32_t)0x00000002) /*!<ADC1_MORT End of conversion */
+#define ADC_CSR_JEOC1_MORT ((uint32_t)0x00000004) /*!<ADC1_MORT Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_MORT ((uint32_t)0x00000008) /*!<ADC1_MORT Injected channel Start flag */
+#define ADC_CSR_STRT1_MORT ((uint32_t)0x00000010) /*!<ADC1_MORT Regular channel Start flag */
+#define ADC_CSR_OVR1_MORT ((uint32_t)0x00000020) /*!<ADC1_MORT DMA overrun flag */
+#define ADC_CSR_AWD2_MORT ((uint32_t)0x00000100) /*!<ADC2_MORT Analog watchdog flag */
+#define ADC_CSR_EOC2_MORT ((uint32_t)0x00000200) /*!<ADC2_MORT End of conversion */
+#define ADC_CSR_JEOC2_MORT ((uint32_t)0x00000400) /*!<ADC2_MORT Injected channel end of conversion */
+#define ADC_CSR_JSTRT2_MORT ((uint32_t)0x00000800) /*!<ADC2_MORT Injected channel Start flag */
+#define ADC_CSR_STRT2_MORT ((uint32_t)0x00001000) /*!<ADC2_MORT Regular channel Start flag */
+#define ADC_CSR_OVR2_MORT ((uint32_t)0x00002000) /*!<ADC2_MORT DMA overrun flag */
+#define ADC_CSR_AWD3_MORT ((uint32_t)0x00010000) /*!<ADC3_MORT Analog watchdog flag */
+#define ADC_CSR_EOC3_MORT ((uint32_t)0x00020000) /*!<ADC3_MORT End of conversion */
+#define ADC_CSR_JEOC3_MORT ((uint32_t)0x00040000) /*!<ADC3_MORT Injected channel end of conversion */
+#define ADC_CSR_JSTRT3_MORT ((uint32_t)0x00080000) /*!<ADC3_MORT Injected channel Start flag */
+#define ADC_CSR_STRT3_MORT ((uint32_t)0x00100000) /*!<ADC3_MORT Regular channel Start flag */
+#define ADC_CSR_OVR3_MORT ((uint32_t)0x00200000) /*!<ADC3_MORT DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1_MORT ADC_CSR_OVR1_MORT
+#define ADC_CSR_DOVR2_MORT ADC_CSR_OVR2_MORT
+#define ADC_CSR_DOVR3_MORT ADC_CSR_OVR3_MORT
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI_MORT ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC_MORT mode selection) */
+#define ADC_CCR_MULTI_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CCR_MULTI_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CCR_MULTI_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CCR_MULTI_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CCR_MULTI_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CCR_DELAY_MORT ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0_MORT ((uint32_t)0x00000100) /*!<Bit 0 */
+#define ADC_CCR_DELAY_1_MORT ((uint32_t)0x00000200) /*!<Bit 1 */
+#define ADC_CCR_DELAY_2_MORT ((uint32_t)0x00000400) /*!<Bit 2 */
+#define ADC_CCR_DELAY_3_MORT ((uint32_t)0x00000800) /*!<Bit 3 */
+#define ADC_CCR_DDS_MORT ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC_MORT mode) */
+#define ADC_CCR_DMA_MORT ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0_MORT ((uint32_t)0x00004000) /*!<Bit 0 */
+#define ADC_CCR_DMA_1_MORT ((uint32_t)0x00008000) /*!<Bit 1 */
+#define ADC_CCR_ADCPRE_MORT ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC_MORT prescaler) */
+#define ADC_CCR_ADCPRE_0_MORT ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1_MORT ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CCR_VBATE_MORT ((uint32_t)0x00400000) /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_MORT ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1_MORT ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_MORT ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+
+
+/******************* Bit definition for CAN_MSR register ********************/
+
+
+/******************* Bit definition for CAN_TSR register ********************/
+
+
+/******************* Bit definition for CAN_RF0R register *******************/
+
+
+/******************* Bit definition for CAN_RF1R register *******************/
+
+
+/******************** Bit definition for CAN_IER register *******************/
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+
+/******************* Bit definition for CAN_BTR register ********************/
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+
+/******************* Bit definition for CAN_TI1R register *******************/
+
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+
+
+/******************* Bit definition for CAN_TI2R register *******************/
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+
+
+/******************* Bit definition for CAN_RI0R register *******************/
+
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+
+
+/******************* Bit definition for CAN_RI1R register *******************/
+
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+
+
+/******************* Bit definition for CAN_FM1R register *******************/
+
+
+/******************* Bit definition for CAN_FS1R register *******************/
+
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+
+
+/******************* Bit definition for CAN_FA1R register *******************/
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+
+
+
+#if defined(STM32F446xx_MORT)
+/******************************************************************************/
+/* */
+/* HDMI-CEC_MORT (CEC_MORT) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CEC_CR register *********************/
+#define CEC_CR_CECEN_MORT ((uint32_t)0x00000001) /*!< CEC_MORT Enable */
+#define CEC_CR_TXSOM_MORT ((uint32_t)0x00000002) /*!< CEC_MORT Tx Start Of Message */
+#define CEC_CR_TXEOM_MORT ((uint32_t)0x00000004) /*!< CEC_MORT Tx End Of Message */
+
+/******************* Bit definition for CEC_CFGR register *******************/
+#define CEC_CFGR_SFT_MORT ((uint32_t)0x00000007) /*!< CEC_MORT Signal Free Time */
+#define CEC_CFGR_RXTOL_MORT ((uint32_t)0x00000008) /*!< CEC_MORT Tolerance */
+#define CEC_CFGR_BRESTP_MORT ((uint32_t)0x00000010) /*!< CEC_MORT Rx Stop */
+#define CEC_CFGR_BREGEN_MORT ((uint32_t)0x00000020) /*!< CEC_MORT Bit Rising Error generation */
+#define CEC_CFGR_LREGEN_MORT ((uint32_t)0x00000040) /*!< CEC_MORT Long Period Error generation */
+#define CEC_CFGR_SFTOPT_MORT ((uint32_t)0x00000100) /*!< CEC_MORT Signal Free Time optional */
+#define CEC_CFGR_BRDNOGEN_MORT ((uint32_t)0x00000080) /*!< CEC_MORT Broadcast No error generation */
+#define CEC_CFGR_OAR_MORT ((uint32_t)0x7FFF0000) /*!< CEC_MORT Own Address */
+#define CEC_CFGR_LSTN_MORT ((uint32_t)0x80000000) /*!< CEC_MORT Listen mode */
+
+/******************* Bit definition for CEC_TXDR register *******************/
+#define CEC_TXDR_TXD_MORT ((uint32_t)0x000000FF) /*!< CEC_MORT Tx Data */
+
+/******************* Bit definition for CEC_RXDR register *******************/
+#define CEC_TXDR_RXD_MORT ((uint32_t)0x000000FF) /*!< CEC_MORT Rx Data */
+
+/******************* Bit definition for CEC_ISR register ********************/
+#define CEC_ISR_RXBR_MORT ((uint32_t)0x00000001) /*!< CEC_MORT Rx-Byte Received */
+#define CEC_ISR_RXEND_MORT ((uint32_t)0x00000002) /*!< CEC_MORT End Of Reception */
+#define CEC_ISR_RXOVR_MORT ((uint32_t)0x00000004) /*!< CEC_MORT Rx-Overrun */
+#define CEC_ISR_BRE_MORT ((uint32_t)0x00000008) /*!< CEC_MORT Rx Bit Rising Error */
+#define CEC_ISR_SBPE_MORT ((uint32_t)0x00000010) /*!< CEC_MORT Rx Short Bit period Error */
+#define CEC_ISR_LBPE_MORT ((uint32_t)0x00000020) /*!< CEC_MORT Rx Long Bit period Error */
+#define CEC_ISR_RXACKE_MORT ((uint32_t)0x00000040) /*!< CEC_MORT Rx Missing Acknowledge */
+#define CEC_ISR_ARBLST_MORT ((uint32_t)0x00000080) /*!< CEC_MORT Arbitration Lost */
+#define CEC_ISR_TXBR_MORT ((uint32_t)0x00000100) /*!< CEC_MORT Tx Byte Request */
+#define CEC_ISR_TXEND_MORT ((uint32_t)0x00000200) /*!< CEC_MORT End of Transmission */
+#define CEC_ISR_TXUDR_MORT ((uint32_t)0x00000400) /*!< CEC_MORT Tx-Buffer Underrun */
+#define CEC_ISR_TXERR_MORT ((uint32_t)0x00000800) /*!< CEC_MORT Tx-Error */
+#define CEC_ISR_TXACKE_MORT ((uint32_t)0x00001000) /*!< CEC_MORT Tx Missing Acknowledge */
+
+/******************* Bit definition for CEC_IER register ********************/
+#define CEC_IER_RXBRIE_MORT ((uint32_t)0x00000001) /*!< CEC_MORT Rx-Byte Received IT Enable */
+#define CEC_IER_RXENDIE_MORT ((uint32_t)0x00000002) /*!< CEC_MORT End Of Reception IT Enable */
+#define CEC_IER_RXOVRIE_MORT ((uint32_t)0x00000004) /*!< CEC_MORT Rx-Overrun IT Enable */
+#define CEC_IER_BREIEIE_MORT ((uint32_t)0x00000008) /*!< CEC_MORT Rx Bit Rising Error IT Enable */
+#define CEC_IER_SBPEIE_MORT ((uint32_t)0x00000010) /*!< CEC_MORT Rx Short Bit period Error IT Enable */
+#define CEC_IER_LBPEIE_MORT ((uint32_t)0x00000020) /*!< CEC_MORT Rx Long Bit period Error IT Enable */
+#define CEC_IER_RXACKEIE_MORT ((uint32_t)0x00000040) /*!< CEC_MORT Rx Missing Acknowledge IT Enable */
+#define CEC_IER_ARBLSTIE_MORT ((uint32_t)0x00000080) /*!< CEC_MORT Arbitration Lost IT Enable */
+#define CEC_IER_TXBRIE_MORT ((uint32_t)0x00000100) /*!< CEC_MORT Tx Byte Request IT Enable */
+#define CEC_IER_TXENDIE_MORT ((uint32_t)0x00000200) /*!< CEC_MORT End of Transmission IT Enable */
+#define CEC_IER_TXUDRIE_MORT ((uint32_t)0x00000400) /*!< CEC_MORT Tx-Buffer Underrun IT Enable */
+#define CEC_IER_TXERRIE_MORT ((uint32_t)0x00000800) /*!< CEC_MORT Tx-Error IT Enable */
+#define CEC_IER_TXACKEIE_MORT ((uint32_t)0x00001000) /*!< CEC_MORT Tx Missing Acknowledge IT Enable */
+#endif /* STM32F446xx_MORT */
+
+/******************************************************************************/
+/* */
+/* CRC_MORT calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_MORT ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_MORT ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_MORT ((uint8_t)0x01) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Crypto Processor */
+/* */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register ********************/
+
+
+/****************** Bits definition for CRYP_SR register *********************/
+
+/****************** Bits definition for CRYP_DMACR register ******************/
+
+/***************** Bits definition for CRYP_IMSCR register ******************/
+
+/****************** Bits definition for CRYP_RISR register *******************/
+
+/****************** Bits definition for CRYP_MISR register *******************/
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_MORT ((uint32_t)0x00000001) /*!<DAC_MORT channel1 enable */
+#define DAC_CR_BOFF1_MORT ((uint32_t)0x00000002) /*!<DAC_MORT channel1 output buffer disable */
+#define DAC_CR_TEN1_MORT ((uint32_t)0x00000004) /*!<DAC_MORT channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_MORT ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC_MORT channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0_MORT ((uint32_t)0x00000008) /*!<Bit 0 */
+#define DAC_CR_TSEL1_1_MORT ((uint32_t)0x00000010) /*!<Bit 1 */
+#define DAC_CR_TSEL1_2_MORT ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define DAC_CR_WAVE1_MORT ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC_MORT channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0_MORT ((uint32_t)0x00000040) /*!<Bit 0 */
+#define DAC_CR_WAVE1_1_MORT ((uint32_t)0x00000080) /*!<Bit 1 */
+
+#define DAC_CR_MAMP1_MORT ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC_MORT channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0_MORT ((uint32_t)0x00000100) /*!<Bit 0 */
+#define DAC_CR_MAMP1_1_MORT ((uint32_t)0x00000200) /*!<Bit 1 */
+#define DAC_CR_MAMP1_2_MORT ((uint32_t)0x00000400) /*!<Bit 2 */
+#define DAC_CR_MAMP1_3_MORT ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1_MORT ((uint32_t)0x00001000) /*!<DAC_MORT channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_MORT ((uint32_t)0x00002000) /*!<DAC_MORT channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2_MORT ((uint32_t)0x00010000) /*!<DAC_MORT channel2 enable */
+#define DAC_CR_BOFF2_MORT ((uint32_t)0x00020000) /*!<DAC_MORT channel2 output buffer disable */
+#define DAC_CR_TEN2_MORT ((uint32_t)0x00040000) /*!<DAC_MORT channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_MORT ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC_MORT channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0_MORT ((uint32_t)0x00080000) /*!<Bit 0 */
+#define DAC_CR_TSEL2_1_MORT ((uint32_t)0x00100000) /*!<Bit 1 */
+#define DAC_CR_TSEL2_2_MORT ((uint32_t)0x00200000) /*!<Bit 2 */
+
+#define DAC_CR_WAVE2_MORT ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC_MORT channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0_MORT ((uint32_t)0x00400000) /*!<Bit 0 */
+#define DAC_CR_WAVE2_1_MORT ((uint32_t)0x00800000) /*!<Bit 1 */
+
+#define DAC_CR_MAMP2_MORT ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC_MORT channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0_MORT ((uint32_t)0x01000000) /*!<Bit 0 */
+#define DAC_CR_MAMP2_1_MORT ((uint32_t)0x02000000) /*!<Bit 1 */
+#define DAC_CR_MAMP2_2_MORT ((uint32_t)0x04000000) /*!<Bit 2 */
+#define DAC_CR_MAMP2_3_MORT ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2_MORT ((uint32_t)0x10000000) /*!<DAC_MORT channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_MORT ((uint32_t)0x20000000U) /*!<DAC_MORT channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_MORT ((uint8_t)0x01) /*!<DAC_MORT channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_MORT ((uint8_t)0x02) /*!<DAC_MORT channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_MORT ((uint16_t)0x0FFF) /*!<DAC_MORT channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_MORT ((uint16_t)0xFFF0) /*!<DAC_MORT channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_MORT ((uint8_t)0xFF) /*!<DAC_MORT channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_MORT ((uint16_t)0x0FFF) /*!<DAC_MORT channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_MORT ((uint16_t)0xFFF0) /*!<DAC_MORT channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_MORT ((uint8_t)0xFF) /*!<DAC_MORT channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_MORT ((uint32_t)0x00000FFF) /*!<DAC_MORT channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_MORT ((uint32_t)0x0FFF0000) /*!<DAC_MORT channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_MORT ((uint32_t)0x0000FFF0) /*!<DAC_MORT channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_MORT ((uint32_t)0xFFF00000) /*!<DAC_MORT channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_MORT ((uint16_t)0x00FF) /*!<DAC_MORT channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_MORT ((uint16_t)0xFF00) /*!<DAC_MORT channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_MORT ((uint16_t)0x0FFF) /*!<DAC_MORT channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_MORT ((uint16_t)0x0FFF) /*!<DAC_MORT channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_MORT ((uint32_t)0x00002000) /*!<DAC_MORT channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_MORT ((uint32_t)0x20000000) /*!<DAC_MORT channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DCMI_MORT */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+
+
+/******************** Bits definition for DCMI_SR register ******************/
+
+
+/******************** Bits definition for DCMI_RIS register *****************/
+
+/* Legacy defines */
+
+
+/******************** Bits definition for DCMI_IER register *****************/
+
+
+/* Legacy defines */
+
+
+/******************** Bits definition for DCMI_MIS register ****************/
+
+
+/* Legacy defines */
+
+
+/******************** Bits definition for DCMI_ICR register *****************/
+
+
+/* Legacy defines */
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+
+
+/******************** Bits definition for DCMI_DR register ******************/
+
+
+/******************************************************************************/
+/* */
+/* Digital Filter for Sigma Delta Modulators */
+/* */
+/******************************************************************************/
+
+/**************** DFSDM channel configuration registers ********************/
+
+/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
+
+/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
+
+/****************** Bit definition for DFSDM_CHAWSCDR register ***************/
+
+/**************** Bit definition for DFSDM_CHWDATR register *******************/
+
+/**************** Bit definition for DFSDM_CHDATINR register *****************/
+
+/************************ DFSDM module registers ****************************/
+
+/***************** Bit definition for DFSDM_FLTCR1 register *******************/
+
+/******************** Bit definition for DFSDM_FLTCR2 register ***************/
+
+/***************** Bit definition for DFSDM_FLTISR register *******************/
+
+/***************** Bit definition for DFSDM_FLTICR register *******************/
+
+/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
+
+/***************** Bit definition for DFSDM_FLTFCR register *******************/
+
+/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
+
+/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
+
+/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
+
+/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
+
+/*************** Bit definition for DFSDM_FLTAWSR register *******************/
+
+/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
+
+/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
+
+/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
+
+/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL_MORT ((uint32_t)0x0E000000)
+#define DMA_SxCR_CHSEL_0_MORT ((uint32_t)0x02000000)
+#define DMA_SxCR_CHSEL_1_MORT ((uint32_t)0x04000000)
+#define DMA_SxCR_CHSEL_2_MORT ((uint32_t)0x08000000)
+#define DMA_SxCR_MBURST_MORT ((uint32_t)0x01800000)
+#define DMA_SxCR_MBURST_0_MORT ((uint32_t)0x00800000)
+#define DMA_SxCR_MBURST_1_MORT ((uint32_t)0x01000000)
+#define DMA_SxCR_PBURST_MORT ((uint32_t)0x00600000)
+#define DMA_SxCR_PBURST_0_MORT ((uint32_t)0x00200000)
+#define DMA_SxCR_PBURST_1_MORT ((uint32_t)0x00400000)
+#define DMA_SxCR_ACK_MORT ((uint32_t)0x00100000)
+#define DMA_SxCR_CT_MORT ((uint32_t)0x00080000)
+#define DMA_SxCR_DBM_MORT ((uint32_t)0x00040000)
+#define DMA_SxCR_PL_MORT ((uint32_t)0x00030000)
+#define DMA_SxCR_PL_0_MORT ((uint32_t)0x00010000)
+#define DMA_SxCR_PL_1_MORT ((uint32_t)0x00020000)
+#define DMA_SxCR_PINCOS_MORT ((uint32_t)0x00008000)
+#define DMA_SxCR_MSIZE_MORT ((uint32_t)0x00006000)
+#define DMA_SxCR_MSIZE_0_MORT ((uint32_t)0x00002000)
+#define DMA_SxCR_MSIZE_1_MORT ((uint32_t)0x00004000)
+#define DMA_SxCR_PSIZE_MORT ((uint32_t)0x00001800)
+#define DMA_SxCR_PSIZE_0_MORT ((uint32_t)0x00000800)
+#define DMA_SxCR_PSIZE_1_MORT ((uint32_t)0x00001000)
+#define DMA_SxCR_MINC_MORT ((uint32_t)0x00000400)
+#define DMA_SxCR_PINC_MORT ((uint32_t)0x00000200)
+#define DMA_SxCR_CIRC_MORT ((uint32_t)0x00000100)
+#define DMA_SxCR_DIR_MORT ((uint32_t)0x000000C0)
+#define DMA_SxCR_DIR_0_MORT ((uint32_t)0x00000040)
+#define DMA_SxCR_DIR_1_MORT ((uint32_t)0x00000080)
+#define DMA_SxCR_PFCTRL_MORT ((uint32_t)0x00000020)
+#define DMA_SxCR_TCIE_MORT ((uint32_t)0x00000010)
+#define DMA_SxCR_HTIE_MORT ((uint32_t)0x00000008)
+#define DMA_SxCR_TEIE_MORT ((uint32_t)0x00000004)
+#define DMA_SxCR_DMEIE_MORT ((uint32_t)0x00000002)
+#define DMA_SxCR_EN_MORT ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_MORT ((uint32_t)0x0000FFFF)
+#define DMA_SxNDT_0_MORT ((uint32_t)0x00000001)
+#define DMA_SxNDT_1_MORT ((uint32_t)0x00000002)
+#define DMA_SxNDT_2_MORT ((uint32_t)0x00000004)
+#define DMA_SxNDT_3_MORT ((uint32_t)0x00000008)
+#define DMA_SxNDT_4_MORT ((uint32_t)0x00000010)
+#define DMA_SxNDT_5_MORT ((uint32_t)0x00000020)
+#define DMA_SxNDT_6_MORT ((uint32_t)0x00000040)
+#define DMA_SxNDT_7_MORT ((uint32_t)0x00000080)
+#define DMA_SxNDT_8_MORT ((uint32_t)0x00000100)
+#define DMA_SxNDT_9_MORT ((uint32_t)0x00000200)
+#define DMA_SxNDT_10_MORT ((uint32_t)0x00000400)
+#define DMA_SxNDT_11_MORT ((uint32_t)0x00000800)
+#define DMA_SxNDT_12_MORT ((uint32_t)0x00001000)
+#define DMA_SxNDT_13_MORT ((uint32_t)0x00002000)
+#define DMA_SxNDT_14_MORT ((uint32_t)0x00004000)
+#define DMA_SxNDT_15_MORT ((uint32_t)0x00008000)
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_MORT ((uint32_t)0x00000080)
+#define DMA_SxFCR_FS_MORT ((uint32_t)0x00000038)
+#define DMA_SxFCR_FS_0_MORT ((uint32_t)0x00000008)
+#define DMA_SxFCR_FS_1_MORT ((uint32_t)0x00000010)
+#define DMA_SxFCR_FS_2_MORT ((uint32_t)0x00000020)
+#define DMA_SxFCR_DMDIS_MORT ((uint32_t)0x00000004)
+#define DMA_SxFCR_FTH_MORT ((uint32_t)0x00000003)
+#define DMA_SxFCR_FTH_0_MORT ((uint32_t)0x00000001)
+#define DMA_SxFCR_FTH_1_MORT ((uint32_t)0x00000002)
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_MORT ((uint32_t)0x08000000)
+#define DMA_LISR_HTIF3_MORT ((uint32_t)0x04000000)
+#define DMA_LISR_TEIF3_MORT ((uint32_t)0x02000000)
+#define DMA_LISR_DMEIF3_MORT ((uint32_t)0x01000000)
+#define DMA_LISR_FEIF3_MORT ((uint32_t)0x00400000)
+#define DMA_LISR_TCIF2_MORT ((uint32_t)0x00200000)
+#define DMA_LISR_HTIF2_MORT ((uint32_t)0x00100000)
+#define DMA_LISR_TEIF2_MORT ((uint32_t)0x00080000)
+#define DMA_LISR_DMEIF2_MORT ((uint32_t)0x00040000)
+#define DMA_LISR_FEIF2_MORT ((uint32_t)0x00010000)
+#define DMA_LISR_TCIF1_MORT ((uint32_t)0x00000800)
+#define DMA_LISR_HTIF1_MORT ((uint32_t)0x00000400)
+#define DMA_LISR_TEIF1_MORT ((uint32_t)0x00000200)
+#define DMA_LISR_DMEIF1_MORT ((uint32_t)0x00000100)
+#define DMA_LISR_FEIF1_MORT ((uint32_t)0x00000040)
+#define DMA_LISR_TCIF0_MORT ((uint32_t)0x00000020)
+#define DMA_LISR_HTIF0_MORT ((uint32_t)0x00000010)
+#define DMA_LISR_TEIF0_MORT ((uint32_t)0x00000008)
+#define DMA_LISR_DMEIF0_MORT ((uint32_t)0x00000004)
+#define DMA_LISR_FEIF0_MORT ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_MORT ((uint32_t)0x08000000)
+#define DMA_HISR_HTIF7_MORT ((uint32_t)0x04000000)
+#define DMA_HISR_TEIF7_MORT ((uint32_t)0x02000000)
+#define DMA_HISR_DMEIF7_MORT ((uint32_t)0x01000000)
+#define DMA_HISR_FEIF7_MORT ((uint32_t)0x00400000)
+#define DMA_HISR_TCIF6_MORT ((uint32_t)0x00200000)
+#define DMA_HISR_HTIF6_MORT ((uint32_t)0x00100000)
+#define DMA_HISR_TEIF6_MORT ((uint32_t)0x00080000)
+#define DMA_HISR_DMEIF6_MORT ((uint32_t)0x00040000)
+#define DMA_HISR_FEIF6_MORT ((uint32_t)0x00010000)
+#define DMA_HISR_TCIF5_MORT ((uint32_t)0x00000800)
+#define DMA_HISR_HTIF5_MORT ((uint32_t)0x00000400)
+#define DMA_HISR_TEIF5_MORT ((uint32_t)0x00000200)
+#define DMA_HISR_DMEIF5_MORT ((uint32_t)0x00000100)
+#define DMA_HISR_FEIF5_MORT ((uint32_t)0x00000040)
+#define DMA_HISR_TCIF4_MORT ((uint32_t)0x00000020)
+#define DMA_HISR_HTIF4_MORT ((uint32_t)0x00000010)
+#define DMA_HISR_TEIF4_MORT ((uint32_t)0x00000008)
+#define DMA_HISR_DMEIF4_MORT ((uint32_t)0x00000004)
+#define DMA_HISR_FEIF4_MORT ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_MORT ((uint32_t)0x08000000)
+#define DMA_LIFCR_CHTIF3_MORT ((uint32_t)0x04000000)
+#define DMA_LIFCR_CTEIF3_MORT ((uint32_t)0x02000000)
+#define DMA_LIFCR_CDMEIF3_MORT ((uint32_t)0x01000000)
+#define DMA_LIFCR_CFEIF3_MORT ((uint32_t)0x00400000)
+#define DMA_LIFCR_CTCIF2_MORT ((uint32_t)0x00200000)
+#define DMA_LIFCR_CHTIF2_MORT ((uint32_t)0x00100000)
+#define DMA_LIFCR_CTEIF2_MORT ((uint32_t)0x00080000)
+#define DMA_LIFCR_CDMEIF2_MORT ((uint32_t)0x00040000)
+#define DMA_LIFCR_CFEIF2_MORT ((uint32_t)0x00010000)
+#define DMA_LIFCR_CTCIF1_MORT ((uint32_t)0x00000800)
+#define DMA_LIFCR_CHTIF1_MORT ((uint32_t)0x00000400)
+#define DMA_LIFCR_CTEIF1_MORT ((uint32_t)0x00000200)
+#define DMA_LIFCR_CDMEIF1_MORT ((uint32_t)0x00000100)
+#define DMA_LIFCR_CFEIF1_MORT ((uint32_t)0x00000040)
+#define DMA_LIFCR_CTCIF0_MORT ((uint32_t)0x00000020)
+#define DMA_LIFCR_CHTIF0_MORT ((uint32_t)0x00000010)
+#define DMA_LIFCR_CTEIF0_MORT ((uint32_t)0x00000008)
+#define DMA_LIFCR_CDMEIF0_MORT ((uint32_t)0x00000004)
+#define DMA_LIFCR_CFEIF0_MORT ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_MORT ((uint32_t)0x08000000)
+#define DMA_HIFCR_CHTIF7_MORT ((uint32_t)0x04000000)
+#define DMA_HIFCR_CTEIF7_MORT ((uint32_t)0x02000000)
+#define DMA_HIFCR_CDMEIF7_MORT ((uint32_t)0x01000000)
+#define DMA_HIFCR_CFEIF7_MORT ((uint32_t)0x00400000)
+#define DMA_HIFCR_CTCIF6_MORT ((uint32_t)0x00200000)
+#define DMA_HIFCR_CHTIF6_MORT ((uint32_t)0x00100000)
+#define DMA_HIFCR_CTEIF6_MORT ((uint32_t)0x00080000)
+#define DMA_HIFCR_CDMEIF6_MORT ((uint32_t)0x00040000)
+#define DMA_HIFCR_CFEIF6_MORT ((uint32_t)0x00010000)
+#define DMA_HIFCR_CTCIF5_MORT ((uint32_t)0x00000800)
+#define DMA_HIFCR_CHTIF5_MORT ((uint32_t)0x00000400)
+#define DMA_HIFCR_CTEIF5_MORT ((uint32_t)0x00000200)
+#define DMA_HIFCR_CDMEIF5_MORT ((uint32_t)0x00000100)
+#define DMA_HIFCR_CFEIF5_MORT ((uint32_t)0x00000040)
+#define DMA_HIFCR_CTCIF4_MORT ((uint32_t)0x00000020)
+#define DMA_HIFCR_CHTIF4_MORT ((uint32_t)0x00000010)
+#define DMA_HIFCR_CTEIF4_MORT ((uint32_t)0x00000008)
+#define DMA_HIFCR_CDMEIF4_MORT ((uint32_t)0x00000004)
+#define DMA_HIFCR_CFEIF4_MORT ((uint32_t)0x00000001)
+
+/******************************************************************************/
+/* */
+/* AHB Master DMA2D_MORT Controller (DMA2D_MORT) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DMA2D_CR register ******************/
+
+#define DMA2D_CR_START_MORT ((uint32_t)0x00000001) /*!< Start transfer */
+#define DMA2D_CR_SUSP_MORT ((uint32_t)0x00000002) /*!< Suspend transfer */
+#define DMA2D_CR_ABORT_MORT ((uint32_t)0x00000004) /*!< Abort transfer */
+#define DMA2D_CR_TEIE_MORT ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE_MORT ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE_MORT ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE_MORT ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE_MORT ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_MORT ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE_MORT ((uint32_t)0x00030000) /*!< DMA2D_MORT Mode */
+
+/******************** Bit definition for DMA2D_ISR register *****************/
+
+#define DMA2D_ISR_TEIF_MORT ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF_MORT ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF_MORT ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF_MORT ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF_MORT ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_MORT ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_IFCR register ****************/
+
+#define DMA2D_IFCR_CTEIF_MORT ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF_MORT ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF_MORT ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF_MORT ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF_MORT ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_MORT ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF_MORT /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF_MORT /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF_MORT /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF_MORT /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF_MORT /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF_MORT /*!< Clears Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_FGMAR register ***************/
+
+#define DMA2D_FGMAR_MA_MORT ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_FGOR register ****************/
+
+#define DMA2D_FGOR_LO_MORT ((uint32_t)0x00003FFF) /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_BGMAR register ***************/
+
+#define DMA2D_BGMAR_MA_MORT ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGOR register ****************/
+
+#define DMA2D_BGOR_LO_MORT ((uint32_t)0x00003FFF) /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_FGPFCCR register *************/
+
+#define DMA2D_FGPFCCR_CM_MORT ((uint32_t)0x0000000F) /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0_MORT ((uint32_t)0x00000001) /*!< Input color mode CM bit 0 */
+#define DMA2D_FGPFCCR_CM_1_MORT ((uint32_t)0x00000002) /*!< Input color mode CM bit 1 */
+#define DMA2D_FGPFCCR_CM_2_MORT ((uint32_t)0x00000004) /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3_MORT ((uint32_t)0x00000008) /*!< Input color mode CM bit 3 */
+#define DMA2D_FGPFCCR_CCM_MORT ((uint32_t)0x00000010) /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_MORT ((uint32_t)0x00000020) /*!< Start */
+#define DMA2D_FGPFCCR_CS_MORT ((uint32_t)0x0000FF00) /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_MORT ((uint32_t)0x00030000) /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0_MORT ((uint32_t)0x00010000) /*!< Alpha mode AM bit 0 */
+#define DMA2D_FGPFCCR_AM_1_MORT ((uint32_t)0x00020000) /*!< Alpha mode AM bit 1 */
+#define DMA2D_FGPFCCR_ALPHA_MORT ((uint32_t)0xFF000000) /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_FGCOLR register **************/
+
+#define DMA2D_FGCOLR_BLUE_MORT ((uint32_t)0x000000FF) /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN_MORT ((uint32_t)0x0000FF00) /*!< Green Value */
+#define DMA2D_FGCOLR_RED_MORT ((uint32_t)0x00FF0000) /*!< Red Value */
+
+/******************** Bit definition for DMA2D_BGPFCCR register *************/
+
+#define DMA2D_BGPFCCR_CM_MORT ((uint32_t)0x0000000F) /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0_MORT ((uint32_t)0x00000001) /*!< Input color mode CM bit 0 */
+#define DMA2D_BGPFCCR_CM_1_MORT ((uint32_t)0x00000002) /*!< Input color mode CM bit 1 */
+#define DMA2D_BGPFCCR_CM_2_MORT ((uint32_t)0x00000004) /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3_MORT ((uint32_t)0x00000008) /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM_MORT ((uint32_t)0x00000010) /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_MORT ((uint32_t)0x00000020) /*!< Start */
+#define DMA2D_BGPFCCR_CS_MORT ((uint32_t)0x0000FF00) /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_MORT ((uint32_t)0x00030000) /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0_MORT ((uint32_t)0x00010000) /*!< Alpha mode AM bit 0 */
+#define DMA2D_BGPFCCR_AM_1_MORT ((uint32_t)0x00020000) /*!< Alpha mode AM bit 1 */
+#define DMA2D_BGPFCCR_ALPHA_MORT ((uint32_t)0xFF000000) /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_BGCOLR register **************/
+
+#define DMA2D_BGCOLR_BLUE_MORT ((uint32_t)0x000000FF) /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN_MORT ((uint32_t)0x0000FF00) /*!< Green Value */
+#define DMA2D_BGCOLR_RED_MORT ((uint32_t)0x00FF0000) /*!< Red Value */
+
+/******************** Bit definition for DMA2D_FGCMAR register **************/
+
+#define DMA2D_FGCMAR_MA_MORT ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGCMAR register **************/
+
+#define DMA2D_BGCMAR_MA_MORT ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OPFCCR register **************/
+
+#define DMA2D_OPFCCR_CM_MORT ((uint32_t)0x00000007) /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0_MORT ((uint32_t)0x00000001) /*!< Color mode CM bit 0 */
+#define DMA2D_OPFCCR_CM_1_MORT ((uint32_t)0x00000002) /*!< Color mode CM bit 1 */
+#define DMA2D_OPFCCR_CM_2_MORT ((uint32_t)0x00000004) /*!< Color mode CM bit 2 */
+
+/******************** Bit definition for DMA2D_OCOLR register ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1_MORT ((uint32_t)0x000000FF) /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1_MORT ((uint32_t)0x0000FF00) /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_1_MORT ((uint32_t)0x00FF0000) /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2_MORT ((uint32_t)0x0000001F) /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2_MORT ((uint32_t)0x000007E0) /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_2_MORT ((uint32_t)0x0000F800) /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3_MORT ((uint32_t)0x0000001F) /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3_MORT ((uint32_t)0x000003E0) /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_3_MORT ((uint32_t)0x00007C00) /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3_MORT ((uint32_t)0x00008000) /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4_MORT ((uint32_t)0x0000000F) /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4_MORT ((uint32_t)0x000000F0) /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_4_MORT ((uint32_t)0x00000F00) /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4_MORT ((uint32_t)0x0000F000) /*!< Alpha Channel Value */
+
+/******************** Bit definition for DMA2D_OMAR register ****************/
+
+#define DMA2D_OMAR_MA_MORT ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OOR register *****************/
+
+#define DMA2D_OOR_LO_MORT ((uint32_t)0x00003FFF) /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_NLR register *****************/
+
+#define DMA2D_NLR_NL_MORT ((uint32_t)0x0000FFFF) /*!< Number of Lines */
+#define DMA2D_NLR_PL_MORT ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */
+
+/******************** Bit definition for DMA2D_LWR register *****************/
+
+#define DMA2D_LWR_LW_MORT ((uint32_t)0x0000FFFF) /*!< Line Watermark */
+
+/******************** Bit definition for DMA2D_AMTCR register ***************/
+
+#define DMA2D_AMTCR_EN_MORT ((uint32_t)0x00000001) /*!< Enable */
+#define DMA2D_AMTCR_DT_MORT ((uint32_t)0x0000FF00) /*!< Dead Time */
+
+
+
+/******************** Bit definition for DMA2D_FGCLUT register **************/
+
+/******************** Bit definition for DMA2D_BGCLUT register **************/
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_MORT ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_MORT ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_MORT ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_MORT ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_MORT ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_MORT ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_MORT ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_MORT ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_MORT ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_MORT ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_MORT ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_MORT ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_MORT ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_MORT ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_MORT ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_MORT ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_MORT ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_MORT ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_MORT ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_MORT ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR23_MORT ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_MORT ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_MORT ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_MORT ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_MORT ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_MORT ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_MORT ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_MORT ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_MORT ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_MORT ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_MORT ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_MORT ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_MORT ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_MORT ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_MORT ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_MORT ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_MORT ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_MORT ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_MORT ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_MORT ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_MORT ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR23_MORT ((uint32_t)0x00800000) /*!< Event Mask on line 19 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_MORT ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_MORT ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_MORT ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_MORT ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_MORT ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_MORT ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_MORT ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_MORT ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_MORT ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_MORT ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_MORT ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_MORT ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_MORT ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_MORT ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_MORT ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_MORT ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_MORT ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_MORT ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_MORT ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_MORT ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR23_MORT ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_MORT ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_MORT ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_MORT ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_MORT ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_MORT ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_MORT ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_MORT ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_MORT ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_MORT ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_MORT ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_MORT ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_MORT ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_MORT ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_MORT ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_MORT ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_MORT ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_MORT ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_MORT ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_MORT ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_MORT ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR23_MORT ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_MORT ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_MORT ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_MORT ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_MORT ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_MORT ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_MORT ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_MORT ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_MORT ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_MORT ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_MORT ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_MORT ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_MORT ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_MORT ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_MORT ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_MORT ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_MORT ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_MORT ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_MORT ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_MORT ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_MORT ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER23_MORT ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_MORT ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_MORT ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_MORT ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_MORT ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_MORT ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_MORT ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_MORT ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_MORT ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_MORT ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_MORT ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_MORT ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_MORT ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_MORT ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_MORT ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_MORT ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_MORT ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_MORT ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_MORT ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_MORT ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_MORT ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR23_MORT ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
+
+/******************************************************************************/
+/* */
+/* FLASH_MORT */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+
+/******************* Bits definition for FLASH_SR register ******************/
+
+/******************* Bits definition for FLASH_CR register ******************/
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FSMC_BCR1 register *******************/
+
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+
+
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+
+
+/****************** Bit definition for FSMC_PCR2 register *******************/
+
+
+/****************** Bit definition for FSMC_PCR3 register *******************/
+
+
+/****************** Bit definition for FSMC_PCR4 register *******************/
+
+
+/******************* Bit definition for FSMC_SR2 register *******************/
+
+
+/******************* Bit definition for FSMC_SR3 register *******************/
+
+
+/******************* Bit definition for FSMC_SR4 register *******************/
+
+/****************** Bit definition for FSMC_PMEM2 register ******************/
+
+
+/****************** Bit definition for FSMC_PMEM3 register ******************/
+
+
+/****************** Bit definition for FSMC_PMEM4 register ******************/
+
+
+/****************** Bit definition for FSMC_PATT2 register ******************/
+
+
+/****************** Bit definition for FSMC_PATT3 register ******************/
+
+
+/****************** Bit definition for FSMC_PATT4 register ******************/
+
+/****************** Bit definition for FSMC_PIO4 register *******************/
+
+
+/****************** Bit definition for FSMC_ECCR2 register ******************/
+
+
+/****************** Bit definition for FSMC_ECCR3 register ******************/
+
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+
+/****************** Bit definition for FMC_PCR2 register *******************/
+
+/****************** Bit definition for FMC_PCR3 register *******************/
+
+/****************** Bit definition for FMC_PCR4 register *******************/
+
+/******************* Bit definition for FMC_SR2 register *******************/
+
+/******************* Bit definition for FMC_SR3 register *******************/
+
+/******************* Bit definition for FMC_SR4 register *******************/
+
+/****************** Bit definition for FMC_PMEM2 register ******************/
+
+
+/****************** Bit definition for FMC_PMEM3 register ******************/
+
+/****************** Bit definition for FMC_PMEM4 register ******************/
+
+/****************** Bit definition for FMC_PATT2 register ******************/
+
+/****************** Bit definition for FMC_PATT3 register ******************/
+
+/****************** Bit definition for FMC_PATT4 register ******************/
+
+/****************** Bit definition for FMC_PIO4 register *******************/
+
+/****************** Bit definition for FMC_ECCR2 register ******************/
+
+/****************** Bit definition for FMC_ECCR3 register ******************/
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+
+/****************** Bit definition for FMC_SDSR register ******************/
+
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0_MORT ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0_MORT ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1_MORT ((uint32_t)0x00000002)
+
+#define GPIO_MODER_MODER1_MORT ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0_MORT ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1_MORT ((uint32_t)0x00000008)
+
+#define GPIO_MODER_MODER2_MORT ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0_MORT ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1_MORT ((uint32_t)0x00000020)
+
+#define GPIO_MODER_MODER3_MORT ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0_MORT ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1_MORT ((uint32_t)0x00000080)
+
+#define GPIO_MODER_MODER4_MORT ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0_MORT ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1_MORT ((uint32_t)0x00000200)
+
+#define GPIO_MODER_MODER5_MORT ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0_MORT ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1_MORT ((uint32_t)0x00000800)
+
+#define GPIO_MODER_MODER6_MORT ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0_MORT ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1_MORT ((uint32_t)0x00002000)
+
+#define GPIO_MODER_MODER7_MORT ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0_MORT ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1_MORT ((uint32_t)0x00008000)
+
+#define GPIO_MODER_MODER8_MORT ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0_MORT ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1_MORT ((uint32_t)0x00020000)
+
+#define GPIO_MODER_MODER9_MORT ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0_MORT ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1_MORT ((uint32_t)0x00080000)
+
+#define GPIO_MODER_MODER10_MORT ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0_MORT ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1_MORT ((uint32_t)0x00200000)
+
+#define GPIO_MODER_MODER11_MORT ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0_MORT ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1_MORT ((uint32_t)0x00800000)
+
+#define GPIO_MODER_MODER12_MORT ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0_MORT ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1_MORT ((uint32_t)0x02000000)
+
+#define GPIO_MODER_MODER13_MORT ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0_MORT ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1_MORT ((uint32_t)0x08000000)
+
+#define GPIO_MODER_MODER14_MORT ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0_MORT ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1_MORT ((uint32_t)0x20000000)
+
+#define GPIO_MODER_MODER15_MORT ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0_MORT ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1_MORT ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0_MORT ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1_MORT ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2_MORT ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3_MORT ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4_MORT ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5_MORT ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6_MORT ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7_MORT ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8_MORT ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9_MORT ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10_MORT ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11_MORT ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12_MORT ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13_MORT ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14_MORT ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15_MORT ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0_MORT ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0_MORT ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1_MORT ((uint32_t)0x00000002)
+
+#define GPIO_OSPEEDER_OSPEEDR1_MORT ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0_MORT ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1_MORT ((uint32_t)0x00000008)
+
+#define GPIO_OSPEEDER_OSPEEDR2_MORT ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0_MORT ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1_MORT ((uint32_t)0x00000020)
+
+#define GPIO_OSPEEDER_OSPEEDR3_MORT ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0_MORT ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1_MORT ((uint32_t)0x00000080)
+
+#define GPIO_OSPEEDER_OSPEEDR4_MORT ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0_MORT ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1_MORT ((uint32_t)0x00000200)
+
+#define GPIO_OSPEEDER_OSPEEDR5_MORT ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0_MORT ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1_MORT ((uint32_t)0x00000800)
+
+#define GPIO_OSPEEDER_OSPEEDR6_MORT ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0_MORT ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1_MORT ((uint32_t)0x00002000)
+
+#define GPIO_OSPEEDER_OSPEEDR7_MORT ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0_MORT ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1_MORT ((uint32_t)0x00008000)
+
+#define GPIO_OSPEEDER_OSPEEDR8_MORT ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0_MORT ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1_MORT ((uint32_t)0x00020000)
+
+#define GPIO_OSPEEDER_OSPEEDR9_MORT ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0_MORT ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1_MORT ((uint32_t)0x00080000)
+
+#define GPIO_OSPEEDER_OSPEEDR10_MORT ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0_MORT ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1_MORT ((uint32_t)0x00200000)
+
+#define GPIO_OSPEEDER_OSPEEDR11_MORT ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0_MORT ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1_MORT ((uint32_t)0x00800000)
+
+#define GPIO_OSPEEDER_OSPEEDR12_MORT ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0_MORT ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1_MORT ((uint32_t)0x02000000)
+
+#define GPIO_OSPEEDER_OSPEEDR13_MORT ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0_MORT ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1_MORT ((uint32_t)0x08000000)
+
+#define GPIO_OSPEEDER_OSPEEDR14_MORT ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0_MORT ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1_MORT ((uint32_t)0x20000000)
+
+#define GPIO_OSPEEDER_OSPEEDR15_MORT ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0_MORT ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1_MORT ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0_MORT ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0_MORT ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1_MORT ((uint32_t)0x00000002)
+
+#define GPIO_PUPDR_PUPDR1_MORT ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0_MORT ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1_MORT ((uint32_t)0x00000008)
+
+#define GPIO_PUPDR_PUPDR2_MORT ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0_MORT ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1_MORT ((uint32_t)0x00000020)
+
+#define GPIO_PUPDR_PUPDR3_MORT ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0_MORT ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1_MORT ((uint32_t)0x00000080)
+
+#define GPIO_PUPDR_PUPDR4_MORT ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0_MORT ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1_MORT ((uint32_t)0x00000200)
+
+#define GPIO_PUPDR_PUPDR5_MORT ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0_MORT ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1_MORT ((uint32_t)0x00000800)
+
+#define GPIO_PUPDR_PUPDR6_MORT ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0_MORT ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1_MORT ((uint32_t)0x00002000)
+
+#define GPIO_PUPDR_PUPDR7_MORT ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0_MORT ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1_MORT ((uint32_t)0x00008000)
+
+#define GPIO_PUPDR_PUPDR8_MORT ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0_MORT ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1_MORT ((uint32_t)0x00020000)
+
+#define GPIO_PUPDR_PUPDR9_MORT ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0_MORT ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1_MORT ((uint32_t)0x00080000)
+
+#define GPIO_PUPDR_PUPDR10_MORT ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0_MORT ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1_MORT ((uint32_t)0x00200000)
+
+#define GPIO_PUPDR_PUPDR11_MORT ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0_MORT ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1_MORT ((uint32_t)0x00800000)
+
+#define GPIO_PUPDR_PUPDR12_MORT ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0_MORT ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1_MORT ((uint32_t)0x02000000)
+
+#define GPIO_PUPDR_PUPDR13_MORT ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0_MORT ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1_MORT ((uint32_t)0x08000000)
+
+#define GPIO_PUPDR_PUPDR14_MORT ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0_MORT ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1_MORT ((uint32_t)0x20000000)
+
+#define GPIO_PUPDR_PUPDR15_MORT ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0_MORT ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1_MORT ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0_MORT ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1_MORT ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2_MORT ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3_MORT ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4_MORT ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5_MORT ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6_MORT ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7_MORT ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8_MORT ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9_MORT ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10_MORT ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11_MORT ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12_MORT ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13_MORT ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14_MORT ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15_MORT ((uint32_t)0x00008000)
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0_MORT GPIO_IDR_IDR_0_MORT
+#define GPIO_OTYPER_IDR_1_MORT GPIO_IDR_IDR_1_MORT
+#define GPIO_OTYPER_IDR_2_MORT GPIO_IDR_IDR_2_MORT
+#define GPIO_OTYPER_IDR_3_MORT GPIO_IDR_IDR_3_MORT
+#define GPIO_OTYPER_IDR_4_MORT GPIO_IDR_IDR_4_MORT
+#define GPIO_OTYPER_IDR_5_MORT GPIO_IDR_IDR_5_MORT
+#define GPIO_OTYPER_IDR_6_MORT GPIO_IDR_IDR_6_MORT
+#define GPIO_OTYPER_IDR_7_MORT GPIO_IDR_IDR_7_MORT
+#define GPIO_OTYPER_IDR_8_MORT GPIO_IDR_IDR_8_MORT
+#define GPIO_OTYPER_IDR_9_MORT GPIO_IDR_IDR_9_MORT
+#define GPIO_OTYPER_IDR_10_MORT GPIO_IDR_IDR_10_MORT
+#define GPIO_OTYPER_IDR_11_MORT GPIO_IDR_IDR_11_MORT
+#define GPIO_OTYPER_IDR_12_MORT GPIO_IDR_IDR_12_MORT
+#define GPIO_OTYPER_IDR_13_MORT GPIO_IDR_IDR_13_MORT
+#define GPIO_OTYPER_IDR_14_MORT GPIO_IDR_IDR_14_MORT
+#define GPIO_OTYPER_IDR_15_MORT GPIO_IDR_IDR_15_MORT
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0_MORT ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1_MORT ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2_MORT ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3_MORT ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4_MORT ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5_MORT ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6_MORT ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7_MORT ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8_MORT ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9_MORT ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10_MORT ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11_MORT ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12_MORT ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13_MORT ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14_MORT ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15_MORT ((uint32_t)0x00008000)
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0_MORT
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1_MORT
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2_MORT
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3_MORT
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4_MORT
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5_MORT
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6_MORT
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7_MORT
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8_MORT
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9_MORT
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10_MORT
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11_MORT
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12_MORT
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13_MORT
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14_MORT
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15_MORT
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0_MORT ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1_MORT ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2_MORT ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3_MORT ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4_MORT ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5_MORT ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6_MORT ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7_MORT ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8_MORT ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9_MORT ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10_MORT ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11_MORT ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12_MORT ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13_MORT ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14_MORT ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15_MORT ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0_MORT ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1_MORT ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2_MORT ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3_MORT ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4_MORT ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5_MORT ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6_MORT ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7_MORT ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8_MORT ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9_MORT ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10_MORT ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11_MORT ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12_MORT ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13_MORT ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14_MORT ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15_MORT ((uint32_t)0x80000000)
+
+/******************************************************************************/
+/* */
+/* HASH_MORT */
+/* */
+/******************************************************************************/
+/****************** Bits definition for HASH_CR register ********************/
+
+
+/****************** Bits definition for HASH_STR register *******************/
+
+
+/****************** Bits definition for HASH_IMR register *******************/
+
+
+/****************** Bits definition for HASH_SR register ********************/
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+
+/******************* Bit definition for I2C_CR2 register ********************/
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+
+/******************** Bit definition for I2C_DR register ********************/
+
+/******************* Bit definition for I2C_SR1 register ********************/
+
+/******************* Bit definition for I2C_SR2 register ********************/
+
+/******************* Bit definition for I2C_CCR register ********************/
+
+/****************** Bit definition for I2C_TRISE register *******************/
+
+/****************** Bit definition for I2C_FLTR register *******************/
+
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT)
+/******************************************************************************/
+/* */
+/* Fast-mode Plus Inter-integrated circuit (FMPI2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+
+/****************** Bit definition for I2C_CR2 register ********************/
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+
+/******************* Bit definition for I2C_TIMINGR register *****************/
+
+/******************* Bit definition for I2C_TIMEOUTR register *****************/
+
+/****************** Bit definition for I2C_ISR register *********************/
+
+/****************** Bit definition for I2C_ICR register *********************/
+
+/****************** Bit definition for I2C_PECR register ********************/
+
+/****************** Bit definition for I2C_RXDR register *********************/
+
+/****************** Bit definition for I2C_TXDR register *********************/
+
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+
+/******************* Bit definition for IWDG_PR register ********************/
+
+/******************* Bit definition for IWDG_RLR register *******************/
+
+/******************* Bit definition for IWDG_SR register ********************/
+
+/******************************************************************************/
+/* */
+/* LCD-TFT Display Controller (LTDC_MORT) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for LTDC_SSCR register *****************/
+
+
+/******************** Bit definition for LTDC_BPCR register *****************/
+
+
+/******************** Bit definition for LTDC_AWCR register *****************/
+
+
+/******************** Bit definition for LTDC_TWCR register *****************/
+
+
+/******************** Bit definition for LTDC_GCR register ******************/
+
+
+/* Legacy defines */
+
+/******************** Bit definition for LTDC_SRCR register *****************/
+
+
+/******************** Bit definition for LTDC_BCCR register *****************/
+
+
+/******************** Bit definition for LTDC_IER register ******************/
+
+
+/******************** Bit definition for LTDC_ISR register ******************/
+
+
+/******************** Bit definition for LTDC_ICR register ******************/
+
+
+/******************** Bit definition for LTDC_LIPCR register ****************/
+
+
+/******************** Bit definition for LTDC_CPSR register *****************/
+
+
+/******************** Bit definition for LTDC_CDSR register *****************/
+
+
+/******************** Bit definition for LTDC_LxCR register *****************/
+
+
+/******************** Bit definition for LTDC_LxWHPCR register **************/
+
+
+/******************** Bit definition for LTDC_LxWVPCR register **************/
+
+
+/******************** Bit definition for LTDC_LxCKCR register ***************/
+
+
+/******************** Bit definition for LTDC_LxPFCR register ***************/
+
+
+/******************** Bit definition for LTDC_LxCACR register ***************/
+
+
+/******************** Bit definition for LTDC_LxDCCR register ***************/
+
+
+/******************** Bit definition for LTDC_LxBFCR register ***************/
+
+
+/******************** Bit definition for LTDC_LxCFBAR register **************/
+
+
+/******************** Bit definition for LTDC_LxCFBLR register **************/
+
+
+/******************** Bit definition for LTDC_LxCFBLNR register *************/
+
+
+/******************** Bit definition for LTDC_LxCLUTWR register *************/
+
+
+#if defined(STM32F469_479xx)
+/******************************************************************************/
+/* */
+/* DSI_MORT */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DSI_VR register *****************/
+
+
+/******************* Bit definition for DSI_CR register *****************/
+
+
+/******************* Bit definition for DSI_CCR register ****************/
+
+
+/******************* Bit definition for DSI_LVCIDR register *************/
+
+
+/******************* Bit definition for DSI_LCOLCR register *************/
+
+
+
+/******************* Bit definition for DSI_LPCR register ***************/
+
+
+/******************* Bit definition for DSI_LPMCR register **************/
+
+
+/******************* Bit definition for DSI_PCR register ****************/
+
+
+/******************* Bit definition for DSI_GVCIDR register *************/
+
+
+/******************* Bit definition for DSI_MCR register ****************/
+
+
+/******************* Bit definition for DSI_VMCR register ***************/
+
+
+/******************* Bit definition for DSI_VPCR register ***************/
+
+
+/******************* Bit definition for DSI_VCCR register ***************/
+
+
+/******************* Bit definition for DSI_VNPCR register **************/
+
+
+/******************* Bit definition for DSI_VHSACR register *************/
+
+
+/******************* Bit definition for DSI_VHBPCR register *************/
+
+
+/******************* Bit definition for DSI_VLCR register ***************/
+
+/******************* Bit definition for DSI_VVSACR register *************/
+
+
+/******************* Bit definition for DSI_VVBPCR register *************/
+
+
+/******************* Bit definition for DSI_VVFPCR register *************/
+
+
+/******************* Bit definition for DSI_VVACR register **************/
+
+
+/******************* Bit definition for DSI_LCCR register ***************/
+
+
+/******************* Bit definition for DSI_CMCR register ***************/
+
+
+/******************* Bit definition for DSI_GHCR register ***************/
+
+
+/******************* Bit definition for DSI_GPDR register ***************/
+
+
+/******************* Bit definition for DSI_GPSR register ***************/
+
+/******************* Bit definition for DSI_TCCR0 register **************/
+
+
+/******************* Bit definition for DSI_TCCR1 register **************/
+
+
+/******************* Bit definition for DSI_TCCR2 register **************/
+
+
+/******************* Bit definition for DSI_TCCR3 register **************/
+
+
+/******************* Bit definition for DSI_TCCR4 register **************/
+
+
+/******************* Bit definition for DSI_TCCR5 register **************/
+
+
+/******************* Bit definition for DSI_TDCR register ***************/
+
+
+/******************* Bit definition for DSI_CLCR register ***************/
+
+
+/******************* Bit definition for DSI_CLTCR register **************/
+
+
+/******************* Bit definition for DSI_DLTCR register **************/
+
+
+/******************* Bit definition for DSI_PCTLR register **************/
+
+
+/******************* Bit definition for DSI_PCONFR register *************/
+
+
+/******************* Bit definition for DSI_PUCR register ***************/
+
+
+/******************* Bit definition for DSI_PTTCR register **************/
+
+
+/******************* Bit definition for DSI_PSR register ****************/
+
+
+/******************* Bit definition for DSI_ISR0 register ***************/
+
+/******************* Bit definition for DSI_ISR1 register ***************/
+
+
+/******************* Bit definition for DSI_IER0 register ***************/
+
+
+/******************* Bit definition for DSI_IER1 register ***************/
+
+
+/******************* Bit definition for DSI_FIR0 register ***************/
+
+
+/******************* Bit definition for DSI_FIR1 register ***************/
+
+
+/******************* Bit definition for DSI_VSCR register ***************/
+
+
+/******************* Bit definition for DSI_LCVCIDR register ************/
+
+
+/******************* Bit definition for DSI_LCCCR register **************/
+
+
+/******************* Bit definition for DSI_LPMCCR register *************/
+
+/******************* Bit definition for DSI_VMCCR register **************/
+
+
+/******************* Bit definition for DSI_VPCCR register **************/
+
+
+/******************* Bit definition for DSI_VCCCR register **************/
+
+
+/******************* Bit definition for DSI_VNPCCR register *************/
+
+
+/******************* Bit definition for DSI_VHSACCR register ************/
+
+
+/******************* Bit definition for DSI_VHBPCCR register ************/
+
+
+/******************* Bit definition for DSI_VLCCR register **************/
+
+
+/******************* Bit definition for DSI_VVSACCR register ***************/
+
+
+/******************* Bit definition for DSI_VVBPCCR register ************/
+
+
+/******************* Bit definition for DSI_VVFPCCR register ************/
+
+
+/******************* Bit definition for DSI_VVACCR register *************/
+
+
+/******************* Bit definition for DSI_TDCCR register **************/
+
+
+/******************* Bit definition for DSI_WCFGR register ***************/
+
+/******************* Bit definition for DSI_WCR register *****************/
+
+
+/******************* Bit definition for DSI_WIER register ****************/
+
+
+/******************* Bit definition for DSI_WISR register ****************/
+
+/******************* Bit definition for DSI_WIFCR register ***************/
+
+/******************* Bit definition for DSI_WPCR0 register ***************/
+
+/******************* Bit definition for DSI_WPCR1 register ***************/
+
+
+/******************* Bit definition for DSI_WPCR2 register ***************/
+
+
+/******************* Bit definition for DSI_WPCR3 register ***************/
+
+
+/******************* Bit definition for DSI_WPCR4 register ***************/
+
+
+/******************* Bit definition for DSI_WRPCR register ***************/
+
+#endif /* STM32F469_479xx */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+
+/*!< PVD level configuration */
+
+/* Legacy define */
+
+/******************* Bit definition for PWR_CSR register ********************/
+
+/* Legacy define */
+
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+/******************************************************************************/
+/* */
+/* QUADSPI_MORT */
+/* */
+/******************************************************************************/
+/***************** Bit definition for QUADSPI_CR register *******************/
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+
+/****************** Bit definition for QUADSPI_AR register *******************/
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_MORT ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY_MORT ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM_MORT ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0_MORT ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1_MORT ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2_MORT ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3_MORT ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4_MORT ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL_MORT ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0_MORT ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1_MORT ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2_MORT ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3_MORT ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4_MORT ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5_MORT ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6_MORT ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7_MORT ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON_MORT ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY_MORT ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP_MORT ((uint32_t)0x00040000)
+#define RCC_CR_CSSON_MORT ((uint32_t)0x00080000)
+#define RCC_CR_PLLON_MORT ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY_MORT ((uint32_t)0x02000000)
+#define RCC_CR_PLLI2SON_MORT ((uint32_t)0x04000000)
+#define RCC_CR_PLLI2SRDY_MORT ((uint32_t)0x08000000)
+#define RCC_CR_PLLSAION_MORT ((uint32_t)0x10000000)
+#define RCC_CR_PLLSAIRDY_MORT ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM_MORT ((uint32_t)0x0000003F)
+#define RCC_PLLCFGR_PLLM_0_MORT ((uint32_t)0x00000001)
+#define RCC_PLLCFGR_PLLM_1_MORT ((uint32_t)0x00000002)
+#define RCC_PLLCFGR_PLLM_2_MORT ((uint32_t)0x00000004)
+#define RCC_PLLCFGR_PLLM_3_MORT ((uint32_t)0x00000008)
+#define RCC_PLLCFGR_PLLM_4_MORT ((uint32_t)0x00000010)
+#define RCC_PLLCFGR_PLLM_5_MORT ((uint32_t)0x00000020)
+
+#define RCC_PLLCFGR_PLLN_MORT ((uint32_t)0x00007FC0)
+#define RCC_PLLCFGR_PLLN_0_MORT ((uint32_t)0x00000040)
+#define RCC_PLLCFGR_PLLN_1_MORT ((uint32_t)0x00000080)
+#define RCC_PLLCFGR_PLLN_2_MORT ((uint32_t)0x00000100)
+#define RCC_PLLCFGR_PLLN_3_MORT ((uint32_t)0x00000200)
+#define RCC_PLLCFGR_PLLN_4_MORT ((uint32_t)0x00000400)
+#define RCC_PLLCFGR_PLLN_5_MORT ((uint32_t)0x00000800)
+#define RCC_PLLCFGR_PLLN_6_MORT ((uint32_t)0x00001000)
+#define RCC_PLLCFGR_PLLN_7_MORT ((uint32_t)0x00002000)
+#define RCC_PLLCFGR_PLLN_8_MORT ((uint32_t)0x00004000)
+
+#define RCC_PLLCFGR_PLLP_MORT ((uint32_t)0x00030000)
+#define RCC_PLLCFGR_PLLP_0_MORT ((uint32_t)0x00010000)
+#define RCC_PLLCFGR_PLLP_1_MORT ((uint32_t)0x00020000)
+
+#define RCC_PLLCFGR_PLLSRC_MORT ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSE_MORT ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSI_MORT ((uint32_t)0x00000000)
+
+#define RCC_PLLCFGR_PLLQ_MORT ((uint32_t)0x0F000000)
+#define RCC_PLLCFGR_PLLQ_0_MORT ((uint32_t)0x01000000)
+#define RCC_PLLCFGR_PLLQ_1_MORT ((uint32_t)0x02000000)
+#define RCC_PLLCFGR_PLLQ_2_MORT ((uint32_t)0x04000000)
+#define RCC_PLLCFGR_PLLQ_3_MORT ((uint32_t)0x08000000)
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+#define RCC_PLLCFGR_PLLR_MORT ((uint32_t)0x70000000)
+#define RCC_PLLCFGR_PLLR_0_MORT ((uint32_t)0x10000000)
+#define RCC_PLLCFGR_PLLR_1_MORT ((uint32_t)0x20000000)
+#define RCC_PLLCFGR_PLLR_2_MORT ((uint32_t)0x40000000)
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_MORT ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0_MORT ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1_MORT ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI_MORT ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE_MORT ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL_MORT ((uint32_t)0x00000002) /*!< PLL/PLLP selected as system clock */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+#define RCC_CFGR_SW_PLLR_MORT ((uint32_t)0x00000003) /*!< PLL/PLLR selected as system clock */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_MORT ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0_MORT ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1_MORT ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI_MORT ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE_MORT ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL_MORT ((uint32_t)0x00000008) /*!< PLL/PLLP used as system clock */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F469_479xx) || defined(STM32F446xx_MORT)
+#define RCC_CFGR_SWS_PLLR_MORT ((uint32_t)0x0000000C) /*!< PLL/PLLR used as system clock */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_MORT ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0_MORT ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1_MORT ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2_MORT ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3_MORT ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1_MORT ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2_MORT ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4_MORT ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8_MORT ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16_MORT ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64_MORT ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128_MORT ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256_MORT ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512_MORT ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+#if defined(STM32F410xx)
+/*!< MCO1EN configuration */
+
+#endif /* STM32F410xx */
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_MORT ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0_MORT ((uint32_t)0x00000400) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1_MORT ((uint32_t)0x00000800) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2_MORT ((uint32_t)0x00001000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1_MORT ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2_MORT ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4_MORT ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8_MORT ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16_MORT ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_MORT ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0_MORT ((uint32_t)0x00002000) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1_MORT ((uint32_t)0x00004000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2_MORT ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1_MORT ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2_MORT ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4_MORT ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8_MORT ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16_MORT ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_MORT ((uint32_t)0x001F0000)
+#define RCC_CFGR_RTCPRE_0_MORT ((uint32_t)0x00010000)
+#define RCC_CFGR_RTCPRE_1_MORT ((uint32_t)0x00020000)
+#define RCC_CFGR_RTCPRE_2_MORT ((uint32_t)0x00040000)
+#define RCC_CFGR_RTCPRE_3_MORT ((uint32_t)0x00080000)
+#define RCC_CFGR_RTCPRE_4_MORT ((uint32_t)0x00100000)
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_MORT ((uint32_t)0x00600000)
+#define RCC_CFGR_MCO1_0_MORT ((uint32_t)0x00200000)
+#define RCC_CFGR_MCO1_1_MORT ((uint32_t)0x00400000)
+
+#define RCC_CFGR_I2SSRC_MORT ((uint32_t)0x00800000)
+
+#define RCC_CFGR_MCO1PRE_MORT ((uint32_t)0x07000000)
+#define RCC_CFGR_MCO1PRE_0_MORT ((uint32_t)0x01000000)
+#define RCC_CFGR_MCO1PRE_1_MORT ((uint32_t)0x02000000)
+#define RCC_CFGR_MCO1PRE_2_MORT ((uint32_t)0x04000000)
+
+#define RCC_CFGR_MCO2PRE_MORT ((uint32_t)0x38000000)
+#define RCC_CFGR_MCO2PRE_0_MORT ((uint32_t)0x08000000)
+#define RCC_CFGR_MCO2PRE_1_MORT ((uint32_t)0x10000000)
+#define RCC_CFGR_MCO2PRE_2_MORT ((uint32_t)0x20000000)
+
+#define RCC_CFGR_MCO2_MORT ((uint32_t)0xC0000000)
+#define RCC_CFGR_MCO2_0_MORT ((uint32_t)0x40000000)
+#define RCC_CFGR_MCO2_1_MORT ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF_MORT ((uint32_t)0x00000001)
+#define RCC_CIR_LSERDYF_MORT ((uint32_t)0x00000002)
+#define RCC_CIR_HSIRDYF_MORT ((uint32_t)0x00000004)
+#define RCC_CIR_HSERDYF_MORT ((uint32_t)0x00000008)
+#define RCC_CIR_PLLRDYF_MORT ((uint32_t)0x00000010)
+#define RCC_CIR_PLLI2SRDYF_MORT ((uint32_t)0x00000020)
+#define RCC_CIR_PLLSAIRDYF_MORT ((uint32_t)0x00000040)
+#define RCC_CIR_CSSF_MORT ((uint32_t)0x00000080)
+#define RCC_CIR_LSIRDYIE_MORT ((uint32_t)0x00000100)
+#define RCC_CIR_LSERDYIE_MORT ((uint32_t)0x00000200)
+#define RCC_CIR_HSIRDYIE_MORT ((uint32_t)0x00000400)
+#define RCC_CIR_HSERDYIE_MORT ((uint32_t)0x00000800)
+#define RCC_CIR_PLLRDYIE_MORT ((uint32_t)0x00001000)
+#define RCC_CIR_PLLI2SRDYIE_MORT ((uint32_t)0x00002000)
+#define RCC_CIR_PLLSAIRDYIE_MORT ((uint32_t)0x00004000)
+#define RCC_CIR_LSIRDYC_MORT ((uint32_t)0x00010000)
+#define RCC_CIR_LSERDYC_MORT ((uint32_t)0x00020000)
+#define RCC_CIR_HSIRDYC_MORT ((uint32_t)0x00040000)
+#define RCC_CIR_HSERDYC_MORT ((uint32_t)0x00080000)
+#define RCC_CIR_PLLRDYC_MORT ((uint32_t)0x00100000)
+#define RCC_CIR_PLLI2SRDYC_MORT ((uint32_t)0x00200000)
+#define RCC_CIR_PLLSAIRDYC_MORT ((uint32_t)0x00400000)
+#define RCC_CIR_CSSC_MORT ((uint32_t)0x00800000)
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST_MORT ((uint32_t)0x00000001)
+#define RCC_AHB1RSTR_GPIOBRST_MORT ((uint32_t)0x00000002)
+#define RCC_AHB1RSTR_GPIOCRST_MORT ((uint32_t)0x00000004)
+#define RCC_AHB1RSTR_GPIODRST_MORT ((uint32_t)0x00000008)
+#define RCC_AHB1RSTR_GPIOERST_MORT ((uint32_t)0x00000010)
+#define RCC_AHB1RSTR_GPIOFRST_MORT ((uint32_t)0x00000020)
+#define RCC_AHB1RSTR_GPIOGRST_MORT ((uint32_t)0x00000040)
+#define RCC_AHB1RSTR_GPIOHRST_MORT ((uint32_t)0x00000080)
+#define RCC_AHB1RSTR_GPIOIRST_MORT ((uint32_t)0x00000100)
+#define RCC_AHB1RSTR_GPIOJRST_MORT ((uint32_t)0x00000200)
+#define RCC_AHB1RSTR_GPIOKRST_MORT ((uint32_t)0x00000400)
+#define RCC_AHB1RSTR_CRCRST_MORT ((uint32_t)0x00001000)
+#define RCC_AHB1RSTR_DMA1RST_MORT ((uint32_t)0x00200000)
+#define RCC_AHB1RSTR_DMA2RST_MORT ((uint32_t)0x00400000)
+#define RCC_AHB1RSTR_DMA2DRST_MORT ((uint32_t)0x00800000)
+#define RCC_AHB1RSTR_ETHMACRST_MORT ((uint32_t)0x02000000)
+#define RCC_AHB1RSTR_OTGHRST_MORT ((uint32_t)0x10000000)
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST_MORT ((uint32_t)0x00000001)
+#define RCC_AHB2RSTR_CRYPRST_MORT ((uint32_t)0x00000010)
+#define RCC_AHB2RSTR_HASHRST_MORT ((uint32_t)0x00000020)
+ /* maintained for legacy purpose */
+#define RCC_AHB2RSTR_HSAHRST_MORT RCC_AHB2RSTR_HASHRST_MORT
+#define RCC_AHB2RSTR_RNGRST_MORT ((uint32_t)0x00000040)
+#define RCC_AHB2RSTR_OTGFSRST_MORT ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+#define RCC_AHB3RSTR_FMCRST_MORT ((uint32_t)0x00000001)
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+#define RCC_AHB3RSTR_QSPIRST_MORT ((uint32_t)0x00000002)
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST_MORT ((uint32_t)0x00000001)
+#define RCC_APB1RSTR_TIM3RST_MORT ((uint32_t)0x00000002)
+#define RCC_APB1RSTR_TIM4RST_MORT ((uint32_t)0x00000004)
+#define RCC_APB1RSTR_TIM5RST_MORT ((uint32_t)0x00000008)
+#define RCC_APB1RSTR_TIM6RST_MORT ((uint32_t)0x00000010)
+#define RCC_APB1RSTR_TIM7RST_MORT ((uint32_t)0x00000020)
+#define RCC_APB1RSTR_TIM12RST_MORT ((uint32_t)0x00000040)
+#define RCC_APB1RSTR_TIM13RST_MORT ((uint32_t)0x00000080)
+#define RCC_APB1RSTR_TIM14RST_MORT ((uint32_t)0x00000100)
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+#define RCC_APB1RSTR_LPTIM1RST_MORT ((uint32_t)0x00000200)
+#endif /* STM32F410xx || STM32F413_423xx */
+#define RCC_APB1RSTR_WWDGRST_MORT ((uint32_t)0x00000800)
+#define RCC_APB1RSTR_SPI2RST_MORT ((uint32_t)0x00004000)
+#define RCC_APB1RSTR_SPI3RST_MORT ((uint32_t)0x00008000)
+#if defined(STM32F446xx_MORT)
+#define RCC_APB1RSTR_SPDIFRXRST_MORT ((uint32_t)0x00010000)
+#endif /* STM32F446xx_MORT */
+#define RCC_APB1RSTR_USART2RST_MORT ((uint32_t)0x00020000)
+#define RCC_APB1RSTR_USART3RST_MORT ((uint32_t)0x00040000)
+#define RCC_APB1RSTR_UART4RST_MORT ((uint32_t)0x00080000)
+#define RCC_APB1RSTR_UART5RST_MORT ((uint32_t)0x00100000)
+#define RCC_APB1RSTR_I2C1RST_MORT ((uint32_t)0x00200000)
+#define RCC_APB1RSTR_I2C2RST_MORT ((uint32_t)0x00400000)
+#define RCC_APB1RSTR_I2C3RST_MORT ((uint32_t)0x00800000)
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT)
+#define RCC_APB1RSTR_FMPI2C1RST_MORT ((uint32_t)0x01000000)
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */
+#define RCC_APB1RSTR_CAN1RST_MORT ((uint32_t)0x02000000)
+#define RCC_APB1RSTR_CAN2RST_MORT ((uint32_t)0x04000000)
+#if defined(STM32F446xx_MORT)
+#define RCC_APB1RSTR_CECRST_MORT ((uint32_t)0x08000000)
+#endif /* STM32F446xx_MORT */
+#define RCC_APB1RSTR_PWRRST_MORT ((uint32_t)0x10000000)
+#define RCC_APB1RSTR_DACRST_MORT ((uint32_t)0x20000000)
+#define RCC_APB1RSTR_UART7RST_MORT ((uint32_t)0x40000000)
+#define RCC_APB1RSTR_UART8RST_MORT ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST_MORT ((uint32_t)0x00000001)
+#define RCC_APB2RSTR_TIM8RST_MORT ((uint32_t)0x00000002)
+#define RCC_APB2RSTR_USART1RST_MORT ((uint32_t)0x00000010)
+#define RCC_APB2RSTR_USART6RST_MORT ((uint32_t)0x00000020)
+#define RCC_APB2RSTR_UART9RST_MORT ((uint32_t)0x00000040)
+#define RCC_APB2RSTR_UART10RST_MORT ((uint32_t)0x00000080)
+#define RCC_APB2RSTR_ADCRST_MORT ((uint32_t)0x00000100)
+#define RCC_APB2RSTR_SDIORST_MORT ((uint32_t)0x00000800)
+#define RCC_APB2RSTR_SPI1RST_MORT ((uint32_t)0x00001000)
+#define RCC_APB2RSTR_SPI4RST_MORT ((uint32_t)0x00002000)
+#define RCC_APB2RSTR_SYSCFGRST_MORT ((uint32_t)0x00004000)
+#define RCC_APB2RSTR_TIM9RST_MORT ((uint32_t)0x00010000)
+#define RCC_APB2RSTR_TIM10RST_MORT ((uint32_t)0x00020000)
+#define RCC_APB2RSTR_TIM11RST_MORT ((uint32_t)0x00040000)
+#define RCC_APB2RSTR_SPI5RST_MORT ((uint32_t)0x00100000)
+#define RCC_APB2RSTR_SPI6RST_MORT ((uint32_t)0x00200000)
+#define RCC_APB2RSTR_SAI1RST_MORT ((uint32_t)0x00400000)
+#if defined(STM32F446xx_MORT)
+#define RCC_APB2RSTR_SAI2RST_MORT ((uint32_t)0x00800000)
+#endif /* STM32F446xx_MORT */
+#define RCC_APB2RSTR_LTDCRST_MORT ((uint32_t)0x04000000)
+#if defined(STM32F469_479xx)
+#define RCC_APB2RSTR_DSIRST_MORT ((uint32_t)0x08000000)
+#endif /* STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define RCC_APB2RSTR_DFSDM1RST_MORT ((uint32_t)0x01000000)
+#endif /* STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F413_423xx)
+#define RCC_APB2RSTR_DFSDM2RST_MORT ((uint32_t)0x02000000)
+#endif /* STM32F413_423xx */
+/* Old definitions, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1_MORT RCC_APB2RSTR_SPI1RST_MORT
+#define RCC_APB2RSTR_DFSDMRST RCC_APB2RSTR_DFSDM1RST_MORT
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN_MORT ((uint32_t)0x00000001)
+#define RCC_AHB1ENR_GPIOBEN_MORT ((uint32_t)0x00000002)
+#define RCC_AHB1ENR_GPIOCEN_MORT ((uint32_t)0x00000004)
+#define RCC_AHB1ENR_GPIODEN_MORT ((uint32_t)0x00000008)
+#define RCC_AHB1ENR_GPIOEEN_MORT ((uint32_t)0x00000010)
+#define RCC_AHB1ENR_GPIOFEN_MORT ((uint32_t)0x00000020)
+#define RCC_AHB1ENR_GPIOGEN_MORT ((uint32_t)0x00000040)
+#define RCC_AHB1ENR_GPIOHEN_MORT ((uint32_t)0x00000080)
+#define RCC_AHB1ENR_GPIOIEN_MORT ((uint32_t)0x00000100)
+#define RCC_AHB1ENR_GPIOJEN_MORT ((uint32_t)0x00000200)
+#define RCC_AHB1ENR_GPIOKEN_MORT ((uint32_t)0x00000400)
+#define RCC_AHB1ENR_CRCEN_MORT ((uint32_t)0x00001000)
+#define RCC_AHB1ENR_BKPSRAMEN_MORT ((uint32_t)0x00040000)
+#define RCC_AHB1ENR_CCMDATARAMEN_MORT ((uint32_t)0x00100000)
+#define RCC_AHB1ENR_DMA1EN_MORT ((uint32_t)0x00200000)
+#define RCC_AHB1ENR_DMA2EN_MORT ((uint32_t)0x00400000)
+#define RCC_AHB1ENR_DMA2DEN_MORT ((uint32_t)0x00800000)
+#define RCC_AHB1ENR_ETHMACEN_MORT ((uint32_t)0x02000000)
+#define RCC_AHB1ENR_ETHMACTXEN_MORT ((uint32_t)0x04000000)
+#define RCC_AHB1ENR_ETHMACRXEN_MORT ((uint32_t)0x08000000)
+#define RCC_AHB1ENR_ETHMACPTPEN_MORT ((uint32_t)0x10000000)
+#define RCC_AHB1ENR_OTGHSEN_MORT ((uint32_t)0x20000000)
+#define RCC_AHB1ENR_OTGHSULPIEN_MORT ((uint32_t)0x40000000)
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_DCMIEN_MORT ((uint32_t)0x00000001)
+#define RCC_AHB2ENR_CRYPEN_MORT ((uint32_t)0x00000010)
+#define RCC_AHB2ENR_HASHEN_MORT ((uint32_t)0x00000020)
+#define RCC_AHB2ENR_RNGEN_MORT ((uint32_t)0x00000040)
+#define RCC_AHB2ENR_OTGFSEN_MORT ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+#define RCC_AHB3ENR_FMCEN_MORT ((uint32_t)0x00000001)
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+#define RCC_AHB3ENR_QSPIEN_MORT ((uint32_t)0x00000002)
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN_MORT ((uint32_t)0x00000001)
+#define RCC_APB1ENR_TIM3EN_MORT ((uint32_t)0x00000002)
+#define RCC_APB1ENR_TIM4EN_MORT ((uint32_t)0x00000004)
+#define RCC_APB1ENR_TIM5EN_MORT ((uint32_t)0x00000008)
+#define RCC_APB1ENR_TIM6EN_MORT ((uint32_t)0x00000010)
+#define RCC_APB1ENR_TIM7EN_MORT ((uint32_t)0x00000020)
+#define RCC_APB1ENR_TIM12EN_MORT ((uint32_t)0x00000040)
+#define RCC_APB1ENR_TIM13EN_MORT ((uint32_t)0x00000080)
+#define RCC_APB1ENR_TIM14EN_MORT ((uint32_t)0x00000100)
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+
+#endif /* STM32F410xx || STM32F413_423xx */
+#define RCC_APB1ENR_WWDGEN_MORT ((uint32_t)0x00000800)
+#define RCC_APB1ENR_SPI2EN_MORT ((uint32_t)0x00004000)
+#define RCC_APB1ENR_SPI3EN_MORT ((uint32_t)0x00008000)
+#if defined(STM32F446xx_MORT)
+#define RCC_APB1ENR_SPDIFRXEN_MORT ((uint32_t)0x00010000)
+#endif /* STM32F446xx_MORT */
+#define RCC_APB1ENR_USART2EN_MORT ((uint32_t)0x00020000)
+#define RCC_APB1ENR_USART3EN_MORT ((uint32_t)0x00040000)
+#define RCC_APB1ENR_UART4EN_MORT ((uint32_t)0x00080000)
+#define RCC_APB1ENR_UART5EN_MORT ((uint32_t)0x00100000)
+#define RCC_APB1ENR_I2C1EN_MORT ((uint32_t)0x00200000)
+#define RCC_APB1ENR_I2C2EN_MORT ((uint32_t)0x00400000)
+#define RCC_APB1ENR_I2C3EN_MORT ((uint32_t)0x00800000)
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT)
+#define RCC_APB1ENR_FMPI2C1EN_MORT ((uint32_t)0x01000000)
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */
+#define RCC_APB1ENR_CAN1EN_MORT ((uint32_t)0x02000000)
+#define RCC_APB1ENR_CAN2EN_MORT ((uint32_t)0x04000000)
+#if defined(STM32F446xx_MORT)
+#define RCC_APB1ENR_CECEN_MORT ((uint32_t)0x08000000)
+#endif /* STM32F446xx_MORT */
+#define RCC_APB1ENR_PWREN_MORT ((uint32_t)0x10000000)
+#define RCC_APB1ENR_DACEN_MORT ((uint32_t)0x20000000)
+#define RCC_APB1ENR_UART7EN_MORT ((uint32_t)0x40000000)
+#define RCC_APB1ENR_UART8EN_MORT ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN_MORT ((uint32_t)0x00000001)
+#define RCC_APB2ENR_TIM8EN_MORT ((uint32_t)0x00000002)
+#define RCC_APB2ENR_USART1EN_MORT ((uint32_t)0x00000010)
+#define RCC_APB2ENR_USART6EN_MORT ((uint32_t)0x00000020)
+#define RCC_APB2ENR_UART9EN_MORT ((uint32_t)0x00000040)
+#define RCC_APB2ENR_UART10EN_MORT ((uint32_t)0x00000080)
+#define RCC_APB2ENR_ADC1EN_MORT ((uint32_t)0x00000100)
+#define RCC_APB2ENR_ADC2EN_MORT ((uint32_t)0x00000200)
+#define RCC_APB2ENR_ADC3EN_MORT ((uint32_t)0x00000400)
+#define RCC_APB2ENR_SDIOEN_MORT ((uint32_t)0x00000800)
+#define RCC_APB2ENR_SPI1EN_MORT ((uint32_t)0x00001000)
+#define RCC_APB2ENR_SPI4EN_MORT ((uint32_t)0x00002000)
+#define RCC_APB2ENR_SYSCFGEN_MORT ((uint32_t)0x00004000)
+#define RCC_APB2ENR_EXTIEN_MORT ((uint32_t)0x00008000)
+#define RCC_APB2ENR_TIM9EN_MORT ((uint32_t)0x00010000)
+#define RCC_APB2ENR_TIM10EN_MORT ((uint32_t)0x00020000)
+#define RCC_APB2ENR_TIM11EN_MORT ((uint32_t)0x00040000)
+#define RCC_APB2ENR_SPI5EN_MORT ((uint32_t)0x00100000)
+#define RCC_APB2ENR_SPI6EN_MORT ((uint32_t)0x00200000)
+#define RCC_APB2ENR_SAI1EN_MORT ((uint32_t)0x00400000)
+#if defined(STM32F446xx_MORT)
+#define RCC_APB2ENR_SAI2EN_MORT ((uint32_t)0x00800000)
+#endif /* STM32F446xx_MORT */
+#define RCC_APB2ENR_LTDCEN_MORT ((uint32_t)0x04000000)
+#if defined(STM32F469_479xx)
+#define RCC_APB2ENR_DSIEN_MORT ((uint32_t)0x08000000)
+#endif /* STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define RCC_APB2ENR_DFSDM1EN_MORT ((uint32_t)0x01000000)
+#endif /* STM32F412xG || STM32F413_423xx */
+#if defined(STM32F413_423xx)
+#define RCC_APB2ENR_DFSDM2EN_MORT ((uint32_t)0x02000000)
+#endif /* STM32F413_423xx */
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN_MORT ((uint32_t)0x00000001)
+#define RCC_AHB1LPENR_GPIOBLPEN_MORT ((uint32_t)0x00000002)
+#define RCC_AHB1LPENR_GPIOCLPEN_MORT ((uint32_t)0x00000004)
+#define RCC_AHB1LPENR_GPIODLPEN_MORT ((uint32_t)0x00000008)
+#define RCC_AHB1LPENR_GPIOELPEN_MORT ((uint32_t)0x00000010)
+#define RCC_AHB1LPENR_GPIOFLPEN_MORT ((uint32_t)0x00000020)
+#define RCC_AHB1LPENR_GPIOGLPEN_MORT ((uint32_t)0x00000040)
+#define RCC_AHB1LPENR_GPIOHLPEN_MORT ((uint32_t)0x00000080)
+#define RCC_AHB1LPENR_GPIOILPEN_MORT ((uint32_t)0x00000100)
+#define RCC_AHB1LPENR_GPIOJLPEN_MORT ((uint32_t)0x00000200)
+#define RCC_AHB1LPENR_GPIOKLPEN_MORT ((uint32_t)0x00000400)
+#define RCC_AHB1LPENR_CRCLPEN_MORT ((uint32_t)0x00001000)
+#define RCC_AHB1LPENR_FLITFLPEN_MORT ((uint32_t)0x00008000)
+#define RCC_AHB1LPENR_SRAM1LPEN_MORT ((uint32_t)0x00010000)
+#define RCC_AHB1LPENR_SRAM2LPEN_MORT ((uint32_t)0x00020000)
+#define RCC_AHB1LPENR_BKPSRAMLPEN_MORT ((uint32_t)0x00040000)
+#define RCC_AHB1LPENR_SRAM3LPEN_MORT ((uint32_t)0x00080000)
+#define RCC_AHB1LPENR_DMA1LPEN_MORT ((uint32_t)0x00200000)
+#define RCC_AHB1LPENR_DMA2LPEN_MORT ((uint32_t)0x00400000)
+#define RCC_AHB1LPENR_DMA2DLPEN_MORT ((uint32_t)0x00800000)
+#define RCC_AHB1LPENR_ETHMACLPEN_MORT ((uint32_t)0x02000000)
+#define RCC_AHB1LPENR_ETHMACTXLPEN_MORT ((uint32_t)0x04000000)
+#define RCC_AHB1LPENR_ETHMACRXLPEN_MORT ((uint32_t)0x08000000)
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_MORT ((uint32_t)0x10000000)
+#define RCC_AHB1LPENR_OTGHSLPEN_MORT ((uint32_t)0x20000000)
+#define RCC_AHB1LPENR_OTGHSULPILPEN_MORT ((uint32_t)0x40000000)
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN_MORT ((uint32_t)0x00000001)
+#define RCC_AHB2LPENR_CRYPLPEN_MORT ((uint32_t)0x00000010)
+#define RCC_AHB2LPENR_HASHLPEN_MORT ((uint32_t)0x00000020)
+#define RCC_AHB2LPENR_RNGLPEN_MORT ((uint32_t)0x00000040)
+#define RCC_AHB2LPENR_OTGFSLPEN_MORT ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+#define RCC_AHB3LPENR_FSMCLPEN_MORT ((uint32_t)0x00000001)
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+#define RCC_AHB3LPENR_FMCLPEN_MORT ((uint32_t)0x00000001)
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+#define RCC_AHB3LPENR_QSPILPEN_MORT ((uint32_t)0x00000002)
+#endif /* STM32F412xG || STM32F413_423xx || STM32F469_479xx || STM32F446xx_MORT */
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN_MORT ((uint32_t)0x00000001)
+#define RCC_APB1LPENR_TIM3LPEN_MORT ((uint32_t)0x00000002)
+#define RCC_APB1LPENR_TIM4LPEN_MORT ((uint32_t)0x00000004)
+#define RCC_APB1LPENR_TIM5LPEN_MORT ((uint32_t)0x00000008)
+#define RCC_APB1LPENR_TIM6LPEN_MORT ((uint32_t)0x00000010)
+#define RCC_APB1LPENR_TIM7LPEN_MORT ((uint32_t)0x00000020)
+#define RCC_APB1LPENR_TIM12LPEN_MORT ((uint32_t)0x00000040)
+#define RCC_APB1LPENR_TIM13LPEN_MORT ((uint32_t)0x00000080)
+#define RCC_APB1LPENR_TIM14LPEN_MORT ((uint32_t)0x00000100)
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+#define RCC_APB1LPENR_LPTIM1LPEN_MORT ((uint32_t)0x00000200)
+#endif /* STM32F410xx || STM32F413_423xx */
+#define RCC_APB1LPENR_WWDGLPEN_MORT ((uint32_t)0x00000800)
+#define RCC_APB1LPENR_SPI2LPEN_MORT ((uint32_t)0x00004000)
+#define RCC_APB1LPENR_SPI3LPEN_MORT ((uint32_t)0x00008000)
+#if defined(STM32F446xx_MORT)
+#define RCC_APB1LPENR_SPDIFRXLPEN_MORT ((uint32_t)0x00010000)
+#endif /* STM32F446xx_MORT */
+#define RCC_APB1LPENR_USART2LPEN_MORT ((uint32_t)0x00020000)
+#define RCC_APB1LPENR_USART3LPEN_MORT ((uint32_t)0x00040000)
+#define RCC_APB1LPENR_UART4LPEN_MORT ((uint32_t)0x00080000)
+#define RCC_APB1LPENR_UART5LPEN_MORT ((uint32_t)0x00100000)
+#define RCC_APB1LPENR_I2C1LPEN_MORT ((uint32_t)0x00200000)
+#define RCC_APB1LPENR_I2C2LPEN_MORT ((uint32_t)0x00400000)
+#define RCC_APB1LPENR_I2C3LPEN_MORT ((uint32_t)0x00800000)
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT)
+#define RCC_APB1LPENR_FMPI2C1LPEN_MORT ((uint32_t)0x01000000)
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */
+#define RCC_APB1LPENR_CAN1LPEN_MORT ((uint32_t)0x02000000)
+#define RCC_APB1LPENR_CAN2LPEN_MORT ((uint32_t)0x04000000)
+#if defined(STM32F446xx_MORT)
+#define RCC_APB1LPENR_CECLPEN_MORT ((uint32_t)0x08000000)
+#endif /* STM32F446xx_MORT */
+#define RCC_APB1LPENR_PWRLPEN_MORT ((uint32_t)0x10000000)
+#define RCC_APB1LPENR_DACLPEN_MORT ((uint32_t)0x20000000)
+#define RCC_APB1LPENR_UART7LPEN_MORT ((uint32_t)0x40000000)
+#define RCC_APB1LPENR_UART8LPEN_MORT ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN_MORT ((uint32_t)0x00000001)
+#define RCC_APB2LPENR_TIM8LPEN_MORT ((uint32_t)0x00000002)
+#define RCC_APB2LPENR_USART1LPEN_MORT ((uint32_t)0x00000010)
+#define RCC_APB2LPENR_USART6LPEN_MORT ((uint32_t)0x00000020)
+#define RCC_APB2LPENR_UART9LPEN_MORT ((uint32_t)0x00000040)
+#define RCC_APB2LPENR_UART10LPEN_MORT ((uint32_t)0x00000080)
+#define RCC_APB2LPENR_ADC1LPEN_MORT ((uint32_t)0x00000100)
+#define RCC_APB2LPENR_ADC2PEN_MORT ((uint32_t)0x00000200)
+#define RCC_APB2LPENR_ADC3LPEN_MORT ((uint32_t)0x00000400)
+#define RCC_APB2LPENR_SDIOLPEN_MORT ((uint32_t)0x00000800)
+#define RCC_APB2LPENR_SPI1LPEN_MORT ((uint32_t)0x00001000)
+#define RCC_APB2LPENR_SPI4LPEN_MORT ((uint32_t)0x00002000)
+#define RCC_APB2LPENR_SYSCFGLPEN_MORT ((uint32_t)0x00004000)
+#define RCC_APB2LPENR_TIM9LPEN_MORT ((uint32_t)0x00010000)
+#define RCC_APB2LPENR_TIM10LPEN_MORT ((uint32_t)0x00020000)
+#define RCC_APB2LPENR_TIM11LPEN_MORT ((uint32_t)0x00040000)
+#define RCC_APB2LPENR_SPI5LPEN_MORT ((uint32_t)0x00100000)
+#define RCC_APB2LPENR_SPI6LPEN_MORT ((uint32_t)0x00200000)
+#define RCC_APB2LPENR_SAI1LPEN_MORT ((uint32_t)0x00400000)
+#if defined(STM32F446xx_MORT)
+#define RCC_APB2LPENR_SAI2LPEN_MORT ((uint32_t)0x00800000)
+#endif /* STM32F446xx_MORT */
+#define RCC_APB2LPENR_LTDCLPEN_MORT ((uint32_t)0x04000000)
+#if defined(STM32F469_479xx)
+
+#endif /* STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+
+#endif /* STM32F412xG || STM32F413_423xx */
+#if defined(STM32F413_423xx)
+
+#endif /* STM32F413_423xx */
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON_MORT ((uint32_t)0x00000001)
+#define RCC_BDCR_LSERDY_MORT ((uint32_t)0x00000002)
+#define RCC_BDCR_LSEBYP_MORT ((uint32_t)0x00000004)
+#define RCC_BDCR_LSEMOD_MORT ((uint32_t)0x00000008)
+
+#define RCC_BDCR_RTCSEL_MORT ((uint32_t)0x00000300)
+#define RCC_BDCR_RTCSEL_0_MORT ((uint32_t)0x00000100)
+#define RCC_BDCR_RTCSEL_1_MORT ((uint32_t)0x00000200)
+
+#define RCC_BDCR_RTCEN_MORT ((uint32_t)0x00008000)
+#define RCC_BDCR_BDRST_MORT ((uint32_t)0x00010000)
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_MORT ((uint32_t)0x00000001)
+#define RCC_CSR_LSIRDY_MORT ((uint32_t)0x00000002)
+#define RCC_CSR_RMVF_MORT ((uint32_t)0x01000000)
+#define RCC_CSR_BORRSTF_MORT ((uint32_t)0x02000000)
+#define RCC_CSR_PADRSTF_MORT ((uint32_t)0x04000000)
+#define RCC_CSR_PORRSTF_MORT ((uint32_t)0x08000000)
+#define RCC_CSR_SFTRSTF_MORT ((uint32_t)0x10000000)
+#define RCC_CSR_WDGRSTF_MORT ((uint32_t)0x20000000)
+#define RCC_CSR_WWDGRSTF_MORT ((uint32_t)0x40000000)
+#define RCC_CSR_LPWRRSTF_MORT ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER_MORT ((uint32_t)0x00001FFF)
+#define RCC_SSCGR_INCSTEP_MORT ((uint32_t)0x0FFFE000)
+#define RCC_SSCGR_SPREADSEL_MORT ((uint32_t)0x40000000)
+#define RCC_SSCGR_SSCGEN_MORT ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM_MORT ((uint32_t)0x0000003F)
+#define RCC_PLLI2SCFGR_PLLI2SM_0_MORT ((uint32_t)0x00000001)
+#define RCC_PLLI2SCFGR_PLLI2SM_1_MORT ((uint32_t)0x00000002)
+#define RCC_PLLI2SCFGR_PLLI2SM_2_MORT ((uint32_t)0x00000004)
+#define RCC_PLLI2SCFGR_PLLI2SM_3_MORT ((uint32_t)0x00000008)
+#define RCC_PLLI2SCFGR_PLLI2SM_4_MORT ((uint32_t)0x00000010)
+#define RCC_PLLI2SCFGR_PLLI2SM_5_MORT ((uint32_t)0x00000020)
+
+#define RCC_PLLI2SCFGR_PLLI2SN_MORT ((uint32_t)0x00007FC0)
+#define RCC_PLLI2SCFGR_PLLI2SN_0_MORT ((uint32_t)0x00000040)
+#define RCC_PLLI2SCFGR_PLLI2SN_1_MORT ((uint32_t)0x00000080)
+#define RCC_PLLI2SCFGR_PLLI2SN_2_MORT ((uint32_t)0x00000100)
+#define RCC_PLLI2SCFGR_PLLI2SN_3_MORT ((uint32_t)0x00000200)
+#define RCC_PLLI2SCFGR_PLLI2SN_4_MORT ((uint32_t)0x00000400)
+#define RCC_PLLI2SCFGR_PLLI2SN_5_MORT ((uint32_t)0x00000800)
+#define RCC_PLLI2SCFGR_PLLI2SN_6_MORT ((uint32_t)0x00001000)
+#define RCC_PLLI2SCFGR_PLLI2SN_7_MORT ((uint32_t)0x00002000)
+#define RCC_PLLI2SCFGR_PLLI2SN_8_MORT ((uint32_t)0x00004000)
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+
+#endif /* STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F446xx_MORT)
+#define RCC_PLLI2SCFGR_PLLI2SP_MORT ((uint32_t)0x00030000)
+#define RCC_PLLI2SCFGR_PLLI2SP_0_MORT ((uint32_t)0x00010000)
+#define RCC_PLLI2SCFGR_PLLI2SP_1_MORT ((uint32_t)0x00020000)
+#endif /* STM32F446xx_MORT */
+
+#define RCC_PLLI2SCFGR_PLLI2SQ_MORT ((uint32_t)0x0F000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_0_MORT ((uint32_t)0x01000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_1_MORT ((uint32_t)0x02000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_2_MORT ((uint32_t)0x04000000)
+#define RCC_PLLI2SCFGR_PLLI2SQ_3_MORT ((uint32_t)0x08000000)
+
+#define RCC_PLLI2SCFGR_PLLI2SR_MORT ((uint32_t)0x70000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_0_MORT ((uint32_t)0x10000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_1_MORT ((uint32_t)0x20000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_2_MORT ((uint32_t)0x40000000)
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#if defined(STM32F446xx_MORT)
+#define RCC_PLLSAICFGR_PLLSAIM_MORT ((uint32_t)0x0000003F)
+#define RCC_PLLSAICFGR_PLLSAIM_0_MORT ((uint32_t)0x00000001)
+#define RCC_PLLSAICFGR_PLLSAIM_1_MORT ((uint32_t)0x00000002)
+#define RCC_PLLSAICFGR_PLLSAIM_2_MORT ((uint32_t)0x00000004)
+#define RCC_PLLSAICFGR_PLLSAIM_3_MORT ((uint32_t)0x00000008)
+#define RCC_PLLSAICFGR_PLLSAIM_4_MORT ((uint32_t)0x00000010)
+#define RCC_PLLSAICFGR_PLLSAIM_5_MORT ((uint32_t)0x00000020)
+#endif /* STM32F446xx_MORT */
+
+#define RCC_PLLSAICFGR_PLLSAIN_MORT ((uint32_t)0x00007FC0)
+#define RCC_PLLSAICFGR_PLLSAIN_0_MORT ((uint32_t)0x00000040)
+#define RCC_PLLSAICFGR_PLLSAIN_1_MORT ((uint32_t)0x00000080)
+#define RCC_PLLSAICFGR_PLLSAIN_2_MORT ((uint32_t)0x00000100)
+#define RCC_PLLSAICFGR_PLLSAIN_3_MORT ((uint32_t)0x00000200)
+#define RCC_PLLSAICFGR_PLLSAIN_4_MORT ((uint32_t)0x00000400)
+#define RCC_PLLSAICFGR_PLLSAIN_5_MORT ((uint32_t)0x00000800)
+#define RCC_PLLSAICFGR_PLLSAIN_6_MORT ((uint32_t)0x00001000)
+#define RCC_PLLSAICFGR_PLLSAIN_7_MORT ((uint32_t)0x00002000)
+#define RCC_PLLSAICFGR_PLLSAIN_8_MORT ((uint32_t)0x00004000)
+
+#if defined(STM32F446xx_MORT) || defined(STM32F469_479xx)
+#define RCC_PLLSAICFGR_PLLSAIP_MORT ((uint32_t)0x00030000)
+#define RCC_PLLSAICFGR_PLLSAIP_0_MORT ((uint32_t)0x00010000)
+#define RCC_PLLSAICFGR_PLLSAIP_1_MORT ((uint32_t)0x00020000)
+#endif /* STM32F446xx_MORT || STM32F469_479xx */
+
+#define RCC_PLLSAICFGR_PLLSAIQ_MORT ((uint32_t)0x0F000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_0_MORT ((uint32_t)0x01000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_1_MORT ((uint32_t)0x02000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_2_MORT ((uint32_t)0x04000000)
+#define RCC_PLLSAICFGR_PLLSAIQ_3_MORT ((uint32_t)0x08000000)
+
+#define RCC_PLLSAICFGR_PLLSAIR_MORT ((uint32_t)0x70000000)
+#define RCC_PLLSAICFGR_PLLSAIR_0_MORT ((uint32_t)0x10000000)
+#define RCC_PLLSAICFGR_PLLSAIR_1_MORT ((uint32_t)0x20000000)
+#define RCC_PLLSAICFGR_PLLSAIR_2_MORT ((uint32_t)0x40000000)
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ_MORT ((uint32_t)0x0000001F)
+#define RCC_DCKCFGR_PLLSAIDIVQ_MORT ((uint32_t)0x00001F00)
+#define RCC_DCKCFGR_PLLSAIDIVR_MORT ((uint32_t)0x00030000)
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+
+#endif /* STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F413_423xx)
+
+#endif /* STM32F413_423xx */
+
+#define RCC_DCKCFGR_SAI1ASRC_MORT ((uint32_t)0x00300000)
+#define RCC_DCKCFGR_SAI1ASRC_0_MORT ((uint32_t)0x00100000)
+#define RCC_DCKCFGR_SAI1ASRC_1_MORT ((uint32_t)0x00200000)
+#if defined(STM32F446xx_MORT)
+#define RCC_DCKCFGR_SAI1SRC_MORT ((uint32_t)0x00300000)
+#define RCC_DCKCFGR_SAI1SRC_0_MORT ((uint32_t)0x00100000)
+#define RCC_DCKCFGR_SAI1SRC_1_MORT ((uint32_t)0x00200000)
+#endif /* STM32F446xx_MORT */
+
+#define RCC_DCKCFGR_SAI1BSRC_MORT ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR_SAI1BSRC_0_MORT ((uint32_t)0x00400000)
+#define RCC_DCKCFGR_SAI1BSRC_1_MORT ((uint32_t)0x00800000)
+#if defined(STM32F446xx_MORT)
+#define RCC_DCKCFGR_SAI2SRC_MORT ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR_SAI2SRC_0_MORT ((uint32_t)0x00400000)
+#define RCC_DCKCFGR_SAI2SRC_1_MORT ((uint32_t)0x00800000)
+#endif /* STM32F446xx_MORT */
+
+#define RCC_DCKCFGR_TIMPRE_MORT ((uint32_t)0x01000000)
+#if defined(STM32F469_479xx)
+
+#endif /* STM32F469_479xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT)
+#define RCC_DCKCFGR_I2S1SRC_MORT ((uint32_t)0x06000000)
+#define RCC_DCKCFGR_I2S1SRC_0_MORT ((uint32_t)0x02000000)
+#define RCC_DCKCFGR_I2S1SRC_1_MORT ((uint32_t)0x04000000)
+#define RCC_DCKCFGR_I2S2SRC_MORT ((uint32_t)0x18000000)
+#define RCC_DCKCFGR_I2S2SRC_0_MORT ((uint32_t)0x08000000)
+#define RCC_DCKCFGR_I2S2SRC_1_MORT ((uint32_t)0x10000000)
+
+/******************** Bit definition for RCC_CKGATENR register ***************/
+#define RCC_CKGATENR_AHB2APB1_CKEN_MORT ((uint32_t)0x00000001)
+#define RCC_CKGATENR_AHB2APB2_CKEN_MORT ((uint32_t)0x00000002)
+#define RCC_CKGATENR_CM4DBG_CKEN_MORT ((uint32_t)0x00000004)
+#define RCC_CKGATENR_SPARE_CKEN_MORT ((uint32_t)0x00000008)
+#define RCC_CKGATENR_SRAM_CKEN_MORT ((uint32_t)0x00000010)
+#define RCC_CKGATENR_FLITF_CKEN_MORT ((uint32_t)0x00000020)
+#define RCC_CKGATENR_RCC_CKEN_MORT ((uint32_t)0x00000040)
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+
+#endif /* STM32F412xG || STM32F413_423xx */
+
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/
+#define RCC_DCKCFGR2_FMPI2C1SEL_MORT ((uint32_t)0x00C00000)
+#define RCC_DCKCFGR2_FMPI2C1SEL_0_MORT ((uint32_t)0x00400000)
+#define RCC_DCKCFGR2_FMPI2C1SEL_1_MORT ((uint32_t)0x00800000)
+#define RCC_DCKCFGR2_CECSEL_MORT ((uint32_t)0x04000000)
+#define RCC_DCKCFGR2_CK48MSEL_MORT ((uint32_t)0x08000000)
+#define RCC_DCKCFGR2_SDIOSEL_MORT ((uint32_t)0x10000000)
+#if defined(STM32F446xx_MORT)
+#define RCC_DCKCFGR2_SPDIFRXSEL_MORT ((uint32_t)0x20000000)
+#endif /* STM32F446xx_MORT */
+#if defined(STM32F413_423xx)
+
+#endif /* STM32F413_423xx */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */
+
+#if defined(STM32F410xx)
+
+#endif /* STM32F410xx */
+
+#if defined(STM32F410xx)
+/******************** Bit definition for RCC_DCKCFGR2 register **************/
+
+#endif /* STM32F410xx */
+/******************************************************************************/
+/* */
+/* RNG_MORT */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_MORT ((uint32_t)0x00000004)
+#define RNG_CR_IE_MORT ((uint32_t)0x00000008)
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_MORT ((uint32_t)0x00000001)
+#define RNG_SR_CECS_MORT ((uint32_t)0x00000002)
+#define RNG_SR_SECS_MORT ((uint32_t)0x00000004)
+#define RNG_SR_CEIS_MORT ((uint32_t)0x00000020)
+#define RNG_SR_SEIS_MORT ((uint32_t)0x00000040)
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC_MORT) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+
+
+/******************** Bits definition for RTC_DR register *******************/
+
+
+/******************** Bits definition for RTC_CR register *******************/
+
+
+/******************** Bits definition for RTC_ISR register ******************/
+
+
+/******************** Bits definition for RTC_PRER register *****************/
+
+
+/******************** Bits definition for RTC_WUTR register *****************/
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+
+/******************** Bits definition for RTC_WPR register ******************/
+
+
+/******************** Bits definition for RTC_SSR register ******************/
+
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+
+
+/******************** Bits definition for RTC_TSTR register *****************/
+
+
+/******************** Bits definition for RTC_TSDR register *****************/
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+
+
+/******************** Bits definition for RTC_CAL register *****************/
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+
+/******************* Bit definition for SAI_xIMR register *******************/
+
+/******************** Bit definition for SAI_xSR register *******************/
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+
+/****************** Bit definition for SAI_xDR register ******************/
+
+
+#if defined(STM32F446xx_MORT)
+/******************************************************************************/
+/* */
+/* SPDIF-RX Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SPDIFRX_CR register *******************/
+
+/******************* Bit definition for SPDIFRX_IMR register *******************/
+
+/******************* Bit definition for SPDIFRX_SR register *******************/
+
+/******************* Bit definition for SPDIFRX_IFCR register *******************/
+
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
+
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
+
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
+
+/******************* Bit definition for SPDIFRX_CSR register *******************/
+
+/******************* Bit definition for SPDIFRX_DIR register *******************/
+
+#endif /* STM32F446xx_MORT */
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+
+/******************* Bit definition for SDIO_ARG register *******************/
+
+/******************* Bit definition for SDIO_CMD register *******************/
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+
+/****************** Bit definition for SDIO_STA register ********************/
+
+/******************* Bit definition for SDIO_ICR register *******************/
+
+
+/****************** Bit definition for SDIO_MASK register *******************/
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_MORT ((uint16_t)0x0001) /*!<Clock Phase */
+#define SPI_CR1_CPOL_MORT ((uint16_t)0x0002) /*!<Clock Polarity */
+#define SPI_CR1_MSTR_MORT ((uint16_t)0x0004) /*!<Master Selection */
+
+#define SPI_CR1_BR_MORT ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0_MORT ((uint16_t)0x0008) /*!<Bit 0 */
+#define SPI_CR1_BR_1_MORT ((uint16_t)0x0010) /*!<Bit 1 */
+#define SPI_CR1_BR_2_MORT ((uint16_t)0x0020) /*!<Bit 2 */
+
+#define SPI_CR1_SPE_MORT ((uint16_t)0x0040) /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST_MORT ((uint16_t)0x0080) /*!<Frame Format */
+#define SPI_CR1_SSI_MORT ((uint16_t)0x0100) /*!<Internal slave select */
+#define SPI_CR1_SSM_MORT ((uint16_t)0x0200) /*!<Software slave management */
+#define SPI_CR1_RXONLY_MORT ((uint16_t)0x0400) /*!<Receive only */
+#define SPI_CR1_DFF_MORT ((uint16_t)0x0800) /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT_MORT ((uint16_t)0x1000) /*!<Transmit CRC_MORT next */
+#define SPI_CR1_CRCEN_MORT ((uint16_t)0x2000) /*!<Hardware CRC_MORT calculation enable */
+#define SPI_CR1_BIDIOE_MORT ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_MORT ((uint16_t)0x8000) /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_MORT ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_MORT ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_MORT ((uint8_t)0x04) /*!<SS Output Enable */
+#define SPI_CR2_ERRIE_MORT ((uint8_t)0x20) /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_MORT ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_MORT ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_MORT ((uint8_t)0x01) /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_MORT ((uint8_t)0x02) /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE_MORT ((uint8_t)0x04) /*!<Channel side */
+#define SPI_SR_UDR_MORT ((uint8_t)0x08) /*!<Underrun flag */
+#define SPI_SR_CRCERR_MORT ((uint8_t)0x10) /*!<CRC_MORT Error flag */
+#define SPI_SR_MODF_MORT ((uint8_t)0x20) /*!<Mode fault */
+#define SPI_SR_OVR_MORT ((uint8_t)0x40) /*!<Overrun flag */
+#define SPI_SR_BSY_MORT ((uint8_t)0x80) /*!<Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_MORT ((uint16_t)0xFFFF) /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_MORT ((uint16_t)0xFFFF) /*!<CRC_MORT polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_MORT ((uint16_t)0xFFFF) /*!<Rx CRC_MORT Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_MORT ((uint16_t)0xFFFF) /*!<Tx CRC_MORT Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_MORT ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_MORT ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0_MORT ((uint16_t)0x0002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1_MORT ((uint16_t)0x0004) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL_MORT ((uint16_t)0x0008) /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_MORT ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC_MORT ((uint16_t)0x0080) /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_MORT ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE_MORT ((uint16_t)0x0400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_MORT ((uint16_t)0x0800) /*!<I2S mode selection */
+#if defined(STM32F413_423xx) || defined(STM32F446xx_MORT)
+#define SPI_I2SCFGR_ASTRTEN_MORT ((uint16_t)0x1000) /*!<Asynchronous start enable */
+#endif /* STM32F413_423xx */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_MORT ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_MORT ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_MORT ((uint16_t)0x0200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG_MORT */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+
+/**
+ * @brief EXTI0 configuration
+ */
+
+
+/**
+ * @brief EXTI1 configuration
+ */
+
+
+/**
+ * @brief EXTI2 configuration
+ */
+
+
+
+/**
+ * @brief EXTI3 configuration
+ */
+
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+
+/**
+ * @brief EXTI4 configuration
+ */
+
+
+/**
+ * @brief EXTI5 configuration
+ */
+
+
+/**
+ * @brief EXTI6 configuration
+ */
+
+
+/**
+ * @brief EXTI7 configuration
+ */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+
+/**
+ * @brief EXTI8 configuration
+ */
+
+
+/**
+ * @brief EXTI9 configuration
+ */
+
+
+/**
+ * @brief EXTI10 configuration
+ */
+
+
+/**
+ * @brief EXTI11 configuration
+ */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+
+/**
+ * @brief EXTI12 configuration
+ */
+
+
+/**
+ * @brief EXTI13 configuration
+ */
+
+
+/**
+ * @brief EXTI14 configuration
+ */
+
+/**
+ * @brief EXTI15 configuration
+ */
+
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+/****************** Bit definition for SYSCFG_CFGR register *****************/
+
+#endif /* STM32F412xG || STM32413_423xx */
+
+#if defined (STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+/****************** Bit definition for SYSCFG_CFGR2 register ****************/
+
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+
+#if defined(STM32F413_423xx)
+/****************** Bit definition for SYSCFG_MCHDLYCR register *****************/
+
+#endif /* STM32F413_423xx */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_MORT ((uint16_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS_MORT ((uint16_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS_MORT ((uint16_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM_MORT ((uint16_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR_MORT ((uint16_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS_MORT ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0_MORT ((uint16_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1_MORT ((uint16_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE_MORT ((uint16_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_MORT ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_MORT ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_MORT ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_MORT ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_MORT ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S_MORT ((uint16_t)0x0080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1_MORT ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_MORT ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_MORT ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_MORT ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_MORT ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_MORT ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_MORT ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_MORT ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0_MORT ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1_MORT ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2_MORT ((uint16_t)0x0004) /*!<Bit 2 */
+
+#define TIM_SMCR_TS_MORT ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM_MORT ((uint16_t)0x0080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_MORT ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2_MORT ((uint16_t)0x0400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3_MORT ((uint16_t)0x0800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS_MORT ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0_MORT ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1_MORT ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE_MORT ((uint16_t)0x4000) /*!<External clock enable */
+#define TIM_SMCR_ETP_MORT ((uint16_t)0x8000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_MORT ((uint16_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_MORT ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_MORT ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_MORT ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_MORT ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_MORT ((uint16_t)0x0020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE_MORT ((uint16_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_MORT ((uint16_t)0x0080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE_MORT ((uint16_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_MORT ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_MORT ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_MORT ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_MORT ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_MORT ((uint16_t)0x2000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE_MORT ((uint16_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_MORT ((uint16_t)0x0001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_MORT ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_MORT ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_MORT ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_MORT ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_MORT ((uint16_t)0x0020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF_MORT ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_MORT ((uint16_t)0x0080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_MORT ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_MORT ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_MORT ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_MORT ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_MORT ((uint8_t)0x01) /*!<Update Generation */
+#define TIM_EGR_CC1G_MORT ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_MORT ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_MORT ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_MORT ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_MORT ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_MORT ((uint8_t)0x40) /*!<Trigger Generation */
+#define TIM_EGR_BG_MORT ((uint8_t)0x80) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_MORT ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0_MORT ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1_MORT ((uint16_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE_MORT ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_MORT ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_MORT ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE_MORT ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_MORT ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE_MORT ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_MORT ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_MORT ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0_MORT ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1_MORT ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2_MORT ((uint16_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE_MORT ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_MORT ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0_MORT ((uint16_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1_MORT ((uint16_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F_MORT ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3_MORT ((uint16_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC_MORT ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0_MORT ((uint16_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1_MORT ((uint16_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F_MORT ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0_MORT ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1_MORT ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2_MORT ((uint16_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3_MORT ((uint16_t)0x8000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_MORT ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0_MORT ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1_MORT ((uint16_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE_MORT ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_MORT ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_MORT ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE_MORT ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_MORT ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE_MORT ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_MORT ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_MORT ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0_MORT ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1_MORT ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2_MORT ((uint16_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE_MORT ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_MORT ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0_MORT ((uint16_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1_MORT ((uint16_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F_MORT ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3_MORT ((uint16_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC_MORT ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0_MORT ((uint16_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1_MORT ((uint16_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F_MORT ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0_MORT ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1_MORT ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2_MORT ((uint16_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3_MORT ((uint16_t)0x8000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_MORT ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_MORT ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_MORT ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_MORT ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_MORT ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_MORT ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_MORT ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_MORT ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_MORT ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_MORT ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_MORT ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_MORT ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_MORT ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_MORT ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_MORT ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_MORT ((uint16_t)0xFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_MORT ((uint16_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_MORT ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP_MORT ((uint8_t)0xFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_MORT ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_MORT ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_MORT ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_MORT ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_MORT ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0_MORT ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1_MORT ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2_MORT ((uint16_t)0x0004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3_MORT ((uint16_t)0x0008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4_MORT ((uint16_t)0x0010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5_MORT ((uint16_t)0x0020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6_MORT ((uint16_t)0x0040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7_MORT ((uint16_t)0x0080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK_MORT ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI_MORT ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_MORT ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_MORT ((uint16_t)0x1000) /*!<Break enable */
+#define TIM_BDTR_BKP_MORT ((uint16_t)0x2000) /*!<Break Polarity */
+#define TIM_BDTR_AOE_MORT ((uint16_t)0x4000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_MORT ((uint16_t)0x8000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_MORT ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0_MORT ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1_MORT ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2_MORT ((uint16_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3_MORT ((uint16_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4_MORT ((uint16_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL_MORT ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2_MORT ((uint16_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3_MORT ((uint16_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4_MORT ((uint16_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_MORT ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP_MORT ((uint16_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5_MORT Input 4 remap) */
+#define TIM_OR_TI4_RMP_0_MORT ((uint16_t)0x0040) /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1_MORT ((uint16_t)0x0080) /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP_MORT ((uint16_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2_MORT Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0_MORT ((uint16_t)0x0400) /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1_MORT ((uint16_t)0x0800) /*!<Bit 1 */
+
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+
+/****************** Bit definition for LPTIM_IER register ********************/
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+
+
+/****************** Bit definition for LPTIM_CR register ********************/
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+
+/****************** Bit definition for LPTIM_OR register *******************/
+
+#endif /* STM32F410xx || STM32F413_423xx */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+
+/******************* Bit definition for USART_DR register *******************/
+
+/****************** Bit definition for USART_BRR register *******************/
+
+/****************** Bit definition for USART_CR1 register *******************/
+
+/****************** Bit definition for USART_CR2 register *******************/
+
+/****************** Bit definition for USART_CR3 register *******************/
+
+/****************** Bit definition for USART_GTPR register ******************/
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+
+/******************* Bit definition for WWDG_CFR register *******************/
+
+/******************* Bit definition for WWDG_SR register ********************/
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+
+
+/* Bit definition for Ethernet MAC Status Register */
+
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+
+
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+
+
+/**
+ *
+ */
+
+ /**
+ * @}
+ */
+
+#ifdef USE_STDPERIPH_DRIVER
+ #include "stm32f4xx_conf.h"
+#endif /* USE_STDPERIPH_DRIVER */
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+#define SET_BIT_MORT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT_MORT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT_MORT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG_MORT(REG) ((REG) = (0x0))
+
+#define WRITE_REG_MORT(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG_MORT(REG) ((REG))
+
+#define MODIFY_REG_MORT(REG, CLEARMASK, SETMASK) WRITE_REG_MORT((REG), (((READ_REG_MORT(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/stm32f4xx_rcc_mort.c Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,3197 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_rcc.c
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Reset and clock control (RCC) peripheral:
+ * + Internal/external clocks, PLL, CSS and MCO configuration
+ * + System, AHB and APB busses clocks configuration
+ * + Peripheral clocks configuration
+ * + Interrupts and flags management
+ *
+ @verbatim
+ ===============================================================================
+ ##### RCC specific features #####
+ ===============================================================================
+ [..]
+ After reset the device is running from Internal High Speed oscillator
+ (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
+ and I-Cache are disabled, and all peripherals are off except internal
+ SRAM, Flash and JTAG.
+ (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
+ all peripherals mapped on these busses are running at HSI speed.
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+ (+) All GPIOs are in input floating state, except the JTAG pins which
+ are assigned to be used for debug purpose.
+ [..]
+ Once the device started from reset, the user application has to:
+ (+) Configure the clock source to be used to drive the System clock
+ (if the application needs higher frequency/performance)
+ (+) Configure the System clock frequency and Flash settings
+ (+) Configure the AHB and APB busses prescalers
+ (+) Enable the clock for the peripheral(s) to be used
+ (+) Configure the clock source(s) for peripherals which clocks are not
+ derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_rcc_mort.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup RCC
+ * @brief RCC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+/* --- CR Register ---*/
+/* Alias word address of HSION bit */
+#define CR_OFFSET (RCC_OFFSET + 0x00)
+#define HSION_BitNumber_MORT 0x00
+#define CR_HSION_BB_MORT (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber_MORT 0x13
+#define CR_CSSON_BB_MORT (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber_MORT 0x18
+#define CR_PLLON_BB_MORT (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+/* Alias word address of PLLI2SON bit */
+#define PLLI2SON_BitNumber_MORT 0x1A
+#define CR_PLLI2SON_BB_MORT (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
+
+/* Alias word address of PLLSAION bit */
+#define PLLSAION_BitNumber_MORT 0x1C
+#define CR_PLLSAION_BB_MORT (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+/* Alias word address of I2SSRC bit */
+#define CFGR_OFFSET (RCC_OFFSET + 0x08)
+#define I2SSRC_BitNumber_MORT 0x17
+#define CFGR_I2SSRC_BB_MORT (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
+
+/* --- BDCR Register ---*/
+/* Alias word address of RTCEN bit */
+#define BDCR_OFFSET (RCC_OFFSET + 0x70)
+#define RTCEN_BitNumber_MORT 0x0F
+#define BDCR_RTCEN_BB_MORT (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber_MORT 0x10
+#define BDCR_BDRST_BB_MORT (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* --- CSR Register ---*/
+/* Alias word address of LSION bit */
+#define CSR_OFFSET (RCC_OFFSET + 0x74)
+#define LSION_BitNumber_MORT 0x00
+#define CSR_LSION_BB_MORT (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+/* --- DCKCFGR Register ---*/
+/* Alias word address of TIMPRE bit */
+#define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
+#define TIMPRE_BitNumber_MORT 0x18
+#define DCKCFGR_TIMPRE_BB_MORT (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+#define RCC_CFGR_OFFSET_MORT (RCC_OFFSET + 0x08)
+ #if defined(STM32F410xx)
+/* Alias word address of MCO1EN bit */
+#define RCC_MCO1EN_BIT_NUMBER 0x8
+#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
+
+/* Alias word address of MCO2EN bit */
+#define RCC_MCO2EN_BIT_NUMBER 0x9
+#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
+#endif /* STM32F410xx */
+/* ---------------------- RCC registers bit mask ------------------------ */
+/* CFGR register bit mask */
+#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)
+#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)
+
+/* RCC Flag Mask */
+#define FLAG_MASK ((uint8_t)0x1F)
+
+/* CR register byte 3 (Bits[23:16]) base address */
+#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define CIR_BYTE2_ADDRESS_MORT ((uint32_t)(RCC_BASE + 0x0C + 0x01))
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
+
+/* BDCR register base address */
+#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Private_Functions
+ * @{
+ */
+
+/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
+ * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
+ *
+@verbatim
+ ===================================================================================
+ ##### Internal and external clocks, PLL, CSS and MCO configuration functions #####
+ ===================================================================================
+ [..]
+ This section provide functions allowing to configure the internal/external clocks,
+ PLLs, CSS and MCO pins.
+
+ (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
+ the PLL as System clock source.
+
+ (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+ clock source.
+
+ (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
+ through the PLL as System clock source. Can be used also as RTC clock source.
+
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+ (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
+ (++) The first output is used to generate the high speed system clock (up to 168 MHz)
+ (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
+ the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
+
+ (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve
+ high-quality audio performance on the I2S interface or SAI interface in case
+ of STM32F429x/439x devices.
+
+ (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI
+ interface and LCD TFT controller available only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
+
+ (#) CSS (Clock security system), once enable and if a HSE clock failure occurs
+ (HSE used directly or through PLL as System clock source), the System clock
+ is automatically switched to HSI and an interrupt is generated if enabled.
+ The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
+ exception vector.
+
+ (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
+ clock (through a configurable prescaler) on PA8 pin.
+
+ (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
+ clock (through a configurable prescaler) on PC9 pin.
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE, PLL and PLLI2S OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS, MCO1 and MCO2 OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @param None
+ * @retval None
+ */
+void RCC_DeInit(void)
+{
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42xxx/43xxx/446xx/469xx/479xx devices) bits */
+ RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F413_423xx) || defined(STM32F469_479xx)
+ /* Reset PLLI2SCFGR register */
+ RCC->PLLI2SCFGR = 0x20003000;
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F413_423xx || STM32F469_479xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+ /* Reset PLLSAICFGR register, only available for STM32F42xxx/43xxx/446xx/469xx/479xx devices */
+ RCC->PLLSAICFGR = 0x24003000;
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+ /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx and STM32F413_423xx devices */
+ RCC->DCKCFGR = 0x00000000;
+
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+ /* Disable LPTIM and FMPI2C clock prescalers selection, only available for STM32F410xx and STM32F413_423xx devices */
+ RCC->DCKCFGR2 = 0x00000000;
+#endif /* STM32F410xx || STM32F413_423xx */
+}
+
+/**
+ * @brief Configures the External High Speed oscillator (HSE).
+ * @note After enabling the HSE (RCC_HSE_ON_MORT or RCC_HSE_Bypass), the application
+ * software should wait on HSERDY flag to be set indicating that HSE clock
+ * is stable and can be used to clock the PLL and/or system clock.
+ * @note HSE state can not be changed if it is used directly or through the
+ * PLL as system clock. In this case, you have to select another source
+ * of the system clock then change the HSE state (ex. disable it).
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
+ * @note This function reset the CSSON bit, so if the Clock security system(CSS)
+ * was previously enabled you have to enable it again after calling this
+ * function.
+ * @param RCC_HSE: specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_OFF_MORT: turn OFF the HSE oscillator, HSERDY flag goes low after
+ * 6 HSE oscillator clock cycles.
+ * @arg RCC_HSE_ON_MORT: turn ON the HSE oscillator
+ * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
+ * @retval None
+ */
+void RCC_HSEConfig(uint8_t RCC_HSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE_MORT(RCC_HSE));
+
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+ *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF_MORT;
+
+ /* Set the new HSE configuration -------------------------------------------*/
+ *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
+}
+
+/**
+ * @brief Waits for HSE start-up.
+ * @note This functions waits on HSERDY flag to be set and return SUCCESS if
+ * this flag is set, otherwise returns ERROR if the timeout is reached
+ * and this flag is not set. The timeout value is defined by the constant
+ * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending
+ * on the HSE crystal used in your application.
+ * @param None
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: HSE oscillator is stable and ready to use
+ * - ERROR: HSE oscillator not yet ready
+ */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+ __IO uint32_t startupcounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus hsestatus = RESET;
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+ startupcounter++;
+ } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
+
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * @param HSICalibrationValue: specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0x1F.
+ * @retval None
+ */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_CALIBRATION_VALUE_MORT(HSICalibrationValue));
+
+ tmpreg = RCC->CR;
+
+ /* Clear HSITRIM[4:0] bits */
+ tmpreg &= ~RCC_CR_HSITRIM_MORT;
+
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+ tmpreg |= (uint32_t)HSICalibrationValue << 3;
+
+ /* Store the new value */
+ RCC->CR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * It is used (enabled by hardware) as system clock source after startup
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+ * of the HSE used directly or indirectly as system clock (if the Clock
+ * Security System CSS is enabled).
+ * @note HSI can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI.
+ * @note After enabling the HSI, the application software should wait on HSIRDY
+ * flag to be set indicating that HSI clock is stable and can be used as
+ * system clock source.
+ * @param NewState: new state of the HSI.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ * @retval None
+ */
+void RCC_HSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE).
+ * @note As the LSE is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
+ * (to be done once after reset).
+ * @note After enabling the LSE (RCC_LSE_ON_MORT or RCC_LSE_Bypass), the application
+ * software should wait on LSERDY flag to be set indicating that LSE clock
+ * is stable and can be used to clock the RTC.
+ * @param RCC_LSE: specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_OFF_MORT: turn OFF the LSE oscillator, LSERDY flag goes low after
+ * 6 LSE oscillator clock cycles.
+ * @arg RCC_LSE_ON_MORT: turn ON the LSE oscillator
+ * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
+ * @retval None
+ */
+void RCC_LSEConfig(uint8_t RCC_LSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE_MORT(RCC_LSE));
+
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+ /* Reset LSEON bit */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF_MORT;
+
+ /* Reset LSEBYP bit */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF_MORT;
+
+ /* Configure LSE (RCC_LSE_OFF_MORT is already covered by the code section above) */
+ switch (RCC_LSE)
+ {
+ case RCC_LSE_ON_MORT:
+ /* Set LSEON bit */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON_MORT;
+ break;
+ case RCC_LSE_Bypass:
+ /* Set LSEBYP and LSEON bits */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON_MORT;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ * @note LSI can not be disabled if the IWDG is running.
+ * @param NewState: new state of the LSI.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ * @retval None
+ */
+void RCC_LSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
+}
+
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+/**
+ * @brief Configures the main PLL clock source, multiplication and division factors.
+ * @note This function must be used only when the main PLL is disabled.
+ *
+ * @param RCC_PLLSource: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+ *
+ * @param PLLM: specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between 0 and 63.
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLL jitter.
+ *
+ * @param PLLN: specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between 50 and 432.
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 100 and 432 MHz.
+ *
+ * @param PLLP: specifies the division factor for main system clock (SYSCLK)
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
+ * the System clock frequency.
+ *
+ * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
+ * This parameter must be a number between 4 and 15.
+ *
+ * @param PLLR: specifies the division factor for I2S, SAI, SYSTEM, SPDIF in STM32F446xx devices
+ * This parameter must be a number between 2 and 7.
+ *
+ * @note If the USB OTG FS is used in your application, you have to set the
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+ * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+ * correctly.
+ *
+ * @retval None
+ */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+ assert_param(IS_RCC_PLLM_VALUE_MORT(PLLM));
+ assert_param(IS_RCC_PLLN_VALUE(PLLN));
+ assert_param(IS_RCC_PLLP_VALUE_MORT(PLLP));
+ assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
+ assert_param(IS_RCC_PLLR_VALUE_MORT(PLLR));
+
+ RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
+ (PLLQ << 24) | (PLLR << 28);
+}
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
+/**
+ * @brief Configures the main PLL clock source, multiplication and division factors.
+ * @note This function must be used only when the main PLL is disabled.
+ *
+ * @param RCC_PLLSource: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+ *
+ * @param PLLM: specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between 0 and 63.
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLL jitter.
+ *
+ * @param PLLN: specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between 50 and 432.
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 100 and 432 MHz.
+ *
+ * @param PLLP: specifies the division factor for main system clock (SYSCLK)
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
+ * the System clock frequency.
+ *
+ * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
+ * This parameter must be a number between 4 and 15.
+ * @note If the USB OTG FS is used in your application, you have to set the
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+ * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+ * correctly.
+ *
+ * @retval None
+ */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+ assert_param(IS_RCC_PLLM_VALUE_MORT(PLLM));
+ assert_param(IS_RCC_PLLN_VALUE(PLLN));
+ assert_param(IS_RCC_PLLP_VALUE_MORT(PLLP));
+ assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
+
+ RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
+ (PLLQ << 24);
+}
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
+
+/**
+ * @brief Enables or disables the main PLL.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The main PLL can not be disabled if it is used as system clock source
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+ * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
+}
+
+#if defined(STM32F40_41xxx) || defined(STM32F401xx)
+/**
+ * @brief Configures the PLLI2S clock multiplication and division factors.
+ *
+ * @note This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx
+ * or STM32F401xx devices.
+ *
+ * @note This function must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * RCC_PLLConfig function )
+ *
+ * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between 50 and 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between 100 and 432 MHz.
+ *
+ * @param PLLI2SR: specifies the division factor for I2S clock
+ * This parameter must be a number between 2 and 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ *
+ * @retval None
+ */
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
+ assert_param(IS_RCC_PLLI2SR_VALUE_MORT(PLLI2SR));
+
+ RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
+}
+#endif /* STM32F40_41xxx || STM32F401xx */
+
+#if defined(STM32F411xE)
+/**
+ * @brief Configures the PLLI2S clock multiplication and division factors.
+ *
+ * @note This function can be used only for STM32F411xE devices.
+ *
+ * @note This function must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * RCC_PLLConfig function )
+ *
+ * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLLI2S jitter.
+ *
+ * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between 50 and 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between 100 and 432 MHz.
+ *
+ * @param PLLI2SR: specifies the division factor for I2S clock
+ * This parameter must be a number between 2 and 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ *
+ * @retval None
+ */
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
+ assert_param(IS_RCC_PLLI2SM_VALUE_MORT(PLLI2SM));
+ assert_param(IS_RCC_PLLI2SR_VALUE_MORT(PLLI2SR));
+
+ RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28) | PLLI2SM;
+}
+#endif /* STM32F411xE */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
+/**
+ * @brief Configures the PLLI2S clock multiplication and division factors.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx devices
+ *
+ * @note This function must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * RCC_PLLConfig function )
+ *
+ * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between 50 and 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between 100 and 432 MHz.
+ *
+ * @param PLLI2SQ: specifies the division factor for SAI1 clock
+ * This parameter must be a number between 2 and 15.
+ *
+ * @param PLLI2SR: specifies the division factor for I2S clock
+ * This parameter must be a number between 2 and 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ *
+ * @retval None
+ */
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ));
+ assert_param(IS_RCC_PLLI2SR_VALUE_MORT(PLLI2SR));
+
+ RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28);
+}
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
+
+#if defined(STM32F412xG ) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/**
+ * @brief Configures the PLLI2S clock multiplication and division factors.
+ *
+ * @note This function can be used only for STM32F446xx devices
+ *
+ * @note This function must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * RCC_PLLConfig function )
+ *
+ * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLLI2S jitter.
+ *
+ * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between 50 and 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between 100 and 432 MHz.
+ *
+ * @param PLLI2SP: specifies the division factor for PLL 48Mhz clock output
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ *
+ * @param PLLI2SQ: specifies the division factor for SAI1 clock
+ * This parameter must be a number between 2 and 15.
+ *
+ * @param PLLI2SR: specifies the division factor for I2S clock
+ * This parameter must be a number between 2 and 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ * @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices.
+ *
+ * @retval None
+ */
+void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLI2SM_VALUE_MORT(PLLI2SM));
+ assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
+ assert_param(IS_RCC_PLLI2SP_VALUE_MORT(PLLI2SP));
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ));
+ assert_param(IS_RCC_PLLI2SR_VALUE_MORT(PLLI2SR));
+
+ RCC->PLLI2SCFGR = PLLI2SM | (PLLI2SN << 6) | (((PLLI2SP >> 1) -1) << 16) | (PLLI2SQ << 24) | (PLLI2SR << 28);
+}
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+/**
+ * @brief Enables or disables the PLLI2S.
+ * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
+ * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLLI2SCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
+}
+
+#if defined(STM32F469_479xx)
+/**
+ * @brief Configures the PLLSAI clock multiplication and division factors.
+ *
+ * @note This function can be used only for STM32F469_479xx devices
+ *
+ * @note This function must be used only when the PLLSAI is disabled.
+ * @note PLLSAI clock source is common with the main PLL (configured in
+ * RCC_PLLConfig function )
+ *
+ * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
+ * This parameter must be a number between 50 and 432.
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
+ * output frequency is between 100 and 432 MHz.
+ *
+ * @param PLLSAIP: specifies the division factor for PLL 48Mhz clock output
+ * This parameter must be a number in the range {2, 4, 6, or 8}..
+ *
+ * @param PLLSAIQ: specifies the division factor for SAI1 clock
+ * This parameter must be a number between 2 and 15.
+ *
+ * @param PLLSAIR: specifies the division factor for LTDC clock
+ * This parameter must be a number between 2 and 7.
+ *
+ * @retval None
+ */
+void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSAIN_VALUE_MORT(PLLSAIN));
+ assert_param(IS_RCC_PLLSAIP_VALUE_MORT(PLLSAIP));
+ assert_param(IS_RCC_PLLSAIQ_VALUE_MORT(PLLSAIQ));
+ assert_param(IS_RCC_PLLSAIR_VALUE_MORT(PLLSAIR));
+
+ RCC->PLLSAICFGR = (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24) | (PLLSAIR << 28);
+}
+#endif /* STM32F469_479xx */
+
+#if defined(STM32F446xx)
+/**
+ * @brief Configures the PLLSAI clock multiplication and division factors.
+ *
+ * @note This function can be used only for STM32F446xx devices
+ *
+ * @note This function must be used only when the PLLSAI is disabled.
+ * @note PLLSAI clock source is common with the main PLL (configured in
+ * RCC_PLLConfig function )
+ *
+ * @param PLLSAIM: specifies the division factor for PLLSAI VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLLSAI jitter.
+ *
+ * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
+ * This parameter must be a number between 50 and 432.
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
+ * output frequency is between 100 and 432 MHz.
+ *
+ * @param PLLSAIP: specifies the division factor for PLL 48Mhz clock output
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ *
+ * @param PLLSAIQ: specifies the division factor for SAI1 clock
+ * This parameter must be a number between 2 and 15.
+ *
+ * @retval None
+ */
+void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSAIM_VALUE_MORT(PLLSAIM));
+ assert_param(IS_RCC_PLLSAIN_VALUE_MORT(PLLSAIN));
+ assert_param(IS_RCC_PLLSAIP_VALUE_MORT(PLLSAIP));
+ assert_param(IS_RCC_PLLSAIQ_VALUE_MORT(PLLSAIQ));
+
+ RCC->PLLSAICFGR = PLLSAIM | (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24);
+}
+#endif /* STM32F446xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
+/**
+ * @brief Configures the PLLSAI clock multiplication and division factors.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx devices
+ *
+ * @note This function must be used only when the PLLSAI is disabled.
+ * @note PLLSAI clock source is common with the main PLL (configured in
+ * RCC_PLLConfig function )
+ *
+ * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
+ * This parameter must be a number between 50 and 432.
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
+ * output frequency is between 100 and 432 MHz.
+ *
+ * @param PLLSAIQ: specifies the division factor for SAI1 clock
+ * This parameter must be a number between 2 and 15.
+ *
+ * @param PLLSAIR: specifies the division factor for LTDC clock
+ * This parameter must be a number between 2 and 7.
+ *
+ * @retval None
+ */
+void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSAIN_VALUE_MORT(PLLSAIN));
+ assert_param(IS_RCC_PLLSAIR_VALUE_MORT(PLLSAIR));
+ assert_param(IS_RCC_PLLSAIQ_VALUE_MORT(PLLSAIQ));
+
+ RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28);
+}
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
+
+/**
+ * @brief Enables or disables the PLLSAI.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices
+ *
+ * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
+ * @param NewState: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLLSAICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_PLLSAION_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the Clock Security System.
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator
+ * is automatically disabled and an interrupt is generated to inform the
+ * software about the failure (Clock Security System Interrupt, CSSI),
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+ * @param NewState: new state of the Clock Security System.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Selects the clock source to output on MCO1 pin(PA8).
+ * @note PA8 should be configured in alternate function mode.
+ * @param RCC_MCO1Source: specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
+ * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
+ * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
+ * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
+ * @param RCC_MCO1Div: specifies the MCO1 prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO1Div_1: no division applied to MCO1 clock
+ * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock
+ * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock
+ * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock
+ * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock
+ * @retval None
+ */
+void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO1SOURCE_MORT(RCC_MCO1Source));
+ assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
+ tmpreg &= CFGR_MCO1_RESET_MASK;
+
+ /* Select MCO1 clock source and prescaler */
+ tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+
+#if defined(STM32F410xx)
+ RCC_MCO1Cmd(ENABLE);
+#endif /* STM32F410xx */
+}
+
+/**
+ * @brief Selects the clock source to output on MCO2 pin(PC9).
+ * @note PC9 should be configured in alternate function mode.
+ * @param RCC_MCO2Source: specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+ * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
+ * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410xx devices
+ * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
+ * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
+ * @param RCC_MCO2Div: specifies the MCO2 prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO2Div_1: no division applied to MCO2 clock
+ * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock
+ * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
+ * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
+ * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
+ * @note For STM32F410xx devices to output I2SCLK clock on MCO2 you should have
+ * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
+ * @retval None
+ */
+void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO2SOURCE_MORT(RCC_MCO2Source));
+ assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear MCO2 and MCO2PRE[2:0] bits */
+ tmpreg &= CFGR_MCO2_RESET_MASK;
+
+ /* Select MCO2 clock source and prescaler */
+ tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+
+#if defined(STM32F410xx)
+ RCC_MCO2Cmd(ENABLE);
+#endif /* STM32F410xx */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
+ * @brief System, AHB and APB busses clocks configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### System, AHB and APB busses clocks configuration functions #####
+ ===============================================================================
+ [..]
+ This section provide functions allowing to configure the System, AHB, APB1 and
+ APB2 busses clocks.
+
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+ HSE and PLL.
+ The AHB clock (HCLK) is derived from System clock through configurable
+ prescaler and used to clock the CPU, memory and peripherals mapped
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+ from AHB clock through configurable prescalers and used to clock
+ the peripherals mapped on these busses. You can use
+ "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
+
+ -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
+ (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
+ from an external clock mapped on the I2S_CKIN pin.
+ You have to use RCC_I2SCLKConfig() function to configure this clock.
+ (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
+ divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
+ functions to configure this clock.
+ (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
+ to work correctly, while the SDIO require a frequency equal or lower than
+ to 48. This clock is derived of the main PLL through PLLQ divider.
+ (+@) IWDG clock which is always the LSI clock.
+
+ (#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency
+ of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending
+ on the device voltage range, the maximum frequency should be adapted accordingly:
+ +-------------------------------------------------------------------------------------+
+ | Latency | HCLK clock frequency (MHz) |
+ | |---------------------------------------------------------------------|
+ | | voltage range | voltage range | voltage range | voltage range |
+ | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
+ +---------------|----------------|----------------|-----------------|-----------------+
+ (#) For STM32F42xxx/43xxx/469xx/479xx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz,
+ PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum
+ frequency should be adapted accordingly:
+ +-------------------------------------------------------------------------------------+
+ | Latency | HCLK clock frequency (MHz) |
+ | |---------------------------------------------------------------------|
+ | | voltage range | voltage range | voltage range | voltage range |
+ | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168|
+ +-------------------------------------------------------------------------------------+
+
+ (#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
+ PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum
+ frequency should be adapted accordingly:
+ +-------------------------------------------------------------------------------------+
+ | Latency | HCLK clock frequency (MHz) |
+ | |---------------------------------------------------------------------|
+ | | voltage range | voltage range | voltage range | voltage range |
+ | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
+ +-------------------------------------------------------------------------------------+
+
+ (#) For STM32F410xx/STM32F411xE devices, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
+ PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum
+ frequency should be adapted accordingly:
+ +-------------------------------------------------------------------------------------+
+ | Latency | HCLK clock frequency (MHz) |
+ | |---------------------------------------------------------------------|
+ | | voltage range | voltage range | voltage range | voltage range |
+ | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 |
+ +-------------------------------------------------------------------------------------+
+
+ -@- On STM32F405xx/407xx and STM32F415xx/417xx devices:
+ (++) when VOS = '0', the maximum value of fHCLK = 144MHz.
+ (++) when VOS = '1', the maximum value of fHCLK = 168MHz.
+ [..]
+ On STM32F42xxx/43xxx/469xx/479xx devices:
+ (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz.
+ (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz.
+ (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz
+ [..]
+ On STM32F401x devices:
+ (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz.
+ (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz.
+ On STM32F410xx/STM32F411xE devices:
+ (++) when VOS[1:0] = '0x01' the maximum value of fHCLK is 64MHz.
+ (++) when VOS[1:0] = '0x10' the maximum value of fHCLK is 84MHz.
+ (++) when VOS[1:0] = '0x11' the maximum value of fHCLK is 100MHz.
+
+ You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the system clock (SYSCLK).
+ * @note The HSI is used (enabled by hardware) as system clock source after
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case
+ * of failure of the HSE used directly or indirectly as system clock
+ * (if the Clock Security System CSS is enabled).
+ * @note A switch from one clock source to another occurs only if the target
+ * clock source is ready (clock stable after startup delay or PLL locked).
+ * If a clock source which is not yet ready is selected, the switch will
+ * occur when the clock source will be ready.
+ * You can use RCC_GetSYSCLKSource() function to know which clock is
+ * currently used as system clock source.
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source (RCC_SYSCLKSource_PLLPCLK for STM32F446xx devices)
+ * @arg RCC_SYSCLKSource_PLLRCLK: PLL R selected as system clock source only for STM32F412xG, STM32F413_423xx and STM32F446xx devices
+ * @retval None
+ */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear SW[1:0] bits */
+ tmpreg &= ~RCC_CFGR_SW_MORT;
+
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+ tmpreg |= RCC_SYSCLKSource;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Returns the clock source used as system clock.
+ * @param None
+ * @retval The clock source used as system clock. The returned value can be one
+ * of the following:
+ * - 0x00: HSI used as system clock
+ * - 0x04: HSE used as system clock
+ * - 0x08: PLL used as system clock (PLL P for STM32F446xx devices)
+ * - 0x0C: PLL R used as system clock (only for STM32F412xG, STM32F413_423xx and STM32F446xx devices)
+ */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+ return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS_MORT));
+}
+
+/**
+ * @brief Configures the AHB clock (HCLK).
+ * @note Depending on the device voltage range, the software has to set correctly
+ * these bits to ensure that HCLK not exceed the maximum allowed frequency
+ * (for more details refer to section above
+ * "CPU, AHB and APB busses clocks configuration functions")
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
+ * the system clock (SYSCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
+ * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+ * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+ * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+ * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+ * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+ * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+ * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+ * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+ * @retval None
+ */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_HCLK_MORT(RCC_SYSCLK));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear HPRE[3:0] bits */
+ tmpreg &= ~RCC_CFGR_HPRE_MORT;
+
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+ tmpreg |= RCC_SYSCLK;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the Low Speed APB clock (PCLK1).
+ * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_Div1: APB1 clock = HCLK
+ * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
+ * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
+ * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
+ * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
+ * @retval None
+ */
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PCLK_MORT(RCC_HCLK));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear PPRE1[2:0] bits */
+ tmpreg &= ~RCC_CFGR_PPRE1_MORT;
+
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+ tmpreg |= RCC_HCLK;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the High Speed APB clock (PCLK2).
+ * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_Div1: APB2 clock = HCLK
+ * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
+ * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
+ * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
+ * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
+ * @retval None
+ */
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PCLK_MORT(RCC_HCLK));
+
+ tmpreg = RCC->CFGR;
+
+ /* Clear PPRE2[2:0] bits */
+ tmpreg &= ~RCC_CFGR_PPRE2_MORT;
+
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+ tmpreg |= RCC_HCLK << 3;
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK,
+ * PCLK1 and PCLK2.
+ *
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
+ * the clocks frequencies.
+ *
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other parameters.
+ * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
+ * must be called to update the structure's field. Otherwise, any
+ * configuration based on this function will be incorrect.
+ *
+ * @retval None
+ */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+ uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+ uint32_t pllr = 2;
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS_MORT;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock source */
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock source */
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+ break;
+ case 0x08: /* PLL P used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLP
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC_MORT) >> 22;
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM_MORT;
+
+ if (pllsource != 0)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN_MORT) >> 6);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN_MORT) >> 6);
+ }
+
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP_MORT) >>16) + 1 ) *2;
+ RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
+ break;
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+ case 0x0C: /* PLL R used as system clock source */
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC_MORT) >> 22;
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM_MORT;
+
+ if (pllsource != 0)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN_MORT) >> 6);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN_MORT) >> 6);
+ }
+
+ pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR_MORT) >>28) + 1 ) *2;
+ RCC_Clocks->SYSCLK_Frequency = pllvco/pllr;
+ break;
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+ default:
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
+
+ /* Get HCLK prescaler */
+ tmp = RCC->CFGR & RCC_CFGR_HPRE_MORT;
+ tmp = tmp >> 4;
+ presc = APBAHBPrescTable[tmp];
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+
+ /* Get PCLK1 prescaler */
+ tmp = RCC->CFGR & RCC_CFGR_PPRE1_MORT;
+ tmp = tmp >> 10;
+ presc = APBAHBPrescTable[tmp];
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+
+ /* Get PCLK2 prescaler */
+ tmp = RCC->CFGR & RCC_CFGR_PPRE2_MORT;
+ tmp = tmp >> 13;
+ presc = APBAHBPrescTable[tmp];
+ /* PCLK2 clock frequency */
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Group3 Peripheral clocks configuration functions
+ * @brief Peripheral clocks configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral clocks configuration functions #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the Peripheral clocks.
+
+ (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided
+ by 2 to 31.
+
+ (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
+ except internal SRAM, Flash and JTAG. Before to start using a peripheral
+ you have to enable its interface clock. You can do this using
+ RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
+
+ (#) To reset the peripherals configuration (to the default state after device reset)
+ you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
+ RCC_APB1PeriphResetCmd() functions.
+
+ (#) To further reduce power consumption in SLEEP mode the peripheral clocks
+ can be disabled prior to executing the WFI or WFE instructions.
+ You can do this using RCC_AHBPeriphClockLPModeCmd(),
+ RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the RTC clock (RTCCLK).
+ * @note As the RTC clock configuration bits are in the Backup domain and write
+ * access is denied to this domain after reset, you have to enable write
+ * access using PWR_BackupAccessCmd(ENABLE) function before to configure
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it can't be changed unless the
+ * Backup domain is reset using RCC_BackupResetCmd() function, or by
+ * a Power On Reset (POR).
+ *
+ * @param RCC_RTCCLKSource: specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+ * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+ * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected
+ * as RTC clock, where x:[2,31]
+ *
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
+ * work in STOP and STANDBY modes, and can be used as wakeup source.
+ * However, when the HSE clock is used as RTC clock source, the RTC
+ * cannot be used in STOP and STANDBY modes.
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
+ * RTC clock source).
+ *
+ * @retval None
+ */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_RTCCLK_SOURCE_MORT(RCC_RTCCLKSource));
+
+ if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
+ { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
+ tmpreg = RCC->CFGR;
+
+ /* Clear RTCPRE[4:0] bits */
+ tmpreg &= ~RCC_CFGR_RTCPRE_MORT;
+
+ /* Configure HSE division factor for RTC clock */
+ tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
+
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+ }
+
+ /* Select the RTC clock source */
+ RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
+}
+
+/**
+ * @brief Enables or disables the RTC clock.
+ * @note This function must be used only after the RTC clock source was selected
+ * using the RCC_RTCCLKConfig function.
+ * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Forces or releases the Backup domain reset.
+ * @note This function resets the RTC peripheral (including the backup registers)
+ * and the RTC clock source selection in RCC_CSR register.
+ * @note The BKPSRAM is not affected by this reset.
+ * @param NewState: new state of the Backup domain reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
+}
+
+#if defined (STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/**
+ * @brief Configures the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the I2S APB clock.
+ *
+ * @param RCC_I2SAPBx: specifies the APBx I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SBus_APB1: I2S peripheral instance is on APB1 Bus
+ * @arg RCC_I2SBus_APB2: I2S peripheral instance is on APB2 Bus
+ *
+ * @param RCC_I2SCLKSource: specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SCLKSource_PLLI2S: PLLI2S clock used as I2S clock source
+ * @arg RCC_I2SCLKSource_Ext: External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source
+ * @arg RCC_I2SCLKSource_PLL: PLL clock used as I2S clock source
+ * @arg RCC_I2SCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as I2S clock source
+ * @retval None
+ */
+void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
+ assert_param(IS_RCC_I2S_APBx(RCC_I2SAPBx));
+
+ if(RCC_I2SAPBx == RCC_I2SBus_APB1)
+ {
+ /* Clear APB1 I2Sx clock source selection bits */
+ RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S1SRC_MORT;
+ /* Set new APB1 I2Sx clock source*/
+ RCC->DCKCFGR |= RCC_I2SCLKSource;
+ }
+ else
+ {
+ /* Clear APB2 I2Sx clock source selection bits */
+ RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S2SRC_MORT;
+ /* Set new APB2 I2Sx clock source */
+ RCC->DCKCFGR |= (RCC_I2SCLKSource << 2);
+ }
+}
+#if defined(STM32F446xx)
+/**
+ * @brief Configures the SAIx clock source (SAIxCLK).
+ * @note This function must be called before enabling the SAIx APB clock.
+ *
+ * @param RCC_SAIInstance: specifies the SAIx clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIInstance_SAI1: SAI1 clock source selection
+ * @arg RCC_SAIInstance_SAI2: SAI2 clock source selections
+ *
+ * @param RCC_SAICLKSource: specifies the SAI clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAICLKSource_PLLSAI: PLLSAI clock used as SAI clock source
+ * @arg RCC_SAICLKSource_PLLI2S: PLLI2S clock used as SAI clock source
+ * @arg RCC_SAICLKSource_PLL: PLL clock used as SAI clock source
+ * @arg RCC_SAICLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
+ * @retval None
+ */
+void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_SAICLK_SOURCE(RCC_SAICLKSource));
+ assert_param(IS_RCC_SAI_INSTANCE(RCC_SAIInstance));
+
+ if(RCC_SAIInstance == RCC_SAIInstance_SAI1)
+ {
+ /* Clear SAI1 clock source selection bits */
+ RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI1SRC_MORT;
+ /* Set new SAI1 clock source */
+ RCC->DCKCFGR |= RCC_SAICLKSource;
+ }
+ else
+ {
+ /* Clear SAI2 clock source selection bits */
+ RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI2SRC_MORT;
+ /* Set new SAI2 clock source */
+ RCC->DCKCFGR |= (RCC_SAICLKSource << 2);
+ }
+}
+#endif /* STM32F446xx */
+
+#if defined(STM32F413_423xx)
+/**
+ * @brief Configures SAI1BlockA clock source selection.
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIACLKSource_PLLI2SR: PLLI2SR clock used as SAI clock source
+ * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S clock used as SAI clock source
+ * @arg RCC_SAIACLKSource_PLL: PLL clock used as SAI clock source
+ * @arg RCC_SAIACLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
+ * @retval None
+ */
+void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear RCC_DCKCFGR_SAI1ASRC_MORT[1:0] bits */
+ tmpreg &= ~RCC_DCKCFGR_SAI1ASRC_MORT;
+
+ /* Set SAI Block A source selection value */
+ tmpreg |= RCC_SAIBlockACLKSource;
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+
+/**
+ * @brief Configures SAI1BlockB clock source selection.
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIBCLKSource_PLLI2SR: PLLI2SR clock used as SAI clock source
+ * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S clock used as SAI clock source
+ * @arg RCC_SAIBCLKSource_PLL: PLL clock used as SAI clock source
+ * @arg RCC_SAIBCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
+ * @retval None
+ */
+void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear RCC_DCKCFGR_SAI1ASRC_MORT[1:0] bits */
+ tmpreg &= ~RCC_DCKCFGR_SAI1BSRC_MORT;
+
+ /* Set SAI Block B source selection value */
+ tmpreg |= RCC_SAIBlockBCLKSource;
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+#endif /* STM32F413_423xx */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+#if defined(STM32F410xx)
+/**
+ * @brief Configures the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the I2S clock.
+ *
+ * @param RCC_I2SCLKSource: specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
+ * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+ * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
+ * @retval None
+ */
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
+
+ /* Clear I2Sx clock source selection bits */
+ RCC->DCKCFGR &= ~RCC_DCKCFGR_I2SSRC;
+ /* Set new I2Sx clock source*/
+ RCC->DCKCFGR |= RCC_I2SCLKSource;
+}
+#endif /* STM32F410xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
+/**
+ * @brief Configures the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the I2S APB clock.
+ * @param RCC_I2SCLKSource: specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
+ * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source
+ * @retval None
+ */
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
+
+ *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
+}
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
+/**
+ * @brief Configures SAI1BlockA clock source selection.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.
+ *
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
+ * as SAI1 Block A clock
+ * @arg RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
+ * as SAI1 Block A clock
+ * @arg RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin
+ * used as SAI1 Block A clock
+ * @retval None
+ */
+void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear RCC_DCKCFGR_SAI1ASRC_MORT[1:0] bits */
+ tmpreg &= ~RCC_DCKCFGR_SAI1ASRC_MORT;
+
+ /* Set SAI Block A source selection value */
+ tmpreg |= RCC_SAIBlockACLKSource;
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+
+/**
+ * @brief Configures SAI1BlockB clock source selection.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.
+ *
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
+ * as SAI1 Block B clock
+ * @arg RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
+ * as SAI1 Block B clock
+ * @arg RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin
+ * used as SAI1 Block B clock
+ * @retval None
+ */
+void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear RCC_DCKCFGR_SAI1BSRC_MORT[1:0] bits */
+ tmpreg &= ~RCC_DCKCFGR_SAI1BSRC_MORT;
+
+ /* Set SAI Block B source selection value */
+ tmpreg |= RCC_SAIBlockBCLKSource;
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
+
+/**
+ * @brief Configures the SAI clock Divider coming from PLLI2S.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
+ *
+ * @note This function must be called before enabling the PLLI2S.
+ *
+ * @param RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock .
+ * This parameter must be a number between 1 and 32.
+ * SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ
+ *
+ * @retval None
+ */
+void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE_MORT(RCC_PLLI2SDivQ));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear PLLI2SDIVQ[4:0] bits */
+ tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ_MORT);
+
+ /* Set PLLI2SDIVQ values */
+ tmpreg |= (RCC_PLLI2SDivQ - 1);
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the SAI clock Divider coming from PLLSAI.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
+ *
+ * @note This function must be called before enabling the PLLSAI.
+ *
+ * @param RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock .
+ * This parameter must be a number between 1 and 32.
+ * SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ
+ *
+ * @retval None
+ */
+void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */
+ tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ_MORT);
+
+ /* Set PLLSAIDIVQ values */
+ tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8);
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+
+#if defined(STM32F413_423xx)
+/**
+ * @brief Configures the SAI clock Divider coming from PLLI2S.
+ *
+ * @note This function can be used only for STM32F413_423xx
+ *
+ * @param RCC_PLLI2SDivR: specifies the PLLI2S division factor for SAI1 clock.
+ * This parameter must be a number between 1 and 32.
+ * SAI1 clock frequency = f(PLLI2SR) / RCC_PLLI2SDivR
+ * @retval None
+ */
+void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLI2S_DIVR_VALUE(RCC_PLLI2SDivR));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear PLLI2SDIVR[4:0] bits */
+ tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVR);
+
+ /* Set PLLI2SDIVR values */
+ tmpreg |= (RCC_PLLI2SDivR-1);
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the SAI clock Divider coming from PLL.
+ *
+ * @note This function can be used only for STM32F413_423xx
+ *
+ * @note This function must be called before enabling the PLLSAI.
+ *
+ * @param RCC_PLLDivR: specifies the PLL division factor for SAI1 clock.
+ * This parameter must be a number between 1 and 32.
+ * SAI1 clock frequency = f(PLLR) / RCC_PLLDivR
+ *
+ * @retval None
+ */
+void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL_DIVR_VALUE(RCC_PLLDivR));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear PLLDIVR[12:8] */
+ tmpreg &= ~(RCC_DCKCFGR_PLLDIVR);
+
+ /* Set PLLDivR values */
+ tmpreg |= ((RCC_PLLDivR - 1 ) << 8);
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+#endif /* STM32F413_423xx */
+
+/**
+ * @brief Configures the LTDC clock Divider coming from PLLSAI.
+ *
+ * @note The LTDC peripheral is only available with STM32F42xxx/43xxx/446xx/469xx/479xx Devices.
+ *
+ * @note This function must be called before enabling the PLLSAI.
+ *
+ * @param RCC_PLLSAIDivR: specifies the PLLSAI division factor for LTDC clock .
+ * LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSAIDivR_Div2: LTDC clock = f(PLLSAI_R)/2
+ * @arg RCC_PLLSAIDivR_Div4: LTDC clock = f(PLLSAI_R)/4
+ * @arg RCC_PLLSAIDivR_Div8: LTDC clock = f(PLLSAI_R)/8
+ * @arg RCC_PLLSAIDivR_Div16: LTDC clock = f(PLLSAI_R)/16
+ *
+ * @retval None
+ */
+void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSAI_DIVR_VALUE_MORT(RCC_PLLSAIDivR));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear PLLSAIDIVR[2:0] bits */
+ tmpreg &= ~RCC_DCKCFGR_PLLSAIDIVR_MORT;
+
+ /* Set PLLSAIDIVR values */
+ tmpreg |= RCC_PLLSAIDivR;
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+/**
+ * @brief Configures the DFSDM clock source (DFSDMCLK).
+ * @note This function must be called before enabling the DFSDM APB clock.
+ * @param RCC_DFSDMCLKSource: specifies the DFSDM clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_DFSDMCLKSource_APB: APB clock used as DFSDM clock source.
+ * @arg RCC_DFSDMCLKSource_SYS: System clock used as DFSDM clock source.
+ *
+ * @retval None
+ */
+void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDMCLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_DFSDM1CLK_SOURCE(RCC_DFSDMCLKSource));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear CKDFSDM-SEL bit */
+ tmpreg &= ~RCC_DCKCFGR_CKDFSDM1SEL;
+
+ /* Set CKDFSDM-SEL bit according to RCC_DFSDMCLKSource value */
+ tmpreg |= (RCC_DFSDMCLKSource << 31) ;
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the DFSDM Audio clock source (DFSDMACLK).
+ * @note This function must be called before enabling the DFSDM APB clock.
+ * @param RCC_DFSDM1ACLKSource: specifies the DFSDM clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source.
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source.
+ *
+ * @retval None
+ */
+void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_DFSDMACLK_SOURCE(RCC_DFSDM1ACLKSource));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear CKDFSDMA SEL bit */
+ tmpreg &= ~RCC_DCKCFGR_CKDFSDM1ASEL;
+
+ /* Set CKDFSDM-SEL bt according to RCC_DFSDMCLKSource value */
+ tmpreg |= RCC_DFSDM1ACLKSource;
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+
+#if defined(STM32F413_423xx)
+/**
+ * @brief Configures the DFSDM Audio clock source (DFSDMACLK).
+ * @note This function must be called before enabling the DFSDM APB clock.
+ * @param RCC_DFSDM2ACLKSource: specifies the DFSDM clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source.
+ * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source.
+ *
+ * @retval None
+ */
+void RCC_DFSDM2ACLKConfig(uint32_t RCC_DFSDMACLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_DFSDMCLK_SOURCE(RCC_DFSDMACLKSource));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear CKDFSDMA SEL bit */
+ tmpreg &= ~RCC_DCKCFGR_CKDFSDM1ASEL;
+
+ /* Set CKDFSDM-SEL bt according to RCC_DFSDMCLKSource value */
+ tmpreg |= RCC_DFSDMACLKSource;
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+#endif /* STM32F413_423xx */
+#endif /* STM32F412xG || STM32F413_423xx */
+
+/**
+ * @brief Configures the Timers clocks prescalers selection.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
+ *
+ * @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection
+ * This parameter can be one of the following values:
+ * @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is
+ * equal to HPRE if PPREx is corresponding to division by 1 or 2,
+ * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
+ * division by 4 or more.
+ *
+ * @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is
+ * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
+ * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
+ * to division by 8 or more.
+ * @retval None
+ */
+void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler));
+
+ *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler;
+}
+
+/**
+ * @brief Enables or disables the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
+ * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
+ * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
+ * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
+ * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
+ * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
+ * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
+ * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
+ * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
+ * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
+ * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
+ * @arg RCC_AHB1Periph_CRC: CRC clock
+ * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
+ * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
+ * @arg RCC_AHB1Periph_DMA1: DMA1_MORT clock
+ * @arg RCC_AHB1Periph_DMA2: DMA2_MORT clock
+ * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
+ * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
+ * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
+ * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
+ * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
+ * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
+ * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
+
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->AHB1ENR |= RCC_AHB1Periph;
+ }
+ else
+ {
+ RCC->AHB1ENR &= ~RCC_AHB1Periph;
+ }
+}
+
+/**
+ * @brief Enables or disables the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHB2Periph_DCMI: DCMI clock
+ * @arg RCC_AHB2Periph_CRYP: CRYP clock
+ * @arg RCC_AHB2Periph_HASH: HASH clock
+ * @arg RCC_AHB2Periph_RNG: RNG clock
+ * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHB2ENR |= RCC_AHB2Periph;
+ }
+ else
+ {
+ RCC->AHB2ENR &= ~RCC_AHB2Periph;
+ }
+}
+
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+/**
+ * @brief Enables or disables the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
+ * This parameter must be:
+ * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices)
+ * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices)
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHB3ENR |= RCC_AHB3Periph;
+ }
+ else
+ {
+ RCC->AHB3ENR &= ~RCC_AHB3Periph;
+ }
+}
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
+
+/**
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1Periph_TIM2: TIM2 clock
+ * @arg RCC_APB1Periph_TIM3: TIM3 clock
+ * @arg RCC_APB1Periph_TIM4: TIM4 clock
+ * @arg RCC_APB1Periph_TIM5: TIM5 clock
+ * @arg RCC_APB1Periph_TIM6: TIM6 clock
+ * @arg RCC_APB1Periph_TIM7: TIM7 clock
+ * @arg RCC_APB1Periph_TIM12: TIM12 clock
+ * @arg RCC_APB1Periph_TIM13: TIM13 clock
+ * @arg RCC_APB1Periph_TIM14: TIM14 clock
+ * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices)
+ * @arg RCC_APB1Periph_WWDG: WWDG clock
+ * @arg RCC_APB1Periph_SPI2: SPI2 clock
+ * @arg RCC_APB1Periph_SPI3: SPI3 clock
+ * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
+ * @arg RCC_APB1Periph_USART2: USART2 clock
+ * @arg RCC_APB1Periph_USART3: USART3 clock
+ * @arg RCC_APB1Periph_UART4: UART4 clock
+ * @arg RCC_APB1Periph_UART5: UART5 clock
+ * @arg RCC_APB1Periph_I2C1: I2C1 clock
+ * @arg RCC_APB1Periph_I2C2: I2C2 clock
+ * @arg RCC_APB1Periph_I2C3: I2C3 clock
+ * @arg RCC_APB1Periph_FMPI2C1:FMPI2C1 clock
+ * @arg RCC_APB1Periph_CAN1: CAN1 clock
+ * @arg RCC_APB1Periph_CAN2: CAN2 clock
+ * @arg RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices)
+ * @arg RCC_APB1Periph_PWR: PWR clock
+ * @arg RCC_APB1Periph_DAC: DAC clock
+ * @arg RCC_APB1Periph_UART7: UART7 clock
+ * @arg RCC_APB1Periph_UART8: UART8 clock
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->APB1ENR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1ENR &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2Periph_TIM1: TIM1 clock
+ * @arg RCC_APB2Periph_TIM8: TIM8 clock
+ * @arg RCC_APB2Periph_USART1: USART1 clock
+ * @arg RCC_APB2Periph_USART6: USART6 clock
+ * @arg RCC_APB2Periph_ADC1: ADC1 clock
+ * @arg RCC_APB2Periph_ADC2: ADC2 clock
+ * @arg RCC_APB2Periph_ADC3: ADC3 clock
+ * @arg RCC_APB2Periph_SDIO: SDIO clock
+ * @arg RCC_APB2Periph_SPI1: SPI1 clock
+ * @arg RCC_APB2Periph_SPI4: SPI4 clock
+ * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
+ * @arg RCC_APB2Periph_EXTIT: EXTIIT clock
+ * @arg RCC_APB2Periph_TIM9: TIM9 clock
+ * @arg RCC_APB2Periph_TIM10: TIM10 clock
+ * @arg RCC_APB2Periph_TIM11: TIM11 clock
+ * @arg RCC_APB2Periph_SPI5: SPI5 clock
+ * @arg RCC_APB2Periph_SPI6: SPI6 clock
+ * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices)
+ * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
+ * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
+ * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
+ * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->APB2ENR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2ENR &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases AHB1 peripheral reset.
+ * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
+ * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
+ * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
+ * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
+ * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
+ * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
+ * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
+ * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
+ * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
+ * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
+ * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices)
+ * @arg RCC_AHB1Periph_CRC: CRC clock
+ * @arg RCC_AHB1Periph_DMA1: DMA1_MORT clock
+ * @arg RCC_AHB1Periph_DMA2: DMA2_MORT clock
+ * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
+ * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
+ * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
+ * @arg RCC_AHB1Periph_RNG: RNG clock for STM32F410xx devices
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHB1RSTR |= RCC_AHB1Periph;
+ }
+ else
+ {
+ RCC->AHB1RSTR &= ~RCC_AHB1Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases AHB2 peripheral reset.
+ * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHB2Periph_DCMI: DCMI clock
+ * @arg RCC_AHB2Periph_CRYP: CRYP clock
+ * @arg RCC_AHB2Periph_HASH: HASH clock
+ * @arg RCC_AHB2Periph_RNG: RNG clock for STM32F40_41xxx/STM32F412xG/STM32F413_423xx/STM32F427_437xx/STM32F429_439xx/STM32F469_479xx devices
+ * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHB2RSTR |= RCC_AHB2Periph;
+ }
+ else
+ {
+ RCC->AHB2RSTR &= ~RCC_AHB2Periph;
+ }
+}
+
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+/**
+ * @brief Forces or releases AHB3 peripheral reset.
+ * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
+ * This parameter must be:
+ * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG, STM32F413_423xx and STM32F429x/439x devices)
+ * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices)
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHB3RSTR |= RCC_AHB3Periph;
+ }
+ else
+ {
+ RCC->AHB3RSTR &= ~RCC_AHB3Periph;
+ }
+}
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
+
+/**
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1Periph_TIM2: TIM2 clock
+ * @arg RCC_APB1Periph_TIM3: TIM3 clock
+ * @arg RCC_APB1Periph_TIM4: TIM4 clock
+ * @arg RCC_APB1Periph_TIM5: TIM5 clock
+ * @arg RCC_APB1Periph_TIM6: TIM6 clock
+ * @arg RCC_APB1Periph_TIM7: TIM7 clock
+ * @arg RCC_APB1Periph_TIM12: TIM12 clock
+ * @arg RCC_APB1Periph_TIM13: TIM13 clock
+ * @arg RCC_APB1Periph_TIM14: TIM14 clock
+ * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices)
+ * @arg RCC_APB1Periph_WWDG: WWDG clock
+ * @arg RCC_APB1Periph_SPI2: SPI2 clock
+ * @arg RCC_APB1Periph_SPI3: SPI3 clock
+ * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
+ * @arg RCC_APB1Periph_USART2: USART2 clock
+ * @arg RCC_APB1Periph_USART3: USART3 clock
+ * @arg RCC_APB1Periph_UART4: UART4 clock
+ * @arg RCC_APB1Periph_UART5: UART5 clock
+ * @arg RCC_APB1Periph_I2C1: I2C1 clock
+ * @arg RCC_APB1Periph_I2C2: I2C2 clock
+ * @arg RCC_APB1Periph_I2C3: I2C3 clock
+ * @arg RCC_APB1Periph_FMPI2C1:FMPI2C1 clock
+ * @arg RCC_APB1Periph_CAN1: CAN1 clock
+ * @arg RCC_APB1Periph_CAN2: CAN2 clock
+ * @arg RCC_APB1Periph_CEC: CEC clock(STM32F446xx devices)
+ * @arg RCC_APB1Periph_PWR: PWR clock
+ * @arg RCC_APB1Periph_DAC: DAC clock
+ * @arg RCC_APB1Periph_UART7: UART7 clock
+ * @arg RCC_APB1Periph_UART8: UART8 clock
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB1RSTR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1RSTR &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2Periph_TIM1: TIM1 clock
+ * @arg RCC_APB2Periph_TIM8: TIM8 clock
+ * @arg RCC_APB2Periph_USART1: USART1 clock
+ * @arg RCC_APB2Periph_USART6: USART6 clock
+ * @arg RCC_APB2Periph_ADC1: ADC1 clock
+ * @arg RCC_APB2Periph_ADC2: ADC2 clock
+ * @arg RCC_APB2Periph_ADC3: ADC3 clock
+ * @arg RCC_APB2Periph_SDIO: SDIO clock
+ * @arg RCC_APB2Periph_SPI1: SPI1 clock
+ * @arg RCC_APB2Periph_SPI4: SPI4 clock
+ * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
+ * @arg RCC_APB2Periph_TIM9: TIM9 clock
+ * @arg RCC_APB2Periph_TIM10: TIM10 clock
+ * @arg RCC_APB2Periph_TIM11: TIM11 clock
+ * @arg RCC_APB2Periph_SPI5: SPI5 clock
+ * @arg RCC_APB2Periph_SPI6: SPI6 clock
+ * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices)
+ * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
+ * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
+ * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
+ * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB2RSTR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2RSTR &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
+ * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
+ * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
+ * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
+ * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
+ * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
+ * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
+ * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
+ * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
+ * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
+ * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
+ * @arg RCC_AHB1Periph_CRC: CRC clock
+ * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
+ * @arg RCC_AHB1Periph_DMA1: DMA1_MORT clock
+ * @arg RCC_AHB1Periph_DMA2: DMA2_MORT clock
+ * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
+ * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
+ * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
+ * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
+ * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
+ * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
+ * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->AHB1LPENR |= RCC_AHB1Periph;
+ }
+ else
+ {
+ RCC->AHB1LPENR &= ~RCC_AHB1Periph;
+ }
+}
+
+/**
+ * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHB2Periph_DCMI: DCMI clock
+ * @arg RCC_AHB2Periph_CRYP: CRYP clock
+ * @arg RCC_AHB2Periph_HASH: HASH clock
+ * @arg RCC_AHB2Periph_RNG: RNG clock
+ * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->AHB2LPENR |= RCC_AHB2Periph;
+ }
+ else
+ {
+ RCC->AHB2LPENR &= ~RCC_AHB2Periph;
+ }
+}
+
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+/**
+ * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
+ * This parameter must be:
+ * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices)
+ * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices)
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->AHB3LPENR |= RCC_AHB3Periph;
+ }
+ else
+ {
+ RCC->AHB3LPENR &= ~RCC_AHB3Periph;
+ }
+}
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
+
+/**
+ * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1Periph_TIM2: TIM2 clock
+ * @arg RCC_APB1Periph_TIM3: TIM3 clock
+ * @arg RCC_APB1Periph_TIM4: TIM4 clock
+ * @arg RCC_APB1Periph_TIM5: TIM5 clock
+ * @arg RCC_APB1Periph_TIM6: TIM6 clock
+ * @arg RCC_APB1Periph_TIM7: TIM7 clock
+ * @arg RCC_APB1Periph_TIM12: TIM12 clock
+ * @arg RCC_APB1Periph_TIM13: TIM13 clock
+ * @arg RCC_APB1Periph_TIM14: TIM14 clock
+ * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices)
+ * @arg RCC_APB1Periph_WWDG: WWDG clock
+ * @arg RCC_APB1Periph_SPI2: SPI2 clock
+ * @arg RCC_APB1Periph_SPI3: SPI3 clock
+ * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
+ * @arg RCC_APB1Periph_USART2: USART2 clock
+ * @arg RCC_APB1Periph_USART3: USART3 clock
+ * @arg RCC_APB1Periph_UART4: UART4 clock
+ * @arg RCC_APB1Periph_UART5: UART5 clock
+ * @arg RCC_APB1Periph_I2C1: I2C1 clock
+ * @arg RCC_APB1Periph_I2C2: I2C2 clock
+ * @arg RCC_APB1Periph_I2C3: I2C3 clock
+ * @arg RCC_APB1Periph_FMPI2C1: FMPI2C1 clock
+ * @arg RCC_APB1Periph_CAN1: CAN1 clock
+ * @arg RCC_APB1Periph_CAN2: CAN2 clock
+ * @arg RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices)
+ * @arg RCC_APB1Periph_PWR: PWR clock
+ * @arg RCC_APB1Periph_DAC: DAC clock
+ * @arg RCC_APB1Periph_UART7: UART7 clock
+ * @arg RCC_APB1Periph_UART8: UART8 clock
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB1LPENR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1LPENR &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2Periph_TIM1: TIM1 clock
+ * @arg RCC_APB2Periph_TIM8: TIM8 clock
+ * @arg RCC_APB2Periph_USART1: USART1 clock
+ * @arg RCC_APB2Periph_USART6: USART6 clock
+ * @arg RCC_APB2Periph_ADC1: ADC1 clock
+ * @arg RCC_APB2Periph_ADC2: ADC2 clock
+ * @arg RCC_APB2Periph_ADC3: ADC3 clock
+ * @arg RCC_APB2Periph_SDIO: SDIO clock
+ * @arg RCC_APB2Periph_SPI1: SPI1 clock
+ * @arg RCC_APB2Periph_SPI4: SPI4 clock
+ * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
+ * @arg RCC_APB2Periph_EXTIT: EXTIIT clock
+ * @arg RCC_APB2Periph_TIM9: TIM9 clock
+ * @arg RCC_APB2Periph_TIM10: TIM10 clock
+ * @arg RCC_APB2Periph_TIM11: TIM11 clock
+ * @arg RCC_APB2Periph_SPI5: SPI5 clock
+ * @arg RCC_APB2Periph_SPI6: SPI6 clock
+ * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices)
+ * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
+ * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
+ * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
+ * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB2LPENR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2LPENR &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Configures the External Low Speed oscillator mode (LSE mode).
+ * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices.
+ * @param Mode: specifies the LSE mode.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode.
+ * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode.
+ * @retval None
+ */
+void RCC_LSEModeConfig(uint8_t RCC_Mode)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE_MODE(RCC_Mode));
+
+ if(RCC_Mode == RCC_LSE_HIGHDRIVE_MODE)
+ {
+ SET_BIT_MORT(RCC->BDCR, RCC_BDCR_LSEMOD_MORT);
+ }
+ else
+ {
+ CLEAR_BIT_MORT(RCC->BDCR, RCC_BDCR_LSEMOD_MORT);
+ }
+}
+
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+/**
+ * @brief Configures the LPTIM1 clock Source.
+ * @note This feature is only available for STM32F410xx devices.
+ * @param RCC_ClockSource: specifies the LPTIM1 clock Source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK: LPTIM1 clock from APB1 selected.
+ * @arg RCC_LPTIM1CLKSOURCE_HSI: LPTIM1 clock from HSI selected.
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LPTIM1 clock from LSI selected.
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LPTIM1 clock from LSE selected.
+ * @retval None
+ */
+void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LPTIM1_CLOCKSOURCE(RCC_ClockSource));
+
+ /* Clear LPTIM1 clock source selection source bits */
+ RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_LPTIM1SEL;
+ /* Set new LPTIM1 clock source */
+ RCC->DCKCFGR2 |= RCC_ClockSource;
+}
+#endif /* STM32F410xx || STM32F413_423xx */
+
+#if defined(STM32F469_479xx)
+/**
+ * @brief Configures the DSI clock Source.
+ * @note This feature is only available for STM32F469_479xx devices.
+ * @param RCC_ClockSource: specifies the DSI clock Source.
+ * This parameter can be one of the following values:
+ * @arg RCC_DSICLKSource_PHY: DSI-PHY used as DSI byte lane clock source (usual case).
+ * @arg RCC_DSICLKSource_PLLR: PLL_R used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode).
+ * @retval None
+ */
+void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_DSI_CLOCKSOURCE(RCC_ClockSource));
+
+ if(RCC_ClockSource == RCC_DSICLKSource_PLLR)
+ {
+ SET_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL);
+ }
+ else
+ {
+ CLEAR_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL);
+ }
+}
+#endif /* STM32F469_479xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+/**
+ * @brief Configures the 48MHz clock Source.
+ * @note This feature is only available for STM32F446xx/STM32F469_479xx devices.
+ * @param RCC_ClockSource: specifies the 48MHz clock Source.
+ * This parameter can be one of the following values:
+ * @arg RCC_48MHZCLKSource_PLL: 48MHz from PLL selected.
+ * @arg RCC_48MHZCLKSource_PLLSAI: 48MHz from PLLSAI selected.
+ * @arg RCC_CK48CLKSOURCE_PLLI2SQ : 48MHz from PLLI2SQ
+ * @retval None
+ */
+void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_48MHZ_CLOCKSOURCE(RCC_ClockSource));
+#if defined(STM32F469_479xx)
+ if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
+ {
+ SET_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
+ }
+ else
+ {
+ CLEAR_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
+ }
+#elif defined(STM32F446xx)
+ if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
+ {
+ SET_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL_MORT);
+ }
+ else
+ {
+ CLEAR_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL_MORT);
+ }
+#elif defined(STM32F412xG) || defined(STM32F413_423xx)
+ if(RCC_ClockSource == RCC_CK48CLKSOURCE_PLLI2SQ)
+ {
+ SET_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL_MORT);
+ }
+ else
+ {
+ CLEAR_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL_MORT);
+ }
+#else
+#endif /* STM32F469_479xx */
+}
+
+/**
+ * @brief Configures the SDIO clock Source.
+ * @note This feature is only available for STM32F469_479xx/STM32F446xx devices.
+ * @param RCC_ClockSource: specifies the SDIO clock Source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SDIOCLKSource_48MHZ: 48MHz clock selected.
+ * @arg RCC_SDIOCLKSource_SYSCLK: system clock selected.
+ * @retval None
+ */
+void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_SDIO_CLOCKSOURCE(RCC_ClockSource));
+#if defined(STM32F469_479xx)
+ if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
+ {
+ SET_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL);
+ }
+ else
+ {
+ CLEAR_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL);
+ }
+#elif defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+ if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
+ {
+ SET_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL_MORT);
+ }
+ else
+ {
+ CLEAR_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL_MORT);
+ }
+#else
+#endif /* STM32F469_479xx */
+}
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F446xx)
+/**
+ * @brief Enables or disables the AHB1 clock gating for the specified IPs.
+ * @note This feature is only available for STM32F446xx devices.
+ * @param RCC_AHB1ClockGating: specifies the AHB1 clock gating.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHB1ClockGating_APB1Bridge: AHB1 to APB1 clock
+ * @arg RCC_AHB1ClockGating_APB2Bridge: AHB1 to APB2 clock
+ * @arg RCC_AHB1ClockGating_CM4DBG: Cortex M4 ETM clock
+ * @arg RCC_AHB1ClockGating_SPARE: Spare clock
+ * @arg RCC_AHB1ClockGating_SRAM: SRAM controller clock
+ * @arg RCC_AHB1ClockGating_FLITF: Flash interface clock
+ * @arg RCC_AHB1ClockGating_RCC: RCC clock
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB1_CLOCKGATING(RCC_AHB1ClockGating));
+
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->CKGATENR &= ~RCC_AHB1ClockGating;
+ }
+ else
+ {
+ RCC->CKGATENR |= RCC_AHB1ClockGating;
+ }
+}
+
+/**
+ * @brief Configures the SPDIFRX clock Source.
+ * @note This feature is only available for STM32F446xx devices.
+ * @param RCC_ClockSource: specifies the SPDIFRX clock Source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SPDIFRXCLKSource_PLLR: SPDIFRX clock from PLL_R selected.
+ * @arg RCC_SPDIFRXCLKSource_PLLI2SP: SPDIFRX clock from PLLI2S_P selected.
+ * @retval None
+ */
+void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_SPDIFRX_CLOCKSOURCE(RCC_ClockSource));
+
+ if(RCC_ClockSource == RCC_SPDIFRXCLKSource_PLLI2SP)
+ {
+ SET_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL_MORT);
+ }
+ else
+ {
+ CLEAR_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL_MORT);
+ }
+}
+
+/**
+ * @brief Configures the CEC clock Source.
+ * @note This feature is only available for STM32F446xx devices.
+ * @param RCC_ClockSource: specifies the CEC clock Source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CECCLKSource_HSIDiv488: CEC clock from HSI/488 selected.
+ * @arg RCC_CECCLKSource_LSE: CEC clock from LSE selected.
+ * @retval None
+ */
+void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_CEC_CLOCKSOURCE(RCC_ClockSource));
+
+ if(RCC_ClockSource == RCC_CECCLKSource_LSE)
+ {
+ SET_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL_MORT);
+ }
+ else
+ {
+ CLEAR_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL_MORT);
+ }
+}
+#endif /* STM32F446xx */
+
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/**
+ * @brief Configures the FMPI2C1 clock Source.
+ * @note This feature is only available for STM32F446xx devices.
+ * @param RCC_ClockSource: specifies the FMPI2C1 clock Source.
+ * This parameter can be one of the following values:
+ * @arg RCC_FMPI2C1CLKSource_APB1: FMPI2C1 clock from APB1 selected.
+ * @arg RCC_FMPI2C1CLKSource_SYSCLK: FMPI2C1 clock from Sytem clock selected.
+ * @arg RCC_FMPI2C1CLKSource_HSI: FMPI2C1 clock from HSI selected.
+ * @retval None
+ */
+void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_FMPI2C1_CLOCKSOURCE(RCC_ClockSource));
+
+ /* Clear FMPI2C1 clock source selection source bits */
+ RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_FMPI2C1SEL_MORT;
+ /* Set new FMPI2C1 clock source */
+ RCC->DCKCFGR2 |= RCC_ClockSource;
+}
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
+/**
+ * @}
+ */
+
+#if defined(STM32F410xx)
+/**
+ * @brief Enables or disables the MCO1.
+ * @param NewState: new state of the MCO1.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_MCO1Cmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the MCO2.
+ * @param NewState: new state of the MCO2.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_MCO2Cmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = (uint32_t)NewState;
+}
+#endif /* STM32F410xx */
+
+/** @defgroup RCC_Group4 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified RCC interrupts.
+ * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
+ * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
+ * @param NewState: new state of the specified RCC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_IT(RCC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
+ }
+ else
+ {
+ /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
+ }
+}
+
+/**
+ * @brief Checks whether the specified RCC flag is set or not.
+ * @param RCC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+ * @arg RCC_FLAG_PLLRDY: main PLL clock ready
+ * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
+ * @arg RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+ * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
+ * @arg RCC_FLAG_PINRST: Pin reset
+ * @arg RCC_FLAG_PORRST: POR/PDR reset
+ * @arg RCC_FLAG_SFTRST: Software reset
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+ * @arg RCC_FLAG_LPWRRST: Low Power reset
+ * @retval The new state of RCC_FLAG (SET or RESET).
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+ uint32_t tmp = 0;
+ uint32_t statusreg = 0;
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+ /* Get the RCC register index */
+ tmp = RCC_FLAG >> 5;
+ if (tmp == 1) /* The flag to check is in CR register */
+ {
+ statusreg = RCC->CR;
+ }
+ else if (tmp == 2) /* The flag to check is in BDCR register */
+ {
+ statusreg = RCC->BDCR;
+ }
+ else /* The flag to check is in CSR register */
+ {
+ statusreg = RCC->CSR;
+ }
+
+ /* Get the flag position */
+ tmp = RCC_FLAG & FLAG_MASK;
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC reset flags.
+ * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+ * @param None
+ * @retval None
+ */
+void RCC_ClearFlag(void)
+{
+ /* Set RMVF bit to clear the reset flags */
+ RCC->CSR |= RCC_CSR_RMVF_MORT;
+}
+
+/**
+ * @brief Checks whether the specified RCC interrupt has occurred or not.
+ * @param RCC_IT: specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
+ * @arg RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @retval The new state of RCC_IT (SET or RESET).
+ */
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+ ITStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_GET_IT(RCC_IT));
+
+ /* Check the status of the specified RCC interrupt */
+ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the RCC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC's interrupt pending bits.
+ * @param RCC_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
+ * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @retval None
+ */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));
+
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
+ pending bits */
+ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/stm32f4xx_rcc_mort.h Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,1071 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_rcc.h
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file contains all the functions prototypes for the RCC firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_RCC_H_MORT
+#define __STM32F4xx_RCC_H_MORT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_mort2.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+typedef struct
+{
+ uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
+ uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
+ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
+ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
+}RCC_ClocksTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RCC_HSE_configuration
+ * @{
+ */
+#define RCC_HSE_OFF_MORT ((uint8_t)0x00)
+#define RCC_HSE_ON_MORT ((uint8_t)0x01)
+#define RCC_HSE_Bypass ((uint8_t)0x05)
+#define IS_RCC_HSE_MORT(HSE) (((HSE) == RCC_HSE_OFF_MORT) || ((HSE) == RCC_HSE_ON_MORT) || \
+ ((HSE) == RCC_HSE_Bypass))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Dual_Mode_Selection
+ * @{
+ */
+#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
+#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
+#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
+ ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLLSAIDivR_Factor
+ * @{
+ */
+#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
+#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
+#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
+#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
+#define IS_RCC_PLLSAI_DIVR_VALUE_MORT(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
+ ((VALUE) == RCC_PLLSAIDivR_Div4) ||\
+ ((VALUE) == RCC_PLLSAIDivR_Div8) ||\
+ ((VALUE) == RCC_PLLSAIDivR_Div16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Clock_Source
+ * @{
+ */
+#define RCC_PLLSource_HSI ((uint32_t)0x00000000)
+#define RCC_PLLSource_HSE ((uint32_t)0x00400000)
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
+ ((SOURCE) == RCC_PLLSource_HSE))
+#define IS_RCC_PLLM_VALUE_MORT(VALUE) ((VALUE) <= 63)
+#define IS_RCC_PLLN_VALUE_MORT(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLP_VALUE_MORT(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+#define IS_RCC_PLLQ_VALUE_MORT(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+#define IS_RCC_PLLR_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+
+#define IS_RCC_PLLI2SN_VALUE_MORT(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLI2SR_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+#define IS_RCC_PLLI2SM_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
+#define IS_RCC_PLLI2SQ_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+#if defined(STM32F446xx)
+#define IS_RCC_PLLI2SP_VALUE_MORT(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+#define IS_RCC_PLLSAIM_VALUE_MORT(VALUE) ((VALUE) <= 63)
+#elif defined(STM32F412xG) || defined(STM32F413_423xx)
+#define IS_RCC_PLLI2SP_VALUE_MORT(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+#else
+#endif /* STM32F446xx */
+#define IS_RCC_PLLSAIN_VALUE_MORT(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
+#if defined(STM32F446xx) || defined(STM32F469_479xx)
+#define IS_RCC_PLLSAIP_VALUE_MORT(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+#endif /* STM32F446xx || STM32F469_479xx */
+#define IS_RCC_PLLSAIQ_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+#define IS_RCC_PLLSAIR_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+
+#define IS_RCC_PLLSAI_DIVQ_VALUE_MORT(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+#define IS_RCC_PLLI2S_DIVQ_VALUE_MORT(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+
+#if defined(STM32F413_423xx)
+#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+#endif /* STM32F413_423xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source
+ * @{
+ */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)
+#define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003)
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \
+ ((SOURCE) == RCC_SYSCLKSource_PLLRCLK))
+/* Add legacy definition */
+#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK
+#endif /* STM32F446xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
+#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source
+ * @{
+ */
+#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
+#define IS_RCC_HCLK_MORT(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+ ((HCLK) == RCC_SYSCLK_Div512))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_APB2_Clock_Source
+ * @{
+ */
+#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2 ((uint32_t)0x00001000)
+#define RCC_HCLK_Div4 ((uint32_t)0x00001400)
+#define RCC_HCLK_Div8 ((uint32_t)0x00001800)
+#define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
+#define IS_RCC_PCLK_MORT(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+ ((PCLK) == RCC_HCLK_Div16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt_Source
+ * @{
+ */
+#define RCC_IT_LSIRDY ((uint8_t)0x01)
+#define RCC_IT_LSERDY ((uint8_t)0x02)
+#define RCC_IT_HSIRDY ((uint8_t)0x04)
+#define RCC_IT_HSERDY ((uint8_t)0x08)
+#define RCC_IT_PLLRDY ((uint8_t)0x10)
+#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
+#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
+#define RCC_IT_CSS ((uint8_t)0x80)
+
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
+ ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
+#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Configuration
+ * @{
+ */
+#define RCC_LSE_OFF_MORT ((uint8_t)0x00)
+#define RCC_LSE_ON_MORT ((uint8_t)0x01)
+#define RCC_LSE_Bypass ((uint8_t)0x04)
+#define IS_RCC_LSE_MORT(LSE) (((LSE) == RCC_LSE_OFF_MORT) || ((LSE) == RCC_LSE_ON_MORT) || \
+ ((LSE) == RCC_LSE_Bypass))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source
+ * @{
+ */
+#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
+#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
+#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
+#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
+#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
+#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
+#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
+#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
+#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
+#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
+#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
+#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
+#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
+#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
+#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
+#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
+#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
+#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
+#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
+#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
+#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
+#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
+#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
+#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
+#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
+#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
+#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
+#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
+#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
+#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
+#define IS_RCC_RTCCLK_SOURCE_MORT(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
+/**
+ * @}
+ */
+
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
+ * @{
+ */
+#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
+#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
+#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
+
+#define IS_RCC_LPTIM1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
+/* Legacy Defines */
+#define IS_RCC_LPTIM1_SOURCE IS_RCC_LPTIM1_CLOCKSOURCE
+
+#if defined(STM32F410xx)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
+ * @{
+ */
+#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000)
+#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
+#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
+#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \
+ ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
+/**
+ * @}
+ */
+#endif /* STM32F413_423xx */
+#endif /* STM32F410xx || STM32F413_423xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/** @defgroup RCC_I2S_Clock_Source
+ * @{
+ */
+#define RCC_I2SCLKSource_PLLI2S ((uint32_t)0x00)
+#define RCC_I2SCLKSource_Ext ((uint32_t)RCC_DCKCFGR_I2S1SRC_0_MORT)
+#define RCC_I2SCLKSource_PLL ((uint32_t)RCC_DCKCFGR_I2S1SRC_1_MORT)
+#define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0_MORT | RCC_DCKCFGR_I2S1SRC_1_MORT)
+
+#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \
+ ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_I2S_APBBus
+ * @{
+ */
+#define RCC_I2SBus_APB1 ((uint8_t)0x00)
+#define RCC_I2SBus_APB2 ((uint8_t)0x01)
+#define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2))
+/**
+ * @}
+ */
+#if defined(STM32F446xx)
+/** @defgroup RCC_SAI_Clock_Source
+ * @{
+ */
+#define RCC_SAICLKSource_PLLSAI ((uint32_t)0x00)
+#define RCC_SAICLKSource_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0_MORT)
+#define RCC_SAICLKSource_PLL ((uint32_t)RCC_DCKCFGR_SAI1SRC_1_MORT)
+#define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0_MORT | RCC_DCKCFGR_SAI1SRC_1_MORT)
+
+#define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \
+ ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_SAI_Instance
+ * @{
+ */
+#define RCC_SAIInstance_SAI1 ((uint8_t)0x00)
+#define RCC_SAIInstance_SAI2 ((uint8_t)0x01)
+#define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2))
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+#if defined(STM32F413_423xx)
+
+/** @defgroup RCC_SAI_BlockA_Clock_Source
+ * @{
+ */
+#define RCC_SAIACLKSource_PLLI2S_R ((uint32_t)0x00000000)
+#define RCC_SAIACLKSource_I2SCKIN ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0_MORT)
+#define RCC_SAIACLKSource_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1_MORT)
+#define RCC_SAIACLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0_MORT | RCC_DCKCFGR_SAI1ASRC_1_MORT)
+
+#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S_R) || ((SOURCE) == RCC_SAIACLKSource_I2SCKIN) || \
+ ((SOURCE) == RCC_SAIACLKSource_PLLR) || ((SOURCE) == RCC_SAIACLKSource_HSI_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_SAI_BlockB_Clock_Source
+ * @{
+ */
+#define RCC_SAIBCLKSource_PLLI2S_R ((uint32_t)0x00000000)
+#define RCC_SAIBCLKSource_I2SCKIN ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0_MORT)
+#define RCC_SAIBCLKSource_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1_MORT)
+#define RCC_SAIBCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0_MORT | RCC_DCKCFGR_SAI1BSRC_1_MORT)
+
+#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S_R) || ((SOURCE) == RCC_SAIBCLKSource_I2SCKIN) || \
+ ((SOURCE) == RCC_SAIBCLKSource_PLLR) || ((SOURCE) == RCC_SAIBCLKSource_HSI_HSE))
+/**
+ * @}
+ */
+#endif /* STM32F413_423xx */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
+/** @defgroup RCC_I2S_Clock_Source
+ * @{
+ */
+#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
+#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
+
+#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_SAI_BlockA_Clock_Source
+ * @{
+ */
+#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
+#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)
+#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)
+
+#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
+ ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
+ ((SOURCE) == RCC_SAIACLKSource_Ext))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_SAI_BlockB_Clock_Source
+ * @{
+ */
+#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)
+#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)
+#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)
+
+#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
+ ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
+ ((SOURCE) == RCC_SAIBCLKSource_Ext))
+/**
+ * @}
+ */
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
+
+/** @defgroup RCC_TIM_PRescaler_Selection
+ * @{
+ */
+#define RCC_TIMPrescDesactivated ((uint8_t)0x00)
+#define RCC_TIMPrescActivated ((uint8_t)0x01)
+
+#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
+/**
+ * @}
+ */
+
+#if defined(STM32F469_479xx)
+/** @defgroup RCC_DSI_Clock_Source_Selection
+ * @{
+ */
+#define RCC_DSICLKSource_PHY ((uint8_t)0x00)
+#define RCC_DSICLKSource_PLLR ((uint8_t)0x01)
+#define IS_RCC_DSI_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_DSICLKSource_PHY) || \
+ ((CLKSOURCE) == RCC_DSICLKSource_PLLR))
+/**
+ * @}
+ */
+#endif /* STM32F469_479xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+/** @defgroup RCC_SDIO_Clock_Source_Selection
+ * @{
+ */
+#define RCC_SDIOCLKSource_48MHZ ((uint8_t)0x00)
+#define RCC_SDIOCLKSource_SYSCLK ((uint8_t)0x01)
+#define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \
+ ((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_48MHZ_Clock_Source_Selection
+ * @{
+ */
+#if defined(STM32F446xx) || defined(STM32F469_479xx)
+#define RCC_48MHZCLKSource_PLL ((uint8_t)0x00)
+#define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01)
+#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \
+ ((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI))
+#endif /* STM32F446xx || STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define RCC_CK48CLKSOURCE_PLLQ ((uint8_t)0x00)
+#define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG and STM32F413_423xx Devices */
+#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \
+ ((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ))
+#endif /* STM32F412xG || STM32F413_423xx */
+/**
+ * @}
+ */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F446xx)
+/** @defgroup RCC_SPDIFRX_Clock_Source_Selection
+ * @{
+ */
+#define RCC_SPDIFRXCLKSource_PLLR ((uint8_t)0x00)
+#define RCC_SPDIFRXCLKSource_PLLI2SP ((uint8_t)0x01)
+#define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \
+ ((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_CEC_Clock_Source_Selection
+ * @{
+ */
+#define RCC_CECCLKSource_HSIDiv488 ((uint8_t)0x00)
+#define RCC_CECCLKSource_LSE ((uint8_t)0x01)
+#define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \
+ ((CLKSOURCE) == RCC_CECCLKSource_LSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB1_ClockGating
+ * @{
+ */
+#define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001)
+#define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002)
+#define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004)
+#define RCC_AHB1ClockGating_SPARE ((uint32_t)0x00000008)
+#define RCC_AHB1ClockGating_SRAM ((uint32_t)0x00000010)
+#define RCC_AHB1ClockGating_FLITF ((uint32_t)0x00000020)
+#define RCC_AHB1ClockGating_RCC ((uint32_t)0x00000040)
+
+#define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/** @defgroup RCC_FMPI2C1_Clock_Source
+ * @{
+ */
+#define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00)
+#define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0_MORT)
+#define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1_MORT)
+
+#define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \
+ ((SOURCE) == RCC_FMPI2C1CLKSource_HSI))
+/**
+ * @}
+ */
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+/** @defgroup RCC_DFSDM_Clock_Source
+ * @{
+ */
+#define RCC_DFSDMCLKSource_APB ((uint8_t)0x00)
+#define RCC_DFSDMCLKSource_SYS ((uint8_t)0x01)
+#define IS_RCC_DFSDMCLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDMCLKSource_APB) || ((SOURCE) == RCC_DFSDMCLKSource_SYS))
+
+/* Legacy Defines */
+#define RCC_DFSDM1CLKSource_APB RCC_DFSDMCLKSource_APB
+#define RCC_DFSDM1CLKSource_SYS RCC_DFSDMCLKSource_SYS
+#define IS_RCC_DFSDM1CLK_SOURCE IS_RCC_DFSDMCLK_SOURCE
+/**
+ * @}
+ */
+
+/** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source
+ * @{
+ */
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000)
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
+#define IS_RCC_DFSDM1ACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2))
+
+/* Legacy Defines */
+#define IS_RCC_DFSDMACLK_SOURCE IS_RCC_DFSDM1ACLK_SOURCE
+/**
+ * @}
+ */
+
+#if defined(STM32F413_423xx)
+/** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source
+ * @{
+ */
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000)
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
+#define IS_RCC_DFSDM2ACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2))
+/**
+ * @}
+ */
+#endif /* STM32F413_423xx */
+#endif /* STM32F412xG || STM32F413_423xx */
+
+/** @defgroup RCC_AHB1_Peripherals
+ * @{
+ */
+#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
+#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
+#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
+#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
+#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
+#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
+#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
+#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
+#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
+#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
+#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
+#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
+#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
+#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
+#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
+#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
+#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)
+#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
+#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
+#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
+#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
+#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
+#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
+#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
+#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
+#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
+#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
+#if defined(STM32F410xx)
+#define RCC_AHB1Periph_RNG ((uint32_t)0x80000000)
+#endif /* STM32F410xx */
+#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB2_Peripherals
+ * @{
+ */
+#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
+#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
+#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
+#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
+#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
+#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB3_Peripherals
+ * @{
+ */
+#if defined(STM32F40_41xxx)
+#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
+#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
+#endif /* STM32F40_41xxx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
+#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
+#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
+#endif /* STM32F427_437xx || STM32F429_439xx */
+
+#if defined(STM32F446xx) || defined(STM32F469_479xx)
+#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
+#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
+#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
+#endif /* STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
+#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
+#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
+#endif /* STM32F412xG || STM32F413_423xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Peripherals
+ * @{
+ */
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
+#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
+#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
+#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+#define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200)
+#endif /* STM32F410xx || STM32F413_423xx */
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
+#if defined(STM32F446xx)
+#define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000)
+#endif /* STM32F446xx */
+#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
+#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+#define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000)
+#endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/
+#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
+#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
+#if defined(STM32F413_423xx)
+#define RCC_APB1Periph_CAN3 ((uint32_t)0x08000000)
+#endif /* STM32F413_423xx */
+#if defined(STM32F446xx)
+#define RCC_APB1Periph_CEC ((uint32_t)0x08000000)
+#endif /* STM32F446xx */
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
+#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
+#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Peripherals
+ * @{
+ */
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
+#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
+#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
+#define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
+#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
+#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
+#define RCC_APB2Periph_EXTIT ((uint32_t)0x00008000)
+#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
+#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
+#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
+#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
+#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
+#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)
+#if defined(STM32F446xx) || defined(STM32F469_479xx)
+#define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000)
+#endif /* STM32F446xx || STM32F469_479xx */
+#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
+#if defined(STM32F469_479xx)
+#define RCC_APB2Periph_DSI ((uint32_t)0x08000000)
+#endif /* STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define RCC_APB2Periph_DFSDM1 ((uint32_t)0x01000000)
+#endif /* STM32F412xG || STM32F413_423xx */
+#if defined(STM32F413_423xx)
+#define RCC_APB2Periph_DFSDM2 ((uint32_t)0x02000000)
+#define RCC_APB2Periph_UART9 ((uint32_t)0x02000040)
+#define RCC_APB2Periph_UART10 ((uint32_t)0x00000080)
+#endif /* STM32F413_423xx */
+
+/* Legacy Defines */
+#define RCC_APB2Periph_DFSDM RCC_APB2Periph_DFSDM1
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF008000C) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF208860C) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO1_Clock_Source_Prescaler
+ * @{
+ */
+#define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
+#define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
+#define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
+#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
+#define RCC_MCO1Div_1 ((uint32_t)0x00000000)
+#define RCC_MCO1Div_2 ((uint32_t)0x04000000)
+#define RCC_MCO1Div_3 ((uint32_t)0x05000000)
+#define RCC_MCO1Div_4 ((uint32_t)0x06000000)
+#define RCC_MCO1Div_5 ((uint32_t)0x07000000)
+#define IS_RCC_MCO1SOURCE_MORT(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
+ ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
+
+#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
+ ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
+ ((DIV) == RCC_MCO1Div_5))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO2_Clock_Source_Prescaler
+ * @{
+ */
+#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
+#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
+#define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
+#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
+#define RCC_MCO2Div_1 ((uint32_t)0x00000000)
+#define RCC_MCO2Div_2 ((uint32_t)0x20000000)
+#define RCC_MCO2Div_3 ((uint32_t)0x28000000)
+#define RCC_MCO2Div_4 ((uint32_t)0x30000000)
+#define RCC_MCO2Div_5 ((uint32_t)0x38000000)
+#define IS_RCC_MCO2SOURCE_MORT(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
+ ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
+
+#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
+ ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
+ ((DIV) == RCC_MCO2Div_5))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag
+ * @{
+ */
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
+#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
+#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)
+#define RCC_FLAG_LSERDY ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
+#define RCC_FLAG_BORRST ((uint8_t)0x79)
+#define RCC_FLAG_PINRST ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
+
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
+ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
+ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
+ ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
+ ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
+
+#define IS_RCC_CALIBRATION_VALUE_MORT(VALUE) ((VALUE) <= 0x1F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Function used to set the RCC clock configuration to the default reset state */
+void RCC_DeInit(void);
+
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
+void RCC_HSEConfig(uint8_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+
+void RCC_PLLCmd(FunctionalState NewState);
+
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR);
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
+
+void RCC_PLLI2SCmd(FunctionalState NewState);
+
+#if defined(STM32F40_41xxx) || defined(STM32F401xx)
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
+#endif /* STM32F40_41xxx || STM32F401xx */
+#if defined(STM32F411xE)
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
+#endif /* STM32F411xE */
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR);
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+void RCC_PLLSAICmd(FunctionalState NewState);
+#if defined(STM32F469_479xx)
+void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR);
+#endif /* STM32F469_479xx */
+#if defined(STM32F446xx)
+void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ);
+#endif /* STM32F446xx */
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
+void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
+
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
+void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
+
+/* System, AHB and APB busses clocks configuration functions ******************/
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+
+/* Peripheral clocks configuration functions **********************************/
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource);
+#if defined(STM32F446xx)
+void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource);
+#endif /* STM32F446xx */
+#if defined(STM32F413_423xx)
+void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
+void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
+#endif /* STM32F413_423xx */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
+void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
+void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
+
+void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
+void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
+
+#if defined(STM32F413_423xx)
+void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR);
+void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR);
+#endif /* STM32F413_423xx */
+
+void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
+void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
+
+void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
+void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
+void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+
+void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
+void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
+void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+
+void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
+void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
+void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+
+/* Features available only for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices */
+void RCC_LSEModeConfig(uint8_t RCC_Mode);
+
+/* Features available only for STM32F469_479xx devices */
+#if defined(STM32F469_479xx)
+void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource);
+#endif /* STM32F469_479xx */
+
+/* Features available only for STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource);
+void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource);
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+
+/* Features available only for STM32F446xx devices */
+#if defined(STM32F446xx)
+void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState);
+void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource);
+void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource);
+#endif /* STM32F446xx */
+
+/* Features available only for STM32F410xx/STM32F412xG/STM32F446xx devices */
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource);
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+/* Features available only for STM32F410xx devices */
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource);
+#if defined(STM32F410xx)
+void RCC_MCO1Cmd(FunctionalState NewState);
+void RCC_MCO2Cmd(FunctionalState NewState);
+#endif /* STM32F410xx */
+#endif /* STM32F410xx || STM32F413_423xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+void RCC_DFSDMCLKConfig(uint32_t RCC_DFSDMCLKSource);
+void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource);
+#if defined(STM32F413_423xx)
+void RCC_DFSDM2ACLKConfig(uint32_t RCC_DFSDMACLKSource);
+#endif /* STM32F413_423xx */
+/* Legacy Defines */
+#define RCC_DFSDM1CLKConfig RCC_DFSDMCLKConfig
+#endif /* STM32F412xG || STM32F413_423xx */
+/* Interrupts and flags management functions **********************************/
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_RCC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/stm32f4xx_syscfg_mort.c Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,214 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_syscfg.c
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file provides firmware functions to manage the SYSCFG_MORT peripheral.
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..] This driver provides functions for:
+
+ (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
+
+ (#) Swapping the internal flash Bank1 and Bank2 this features is only visible for
+ STM32F42xxx/43xxx devices Devices.
+
+ (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig_mort()
+
+ (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig_mort()
+
+ -@- SYSCFG_MORT APB clock must be enabled to get write access to SYSCFG_MORT registers,
+ using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_syscfg_mort.h"
+#include "stm32f4xx_rcc_mort.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup SYSCFG_MORT
+ * @brief SYSCFG_MORT driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define SYSCFG_OFFSET_MORT (SYSCFG_BASE_MORT - PERIPH_BASE_MORT)
+/* --- MEMRMP Register ---*/
+/* Alias word address of UFB_MODE bit */
+#define MEMRMP_OFFSET_MORT SYSCFG_OFFSET_MORT
+#define UFB_MODE_BitNumber_MORT ((uint8_t)0x8)
+#define UFB_MODE_BB_MORT (PERIPH_BB_BASE + (MEMRMP_OFFSET_MORT * 32) + (UFB_MODE_BitNumber_MORT * 4))
+
+/* --- PMC Register ---*/
+/* Alias word address of MII_RMII_SEL bit */
+#define PMC_OFFSET_MORT (SYSCFG_OFFSET_MORT + 0x04)
+#define MII_RMII_SEL_BitNumber_MORT ((uint8_t)0x17)
+#define PMC_MII_RMII_SEL_BB_MORT (PERIPH_BB_BASE + (PMC_OFFSET_MORT * 32) + (MII_RMII_SEL_BitNumber_MORT * 4))
+
+/* --- CMPCR Register ---*/
+/* Alias word address of CMP_PD bit */
+#define CMPCR_OFFSET_MORT (SYSCFG_OFFSET_MORT + 0x20)
+#define CMP_PD_BitNumber_MORT ((uint8_t)0x00)
+#define CMPCR_CMP_PD_BB_MORT (PERIPH_BB_BASE + (CMPCR_OFFSET_MORT * 32) + (CMP_PD_BitNumber_MORT * 4))
+
+/* --- MCHDLYCR Register ---*/
+/* Alias word address of BSCKSEL bit */
+#define MCHDLYCR_OFFSET_MORT (SYSCFG_OFFSET_MORT + 0x30)
+#define BSCKSEL_BIT_NUMBER_MORT POSITION_VAL(SYSCFG_MCHDLYCR_BSCKSEL)
+#define MCHDLYCR_BSCKSEL_BB_MORT (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET_MORT * 32) + (BSCKSEL_BIT_NUMBER_MORT * 4))
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the Alternate Functions (remap and EXTI configuration)
+ * registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void SYSCFG_DeInit_mort(void)
+{
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
+}
+
+
+/**
+ * @brief Selects the GPIO pin used as EXTI Line.
+ * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
+ * EXTI lines where x can be (A..K) for STM32F42xxx/43xxx devices, (A..I)
+ * for STM32F405xx/407xx and STM32F415xx/417xx devices or (A, B, C, D and H)
+ * for STM32401xx devices.
+ *
+ * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
+ * This parameter can be EXTI_PinSourcex where x can be (0..15, except
+ * for EXTI_PortSourceGPIOI_MORT x can be (0..11) for STM32F405xx/407xx
+ * and STM32F405xx/407xx devices and for EXTI_PortSourceGPIOK_MORT x can
+ * be (0..7) for STM32F42xxx/43xxx devices.
+ *
+ * @retval None
+ */
+void SYSCFG_EXTILineConfig_mort(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
+{
+ uint32_t tmp = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_PORT_SOURCE_MORT(EXTI_PortSourceGPIOx));
+ assert_param(IS_EXTI_PIN_SOURCE_MORT(EXTI_PinSourcex));
+
+ tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
+ SYSCFG_MORT->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
+ SYSCFG_MORT->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
+}
+
+/**
+ * @brief Selects the ETHERNET media interface
+ * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode.
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_ETH_MediaInterface_MII_MORT: MII mode selected
+ * @arg SYSCFG_ETH_MediaInterface_RMII_MORT: RMII mode selected
+ * @retval None
+ */
+void SYSCFG_ETH_MediaInterfaceConfig_mort(uint32_t SYSCFG_ETH_MediaInterface)
+{
+ assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE_MORT(SYSCFG_ETH_MediaInterface));
+ /* Configure MII_RMII selection bit */
+ *(__IO uint32_t *) PMC_MII_RMII_SEL_BB_MORT = SYSCFG_ETH_MediaInterface;
+}
+
+/**
+ * @brief Enables or disables the I/O Compensation Cell.
+ * @note The I/O compensation cell can be used only when the device supply
+ * voltage ranges from 2.4 to 3.6 V.
+ * @param NewState: new state of the I/O Compensation Cell.
+ * This parameter can be one of the following values:
+ * @arg ENABLE: I/O compensation cell enabled
+ * @arg DISABLE: I/O compensation cell power-down mode
+ * @retval None
+ */
+void SYSCFG_CompensationCellCmd_mort(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMPCR_CMP_PD_BB_MORT = (uint32_t)NewState;
+}
+
+/**
+ * @brief Checks whether the I/O Compensation Cell ready flag is set or not.
+ * @param None
+ * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)
+ */
+FlagStatus SYSCFG_GetCompensationCellStatus_mort(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((SYSCFG_MORT->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/stm32f4xx_syscfg_mort.h Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,164 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_syscfg.h
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file contains all the functions prototypes for the SYSCFG_MORT firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_SYSCFG_H
+#define __STM32F4xx_SYSCFG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_mort2.h"
+
+
+
+/** @defgroup SYSCFG_EXTI_Port_Sources
+ * @{
+ */
+#define EXTI_PortSourceGPIOA_MORT ((uint8_t)0x00)
+#define EXTI_PortSourceGPIOB_MORT ((uint8_t)0x01)
+#define EXTI_PortSourceGPIOC_MORT ((uint8_t)0x02)
+#define EXTI_PortSourceGPIOD_MORT ((uint8_t)0x03)
+#define EXTI_PortSourceGPIOE_MORT ((uint8_t)0x04)
+#define EXTI_PortSourceGPIOF_MORT ((uint8_t)0x05)
+#define EXTI_PortSourceGPIOG_MORT ((uint8_t)0x06)
+#define EXTI_PortSourceGPIOH_MORT ((uint8_t)0x07)
+#define EXTI_PortSourceGPIOI_MORT ((uint8_t)0x08)
+#define EXTI_PortSourceGPIOJ_MORT ((uint8_t)0x09)
+#define EXTI_PortSourceGPIOK_MORT ((uint8_t)0x0A)
+
+#define IS_EXTI_PORT_SOURCE_MORT(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA_MORT) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOB_MORT) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOC_MORT) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOD_MORT) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOE_MORT) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOF_MORT) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOG_MORT) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOH_MORT) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOI_MORT) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOJ_MORT) || \
+ ((PORTSOURCE) == EXTI_PortSourceGPIOK_MORT))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup SYSCFG_EXTI_Pin_Sources
+ * @{
+ */
+#define EXTI_PinSource0_MORT ((uint8_t)0x00)
+#define EXTI_PinSource1_MORT ((uint8_t)0x01)
+#define EXTI_PinSource2_MORT ((uint8_t)0x02)
+#define EXTI_PinSource3_MORT ((uint8_t)0x03)
+#define EXTI_PinSource4_MORT ((uint8_t)0x04)
+#define EXTI_PinSource5_MORT ((uint8_t)0x05)
+#define EXTI_PinSource6_MORT ((uint8_t)0x06)
+#define EXTI_PinSource7_MORT ((uint8_t)0x07)
+#define EXTI_PinSource8_MORT ((uint8_t)0x08)
+#define EXTI_PinSource9_MORT ((uint8_t)0x09)
+#define EXTI_PinSource10_MORT ((uint8_t)0x0A)
+#define EXTI_PinSource11_MORT ((uint8_t)0x0B)
+#define EXTI_PinSource12_MORT ((uint8_t)0x0C)
+#define EXTI_PinSource13_MORT ((uint8_t)0x0D)
+#define EXTI_PinSource14_MORT ((uint8_t)0x0E)
+#define EXTI_PinSource15_MORT ((uint8_t)0x0F)
+#define IS_EXTI_PIN_SOURCE_MORT(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0_MORT) || \
+ ((PINSOURCE) == EXTI_PinSource1_MORT) || \
+ ((PINSOURCE) == EXTI_PinSource2_MORT) || \
+ ((PINSOURCE) == EXTI_PinSource3_MORT) || \
+ ((PINSOURCE) == EXTI_PinSource4_MORT) || \
+ ((PINSOURCE) == EXTI_PinSource5_MORT) || \
+ ((PINSOURCE) == EXTI_PinSource6_MORT) || \
+ ((PINSOURCE) == EXTI_PinSource7_MORT) || \
+ ((PINSOURCE) == EXTI_PinSource8_MORT) || \
+ ((PINSOURCE) == EXTI_PinSource9_MORT) || \
+ ((PINSOURCE) == EXTI_PinSource10_MORT) || \
+ ((PINSOURCE) == EXTI_PinSource11_MORT) || \
+ ((PINSOURCE) == EXTI_PinSource12_MORT) || \
+ ((PINSOURCE) == EXTI_PinSource13_MORT) || \
+ ((PINSOURCE) == EXTI_PinSource14_MORT) || \
+ ((PINSOURCE) == EXTI_PinSource15_MORT))
+/**
+ * @}
+ */
+
+
+
+
+
+/** @defgroup SYSCFG_ETHERNET_Media_Interface
+ * @{
+ */
+#define SYSCFG_ETH_MediaInterface_MII_MORT ((uint32_t)0x00000000)
+#define SYSCFG_ETH_MediaInterface_RMII_MORT ((uint32_t)0x00000001)
+
+#define IS_SYSCFG_ETH_MEDIA_INTERFACE_MORT(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII_MORT) || \
+ ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII_MORT))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+void SYSCFG_DeInit_mort(void);
+
+void SYSCFG_EXTILineConfig_mort(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
+void SYSCFG_ETH_MediaInterfaceConfig_mort(uint32_t SYSCFG_ETH_MediaInterface);
+void SYSCFG_CompensationCellCmd_mort(FunctionalState NewState);
+FlagStatus SYSCFG_GetCompensationCellStatus_mort(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_SYSCFG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/stm32f4xx_tim_mort.c Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,3370 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_tim.c
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the TIM peripheral:
+ * + TimeBase management
+ * + Output Compare management
+ * + Input Capture management
+ * + Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features
+ * + Interrupts, DMA and flags management
+ * + Clocks management
+ * + Synchronization management
+ * + Specific interface management
+ * + Specific remapping management
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ This driver provides functions to configure and program the TIM
+ of all STM32F4xx devices.
+ These functions are split in 9 groups:
+
+ (#) TIM TimeBase management: this group includes all needed functions
+ to configure the TM Timebase unit:
+ (++) Set/Get Prescaler
+ (++) Set/Get Autoreload
+ (++) Counter modes configuration
+ (++) Set Clock division
+ (++) Select the One Pulse mode
+ (++) Update Request Configuration
+ (++) Update Disable Configuration
+ (++) Auto-Preload Configuration
+ (++) Enable/Disable the counter
+
+ (#) TIM Output Compare management: this group includes all needed
+ functions to configure the Capture/Compare unit used in Output
+ compare mode:
+ (++) Configure each channel, independently, in Output Compare mode
+ (++) Select the output compare modes
+ (++) Select the Polarities of each channel
+ (++) Set/Get the Capture/Compare register values
+ (++) Select the Output Compare Fast mode
+ (++) Select the Output Compare Forced mode
+ (++) Output Compare-Preload Configuration
+ (++) Clear Output Compare Reference
+ (++) Select the OCREF Clear signal
+ (++) Enable/Disable the Capture/Compare Channels
+
+ (#) TIM Input Capture management: this group includes all needed
+ functions to configure the Capture/Compare unit used in
+ Input Capture mode:
+ (++) Configure each channel in input capture mode
+ (++) Configure Channel1/2 in PWM Input mode
+ (++) Set the Input Capture Prescaler
+ (++) Get the Capture/Compare values
+
+ (#) Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features
+ (++) Configures the Break input, dead time, Lock level, the OSSI,
+ the OSSR State and the AOE(automatic output enable)
+ (++) Enable/Disable the TIM peripheral Main Outputs
+ (++) Select the Commutation event
+ (++) Set/Reset the Capture Compare Preload Control bit
+
+ (#) TIM interrupts, DMA and flags management
+ (++) Enable/Disable interrupt sources
+ (++) Get flags status
+ (++) Clear flags/ Pending bits
+ (++) Enable/Disable DMA requests
+ (++) Configure DMA burst mode
+ (++) Select CaptureCompare DMA request
+
+ (#) TIM clocks management: this group includes all needed functions
+ to configure the clock controller unit:
+ (++) Select internal/External clock
+ (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
+
+ (#) TIM synchronization management: this group includes all needed
+ functions to configure the Synchronization unit:
+ (++) Select Input Trigger
+ (++) Select Output Trigger
+ (++) Select Master Slave Mode
+ (++) ETR Configuration when used as external trigger
+
+ (#) TIM specific interface management, this group includes all
+ needed functions to use the specific TIM interface:
+ (++) Encoder Interface Configuration
+ (++) Select Hall Sensor
+
+ (#) TIM specific remapping management includes the Remapping
+ configuration of specific timers
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_tim_mort.h"
+#include "stm32f4xx_rcc_mort.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup TIM
+ * @brief TIM driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define SMCR_ETR_MASK_MORT ((uint16_t)0x00FF)
+#define CCMR_OFFSET_MORT ((uint16_t)0x0018)
+#define CCER_CCE_SET_MORT ((uint16_t)0x0001)
+#define CCER_CCNE_SET_MORT ((uint16_t)0x0004)
+#define CCMR_OC13M_MASK_MORT ((uint16_t)0xFF8F)
+#define CCMR_OC24M_MASK_MORT ((uint16_t)0x8FFF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TI1_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI2_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI3_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI4_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup TIM_Private_Functions
+ * @{
+ */
+
+/** @defgroup TIM_Group1 TimeBase management functions
+ * @brief TimeBase management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### TimeBase management functions #####
+ ===============================================================================
+
+
+ ##### TIM Driver: how to use it in Timing(Time base) Mode #####
+ ===============================================================================
+ [..]
+ To use the Timer in Timing(Time base) mode, the following steps are mandatory:
+
+ (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
+
+ (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
+
+ (#) Call TIM_TimeBaseInit_mort(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit
+ with the corresponding configuration
+
+ (#) Enable the NVIC if you need to generate the update interrupt.
+
+ (#) Enable the corresponding interrupt using the function TIM_ITConfig_mort(TIMx, TIM_IT_Update_MORT)
+
+ (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+
+ -@- All other functions can be used separately to modify, if needed,
+ a specific feature of the Timer.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @retval None
+
+ */
+void TIM_DeInit_mort(TIM_TypeDef_mort* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+
+ if (TIMx == TIM1_MORT)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
+ }
+ else if (TIMx == TIM2_MORT)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+ }
+ else if (TIMx == TIM3_MORT)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+ }
+ else if (TIMx == TIM4_MORT)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+ }
+ else if (TIMx == TIM5_MORT)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
+ }
+ else if (TIMx == TIM6_MORT)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
+ }
+ else if (TIMx == TIM7_MORT)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
+ }
+ else if (TIMx == TIM8_MORT)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
+ }
+ else if (TIMx == TIM9_MORT)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
+ }
+ else if (TIMx == TIM10_MORT)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
+ }
+ else if (TIMx == TIM11_MORT)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
+ }
+ else if (TIMx == TIM12_MORT)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
+ }
+ else if (TIMx == TIM13_MORT)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
+ }
+ else
+ {
+ if (TIMx == TIM14_MORT)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the TIMx Time Base Unit peripheral according to
+ * the specified parameters in the TIM_TimeBaseInitStruct.
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef_mort structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_TimeBaseInit_mort(TIM_TypeDef_mort* TIMx, TIM_TimeBaseInitTypeDef_mort* TIM_TimeBaseInitStruct)
+{
+ uint16_t tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
+ assert_param(IS_TIM_CKD_DIV_MORT(TIM_TimeBaseInitStruct->TIM_ClockDivision));
+
+ tmpcr1 = TIMx->CR1;
+
+ if((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT)||
+ (TIMx == TIM2_MORT) || (TIMx == TIM3_MORT)||
+ (TIMx == TIM4_MORT) || (TIMx == TIM5_MORT))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR_MORT | TIM_CR1_CMS_MORT));
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
+ }
+
+ if((TIMx != TIM6_MORT) && (TIMx != TIM7_MORT))
+ {
+ /* Set the clock division */
+ tmpcr1 &= (uint16_t)(~TIM_CR1_CKD_MORT);
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
+ }
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+
+ if ((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter(only for TIM1_MORT and TIM8_MORT) value immediately */
+ TIMx->EGR = TIM_PSCReloadMode_Immediate_MORT;
+}
+
+/**
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
+ * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef_mort
+ * structure which will be initialized.
+ * @retval None
+ */
+void TIM_TimeBaseStructInit_mort(TIM_TimeBaseInitTypeDef_mort* TIM_TimeBaseInitStruct)
+{
+ /* Set the default configuration */
+ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
+ TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
+ TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1_MORT;
+ TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up_MORT;
+ TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
+}
+
+/**
+ * @brief Configures the TIMx Prescaler.
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @param Prescaler: specifies the Prescaler Register value
+ * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
+ * This parameter can be one of the following values:
+ * @arg TIM_PSCReloadMode_Update_MORT: The Prescaler is loaded at the update event.
+ * @arg TIM_PSCReloadMode_Immediate_MORT: The Prescaler is loaded immediately.
+ * @retval None
+ */
+void TIM_PrescalerConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_PRESCALER_RELOAD_MORT(TIM_PSCReloadMode));
+ /* Set the Prescaler value */
+ TIMx->PSC = Prescaler;
+ /* Set or reset the UG Bit */
+ TIMx->EGR = TIM_PSCReloadMode;
+}
+
+/**
+ * @brief Specifies the TIMx Counter Mode to be used.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_CounterMode: specifies the Counter Mode to be used
+ * This parameter can be one of the following values:
+ * @arg TIM_CounterMode_Up_MORT: TIM Up Counting Mode
+ * @arg TIM_CounterMode_Down_MORT: TIM Down Counting Mode
+ * @arg TIM_CounterMode_CenterAligned1_MORT: TIM Center Aligned Mode1
+ * @arg TIM_CounterMode_CenterAligned2_MORT: TIM Center Aligned Mode2
+ * @arg TIM_CounterMode_CenterAligned3_MORT: TIM Center Aligned Mode3
+ * @retval None
+ */
+void TIM_CounterModeConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_CounterMode)
+{
+ uint16_t tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
+
+ tmpcr1 = TIMx->CR1;
+
+ /* Reset the CMS and DIR Bits */
+ tmpcr1 &= (uint16_t)~(TIM_CR1_DIR_MORT | TIM_CR1_CMS_MORT);
+
+ /* Set the Counter Mode */
+ tmpcr1 |= TIM_CounterMode;
+
+ /* Write to TIMx CR1 register */
+ TIMx->CR1 = tmpcr1;
+}
+
+/**
+ * @brief Sets the TIMx Counter Register value
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @param Counter: specifies the Counter register new value.
+ * @retval None
+ */
+void TIM_SetCounter_mort(TIM_TypeDef_mort* TIMx, uint32_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+
+ /* Set the Counter Register value */
+ TIMx->CNT = Counter;
+}
+
+/**
+ * @brief Sets the TIMx Autoreload Register value
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @param Autoreload: specifies the Autoreload register new value.
+ * @retval None
+ */
+void TIM_SetAutoreload_mort(TIM_TypeDef_mort* TIMx, uint32_t Autoreload)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+
+ /* Set the Autoreload Register value */
+ TIMx->ARR = Autoreload;
+}
+
+/**
+ * @brief Gets the TIMx Counter value.
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @retval Counter Register value
+ */
+uint32_t TIM_GetCounter_mort(TIM_TypeDef_mort* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+
+ /* Get the Counter Register value */
+ return TIMx->CNT;
+}
+
+/**
+ * @brief Gets the TIMx Prescaler value.
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @retval Prescaler Register value.
+ */
+uint16_t TIM_GetPrescaler_mort(TIM_TypeDef_mort* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+
+ /* Get the Prescaler Register value */
+ return TIMx->PSC;
+}
+
+/**
+ * @brief Enables or Disables the TIMx Update event.
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx UDIS bit
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_UpdateDisableConfig_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the Update Disable Bit */
+ TIMx->CR1 |= TIM_CR1_UDIS_MORT;
+ }
+ else
+ {
+ /* Reset the Update Disable Bit */
+ TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS_MORT;
+ }
+}
+
+/**
+ * @brief Configures the TIMx Update Request Interrupt source.
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @param TIM_UpdateSource: specifies the Update source.
+ * This parameter can be one of the following values:
+ * @arg TIM_UpdateSource_Global_MORT: Source of update is the counter
+ * overflow/underflow or the setting of UG bit, or an update
+ * generation through the slave mode controller.
+ * @arg TIM_UpdateSource_Regular_MORT: Source of update is counter overflow/underflow.
+ * @retval None
+ */
+void TIM_UpdateRequestConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_UpdateSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_UPDATE_SOURCE_MORT(TIM_UpdateSource));
+
+ if (TIM_UpdateSource != TIM_UpdateSource_Global_MORT)
+ {
+ /* Set the URS Bit */
+ TIMx->CR1 |= TIM_CR1_URS_MORT;
+ }
+ else
+ {
+ /* Reset the URS Bit */
+ TIMx->CR1 &= (uint16_t)~TIM_CR1_URS_MORT;
+ }
+}
+
+/**
+ * @brief Enables or disables TIMx peripheral Preload register on ARR.
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx peripheral Preload register
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_ARRPreloadConfig_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the ARR Preload Bit */
+ TIMx->CR1 |= TIM_CR1_ARPE_MORT;
+ }
+ else
+ {
+ /* Reset the ARR Preload Bit */
+ TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE_MORT;
+ }
+}
+
+/**
+ * @brief Selects the TIMx's One Pulse Mode.
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @param TIM_OPMode: specifies the OPM Mode to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMode_Single_MORT
+ * @arg TIM_OPMode_Repetitive_MORT
+ * @retval None
+ */
+void TIM_SelectOnePulseMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OPMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OPM_MODE_MORT(TIM_OPMode));
+
+ /* Reset the OPM Bit */
+ TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM_MORT;
+
+ /* Configure the OPM Mode */
+ TIMx->CR1 |= TIM_OPMode;
+}
+
+/**
+ * @brief Sets the TIMx Clock Division value.
+ * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+ * @param TIM_CKD: specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CKD_DIV1_MORT: TDTS = Tck_tim
+ * @arg TIM_CKD_DIV2_MORT: TDTS = 2*Tck_tim
+ * @arg TIM_CKD_DIV4_MORT: TDTS = 4*Tck_tim
+ * @retval None
+ */
+void TIM_SetClockDivision_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_CKD)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_CKD_DIV_MORT(TIM_CKD));
+
+ /* Reset the CKD Bits */
+ TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD_MORT);
+
+ /* Set the CKD value */
+ TIMx->CR1 |= TIM_CKD;
+}
+
+/**
+ * @brief Enables or disables the specified TIM peripheral.
+ * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
+ * @param NewState: new state of the TIMx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_Cmd_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the TIM Counter */
+ TIMx->CR1 |= TIM_CR1_CEN_MORT;
+ }
+ else
+ {
+ /* Disable the TIM Counter */
+ TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN_MORT;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group2 Output Compare management functions
+ * @brief Output Compare management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Output Compare management functions #####
+ ===============================================================================
+
+
+ ##### TIM Driver: how to use it in Output Compare Mode #####
+ ===============================================================================
+ [..]
+ To use the Timer in Output Compare mode, the following steps are mandatory:
+
+ (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
+ function
+
+ (#) Configure the TIM pins by configuring the corresponding GPIO pins
+
+ (#) Configure the Time base unit as described in the first part of this driver,
+ (++) if needed, else the Timer will run with the default configuration:
+ Autoreload value = 0xFFFF
+ (++) Prescaler value = 0x0000
+ (++) Counter mode = Up counting
+ (++) Clock Division = TIM_CKD_DIV1_MORT
+
+ (#) Fill the TIM_OCInitStruct with the desired parameters including:
+ (++) The TIM Output Compare mode: TIM_OCMode
+ (++) TIM Output State: TIM_OutputState
+ (++) TIM Pulse value: TIM_Pulse
+ (++) TIM Output Compare Polarity : TIM_OCPolarity
+
+ (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired
+ channel with the corresponding configuration
+
+ (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+
+ -@- All other functions can be used separately to modify, if needed,
+ a specific feature of the Timer.
+
+ -@- In case of PWM mode, this function is mandatory:
+ TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_Enable_MORT);
+
+ -@- If the corresponding interrupt or DMA request are needed, the user should:
+ (+@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
+ (+@) Enable the corresponding interrupt (or DMA request) using the function
+ TIM_ITConfig_mort(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the TIMx Channel1 according to the specified parameters in
+ * the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef_mort structure that contains
+ * the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC1Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OC_MODE_MORT(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E_MORT;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M_MORT;
+ tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S_MORT;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint16_t)~TIM_CCER_CC1P_MORT;
+ /* Set the Output Compare Polarity */
+ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+
+ /* Set the Output State */
+ tmpccer |= TIM_OCInitStruct->TIM_OutputState;
+
+ if((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE_MORT(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint16_t)~TIM_CCER_CC1NP_MORT;
+ /* Set the Output N Polarity */
+ tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
+ /* Reset the Output N State */
+ tmpccer &= (uint16_t)~TIM_CCER_CC1NE_MORT;
+
+ /* Set the Output N State */
+ tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint16_t)~TIM_CR2_OIS1_MORT;
+ tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N_MORT;
+ /* Set the Output Idle state */
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel2 according to the specified parameters
+ * in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
+ * peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef_mort structure that contains
+ * the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC2Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OC_MODE_MORT(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E_MORT;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M_MORT;
+ tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S_MORT;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint16_t)~TIM_CCER_CC2P_MORT;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
+
+ /* Set the Output State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
+
+ if((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE_MORT(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint16_t)~TIM_CCER_CC2NP_MORT;
+ /* Set the Output N Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
+ /* Reset the Output N State */
+ tmpccer &= (uint16_t)~TIM_CCER_CC2NE_MORT;
+
+ /* Set the Output N State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint16_t)~TIM_CR2_OIS2_MORT;
+ tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N_MORT;
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel3 according to the specified parameters
+ * in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef_mort structure that contains
+ * the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC3Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OC_MODE_MORT(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+
+ /* Disable the Channel 3: Reset the CC2E Bit */
+ TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E_MORT;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M_MORT;
+ tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S_MORT;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint16_t)~TIM_CCER_CC3P_MORT;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
+
+ /* Set the Output State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
+
+ if((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE_MORT(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint16_t)~TIM_CCER_CC3NP_MORT;
+ /* Set the Output N Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
+ /* Reset the Output N State */
+ tmpccer &= (uint16_t)~TIM_CCER_CC3NE_MORT;
+
+ /* Set the Output N State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint16_t)~TIM_CR2_OIS3_MORT;
+ tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N_MORT;
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel4 according to the specified parameters
+ * in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef_mort structure that contains
+ * the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC4Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OC_MODE_MORT(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E_MORT;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M_MORT;
+ tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S_MORT;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint16_t)~TIM_CCER_CC4P_MORT;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
+
+ /* Set the Output State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
+
+ if((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT))
+ {
+ assert_param(IS_TIM_OCIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4_MORT;
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Fills each TIM_OCInitStruct member with its default value.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef_mort structure which will
+ * be initialized.
+ * @retval None
+ */
+void TIM_OCStructInit_mort(TIM_OCInitTypeDef_mort* TIM_OCInitStruct)
+{
+ /* Set the default configuration */
+ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing_MORT;
+ TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable_MORT;
+ TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable_MORT;
+ TIM_OCInitStruct->TIM_Pulse = 0x00000000;
+ TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High_MORT;
+ TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High_MORT;
+ TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset_MORT;
+ TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset_MORT;
+}
+
+/**
+ * @brief Selects the TIM Output Compare Mode.
+ * @note This function disables the selected channel before changing the Output
+ * Compare Mode. If needed, user has to enable this channel using
+ * TIM_CCxCmd_mort() and TIM_CCxNCmd_mort() functions.
+ * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1_MORT: TIM Channel 1
+ * @arg TIM_Channel_2_MORT: TIM Channel 2
+ * @arg TIM_Channel_3_MORT: TIM Channel 3
+ * @arg TIM_Channel_4_MORT: TIM Channel 4
+ * @param TIM_OCMode: specifies the TIM Output Compare Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCMode_Timing_MORT
+ * @arg TIM_OCMode_Active_MORT
+ * @arg TIM_OCMode_Toggle
+ * @arg TIM_OCMode_PWM1_MORT
+ * @arg TIM_OCMode_PWM2_MORT
+ * @arg TIM_ForcedAction_Active_MORT
+ * @arg TIM_ForcedAction_InActive_MORT
+ * @retval None
+ */
+void TIM_SelectOCxM_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
+{
+ uint32_t tmp = 0;
+ uint16_t tmp1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_CHANNEL_MORT(TIM_Channel));
+ assert_param(IS_TIM_OCM_MORT(TIM_OCMode));
+
+ tmp = (uint32_t) TIMx;
+ tmp += CCMR_OFFSET_MORT;
+
+ tmp1 = CCER_CCE_SET_MORT << (uint16_t)TIM_Channel;
+
+ /* Disable the Channel: Reset the CCxE Bit */
+ TIMx->CCER &= (uint16_t) ~tmp1;
+
+ if((TIM_Channel == TIM_Channel_1_MORT) ||(TIM_Channel == TIM_Channel_3_MORT))
+ {
+ tmp += (TIM_Channel>>1);
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK_MORT;
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp |= TIM_OCMode;
+ }
+ else
+ {
+ tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK_MORT;
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
+ }
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare1 Register value
+ * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+ * @param Compare1: specifies the Capture Compare1 register new value.
+ * @retval None
+ */
+void TIM_SetCompare1_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare1)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
+
+ /* Set the Capture Compare1 Register value */
+ TIMx->CCR1 = Compare1;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare2 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
+ * peripheral.
+ * @param Compare2: specifies the Capture Compare2 register new value.
+ * @retval None
+ */
+void TIM_SetCompare2_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare2)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+
+ /* Set the Capture Compare2 Register value */
+ TIMx->CCR2 = Compare2;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare3 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare3: specifies the Capture Compare3 register new value.
+ * @retval None
+ */
+void TIM_SetCompare3_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare3)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+
+ /* Set the Capture Compare3 Register value */
+ TIMx->CCR3 = Compare3;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare4 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare4: specifies the Capture Compare4 register new value.
+ * @retval None
+ */
+void TIM_SetCompare4_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare4)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCR4 = Compare4;
+}
+
+/**
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.
+ * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active_MORT: Force active level on OC1REF
+ * @arg TIM_ForcedAction_InActive_MORT: Force inactive level on OC1REF.
+ * @retval None
+ */
+void TIM_ForcedOC1Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION_MORT(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC1M Bits */
+ tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M_MORT;
+
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= TIM_ForcedAction;
+
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
+ * peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active_MORT: Force active level on OC2REF
+ * @arg TIM_ForcedAction_InActive_MORT: Force inactive level on OC2REF.
+ * @retval None
+ */
+void TIM_ForcedOC2Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION_MORT(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC2M Bits */
+ tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M_MORT;
+
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active_MORT: Force active level on OC3REF
+ * @arg TIM_ForcedAction_InActive_MORT: Force inactive level on OC3REF.
+ * @retval None
+ */
+void TIM_ForcedOC3Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION_MORT(TIM_ForcedAction));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC1M Bits */
+ tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M_MORT;
+
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= TIM_ForcedAction;
+
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active_MORT: Force active level on OC4REF
+ * @arg TIM_ForcedAction_InActive_MORT: Force inactive level on OC4REF.
+ * @retval None
+ */
+void TIM_ForcedOC4Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION_MORT(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC2M Bits */
+ tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M_MORT;
+
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
+ * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable_MORT
+ * @arg TIM_OCPreload_Disable_MORT
+ * @retval None
+ */
+void TIM_OC1PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE_MORT(TIM_OCPreload));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC1PE Bit */
+ tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE_MORT);
+
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= TIM_OCPreload;
+
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
+ * peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable_MORT
+ * @arg TIM_OCPreload_Disable_MORT
+ * @retval None
+ */
+void TIM_OC2PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE_MORT(TIM_OCPreload));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC2PE Bit */
+ tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE_MORT);
+
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable_MORT
+ * @arg TIM_OCPreload_Disable_MORT
+ * @retval None
+ */
+void TIM_OC3PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE_MORT(TIM_OCPreload));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC3PE Bit */
+ tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE_MORT);
+
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= TIM_OCPreload;
+
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable_MORT
+ * @arg TIM_OCPreload_Disable_MORT
+ * @retval None
+ */
+void TIM_OC4PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE_MORT(TIM_OCPreload));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC4PE Bit */
+ tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE_MORT);
+
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 1 Fast feature.
+ * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable_MORT: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC1FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE_MORT(TIM_OCFast));
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC1FE Bit */
+ tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE_MORT;
+
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= TIM_OCFast;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 2 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
+ * peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable_MORT: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC2FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE_MORT(TIM_OCFast));
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC2FE Bit */
+ tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE_MORT);
+
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 3 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable_MORT: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC3FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE_MORT(TIM_OCFast));
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC3FE Bit */
+ tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE_MORT;
+
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= TIM_OCFast;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 4 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable_MORT: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC4FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE_MORT(TIM_OCFast));
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC4FE Bit */
+ tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE_MORT);
+
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF1 signal on an external event
+ * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable_MORT: TIM Output clear enable
+ * @arg TIM_OCClear_Disable_MORT: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC1Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE_MORT(TIM_OCClear));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC1CE Bit */
+ tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE_MORT;
+
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= TIM_OCClear;
+
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF2 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
+ * peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable_MORT: TIM Output clear enable
+ * @arg TIM_OCClear_Disable_MORT: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC2Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE_MORT(TIM_OCClear));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC2CE Bit */
+ tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE_MORT;
+
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF3 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable_MORT: TIM Output clear enable
+ * @arg TIM_OCClear_Disable_MORT: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC3Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE_MORT(TIM_OCClear));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC3CE Bit */
+ tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE_MORT;
+
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= TIM_OCClear;
+
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF4 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable_MORT: TIM Output clear enable
+ * @arg TIM_OCClear_Disable_MORT: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC4Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE_MORT(TIM_OCClear));
+
+ tmpccmr2 = TIMx->CCMR2;
+
+ /* Reset the OC4CE Bit */
+ tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE_MORT;
+
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx channel 1 polarity.
+ * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High_MORT: Output Compare active high
+ * @arg TIM_OCPolarity_Low_MORT: Output Compare active low
+ * @retval None
+ */
+void TIM_OC1PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC1P Bit */
+ tmpccer &= (uint16_t)(~TIM_CCER_CC1P_MORT);
+ tmpccer |= TIM_OCPolarity;
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 1N polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC1N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCNPolarity_High_MORT: Output Compare active high
+ * @arg TIM_OCNPolarity_Low_MORT: Output Compare active low
+ * @retval None
+ */
+void TIM_OC1NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC1NP Bit */
+ tmpccer &= (uint16_t)~TIM_CCER_CC1NP_MORT;
+ tmpccer |= TIM_OCNPolarity;
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 2 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
+ * peripheral.
+ * @param TIM_OCPolarity: specifies the OC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High_MORT: Output Compare active high
+ * @arg TIM_OCPolarity_Low_MORT: Output Compare active low
+ * @retval None
+ */
+void TIM_OC2PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC2P Bit */
+ tmpccer &= (uint16_t)(~TIM_CCER_CC2P_MORT);
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 2N polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC2N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCNPolarity_High_MORT: Output Compare active high
+ * @arg TIM_OCNPolarity_Low_MORT: Output Compare active low
+ * @retval None
+ */
+void TIM_OC2NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC2NP Bit */
+ tmpccer &= (uint16_t)~TIM_CCER_CC2NP_MORT;
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 3 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC3 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High_MORT: Output Compare active high
+ * @arg TIM_OCPolarity_Low_MORT: Output Compare active low
+ * @retval None
+ */
+void TIM_OC3PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC3P Bit */
+ tmpccer &= (uint16_t)~TIM_CCER_CC3P_MORT;
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 3N polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC3N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCNPolarity_High_MORT: Output Compare active high
+ * @arg TIM_OCNPolarity_Low_MORT: Output Compare active low
+ * @retval None
+ */
+void TIM_OC3NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC3NP Bit */
+ tmpccer &= (uint16_t)~TIM_CCER_CC3NP_MORT;
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 4 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC4 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High_MORT: Output Compare active high
+ * @arg TIM_OCPolarity_Low_MORT: Output Compare active low
+ * @retval None
+ */
+void TIM_OC4PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+ tmpccer = TIMx->CCER;
+
+ /* Set or Reset the CC4P Bit */
+ tmpccer &= (uint16_t)~TIM_CCER_CC4P_MORT;
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
+
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1_MORT: TIM Channel 1
+ * @arg TIM_Channel_2_MORT: TIM Channel 2
+ * @arg TIM_Channel_3_MORT: TIM Channel 3
+ * @arg TIM_Channel_4_MORT: TIM Channel 4
+ * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_Enable_MORT or TIM_CCx_Disable_MORT.
+ * @retval None
+ */
+void TIM_CCxCmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_CHANNEL_MORT(TIM_Channel));
+ assert_param(IS_TIM_CCX_MORT(TIM_CCx));
+
+ tmp = CCER_CCE_SET_MORT << TIM_Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= (uint16_t)~ tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1_MORT: TIM Channel 1
+ * @arg TIM_Channel_2_MORT: TIM Channel 2
+ * @arg TIM_Channel_3_MORT: TIM Channel 3
+ * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
+ * @retval None
+ */
+void TIM_CCxNCmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_COMPLEMENTARY_CHANNEL_MORT(TIM_Channel));
+ assert_param(IS_TIM_CCXN_MORT(TIM_CCxN));
+
+ tmp = CCER_CCNE_SET_MORT << TIM_Channel;
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCER &= (uint16_t) ~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group3 Input Capture management functions
+ * @brief Input Capture management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Input Capture management functions #####
+ ===============================================================================
+
+ ##### TIM Driver: how to use it in Input Capture Mode #####
+ ===============================================================================
+ [..]
+ To use the Timer in Input Capture mode, the following steps are mandatory:
+
+ (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
+ function
+
+ (#) Configure the TIM pins by configuring the corresponding GPIO pins
+
+ (#) Configure the Time base unit as described in the first part of this driver,
+ if needed, else the Timer will run with the default configuration:
+ (++) Autoreload value = 0xFFFF
+ (++) Prescaler value = 0x0000
+ (++) Counter mode = Up counting
+ (++) Clock Division = TIM_CKD_DIV1_MORT
+
+ (#) Fill the TIM_ICInitStruct with the desired parameters including:
+ (++) TIM Channel: TIM_Channel
+ (++) TIM Input Capture polarity: TIM_ICPolarity
+ (++) TIM Input Capture selection: TIM_ICSelection
+ (++) TIM Input Capture Prescaler: TIM_ICPrescaler
+ (++) TIM Input Capture filter value: TIM_ICFilter
+
+ (#) Call TIM_ICInit_mort(TIMx, &TIM_ICInitStruct) to configure the desired channel
+ with the corresponding configuration and to measure only frequency
+ or duty cycle of the input signal, or, Call TIM_PWMIConfig_mort(TIMx, &TIM_ICInitStruct)
+ to configure the desired channels with the corresponding configuration
+ and to measure the frequency and the duty cycle of the input signal
+
+ (#) Enable the NVIC or the DMA to read the measured frequency.
+
+ (#) Enable the corresponding interrupt (or DMA request) to read the Captured
+ value, using the function TIM_ITConfig_mort(TIMx, TIM_IT_CCx)
+ (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
+
+ (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+
+ (#) Use TIM_GetCapturex(TIMx); to read the captured value.
+
+ -@- All other functions can be used separately to modify, if needed,
+ a specific feature of the Timer.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the TIM peripheral according to the specified parameters
+ * in the TIM_ICInitStruct.
+ * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef_mort structure that contains
+ * the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_ICInit_mort(TIM_TypeDef_mort* TIMx, TIM_ICInitTypeDef_mort* TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
+ assert_param(IS_TIM_IC_SELECTION_MORT(TIM_ICInitStruct->TIM_ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER_MORT(TIM_ICInitStruct->TIM_ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER_MORT(TIM_ICInitStruct->TIM_ICFilter));
+
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1_MORT)
+ {
+ /* TI1 Configuration */
+ TI1_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2_MORT)
+ {
+ /* TI2 Configuration */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+ TI2_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3_MORT)
+ {
+ /* TI3 Configuration */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ TI3_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC3Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else
+ {
+ /* TI4 Configuration */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ TI4_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC4Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+}
+
+/**
+ * @brief Fills each TIM_ICInitStruct member with its default value.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef_mort structure which will
+ * be initialized.
+ * @retval None
+ */
+void TIM_ICStructInit_mort(TIM_ICInitTypeDef_mort* TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1_MORT;
+ TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising_MORT;
+ TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI_MORT;
+ TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1_MORT;
+ TIM_ICInitStruct->TIM_ICFilter = 0x00;
+}
+
+/**
+ * @brief Configures the TIM peripheral according to the specified parameters
+ * in the TIM_ICInitStruct to measure an external PWM signal.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM
+ * peripheral.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef_mort structure that contains
+ * the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_PWMIConfig_mort(TIM_TypeDef_mort* TIMx, TIM_ICInitTypeDef_mort* TIM_ICInitStruct)
+{
+ uint16_t icoppositepolarity = TIM_ICPolarity_Rising_MORT;
+ uint16_t icoppositeselection = TIM_ICSelection_DirectTI_MORT;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+
+ /* Select the Opposite Input Polarity */
+ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising_MORT)
+ {
+ icoppositepolarity = TIM_ICPolarity_Falling_MORT;
+ }
+ else
+ {
+ icoppositepolarity = TIM_ICPolarity_Rising_MORT;
+ }
+ /* Select the Opposite Input */
+ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI_MORT)
+ {
+ icoppositeselection = TIM_ICSelection_IndirectTI_MORT;
+ }
+ else
+ {
+ icoppositeselection = TIM_ICSelection_DirectTI_MORT;
+ }
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1_MORT)
+ {
+ /* TI1 Configuration */
+ TI1_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ /* TI2 Configuration */
+ TI2_Config_mort(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else
+ {
+ /* TI2 Configuration */
+ TI2_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ /* TI1 Configuration */
+ TI1_Config_mort(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 1 value.
+ * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+ * @retval Capture Compare 1 Register value.
+ */
+uint32_t TIM_GetCapture1_mort(TIM_TypeDef_mort* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
+
+ /* Get the Capture 1 Register value */
+ return TIMx->CCR1;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 2 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
+ * peripheral.
+ * @retval Capture Compare 2 Register value.
+ */
+uint32_t TIM_GetCapture2_mort(TIM_TypeDef_mort* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+
+ /* Get the Capture 2 Register value */
+ return TIMx->CCR2;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 3 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 3 Register value.
+ */
+uint32_t TIM_GetCapture3_mort(TIM_TypeDef_mort* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+
+ /* Get the Capture 3 Register value */
+ return TIMx->CCR3;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 4 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 4 Register value.
+ */
+uint32_t TIM_GetCapture4_mort(TIM_TypeDef_mort* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+
+ /* Get the Capture 4 Register value */
+ return TIMx->CCR4;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 1 prescaler.
+ * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1_MORT: no prescaler
+ * @arg TIM_ICPSC_DIV2_MORT: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4_MORT: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8_MORT: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC1Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER_MORT(TIM_ICPSC));
+
+ /* Reset the IC1PSC Bits */
+ TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC_MORT;
+
+ /* Set the IC1PSC value */
+ TIMx->CCMR1 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 2 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
+ * peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1_MORT: no prescaler
+ * @arg TIM_ICPSC_DIV2_MORT: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4_MORT: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8_MORT: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC2Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER_MORT(TIM_ICPSC));
+
+ /* Reset the IC2PSC Bits */
+ TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC_MORT;
+
+ /* Set the IC2PSC value */
+ TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 3 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1_MORT: no prescaler
+ * @arg TIM_ICPSC_DIV2_MORT: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4_MORT: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8_MORT: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC3Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER_MORT(TIM_ICPSC));
+
+ /* Reset the IC3PSC Bits */
+ TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC_MORT;
+
+ /* Set the IC3PSC value */
+ TIMx->CCMR2 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 4 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1_MORT: no prescaler
+ * @arg TIM_ICPSC_DIV2_MORT: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4_MORT: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8_MORT: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC4Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER_MORT(TIM_ICPSC));
+
+ /* Reset the IC4PSC Bits */
+ TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC_MORT;
+
+ /* Set the IC4PSC value */
+ TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group4 Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features
+ * @brief Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features
+ *
+@verbatim
+ ===============================================================================
+ ##### Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features #####
+ ===============================================================================
+
+ ##### TIM Driver: how to use the Break feature #####
+ ===============================================================================
+ [..]
+ After configuring the Timer channel(s) in the appropriate Output Compare mode:
+
+ (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
+ Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
+ AOE(automatic output enable).
+
+ (#) Call TIM_BDTRConfig_mort(TIMx, &TIM_BDTRInitStruct) to configure the Timer
+
+ (#) Enable the Main Output using TIM_CtrlPWMOutputs_mort(TIM1_MORT, ENABLE)
+
+ (#) Once the break even occurs, the Timer's output signals are put in reset
+ state or in a known state (according to the configuration made in
+ TIM_BDTRConfig_mort() function).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * and the AOE(automatic output enable).
+ * @param TIMx: where x can be 1 or 8 to select the TIM
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef_mort structure that
+ * contains the BDTR Register configuration information for the TIM peripheral.
+ * @retval None
+ */
+void TIM_BDTRConfig_mort(TIM_TypeDef_mort* TIMx, TIM_BDTRInitTypeDef_mort *TIM_BDTRInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
+ assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
+ assert_param(IS_TIM_LOCK_LEVEL_MORT(TIM_BDTRInitStruct->TIM_LOCKLevel));
+ assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
+ assert_param(IS_TIM_BREAK_POLARITY_MORT(TIM_BDTRInitStruct->TIM_BreakPolarity));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE_MORT(TIM_BDTRInitStruct->TIM_AutomaticOutput));
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
+ TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
+ TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
+ TIM_BDTRInitStruct->TIM_AutomaticOutput;
+}
+
+/**
+ * @brief Fills each TIM_BDTRInitStruct member with its default value.
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef_mort structure which
+ * will be initialized.
+ * @retval None
+ */
+void TIM_BDTRStructInit_mort(TIM_BDTRInitTypeDef_mort* TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable_MORT;
+ TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable_MORT;
+ TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF_MORT;
+ TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
+ TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable_MORT;
+ TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low_MORT;
+ TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable_MORT;
+}
+
+/**
+ * @brief Enables or disables the TIM peripheral Main Outputs.
+ * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
+ * @param NewState: new state of the TIM peripheral Main Outputs.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_CtrlPWMOutputs_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the TIM Main Output */
+ TIMx->BDTR |= TIM_BDTR_MOE_MORT;
+ }
+ else
+ {
+ /* Disable the TIM Main Output */
+ TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE_MORT;
+ }
+}
+
+/**
+ * @brief Selects the TIM peripheral Commutation event.
+ * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
+ * @param NewState: new state of the Commutation event.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectCOM_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the COM Bit */
+ TIMx->CR2 |= TIM_CR2_CCUS_MORT;
+ }
+ else
+ {
+ /* Reset the COM Bit */
+ TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS_MORT;
+ }
+}
+
+/**
+ * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+ * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
+ * @param NewState: new state of the Capture Compare Preload Control bit
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_CCPreloadControl_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the CCPC Bit */
+ TIMx->CR2 |= TIM_CR2_CCPC_MORT;
+ }
+ else
+ {
+ /* Reset the CCPC Bit */
+ TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC_MORT;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
+ * @brief Interrupts, DMA and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts, DMA and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified TIM interrupts.
+ * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
+ * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_IT_Update_MORT: TIM update Interrupt source
+ * @arg TIM_IT_CC1_MORT: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2_MORT: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3_MORT: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4_MORT: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM_MORT: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger_MORT: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break_MORT: TIM Break Interrupt source
+ *
+ * @note For TIM6_MORT and TIM7_MORT only the parameter TIM_IT_Update_MORT can be used
+ * @note For TIM9_MORT and TIM12_MORT only one of the following parameters can be used: TIM_IT_Update_MORT,
+ * TIM_IT_CC1_MORT, TIM_IT_CC2_MORT or TIM_IT_Trigger_MORT.
+ * @note For TIM10_MORT, TIM11_MORT, TIM13_MORT and TIM14_MORT only one of the following parameters can
+ * be used: TIM_IT_Update_MORT or TIM_IT_CC1_MORT
+ * @note TIM_IT_COM_MORT and TIM_IT_Break_MORT can be used only with TIM1_MORT and TIM8_MORT
+ *
+ * @param NewState: new state of the TIM interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_ITConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_IT_MORT(TIM_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Interrupt sources */
+ TIMx->DIER |= TIM_IT;
+ }
+ else
+ {
+ /* Disable the Interrupt sources */
+ TIMx->DIER &= (uint16_t)~TIM_IT;
+ }
+}
+
+/**
+ * @brief Configures the TIMx event to be generate by software.
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @param TIM_EventSource: specifies the event source.
+ * This parameter can be one or more of the following values:
+ * @arg TIM_EventSource_Update_MORT: Timer update Event source
+ * @arg TIM_EventSource_CC1_MORT: Timer Capture Compare 1 Event source
+ * @arg TIM_EventSource_CC2_MORT: Timer Capture Compare 2 Event source
+ * @arg TIM_EventSource_CC3_MORT: Timer Capture Compare 3 Event source
+ * @arg TIM_EventSource_CC4_MORT: Timer Capture Compare 4 Event source
+ * @arg TIM_EventSource_COM_MORT: Timer COM event source
+ * @arg TIM_EventSource_Trigger_MORT: Timer Trigger Event source
+ * @arg TIM_EventSource_Break_MORT: Timer Break event source
+ *
+ * @note TIM6_MORT and TIM7_MORT can only generate an update event.
+ * @note TIM_EventSource_COM_MORT and TIM_EventSource_Break_MORT are used only with TIM1_MORT and TIM8_MORT.
+ *
+ * @retval None
+ */
+void TIM_GenerateEvent_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_EventSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_EVENT_SOURCE_MORT(TIM_EventSource));
+
+ /* Set the event sources */
+ TIMx->EGR = TIM_EventSource;
+}
+
+/**
+ * @brief Checks whether the specified TIM flag is set or not.
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @param TIM_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_Update_MORT: TIM update Flag
+ * @arg TIM_FLAG_CC1_MORT: TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2_MORT: TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3_MORT: TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4_MORT: TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM_MORT: TIM Commutation Flag
+ * @arg TIM_FLAG_Trigger_MORT: TIM Trigger Flag
+ * @arg TIM_FLAG_Break_MORT: TIM Break Flag
+ * @arg TIM_FLAG_CC1OF_MORT: TIM Capture Compare 1 over capture Flag
+ * @arg TIM_FLAG_CC2OF_MORT: TIM Capture Compare 2 over capture Flag
+ * @arg TIM_FLAG_CC3OF_MORT: TIM Capture Compare 3 over capture Flag
+ * @arg TIM_FLAG_CC4OF_MORT: TIM Capture Compare 4 over capture Flag
+ *
+ * @note TIM6_MORT and TIM7_MORT can have only one update flag.
+ * @note TIM_FLAG_COM_MORT and TIM_FLAG_Break_MORT are used only with TIM1_MORT and TIM8_MORT.
+ *
+ * @retval The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetFlagStatus_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_FLAG)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
+
+
+ if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's pending flags.
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @param TIM_FLAG: specifies the flag bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_FLAG_Update_MORT: TIM update Flag
+ * @arg TIM_FLAG_CC1_MORT: TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2_MORT: TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3_MORT: TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4_MORT: TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM_MORT: TIM Commutation Flag
+ * @arg TIM_FLAG_Trigger_MORT: TIM Trigger Flag
+ * @arg TIM_FLAG_Break_MORT: TIM Break Flag
+ * @arg TIM_FLAG_CC1OF_MORT: TIM Capture Compare 1 over capture Flag
+ * @arg TIM_FLAG_CC2OF_MORT: TIM Capture Compare 2 over capture Flag
+ * @arg TIM_FLAG_CC3OF_MORT: TIM Capture Compare 3 over capture Flag
+ * @arg TIM_FLAG_CC4OF_MORT: TIM Capture Compare 4 over capture Flag
+ *
+ * @note TIM6_MORT and TIM7_MORT can have only one update flag.
+ * @note TIM_FLAG_COM_MORT and TIM_FLAG_Break_MORT are used only with TIM1_MORT and TIM8_MORT.
+ *
+ * @retval None
+ */
+void TIM_ClearFlag_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+
+ /* Clear the flags */
+ TIMx->SR = (uint16_t)~TIM_FLAG;
+}
+
+/**
+ * @brief Checks whether the TIM interrupt has occurred or not.
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @param TIM_IT: specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_Update_MORT: TIM update Interrupt source
+ * @arg TIM_IT_CC1_MORT: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2_MORT: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3_MORT: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4_MORT: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM_MORT: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger_MORT: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break_MORT: TIM Break Interrupt source
+ *
+ * @note TIM6_MORT and TIM7_MORT can generate only an update interrupt.
+ * @note TIM_IT_COM_MORT and TIM_IT_Break_MORT are used only with TIM1_MORT and TIM8_MORT.
+ *
+ * @retval The new state of the TIM_IT(SET or RESET).
+ */
+ITStatus TIM_GetITStatus_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itstatus = 0x0, itenable = 0x0;
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_GET_IT_MORT(TIM_IT));
+
+ itstatus = TIMx->SR & TIM_IT;
+
+ itenable = TIMx->DIER & TIM_IT;
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's interrupt pending bits.
+ * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
+ * @param TIM_IT: specifies the pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_IT_Update_MORT: TIM1_MORT update Interrupt source
+ * @arg TIM_IT_CC1_MORT: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2_MORT: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3_MORT: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4_MORT: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM_MORT: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger_MORT: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break_MORT: TIM Break Interrupt source
+ *
+ * @note TIM6_MORT and TIM7_MORT can generate only an update interrupt.
+ * @note TIM_IT_COM_MORT and TIM_IT_Break_MORT are used only with TIM1_MORT and TIM8_MORT.
+ *
+ * @retval None
+ */
+void TIM_ClearITPendingBit_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
+
+ /* Clear the IT pending Bit */
+ TIMx->SR = (uint16_t)~TIM_IT;
+}
+
+/**
+ * @brief Configures the TIMx's DMA interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_DMABase: DMA Base address.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABase_CR1_MORT
+ * @arg TIM_DMABase_CR2_MORT
+ * @arg TIM_DMABase_SMCR_MORT
+ * @arg TIM_DMABase_DIER_MORT
+ * @arg TIM1_DMABase_SR
+ * @arg TIM_DMABase_EGR_MORT
+ * @arg TIM_DMABase_CCMR1_MORT
+ * @arg TIM_DMABase_CCMR2_MORT
+ * @arg TIM_DMABase_CCER_MORT
+ * @arg TIM_DMABase_CNT_MORT
+ * @arg TIM_DMABase_PSC_MORT
+ * @arg TIM_DMABase_ARR
+ * @arg TIM_DMABase_RCR_MORT
+ * @arg TIM_DMABase_CCR1_MORT
+ * @arg TIM_DMABase_CCR2_MORT
+ * @arg TIM_DMABase_CCR3_MORT
+ * @arg TIM_DMABase_CCR4_MORT
+ * @arg TIM_DMABase_BDTR_MORT
+ * @arg TIM_DMABase_DCR_MORT
+ * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value
+ * between: TIM_DMABurstLength_1Transfer_MORT and TIM_DMABurstLength_18Transfers_MORT.
+ * @retval None
+ */
+void TIM_DMAConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_DMA_BASE_MORT(TIM_DMABase));
+ assert_param(IS_TIM_DMA_LENGTH_MORT(TIM_DMABurstLength));
+
+ /* Set the DMA Base and the DMA Burst Length */
+ TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+ * @brief Enables or disables the TIMx's DMA Requests.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
+ * @param TIM_DMASource: specifies the DMA Request sources.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_DMA_Update_MORT: TIM update Interrupt source
+ * @arg TIM_DMA_CC1_MORT: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2_MORT: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3_MORT: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4_MORT: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM_MORT: TIM Commutation DMA source
+ * @arg TIM_DMA_Trigger_MORT: TIM Trigger DMA source
+ * @param NewState: new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_DMACmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST5_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_DMA_SOURCE_MORT(TIM_DMASource));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA sources */
+ TIMx->DIER |= TIM_DMASource;
+ }
+ else
+ {
+ /* Disable the DMA sources */
+ TIMx->DIER &= (uint16_t)~TIM_DMASource;
+ }
+}
+
+/**
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param NewState: new state of the Capture Compare DMA source
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectCCDMA_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the CCDS Bit */
+ TIMx->CR2 |= TIM_CR2_CCDS_MORT;
+ }
+ else
+ {
+ /* Reset the CCDS Bit */
+ TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS_MORT;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group6 Clocks management functions
+ * @brief Clocks management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Clocks management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the TIMx internal Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
+ * peripheral.
+ * @retval None
+ */
+void TIM_InternalClockConfig_mort(TIM_TypeDef_mort* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS_MORT;
+}
+
+/**
+ * @brief Configures the TIMx Internal Trigger as External Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
+ * peripheral.
+ * @param TIM_InputTriggerSource: Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0_MORT: Internal Trigger 0
+ * @arg TIM_TS_ITR1_MORT: Internal Trigger 1
+ * @arg TIM_TS_ITR2_MORT: Internal Trigger 2
+ * @arg TIM_TS_ITR3_MORT: Internal Trigger 3
+ * @retval None
+ */
+void TIM_ITRxExternalClockConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION_MORT(TIM_InputTriggerSource));
+
+ /* Select the Internal Trigger */
+ TIM_SelectInputTrigger_mort(TIMx, TIM_InputTriggerSource);
+
+ /* Select the External clock mode1 */
+ TIMx->SMCR |= TIM_SlaveMode_External1_MORT;
+}
+
+/**
+ * @brief Configures the TIMx Trigger as External Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
+ * to select the TIM peripheral.
+ * @param TIM_TIxExternalCLKSource: Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIxExternalCLK1Source_TI1ED_MORT: TI1 Edge Detector
+ * @arg TIM_TIxExternalCLK1Source_TI1_MORT: Filtered Timer Input 1
+ * @arg TIM_TIxExternalCLK1Source_TI2_MORT: Filtered Timer Input 2
+ * @param TIM_ICPolarity: specifies the TIx Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising_MORT
+ * @arg TIM_ICPolarity_Falling_MORT
+ * @param ICFilter: specifies the filter value.
+ * This parameter must be a value between 0x0 and 0xF.
+ * @retval None
+ */
+void TIM_TIxExternalClockConfig(TIM_TypeDef_mort* TIMx, uint16_t TIM_TIxExternalCLKSource,
+ uint16_t TIM_ICPolarity, uint16_t ICFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
+ assert_param(IS_TIM_IC_FILTER_MORT(ICFilter));
+
+ /* Configure the Timer Input Clock Source */
+ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2_MORT)
+ {
+ TI2_Config_mort(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI_MORT, ICFilter);
+ }
+ else
+ {
+ TI1_Config_mort(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI_MORT, ICFilter);
+ }
+ /* Select the Trigger source */
+ TIM_SelectInputTrigger_mort(TIMx, TIM_TIxExternalCLKSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCR |= TIM_SlaveMode_External1_MORT;
+}
+
+/**
+ * @brief Configures the External clock Mode1
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF_MORT: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2_MORT: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4_MORT: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8_MORT: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted_MORT: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted_MORT: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRClockMode1Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER_MORT(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY_MORT(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER_MORT(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ETRConfig_mort(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the SMS Bits */
+ tmpsmcr &= (uint16_t)~TIM_SMCR_SMS_MORT;
+
+ /* Select the External clock mode1 */
+ tmpsmcr |= TIM_SlaveMode_External1_MORT;
+
+ /* Select the Trigger selection : ETRF */
+ tmpsmcr &= (uint16_t)~TIM_SMCR_TS_MORT;
+ tmpsmcr |= TIM_TS_ETRF_MORT;
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Configures the External clock Mode2
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF_MORT: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2_MORT: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4_MORT: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8_MORT: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted_MORT: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted_MORT: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRClockMode2Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER_MORT(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY_MORT(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER_MORT(ExtTRGFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETRConfig_mort(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Enable the External clock mode2 */
+ TIMx->SMCR |= TIM_SMCR_ECE_MORT;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group7 Synchronization management functions
+ * @brief Synchronization management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Synchronization management functions #####
+ ===============================================================================
+
+ ##### TIM Driver: how to use it in synchronization Mode #####
+ ===============================================================================
+ [..]
+
+ *** Case of two/several Timers ***
+ ==================================
+ [..]
+ (#) Configure the Master Timers using the following functions:
+ (++) void TIM_SelectOutputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_TRGOSource);
+ (++) void TIM_SelectMasterSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_MasterSlaveMode);
+ (#) Configure the Slave Timers using the following functions:
+ (++) void TIM_SelectInputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource);
+ (++) void TIM_SelectSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_SlaveMode);
+
+ *** Case of Timers and external trigger(ETR pin) ***
+ ====================================================
+ [..]
+ (#) Configure the External trigger using this function:
+ (++) void TIM_ETRConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+ (#) Configure the Slave Timers using the following functions:
+ (++) void TIM_SelectInputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource);
+ (++) void TIM_SelectSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_SlaveMode);
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
+ * to select the TIM peripheral.
+ * @param TIM_InputTriggerSource: The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0_MORT: Internal Trigger 0
+ * @arg TIM_TS_ITR1_MORT: Internal Trigger 1
+ * @arg TIM_TS_ITR2_MORT: Internal Trigger 2
+ * @arg TIM_TS_ITR3_MORT: Internal Trigger 3
+ * @arg TIM_TS_TI1F_ED_MORT: TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1_MORT: Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2_MORT: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF_MORT: External Trigger input
+ * @retval None
+ */
+void TIM_SelectInputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ uint16_t tmpsmcr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_TRIGGER_SELECTION_MORT(TIM_InputTriggerSource));
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the TS Bits */
+ tmpsmcr &= (uint16_t)~TIM_SMCR_TS_MORT;
+
+ /* Set the Input Trigger source */
+ tmpsmcr |= TIM_InputTriggerSource;
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Selects the TIMx Trigger Output Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
+ *
+ * @param TIM_TRGOSource: specifies the Trigger Output source.
+ * This parameter can be one of the following values:
+ *
+ * - For all TIMx
+ * @arg TIM_TRGOSource_Reset_MORT: The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
+ * @arg TIM_TRGOSource_Enable_MORT: The Counter Enable CEN is used as the trigger output(TRGO)
+ * @arg TIM_TRGOSource_Update_MORT: The update event is selected as the trigger output(TRGO)
+ *
+ * - For all TIMx except TIM6_MORT and TIM7_MORT
+ * @arg TIM_TRGOSource_OC1_MORT: The trigger output sends a positive pulse when the CC1IF flag
+ * is to be set, as soon as a capture or compare match occurs(TRGO)
+ * @arg TIM_TRGOSource_OC1Ref_MORT: OC1REF signal is used as the trigger output(TRGO)
+ * @arg TIM_TRGOSource_OC2Ref_MORT: OC2REF signal is used as the trigger output(TRGO)
+ * @arg TIM_TRGOSource_OC3Ref_MORT: OC3REF signal is used as the trigger output(TRGO)
+ * @arg TIM_TRGOSource_OC4Ref_MORT: OC4REF signal is used as the trigger output(TRGO)
+ *
+ * @retval None
+ */
+void TIM_SelectOutputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_TRGOSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST5_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_TRGO_SOURCE_MORT(TIM_TRGOSource));
+
+ /* Reset the MMS Bits */
+ TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS_MORT;
+ /* Select the TRGO source */
+ TIMx->CR2 |= TIM_TRGOSource;
+}
+
+/**
+ * @brief Selects the TIMx Slave Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
+ * @param TIM_SlaveMode: specifies the Timer Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_SlaveMode_Reset_MORT: Rising edge of the selected trigger signal(TRGI) reinitialize
+ * the counter and triggers an update of the registers
+ * @arg TIM_SlaveMode_Gated_MORT: The counter clock is enabled when the trigger signal (TRGI) is high
+ * @arg TIM_SlaveMode_Trigger_MORT: The counter starts at a rising edge of the trigger TRGI
+ * @arg TIM_SlaveMode_External1_MORT: Rising edges of the selected trigger (TRGI) clock the counter
+ * @retval None
+ */
+void TIM_SelectSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_SlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_SLAVE_MODE_MORT(TIM_SlaveMode));
+
+ /* Reset the SMS Bits */
+ TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS_MORT;
+
+ /* Select the Slave Mode */
+ TIMx->SMCR |= TIM_SlaveMode;
+}
+
+/**
+ * @brief Sets or Resets the TIMx Master/Slave Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
+ * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_MasterSlaveMode_Enable_MORT: synchronization between the current timer
+ * and its slaves (through TRGO)
+ * @arg TIM_MasterSlaveMode_Disable_MORT: No action
+ * @retval None
+ */
+void TIM_SelectMasterSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
+
+ /* Reset the MSM Bit */
+ TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM_MORT;
+
+ /* Set or Reset the MSM Bit */
+ TIMx->SMCR |= TIM_MasterSlaveMode;
+}
+
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF_MORT: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2_MORT: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4_MORT: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8_MORT: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted_MORT: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted_MORT: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER_MORT(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY_MORT(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER_MORT(ExtTRGFilter));
+
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the ETR Bits */
+ tmpsmcr &= SMCR_ETR_MASK_MORT;
+
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group8 Specific interface management functions
+ * @brief Specific interface management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Specific interface management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the TIMx Encoder Interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
+ * peripheral.
+ * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_EncoderMode_TI1_MORT: Counter counts on TI1FP1 edge depending on TI2FP2 level.
+ * @arg TIM_EncoderMode_TI2_MORT: Counter counts on TI2FP2 edge depending on TI1FP1 level.
+ * @arg TIM_EncoderMode_TI12_MORT: Counter counts on both TI1FP1 and TI2FP2 edges depending
+ * on the level of the other input.
+ * @param TIM_IC1Polarity: specifies the IC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Falling_MORT: IC Falling edge.
+ * @arg TIM_ICPolarity_Rising_MORT: IC Rising edge.
+ * @param TIM_IC2Polarity: specifies the IC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Falling_MORT: IC Falling edge.
+ * @arg TIM_ICPolarity_Rising_MORT: IC Rising edge.
+ * @retval None
+ */
+void TIM_EncoderInterfaceConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
+{
+ uint16_t tmpsmcr = 0;
+ uint16_t tmpccmr1 = 0;
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_ENCODER_MODE_MORT(TIM_EncoderMode));
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr &= (uint16_t)~TIM_SMCR_SMS_MORT;
+ tmpsmcr |= TIM_EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S_MORT) & ((uint16_t)~TIM_CCMR1_CC2S_MORT);
+ tmpccmr1 |= TIM_CCMR1_CC1S_0_MORT | TIM_CCMR1_CC2S_0_MORT;
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= ((uint16_t)~TIM_CCER_CC1P_MORT) & ((uint16_t)~TIM_CCER_CC2P_MORT);
+ tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Enables or disables the TIMx's Hall sensor interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
+ * peripheral.
+ * @param NewState: new state of the TIMx Hall sensor interface.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectHallSensor_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Set the TI1S Bit */
+ TIMx->CR2 |= TIM_CR2_TI1S_MORT;
+ }
+ else
+ {
+ /* Reset the TI1S Bit */
+ TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S_MORT;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group9 Specific remapping management function
+ * @brief Specific remapping management function
+ *
+@verbatim
+ ===============================================================================
+ ##### Specific remapping management function #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the TIM2_MORT, TIM5_MORT and TIM11_MORT Remapping input capabilities.
+ * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral.
+ * @param TIM_Remap: specifies the TIM input remapping source.
+ * This parameter can be one of the following values:
+ * @arg TIM2_TIM8_TRGO: TIM2_MORT ITR1 input is connected to TIM8_MORT Trigger output(default)
+ * @arg TIM2_ETH_PTP_MORT: TIM2_MORT ITR1 input is connected to ETH PTP trigger output.
+ * @arg TIM2_USBFS_SOF_MORT: TIM2_MORT ITR1 input is connected to USB FS SOF.
+ * @arg TIM2_USBHS_SOF_MORT: TIM2_MORT ITR1 input is connected to USB HS SOF.
+ * @arg TIM5_GPIO: TIM5_MORT CH4 input is connected to dedicated Timer pin(default)
+ * @arg TIM5_LSI_MORT: TIM5_MORT CH4 input is connected to LSI clock.
+ * @arg TIM5_LSE_MORT: TIM5_MORT CH4 input is connected to LSE clock.
+ * @arg TIM5_RTC_MORT: TIM5_MORT CH4 input is connected to RTC Output event.
+ * @arg TIM11_GPIO_MORT: TIM11_MORT CH4 input is connected to dedicated Timer pin(default)
+ * @arg TIM11_HSE_MORT: TIM11_MORT CH4 input is connected to HSE_RTC clock
+ * (HSE divided by a programmable prescaler)
+ * @retval None
+ */
+void TIM_RemapConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Remap)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH_MORT(TIMx));
+ assert_param(IS_TIM_REMAP(TIM_Remap));
+
+ /* Set the Timer remapping configuration */
+ TIMx->OR = TIM_Remap;
+}
+/**
+ * @}
+ */
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
+ * to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising_MORT
+ * @arg TIM_ICPolarity_Falling_MORT
+ * @arg TIM_ICPolarity_BothEdge_MORT
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI_MORT: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_IndirectTI_MORT: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_TRC_MORT: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI1_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr1 = 0, tmpccer = 0;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E_MORT;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input and set the filter */
+ tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S_MORT) & ((uint16_t)~TIM_CCMR1_IC1F_MORT);
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= (uint16_t)~(TIM_CCER_CC1P_MORT | TIM_CCER_CC1NP_MORT);
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E_MORT);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
+ * peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising_MORT
+ * @arg TIM_ICPolarity_Falling_MORT
+ * @arg TIM_ICPolarity_BothEdge_MORT
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI_MORT: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_IndirectTI_MORT: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_TRC_MORT: TIM Input 2 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI2_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E_MORT;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 4);
+
+ /* Select the Input and set the filter */
+ tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S_MORT) & ((uint16_t)~TIM_CCMR1_IC2F_MORT);
+ tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= (uint16_t)~(TIM_CCER_CC2P_MORT | TIM_CCER_CC2NP_MORT);
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E_MORT);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising_MORT
+ * @arg TIM_ICPolarity_Falling_MORT
+ * @arg TIM_ICPolarity_BothEdge_MORT
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI_MORT: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_IndirectTI_MORT: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_TRC_MORT: TIM Input 3 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI3_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E_MORT;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 8);
+
+ /* Select the Input and set the filter */
+ tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S_MORT) & ((uint16_t)~TIM_CCMR2_IC3F_MORT);
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= (uint16_t)~(TIM_CCER_CC3P_MORT | TIM_CCER_CC3NP_MORT);
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E_MORT);
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising_MORT
+ * @arg TIM_ICPolarity_Falling_MORT
+ * @arg TIM_ICPolarity_BothEdge_MORT
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI_MORT: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_IndirectTI_MORT: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_TRC_MORT: TIM Input 4 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI4_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E_MORT;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 12);
+
+ /* Select the Input and set the filter */
+ tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S_MORT) & ((uint16_t)~TIM_CCMR1_IC2F_MORT);
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
+ tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
+
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= (uint16_t)~(TIM_CCER_CC4P_MORT | TIM_CCER_CC4NP_MORT);
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E_MORT);
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer ;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/stm32f4xx_tim_mort.h Sat Oct 23 05:49:09 2021 +0000
@@ -0,0 +1,1156 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_tim.h
+ * @author MCD Application Team
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file contains all the functions prototypes for the TIM firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_TIM_H_MORT_
+#define __STM32F4xx_TIM_H_MORT_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_mort2.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief TIM Time Base Init structure definition
+ * @note This structure is used with all TIMx except for TIM6_MORT and TIM7_MORT.
+ */
+
+typedef struct
+{
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between 0x0000 and 0xFFFF. */
+
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+ uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between 0x00 and 0xFF.
+ @note This parameter is valid only for TIM1_MORT and TIM8_MORT. */
+} TIM_TimeBaseInitTypeDef_mort;
+
+/**
+ * @brief TIM Output Compare Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_State */
+
+ uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_State
+ @note This parameter is valid only for TIM1_MORT and TIM8_MORT. */
+
+ uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1_MORT and TIM8_MORT. */
+
+ uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1_MORT and TIM8_MORT. */
+
+ uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1_MORT and TIM8_MORT. */
+} TIM_OCInitTypeDef_mort;
+
+/**
+ * @brief TIM Input Capture Init structure definition
+ */
+
+typedef struct
+{
+
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.
+ This parameter can be a value of @ref TIM_Channel */
+
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint16_t TIM_ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef_mort;
+
+/**
+ * @brief BDTR structure definition
+ * @note This structure is used only with TIM1_MORT and TIM8_MORT.
+ */
+
+typedef struct
+{
+
+ uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref TIM_Lock_level */
+
+ uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+ uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref TIM_Break_Polarity */
+
+ uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef_mort;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_constants
+ * @{
+ */
+
+#define IS_TIM_ALL_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \
+ ((PERIPH) == TIM2_MORT) || \
+ ((PERIPH) == TIM3_MORT) || \
+ ((PERIPH) == TIM4_MORT) || \
+ ((PERIPH) == TIM5_MORT) || \
+ ((PERIPH) == TIM6_MORT) || \
+ ((PERIPH) == TIM7_MORT) || \
+ ((PERIPH) == TIM8_MORT) || \
+ ((PERIPH) == TIM9_MORT) || \
+ ((PERIPH) == TIM10_MORT) || \
+ ((PERIPH) == TIM11_MORT) || \
+ ((PERIPH) == TIM12_MORT) || \
+ (((PERIPH) == TIM13_MORT) || \
+ ((PERIPH) == TIM14_MORT)))
+/* LIST1: TIM1_MORT, TIM2_MORT, TIM3_MORT, TIM4_MORT, TIM5_MORT, TIM8_MORT, TIM9_MORT, TIM10_MORT, TIM11_MORT, TIM12_MORT, TIM13_MORT and TIM14_MORT */
+#define IS_TIM_LIST1_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \
+ ((PERIPH) == TIM2_MORT) || \
+ ((PERIPH) == TIM3_MORT) || \
+ ((PERIPH) == TIM4_MORT) || \
+ ((PERIPH) == TIM5_MORT) || \
+ ((PERIPH) == TIM8_MORT) || \
+ ((PERIPH) == TIM9_MORT) || \
+ ((PERIPH) == TIM10_MORT) || \
+ ((PERIPH) == TIM11_MORT) || \
+ ((PERIPH) == TIM12_MORT) || \
+ ((PERIPH) == TIM13_MORT) || \
+ ((PERIPH) == TIM14_MORT))
+
+/* LIST2: TIM1_MORT, TIM2_MORT, TIM3_MORT, TIM4_MORT, TIM5_MORT, TIM8_MORT, TIM9_MORT and TIM12_MORT */
+#define IS_TIM_LIST2_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \
+ ((PERIPH) == TIM2_MORT) || \
+ ((PERIPH) == TIM3_MORT) || \
+ ((PERIPH) == TIM4_MORT) || \
+ ((PERIPH) == TIM5_MORT) || \
+ ((PERIPH) == TIM8_MORT) || \
+ ((PERIPH) == TIM9_MORT) || \
+ ((PERIPH) == TIM12_MORT))
+/* LIST3: TIM1_MORT, TIM2_MORT, TIM3_MORT, TIM4_MORT, TIM5_MORT and TIM8_MORT */
+#define IS_TIM_LIST3_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \
+ ((PERIPH) == TIM2_MORT) || \
+ ((PERIPH) == TIM3_MORT) || \
+ ((PERIPH) == TIM4_MORT) || \
+ ((PERIPH) == TIM5_MORT) || \
+ ((PERIPH) == TIM8_MORT))
+/* LIST4: TIM1_MORT and TIM8_MORT */
+#define IS_TIM_LIST4_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \
+ ((PERIPH) == TIM8_MORT))
+/* LIST5: TIM1_MORT, TIM2_MORT, TIM3_MORT, TIM4_MORT, TIM5_MORT, TIM6_MORT, TIM7_MORT and TIM8_MORT */
+#define IS_TIM_LIST5_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \
+ ((PERIPH) == TIM2_MORT) || \
+ ((PERIPH) == TIM3_MORT) || \
+ ((PERIPH) == TIM4_MORT) || \
+ ((PERIPH) == TIM5_MORT) || \
+ ((PERIPH) == TIM6_MORT) || \
+ ((PERIPH) == TIM7_MORT) || \
+ ((PERIPH) == TIM8_MORT))
+/* LIST6: TIM2_MORT, TIM5_MORT and TIM11_MORT */
+#define IS_TIM_LIST6_PERIPH_MORT(TIMx)(((TIMx) == TIM2_MORT) || \
+ ((TIMx) == TIM5_MORT) || \
+ ((TIMx) == TIM11_MORT))
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes
+ * @{
+ */
+
+#define TIM_OCMode_Timing_MORT ((uint16_t)0x0000)
+#define TIM_OCMode_Active_MORT ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive_MORT ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle_MORT ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1_MORT ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2_MORT ((uint16_t)0x0070)
+#define IS_TIM_OC_MODE_MORT(MODE) (((MODE) == TIM_OCMode_Timing_MORT) || \
+ ((MODE) == TIM_OCMode_Active_MORT) || \
+ ((MODE) == TIM_OCMode_Inactive_MORT) || \
+ ((MODE) == TIM_OCMode_Toggle_MORT)|| \
+ ((MODE) == TIM_OCMode_PWM1_MORT) || \
+ ((MODE) == TIM_OCMode_PWM2_MORT))
+#define IS_TIM_OCM_MORT(MODE) (((MODE) == TIM_OCMode_Timing_MORT) || \
+ ((MODE) == TIM_OCMode_Active_MORT) || \
+ ((MODE) == TIM_OCMode_Inactive_MORT) || \
+ ((MODE) == TIM_OCMode_Toggle_MORT)|| \
+ ((MODE) == TIM_OCMode_PWM1_MORT) || \
+ ((MODE) == TIM_OCMode_PWM2_MORT) || \
+ ((MODE) == TIM_ForcedAction_Active_MORT) || \
+ ((MODE) == TIM_ForcedAction_InActive_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode
+ * @{
+ */
+
+#define TIM_OPMode_Single_MORT ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive_MORT ((uint16_t)0x0000)
+#define IS_TIM_OPM_MODE_MORT(MODE) (((MODE) == TIM_OPMode_Single_MORT) || \
+ ((MODE) == TIM_OPMode_Repetitive_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel
+ * @{
+ */
+
+#define TIM_Channel_1_MORT ((uint16_t)0x0000)
+#define TIM_Channel_2_MORT ((uint16_t)0x0004)
+#define TIM_Channel_3_MORT ((uint16_t)0x0008)
+#define TIM_Channel_4_MORT ((uint16_t)0x000C)
+
+#define IS_TIM_CHANNEL_MORT(CHANNEL) (((CHANNEL) == TIM_Channel_1_MORT) || \
+ ((CHANNEL) == TIM_Channel_2_MORT) || \
+ ((CHANNEL) == TIM_Channel_3_MORT) || \
+ ((CHANNEL) == TIM_Channel_4_MORT))
+
+#define IS_TIM_PWMI_CHANNEL_MORT(CHANNEL) (((CHANNEL) == TIM_Channel_1_MORT) || \
+ ((CHANNEL) == TIM_Channel_2_MORT))
+#define IS_TIM_COMPLEMENTARY_CHANNEL_MORT(CHANNEL) (((CHANNEL) == TIM_Channel_1_MORT) || \
+ ((CHANNEL) == TIM_Channel_2_MORT) || \
+ ((CHANNEL) == TIM_Channel_3_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Division_CKD
+ * @{
+ */
+
+#define TIM_CKD_DIV1_MORT ((uint16_t)0x0000)
+#define TIM_CKD_DIV2_MORT ((uint16_t)0x0100)
+#define TIM_CKD_DIV4_MORT ((uint16_t)0x0200)
+#define IS_TIM_CKD_DIV_MORT(DIV) (((DIV) == TIM_CKD_DIV1_MORT) || \
+ ((DIV) == TIM_CKD_DIV2_MORT) || \
+ ((DIV) == TIM_CKD_DIV4_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode
+ * @{
+ */
+
+#define TIM_CounterMode_Up_MORT ((uint16_t)0x0000)
+#define TIM_CounterMode_Down_MORT ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1_MORT ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2_MORT ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3_MORT ((uint16_t)0x0060)
+#define IS_TIM_COUNTER_MODE_MORT(MODE) (((MODE) == TIM_CounterMode_Up_MORT) || \
+ ((MODE) == TIM_CounterMode_Down_MORT) || \
+ ((MODE) == TIM_CounterMode_CenterAligned1_MORT) || \
+ ((MODE) == TIM_CounterMode_CenterAligned2_MORT) || \
+ ((MODE) == TIM_CounterMode_CenterAligned3_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity
+ * @{
+ */
+
+#define TIM_OCPolarity_High_MORT ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low_MORT ((uint16_t)0x0002)
+#define IS_TIM_OC_POLARITY_MORT(POLARITY) (((POLARITY) == TIM_OCPolarity_High_MORT) || \
+ ((POLARITY) == TIM_OCPolarity_Low_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity
+ * @{
+ */
+
+#define TIM_OCNPolarity_High_MORT ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low_MORT ((uint16_t)0x0008)
+#define IS_TIM_OCN_POLARITY_MORT(POLARITY) (((POLARITY) == TIM_OCNPolarity_High_MORT) || \
+ ((POLARITY) == TIM_OCNPolarity_Low_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_State
+ * @{
+ */
+
+#define TIM_OutputState_Disable_MORT ((uint16_t)0x0000)
+#define TIM_OutputState_Enable_MORT ((uint16_t)0x0001)
+#define IS_TIM_OUTPUT_STATE_MORT(STATE) (((STATE) == TIM_OutputState_Disable_MORT) || \
+ ((STATE) == TIM_OutputState_Enable_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_State
+ * @{
+ */
+
+#define TIM_OutputNState_Disable_MORT ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable_MORT ((uint16_t)0x0004)
+#define IS_TIM_OUTPUTN_STATE_MORT(STATE) (((STATE) == TIM_OutputNState_Disable_MORT) || \
+ ((STATE) == TIM_OutputNState_Enable_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Capture_Compare_State
+ * @{
+ */
+
+#define TIM_CCx_Enable_MORT ((uint16_t)0x0001)
+#define TIM_CCx_Disable_MORT ((uint16_t)0x0000)
+#define IS_TIM_CCX_MORT(CCX) (((CCX) == TIM_CCx_Enable_MORT) || \
+ ((CCX) == TIM_CCx_Disable_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Capture_Compare_N_State
+ * @{
+ */
+
+#define TIM_CCxN_Enable_MORT ((uint16_t)0x0004)
+#define TIM_CCxN_Disable_MORT ((uint16_t)0x0000)
+#define IS_TIM_CCXN_MORT(CCXN) (((CCXN) == TIM_CCxN_Enable_MORT) || \
+ ((CCXN) == TIM_CCxN_Disable_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Input_enable_disable
+ * @{
+ */
+
+#define TIM_Break_Enable_MORT ((uint16_t)0x1000)
+#define TIM_Break_Disable_MORT ((uint16_t)0x0000)
+#define IS_TIM_BREAK_STATE_MORT(STATE) (((STATE) == TIM_Break_Enable_MORT) || \
+ ((STATE) == TIM_Break_Disable_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Polarity
+ * @{
+ */
+
+#define TIM_BreakPolarity_Low_MORT ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High_MORT ((uint16_t)0x2000)
+#define IS_TIM_BREAK_POLARITY_MORT(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low_MORT) || \
+ ((POLARITY) == TIM_BreakPolarity_High_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset
+ * @{
+ */
+
+#define TIM_AutomaticOutput_Enable_MORT ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable_MORT ((uint16_t)0x0000)
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE_MORT(STATE) (((STATE) == TIM_AutomaticOutput_Enable_MORT) || \
+ ((STATE) == TIM_AutomaticOutput_Disable_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Lock_level
+ * @{
+ */
+
+#define TIM_LOCKLevel_OFF_MORT ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1_MORT ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2_MORT ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3_MORT ((uint16_t)0x0300)
+#define IS_TIM_LOCK_LEVEL_MORT(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF_MORT) || \
+ ((LEVEL) == TIM_LOCKLevel_1_MORT) || \
+ ((LEVEL) == TIM_LOCKLevel_2_MORT) || \
+ ((LEVEL) == TIM_LOCKLevel_3_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
+ * @{
+ */
+
+#define TIM_OSSIState_Enable_MORT ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable_MORT ((uint16_t)0x0000)
+#define IS_TIM_OSSI_STATE_MORT(STATE) (((STATE) == TIM_OSSIState_Enable_MORT) || \
+ ((STATE) == TIM_OSSIState_Disable_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
+ * @{
+ */
+
+#define TIM_OSSRState_Enable_MORT ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable_MORT ((uint16_t)0x0000)
+#define IS_TIM_OSSR_STATE_MORT(STATE) (((STATE) == TIM_OSSRState_Enable_MORT) || \
+ ((STATE) == TIM_OSSRState_Disable_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State
+ * @{
+ */
+
+#define TIM_OCIdleState_Set_MORT ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset_MORT ((uint16_t)0x0000)
+#define IS_TIM_OCIDLE_STATE_MORT(STATE) (((STATE) == TIM_OCIdleState_Set_MORT) || \
+ ((STATE) == TIM_OCIdleState_Reset_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State
+ * @{
+ */
+
+#define TIM_OCNIdleState_Set_MORT ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset_MORT ((uint16_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE_MORT(STATE) (((STATE) == TIM_OCNIdleState_Set_MORT) || \
+ ((STATE) == TIM_OCNIdleState_Reset_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity
+ * @{
+ */
+
+#define TIM_ICPolarity_Rising_MORT ((uint16_t)0x0000)
+#define TIM_ICPolarity_Falling_MORT ((uint16_t)0x0002)
+#define TIM_ICPolarity_BothEdge_MORT ((uint16_t)0x000A)
+#define IS_TIM_IC_POLARITY_MORT(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising_MORT) || \
+ ((POLARITY) == TIM_ICPolarity_Falling_MORT)|| \
+ ((POLARITY) == TIM_ICPolarity_BothEdge_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection
+ * @{
+ */
+
+#define TIM_ICSelection_DirectTI_MORT ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI_MORT ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC_MORT ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IS_TIM_IC_SELECTION_MORT(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI_MORT) || \
+ ((SELECTION) == TIM_ICSelection_IndirectTI_MORT) || \
+ ((SELECTION) == TIM_ICSelection_TRC_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler
+ * @{
+ */
+
+#define TIM_ICPSC_DIV1_MORT ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2_MORT ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4_MORT ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8_MORT ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IS_TIM_IC_PRESCALER_MORT(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1_MORT) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2_MORT) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4_MORT) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_interrupt_sources
+ * @{
+ */
+
+#define TIM_IT_Update_MORT ((uint16_t)0x0001)
+#define TIM_IT_CC1_MORT ((uint16_t)0x0002)
+#define TIM_IT_CC2_MORT ((uint16_t)0x0004)
+#define TIM_IT_CC3_MORT ((uint16_t)0x0008)
+#define TIM_IT_CC4_MORT ((uint16_t)0x0010)
+#define TIM_IT_COM_MORT ((uint16_t)0x0020)
+#define TIM_IT_Trigger_MORT ((uint16_t)0x0040)
+#define TIM_IT_Break_MORT ((uint16_t)0x0080)
+#define IS_TIM_IT_MORT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_TIM_GET_IT_MORT(IT) (((IT) == TIM_IT_Update_MORT) || \
+ ((IT) == TIM_IT_CC1_MORT) || \
+ ((IT) == TIM_IT_CC2_MORT) || \
+ ((IT) == TIM_IT_CC3_MORT) || \
+ ((IT) == TIM_IT_CC4_MORT) || \
+ ((IT) == TIM_IT_COM_MORT) || \
+ ((IT) == TIM_IT_Trigger_MORT) || \
+ ((IT) == TIM_IT_Break_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address
+ * @{
+ */
+
+#define TIM_DMABase_CR1_MORT ((uint16_t)0x0000)
+#define TIM_DMABase_CR2_MORT ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR_MORT ((uint16_t)0x0002)
+#define TIM_DMABase_DIER_MORT ((uint16_t)0x0003)
+#define TIM_DMABase_SR_MORT ((uint16_t)0x0004)
+#define TIM_DMABase_EGR_MORT ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1_MORT ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2_MORT ((uint16_t)0x0007)
+#define TIM_DMABase_CCER_MORT ((uint16_t)0x0008)
+#define TIM_DMABase_CNT_MORT ((uint16_t)0x0009)
+#define TIM_DMABase_PSC_MORT ((uint16_t)0x000A)
+#define TIM_DMABase_ARR_MORT ((uint16_t)0x000B)
+#define TIM_DMABase_RCR_MORT ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1_MORT ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2_MORT ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3_MORT ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4_MORT ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR_MORT ((uint16_t)0x0011)
+#define TIM_DMABase_DCR_MORT ((uint16_t)0x0012)
+#define TIM_DMABase_OR_MORT ((uint16_t)0x0013)
+#define IS_TIM_DMA_BASE_MORT(BASE) (((BASE) == TIM_DMABase_CR1_MORT) || \
+ ((BASE) == TIM_DMABase_CR2_MORT) || \
+ ((BASE) == TIM_DMABase_SMCR_MORT) || \
+ ((BASE) == TIM_DMABase_DIER_MORT) || \
+ ((BASE) == TIM_DMABase_SR_MORT) || \
+ ((BASE) == TIM_DMABase_EGR_MORT) || \
+ ((BASE) == TIM_DMABase_CCMR1_MORT) || \
+ ((BASE) == TIM_DMABase_CCMR2_MORT) || \
+ ((BASE) == TIM_DMABase_CCER_MORT) || \
+ ((BASE) == TIM_DMABase_CNT_MORT) || \
+ ((BASE) == TIM_DMABase_PSC_MORT) || \
+ ((BASE) == TIM_DMABase_ARR_MORT) || \
+ ((BASE) == TIM_DMABase_RCR_MORT) || \
+ ((BASE) == TIM_DMABase_CCR1_MORT) || \
+ ((BASE) == TIM_DMABase_CCR2_MORT) || \
+ ((BASE) == TIM_DMABase_CCR3_MORT) || \
+ ((BASE) == TIM_DMABase_CCR4_MORT) || \
+ ((BASE) == TIM_DMABase_BDTR_MORT) || \
+ ((BASE) == TIM_DMABase_DCR_MORT) || \
+ ((BASE) == TIM_DMABase_OR_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Transfer_MORT ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers_MORT ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers_MORT ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers_MORT ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers_MORT ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers_MORT ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers_MORT ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers_MORT ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers_MORT ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers_MORT ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers_MORT ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers_MORT ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers_MORT ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers_MORT ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers_MORT ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers_MORT ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers_MORT ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers_MORT ((uint16_t)0x1100)
+#define IS_TIM_DMA_LENGTH_MORT(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_2Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_3Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_4Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_5Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_6Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_7Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_8Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_9Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_10Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_11Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_12Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_13Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_14Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_15Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_16Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_17Transfers_MORT) || \
+ ((LENGTH) == TIM_DMABurstLength_18Transfers_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_sources
+ * @{
+ */
+
+#define TIM_DMA_Update_MORT ((uint16_t)0x0100)
+#define TIM_DMA_CC1_MORT ((uint16_t)0x0200)
+#define TIM_DMA_CC2_MORT ((uint16_t)0x0400)
+#define TIM_DMA_CC3_MORT ((uint16_t)0x0800)
+#define TIM_DMA_CC4_MORT ((uint16_t)0x1000)
+#define TIM_DMA_COM_MORT ((uint16_t)0x2000)
+#define TIM_DMA_Trigger_MORT ((uint16_t)0x4000)
+#define IS_TIM_DMA_SOURCE_MORT(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Prescaler
+ * @{
+ */
+
+#define TIM_ExtTRGPSC_OFF_MORT ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2_MORT ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4_MORT ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8_MORT ((uint16_t)0x3000)
+#define IS_TIM_EXT_PRESCALER_MORT(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF_MORT) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2_MORT) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4_MORT) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Internal_Trigger_Selection
+ * @{
+ */
+
+#define TIM_TS_ITR0_MORT ((uint16_t)0x0000)
+#define TIM_TS_ITR1_MORT ((uint16_t)0x0010)
+#define TIM_TS_ITR2_MORT ((uint16_t)0x0020)
+#define TIM_TS_ITR3_MORT ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED_MORT ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1_MORT ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2_MORT ((uint16_t)0x0060)
+#define TIM_TS_ETRF_MORT ((uint16_t)0x0070)
+#define IS_TIM_TRIGGER_SELECTION_MORT(SELECTION) (((SELECTION) == TIM_TS_ITR0_MORT) || \
+ ((SELECTION) == TIM_TS_ITR1_MORT) || \
+ ((SELECTION) == TIM_TS_ITR2_MORT) || \
+ ((SELECTION) == TIM_TS_ITR3_MORT) || \
+ ((SELECTION) == TIM_TS_TI1F_ED_MORT) || \
+ ((SELECTION) == TIM_TS_TI1FP1_MORT) || \
+ ((SELECTION) == TIM_TS_TI2FP2_MORT) || \
+ ((SELECTION) == TIM_TS_ETRF_MORT))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION_MORT(SELECTION) (((SELECTION) == TIM_TS_ITR0_MORT) || \
+ ((SELECTION) == TIM_TS_ITR1_MORT) || \
+ ((SELECTION) == TIM_TS_ITR2_MORT) || \
+ ((SELECTION) == TIM_TS_ITR3_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_TIx_External_Clock_Source
+ * @{
+ */
+
+#define TIM_TIxExternalCLK1Source_TI1_MORT ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2_MORT ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED_MORT ((uint16_t)0x0040)
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Polarity
+ * @{
+ */
+#define TIM_ExtTRGPolarity_Inverted_MORT ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted_MORT ((uint16_t)0x0000)
+#define IS_TIM_EXT_POLARITY_MORT(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted_MORT) || \
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Prescaler_Reload_Mode
+ * @{
+ */
+
+#define TIM_PSCReloadMode_Update_MORT ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate_MORT ((uint16_t)0x0001)
+#define IS_TIM_PRESCALER_RELOAD_MORT(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update_MORT) || \
+ ((RELOAD) == TIM_PSCReloadMode_Immediate_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Forced_Action
+ * @{
+ */
+
+#define TIM_ForcedAction_Active_MORT ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive_MORT ((uint16_t)0x0040)
+#define IS_TIM_FORCED_ACTION_MORT(ACTION) (((ACTION) == TIM_ForcedAction_Active_MORT) || \
+ ((ACTION) == TIM_ForcedAction_InActive_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Mode
+ * @{
+ */
+
+#define TIM_EncoderMode_TI1_MORT ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2_MORT ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12_MORT ((uint16_t)0x0003)
+#define IS_TIM_ENCODER_MODE_MORT(MODE) (((MODE) == TIM_EncoderMode_TI1_MORT) || \
+ ((MODE) == TIM_EncoderMode_TI2_MORT) || \
+ ((MODE) == TIM_EncoderMode_TI12_MORT))
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_Event_Source
+ * @{
+ */
+
+#define TIM_EventSource_Update_MORT ((uint16_t)0x0001)
+#define TIM_EventSource_CC1_MORT ((uint16_t)0x0002)
+#define TIM_EventSource_CC2_MORT ((uint16_t)0x0004)
+#define TIM_EventSource_CC3_MORT ((uint16_t)0x0008)
+#define TIM_EventSource_CC4_MORT ((uint16_t)0x0010)
+#define TIM_EventSource_COM_MORT ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger_MORT ((uint16_t)0x0040)
+#define TIM_EventSource_Break_MORT ((uint16_t)0x0080)
+#define IS_TIM_EVENT_SOURCE_MORT(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Update_Source
+ * @{
+ */
+
+#define TIM_UpdateSource_Global_MORT ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller. */
+#define TIM_UpdateSource_Regular_MORT ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IS_TIM_UPDATE_SOURCE_MORT(SOURCE) (((SOURCE) == TIM_UpdateSource_Global_MORT) || \
+ ((SOURCE) == TIM_UpdateSource_Regular_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Preload_State
+ * @{
+ */
+
+#define TIM_OCPreload_Enable_MORT ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable_MORT ((uint16_t)0x0000)
+#define IS_TIM_OCPRELOAD_STATE_MORT(STATE) (((STATE) == TIM_OCPreload_Enable_MORT) || \
+ ((STATE) == TIM_OCPreload_Disable_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Fast_State
+ * @{
+ */
+
+#define TIM_OCFast_Enable_MORT ((uint16_t)0x0004)
+#define TIM_OCFast_Disable_MORT ((uint16_t)0x0000)
+#define IS_TIM_OCFAST_STATE_MORT(STATE) (((STATE) == TIM_OCFast_Enable_MORT) || \
+ ((STATE) == TIM_OCFast_Disable_MORT))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Clear_State
+ * @{
+ */
+
+#define TIM_OCClear_Enable_MORT ((uint16_t)0x0080)
+#define TIM_OCClear_Disable_MORT ((uint16_t)0x0000)
+#define IS_TIM_OCCLEAR_STATE_MORT(STATE) (((STATE) == TIM_OCClear_Enable_MORT) || \
+ ((STATE) == TIM_OCClear_Disable_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Output_Source
+ * @{
+ */
+
+#define TIM_TRGOSource_Reset_MORT ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable_MORT ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update_MORT ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1_MORT ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref_MORT ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref_MORT ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref_MORT ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref_MORT ((uint16_t)0x0070)
+#define IS_TIM_TRGO_SOURCE_MORT(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset_MORT) || \
+ ((SOURCE) == TIM_TRGOSource_Enable_MORT) || \
+ ((SOURCE) == TIM_TRGOSource_Update_MORT) || \
+ ((SOURCE) == TIM_TRGOSource_OC1_MORT) || \
+ ((SOURCE) == TIM_TRGOSource_OC1Ref_MORT) || \
+ ((SOURCE) == TIM_TRGOSource_OC2Ref_MORT) || \
+ ((SOURCE) == TIM_TRGOSource_OC3Ref_MORT) || \
+ ((SOURCE) == TIM_TRGOSource_OC4Ref_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Slave_Mode
+ * @{
+ */
+
+#define TIM_SlaveMode_Reset_MORT ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated_MORT ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger_MORT ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1_MORT ((uint16_t)0x0007)
+#define IS_TIM_SLAVE_MODE_MORT(MODE) (((MODE) == TIM_SlaveMode_Reset_MORT) || \
+ ((MODE) == TIM_SlaveMode_Gated_MORT) || \
+ ((MODE) == TIM_SlaveMode_Trigger_MORT) || \
+ ((MODE) == TIM_SlaveMode_External1_MORT))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode
+ * @{
+ */
+
+#define TIM_MasterSlaveMode_Enable_MORT ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable_MORT ((uint16_t)0x0000)
+#define IS_TIM_MSM_STATE_MORT(STATE) (((STATE) == TIM_MasterSlaveMode_Enable_MORT) || \
+ ((STATE) == TIM_MasterSlaveMode_Disable_MORT))
+/**
+ * @}
+ */
+/** @defgroup TIM_Remap
+ * @{
+ */
+
+#define TIM2_TIM8_TRGO_MORT ((uint16_t)0x0000)
+#define TIM2_ETH_PTP_MORT ((uint16_t)0x0400)
+#define TIM2_USBFS_SOF_MORT ((uint16_t)0x0800)
+#define TIM2_USBHS_SOF_MORT ((uint16_t)0x0C00)
+
+#define TIM5_GPIO_MORT ((uint16_t)0x0000)
+#define TIM5_LSI_MORT ((uint16_t)0x0040)
+#define TIM5_LSE_MORT ((uint16_t)0x0080)
+#define TIM5_RTC_MORT ((uint16_t)0x00C0)
+
+#define TIM11_GPIO_MORT ((uint16_t)0x0000)
+#define TIM11_HSE_MORT ((uint16_t)0x0002)
+
+#define IS_TIM_REMAP_MORT(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO_MORT)||\
+ ((TIM_REMAP) == TIM2_ETH_PTP_MORT)||\
+ ((TIM_REMAP) == TIM2_USBFS_SOF_MORT)||\
+ ((TIM_REMAP) == TIM2_USBHS_SOF_MORT)||\
+ ((TIM_REMAP) == TIM5_GPIO_MORT)||\
+ ((TIM_REMAP) == TIM5_LSI_MORT)||\
+ ((TIM_REMAP) == TIM5_LSE_MORT)||\
+ ((TIM_REMAP) == TIM5_RTC_MORT)||\
+ ((TIM_REMAP) == TIM11_GPIO_MORT)||\
+ ((TIM_REMAP) == TIM11_HSE_MORT))
+
+/**
+ * @}
+ */
+/** @defgroup TIM_Flags
+ * @{
+ */
+
+#define TIM_FLAG_Update_MORT ((uint16_t)0x0001)
+#define TIM_FLAG_CC1_MORT ((uint16_t)0x0002)
+#define TIM_FLAG_CC2_MORT ((uint16_t)0x0004)
+#define TIM_FLAG_CC3_MORT ((uint16_t)0x0008)
+#define TIM_FLAG_CC4_MORT ((uint16_t)0x0010)
+#define TIM_FLAG_COM_MORT ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger_MORT ((uint16_t)0x0040)
+#define TIM_FLAG_Break_MORT ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF_MORT ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF_MORT ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF_MORT ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF_MORT ((uint16_t)0x1000)
+#define IS_TIM_GET_FLAG_MORT(FLAG) (((FLAG) == TIM_FLAG_Update_MORT) || \
+ ((FLAG) == TIM_FLAG_CC1_MORT) || \
+ ((FLAG) == TIM_FLAG_CC2_MORT) || \
+ ((FLAG) == TIM_FLAG_CC3_MORT) || \
+ ((FLAG) == TIM_FLAG_CC4_MORT) || \
+ ((FLAG) == TIM_FLAG_COM_MORT) || \
+ ((FLAG) == TIM_FLAG_Trigger_MORT) || \
+ ((FLAG) == TIM_FLAG_Break_MORT) || \
+ ((FLAG) == TIM_FLAG_CC1OF_MORT) || \
+ ((FLAG) == TIM_FLAG_CC2OF_MORT) || \
+ ((FLAG) == TIM_FLAG_CC3OF_MORT) || \
+ ((FLAG) == TIM_FLAG_CC4OF_MORT))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Filer_Value
+ * @{
+ */
+
+#define IS_TIM_IC_FILTER_MORT(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Filter
+ * @{
+ */
+
+#define IS_TIM_EXT_FILTER_MORT(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Legacy
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Byte_MORT TIM_DMABurstLength_1Transfer_MORT
+#define TIM_DMABurstLength_2Bytes_MORT TIM_DMABurstLength_2Transfers_MORT
+#define TIM_DMABurstLength_3Bytes_MORT TIM_DMABurstLength_3Transfers_MORT
+#define TIM_DMABurstLength_4Bytes_MORT TIM_DMABurstLength_4Transfers_MORT
+#define TIM_DMABurstLength_5Bytes_MORT TIM_DMABurstLength_5Transfers_MORT
+#define TIM_DMABurstLength_6Bytes_MORT TIM_DMABurstLength_6Transfers_MORT
+#define TIM_DMABurstLength_7Bytes_MORT TIM_DMABurstLength_7Transfers_MORT
+#define TIM_DMABurstLength_8Bytes_MORT TIM_DMABurstLength_8Transfers_MORT
+#define TIM_DMABurstLength_9Bytes_MORT TIM_DMABurstLength_9Transfers_MORT
+#define TIM_DMABurstLength_10Bytes_MORT TIM_DMABurstLength_10Transfers_MORT
+#define TIM_DMABurstLength_11Bytes_MORT TIM_DMABurstLength_11Transfers_MORT
+#define TIM_DMABurstLength_12Bytes_MORT TIM_DMABurstLength_12Transfers_MORT
+#define TIM_DMABurstLength_13Bytes_MORT TIM_DMABurstLength_13Transfers_MORT
+#define TIM_DMABurstLength_14Bytes_MORT TIM_DMABurstLength_14Transfers_MORT
+#define TIM_DMABurstLength_15Bytes_MORT TIM_DMABurstLength_15Transfers_MORT
+#define TIM_DMABurstLength_16Bytes_MORT TIM_DMABurstLength_16Transfers_MORT
+#define TIM_DMABurstLength_17Bytes_MORT TIM_DMABurstLength_17Transfers_MORT
+#define TIM_DMABurstLength_18Bytes_MORT TIM_DMABurstLength_18Transfers_MORT
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* TimeBase management ********************************************************/
+void TIM_DeInit_mort(TIM_TypeDef_mort* TIMx);
+void TIM_TimeBaseInit_mort(TIM_TypeDef_mort* TIMx, TIM_TimeBaseInitTypeDef_mort* TIM_TimeBaseInitStruct);
+void TIM_TimeBaseStructInit_mort(TIM_TimeBaseInitTypeDef_mort* TIM_TimeBaseInitStruct);
+void TIM_PrescalerConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_CounterMode);
+void TIM_SetCounter_mort(TIM_TypeDef_mort* TIMx, uint32_t Counter);
+void TIM_SetAutoreload_mort(TIM_TypeDef_mort* TIMx, uint32_t Autoreload);
+uint32_t TIM_GetCounter_mort(TIM_TypeDef_mort* TIMx);
+uint16_t TIM_GetPrescaler_mort(TIM_TypeDef_mort* TIMx);
+void TIM_UpdateDisableConfig_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_UpdateSource);
+void TIM_ARRPreloadConfig_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OPMode);
+void TIM_SetClockDivision_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_CKD);
+void TIM_Cmd_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
+
+/* Output Compare management **************************************************/
+void TIM_OC1Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct);
+void TIM_OC2Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct);
+void TIM_OC3Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct);
+void TIM_OC4Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct);
+void TIM_OCStructInit_mort(TIM_OCInitTypeDef_mort* TIM_OCInitStruct);
+void TIM_SelectOCxM_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void TIM_SetCompare1_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare1);
+void TIM_SetCompare2_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare2);
+void TIM_SetCompare3_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare3);
+void TIM_SetCompare4_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare4);
+void TIM_ForcedOC1Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction);
+void TIM_OC1PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity);
+void TIM_CCxCmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+
+/* Input Capture management ***************************************************/
+void TIM_ICInit_mort(TIM_TypeDef_mort* TIMx, TIM_ICInitTypeDef_mort* TIM_ICInitStruct);
+void TIM_ICStructInit_mort(TIM_ICInitTypeDef_mort* TIM_ICInitStruct);
+void TIM_PWMIConfig_mort(TIM_TypeDef_mort* TIMx, TIM_ICInitTypeDef_mort* TIM_ICInitStruct);
+uint32_t TIM_GetCapture1_mort(TIM_TypeDef_mort* TIMx);
+uint32_t TIM_GetCapture2_mort(TIM_TypeDef_mort* TIMx);
+uint32_t TIM_GetCapture3_mort(TIM_TypeDef_mort* TIMx);
+uint32_t TIM_GetCapture4_mort(TIM_TypeDef_mort* TIMx);
+void TIM_SetIC1Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC);
+
+/* Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features ******************/
+void TIM_BDTRConfig_mort(TIM_TypeDef_mort* TIMx, TIM_BDTRInitTypeDef_mort *TIM_BDTRInitStruct);
+void TIM_BDTRStructInit_mort(TIM_BDTRInitTypeDef_mort* TIM_BDTRInitStruct);
+void TIM_CtrlPWMOutputs_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
+void TIM_SelectCOM_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
+void TIM_CCPreloadControl_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
+
+/* Interrupts, DMA and flags management ***************************************/
+void TIM_ITConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_EventSource);
+FlagStatus TIM_GetFlagStatus_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT);
+void TIM_DMAConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_SelectCCDMA_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
+
+/* Clocks management **********************************************************/
+void TIM_InternalClockConfig_mort(TIM_TypeDef_mort* TIMx);
+void TIM_ITRxExternalClockConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_TIxExternalCLKSource,
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+
+/* Synchronization management *************************************************/
+void TIM_SelectInputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_SelectOutputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_ETRConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+
+/* Specific interface management **********************************************/
+void TIM_EncoderInterfaceConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_SelectHallSensor_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
+
+/* Specific remapping management **********************************************/
+void TIM_RemapConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Remap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_TIM_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
+