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Dependencies:   mbed

stm32f4xx_rcc_mort.h@0:34ee385f4d2d, 2021-10-23 (annotated)

Committer:
rajathr
Date:
Sat Oct 23 05:49:09 2021 +0000
Revision:
0:34ee385f4d2d
At 23rd Oct 21 - All Code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rajathr 0:34ee385f4d2d 1 /**
rajathr 0:34ee385f4d2d 2 ******************************************************************************
rajathr 0:34ee385f4d2d 3 * @file stm32f4xx_rcc.h
rajathr 0:34ee385f4d2d 4 * @author MCD Application Team
rajathr 0:34ee385f4d2d 5 * @version V1.8.0
rajathr 0:34ee385f4d2d 6 * @date 04-November-2016
rajathr 0:34ee385f4d2d 7 * @brief This file contains all the functions prototypes for the RCC firmware library.
rajathr 0:34ee385f4d2d 8 ******************************************************************************
rajathr 0:34ee385f4d2d 9 * @attention
rajathr 0:34ee385f4d2d 10 *
rajathr 0:34ee385f4d2d 11 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
rajathr 0:34ee385f4d2d 12 *
rajathr 0:34ee385f4d2d 13 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
rajathr 0:34ee385f4d2d 14 * You may not use this file except in compliance with the License.
rajathr 0:34ee385f4d2d 15 * You may obtain a copy of the License at:
rajathr 0:34ee385f4d2d 16 *
rajathr 0:34ee385f4d2d 17 * http://www.st.com/software_license_agreement_liberty_v2
rajathr 0:34ee385f4d2d 18 *
rajathr 0:34ee385f4d2d 19 * Unless required by applicable law or agreed to in writing, software
rajathr 0:34ee385f4d2d 20 * distributed under the License is distributed on an "AS IS" BASIS,
rajathr 0:34ee385f4d2d 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
rajathr 0:34ee385f4d2d 22 * See the License for the specific language governing permissions and
rajathr 0:34ee385f4d2d 23 * limitations under the License.
rajathr 0:34ee385f4d2d 24 *
rajathr 0:34ee385f4d2d 25 ******************************************************************************
rajathr 0:34ee385f4d2d 26 */
rajathr 0:34ee385f4d2d 27
rajathr 0:34ee385f4d2d 28 /* Define to prevent recursive inclusion -------------------------------------*/
rajathr 0:34ee385f4d2d 29 #ifndef __STM32F4xx_RCC_H_MORT
rajathr 0:34ee385f4d2d 30 #define __STM32F4xx_RCC_H_MORT
rajathr 0:34ee385f4d2d 31
rajathr 0:34ee385f4d2d 32 #ifdef __cplusplus
rajathr 0:34ee385f4d2d 33 extern "C" {
rajathr 0:34ee385f4d2d 34 #endif
rajathr 0:34ee385f4d2d 35
rajathr 0:34ee385f4d2d 36 /* Includes ------------------------------------------------------------------*/
rajathr 0:34ee385f4d2d 37 #include "stm32f4xx_mort2.h"
rajathr 0:34ee385f4d2d 38
rajathr 0:34ee385f4d2d 39 /** @addtogroup STM32F4xx_StdPeriph_Driver
rajathr 0:34ee385f4d2d 40 * @{
rajathr 0:34ee385f4d2d 41 */
rajathr 0:34ee385f4d2d 42
rajathr 0:34ee385f4d2d 43 /** @addtogroup RCC
rajathr 0:34ee385f4d2d 44 * @{
rajathr 0:34ee385f4d2d 45 */
rajathr 0:34ee385f4d2d 46
rajathr 0:34ee385f4d2d 47 /* Exported types ------------------------------------------------------------*/
rajathr 0:34ee385f4d2d 48 typedef struct
rajathr 0:34ee385f4d2d 49 {
rajathr 0:34ee385f4d2d 50 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
rajathr 0:34ee385f4d2d 51 uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
rajathr 0:34ee385f4d2d 52 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
rajathr 0:34ee385f4d2d 53 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
rajathr 0:34ee385f4d2d 54 }RCC_ClocksTypeDef;
rajathr 0:34ee385f4d2d 55
rajathr 0:34ee385f4d2d 56 /* Exported constants --------------------------------------------------------*/
rajathr 0:34ee385f4d2d 57
rajathr 0:34ee385f4d2d 58 /** @defgroup RCC_Exported_Constants
rajathr 0:34ee385f4d2d 59 * @{
rajathr 0:34ee385f4d2d 60 */
rajathr 0:34ee385f4d2d 61
rajathr 0:34ee385f4d2d 62 /** @defgroup RCC_HSE_configuration
rajathr 0:34ee385f4d2d 63 * @{
rajathr 0:34ee385f4d2d 64 */
rajathr 0:34ee385f4d2d 65 #define RCC_HSE_OFF_MORT ((uint8_t)0x00)
rajathr 0:34ee385f4d2d 66 #define RCC_HSE_ON_MORT ((uint8_t)0x01)
rajathr 0:34ee385f4d2d 67 #define RCC_HSE_Bypass ((uint8_t)0x05)
rajathr 0:34ee385f4d2d 68 #define IS_RCC_HSE_MORT(HSE) (((HSE) == RCC_HSE_OFF_MORT) || ((HSE) == RCC_HSE_ON_MORT) || \
rajathr 0:34ee385f4d2d 69 ((HSE) == RCC_HSE_Bypass))
rajathr 0:34ee385f4d2d 70 /**
rajathr 0:34ee385f4d2d 71 * @}
rajathr 0:34ee385f4d2d 72 */
rajathr 0:34ee385f4d2d 73
rajathr 0:34ee385f4d2d 74 /** @defgroup RCC_LSE_Dual_Mode_Selection
rajathr 0:34ee385f4d2d 75 * @{
rajathr 0:34ee385f4d2d 76 */
rajathr 0:34ee385f4d2d 77 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
rajathr 0:34ee385f4d2d 78 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
rajathr 0:34ee385f4d2d 79 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
rajathr 0:34ee385f4d2d 80 ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
rajathr 0:34ee385f4d2d 81 /**
rajathr 0:34ee385f4d2d 82 * @}
rajathr 0:34ee385f4d2d 83 */
rajathr 0:34ee385f4d2d 84
rajathr 0:34ee385f4d2d 85 /** @defgroup RCC_PLLSAIDivR_Factor
rajathr 0:34ee385f4d2d 86 * @{
rajathr 0:34ee385f4d2d 87 */
rajathr 0:34ee385f4d2d 88 #define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 89 #define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
rajathr 0:34ee385f4d2d 90 #define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
rajathr 0:34ee385f4d2d 91 #define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
rajathr 0:34ee385f4d2d 92 #define IS_RCC_PLLSAI_DIVR_VALUE_MORT(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
rajathr 0:34ee385f4d2d 93 ((VALUE) == RCC_PLLSAIDivR_Div4) ||\
rajathr 0:34ee385f4d2d 94 ((VALUE) == RCC_PLLSAIDivR_Div8) ||\
rajathr 0:34ee385f4d2d 95 ((VALUE) == RCC_PLLSAIDivR_Div16))
rajathr 0:34ee385f4d2d 96 /**
rajathr 0:34ee385f4d2d 97 * @}
rajathr 0:34ee385f4d2d 98 */
rajathr 0:34ee385f4d2d 99
rajathr 0:34ee385f4d2d 100 /** @defgroup RCC_PLL_Clock_Source
rajathr 0:34ee385f4d2d 101 * @{
rajathr 0:34ee385f4d2d 102 */
rajathr 0:34ee385f4d2d 103 #define RCC_PLLSource_HSI ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 104 #define RCC_PLLSource_HSE ((uint32_t)0x00400000)
rajathr 0:34ee385f4d2d 105 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
rajathr 0:34ee385f4d2d 106 ((SOURCE) == RCC_PLLSource_HSE))
rajathr 0:34ee385f4d2d 107 #define IS_RCC_PLLM_VALUE_MORT(VALUE) ((VALUE) <= 63)
rajathr 0:34ee385f4d2d 108 #define IS_RCC_PLLN_VALUE_MORT(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
rajathr 0:34ee385f4d2d 109 #define IS_RCC_PLLP_VALUE_MORT(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
rajathr 0:34ee385f4d2d 110 #define IS_RCC_PLLQ_VALUE_MORT(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
rajathr 0:34ee385f4d2d 111 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 112 #define IS_RCC_PLLR_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
rajathr 0:34ee385f4d2d 113 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 114
rajathr 0:34ee385f4d2d 115 #define IS_RCC_PLLI2SN_VALUE_MORT(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
rajathr 0:34ee385f4d2d 116 #define IS_RCC_PLLI2SR_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
rajathr 0:34ee385f4d2d 117 #define IS_RCC_PLLI2SM_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
rajathr 0:34ee385f4d2d 118 #define IS_RCC_PLLI2SQ_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
rajathr 0:34ee385f4d2d 119 #if defined(STM32F446xx)
rajathr 0:34ee385f4d2d 120 #define IS_RCC_PLLI2SP_VALUE_MORT(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
rajathr 0:34ee385f4d2d 121 #define IS_RCC_PLLSAIM_VALUE_MORT(VALUE) ((VALUE) <= 63)
rajathr 0:34ee385f4d2d 122 #elif defined(STM32F412xG) || defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 123 #define IS_RCC_PLLI2SP_VALUE_MORT(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
rajathr 0:34ee385f4d2d 124 #else
rajathr 0:34ee385f4d2d 125 #endif /* STM32F446xx */
rajathr 0:34ee385f4d2d 126 #define IS_RCC_PLLSAIN_VALUE_MORT(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
rajathr 0:34ee385f4d2d 127 #if defined(STM32F446xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 128 #define IS_RCC_PLLSAIP_VALUE_MORT(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
rajathr 0:34ee385f4d2d 129 #endif /* STM32F446xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 130 #define IS_RCC_PLLSAIQ_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
rajathr 0:34ee385f4d2d 131 #define IS_RCC_PLLSAIR_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
rajathr 0:34ee385f4d2d 132
rajathr 0:34ee385f4d2d 133 #define IS_RCC_PLLSAI_DIVQ_VALUE_MORT(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
rajathr 0:34ee385f4d2d 134 #define IS_RCC_PLLI2S_DIVQ_VALUE_MORT(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
rajathr 0:34ee385f4d2d 135
rajathr 0:34ee385f4d2d 136 #if defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 137 #define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
rajathr 0:34ee385f4d2d 138 #define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
rajathr 0:34ee385f4d2d 139 #endif /* STM32F413_423xx */
rajathr 0:34ee385f4d2d 140 /**
rajathr 0:34ee385f4d2d 141 * @}
rajathr 0:34ee385f4d2d 142 */
rajathr 0:34ee385f4d2d 143
rajathr 0:34ee385f4d2d 144 /** @defgroup RCC_System_Clock_Source
rajathr 0:34ee385f4d2d 145 * @{
rajathr 0:34ee385f4d2d 146 */
rajathr 0:34ee385f4d2d 147
rajathr 0:34ee385f4d2d 148 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
rajathr 0:34ee385f4d2d 149 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 150 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
rajathr 0:34ee385f4d2d 151 #define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)
rajathr 0:34ee385f4d2d 152 #define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003)
rajathr 0:34ee385f4d2d 153 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
rajathr 0:34ee385f4d2d 154 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
rajathr 0:34ee385f4d2d 155 ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \
rajathr 0:34ee385f4d2d 156 ((SOURCE) == RCC_SYSCLKSource_PLLRCLK))
rajathr 0:34ee385f4d2d 157 /* Add legacy definition */
rajathr 0:34ee385f4d2d 158 #define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK
rajathr 0:34ee385f4d2d 159 #endif /* STM32F446xx */
rajathr 0:34ee385f4d2d 160
rajathr 0:34ee385f4d2d 161 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 162 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 163 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
rajathr 0:34ee385f4d2d 164 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
rajathr 0:34ee385f4d2d 165 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
rajathr 0:34ee385f4d2d 166 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
rajathr 0:34ee385f4d2d 167 ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
rajathr 0:34ee385f4d2d 168 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
rajathr 0:34ee385f4d2d 169 /**
rajathr 0:34ee385f4d2d 170 * @}
rajathr 0:34ee385f4d2d 171 */
rajathr 0:34ee385f4d2d 172
rajathr 0:34ee385f4d2d 173 /** @defgroup RCC_AHB_Clock_Source
rajathr 0:34ee385f4d2d 174 * @{
rajathr 0:34ee385f4d2d 175 */
rajathr 0:34ee385f4d2d 176 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 177 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
rajathr 0:34ee385f4d2d 178 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
rajathr 0:34ee385f4d2d 179 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
rajathr 0:34ee385f4d2d 180 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
rajathr 0:34ee385f4d2d 181 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
rajathr 0:34ee385f4d2d 182 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
rajathr 0:34ee385f4d2d 183 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
rajathr 0:34ee385f4d2d 184 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
rajathr 0:34ee385f4d2d 185 #define IS_RCC_HCLK_MORT(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
rajathr 0:34ee385f4d2d 186 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
rajathr 0:34ee385f4d2d 187 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
rajathr 0:34ee385f4d2d 188 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
rajathr 0:34ee385f4d2d 189 ((HCLK) == RCC_SYSCLK_Div512))
rajathr 0:34ee385f4d2d 190 /**
rajathr 0:34ee385f4d2d 191 * @}
rajathr 0:34ee385f4d2d 192 */
rajathr 0:34ee385f4d2d 193
rajathr 0:34ee385f4d2d 194 /** @defgroup RCC_APB1_APB2_Clock_Source
rajathr 0:34ee385f4d2d 195 * @{
rajathr 0:34ee385f4d2d 196 */
rajathr 0:34ee385f4d2d 197 #define RCC_HCLK_Div1 ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 198 #define RCC_HCLK_Div2 ((uint32_t)0x00001000)
rajathr 0:34ee385f4d2d 199 #define RCC_HCLK_Div4 ((uint32_t)0x00001400)
rajathr 0:34ee385f4d2d 200 #define RCC_HCLK_Div8 ((uint32_t)0x00001800)
rajathr 0:34ee385f4d2d 201 #define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
rajathr 0:34ee385f4d2d 202 #define IS_RCC_PCLK_MORT(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
rajathr 0:34ee385f4d2d 203 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
rajathr 0:34ee385f4d2d 204 ((PCLK) == RCC_HCLK_Div16))
rajathr 0:34ee385f4d2d 205 /**
rajathr 0:34ee385f4d2d 206 * @}
rajathr 0:34ee385f4d2d 207 */
rajathr 0:34ee385f4d2d 208
rajathr 0:34ee385f4d2d 209 /** @defgroup RCC_Interrupt_Source
rajathr 0:34ee385f4d2d 210 * @{
rajathr 0:34ee385f4d2d 211 */
rajathr 0:34ee385f4d2d 212 #define RCC_IT_LSIRDY ((uint8_t)0x01)
rajathr 0:34ee385f4d2d 213 #define RCC_IT_LSERDY ((uint8_t)0x02)
rajathr 0:34ee385f4d2d 214 #define RCC_IT_HSIRDY ((uint8_t)0x04)
rajathr 0:34ee385f4d2d 215 #define RCC_IT_HSERDY ((uint8_t)0x08)
rajathr 0:34ee385f4d2d 216 #define RCC_IT_PLLRDY ((uint8_t)0x10)
rajathr 0:34ee385f4d2d 217 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
rajathr 0:34ee385f4d2d 218 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
rajathr 0:34ee385f4d2d 219 #define RCC_IT_CSS ((uint8_t)0x80)
rajathr 0:34ee385f4d2d 220
rajathr 0:34ee385f4d2d 221 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
rajathr 0:34ee385f4d2d 222 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
rajathr 0:34ee385f4d2d 223 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
rajathr 0:34ee385f4d2d 224 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
rajathr 0:34ee385f4d2d 225 ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
rajathr 0:34ee385f4d2d 226 #define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)
rajathr 0:34ee385f4d2d 227
rajathr 0:34ee385f4d2d 228 /**
rajathr 0:34ee385f4d2d 229 * @}
rajathr 0:34ee385f4d2d 230 */
rajathr 0:34ee385f4d2d 231
rajathr 0:34ee385f4d2d 232 /** @defgroup RCC_LSE_Configuration
rajathr 0:34ee385f4d2d 233 * @{
rajathr 0:34ee385f4d2d 234 */
rajathr 0:34ee385f4d2d 235 #define RCC_LSE_OFF_MORT ((uint8_t)0x00)
rajathr 0:34ee385f4d2d 236 #define RCC_LSE_ON_MORT ((uint8_t)0x01)
rajathr 0:34ee385f4d2d 237 #define RCC_LSE_Bypass ((uint8_t)0x04)
rajathr 0:34ee385f4d2d 238 #define IS_RCC_LSE_MORT(LSE) (((LSE) == RCC_LSE_OFF_MORT) || ((LSE) == RCC_LSE_ON_MORT) || \
rajathr 0:34ee385f4d2d 239 ((LSE) == RCC_LSE_Bypass))
rajathr 0:34ee385f4d2d 240 /**
rajathr 0:34ee385f4d2d 241 * @}
rajathr 0:34ee385f4d2d 242 */
rajathr 0:34ee385f4d2d 243
rajathr 0:34ee385f4d2d 244 /** @defgroup RCC_RTC_Clock_Source
rajathr 0:34ee385f4d2d 245 * @{
rajathr 0:34ee385f4d2d 246 */
rajathr 0:34ee385f4d2d 247 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
rajathr 0:34ee385f4d2d 248 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
rajathr 0:34ee385f4d2d 249 #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
rajathr 0:34ee385f4d2d 250 #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
rajathr 0:34ee385f4d2d 251 #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
rajathr 0:34ee385f4d2d 252 #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
rajathr 0:34ee385f4d2d 253 #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
rajathr 0:34ee385f4d2d 254 #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
rajathr 0:34ee385f4d2d 255 #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
rajathr 0:34ee385f4d2d 256 #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
rajathr 0:34ee385f4d2d 257 #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
rajathr 0:34ee385f4d2d 258 #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
rajathr 0:34ee385f4d2d 259 #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
rajathr 0:34ee385f4d2d 260 #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
rajathr 0:34ee385f4d2d 261 #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
rajathr 0:34ee385f4d2d 262 #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
rajathr 0:34ee385f4d2d 263 #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
rajathr 0:34ee385f4d2d 264 #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
rajathr 0:34ee385f4d2d 265 #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
rajathr 0:34ee385f4d2d 266 #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
rajathr 0:34ee385f4d2d 267 #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
rajathr 0:34ee385f4d2d 268 #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
rajathr 0:34ee385f4d2d 269 #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
rajathr 0:34ee385f4d2d 270 #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
rajathr 0:34ee385f4d2d 271 #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
rajathr 0:34ee385f4d2d 272 #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
rajathr 0:34ee385f4d2d 273 #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
rajathr 0:34ee385f4d2d 274 #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
rajathr 0:34ee385f4d2d 275 #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
rajathr 0:34ee385f4d2d 276 #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
rajathr 0:34ee385f4d2d 277 #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
rajathr 0:34ee385f4d2d 278 #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
rajathr 0:34ee385f4d2d 279 #define IS_RCC_RTCCLK_SOURCE_MORT(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
rajathr 0:34ee385f4d2d 280 ((SOURCE) == RCC_RTCCLKSource_LSI) || \
rajathr 0:34ee385f4d2d 281 ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
rajathr 0:34ee385f4d2d 282 ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
rajathr 0:34ee385f4d2d 283 ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
rajathr 0:34ee385f4d2d 284 ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
rajathr 0:34ee385f4d2d 285 ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
rajathr 0:34ee385f4d2d 286 ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
rajathr 0:34ee385f4d2d 287 ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
rajathr 0:34ee385f4d2d 288 ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
rajathr 0:34ee385f4d2d 289 ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
rajathr 0:34ee385f4d2d 290 ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
rajathr 0:34ee385f4d2d 291 ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
rajathr 0:34ee385f4d2d 292 ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
rajathr 0:34ee385f4d2d 293 ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
rajathr 0:34ee385f4d2d 294 ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
rajathr 0:34ee385f4d2d 295 ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
rajathr 0:34ee385f4d2d 296 ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
rajathr 0:34ee385f4d2d 297 ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
rajathr 0:34ee385f4d2d 298 ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
rajathr 0:34ee385f4d2d 299 ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
rajathr 0:34ee385f4d2d 300 ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
rajathr 0:34ee385f4d2d 301 ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
rajathr 0:34ee385f4d2d 302 ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
rajathr 0:34ee385f4d2d 303 ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
rajathr 0:34ee385f4d2d 304 ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
rajathr 0:34ee385f4d2d 305 ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
rajathr 0:34ee385f4d2d 306 ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
rajathr 0:34ee385f4d2d 307 ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
rajathr 0:34ee385f4d2d 308 ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
rajathr 0:34ee385f4d2d 309 ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
rajathr 0:34ee385f4d2d 310 ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
rajathr 0:34ee385f4d2d 311 /**
rajathr 0:34ee385f4d2d 312 * @}
rajathr 0:34ee385f4d2d 313 */
rajathr 0:34ee385f4d2d 314
rajathr 0:34ee385f4d2d 315 #if defined(STM32F410xx) || defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 316 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
rajathr 0:34ee385f4d2d 317 * @{
rajathr 0:34ee385f4d2d 318 */
rajathr 0:34ee385f4d2d 319 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 320 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
rajathr 0:34ee385f4d2d 321 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
rajathr 0:34ee385f4d2d 322 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
rajathr 0:34ee385f4d2d 323
rajathr 0:34ee385f4d2d 324 #define IS_RCC_LPTIM1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
rajathr 0:34ee385f4d2d 325 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
rajathr 0:34ee385f4d2d 326 /* Legacy Defines */
rajathr 0:34ee385f4d2d 327 #define IS_RCC_LPTIM1_SOURCE IS_RCC_LPTIM1_CLOCKSOURCE
rajathr 0:34ee385f4d2d 328
rajathr 0:34ee385f4d2d 329 #if defined(STM32F410xx)
rajathr 0:34ee385f4d2d 330 /**
rajathr 0:34ee385f4d2d 331 * @}
rajathr 0:34ee385f4d2d 332 */
rajathr 0:34ee385f4d2d 333
rajathr 0:34ee385f4d2d 334 /** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
rajathr 0:34ee385f4d2d 335 * @{
rajathr 0:34ee385f4d2d 336 */
rajathr 0:34ee385f4d2d 337 #define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 338 #define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
rajathr 0:34ee385f4d2d 339 #define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
rajathr 0:34ee385f4d2d 340 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \
rajathr 0:34ee385f4d2d 341 ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
rajathr 0:34ee385f4d2d 342 /**
rajathr 0:34ee385f4d2d 343 * @}
rajathr 0:34ee385f4d2d 344 */
rajathr 0:34ee385f4d2d 345 #endif /* STM32F413_423xx */
rajathr 0:34ee385f4d2d 346 #endif /* STM32F410xx || STM32F413_423xx */
rajathr 0:34ee385f4d2d 347
rajathr 0:34ee385f4d2d 348 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
rajathr 0:34ee385f4d2d 349 /** @defgroup RCC_I2S_Clock_Source
rajathr 0:34ee385f4d2d 350 * @{
rajathr 0:34ee385f4d2d 351 */
rajathr 0:34ee385f4d2d 352 #define RCC_I2SCLKSource_PLLI2S ((uint32_t)0x00)
rajathr 0:34ee385f4d2d 353 #define RCC_I2SCLKSource_Ext ((uint32_t)RCC_DCKCFGR_I2S1SRC_0_MORT)
rajathr 0:34ee385f4d2d 354 #define RCC_I2SCLKSource_PLL ((uint32_t)RCC_DCKCFGR_I2S1SRC_1_MORT)
rajathr 0:34ee385f4d2d 355 #define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0_MORT | RCC_DCKCFGR_I2S1SRC_1_MORT)
rajathr 0:34ee385f4d2d 356
rajathr 0:34ee385f4d2d 357 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \
rajathr 0:34ee385f4d2d 358 ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE))
rajathr 0:34ee385f4d2d 359 /**
rajathr 0:34ee385f4d2d 360 * @}
rajathr 0:34ee385f4d2d 361 */
rajathr 0:34ee385f4d2d 362
rajathr 0:34ee385f4d2d 363 /** @defgroup RCC_I2S_APBBus
rajathr 0:34ee385f4d2d 364 * @{
rajathr 0:34ee385f4d2d 365 */
rajathr 0:34ee385f4d2d 366 #define RCC_I2SBus_APB1 ((uint8_t)0x00)
rajathr 0:34ee385f4d2d 367 #define RCC_I2SBus_APB2 ((uint8_t)0x01)
rajathr 0:34ee385f4d2d 368 #define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2))
rajathr 0:34ee385f4d2d 369 /**
rajathr 0:34ee385f4d2d 370 * @}
rajathr 0:34ee385f4d2d 371 */
rajathr 0:34ee385f4d2d 372 #if defined(STM32F446xx)
rajathr 0:34ee385f4d2d 373 /** @defgroup RCC_SAI_Clock_Source
rajathr 0:34ee385f4d2d 374 * @{
rajathr 0:34ee385f4d2d 375 */
rajathr 0:34ee385f4d2d 376 #define RCC_SAICLKSource_PLLSAI ((uint32_t)0x00)
rajathr 0:34ee385f4d2d 377 #define RCC_SAICLKSource_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0_MORT)
rajathr 0:34ee385f4d2d 378 #define RCC_SAICLKSource_PLL ((uint32_t)RCC_DCKCFGR_SAI1SRC_1_MORT)
rajathr 0:34ee385f4d2d 379 #define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0_MORT | RCC_DCKCFGR_SAI1SRC_1_MORT)
rajathr 0:34ee385f4d2d 380
rajathr 0:34ee385f4d2d 381 #define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \
rajathr 0:34ee385f4d2d 382 ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE))
rajathr 0:34ee385f4d2d 383 /**
rajathr 0:34ee385f4d2d 384 * @}
rajathr 0:34ee385f4d2d 385 */
rajathr 0:34ee385f4d2d 386
rajathr 0:34ee385f4d2d 387 /** @defgroup RCC_SAI_Instance
rajathr 0:34ee385f4d2d 388 * @{
rajathr 0:34ee385f4d2d 389 */
rajathr 0:34ee385f4d2d 390 #define RCC_SAIInstance_SAI1 ((uint8_t)0x00)
rajathr 0:34ee385f4d2d 391 #define RCC_SAIInstance_SAI2 ((uint8_t)0x01)
rajathr 0:34ee385f4d2d 392 #define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2))
rajathr 0:34ee385f4d2d 393 /**
rajathr 0:34ee385f4d2d 394 * @}
rajathr 0:34ee385f4d2d 395 */
rajathr 0:34ee385f4d2d 396 #endif /* STM32F446xx */
rajathr 0:34ee385f4d2d 397 #if defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 398
rajathr 0:34ee385f4d2d 399 /** @defgroup RCC_SAI_BlockA_Clock_Source
rajathr 0:34ee385f4d2d 400 * @{
rajathr 0:34ee385f4d2d 401 */
rajathr 0:34ee385f4d2d 402 #define RCC_SAIACLKSource_PLLI2S_R ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 403 #define RCC_SAIACLKSource_I2SCKIN ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0_MORT)
rajathr 0:34ee385f4d2d 404 #define RCC_SAIACLKSource_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1_MORT)
rajathr 0:34ee385f4d2d 405 #define RCC_SAIACLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0_MORT | RCC_DCKCFGR_SAI1ASRC_1_MORT)
rajathr 0:34ee385f4d2d 406
rajathr 0:34ee385f4d2d 407 #define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S_R) || ((SOURCE) == RCC_SAIACLKSource_I2SCKIN) || \
rajathr 0:34ee385f4d2d 408 ((SOURCE) == RCC_SAIACLKSource_PLLR) || ((SOURCE) == RCC_SAIACLKSource_HSI_HSE))
rajathr 0:34ee385f4d2d 409 /**
rajathr 0:34ee385f4d2d 410 * @}
rajathr 0:34ee385f4d2d 411 */
rajathr 0:34ee385f4d2d 412
rajathr 0:34ee385f4d2d 413 /** @defgroup RCC_SAI_BlockB_Clock_Source
rajathr 0:34ee385f4d2d 414 * @{
rajathr 0:34ee385f4d2d 415 */
rajathr 0:34ee385f4d2d 416 #define RCC_SAIBCLKSource_PLLI2S_R ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 417 #define RCC_SAIBCLKSource_I2SCKIN ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0_MORT)
rajathr 0:34ee385f4d2d 418 #define RCC_SAIBCLKSource_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1_MORT)
rajathr 0:34ee385f4d2d 419 #define RCC_SAIBCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0_MORT | RCC_DCKCFGR_SAI1BSRC_1_MORT)
rajathr 0:34ee385f4d2d 420
rajathr 0:34ee385f4d2d 421 #define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S_R) || ((SOURCE) == RCC_SAIBCLKSource_I2SCKIN) || \
rajathr 0:34ee385f4d2d 422 ((SOURCE) == RCC_SAIBCLKSource_PLLR) || ((SOURCE) == RCC_SAIBCLKSource_HSI_HSE))
rajathr 0:34ee385f4d2d 423 /**
rajathr 0:34ee385f4d2d 424 * @}
rajathr 0:34ee385f4d2d 425 */
rajathr 0:34ee385f4d2d 426 #endif /* STM32F413_423xx */
rajathr 0:34ee385f4d2d 427 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
rajathr 0:34ee385f4d2d 428
rajathr 0:34ee385f4d2d 429 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 430 /** @defgroup RCC_I2S_Clock_Source
rajathr 0:34ee385f4d2d 431 * @{
rajathr 0:34ee385f4d2d 432 */
rajathr 0:34ee385f4d2d 433 #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
rajathr 0:34ee385f4d2d 434 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
rajathr 0:34ee385f4d2d 435
rajathr 0:34ee385f4d2d 436 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
rajathr 0:34ee385f4d2d 437 /**
rajathr 0:34ee385f4d2d 438 * @}
rajathr 0:34ee385f4d2d 439 */
rajathr 0:34ee385f4d2d 440
rajathr 0:34ee385f4d2d 441 /** @defgroup RCC_SAI_BlockA_Clock_Source
rajathr 0:34ee385f4d2d 442 * @{
rajathr 0:34ee385f4d2d 443 */
rajathr 0:34ee385f4d2d 444 #define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 445 #define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)
rajathr 0:34ee385f4d2d 446 #define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)
rajathr 0:34ee385f4d2d 447
rajathr 0:34ee385f4d2d 448 #define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
rajathr 0:34ee385f4d2d 449 ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
rajathr 0:34ee385f4d2d 450 ((SOURCE) == RCC_SAIACLKSource_Ext))
rajathr 0:34ee385f4d2d 451 /**
rajathr 0:34ee385f4d2d 452 * @}
rajathr 0:34ee385f4d2d 453 */
rajathr 0:34ee385f4d2d 454
rajathr 0:34ee385f4d2d 455 /** @defgroup RCC_SAI_BlockB_Clock_Source
rajathr 0:34ee385f4d2d 456 * @{
rajathr 0:34ee385f4d2d 457 */
rajathr 0:34ee385f4d2d 458 #define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 459 #define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)
rajathr 0:34ee385f4d2d 460 #define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)
rajathr 0:34ee385f4d2d 461
rajathr 0:34ee385f4d2d 462 #define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
rajathr 0:34ee385f4d2d 463 ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
rajathr 0:34ee385f4d2d 464 ((SOURCE) == RCC_SAIBCLKSource_Ext))
rajathr 0:34ee385f4d2d 465 /**
rajathr 0:34ee385f4d2d 466 * @}
rajathr 0:34ee385f4d2d 467 */
rajathr 0:34ee385f4d2d 468 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
rajathr 0:34ee385f4d2d 469
rajathr 0:34ee385f4d2d 470 /** @defgroup RCC_TIM_PRescaler_Selection
rajathr 0:34ee385f4d2d 471 * @{
rajathr 0:34ee385f4d2d 472 */
rajathr 0:34ee385f4d2d 473 #define RCC_TIMPrescDesactivated ((uint8_t)0x00)
rajathr 0:34ee385f4d2d 474 #define RCC_TIMPrescActivated ((uint8_t)0x01)
rajathr 0:34ee385f4d2d 475
rajathr 0:34ee385f4d2d 476 #define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
rajathr 0:34ee385f4d2d 477 /**
rajathr 0:34ee385f4d2d 478 * @}
rajathr 0:34ee385f4d2d 479 */
rajathr 0:34ee385f4d2d 480
rajathr 0:34ee385f4d2d 481 #if defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 482 /** @defgroup RCC_DSI_Clock_Source_Selection
rajathr 0:34ee385f4d2d 483 * @{
rajathr 0:34ee385f4d2d 484 */
rajathr 0:34ee385f4d2d 485 #define RCC_DSICLKSource_PHY ((uint8_t)0x00)
rajathr 0:34ee385f4d2d 486 #define RCC_DSICLKSource_PLLR ((uint8_t)0x01)
rajathr 0:34ee385f4d2d 487 #define IS_RCC_DSI_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_DSICLKSource_PHY) || \
rajathr 0:34ee385f4d2d 488 ((CLKSOURCE) == RCC_DSICLKSource_PLLR))
rajathr 0:34ee385f4d2d 489 /**
rajathr 0:34ee385f4d2d 490 * @}
rajathr 0:34ee385f4d2d 491 */
rajathr 0:34ee385f4d2d 492 #endif /* STM32F469_479xx */
rajathr 0:34ee385f4d2d 493
rajathr 0:34ee385f4d2d 494 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 495 /** @defgroup RCC_SDIO_Clock_Source_Selection
rajathr 0:34ee385f4d2d 496 * @{
rajathr 0:34ee385f4d2d 497 */
rajathr 0:34ee385f4d2d 498 #define RCC_SDIOCLKSource_48MHZ ((uint8_t)0x00)
rajathr 0:34ee385f4d2d 499 #define RCC_SDIOCLKSource_SYSCLK ((uint8_t)0x01)
rajathr 0:34ee385f4d2d 500 #define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \
rajathr 0:34ee385f4d2d 501 ((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK))
rajathr 0:34ee385f4d2d 502 /**
rajathr 0:34ee385f4d2d 503 * @}
rajathr 0:34ee385f4d2d 504 */
rajathr 0:34ee385f4d2d 505
rajathr 0:34ee385f4d2d 506
rajathr 0:34ee385f4d2d 507 /** @defgroup RCC_48MHZ_Clock_Source_Selection
rajathr 0:34ee385f4d2d 508 * @{
rajathr 0:34ee385f4d2d 509 */
rajathr 0:34ee385f4d2d 510 #if defined(STM32F446xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 511 #define RCC_48MHZCLKSource_PLL ((uint8_t)0x00)
rajathr 0:34ee385f4d2d 512 #define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01)
rajathr 0:34ee385f4d2d 513 #define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \
rajathr 0:34ee385f4d2d 514 ((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI))
rajathr 0:34ee385f4d2d 515 #endif /* STM32F446xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 516 #if defined(STM32F412xG) || defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 517 #define RCC_CK48CLKSOURCE_PLLQ ((uint8_t)0x00)
rajathr 0:34ee385f4d2d 518 #define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG and STM32F413_423xx Devices */
rajathr 0:34ee385f4d2d 519 #define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \
rajathr 0:34ee385f4d2d 520 ((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ))
rajathr 0:34ee385f4d2d 521 #endif /* STM32F412xG || STM32F413_423xx */
rajathr 0:34ee385f4d2d 522 /**
rajathr 0:34ee385f4d2d 523 * @}
rajathr 0:34ee385f4d2d 524 */
rajathr 0:34ee385f4d2d 525 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 526
rajathr 0:34ee385f4d2d 527 #if defined(STM32F446xx)
rajathr 0:34ee385f4d2d 528 /** @defgroup RCC_SPDIFRX_Clock_Source_Selection
rajathr 0:34ee385f4d2d 529 * @{
rajathr 0:34ee385f4d2d 530 */
rajathr 0:34ee385f4d2d 531 #define RCC_SPDIFRXCLKSource_PLLR ((uint8_t)0x00)
rajathr 0:34ee385f4d2d 532 #define RCC_SPDIFRXCLKSource_PLLI2SP ((uint8_t)0x01)
rajathr 0:34ee385f4d2d 533 #define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \
rajathr 0:34ee385f4d2d 534 ((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP))
rajathr 0:34ee385f4d2d 535 /**
rajathr 0:34ee385f4d2d 536 * @}
rajathr 0:34ee385f4d2d 537 */
rajathr 0:34ee385f4d2d 538
rajathr 0:34ee385f4d2d 539 /** @defgroup RCC_CEC_Clock_Source_Selection
rajathr 0:34ee385f4d2d 540 * @{
rajathr 0:34ee385f4d2d 541 */
rajathr 0:34ee385f4d2d 542 #define RCC_CECCLKSource_HSIDiv488 ((uint8_t)0x00)
rajathr 0:34ee385f4d2d 543 #define RCC_CECCLKSource_LSE ((uint8_t)0x01)
rajathr 0:34ee385f4d2d 544 #define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \
rajathr 0:34ee385f4d2d 545 ((CLKSOURCE) == RCC_CECCLKSource_LSE))
rajathr 0:34ee385f4d2d 546 /**
rajathr 0:34ee385f4d2d 547 * @}
rajathr 0:34ee385f4d2d 548 */
rajathr 0:34ee385f4d2d 549
rajathr 0:34ee385f4d2d 550 /** @defgroup RCC_AHB1_ClockGating
rajathr 0:34ee385f4d2d 551 * @{
rajathr 0:34ee385f4d2d 552 */
rajathr 0:34ee385f4d2d 553 #define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001)
rajathr 0:34ee385f4d2d 554 #define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002)
rajathr 0:34ee385f4d2d 555 #define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004)
rajathr 0:34ee385f4d2d 556 #define RCC_AHB1ClockGating_SPARE ((uint32_t)0x00000008)
rajathr 0:34ee385f4d2d 557 #define RCC_AHB1ClockGating_SRAM ((uint32_t)0x00000010)
rajathr 0:34ee385f4d2d 558 #define RCC_AHB1ClockGating_FLITF ((uint32_t)0x00000020)
rajathr 0:34ee385f4d2d 559 #define RCC_AHB1ClockGating_RCC ((uint32_t)0x00000040)
rajathr 0:34ee385f4d2d 560
rajathr 0:34ee385f4d2d 561 #define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00))
rajathr 0:34ee385f4d2d 562
rajathr 0:34ee385f4d2d 563 /**
rajathr 0:34ee385f4d2d 564 * @}
rajathr 0:34ee385f4d2d 565 */
rajathr 0:34ee385f4d2d 566 #endif /* STM32F446xx */
rajathr 0:34ee385f4d2d 567
rajathr 0:34ee385f4d2d 568 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
rajathr 0:34ee385f4d2d 569 /** @defgroup RCC_FMPI2C1_Clock_Source
rajathr 0:34ee385f4d2d 570 * @{
rajathr 0:34ee385f4d2d 571 */
rajathr 0:34ee385f4d2d 572 #define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00)
rajathr 0:34ee385f4d2d 573 #define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0_MORT)
rajathr 0:34ee385f4d2d 574 #define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1_MORT)
rajathr 0:34ee385f4d2d 575
rajathr 0:34ee385f4d2d 576 #define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \
rajathr 0:34ee385f4d2d 577 ((SOURCE) == RCC_FMPI2C1CLKSource_HSI))
rajathr 0:34ee385f4d2d 578 /**
rajathr 0:34ee385f4d2d 579 * @}
rajathr 0:34ee385f4d2d 580 */
rajathr 0:34ee385f4d2d 581 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
rajathr 0:34ee385f4d2d 582
rajathr 0:34ee385f4d2d 583 #if defined(STM32F412xG) || defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 584 /** @defgroup RCC_DFSDM_Clock_Source
rajathr 0:34ee385f4d2d 585 * @{
rajathr 0:34ee385f4d2d 586 */
rajathr 0:34ee385f4d2d 587 #define RCC_DFSDMCLKSource_APB ((uint8_t)0x00)
rajathr 0:34ee385f4d2d 588 #define RCC_DFSDMCLKSource_SYS ((uint8_t)0x01)
rajathr 0:34ee385f4d2d 589 #define IS_RCC_DFSDMCLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDMCLKSource_APB) || ((SOURCE) == RCC_DFSDMCLKSource_SYS))
rajathr 0:34ee385f4d2d 590
rajathr 0:34ee385f4d2d 591 /* Legacy Defines */
rajathr 0:34ee385f4d2d 592 #define RCC_DFSDM1CLKSource_APB RCC_DFSDMCLKSource_APB
rajathr 0:34ee385f4d2d 593 #define RCC_DFSDM1CLKSource_SYS RCC_DFSDMCLKSource_SYS
rajathr 0:34ee385f4d2d 594 #define IS_RCC_DFSDM1CLK_SOURCE IS_RCC_DFSDMCLK_SOURCE
rajathr 0:34ee385f4d2d 595 /**
rajathr 0:34ee385f4d2d 596 * @}
rajathr 0:34ee385f4d2d 597 */
rajathr 0:34ee385f4d2d 598
rajathr 0:34ee385f4d2d 599 /** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source
rajathr 0:34ee385f4d2d 600 * @{
rajathr 0:34ee385f4d2d 601 */
rajathr 0:34ee385f4d2d 602 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 603 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
rajathr 0:34ee385f4d2d 604 #define IS_RCC_DFSDM1ACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2))
rajathr 0:34ee385f4d2d 605
rajathr 0:34ee385f4d2d 606 /* Legacy Defines */
rajathr 0:34ee385f4d2d 607 #define IS_RCC_DFSDMACLK_SOURCE IS_RCC_DFSDM1ACLK_SOURCE
rajathr 0:34ee385f4d2d 608 /**
rajathr 0:34ee385f4d2d 609 * @}
rajathr 0:34ee385f4d2d 610 */
rajathr 0:34ee385f4d2d 611
rajathr 0:34ee385f4d2d 612 #if defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 613 /** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source
rajathr 0:34ee385f4d2d 614 * @{
rajathr 0:34ee385f4d2d 615 */
rajathr 0:34ee385f4d2d 616 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 617 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
rajathr 0:34ee385f4d2d 618 #define IS_RCC_DFSDM2ACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2))
rajathr 0:34ee385f4d2d 619 /**
rajathr 0:34ee385f4d2d 620 * @}
rajathr 0:34ee385f4d2d 621 */
rajathr 0:34ee385f4d2d 622 #endif /* STM32F413_423xx */
rajathr 0:34ee385f4d2d 623 #endif /* STM32F412xG || STM32F413_423xx */
rajathr 0:34ee385f4d2d 624
rajathr 0:34ee385f4d2d 625 /** @defgroup RCC_AHB1_Peripherals
rajathr 0:34ee385f4d2d 626 * @{
rajathr 0:34ee385f4d2d 627 */
rajathr 0:34ee385f4d2d 628 #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
rajathr 0:34ee385f4d2d 629 #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
rajathr 0:34ee385f4d2d 630 #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
rajathr 0:34ee385f4d2d 631 #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
rajathr 0:34ee385f4d2d 632 #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
rajathr 0:34ee385f4d2d 633 #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
rajathr 0:34ee385f4d2d 634 #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
rajathr 0:34ee385f4d2d 635 #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
rajathr 0:34ee385f4d2d 636 #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
rajathr 0:34ee385f4d2d 637 #define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
rajathr 0:34ee385f4d2d 638 #define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
rajathr 0:34ee385f4d2d 639 #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
rajathr 0:34ee385f4d2d 640 #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
rajathr 0:34ee385f4d2d 641 #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
rajathr 0:34ee385f4d2d 642 #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
rajathr 0:34ee385f4d2d 643 #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
rajathr 0:34ee385f4d2d 644 #define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)
rajathr 0:34ee385f4d2d 645 #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
rajathr 0:34ee385f4d2d 646 #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
rajathr 0:34ee385f4d2d 647 #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
rajathr 0:34ee385f4d2d 648 #define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
rajathr 0:34ee385f4d2d 649 #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
rajathr 0:34ee385f4d2d 650 #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
rajathr 0:34ee385f4d2d 651 #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
rajathr 0:34ee385f4d2d 652 #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
rajathr 0:34ee385f4d2d 653 #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
rajathr 0:34ee385f4d2d 654 #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
rajathr 0:34ee385f4d2d 655 #if defined(STM32F410xx)
rajathr 0:34ee385f4d2d 656 #define RCC_AHB1Periph_RNG ((uint32_t)0x80000000)
rajathr 0:34ee385f4d2d 657 #endif /* STM32F410xx */
rajathr 0:34ee385f4d2d 658 #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00))
rajathr 0:34ee385f4d2d 659 #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00))
rajathr 0:34ee385f4d2d 660 #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00))
rajathr 0:34ee385f4d2d 661
rajathr 0:34ee385f4d2d 662 /**
rajathr 0:34ee385f4d2d 663 * @}
rajathr 0:34ee385f4d2d 664 */
rajathr 0:34ee385f4d2d 665
rajathr 0:34ee385f4d2d 666 /** @defgroup RCC_AHB2_Peripherals
rajathr 0:34ee385f4d2d 667 * @{
rajathr 0:34ee385f4d2d 668 */
rajathr 0:34ee385f4d2d 669 #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
rajathr 0:34ee385f4d2d 670 #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
rajathr 0:34ee385f4d2d 671 #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
rajathr 0:34ee385f4d2d 672 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 673 #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
rajathr 0:34ee385f4d2d 674 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 675 #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
rajathr 0:34ee385f4d2d 676 #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
rajathr 0:34ee385f4d2d 677 /**
rajathr 0:34ee385f4d2d 678 * @}
rajathr 0:34ee385f4d2d 679 */
rajathr 0:34ee385f4d2d 680
rajathr 0:34ee385f4d2d 681 /** @defgroup RCC_AHB3_Peripherals
rajathr 0:34ee385f4d2d 682 * @{
rajathr 0:34ee385f4d2d 683 */
rajathr 0:34ee385f4d2d 684 #if defined(STM32F40_41xxx)
rajathr 0:34ee385f4d2d 685 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
rajathr 0:34ee385f4d2d 686 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
rajathr 0:34ee385f4d2d 687 #endif /* STM32F40_41xxx */
rajathr 0:34ee385f4d2d 688
rajathr 0:34ee385f4d2d 689 #if defined(STM32F427_437xx) || defined(STM32F429_439xx)
rajathr 0:34ee385f4d2d 690 #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
rajathr 0:34ee385f4d2d 691 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
rajathr 0:34ee385f4d2d 692 #endif /* STM32F427_437xx || STM32F429_439xx */
rajathr 0:34ee385f4d2d 693
rajathr 0:34ee385f4d2d 694 #if defined(STM32F446xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 695 #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
rajathr 0:34ee385f4d2d 696 #define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
rajathr 0:34ee385f4d2d 697 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
rajathr 0:34ee385f4d2d 698 #endif /* STM32F446xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 699
rajathr 0:34ee385f4d2d 700 #if defined(STM32F412xG) || defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 701 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
rajathr 0:34ee385f4d2d 702 #define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
rajathr 0:34ee385f4d2d 703 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
rajathr 0:34ee385f4d2d 704 #endif /* STM32F412xG || STM32F413_423xx */
rajathr 0:34ee385f4d2d 705
rajathr 0:34ee385f4d2d 706 /**
rajathr 0:34ee385f4d2d 707 * @}
rajathr 0:34ee385f4d2d 708 */
rajathr 0:34ee385f4d2d 709
rajathr 0:34ee385f4d2d 710 /** @defgroup RCC_APB1_Peripherals
rajathr 0:34ee385f4d2d 711 * @{
rajathr 0:34ee385f4d2d 712 */
rajathr 0:34ee385f4d2d 713 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
rajathr 0:34ee385f4d2d 714 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
rajathr 0:34ee385f4d2d 715 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
rajathr 0:34ee385f4d2d 716 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
rajathr 0:34ee385f4d2d 717 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
rajathr 0:34ee385f4d2d 718 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
rajathr 0:34ee385f4d2d 719 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
rajathr 0:34ee385f4d2d 720 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
rajathr 0:34ee385f4d2d 721 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
rajathr 0:34ee385f4d2d 722 #if defined(STM32F410xx) || defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 723 #define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200)
rajathr 0:34ee385f4d2d 724 #endif /* STM32F410xx || STM32F413_423xx */
rajathr 0:34ee385f4d2d 725 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
rajathr 0:34ee385f4d2d 726 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
rajathr 0:34ee385f4d2d 727 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
rajathr 0:34ee385f4d2d 728 #if defined(STM32F446xx)
rajathr 0:34ee385f4d2d 729 #define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000)
rajathr 0:34ee385f4d2d 730 #endif /* STM32F446xx */
rajathr 0:34ee385f4d2d 731 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
rajathr 0:34ee385f4d2d 732 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
rajathr 0:34ee385f4d2d 733 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
rajathr 0:34ee385f4d2d 734 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
rajathr 0:34ee385f4d2d 735 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
rajathr 0:34ee385f4d2d 736 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
rajathr 0:34ee385f4d2d 737 #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
rajathr 0:34ee385f4d2d 738 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
rajathr 0:34ee385f4d2d 739 #define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000)
rajathr 0:34ee385f4d2d 740 #endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/
rajathr 0:34ee385f4d2d 741 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
rajathr 0:34ee385f4d2d 742 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
rajathr 0:34ee385f4d2d 743 #if defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 744 #define RCC_APB1Periph_CAN3 ((uint32_t)0x08000000)
rajathr 0:34ee385f4d2d 745 #endif /* STM32F413_423xx */
rajathr 0:34ee385f4d2d 746 #if defined(STM32F446xx)
rajathr 0:34ee385f4d2d 747 #define RCC_APB1Periph_CEC ((uint32_t)0x08000000)
rajathr 0:34ee385f4d2d 748 #endif /* STM32F446xx */
rajathr 0:34ee385f4d2d 749 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
rajathr 0:34ee385f4d2d 750 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
rajathr 0:34ee385f4d2d 751 #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
rajathr 0:34ee385f4d2d 752 #define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
rajathr 0:34ee385f4d2d 753 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))
rajathr 0:34ee385f4d2d 754 /**
rajathr 0:34ee385f4d2d 755 * @}
rajathr 0:34ee385f4d2d 756 */
rajathr 0:34ee385f4d2d 757
rajathr 0:34ee385f4d2d 758 /** @defgroup RCC_APB2_Peripherals
rajathr 0:34ee385f4d2d 759 * @{
rajathr 0:34ee385f4d2d 760 */
rajathr 0:34ee385f4d2d 761 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
rajathr 0:34ee385f4d2d 762 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
rajathr 0:34ee385f4d2d 763 #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
rajathr 0:34ee385f4d2d 764 #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
rajathr 0:34ee385f4d2d 765 #define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
rajathr 0:34ee385f4d2d 766 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
rajathr 0:34ee385f4d2d 767 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
rajathr 0:34ee385f4d2d 768 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
rajathr 0:34ee385f4d2d 769 #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
rajathr 0:34ee385f4d2d 770 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
rajathr 0:34ee385f4d2d 771 #define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
rajathr 0:34ee385f4d2d 772 #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
rajathr 0:34ee385f4d2d 773 #define RCC_APB2Periph_EXTIT ((uint32_t)0x00008000)
rajathr 0:34ee385f4d2d 774 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
rajathr 0:34ee385f4d2d 775 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
rajathr 0:34ee385f4d2d 776 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
rajathr 0:34ee385f4d2d 777 #define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
rajathr 0:34ee385f4d2d 778 #define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
rajathr 0:34ee385f4d2d 779 #define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)
rajathr 0:34ee385f4d2d 780 #if defined(STM32F446xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 781 #define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000)
rajathr 0:34ee385f4d2d 782 #endif /* STM32F446xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 783 #define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
rajathr 0:34ee385f4d2d 784 #if defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 785 #define RCC_APB2Periph_DSI ((uint32_t)0x08000000)
rajathr 0:34ee385f4d2d 786 #endif /* STM32F469_479xx */
rajathr 0:34ee385f4d2d 787 #if defined(STM32F412xG) || defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 788 #define RCC_APB2Periph_DFSDM1 ((uint32_t)0x01000000)
rajathr 0:34ee385f4d2d 789 #endif /* STM32F412xG || STM32F413_423xx */
rajathr 0:34ee385f4d2d 790 #if defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 791 #define RCC_APB2Periph_DFSDM2 ((uint32_t)0x02000000)
rajathr 0:34ee385f4d2d 792 #define RCC_APB2Periph_UART9 ((uint32_t)0x02000040)
rajathr 0:34ee385f4d2d 793 #define RCC_APB2Periph_UART10 ((uint32_t)0x00000080)
rajathr 0:34ee385f4d2d 794 #endif /* STM32F413_423xx */
rajathr 0:34ee385f4d2d 795
rajathr 0:34ee385f4d2d 796 /* Legacy Defines */
rajathr 0:34ee385f4d2d 797 #define RCC_APB2Periph_DFSDM RCC_APB2Periph_DFSDM1
rajathr 0:34ee385f4d2d 798
rajathr 0:34ee385f4d2d 799 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF008000C) == 0x00) && ((PERIPH) != 0x00))
rajathr 0:34ee385f4d2d 800 #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF208860C) == 0x00) && ((PERIPH) != 0x00))
rajathr 0:34ee385f4d2d 801
rajathr 0:34ee385f4d2d 802 /**
rajathr 0:34ee385f4d2d 803 * @}
rajathr 0:34ee385f4d2d 804 */
rajathr 0:34ee385f4d2d 805
rajathr 0:34ee385f4d2d 806 /** @defgroup RCC_MCO1_Clock_Source_Prescaler
rajathr 0:34ee385f4d2d 807 * @{
rajathr 0:34ee385f4d2d 808 */
rajathr 0:34ee385f4d2d 809 #define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 810 #define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
rajathr 0:34ee385f4d2d 811 #define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
rajathr 0:34ee385f4d2d 812 #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
rajathr 0:34ee385f4d2d 813 #define RCC_MCO1Div_1 ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 814 #define RCC_MCO1Div_2 ((uint32_t)0x04000000)
rajathr 0:34ee385f4d2d 815 #define RCC_MCO1Div_3 ((uint32_t)0x05000000)
rajathr 0:34ee385f4d2d 816 #define RCC_MCO1Div_4 ((uint32_t)0x06000000)
rajathr 0:34ee385f4d2d 817 #define RCC_MCO1Div_5 ((uint32_t)0x07000000)
rajathr 0:34ee385f4d2d 818 #define IS_RCC_MCO1SOURCE_MORT(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
rajathr 0:34ee385f4d2d 819 ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
rajathr 0:34ee385f4d2d 820
rajathr 0:34ee385f4d2d 821 #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
rajathr 0:34ee385f4d2d 822 ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
rajathr 0:34ee385f4d2d 823 ((DIV) == RCC_MCO1Div_5))
rajathr 0:34ee385f4d2d 824 /**
rajathr 0:34ee385f4d2d 825 * @}
rajathr 0:34ee385f4d2d 826 */
rajathr 0:34ee385f4d2d 827
rajathr 0:34ee385f4d2d 828 /** @defgroup RCC_MCO2_Clock_Source_Prescaler
rajathr 0:34ee385f4d2d 829 * @{
rajathr 0:34ee385f4d2d 830 */
rajathr 0:34ee385f4d2d 831 #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 832 #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
rajathr 0:34ee385f4d2d 833 #define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
rajathr 0:34ee385f4d2d 834 #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
rajathr 0:34ee385f4d2d 835 #define RCC_MCO2Div_1 ((uint32_t)0x00000000)
rajathr 0:34ee385f4d2d 836 #define RCC_MCO2Div_2 ((uint32_t)0x20000000)
rajathr 0:34ee385f4d2d 837 #define RCC_MCO2Div_3 ((uint32_t)0x28000000)
rajathr 0:34ee385f4d2d 838 #define RCC_MCO2Div_4 ((uint32_t)0x30000000)
rajathr 0:34ee385f4d2d 839 #define RCC_MCO2Div_5 ((uint32_t)0x38000000)
rajathr 0:34ee385f4d2d 840 #define IS_RCC_MCO2SOURCE_MORT(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
rajathr 0:34ee385f4d2d 841 ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
rajathr 0:34ee385f4d2d 842
rajathr 0:34ee385f4d2d 843 #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
rajathr 0:34ee385f4d2d 844 ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
rajathr 0:34ee385f4d2d 845 ((DIV) == RCC_MCO2Div_5))
rajathr 0:34ee385f4d2d 846 /**
rajathr 0:34ee385f4d2d 847 * @}
rajathr 0:34ee385f4d2d 848 */
rajathr 0:34ee385f4d2d 849
rajathr 0:34ee385f4d2d 850 /** @defgroup RCC_Flag
rajathr 0:34ee385f4d2d 851 * @{
rajathr 0:34ee385f4d2d 852 */
rajathr 0:34ee385f4d2d 853 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
rajathr 0:34ee385f4d2d 854 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
rajathr 0:34ee385f4d2d 855 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
rajathr 0:34ee385f4d2d 856 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
rajathr 0:34ee385f4d2d 857 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)
rajathr 0:34ee385f4d2d 858 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
rajathr 0:34ee385f4d2d 859 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
rajathr 0:34ee385f4d2d 860 #define RCC_FLAG_BORRST ((uint8_t)0x79)
rajathr 0:34ee385f4d2d 861 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
rajathr 0:34ee385f4d2d 862 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
rajathr 0:34ee385f4d2d 863 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
rajathr 0:34ee385f4d2d 864 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
rajathr 0:34ee385f4d2d 865 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
rajathr 0:34ee385f4d2d 866 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
rajathr 0:34ee385f4d2d 867
rajathr 0:34ee385f4d2d 868 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
rajathr 0:34ee385f4d2d 869 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
rajathr 0:34ee385f4d2d 870 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
rajathr 0:34ee385f4d2d 871 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
rajathr 0:34ee385f4d2d 872 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
rajathr 0:34ee385f4d2d 873 ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
rajathr 0:34ee385f4d2d 874 ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
rajathr 0:34ee385f4d2d 875
rajathr 0:34ee385f4d2d 876 #define IS_RCC_CALIBRATION_VALUE_MORT(VALUE) ((VALUE) <= 0x1F)
rajathr 0:34ee385f4d2d 877 /**
rajathr 0:34ee385f4d2d 878 * @}
rajathr 0:34ee385f4d2d 879 */
rajathr 0:34ee385f4d2d 880
rajathr 0:34ee385f4d2d 881 /**
rajathr 0:34ee385f4d2d 882 * @}
rajathr 0:34ee385f4d2d 883 */
rajathr 0:34ee385f4d2d 884
rajathr 0:34ee385f4d2d 885 /* Exported macro ------------------------------------------------------------*/
rajathr 0:34ee385f4d2d 886 /* Exported functions --------------------------------------------------------*/
rajathr 0:34ee385f4d2d 887
rajathr 0:34ee385f4d2d 888 /* Function used to set the RCC clock configuration to the default reset state */
rajathr 0:34ee385f4d2d 889 void RCC_DeInit(void);
rajathr 0:34ee385f4d2d 890
rajathr 0:34ee385f4d2d 891 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
rajathr 0:34ee385f4d2d 892 void RCC_HSEConfig(uint8_t RCC_HSE);
rajathr 0:34ee385f4d2d 893 ErrorStatus RCC_WaitForHSEStartUp(void);
rajathr 0:34ee385f4d2d 894 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
rajathr 0:34ee385f4d2d 895 void RCC_HSICmd(FunctionalState NewState);
rajathr 0:34ee385f4d2d 896 void RCC_LSEConfig(uint8_t RCC_LSE);
rajathr 0:34ee385f4d2d 897 void RCC_LSICmd(FunctionalState NewState);
rajathr 0:34ee385f4d2d 898
rajathr 0:34ee385f4d2d 899 void RCC_PLLCmd(FunctionalState NewState);
rajathr 0:34ee385f4d2d 900
rajathr 0:34ee385f4d2d 901 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 902 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR);
rajathr 0:34ee385f4d2d 903 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 904
rajathr 0:34ee385f4d2d 905 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
rajathr 0:34ee385f4d2d 906 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
rajathr 0:34ee385f4d2d 907 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
rajathr 0:34ee385f4d2d 908
rajathr 0:34ee385f4d2d 909 void RCC_PLLI2SCmd(FunctionalState NewState);
rajathr 0:34ee385f4d2d 910
rajathr 0:34ee385f4d2d 911 #if defined(STM32F40_41xxx) || defined(STM32F401xx)
rajathr 0:34ee385f4d2d 912 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
rajathr 0:34ee385f4d2d 913 #endif /* STM32F40_41xxx || STM32F401xx */
rajathr 0:34ee385f4d2d 914 #if defined(STM32F411xE)
rajathr 0:34ee385f4d2d 915 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
rajathr 0:34ee385f4d2d 916 #endif /* STM32F411xE */
rajathr 0:34ee385f4d2d 917 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 918 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
rajathr 0:34ee385f4d2d 919 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 920 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
rajathr 0:34ee385f4d2d 921 void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR);
rajathr 0:34ee385f4d2d 922 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
rajathr 0:34ee385f4d2d 923
rajathr 0:34ee385f4d2d 924 void RCC_PLLSAICmd(FunctionalState NewState);
rajathr 0:34ee385f4d2d 925 #if defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 926 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR);
rajathr 0:34ee385f4d2d 927 #endif /* STM32F469_479xx */
rajathr 0:34ee385f4d2d 928 #if defined(STM32F446xx)
rajathr 0:34ee385f4d2d 929 void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ);
rajathr 0:34ee385f4d2d 930 #endif /* STM32F446xx */
rajathr 0:34ee385f4d2d 931 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
rajathr 0:34ee385f4d2d 932 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
rajathr 0:34ee385f4d2d 933 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
rajathr 0:34ee385f4d2d 934
rajathr 0:34ee385f4d2d 935 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
rajathr 0:34ee385f4d2d 936 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
rajathr 0:34ee385f4d2d 937 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
rajathr 0:34ee385f4d2d 938
rajathr 0:34ee385f4d2d 939 /* System, AHB and APB busses clocks configuration functions ******************/
rajathr 0:34ee385f4d2d 940 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
rajathr 0:34ee385f4d2d 941 uint8_t RCC_GetSYSCLKSource(void);
rajathr 0:34ee385f4d2d 942 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
rajathr 0:34ee385f4d2d 943 void RCC_PCLK1Config(uint32_t RCC_HCLK);
rajathr 0:34ee385f4d2d 944 void RCC_PCLK2Config(uint32_t RCC_HCLK);
rajathr 0:34ee385f4d2d 945 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
rajathr 0:34ee385f4d2d 946
rajathr 0:34ee385f4d2d 947 /* Peripheral clocks configuration functions **********************************/
rajathr 0:34ee385f4d2d 948 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
rajathr 0:34ee385f4d2d 949 void RCC_RTCCLKCmd(FunctionalState NewState);
rajathr 0:34ee385f4d2d 950 void RCC_BackupResetCmd(FunctionalState NewState);
rajathr 0:34ee385f4d2d 951
rajathr 0:34ee385f4d2d 952 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
rajathr 0:34ee385f4d2d 953 void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource);
rajathr 0:34ee385f4d2d 954 #if defined(STM32F446xx)
rajathr 0:34ee385f4d2d 955 void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource);
rajathr 0:34ee385f4d2d 956 #endif /* STM32F446xx */
rajathr 0:34ee385f4d2d 957 #if defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 958 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
rajathr 0:34ee385f4d2d 959 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
rajathr 0:34ee385f4d2d 960 #endif /* STM32F413_423xx */
rajathr 0:34ee385f4d2d 961 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
rajathr 0:34ee385f4d2d 962
rajathr 0:34ee385f4d2d 963 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 964 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
rajathr 0:34ee385f4d2d 965 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
rajathr 0:34ee385f4d2d 966
rajathr 0:34ee385f4d2d 967 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 968 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
rajathr 0:34ee385f4d2d 969 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
rajathr 0:34ee385f4d2d 970 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 971
rajathr 0:34ee385f4d2d 972 void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
rajathr 0:34ee385f4d2d 973 void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
rajathr 0:34ee385f4d2d 974
rajathr 0:34ee385f4d2d 975 #if defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 976 void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR);
rajathr 0:34ee385f4d2d 977 void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR);
rajathr 0:34ee385f4d2d 978 #endif /* STM32F413_423xx */
rajathr 0:34ee385f4d2d 979
rajathr 0:34ee385f4d2d 980 void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
rajathr 0:34ee385f4d2d 981 void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
rajathr 0:34ee385f4d2d 982
rajathr 0:34ee385f4d2d 983 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
rajathr 0:34ee385f4d2d 984 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
rajathr 0:34ee385f4d2d 985 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
rajathr 0:34ee385f4d2d 986 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
rajathr 0:34ee385f4d2d 987 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
rajathr 0:34ee385f4d2d 988
rajathr 0:34ee385f4d2d 989 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
rajathr 0:34ee385f4d2d 990 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
rajathr 0:34ee385f4d2d 991 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
rajathr 0:34ee385f4d2d 992 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
rajathr 0:34ee385f4d2d 993 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
rajathr 0:34ee385f4d2d 994
rajathr 0:34ee385f4d2d 995 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
rajathr 0:34ee385f4d2d 996 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
rajathr 0:34ee385f4d2d 997 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
rajathr 0:34ee385f4d2d 998 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
rajathr 0:34ee385f4d2d 999 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
rajathr 0:34ee385f4d2d 1000
rajathr 0:34ee385f4d2d 1001 /* Features available only for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices */
rajathr 0:34ee385f4d2d 1002 void RCC_LSEModeConfig(uint8_t RCC_Mode);
rajathr 0:34ee385f4d2d 1003
rajathr 0:34ee385f4d2d 1004 /* Features available only for STM32F469_479xx devices */
rajathr 0:34ee385f4d2d 1005 #if defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 1006 void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource);
rajathr 0:34ee385f4d2d 1007 #endif /* STM32F469_479xx */
rajathr 0:34ee385f4d2d 1008
rajathr 0:34ee385f4d2d 1009 /* Features available only for STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices */
rajathr 0:34ee385f4d2d 1010 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 1011 void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource);
rajathr 0:34ee385f4d2d 1012 void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource);
rajathr 0:34ee385f4d2d 1013 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 1014
rajathr 0:34ee385f4d2d 1015 /* Features available only for STM32F446xx devices */
rajathr 0:34ee385f4d2d 1016 #if defined(STM32F446xx)
rajathr 0:34ee385f4d2d 1017 void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState);
rajathr 0:34ee385f4d2d 1018 void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource);
rajathr 0:34ee385f4d2d 1019 void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource);
rajathr 0:34ee385f4d2d 1020 #endif /* STM32F446xx */
rajathr 0:34ee385f4d2d 1021
rajathr 0:34ee385f4d2d 1022 /* Features available only for STM32F410xx/STM32F412xG/STM32F446xx devices */
rajathr 0:34ee385f4d2d 1023 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
rajathr 0:34ee385f4d2d 1024 void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource);
rajathr 0:34ee385f4d2d 1025 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
rajathr 0:34ee385f4d2d 1026
rajathr 0:34ee385f4d2d 1027 /* Features available only for STM32F410xx devices */
rajathr 0:34ee385f4d2d 1028 #if defined(STM32F410xx) || defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 1029 void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource);
rajathr 0:34ee385f4d2d 1030 #if defined(STM32F410xx)
rajathr 0:34ee385f4d2d 1031 void RCC_MCO1Cmd(FunctionalState NewState);
rajathr 0:34ee385f4d2d 1032 void RCC_MCO2Cmd(FunctionalState NewState);
rajathr 0:34ee385f4d2d 1033 #endif /* STM32F410xx */
rajathr 0:34ee385f4d2d 1034 #endif /* STM32F410xx || STM32F413_423xx */
rajathr 0:34ee385f4d2d 1035
rajathr 0:34ee385f4d2d 1036 #if defined(STM32F412xG) || defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 1037 void RCC_DFSDMCLKConfig(uint32_t RCC_DFSDMCLKSource);
rajathr 0:34ee385f4d2d 1038 void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource);
rajathr 0:34ee385f4d2d 1039 #if defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 1040 void RCC_DFSDM2ACLKConfig(uint32_t RCC_DFSDMACLKSource);
rajathr 0:34ee385f4d2d 1041 #endif /* STM32F413_423xx */
rajathr 0:34ee385f4d2d 1042 /* Legacy Defines */
rajathr 0:34ee385f4d2d 1043 #define RCC_DFSDM1CLKConfig RCC_DFSDMCLKConfig
rajathr 0:34ee385f4d2d 1044 #endif /* STM32F412xG || STM32F413_423xx */
rajathr 0:34ee385f4d2d 1045 /* Interrupts and flags management functions **********************************/
rajathr 0:34ee385f4d2d 1046 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
rajathr 0:34ee385f4d2d 1047 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
rajathr 0:34ee385f4d2d 1048 void RCC_ClearFlag(void);
rajathr 0:34ee385f4d2d 1049 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
rajathr 0:34ee385f4d2d 1050 void RCC_ClearITPendingBit(uint8_t RCC_IT);
rajathr 0:34ee385f4d2d 1051
rajathr 0:34ee385f4d2d 1052 #ifdef __cplusplus
rajathr 0:34ee385f4d2d 1053 }
rajathr 0:34ee385f4d2d 1054 #endif
rajathr 0:34ee385f4d2d 1055
rajathr 0:34ee385f4d2d 1056 #endif /* __STM32F4xx_RCC_H */
rajathr 0:34ee385f4d2d 1057
rajathr 0:34ee385f4d2d 1058 /**
rajathr 0:34ee385f4d2d 1059 * @}
rajathr 0:34ee385f4d2d 1060 */
rajathr 0:34ee385f4d2d 1061
rajathr 0:34ee385f4d2d 1062 /**
rajathr 0:34ee385f4d2d 1063 * @}
rajathr 0:34ee385f4d2d 1064 */
rajathr 0:34ee385f4d2d 1065
rajathr 0:34ee385f4d2d 1066 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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