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Dependencies:   mbed

stm32f4xx_adc_mort.c@0:34ee385f4d2d, 2021-10-23 (annotated)

Committer:
rajathr
Date:
Sat Oct 23 05:49:09 2021 +0000
Revision:
0:34ee385f4d2d
At 23rd Oct 21 - All Code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rajathr 0:34ee385f4d2d 1 /**
rajathr 0:34ee385f4d2d 2 ******************************************************************************
rajathr 0:34ee385f4d2d 3 * @file stm32f4xx_adc_mort.c
rajathr 0:34ee385f4d2d 4 * @author MCD Application Team (with some modifications by melisao@stanford.edu)
rajathr 0:34ee385f4d2d 5 * @version V1.8.0
rajathr 0:34ee385f4d2d 6 * @date 04-November-2016
rajathr 0:34ee385f4d2d 7 * @brief This file provides firmware functions to manage the following
rajathr 0:34ee385f4d2d 8 * functionalities of the Analog to Digital Convertor (ADC) peripheral:
rajathr 0:34ee385f4d2d 9 * + Initialization and Configuration (in addition to ADC multi mode
rajathr 0:34ee385f4d2d 10 * selection)
rajathr 0:34ee385f4d2d 11 * + Analog Watchdog configuration
rajathr 0:34ee385f4d2d 12 * + Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT
rajathr 0:34ee385f4d2d 13 * management
rajathr 0:34ee385f4d2d 14 * + Regular Channels Configuration
rajathr 0:34ee385f4d2d 15 * + Regular Channels DMA Configuration
rajathr 0:34ee385f4d2d 16 * + Injected channels Configuration
rajathr 0:34ee385f4d2d 17 * + Interrupts and flags management
rajathr 0:34ee385f4d2d 18 *
rajathr 0:34ee385f4d2d 19 @verbatim
rajathr 0:34ee385f4d2d 20 ===============================================================================
rajathr 0:34ee385f4d2d 21 ##### How to use this driver #####
rajathr 0:34ee385f4d2d 22 ===============================================================================
rajathr 0:34ee385f4d2d 23 [..]
rajathr 0:34ee385f4d2d 24 (#) Enable the ADC interface clock using
rajathr 0:34ee385f4d2d 25 RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE);
rajathr 0:34ee385f4d2d 26
rajathr 0:34ee385f4d2d 27 (#) ADC pins configuration
rajathr 0:34ee385f4d2d 28 (++) Enable the clock for the ADC GPIOs using the following function:
rajathr 0:34ee385f4d2d 29 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
rajathr 0:34ee385f4d2d 30 (++) Configure these ADC pins in analog mode using GPIO_Init();
rajathr 0:34ee385f4d2d 31
rajathr 0:34ee385f4d2d 32 (#) Configure the ADC Prescaler, conversion resolution and data
rajathr 0:34ee385f4d2d 33 alignment using the ADC_Init() function.
rajathr 0:34ee385f4d2d 34 (#) Activate the ADC peripheral using ADC_Cmd() function.
rajathr 0:34ee385f4d2d 35
rajathr 0:34ee385f4d2d 36 *** Regular channels group configuration ***
rajathr 0:34ee385f4d2d 37 ============================================
rajathr 0:34ee385f4d2d 38 [..]
rajathr 0:34ee385f4d2d 39 (+) To configure the ADC regular channels group features, use
rajathr 0:34ee385f4d2d 40 ADC_Init() and ADC_RegularChannelConfig() functions.
rajathr 0:34ee385f4d2d 41 (+) To activate the continuous mode, use the ADC_continuousModeCmd()
rajathr 0:34ee385f4d2d 42 function.
rajathr 0:34ee385f4d2d 43 (+) To configurate and activate the Discontinuous mode, use the
rajathr 0:34ee385f4d2d 44 ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
rajathr 0:34ee385f4d2d 45 (+) To read the ADC converted values, use the ADC_GetConversionValue()
rajathr 0:34ee385f4d2d 46 function.
rajathr 0:34ee385f4d2d 47
rajathr 0:34ee385f4d2d 48 *** Multi mode ADCs Regular channels configuration ***
rajathr 0:34ee385f4d2d 49 ======================================================
rajathr 0:34ee385f4d2d 50 [..]
rajathr 0:34ee385f4d2d 51 (+) Refer to "Regular channels group configuration" description to
rajathr 0:34ee385f4d2d 52 configure the ADC1, ADC2 and ADC3 regular channels.
rajathr 0:34ee385f4d2d 53 (+) Select the Multi mode ADC regular channels features (dual or
rajathr 0:34ee385f4d2d 54 triple mode) using ADC_CommonInit() function and configure
rajathr 0:34ee385f4d2d 55 the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd()
rajathr 0:34ee385f4d2d 56 functions.
rajathr 0:34ee385f4d2d 57 (+) Read the ADCs converted values using the
rajathr 0:34ee385f4d2d 58 ADC_GetMultiModeConversionValue() function.
rajathr 0:34ee385f4d2d 59
rajathr 0:34ee385f4d2d 60 *** DMA for Regular channels group features configuration ***
rajathr 0:34ee385f4d2d 61 =============================================================
rajathr 0:34ee385f4d2d 62 [..]
rajathr 0:34ee385f4d2d 63 (+) To enable the DMA mode for regular channels group, use the
rajathr 0:34ee385f4d2d 64 ADC_DMACmd() function.
rajathr 0:34ee385f4d2d 65 (+) To enable the generation of DMA requests continuously at the end
rajathr 0:34ee385f4d2d 66 of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd()
rajathr 0:34ee385f4d2d 67 function.
rajathr 0:34ee385f4d2d 68
rajathr 0:34ee385f4d2d 69 *** Injected channels group configuration ***
rajathr 0:34ee385f4d2d 70 =============================================
rajathr 0:34ee385f4d2d 71 [..]
rajathr 0:34ee385f4d2d 72 (+) To configure the ADC Injected channels group features, use
rajathr 0:34ee385f4d2d 73 ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()
rajathr 0:34ee385f4d2d 74 functions.
rajathr 0:34ee385f4d2d 75 (+) To activate the continuous mode, use the ADC_continuousModeCmd()
rajathr 0:34ee385f4d2d 76 function.
rajathr 0:34ee385f4d2d 77 (+) To activate the Injected Discontinuous mode, use the
rajathr 0:34ee385f4d2d 78 ADC_InjectedDiscModeCmd() function.
rajathr 0:34ee385f4d2d 79 (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd()
rajathr 0:34ee385f4d2d 80 function.
rajathr 0:34ee385f4d2d 81 (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue()
rajathr 0:34ee385f4d2d 82 function.
rajathr 0:34ee385f4d2d 83
rajathr 0:34ee385f4d2d 84 @endverbatim
rajathr 0:34ee385f4d2d 85 ******************************************************************************
rajathr 0:34ee385f4d2d 86 * @attention
rajathr 0:34ee385f4d2d 87 *
rajathr 0:34ee385f4d2d 88 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
rajathr 0:34ee385f4d2d 89 *
rajathr 0:34ee385f4d2d 90 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
rajathr 0:34ee385f4d2d 91 * You may not use this file except in compliance with the License.
rajathr 0:34ee385f4d2d 92 * You may obtain a copy of the License at:
rajathr 0:34ee385f4d2d 93 *
rajathr 0:34ee385f4d2d 94 * http://www.st.com/software_license_agreement_liberty_v2
rajathr 0:34ee385f4d2d 95 *
rajathr 0:34ee385f4d2d 96 * Unless required by applicable law or agreed to in writing, software
rajathr 0:34ee385f4d2d 97 * distributed under the License is distributed on an "AS IS" BASIS,
rajathr 0:34ee385f4d2d 98 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
rajathr 0:34ee385f4d2d 99 * See the License for the specific language governing permissions and
rajathr 0:34ee385f4d2d 100 * limitations under the License.
rajathr 0:34ee385f4d2d 101 *
rajathr 0:34ee385f4d2d 102 ******************************************************************************
rajathr 0:34ee385f4d2d 103 */
rajathr 0:34ee385f4d2d 104
rajathr 0:34ee385f4d2d 105 /* Includes ------------------------------------------------------------------*/
rajathr 0:34ee385f4d2d 106 #include "stm32f4xx_adc_mort.h"
rajathr 0:34ee385f4d2d 107 #include "stm32f4xx_rcc_mort.h"
rajathr 0:34ee385f4d2d 108
rajathr 0:34ee385f4d2d 109 /** @addtogroup STM32F4xx_StdPeriph_Driver
rajathr 0:34ee385f4d2d 110 * @{
rajathr 0:34ee385f4d2d 111 */
rajathr 0:34ee385f4d2d 112
rajathr 0:34ee385f4d2d 113 /** @defgroup ADC
rajathr 0:34ee385f4d2d 114 * @brief ADC driver modules
rajathr 0:34ee385f4d2d 115 * @{
rajathr 0:34ee385f4d2d 116 */
rajathr 0:34ee385f4d2d 117
rajathr 0:34ee385f4d2d 118 /* Private typedef -----------------------------------------------------------*/
rajathr 0:34ee385f4d2d 119 /* Private define ------------------------------------------------------------*/
rajathr 0:34ee385f4d2d 120
rajathr 0:34ee385f4d2d 121 /* ADC DISCNUM mask */
rajathr 0:34ee385f4d2d 122 #define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)
rajathr 0:34ee385f4d2d 123
rajathr 0:34ee385f4d2d 124 /* ADC AWDCH mask */
rajathr 0:34ee385f4d2d 125 #define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)
rajathr 0:34ee385f4d2d 126
rajathr 0:34ee385f4d2d 127 /* ADC Analog watchdog enable mode mask */
rajathr 0:34ee385f4d2d 128 #define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF)
rajathr 0:34ee385f4d2d 129
rajathr 0:34ee385f4d2d 130 /* CR1 register Mask */
rajathr 0:34ee385f4d2d 131 #define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF)
rajathr 0:34ee385f4d2d 132
rajathr 0:34ee385f4d2d 133 /* ADC EXTEN mask */
rajathr 0:34ee385f4d2d 134 #define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF)
rajathr 0:34ee385f4d2d 135
rajathr 0:34ee385f4d2d 136 /* ADC JEXTEN mask */
rajathr 0:34ee385f4d2d 137 #define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)
rajathr 0:34ee385f4d2d 138
rajathr 0:34ee385f4d2d 139 /* ADC JEXTSEL mask */
rajathr 0:34ee385f4d2d 140 #define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)
rajathr 0:34ee385f4d2d 141
rajathr 0:34ee385f4d2d 142 /* CR2 register Mask */
rajathr 0:34ee385f4d2d 143 #define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)
rajathr 0:34ee385f4d2d 144
rajathr 0:34ee385f4d2d 145 /* ADC SQx mask */
rajathr 0:34ee385f4d2d 146 #define SQR3_SQ_SET ((uint32_t)0x0000001F)
rajathr 0:34ee385f4d2d 147 #define SQR2_SQ_SET ((uint32_t)0x0000001F)
rajathr 0:34ee385f4d2d 148 #define SQR1_SQ_SET ((uint32_t)0x0000001F)
rajathr 0:34ee385f4d2d 149
rajathr 0:34ee385f4d2d 150 /* ADC L Mask */
rajathr 0:34ee385f4d2d 151 #define SQR1_L_RESET ((uint32_t)0xFF0FFFFF)
rajathr 0:34ee385f4d2d 152
rajathr 0:34ee385f4d2d 153 /* ADC JSQx mask */
rajathr 0:34ee385f4d2d 154 #define JSQR_JSQ_SET ((uint32_t)0x0000001F)
rajathr 0:34ee385f4d2d 155
rajathr 0:34ee385f4d2d 156 /* ADC JL mask */
rajathr 0:34ee385f4d2d 157 #define JSQR_JL_SET ((uint32_t)0x00300000)
rajathr 0:34ee385f4d2d 158 #define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)
rajathr 0:34ee385f4d2d 159
rajathr 0:34ee385f4d2d 160 /* ADC SMPx mask */
rajathr 0:34ee385f4d2d 161 #define SMPR1_SMP_SET ((uint32_t)0x00000007)
rajathr 0:34ee385f4d2d 162 #define SMPR2_SMP_SET ((uint32_t)0x00000007)
rajathr 0:34ee385f4d2d 163
rajathr 0:34ee385f4d2d 164 /* ADC JDRx registers offset */
rajathr 0:34ee385f4d2d 165 #define JDR_OFFSET ((uint8_t)0x28)
rajathr 0:34ee385f4d2d 166
rajathr 0:34ee385f4d2d 167 /* ADC CDR register base address */
rajathr 0:34ee385f4d2d 168 #define CDR_ADDRESS ((uint32_t)0x40012308)
rajathr 0:34ee385f4d2d 169
rajathr 0:34ee385f4d2d 170 /* ADC CCR register Mask */
rajathr 0:34ee385f4d2d 171 #define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0)
rajathr 0:34ee385f4d2d 172
rajathr 0:34ee385f4d2d 173 /* Private macro -------------------------------------------------------------*/
rajathr 0:34ee385f4d2d 174 /* Private variables ---------------------------------------------------------*/
rajathr 0:34ee385f4d2d 175 /* Private function prototypes -----------------------------------------------*/
rajathr 0:34ee385f4d2d 176 /* Private functions ---------------------------------------------------------*/
rajathr 0:34ee385f4d2d 177
rajathr 0:34ee385f4d2d 178 /** @defgroup ADC_Private_Functions
rajathr 0:34ee385f4d2d 179 * @{
rajathr 0:34ee385f4d2d 180 */
rajathr 0:34ee385f4d2d 181
rajathr 0:34ee385f4d2d 182 /** @defgroup ADC_Group1 Initialization and Configuration functions
rajathr 0:34ee385f4d2d 183 * @brief Initialization and Configuration functions
rajathr 0:34ee385f4d2d 184 *
rajathr 0:34ee385f4d2d 185 @verbatim
rajathr 0:34ee385f4d2d 186 ===============================================================================
rajathr 0:34ee385f4d2d 187 ##### Initialization and Configuration functions #####
rajathr 0:34ee385f4d2d 188 ===============================================================================
rajathr 0:34ee385f4d2d 189 [..] This section provides functions allowing to:
rajathr 0:34ee385f4d2d 190 (+) Initialize and configure the ADC Prescaler
rajathr 0:34ee385f4d2d 191 (+) ADC Conversion Resolution (12bit..6bit)
rajathr 0:34ee385f4d2d 192 (+) Scan Conversion Mode (multichannel or one channel) for regular group
rajathr 0:34ee385f4d2d 193 (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for
rajathr 0:34ee385f4d2d 194 regular group
rajathr 0:34ee385f4d2d 195 (+) External trigger Edge and source of regular group,
rajathr 0:34ee385f4d2d 196 (+) Converted data alignment (left or right)
rajathr 0:34ee385f4d2d 197 (+) The number of ADC conversions that will be done using the sequencer for
rajathr 0:34ee385f4d2d 198 regular channel group
rajathr 0:34ee385f4d2d 199 (+) Multi ADC mode selection
rajathr 0:34ee385f4d2d 200 (+) Direct memory access mode selection for multi ADC mode
rajathr 0:34ee385f4d2d 201 (+) Delay between 2 sampling phases (used in dual or triple interleaved modes)
rajathr 0:34ee385f4d2d 202 (+) Enable or disable the ADC peripheral
rajathr 0:34ee385f4d2d 203 @endverbatim
rajathr 0:34ee385f4d2d 204 * @{
rajathr 0:34ee385f4d2d 205 */
rajathr 0:34ee385f4d2d 206
rajathr 0:34ee385f4d2d 207 /**
rajathr 0:34ee385f4d2d 208 * @brief Deinitializes all ADCs peripherals registers to their default reset
rajathr 0:34ee385f4d2d 209 * values.
rajathr 0:34ee385f4d2d 210 * @param None
rajathr 0:34ee385f4d2d 211 * @retval None
rajathr 0:34ee385f4d2d 212 */
rajathr 0:34ee385f4d2d 213 void ADC_DeInit_mort(void)
rajathr 0:34ee385f4d2d 214 {
rajathr 0:34ee385f4d2d 215 /* Enable all ADCs reset state */
rajathr 0:34ee385f4d2d 216 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE);
rajathr 0:34ee385f4d2d 217
rajathr 0:34ee385f4d2d 218 /* Release all ADCs from reset state */
rajathr 0:34ee385f4d2d 219 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE);
rajathr 0:34ee385f4d2d 220 }
rajathr 0:34ee385f4d2d 221
rajathr 0:34ee385f4d2d 222 /**
rajathr 0:34ee385f4d2d 223 * @brief Initializes the ADCx peripheral according to the specified parameters
rajathr 0:34ee385f4d2d 224 * in the ADC_InitStruct.
rajathr 0:34ee385f4d2d 225 * @note This function is used to configure the global features of the ADC (
rajathr 0:34ee385f4d2d 226 * Resolution and Data Alignment), however, the rest of the configuration
rajathr 0:34ee385f4d2d 227 * parameters are specific to the regular channels group (scan mode
rajathr 0:34ee385f4d2d 228 * activation, continuous mode activation, External trigger source and
rajathr 0:34ee385f4d2d 229 * edge, number of conversion in the regular channels group sequencer).
rajathr 0:34ee385f4d2d 230 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 231 * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
rajathr 0:34ee385f4d2d 232 * the configuration information for the specified ADC peripheral.
rajathr 0:34ee385f4d2d 233 * @retval None
rajathr 0:34ee385f4d2d 234 */
rajathr 0:34ee385f4d2d 235 void ADC_Init_mort(ADC_TypeDef_mort* ADCx, ADC_InitTypeDef_mort* ADC_InitStruct)
rajathr 0:34ee385f4d2d 236 {
rajathr 0:34ee385f4d2d 237 uint32_t tmpreg1 = 0;
rajathr 0:34ee385f4d2d 238 uint8_t tmpreg2 = 0;
rajathr 0:34ee385f4d2d 239 /* Check the parameters */
rajathr 0:34ee385f4d2d 240 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 241 assert_param(IS_ADC_RESOLUTION_MORT(ADC_InitStruct->ADC_Resolution));
rajathr 0:34ee385f4d2d 242 assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
rajathr 0:34ee385f4d2d 243 assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
rajathr 0:34ee385f4d2d 244 assert_param(IS_ADC_EXT_TRIG_EDGE_MORT(ADC_InitStruct->ADC_ExternalTrigConvEdge));
rajathr 0:34ee385f4d2d 245 assert_param(IS_ADC_EXT_TRIG_MORT(ADC_InitStruct->ADC_ExternalTrigConv));
rajathr 0:34ee385f4d2d 246 assert_param(IS_ADC_DATA_ALIGN_MORT(ADC_InitStruct->ADC_DataAlign));
rajathr 0:34ee385f4d2d 247 assert_param(IS_ADC_REGULAR_LENGTH_MORT(ADC_InitStruct->ADC_NbrOfConversion));
rajathr 0:34ee385f4d2d 248
rajathr 0:34ee385f4d2d 249 /*---------------------------- ADCx CR1 Configuration -----------------*/
rajathr 0:34ee385f4d2d 250 /* Get the ADCx CR1 value */
rajathr 0:34ee385f4d2d 251 tmpreg1 = ADCx->CR1;
rajathr 0:34ee385f4d2d 252
rajathr 0:34ee385f4d2d 253 /* Clear RES and SCAN bits */
rajathr 0:34ee385f4d2d 254 tmpreg1 &= CR1_CLEAR_MASK;
rajathr 0:34ee385f4d2d 255
rajathr 0:34ee385f4d2d 256 /* Configure ADCx: scan conversion mode and resolution */
rajathr 0:34ee385f4d2d 257 /* Set SCAN bit according to ADC_ScanConvMode value */
rajathr 0:34ee385f4d2d 258 /* Set RES bit according to ADC_Resolution value */
rajathr 0:34ee385f4d2d 259 tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \
rajathr 0:34ee385f4d2d 260 ADC_InitStruct->ADC_Resolution);
rajathr 0:34ee385f4d2d 261 /* Write to ADCx CR1 */
rajathr 0:34ee385f4d2d 262 ADCx->CR1 = tmpreg1;
rajathr 0:34ee385f4d2d 263 /*---------------------------- ADCx CR2 Configuration -----------------*/
rajathr 0:34ee385f4d2d 264 /* Get the ADCx CR2 value */
rajathr 0:34ee385f4d2d 265 tmpreg1 = ADCx->CR2;
rajathr 0:34ee385f4d2d 266
rajathr 0:34ee385f4d2d 267 /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */
rajathr 0:34ee385f4d2d 268 tmpreg1 &= CR2_CLEAR_MASK;
rajathr 0:34ee385f4d2d 269
rajathr 0:34ee385f4d2d 270 /* Configure ADCx: external trigger event and edge, data alignment and
rajathr 0:34ee385f4d2d 271 continuous conversion mode */
rajathr 0:34ee385f4d2d 272 /* Set ALIGN bit according to ADC_DataAlign value */
rajathr 0:34ee385f4d2d 273 /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */
rajathr 0:34ee385f4d2d 274 /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
rajathr 0:34ee385f4d2d 275 /* Set CONT bit according to ADC_ContinuousConvMode value */
rajathr 0:34ee385f4d2d 276 tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \
rajathr 0:34ee385f4d2d 277 ADC_InitStruct->ADC_ExternalTrigConv |
rajathr 0:34ee385f4d2d 278 ADC_InitStruct->ADC_ExternalTrigConvEdge | \
rajathr 0:34ee385f4d2d 279 ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
rajathr 0:34ee385f4d2d 280
rajathr 0:34ee385f4d2d 281 /* Write to ADCx CR2 */
rajathr 0:34ee385f4d2d 282 ADCx->CR2 = tmpreg1;
rajathr 0:34ee385f4d2d 283 /*---------------------------- ADCx SQR1 Configuration -----------------*/
rajathr 0:34ee385f4d2d 284 /* Get the ADCx SQR1 value */
rajathr 0:34ee385f4d2d 285 tmpreg1 = ADCx->SQR1;
rajathr 0:34ee385f4d2d 286
rajathr 0:34ee385f4d2d 287 /* Clear L bits */
rajathr 0:34ee385f4d2d 288 tmpreg1 &= SQR1_L_RESET;
rajathr 0:34ee385f4d2d 289
rajathr 0:34ee385f4d2d 290 /* Configure ADCx: regular channel sequence length */
rajathr 0:34ee385f4d2d 291 /* Set L bits according to ADC_NbrOfConversion value */
rajathr 0:34ee385f4d2d 292 tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);
rajathr 0:34ee385f4d2d 293 tmpreg1 |= ((uint32_t)tmpreg2 << 20);
rajathr 0:34ee385f4d2d 294
rajathr 0:34ee385f4d2d 295 /* Write to ADCx SQR1 */
rajathr 0:34ee385f4d2d 296 ADCx->SQR1 = tmpreg1;
rajathr 0:34ee385f4d2d 297 }
rajathr 0:34ee385f4d2d 298
rajathr 0:34ee385f4d2d 299 /**
rajathr 0:34ee385f4d2d 300 * @brief Fills each ADC_InitStruct member with its default value.
rajathr 0:34ee385f4d2d 301 * @note This function is used to initialize the global features of the ADC (
rajathr 0:34ee385f4d2d 302 * Resolution and Data Alignment), however, the rest of the configuration
rajathr 0:34ee385f4d2d 303 * parameters are specific to the regular channels group (scan mode
rajathr 0:34ee385f4d2d 304 * activation, continuous mode activation, External trigger source and
rajathr 0:34ee385f4d2d 305 * edge, number of conversion in the regular channels group sequencer).
rajathr 0:34ee385f4d2d 306 * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will
rajathr 0:34ee385f4d2d 307 * be initialized.
rajathr 0:34ee385f4d2d 308 * @retval None
rajathr 0:34ee385f4d2d 309 */
rajathr 0:34ee385f4d2d 310 void ADC_StructInit_mort(ADC_InitTypeDef_mort* ADC_InitStruct)
rajathr 0:34ee385f4d2d 311 {
rajathr 0:34ee385f4d2d 312 /* Initialize the ADC_Mode member */
rajathr 0:34ee385f4d2d 313 ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
rajathr 0:34ee385f4d2d 314
rajathr 0:34ee385f4d2d 315 /* initialize the ADC_ScanConvMode member */
rajathr 0:34ee385f4d2d 316 ADC_InitStruct->ADC_ScanConvMode = DISABLE;
rajathr 0:34ee385f4d2d 317
rajathr 0:34ee385f4d2d 318 /* Initialize the ADC_ContinuousConvMode member */
rajathr 0:34ee385f4d2d 319 ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
rajathr 0:34ee385f4d2d 320
rajathr 0:34ee385f4d2d 321 /* Initialize the ADC_ExternalTrigConvEdge member */
rajathr 0:34ee385f4d2d 322 ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
rajathr 0:34ee385f4d2d 323
rajathr 0:34ee385f4d2d 324 /* Initialize the ADC_ExternalTrigConv member */
rajathr 0:34ee385f4d2d 325 ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
rajathr 0:34ee385f4d2d 326
rajathr 0:34ee385f4d2d 327 /* Initialize the ADC_DataAlign member */
rajathr 0:34ee385f4d2d 328 ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
rajathr 0:34ee385f4d2d 329
rajathr 0:34ee385f4d2d 330 /* Initialize the ADC_NbrOfConversion member */
rajathr 0:34ee385f4d2d 331 ADC_InitStruct->ADC_NbrOfConversion = 1;
rajathr 0:34ee385f4d2d 332 }
rajathr 0:34ee385f4d2d 333
rajathr 0:34ee385f4d2d 334 /**
rajathr 0:34ee385f4d2d 335 * @brief Initializes the ADCs peripherals according to the specified parameters
rajathr 0:34ee385f4d2d 336 * in the ADC_CommonInitStruct.
rajathr 0:34ee385f4d2d 337 * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
rajathr 0:34ee385f4d2d 338 * that contains the configuration information for All ADCs peripherals.
rajathr 0:34ee385f4d2d 339 * @retval None
rajathr 0:34ee385f4d2d 340 */
rajathr 0:34ee385f4d2d 341 void ADC_CommonInit_mort(ADC_CommonInitTypeDef_mort* ADC_CommonInitStruct)
rajathr 0:34ee385f4d2d 342 {
rajathr 0:34ee385f4d2d 343 uint32_t tmpreg1 = 0;
rajathr 0:34ee385f4d2d 344 /* Check the parameters */
rajathr 0:34ee385f4d2d 345 assert_param(IS_ADC_MODE_MORT(ADC_CommonInitStruct->ADC_Mode));
rajathr 0:34ee385f4d2d 346 assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));
rajathr 0:34ee385f4d2d 347 assert_param(IS_ADC_DMA_ACCESS_MODE_MORT(ADC_CommonInitStruct->ADC_DMAAccessMode));
rajathr 0:34ee385f4d2d 348 assert_param(IS_ADC_SAMPLING_DELAY_MORT(ADC_CommonInitStruct->ADC_TwoSamplingDelay));
rajathr 0:34ee385f4d2d 349 /*---------------------------- ADC CCR Configuration -----------------*/
rajathr 0:34ee385f4d2d 350 /* Get the ADC CCR value */
rajathr 0:34ee385f4d2d 351 tmpreg1 = ADC->CCR;
rajathr 0:34ee385f4d2d 352
rajathr 0:34ee385f4d2d 353 /* Clear MULTI, DELAY, DMA and ADCPRE bits */
rajathr 0:34ee385f4d2d 354 tmpreg1 &= CR_CLEAR_MASK;
rajathr 0:34ee385f4d2d 355
rajathr 0:34ee385f4d2d 356 /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler,
rajathr 0:34ee385f4d2d 357 and DMA access mode for multimode */
rajathr 0:34ee385f4d2d 358 /* Set MULTI bits according to ADC_Mode value */
rajathr 0:34ee385f4d2d 359 /* Set ADCPRE bits according to ADC_Prescaler value */
rajathr 0:34ee385f4d2d 360 /* Set DMA bits according to ADC_DMAAccessMode value */
rajathr 0:34ee385f4d2d 361 /* Set DELAY bits according to ADC_TwoSamplingDelay value */
rajathr 0:34ee385f4d2d 362 tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode |
rajathr 0:34ee385f4d2d 363 ADC_CommonInitStruct->ADC_Prescaler |
rajathr 0:34ee385f4d2d 364 ADC_CommonInitStruct->ADC_DMAAccessMode |
rajathr 0:34ee385f4d2d 365 ADC_CommonInitStruct->ADC_TwoSamplingDelay);
rajathr 0:34ee385f4d2d 366
rajathr 0:34ee385f4d2d 367 /* Write to ADC CCR */
rajathr 0:34ee385f4d2d 368 ADC->CCR = tmpreg1;
rajathr 0:34ee385f4d2d 369 }
rajathr 0:34ee385f4d2d 370
rajathr 0:34ee385f4d2d 371 /**
rajathr 0:34ee385f4d2d 372 * @brief Fills each ADC_CommonInitStruct member with its default value.
rajathr 0:34ee385f4d2d 373 * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
rajathr 0:34ee385f4d2d 374 * which will be initialized.
rajathr 0:34ee385f4d2d 375 * @retval None
rajathr 0:34ee385f4d2d 376 */
rajathr 0:34ee385f4d2d 377 void ADC_CommonStructInit_mort(ADC_CommonInitTypeDef_mort* ADC_CommonInitStruct)
rajathr 0:34ee385f4d2d 378 {
rajathr 0:34ee385f4d2d 379 /* Initialize the ADC_Mode member */
rajathr 0:34ee385f4d2d 380 ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;
rajathr 0:34ee385f4d2d 381
rajathr 0:34ee385f4d2d 382 /* initialize the ADC_Prescaler member */
rajathr 0:34ee385f4d2d 383 ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2;
rajathr 0:34ee385f4d2d 384
rajathr 0:34ee385f4d2d 385 /* Initialize the ADC_DMAAccessMode member */
rajathr 0:34ee385f4d2d 386 ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
rajathr 0:34ee385f4d2d 387
rajathr 0:34ee385f4d2d 388 /* Initialize the ADC_TwoSamplingDelay member */
rajathr 0:34ee385f4d2d 389 ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
rajathr 0:34ee385f4d2d 390 }
rajathr 0:34ee385f4d2d 391
rajathr 0:34ee385f4d2d 392 /**
rajathr 0:34ee385f4d2d 393 * @brief Enables or disables the specified ADC peripheral.
rajathr 0:34ee385f4d2d 394 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 395 * @param NewState: new state of the ADCx peripheral.
rajathr 0:34ee385f4d2d 396 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 397 * @retval None
rajathr 0:34ee385f4d2d 398 */
rajathr 0:34ee385f4d2d 399 void ADC_Cmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 400 {
rajathr 0:34ee385f4d2d 401 /* Check the parameters */
rajathr 0:34ee385f4d2d 402 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 403 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 404 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 405 {
rajathr 0:34ee385f4d2d 406 /* Set the ADON bit to wake up the ADC from power down mode */
rajathr 0:34ee385f4d2d 407 ADCx->CR2 |= (uint32_t)ADC_CR2_ADON_MORT;
rajathr 0:34ee385f4d2d 408 }
rajathr 0:34ee385f4d2d 409 else
rajathr 0:34ee385f4d2d 410 {
rajathr 0:34ee385f4d2d 411 /* Disable the selected ADC peripheral */
rajathr 0:34ee385f4d2d 412 ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON_MORT);
rajathr 0:34ee385f4d2d 413 }
rajathr 0:34ee385f4d2d 414 }
rajathr 0:34ee385f4d2d 415 /**
rajathr 0:34ee385f4d2d 416 * @}
rajathr 0:34ee385f4d2d 417 */
rajathr 0:34ee385f4d2d 418
rajathr 0:34ee385f4d2d 419 /** @defgroup ADC_Group2 Analog Watchdog configuration functions
rajathr 0:34ee385f4d2d 420 * @brief Analog Watchdog configuration functions
rajathr 0:34ee385f4d2d 421 *
rajathr 0:34ee385f4d2d 422 @verbatim
rajathr 0:34ee385f4d2d 423 ===============================================================================
rajathr 0:34ee385f4d2d 424 ##### Analog Watchdog configuration functions #####
rajathr 0:34ee385f4d2d 425 ===============================================================================
rajathr 0:34ee385f4d2d 426 [..] This section provides functions allowing to configure the Analog Watchdog
rajathr 0:34ee385f4d2d 427 (AWD) feature in the ADC.
rajathr 0:34ee385f4d2d 428
rajathr 0:34ee385f4d2d 429 [..] A typical configuration Analog Watchdog is done following these steps :
rajathr 0:34ee385f4d2d 430 (#) the ADC guarded channel(s) is (are) selected using the
rajathr 0:34ee385f4d2d 431 ADC_AnalogWatchdogSingleChannelConfig() function.
rajathr 0:34ee385f4d2d 432 (#) The Analog watchdog lower and higher threshold are configured using the
rajathr 0:34ee385f4d2d 433 ADC_AnalogWatchdogThresholdsConfig() function.
rajathr 0:34ee385f4d2d 434 (#) The Analog watchdog is enabled and configured to enable the check, on one
rajathr 0:34ee385f4d2d 435 or more channels, using the ADC_AnalogWatchdogCmd() function.
rajathr 0:34ee385f4d2d 436 @endverbatim
rajathr 0:34ee385f4d2d 437 * @{
rajathr 0:34ee385f4d2d 438 */
rajathr 0:34ee385f4d2d 439
rajathr 0:34ee385f4d2d 440 /**
rajathr 0:34ee385f4d2d 441 * @brief Enables or disables the analog watchdog on single/all regular or
rajathr 0:34ee385f4d2d 442 * injected channels
rajathr 0:34ee385f4d2d 443 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 444 * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
rajathr 0:34ee385f4d2d 445 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 446 * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
rajathr 0:34ee385f4d2d 447 * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
rajathr 0:34ee385f4d2d 448 * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
rajathr 0:34ee385f4d2d 449 * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
rajathr 0:34ee385f4d2d 450 * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
rajathr 0:34ee385f4d2d 451 * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
rajathr 0:34ee385f4d2d 452 * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
rajathr 0:34ee385f4d2d 453 * @retval None
rajathr 0:34ee385f4d2d 454 */
rajathr 0:34ee385f4d2d 455 void ADC_AnalogWatchdogCmd_mort(ADC_TypeDef_mort* ADCx, uint32_t ADC_AnalogWatchdog)
rajathr 0:34ee385f4d2d 456 {
rajathr 0:34ee385f4d2d 457 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 458 /* Check the parameters */
rajathr 0:34ee385f4d2d 459 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 460 assert_param(IS_ADC_ANALOG_WATCHDOG_MORT(ADC_AnalogWatchdog));
rajathr 0:34ee385f4d2d 461
rajathr 0:34ee385f4d2d 462 /* Get the old register value */
rajathr 0:34ee385f4d2d 463 tmpreg = ADCx->CR1;
rajathr 0:34ee385f4d2d 464
rajathr 0:34ee385f4d2d 465 /* Clear AWDEN, JAWDEN and AWDSGL bits */
rajathr 0:34ee385f4d2d 466 tmpreg &= CR1_AWDMode_RESET;
rajathr 0:34ee385f4d2d 467
rajathr 0:34ee385f4d2d 468 /* Set the analog watchdog enable mode */
rajathr 0:34ee385f4d2d 469 tmpreg |= ADC_AnalogWatchdog;
rajathr 0:34ee385f4d2d 470
rajathr 0:34ee385f4d2d 471 /* Store the new register value */
rajathr 0:34ee385f4d2d 472 ADCx->CR1 = tmpreg;
rajathr 0:34ee385f4d2d 473 }
rajathr 0:34ee385f4d2d 474
rajathr 0:34ee385f4d2d 475 /**
rajathr 0:34ee385f4d2d 476 * @brief Configures the high and low thresholds of the analog watchdog.
rajathr 0:34ee385f4d2d 477 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 478 * @param HighThreshold: the ADC analog watchdog High threshold value.
rajathr 0:34ee385f4d2d 479 * This parameter must be a 12-bit value.
rajathr 0:34ee385f4d2d 480 * @param LowThreshold: the ADC analog watchdog Low threshold value.
rajathr 0:34ee385f4d2d 481 * This parameter must be a 12-bit value.
rajathr 0:34ee385f4d2d 482 * @retval None
rajathr 0:34ee385f4d2d 483 */
rajathr 0:34ee385f4d2d 484 void ADC_AnalogWatchdogThresholdsConfig_mort(ADC_TypeDef_mort* ADCx, uint16_t HighThreshold,
rajathr 0:34ee385f4d2d 485 uint16_t LowThreshold)
rajathr 0:34ee385f4d2d 486 {
rajathr 0:34ee385f4d2d 487 /* Check the parameters */
rajathr 0:34ee385f4d2d 488 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 489 assert_param(IS_ADC_THRESHOLD_MORT(HighThreshold));
rajathr 0:34ee385f4d2d 490 assert_param(IS_ADC_THRESHOLD_MORT(LowThreshold));
rajathr 0:34ee385f4d2d 491
rajathr 0:34ee385f4d2d 492 /* Set the ADCx high threshold */
rajathr 0:34ee385f4d2d 493 ADCx->HTR = HighThreshold;
rajathr 0:34ee385f4d2d 494
rajathr 0:34ee385f4d2d 495 /* Set the ADCx low threshold */
rajathr 0:34ee385f4d2d 496 ADCx->LTR = LowThreshold;
rajathr 0:34ee385f4d2d 497 }
rajathr 0:34ee385f4d2d 498
rajathr 0:34ee385f4d2d 499 /**
rajathr 0:34ee385f4d2d 500 * @brief Configures the analog watchdog guarded single channel
rajathr 0:34ee385f4d2d 501 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 502 * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
rajathr 0:34ee385f4d2d 503 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 504 * @arg ADC_Channel_0: ADC Channel0 selected
rajathr 0:34ee385f4d2d 505 * @arg ADC_Channel_1: ADC Channel1 selected
rajathr 0:34ee385f4d2d 506 * @arg ADC_Channel_2: ADC Channel2 selected
rajathr 0:34ee385f4d2d 507 * @arg ADC_Channel_3: ADC Channel3 selected
rajathr 0:34ee385f4d2d 508 * @arg ADC_Channel_4: ADC Channel4 selected
rajathr 0:34ee385f4d2d 509 * @arg ADC_Channel_5: ADC Channel5 selected
rajathr 0:34ee385f4d2d 510 * @arg ADC_Channel_6: ADC Channel6 selected
rajathr 0:34ee385f4d2d 511 * @arg ADC_Channel_7: ADC Channel7 selected
rajathr 0:34ee385f4d2d 512 * @arg ADC_Channel_8: ADC Channel8 selected
rajathr 0:34ee385f4d2d 513 * @arg ADC_Channel_9: ADC Channel9 selected
rajathr 0:34ee385f4d2d 514 * @arg ADC_Channel_10: ADC Channel10 selected
rajathr 0:34ee385f4d2d 515 * @arg ADC_Channel_11: ADC Channel11 selected
rajathr 0:34ee385f4d2d 516 * @arg ADC_Channel_12: ADC Channel12 selected
rajathr 0:34ee385f4d2d 517 * @arg ADC_Channel_13: ADC Channel13 selected
rajathr 0:34ee385f4d2d 518 * @arg ADC_Channel_14: ADC Channel14 selected
rajathr 0:34ee385f4d2d 519 * @arg ADC_Channel_15: ADC Channel15 selected
rajathr 0:34ee385f4d2d 520 * @arg ADC_Channel_16: ADC Channel16 selected
rajathr 0:34ee385f4d2d 521 * @arg ADC_Channel_17: ADC Channel17 selected
rajathr 0:34ee385f4d2d 522 * @arg ADC_Channel_18: ADC Channel18 selected
rajathr 0:34ee385f4d2d 523 * @retval None
rajathr 0:34ee385f4d2d 524 */
rajathr 0:34ee385f4d2d 525 void ADC_AnalogWatchdogSingleChannelConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_Channel)
rajathr 0:34ee385f4d2d 526 {
rajathr 0:34ee385f4d2d 527 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 528 /* Check the parameters */
rajathr 0:34ee385f4d2d 529 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 530 assert_param(IS_ADC_CHANNEL(ADC_Channel));
rajathr 0:34ee385f4d2d 531
rajathr 0:34ee385f4d2d 532 /* Get the old register value */
rajathr 0:34ee385f4d2d 533 tmpreg = ADCx->CR1;
rajathr 0:34ee385f4d2d 534
rajathr 0:34ee385f4d2d 535 /* Clear the Analog watchdog channel select bits */
rajathr 0:34ee385f4d2d 536 tmpreg &= CR1_AWDCH_RESET;
rajathr 0:34ee385f4d2d 537
rajathr 0:34ee385f4d2d 538 /* Set the Analog watchdog channel */
rajathr 0:34ee385f4d2d 539 tmpreg |= ADC_Channel;
rajathr 0:34ee385f4d2d 540
rajathr 0:34ee385f4d2d 541 /* Store the new register value */
rajathr 0:34ee385f4d2d 542 ADCx->CR1 = tmpreg;
rajathr 0:34ee385f4d2d 543 }
rajathr 0:34ee385f4d2d 544 /**
rajathr 0:34ee385f4d2d 545 * @}
rajathr 0:34ee385f4d2d 546 */
rajathr 0:34ee385f4d2d 547
rajathr 0:34ee385f4d2d 548 /** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal)
rajathr 0:34ee385f4d2d 549 * and VBAT (Voltage BATtery) management functions
rajathr 0:34ee385f4d2d 550 * @brief Temperature Sensor, Vrefint and VBAT management functions
rajathr 0:34ee385f4d2d 551 *
rajathr 0:34ee385f4d2d 552 @verbatim
rajathr 0:34ee385f4d2d 553 ===============================================================================
rajathr 0:34ee385f4d2d 554 ##### Temperature Sensor, Vrefint and VBAT management functions #####
rajathr 0:34ee385f4d2d 555 ===============================================================================
rajathr 0:34ee385f4d2d 556 [..] This section provides functions allowing to enable/ disable the internal
rajathr 0:34ee385f4d2d 557 connections between the ADC and the Temperature Sensor, the Vrefint and
rajathr 0:34ee385f4d2d 558 the Vbat sources.
rajathr 0:34ee385f4d2d 559
rajathr 0:34ee385f4d2d 560 [..] A typical configuration to get the Temperature sensor and Vrefint channels
rajathr 0:34ee385f4d2d 561 voltages is done following these steps :
rajathr 0:34ee385f4d2d 562 (#) Enable the internal connection of Temperature sensor and Vrefint sources
rajathr 0:34ee385f4d2d 563 with the ADC channels using ADC_TempSensorVrefintCmd() function.
rajathr 0:34ee385f4d2d 564 (#) Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using
rajathr 0:34ee385f4d2d 565 ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions
rajathr 0:34ee385f4d2d 566 (#) Get the voltage values, using ADC_GetConversionValue() or
rajathr 0:34ee385f4d2d 567 ADC_GetInjectedConversionValue().
rajathr 0:34ee385f4d2d 568
rajathr 0:34ee385f4d2d 569 [..] A typical configuration to get the VBAT channel voltage is done following
rajathr 0:34ee385f4d2d 570 these steps :
rajathr 0:34ee385f4d2d 571 (#) Enable the internal connection of VBAT source with the ADC channel using
rajathr 0:34ee385f4d2d 572 ADC_VBATCmd() function.
rajathr 0:34ee385f4d2d 573 (#) Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or
rajathr 0:34ee385f4d2d 574 ADC_InjectedChannelConfig() functions
rajathr 0:34ee385f4d2d 575 (#) Get the voltage value, using ADC_GetConversionValue() or
rajathr 0:34ee385f4d2d 576 ADC_GetInjectedConversionValue().
rajathr 0:34ee385f4d2d 577
rajathr 0:34ee385f4d2d 578 @endverbatim
rajathr 0:34ee385f4d2d 579 * @{
rajathr 0:34ee385f4d2d 580 */
rajathr 0:34ee385f4d2d 581
rajathr 0:34ee385f4d2d 582
rajathr 0:34ee385f4d2d 583 /**
rajathr 0:34ee385f4d2d 584 * @brief Enables or disables the temperature sensor and Vrefint channels.
rajathr 0:34ee385f4d2d 585 * @param NewState: new state of the temperature sensor and Vrefint channels.
rajathr 0:34ee385f4d2d 586 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 587 * @retval None
rajathr 0:34ee385f4d2d 588 */
rajathr 0:34ee385f4d2d 589 void ADC_TempSensorVrefintCmd_mort(FunctionalState NewState)
rajathr 0:34ee385f4d2d 590 {
rajathr 0:34ee385f4d2d 591 /* Check the parameters */
rajathr 0:34ee385f4d2d 592 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 593 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 594 {
rajathr 0:34ee385f4d2d 595 /* Enable the temperature sensor and Vrefint channel*/
rajathr 0:34ee385f4d2d 596 ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE_MORT;
rajathr 0:34ee385f4d2d 597 }
rajathr 0:34ee385f4d2d 598 else
rajathr 0:34ee385f4d2d 599 {
rajathr 0:34ee385f4d2d 600 /* Disable the temperature sensor and Vrefint channel*/
rajathr 0:34ee385f4d2d 601 ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE_MORT);
rajathr 0:34ee385f4d2d 602 }
rajathr 0:34ee385f4d2d 603 }
rajathr 0:34ee385f4d2d 604
rajathr 0:34ee385f4d2d 605 /**
rajathr 0:34ee385f4d2d 606 * @brief Enables or disables the VBAT (Voltage Battery) channel.
rajathr 0:34ee385f4d2d 607 *
rajathr 0:34ee385f4d2d 608 * @note the Battery voltage measured is equal to VBAT/2 on STM32F40xx and
rajathr 0:34ee385f4d2d 609 * STM32F41xx devices and equal to VBAT/4 on STM32F42xx and STM32F43xx devices
rajathr 0:34ee385f4d2d 610 *
rajathr 0:34ee385f4d2d 611 * @param NewState: new state of the VBAT channel.
rajathr 0:34ee385f4d2d 612 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 613 * @retval None
rajathr 0:34ee385f4d2d 614 */
rajathr 0:34ee385f4d2d 615 void ADC_VBATCmd_mort(FunctionalState NewState)
rajathr 0:34ee385f4d2d 616 {
rajathr 0:34ee385f4d2d 617 /* Check the parameters */
rajathr 0:34ee385f4d2d 618 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 619 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 620 {
rajathr 0:34ee385f4d2d 621 /* Enable the VBAT channel*/
rajathr 0:34ee385f4d2d 622 ADC->CCR |= (uint32_t)ADC_CCR_VBATE_MORT;
rajathr 0:34ee385f4d2d 623 }
rajathr 0:34ee385f4d2d 624 else
rajathr 0:34ee385f4d2d 625 {
rajathr 0:34ee385f4d2d 626 /* Disable the VBAT channel*/
rajathr 0:34ee385f4d2d 627 ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE_MORT);
rajathr 0:34ee385f4d2d 628 }
rajathr 0:34ee385f4d2d 629 }
rajathr 0:34ee385f4d2d 630
rajathr 0:34ee385f4d2d 631 /**
rajathr 0:34ee385f4d2d 632 * @}
rajathr 0:34ee385f4d2d 633 */
rajathr 0:34ee385f4d2d 634
rajathr 0:34ee385f4d2d 635 /** @defgroup ADC_Group4 Regular Channels Configuration functions
rajathr 0:34ee385f4d2d 636 * @brief Regular Channels Configuration functions
rajathr 0:34ee385f4d2d 637 *
rajathr 0:34ee385f4d2d 638 @verbatim
rajathr 0:34ee385f4d2d 639 ===============================================================================
rajathr 0:34ee385f4d2d 640 ##### Regular Channels Configuration functions #####
rajathr 0:34ee385f4d2d 641 ===============================================================================
rajathr 0:34ee385f4d2d 642
rajathr 0:34ee385f4d2d 643 [..] This section provides functions allowing to manage the ADC's regular channels,
rajathr 0:34ee385f4d2d 644 it is composed of 2 sub sections :
rajathr 0:34ee385f4d2d 645
rajathr 0:34ee385f4d2d 646 (#) Configuration and management functions for regular channels: This subsection
rajathr 0:34ee385f4d2d 647 provides functions allowing to configure the ADC regular channels :
rajathr 0:34ee385f4d2d 648 (++) Configure the rank in the regular group sequencer for each channel
rajathr 0:34ee385f4d2d 649 (++) Configure the sampling time for each channel
rajathr 0:34ee385f4d2d 650 (++) select the conversion Trigger for regular channels
rajathr 0:34ee385f4d2d 651 (++) select the desired EOC event behavior configuration
rajathr 0:34ee385f4d2d 652 (++) Activate the continuous Mode (*)
rajathr 0:34ee385f4d2d 653 (++) Activate the Discontinuous Mode
rajathr 0:34ee385f4d2d 654 -@@- Please Note that the following features for regular channels
rajathr 0:34ee385f4d2d 655 are configured using the ADC_Init() function :
rajathr 0:34ee385f4d2d 656 (+@@) scan mode activation
rajathr 0:34ee385f4d2d 657 (+@@) continuous mode activation (**)
rajathr 0:34ee385f4d2d 658 (+@@) External trigger source
rajathr 0:34ee385f4d2d 659 (+@@) External trigger edge
rajathr 0:34ee385f4d2d 660 (+@@) number of conversion in the regular channels group sequencer.
rajathr 0:34ee385f4d2d 661
rajathr 0:34ee385f4d2d 662 -@@- (*) and (**) are performing the same configuration
rajathr 0:34ee385f4d2d 663
rajathr 0:34ee385f4d2d 664 (#) Get the conversion data: This subsection provides an important function in
rajathr 0:34ee385f4d2d 665 the ADC peripheral since it returns the converted data of the current
rajathr 0:34ee385f4d2d 666 regular channel. When the Conversion value is read, the EOC Flag is
rajathr 0:34ee385f4d2d 667 automatically cleared.
rajathr 0:34ee385f4d2d 668
rajathr 0:34ee385f4d2d 669 -@- For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions
rajathr 0:34ee385f4d2d 670 results data (in the selected multi mode) can be returned in the same
rajathr 0:34ee385f4d2d 671 time using ADC_GetMultiModeConversionValue() function.
rajathr 0:34ee385f4d2d 672
rajathr 0:34ee385f4d2d 673 @endverbatim
rajathr 0:34ee385f4d2d 674 * @{
rajathr 0:34ee385f4d2d 675 */
rajathr 0:34ee385f4d2d 676 /**
rajathr 0:34ee385f4d2d 677 * @brief Configures for the selected ADC regular channel its corresponding
rajathr 0:34ee385f4d2d 678 * rank in the sequencer and its sample time.
rajathr 0:34ee385f4d2d 679 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 680 * @param ADC_Channel: the ADC channel to configure.
rajathr 0:34ee385f4d2d 681 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 682 * @arg ADC_Channel_0: ADC Channel0 selected
rajathr 0:34ee385f4d2d 683 * @arg ADC_Channel_1: ADC Channel1 selected
rajathr 0:34ee385f4d2d 684 * @arg ADC_Channel_2: ADC Channel2 selected
rajathr 0:34ee385f4d2d 685 * @arg ADC_Channel_3: ADC Channel3 selected
rajathr 0:34ee385f4d2d 686 * @arg ADC_Channel_4: ADC Channel4 selected
rajathr 0:34ee385f4d2d 687 * @arg ADC_Channel_5: ADC Channel5 selected
rajathr 0:34ee385f4d2d 688 * @arg ADC_Channel_6: ADC Channel6 selected
rajathr 0:34ee385f4d2d 689 * @arg ADC_Channel_7: ADC Channel7 selected
rajathr 0:34ee385f4d2d 690 * @arg ADC_Channel_8: ADC Channel8 selected
rajathr 0:34ee385f4d2d 691 * @arg ADC_Channel_9: ADC Channel9 selected
rajathr 0:34ee385f4d2d 692 * @arg ADC_Channel_10: ADC Channel10 selected
rajathr 0:34ee385f4d2d 693 * @arg ADC_Channel_11: ADC Channel11 selected
rajathr 0:34ee385f4d2d 694 * @arg ADC_Channel_12: ADC Channel12 selected
rajathr 0:34ee385f4d2d 695 * @arg ADC_Channel_13: ADC Channel13 selected
rajathr 0:34ee385f4d2d 696 * @arg ADC_Channel_14: ADC Channel14 selected
rajathr 0:34ee385f4d2d 697 * @arg ADC_Channel_15: ADC Channel15 selected
rajathr 0:34ee385f4d2d 698 * @arg ADC_Channel_16: ADC Channel16 selected
rajathr 0:34ee385f4d2d 699 * @arg ADC_Channel_17: ADC Channel17 selected
rajathr 0:34ee385f4d2d 700 * @arg ADC_Channel_18: ADC Channel18 selected
rajathr 0:34ee385f4d2d 701 * @param Rank: The rank in the regular group sequencer.
rajathr 0:34ee385f4d2d 702 * This parameter must be between 1 to 16.
rajathr 0:34ee385f4d2d 703 * @param ADC_SampleTime: The sample time value to be set for the selected channel.
rajathr 0:34ee385f4d2d 704 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 705 * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
rajathr 0:34ee385f4d2d 706 * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
rajathr 0:34ee385f4d2d 707 * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
rajathr 0:34ee385f4d2d 708 * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
rajathr 0:34ee385f4d2d 709 * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
rajathr 0:34ee385f4d2d 710 * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
rajathr 0:34ee385f4d2d 711 * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
rajathr 0:34ee385f4d2d 712 * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
rajathr 0:34ee385f4d2d 713 * @retval None
rajathr 0:34ee385f4d2d 714 */
rajathr 0:34ee385f4d2d 715 void ADC_RegularChannelConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
rajathr 0:34ee385f4d2d 716 {
rajathr 0:34ee385f4d2d 717 uint32_t tmpreg1 = 0, tmpreg2 = 0;
rajathr 0:34ee385f4d2d 718 /* Check the parameters */
rajathr 0:34ee385f4d2d 719 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 720 assert_param(IS_ADC_CHANNEL(ADC_Channel));
rajathr 0:34ee385f4d2d 721 assert_param(IS_ADC_REGULAR_RANK_MORT(Rank));
rajathr 0:34ee385f4d2d 722 assert_param(IS_ADC_SAMPLE_TIME_MORT(ADC_SampleTime));
rajathr 0:34ee385f4d2d 723
rajathr 0:34ee385f4d2d 724 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
rajathr 0:34ee385f4d2d 725 if (ADC_Channel > ADC_Channel_9)
rajathr 0:34ee385f4d2d 726 {
rajathr 0:34ee385f4d2d 727 /* Get the old register value */
rajathr 0:34ee385f4d2d 728 tmpreg1 = ADCx->SMPR1;
rajathr 0:34ee385f4d2d 729
rajathr 0:34ee385f4d2d 730 /* Calculate the mask to clear */
rajathr 0:34ee385f4d2d 731 tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10));
rajathr 0:34ee385f4d2d 732
rajathr 0:34ee385f4d2d 733 /* Clear the old sample time */
rajathr 0:34ee385f4d2d 734 tmpreg1 &= ~tmpreg2;
rajathr 0:34ee385f4d2d 735
rajathr 0:34ee385f4d2d 736 /* Calculate the mask to set */
rajathr 0:34ee385f4d2d 737 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
rajathr 0:34ee385f4d2d 738
rajathr 0:34ee385f4d2d 739 /* Set the new sample time */
rajathr 0:34ee385f4d2d 740 tmpreg1 |= tmpreg2;
rajathr 0:34ee385f4d2d 741
rajathr 0:34ee385f4d2d 742 /* Store the new register value */
rajathr 0:34ee385f4d2d 743 ADCx->SMPR1 = tmpreg1;
rajathr 0:34ee385f4d2d 744 }
rajathr 0:34ee385f4d2d 745 else /* ADC_Channel include in ADC_Channel_[0..9] */
rajathr 0:34ee385f4d2d 746 {
rajathr 0:34ee385f4d2d 747 /* Get the old register value */
rajathr 0:34ee385f4d2d 748 tmpreg1 = ADCx->SMPR2;
rajathr 0:34ee385f4d2d 749
rajathr 0:34ee385f4d2d 750 /* Calculate the mask to clear */
rajathr 0:34ee385f4d2d 751 tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
rajathr 0:34ee385f4d2d 752
rajathr 0:34ee385f4d2d 753 /* Clear the old sample time */
rajathr 0:34ee385f4d2d 754 tmpreg1 &= ~tmpreg2;
rajathr 0:34ee385f4d2d 755
rajathr 0:34ee385f4d2d 756 /* Calculate the mask to set */
rajathr 0:34ee385f4d2d 757 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
rajathr 0:34ee385f4d2d 758
rajathr 0:34ee385f4d2d 759 /* Set the new sample time */
rajathr 0:34ee385f4d2d 760 tmpreg1 |= tmpreg2;
rajathr 0:34ee385f4d2d 761
rajathr 0:34ee385f4d2d 762 /* Store the new register value */
rajathr 0:34ee385f4d2d 763 ADCx->SMPR2 = tmpreg1;
rajathr 0:34ee385f4d2d 764 }
rajathr 0:34ee385f4d2d 765 /* For Rank 1 to 6 */
rajathr 0:34ee385f4d2d 766 if (Rank < 7)
rajathr 0:34ee385f4d2d 767 {
rajathr 0:34ee385f4d2d 768 /* Get the old register value */
rajathr 0:34ee385f4d2d 769 tmpreg1 = ADCx->SQR3;
rajathr 0:34ee385f4d2d 770
rajathr 0:34ee385f4d2d 771 /* Calculate the mask to clear */
rajathr 0:34ee385f4d2d 772 tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1));
rajathr 0:34ee385f4d2d 773
rajathr 0:34ee385f4d2d 774 /* Clear the old SQx bits for the selected rank */
rajathr 0:34ee385f4d2d 775 tmpreg1 &= ~tmpreg2;
rajathr 0:34ee385f4d2d 776
rajathr 0:34ee385f4d2d 777 /* Calculate the mask to set */
rajathr 0:34ee385f4d2d 778 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
rajathr 0:34ee385f4d2d 779
rajathr 0:34ee385f4d2d 780 /* Set the SQx bits for the selected rank */
rajathr 0:34ee385f4d2d 781 tmpreg1 |= tmpreg2;
rajathr 0:34ee385f4d2d 782
rajathr 0:34ee385f4d2d 783 /* Store the new register value */
rajathr 0:34ee385f4d2d 784 ADCx->SQR3 = tmpreg1;
rajathr 0:34ee385f4d2d 785 }
rajathr 0:34ee385f4d2d 786 /* For Rank 7 to 12 */
rajathr 0:34ee385f4d2d 787 else if (Rank < 13)
rajathr 0:34ee385f4d2d 788 {
rajathr 0:34ee385f4d2d 789 /* Get the old register value */
rajathr 0:34ee385f4d2d 790 tmpreg1 = ADCx->SQR2;
rajathr 0:34ee385f4d2d 791
rajathr 0:34ee385f4d2d 792 /* Calculate the mask to clear */
rajathr 0:34ee385f4d2d 793 tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7));
rajathr 0:34ee385f4d2d 794
rajathr 0:34ee385f4d2d 795 /* Clear the old SQx bits for the selected rank */
rajathr 0:34ee385f4d2d 796 tmpreg1 &= ~tmpreg2;
rajathr 0:34ee385f4d2d 797
rajathr 0:34ee385f4d2d 798 /* Calculate the mask to set */
rajathr 0:34ee385f4d2d 799 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
rajathr 0:34ee385f4d2d 800
rajathr 0:34ee385f4d2d 801 /* Set the SQx bits for the selected rank */
rajathr 0:34ee385f4d2d 802 tmpreg1 |= tmpreg2;
rajathr 0:34ee385f4d2d 803
rajathr 0:34ee385f4d2d 804 /* Store the new register value */
rajathr 0:34ee385f4d2d 805 ADCx->SQR2 = tmpreg1;
rajathr 0:34ee385f4d2d 806 }
rajathr 0:34ee385f4d2d 807 /* For Rank 13 to 16 */
rajathr 0:34ee385f4d2d 808 else
rajathr 0:34ee385f4d2d 809 {
rajathr 0:34ee385f4d2d 810 /* Get the old register value */
rajathr 0:34ee385f4d2d 811 tmpreg1 = ADCx->SQR1;
rajathr 0:34ee385f4d2d 812
rajathr 0:34ee385f4d2d 813 /* Calculate the mask to clear */
rajathr 0:34ee385f4d2d 814 tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13));
rajathr 0:34ee385f4d2d 815
rajathr 0:34ee385f4d2d 816 /* Clear the old SQx bits for the selected rank */
rajathr 0:34ee385f4d2d 817 tmpreg1 &= ~tmpreg2;
rajathr 0:34ee385f4d2d 818
rajathr 0:34ee385f4d2d 819 /* Calculate the mask to set */
rajathr 0:34ee385f4d2d 820 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
rajathr 0:34ee385f4d2d 821
rajathr 0:34ee385f4d2d 822 /* Set the SQx bits for the selected rank */
rajathr 0:34ee385f4d2d 823 tmpreg1 |= tmpreg2;
rajathr 0:34ee385f4d2d 824
rajathr 0:34ee385f4d2d 825 /* Store the new register value */
rajathr 0:34ee385f4d2d 826 ADCx->SQR1 = tmpreg1;
rajathr 0:34ee385f4d2d 827 }
rajathr 0:34ee385f4d2d 828 }
rajathr 0:34ee385f4d2d 829
rajathr 0:34ee385f4d2d 830 /**
rajathr 0:34ee385f4d2d 831 * @brief Enables the selected ADC software start conversion of the regular channels.
rajathr 0:34ee385f4d2d 832 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 833 * @retval None
rajathr 0:34ee385f4d2d 834 */
rajathr 0:34ee385f4d2d 835 void ADC_SoftwareStartConv_mort(ADC_TypeDef_mort* ADCx)
rajathr 0:34ee385f4d2d 836 {
rajathr 0:34ee385f4d2d 837 /* Check the parameters */
rajathr 0:34ee385f4d2d 838 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 839
rajathr 0:34ee385f4d2d 840 /* Enable the selected ADC conversion for regular group */
rajathr 0:34ee385f4d2d 841 ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART_MORT;
rajathr 0:34ee385f4d2d 842 }
rajathr 0:34ee385f4d2d 843
rajathr 0:34ee385f4d2d 844 /**
rajathr 0:34ee385f4d2d 845 * @brief Gets the selected ADC Software start regular conversion Status.
rajathr 0:34ee385f4d2d 846 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 847 * @retval The new state of ADC software start conversion (SET or RESET).
rajathr 0:34ee385f4d2d 848 */
rajathr 0:34ee385f4d2d 849 FlagStatus ADC_GetSoftwareStartConvStatus_mort(ADC_TypeDef_mort* ADCx)
rajathr 0:34ee385f4d2d 850 {
rajathr 0:34ee385f4d2d 851 FlagStatus bitstatus = RESET;
rajathr 0:34ee385f4d2d 852 /* Check the parameters */
rajathr 0:34ee385f4d2d 853 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 854
rajathr 0:34ee385f4d2d 855 /* Check the status of SWSTART bit */
rajathr 0:34ee385f4d2d 856 if ((ADCx->CR2 & ADC_CR2_SWSTART_MORT) != (uint32_t)RESET)
rajathr 0:34ee385f4d2d 857 {
rajathr 0:34ee385f4d2d 858 /* SWSTART bit is set */
rajathr 0:34ee385f4d2d 859 bitstatus = SET;
rajathr 0:34ee385f4d2d 860 }
rajathr 0:34ee385f4d2d 861 else
rajathr 0:34ee385f4d2d 862 {
rajathr 0:34ee385f4d2d 863 /* SWSTART bit is reset */
rajathr 0:34ee385f4d2d 864 bitstatus = RESET;
rajathr 0:34ee385f4d2d 865 }
rajathr 0:34ee385f4d2d 866
rajathr 0:34ee385f4d2d 867 /* Return the SWSTART bit status */
rajathr 0:34ee385f4d2d 868 return bitstatus;
rajathr 0:34ee385f4d2d 869 }
rajathr 0:34ee385f4d2d 870
rajathr 0:34ee385f4d2d 871
rajathr 0:34ee385f4d2d 872 /**
rajathr 0:34ee385f4d2d 873 * @brief Enables or disables the EOC on each regular channel conversion
rajathr 0:34ee385f4d2d 874 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 875 * @param NewState: new state of the selected ADC EOC flag rising
rajathr 0:34ee385f4d2d 876 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 877 * @retval None
rajathr 0:34ee385f4d2d 878 */
rajathr 0:34ee385f4d2d 879 void ADC_EOCOnEachRegularChannelCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 880 {
rajathr 0:34ee385f4d2d 881 /* Check the parameters */
rajathr 0:34ee385f4d2d 882 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 883 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 884
rajathr 0:34ee385f4d2d 885 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 886 {
rajathr 0:34ee385f4d2d 887 /* Enable the selected ADC EOC rising on each regular channel conversion */
rajathr 0:34ee385f4d2d 888 ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS_MORT;
rajathr 0:34ee385f4d2d 889 }
rajathr 0:34ee385f4d2d 890 else
rajathr 0:34ee385f4d2d 891 {
rajathr 0:34ee385f4d2d 892 /* Disable the selected ADC EOC rising on each regular channel conversion */
rajathr 0:34ee385f4d2d 893 ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS_MORT);
rajathr 0:34ee385f4d2d 894 }
rajathr 0:34ee385f4d2d 895 }
rajathr 0:34ee385f4d2d 896
rajathr 0:34ee385f4d2d 897 /**
rajathr 0:34ee385f4d2d 898 * @brief Enables or disables the ADC continuous conversion mode
rajathr 0:34ee385f4d2d 899 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 900 * @param NewState: new state of the selected ADC continuous conversion mode
rajathr 0:34ee385f4d2d 901 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 902 * @retval None
rajathr 0:34ee385f4d2d 903 */
rajathr 0:34ee385f4d2d 904 void ADC_ContinuousModeCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 905 {
rajathr 0:34ee385f4d2d 906 /* Check the parameters */
rajathr 0:34ee385f4d2d 907 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 908 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 909
rajathr 0:34ee385f4d2d 910 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 911 {
rajathr 0:34ee385f4d2d 912 /* Enable the selected ADC continuous conversion mode */
rajathr 0:34ee385f4d2d 913 ADCx->CR2 |= (uint32_t)ADC_CR2_CONT_MORT;
rajathr 0:34ee385f4d2d 914 }
rajathr 0:34ee385f4d2d 915 else
rajathr 0:34ee385f4d2d 916 {
rajathr 0:34ee385f4d2d 917 /* Disable the selected ADC continuous conversion mode */
rajathr 0:34ee385f4d2d 918 ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT_MORT);
rajathr 0:34ee385f4d2d 919 }
rajathr 0:34ee385f4d2d 920 }
rajathr 0:34ee385f4d2d 921
rajathr 0:34ee385f4d2d 922 /**
rajathr 0:34ee385f4d2d 923 * @brief Configures the discontinuous mode for the selected ADC regular group
rajathr 0:34ee385f4d2d 924 * channel.
rajathr 0:34ee385f4d2d 925 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 926 * @param Number: specifies the discontinuous mode regular channel count value.
rajathr 0:34ee385f4d2d 927 * This number must be between 1 and 8.
rajathr 0:34ee385f4d2d 928 * @retval None
rajathr 0:34ee385f4d2d 929 */
rajathr 0:34ee385f4d2d 930 void ADC_DiscModeChannelCountConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t Number)
rajathr 0:34ee385f4d2d 931 {
rajathr 0:34ee385f4d2d 932 uint32_t tmpreg1 = 0;
rajathr 0:34ee385f4d2d 933 uint32_t tmpreg2 = 0;
rajathr 0:34ee385f4d2d 934
rajathr 0:34ee385f4d2d 935 /* Check the parameters */
rajathr 0:34ee385f4d2d 936 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 937 assert_param(IS_ADC_REGULAR_DISC_NUMBER_MORT(Number));
rajathr 0:34ee385f4d2d 938
rajathr 0:34ee385f4d2d 939 /* Get the old register value */
rajathr 0:34ee385f4d2d 940 tmpreg1 = ADCx->CR1;
rajathr 0:34ee385f4d2d 941
rajathr 0:34ee385f4d2d 942 /* Clear the old discontinuous mode channel count */
rajathr 0:34ee385f4d2d 943 tmpreg1 &= CR1_DISCNUM_RESET;
rajathr 0:34ee385f4d2d 944
rajathr 0:34ee385f4d2d 945 /* Set the discontinuous mode channel count */
rajathr 0:34ee385f4d2d 946 tmpreg2 = Number - 1;
rajathr 0:34ee385f4d2d 947 tmpreg1 |= tmpreg2 << 13;
rajathr 0:34ee385f4d2d 948
rajathr 0:34ee385f4d2d 949 /* Store the new register value */
rajathr 0:34ee385f4d2d 950 ADCx->CR1 = tmpreg1;
rajathr 0:34ee385f4d2d 951 }
rajathr 0:34ee385f4d2d 952
rajathr 0:34ee385f4d2d 953 /**
rajathr 0:34ee385f4d2d 954 * @brief Enables or disables the discontinuous mode on regular group channel
rajathr 0:34ee385f4d2d 955 * for the specified ADC
rajathr 0:34ee385f4d2d 956 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 957 * @param NewState: new state of the selected ADC discontinuous mode on
rajathr 0:34ee385f4d2d 958 * regular group channel.
rajathr 0:34ee385f4d2d 959 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 960 * @retval None
rajathr 0:34ee385f4d2d 961 */
rajathr 0:34ee385f4d2d 962 void ADC_DiscModeCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 963 {
rajathr 0:34ee385f4d2d 964 /* Check the parameters */
rajathr 0:34ee385f4d2d 965 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 966 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 967
rajathr 0:34ee385f4d2d 968 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 969 {
rajathr 0:34ee385f4d2d 970 /* Enable the selected ADC regular discontinuous mode */
rajathr 0:34ee385f4d2d 971 ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN_MORT;
rajathr 0:34ee385f4d2d 972 }
rajathr 0:34ee385f4d2d 973 else
rajathr 0:34ee385f4d2d 974 {
rajathr 0:34ee385f4d2d 975 /* Disable the selected ADC regular discontinuous mode */
rajathr 0:34ee385f4d2d 976 ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN_MORT);
rajathr 0:34ee385f4d2d 977 }
rajathr 0:34ee385f4d2d 978 }
rajathr 0:34ee385f4d2d 979
rajathr 0:34ee385f4d2d 980 /**
rajathr 0:34ee385f4d2d 981 * @brief Returns the last ADCx conversion result data for regular channel.
rajathr 0:34ee385f4d2d 982 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 983 * @retval The Data conversion value.
rajathr 0:34ee385f4d2d 984 */
rajathr 0:34ee385f4d2d 985 uint16_t ADC_GetConversionValue_mort(ADC_TypeDef_mort* ADCx)
rajathr 0:34ee385f4d2d 986 {
rajathr 0:34ee385f4d2d 987 /* Check the parameters */
rajathr 0:34ee385f4d2d 988 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 989
rajathr 0:34ee385f4d2d 990 /* Return the selected ADC conversion value */
rajathr 0:34ee385f4d2d 991 return (uint16_t) ADCx->DR;
rajathr 0:34ee385f4d2d 992 }
rajathr 0:34ee385f4d2d 993
rajathr 0:34ee385f4d2d 994 /**
rajathr 0:34ee385f4d2d 995 * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results
rajathr 0:34ee385f4d2d 996 * data in the selected multi mode.
rajathr 0:34ee385f4d2d 997 * @param None
rajathr 0:34ee385f4d2d 998 * @retval The Data conversion value.
rajathr 0:34ee385f4d2d 999 * @note In dual mode, the value returned by this function is as following
rajathr 0:34ee385f4d2d 1000 * Data[15:0] : these bits contain the regular data of ADC1.
rajathr 0:34ee385f4d2d 1001 * Data[31:16]: these bits contain the regular data of ADC2.
rajathr 0:34ee385f4d2d 1002 * @note In triple mode, the value returned by this function is as following
rajathr 0:34ee385f4d2d 1003 * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2.
rajathr 0:34ee385f4d2d 1004 * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3.
rajathr 0:34ee385f4d2d 1005 */
rajathr 0:34ee385f4d2d 1006 uint32_t ADC_GetMultiModeConversionValue_mort(void)
rajathr 0:34ee385f4d2d 1007 {
rajathr 0:34ee385f4d2d 1008 /* Return the multi mode conversion value */
rajathr 0:34ee385f4d2d 1009 return (*(__IO uint32_t *) CDR_ADDRESS);
rajathr 0:34ee385f4d2d 1010 }
rajathr 0:34ee385f4d2d 1011 /**
rajathr 0:34ee385f4d2d 1012 * @}
rajathr 0:34ee385f4d2d 1013 */
rajathr 0:34ee385f4d2d 1014
rajathr 0:34ee385f4d2d 1015 /** @defgroup ADC_Group5 Regular Channels DMA Configuration functions
rajathr 0:34ee385f4d2d 1016 * @brief Regular Channels DMA Configuration functions
rajathr 0:34ee385f4d2d 1017 *
rajathr 0:34ee385f4d2d 1018 @verbatim
rajathr 0:34ee385f4d2d 1019 ===============================================================================
rajathr 0:34ee385f4d2d 1020 ##### Regular Channels DMA Configuration functions #####
rajathr 0:34ee385f4d2d 1021 ===============================================================================
rajathr 0:34ee385f4d2d 1022 [..] This section provides functions allowing to configure the DMA for ADC
rajathr 0:34ee385f4d2d 1023 regular channels.
rajathr 0:34ee385f4d2d 1024 Since converted regular channel values are stored into a unique data
rajathr 0:34ee385f4d2d 1025 register, it is useful to use DMA for conversion of more than one regular
rajathr 0:34ee385f4d2d 1026 channel. This avoids the loss of the data already stored in the ADC
rajathr 0:34ee385f4d2d 1027 Data register.
rajathr 0:34ee385f4d2d 1028 When the DMA mode is enabled (using the ADC_DMACmd() function), after each
rajathr 0:34ee385f4d2d 1029 conversion of a regular channel, a DMA request is generated.
rajathr 0:34ee385f4d2d 1030 [..] Depending on the "DMA disable selection for Independent ADC mode"
rajathr 0:34ee385f4d2d 1031 configuration (using the ADC_DMARequestAfterLastTransferCmd() function),
rajathr 0:34ee385f4d2d 1032 at the end of the last DMA transfer, two possibilities are allowed:
rajathr 0:34ee385f4d2d 1033 (+) No new DMA request is issued to the DMA controller (feature DISABLED)
rajathr 0:34ee385f4d2d 1034 (+) Requests can continue to be generated (feature ENABLED).
rajathr 0:34ee385f4d2d 1035 [..] Depending on the "DMA disable selection for multi ADC mode" configuration
rajathr 0:34ee385f4d2d 1036 (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function),
rajathr 0:34ee385f4d2d 1037 at the end of the last DMA transfer, two possibilities are allowed:
rajathr 0:34ee385f4d2d 1038 (+) No new DMA request is issued to the DMA controller (feature DISABLED)
rajathr 0:34ee385f4d2d 1039 (+) Requests can continue to be generated (feature ENABLED).
rajathr 0:34ee385f4d2d 1040
rajathr 0:34ee385f4d2d 1041 @endverbatim
rajathr 0:34ee385f4d2d 1042 * @{
rajathr 0:34ee385f4d2d 1043 */
rajathr 0:34ee385f4d2d 1044
rajathr 0:34ee385f4d2d 1045 /**
rajathr 0:34ee385f4d2d 1046 * @brief Enables or disables the specified ADC DMA request.
rajathr 0:34ee385f4d2d 1047 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1048 * @param NewState: new state of the selected ADC DMA transfer.
rajathr 0:34ee385f4d2d 1049 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 1050 * @retval None
rajathr 0:34ee385f4d2d 1051 */
rajathr 0:34ee385f4d2d 1052 void ADC_DMACmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 1053 {
rajathr 0:34ee385f4d2d 1054 /* Check the parameters */
rajathr 0:34ee385f4d2d 1055 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1056 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 1057 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 1058 {
rajathr 0:34ee385f4d2d 1059 /* Enable the selected ADC DMA request */
rajathr 0:34ee385f4d2d 1060 ADCx->CR2 |= (uint32_t)ADC_CR2_DMA_MORT;
rajathr 0:34ee385f4d2d 1061 }
rajathr 0:34ee385f4d2d 1062 else
rajathr 0:34ee385f4d2d 1063 {
rajathr 0:34ee385f4d2d 1064 /* Disable the selected ADC DMA request */
rajathr 0:34ee385f4d2d 1065 ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA_MORT);
rajathr 0:34ee385f4d2d 1066 }
rajathr 0:34ee385f4d2d 1067 }
rajathr 0:34ee385f4d2d 1068
rajathr 0:34ee385f4d2d 1069 /**
rajathr 0:34ee385f4d2d 1070 * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
rajathr 0:34ee385f4d2d 1071 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1072 * @param NewState: new state of the selected ADC DMA request after last transfer.
rajathr 0:34ee385f4d2d 1073 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 1074 * @retval None
rajathr 0:34ee385f4d2d 1075 */
rajathr 0:34ee385f4d2d 1076 void ADC_DMARequestAfterLastTransferCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 1077 {
rajathr 0:34ee385f4d2d 1078 /* Check the parameters */
rajathr 0:34ee385f4d2d 1079 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1080 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 1081 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 1082 {
rajathr 0:34ee385f4d2d 1083 /* Enable the selected ADC DMA request after last transfer */
rajathr 0:34ee385f4d2d 1084 ADCx->CR2 |= (uint32_t)ADC_CR2_DDS_MORT;
rajathr 0:34ee385f4d2d 1085 }
rajathr 0:34ee385f4d2d 1086 else
rajathr 0:34ee385f4d2d 1087 {
rajathr 0:34ee385f4d2d 1088 /* Disable the selected ADC DMA request after last transfer */
rajathr 0:34ee385f4d2d 1089 ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS_MORT);
rajathr 0:34ee385f4d2d 1090 }
rajathr 0:34ee385f4d2d 1091 }
rajathr 0:34ee385f4d2d 1092
rajathr 0:34ee385f4d2d 1093 /**
rajathr 0:34ee385f4d2d 1094 * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode
rajathr 0:34ee385f4d2d 1095 * @param NewState: new state of the selected ADC DMA request after last transfer.
rajathr 0:34ee385f4d2d 1096 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 1097 * @note if Enabled, DMA requests are issued as long as data are converted and
rajathr 0:34ee385f4d2d 1098 * DMA mode for multi ADC mode (selected using ADC_CommonInit() function
rajathr 0:34ee385f4d2d 1099 * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is
rajathr 0:34ee385f4d2d 1100 * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3.
rajathr 0:34ee385f4d2d 1101 * @retval None
rajathr 0:34ee385f4d2d 1102 */
rajathr 0:34ee385f4d2d 1103 void ADC_MultiModeDMARequestAfterLastTransferCmd_mort(FunctionalState NewState)
rajathr 0:34ee385f4d2d 1104 {
rajathr 0:34ee385f4d2d 1105 /* Check the parameters */
rajathr 0:34ee385f4d2d 1106 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 1107 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 1108 {
rajathr 0:34ee385f4d2d 1109 /* Enable the selected ADC DMA request after last transfer */
rajathr 0:34ee385f4d2d 1110 ADC->CCR |= (uint32_t)ADC_CCR_DDS_MORT;
rajathr 0:34ee385f4d2d 1111 }
rajathr 0:34ee385f4d2d 1112 else
rajathr 0:34ee385f4d2d 1113 {
rajathr 0:34ee385f4d2d 1114 /* Disable the selected ADC DMA request after last transfer */
rajathr 0:34ee385f4d2d 1115 ADC->CCR &= (uint32_t)(~ADC_CCR_DDS_MORT);
rajathr 0:34ee385f4d2d 1116 }
rajathr 0:34ee385f4d2d 1117 }
rajathr 0:34ee385f4d2d 1118 /**
rajathr 0:34ee385f4d2d 1119 * @}
rajathr 0:34ee385f4d2d 1120 */
rajathr 0:34ee385f4d2d 1121
rajathr 0:34ee385f4d2d 1122 /** @defgroup ADC_Group6 Injected channels Configuration functions
rajathr 0:34ee385f4d2d 1123 * @brief Injected channels Configuration functions
rajathr 0:34ee385f4d2d 1124 *
rajathr 0:34ee385f4d2d 1125 @verbatim
rajathr 0:34ee385f4d2d 1126 ===============================================================================
rajathr 0:34ee385f4d2d 1127 ##### Injected channels Configuration functions #####
rajathr 0:34ee385f4d2d 1128 ===============================================================================
rajathr 0:34ee385f4d2d 1129
rajathr 0:34ee385f4d2d 1130 [..] This section provide functions allowing to configure the ADC Injected channels,
rajathr 0:34ee385f4d2d 1131 it is composed of 2 sub sections :
rajathr 0:34ee385f4d2d 1132
rajathr 0:34ee385f4d2d 1133 (#) Configuration functions for Injected channels: This subsection provides
rajathr 0:34ee385f4d2d 1134 functions allowing to configure the ADC injected channels :
rajathr 0:34ee385f4d2d 1135 (++) Configure the rank in the injected group sequencer for each channel
rajathr 0:34ee385f4d2d 1136 (++) Configure the sampling time for each channel
rajathr 0:34ee385f4d2d 1137 (++) Activate the Auto injected Mode
rajathr 0:34ee385f4d2d 1138 (++) Activate the Discontinuous Mode
rajathr 0:34ee385f4d2d 1139 (++) scan mode activation
rajathr 0:34ee385f4d2d 1140 (++) External/software trigger source
rajathr 0:34ee385f4d2d 1141 (++) External trigger edge
rajathr 0:34ee385f4d2d 1142 (++) injected channels sequencer.
rajathr 0:34ee385f4d2d 1143
rajathr 0:34ee385f4d2d 1144 (#) Get the Specified Injected channel conversion data: This subsection
rajathr 0:34ee385f4d2d 1145 provides an important function in the ADC peripheral since it returns the
rajathr 0:34ee385f4d2d 1146 converted data of the specific injected channel.
rajathr 0:34ee385f4d2d 1147
rajathr 0:34ee385f4d2d 1148 @endverbatim
rajathr 0:34ee385f4d2d 1149 * @{
rajathr 0:34ee385f4d2d 1150 */
rajathr 0:34ee385f4d2d 1151 /**
rajathr 0:34ee385f4d2d 1152 * @brief Configures for the selected ADC injected channel its corresponding
rajathr 0:34ee385f4d2d 1153 * rank in the sequencer and its sample time.
rajathr 0:34ee385f4d2d 1154 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1155 * @param ADC_Channel: the ADC channel to configure.
rajathr 0:34ee385f4d2d 1156 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1157 * @arg ADC_Channel_0: ADC Channel0 selected
rajathr 0:34ee385f4d2d 1158 * @arg ADC_Channel_1: ADC Channel1 selected
rajathr 0:34ee385f4d2d 1159 * @arg ADC_Channel_2: ADC Channel2 selected
rajathr 0:34ee385f4d2d 1160 * @arg ADC_Channel_3: ADC Channel3 selected
rajathr 0:34ee385f4d2d 1161 * @arg ADC_Channel_4: ADC Channel4 selected
rajathr 0:34ee385f4d2d 1162 * @arg ADC_Channel_5: ADC Channel5 selected
rajathr 0:34ee385f4d2d 1163 * @arg ADC_Channel_6: ADC Channel6 selected
rajathr 0:34ee385f4d2d 1164 * @arg ADC_Channel_7: ADC Channel7 selected
rajathr 0:34ee385f4d2d 1165 * @arg ADC_Channel_8: ADC Channel8 selected
rajathr 0:34ee385f4d2d 1166 * @arg ADC_Channel_9: ADC Channel9 selected
rajathr 0:34ee385f4d2d 1167 * @arg ADC_Channel_10: ADC Channel10 selected
rajathr 0:34ee385f4d2d 1168 * @arg ADC_Channel_11: ADC Channel11 selected
rajathr 0:34ee385f4d2d 1169 * @arg ADC_Channel_12: ADC Channel12 selected
rajathr 0:34ee385f4d2d 1170 * @arg ADC_Channel_13: ADC Channel13 selected
rajathr 0:34ee385f4d2d 1171 * @arg ADC_Channel_14: ADC Channel14 selected
rajathr 0:34ee385f4d2d 1172 * @arg ADC_Channel_15: ADC Channel15 selected
rajathr 0:34ee385f4d2d 1173 * @arg ADC_Channel_16: ADC Channel16 selected
rajathr 0:34ee385f4d2d 1174 * @arg ADC_Channel_17: ADC Channel17 selected
rajathr 0:34ee385f4d2d 1175 * @arg ADC_Channel_18: ADC Channel18 selected
rajathr 0:34ee385f4d2d 1176 * @param Rank: The rank in the injected group sequencer.
rajathr 0:34ee385f4d2d 1177 * This parameter must be between 1 to 4.
rajathr 0:34ee385f4d2d 1178 * @param ADC_SampleTime: The sample time value to be set for the selected channel.
rajathr 0:34ee385f4d2d 1179 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1180 * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
rajathr 0:34ee385f4d2d 1181 * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
rajathr 0:34ee385f4d2d 1182 * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
rajathr 0:34ee385f4d2d 1183 * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
rajathr 0:34ee385f4d2d 1184 * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
rajathr 0:34ee385f4d2d 1185 * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
rajathr 0:34ee385f4d2d 1186 * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
rajathr 0:34ee385f4d2d 1187 * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
rajathr 0:34ee385f4d2d 1188 * @retval None
rajathr 0:34ee385f4d2d 1189 */
rajathr 0:34ee385f4d2d 1190 void ADC_InjectedChannelConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
rajathr 0:34ee385f4d2d 1191 {
rajathr 0:34ee385f4d2d 1192 uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
rajathr 0:34ee385f4d2d 1193 /* Check the parameters */
rajathr 0:34ee385f4d2d 1194 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1195 assert_param(IS_ADC_CHANNEL(ADC_Channel));
rajathr 0:34ee385f4d2d 1196 assert_param(IS_ADC_INJECTED_RANK_MORT(Rank));
rajathr 0:34ee385f4d2d 1197 assert_param(IS_ADC_SAMPLE_TIME_MORT(ADC_SampleTime));
rajathr 0:34ee385f4d2d 1198 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
rajathr 0:34ee385f4d2d 1199 if (ADC_Channel > ADC_Channel_9)
rajathr 0:34ee385f4d2d 1200 {
rajathr 0:34ee385f4d2d 1201 /* Get the old register value */
rajathr 0:34ee385f4d2d 1202 tmpreg1 = ADCx->SMPR1;
rajathr 0:34ee385f4d2d 1203 /* Calculate the mask to clear */
rajathr 0:34ee385f4d2d 1204 tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10));
rajathr 0:34ee385f4d2d 1205 /* Clear the old sample time */
rajathr 0:34ee385f4d2d 1206 tmpreg1 &= ~tmpreg2;
rajathr 0:34ee385f4d2d 1207 /* Calculate the mask to set */
rajathr 0:34ee385f4d2d 1208 tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
rajathr 0:34ee385f4d2d 1209 /* Set the new sample time */
rajathr 0:34ee385f4d2d 1210 tmpreg1 |= tmpreg2;
rajathr 0:34ee385f4d2d 1211 /* Store the new register value */
rajathr 0:34ee385f4d2d 1212 ADCx->SMPR1 = tmpreg1;
rajathr 0:34ee385f4d2d 1213 }
rajathr 0:34ee385f4d2d 1214 else /* ADC_Channel include in ADC_Channel_[0..9] */
rajathr 0:34ee385f4d2d 1215 {
rajathr 0:34ee385f4d2d 1216 /* Get the old register value */
rajathr 0:34ee385f4d2d 1217 tmpreg1 = ADCx->SMPR2;
rajathr 0:34ee385f4d2d 1218 /* Calculate the mask to clear */
rajathr 0:34ee385f4d2d 1219 tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
rajathr 0:34ee385f4d2d 1220 /* Clear the old sample time */
rajathr 0:34ee385f4d2d 1221 tmpreg1 &= ~tmpreg2;
rajathr 0:34ee385f4d2d 1222 /* Calculate the mask to set */
rajathr 0:34ee385f4d2d 1223 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
rajathr 0:34ee385f4d2d 1224 /* Set the new sample time */
rajathr 0:34ee385f4d2d 1225 tmpreg1 |= tmpreg2;
rajathr 0:34ee385f4d2d 1226 /* Store the new register value */
rajathr 0:34ee385f4d2d 1227 ADCx->SMPR2 = tmpreg1;
rajathr 0:34ee385f4d2d 1228 }
rajathr 0:34ee385f4d2d 1229 /* Rank configuration */
rajathr 0:34ee385f4d2d 1230 /* Get the old register value */
rajathr 0:34ee385f4d2d 1231 tmpreg1 = ADCx->JSQR;
rajathr 0:34ee385f4d2d 1232 /* Get JL value: Number = JL+1 */
rajathr 0:34ee385f4d2d 1233 tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;
rajathr 0:34ee385f4d2d 1234 /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
rajathr 0:34ee385f4d2d 1235 tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
rajathr 0:34ee385f4d2d 1236 /* Clear the old JSQx bits for the selected rank */
rajathr 0:34ee385f4d2d 1237 tmpreg1 &= ~tmpreg2;
rajathr 0:34ee385f4d2d 1238 /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
rajathr 0:34ee385f4d2d 1239 tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
rajathr 0:34ee385f4d2d 1240 /* Set the JSQx bits for the selected rank */
rajathr 0:34ee385f4d2d 1241 tmpreg1 |= tmpreg2;
rajathr 0:34ee385f4d2d 1242 /* Store the new register value */
rajathr 0:34ee385f4d2d 1243 ADCx->JSQR = tmpreg1;
rajathr 0:34ee385f4d2d 1244 }
rajathr 0:34ee385f4d2d 1245
rajathr 0:34ee385f4d2d 1246 /**
rajathr 0:34ee385f4d2d 1247 * @brief Configures the sequencer length for injected channels
rajathr 0:34ee385f4d2d 1248 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1249 * @param Length: The sequencer length.
rajathr 0:34ee385f4d2d 1250 * This parameter must be a number between 1 to 4.
rajathr 0:34ee385f4d2d 1251 * @retval None
rajathr 0:34ee385f4d2d 1252 */
rajathr 0:34ee385f4d2d 1253 void ADC_InjectedSequencerLengthConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t Length)
rajathr 0:34ee385f4d2d 1254 {
rajathr 0:34ee385f4d2d 1255 uint32_t tmpreg1 = 0;
rajathr 0:34ee385f4d2d 1256 uint32_t tmpreg2 = 0;
rajathr 0:34ee385f4d2d 1257 /* Check the parameters */
rajathr 0:34ee385f4d2d 1258 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1259 assert_param(IS_ADC_INJECTED_LENGTH_MORT(Length));
rajathr 0:34ee385f4d2d 1260
rajathr 0:34ee385f4d2d 1261 /* Get the old register value */
rajathr 0:34ee385f4d2d 1262 tmpreg1 = ADCx->JSQR;
rajathr 0:34ee385f4d2d 1263
rajathr 0:34ee385f4d2d 1264 /* Clear the old injected sequence length JL bits */
rajathr 0:34ee385f4d2d 1265 tmpreg1 &= JSQR_JL_RESET;
rajathr 0:34ee385f4d2d 1266
rajathr 0:34ee385f4d2d 1267 /* Set the injected sequence length JL bits */
rajathr 0:34ee385f4d2d 1268 tmpreg2 = Length - 1;
rajathr 0:34ee385f4d2d 1269 tmpreg1 |= tmpreg2 << 20;
rajathr 0:34ee385f4d2d 1270
rajathr 0:34ee385f4d2d 1271 /* Store the new register value */
rajathr 0:34ee385f4d2d 1272 ADCx->JSQR = tmpreg1;
rajathr 0:34ee385f4d2d 1273 }
rajathr 0:34ee385f4d2d 1274
rajathr 0:34ee385f4d2d 1275 /**
rajathr 0:34ee385f4d2d 1276 * @brief Set the injected channels conversion value offset
rajathr 0:34ee385f4d2d 1277 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1278 * @param ADC_InjectedChannel: the ADC injected channel to set its offset.
rajathr 0:34ee385f4d2d 1279 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1280 * @arg ADC_InjectedChannel_1: Injected Channel1 selected
rajathr 0:34ee385f4d2d 1281 * @arg ADC_InjectedChannel_2: Injected Channel2 selected
rajathr 0:34ee385f4d2d 1282 * @arg ADC_InjectedChannel_3: Injected Channel3 selected
rajathr 0:34ee385f4d2d 1283 * @arg ADC_InjectedChannel_4: Injected Channel4 selected
rajathr 0:34ee385f4d2d 1284 * @param Offset: the offset value for the selected ADC injected channel
rajathr 0:34ee385f4d2d 1285 * This parameter must be a 12bit value.
rajathr 0:34ee385f4d2d 1286 * @retval None
rajathr 0:34ee385f4d2d 1287 */
rajathr 0:34ee385f4d2d 1288 void ADC_SetInjectedOffset_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
rajathr 0:34ee385f4d2d 1289 {
rajathr 0:34ee385f4d2d 1290 __IO uint32_t tmp = 0;
rajathr 0:34ee385f4d2d 1291 /* Check the parameters */
rajathr 0:34ee385f4d2d 1292 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1293 assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
rajathr 0:34ee385f4d2d 1294 assert_param(IS_ADC_OFFSET(Offset));
rajathr 0:34ee385f4d2d 1295
rajathr 0:34ee385f4d2d 1296 tmp = (uint32_t)ADCx;
rajathr 0:34ee385f4d2d 1297 tmp += ADC_InjectedChannel;
rajathr 0:34ee385f4d2d 1298
rajathr 0:34ee385f4d2d 1299 /* Set the selected injected channel data offset */
rajathr 0:34ee385f4d2d 1300 *(__IO uint32_t *) tmp = (uint32_t)Offset;
rajathr 0:34ee385f4d2d 1301 }
rajathr 0:34ee385f4d2d 1302
rajathr 0:34ee385f4d2d 1303 /**
rajathr 0:34ee385f4d2d 1304 * @brief Configures the ADCx external trigger for injected channels conversion.
rajathr 0:34ee385f4d2d 1305 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1306 * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
rajathr 0:34ee385f4d2d 1307 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1308 * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected
rajathr 0:34ee385f4d2d 1309 * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected
rajathr 0:34ee385f4d2d 1310 * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected
rajathr 0:34ee385f4d2d 1311 * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected
rajathr 0:34ee385f4d2d 1312 * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected
rajathr 0:34ee385f4d2d 1313 * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected
rajathr 0:34ee385f4d2d 1314 * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected
rajathr 0:34ee385f4d2d 1315 * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected
rajathr 0:34ee385f4d2d 1316 * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected
rajathr 0:34ee385f4d2d 1317 * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected
rajathr 0:34ee385f4d2d 1318 * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected
rajathr 0:34ee385f4d2d 1319 * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected
rajathr 0:34ee385f4d2d 1320 * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected
rajathr 0:34ee385f4d2d 1321 * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected
rajathr 0:34ee385f4d2d 1322 * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected
rajathr 0:34ee385f4d2d 1323 * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected
rajathr 0:34ee385f4d2d 1324 * @retval None
rajathr 0:34ee385f4d2d 1325 */
rajathr 0:34ee385f4d2d 1326 void ADC_ExternalTrigInjectedConvConfig_mort(ADC_TypeDef_mort* ADCx, uint32_t ADC_ExternalTrigInjecConv)
rajathr 0:34ee385f4d2d 1327 {
rajathr 0:34ee385f4d2d 1328 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1329 /* Check the parameters */
rajathr 0:34ee385f4d2d 1330 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1331 assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
rajathr 0:34ee385f4d2d 1332
rajathr 0:34ee385f4d2d 1333 /* Get the old register value */
rajathr 0:34ee385f4d2d 1334 tmpreg = ADCx->CR2;
rajathr 0:34ee385f4d2d 1335
rajathr 0:34ee385f4d2d 1336 /* Clear the old external event selection for injected group */
rajathr 0:34ee385f4d2d 1337 tmpreg &= CR2_JEXTSEL_RESET;
rajathr 0:34ee385f4d2d 1338
rajathr 0:34ee385f4d2d 1339 /* Set the external event selection for injected group */
rajathr 0:34ee385f4d2d 1340 tmpreg |= ADC_ExternalTrigInjecConv;
rajathr 0:34ee385f4d2d 1341
rajathr 0:34ee385f4d2d 1342 /* Store the new register value */
rajathr 0:34ee385f4d2d 1343 ADCx->CR2 = tmpreg;
rajathr 0:34ee385f4d2d 1344 }
rajathr 0:34ee385f4d2d 1345
rajathr 0:34ee385f4d2d 1346 /**
rajathr 0:34ee385f4d2d 1347 * @brief Configures the ADCx external trigger edge for injected channels conversion.
rajathr 0:34ee385f4d2d 1348 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1349 * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge
rajathr 0:34ee385f4d2d 1350 * to start injected conversion.
rajathr 0:34ee385f4d2d 1351 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1352 * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for
rajathr 0:34ee385f4d2d 1353 * injected conversion
rajathr 0:34ee385f4d2d 1354 * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge
rajathr 0:34ee385f4d2d 1355 * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge
rajathr 0:34ee385f4d2d 1356 * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising
rajathr 0:34ee385f4d2d 1357 * and falling edge
rajathr 0:34ee385f4d2d 1358 * @retval None
rajathr 0:34ee385f4d2d 1359 */
rajathr 0:34ee385f4d2d 1360 void ADC_ExternalTrigInjectedConvEdgeConfig_mort(ADC_TypeDef_mort* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
rajathr 0:34ee385f4d2d 1361 {
rajathr 0:34ee385f4d2d 1362 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1363 /* Check the parameters */
rajathr 0:34ee385f4d2d 1364 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1365 assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE_MORT(ADC_ExternalTrigInjecConvEdge));
rajathr 0:34ee385f4d2d 1366 /* Get the old register value */
rajathr 0:34ee385f4d2d 1367 tmpreg = ADCx->CR2;
rajathr 0:34ee385f4d2d 1368 /* Clear the old external trigger edge for injected group */
rajathr 0:34ee385f4d2d 1369 tmpreg &= CR2_JEXTEN_RESET;
rajathr 0:34ee385f4d2d 1370 /* Set the new external trigger edge for injected group */
rajathr 0:34ee385f4d2d 1371 tmpreg |= ADC_ExternalTrigInjecConvEdge;
rajathr 0:34ee385f4d2d 1372 /* Store the new register value */
rajathr 0:34ee385f4d2d 1373 ADCx->CR2 = tmpreg;
rajathr 0:34ee385f4d2d 1374 }
rajathr 0:34ee385f4d2d 1375
rajathr 0:34ee385f4d2d 1376 /**
rajathr 0:34ee385f4d2d 1377 * @brief Enables the selected ADC software start conversion of the injected channels.
rajathr 0:34ee385f4d2d 1378 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1379 * @retval None
rajathr 0:34ee385f4d2d 1380 */
rajathr 0:34ee385f4d2d 1381 void ADC_SoftwareStartInjectedConv_mort(ADC_TypeDef_mort* ADCx)
rajathr 0:34ee385f4d2d 1382 {
rajathr 0:34ee385f4d2d 1383 /* Check the parameters */
rajathr 0:34ee385f4d2d 1384 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1385 /* Enable the selected ADC conversion for injected group */
rajathr 0:34ee385f4d2d 1386 ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART_MORT;
rajathr 0:34ee385f4d2d 1387 }
rajathr 0:34ee385f4d2d 1388
rajathr 0:34ee385f4d2d 1389 /**
rajathr 0:34ee385f4d2d 1390 * @brief Gets the selected ADC Software start injected conversion Status.
rajathr 0:34ee385f4d2d 1391 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1392 * @retval The new state of ADC software start injected conversion (SET or RESET).
rajathr 0:34ee385f4d2d 1393 */
rajathr 0:34ee385f4d2d 1394 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus_mort(ADC_TypeDef_mort* ADCx)
rajathr 0:34ee385f4d2d 1395 {
rajathr 0:34ee385f4d2d 1396 FlagStatus bitstatus = RESET;
rajathr 0:34ee385f4d2d 1397 /* Check the parameters */
rajathr 0:34ee385f4d2d 1398 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1399
rajathr 0:34ee385f4d2d 1400 /* Check the status of JSWSTART bit */
rajathr 0:34ee385f4d2d 1401 if ((ADCx->CR2 & ADC_CR2_JSWSTART_MORT) != (uint32_t)RESET)
rajathr 0:34ee385f4d2d 1402 {
rajathr 0:34ee385f4d2d 1403 /* JSWSTART bit is set */
rajathr 0:34ee385f4d2d 1404 bitstatus = SET;
rajathr 0:34ee385f4d2d 1405 }
rajathr 0:34ee385f4d2d 1406 else
rajathr 0:34ee385f4d2d 1407 {
rajathr 0:34ee385f4d2d 1408 /* JSWSTART bit is reset */
rajathr 0:34ee385f4d2d 1409 bitstatus = RESET;
rajathr 0:34ee385f4d2d 1410 }
rajathr 0:34ee385f4d2d 1411 /* Return the JSWSTART bit status */
rajathr 0:34ee385f4d2d 1412 return bitstatus;
rajathr 0:34ee385f4d2d 1413 }
rajathr 0:34ee385f4d2d 1414
rajathr 0:34ee385f4d2d 1415 /**
rajathr 0:34ee385f4d2d 1416 * @brief Enables or disables the selected ADC automatic injected group
rajathr 0:34ee385f4d2d 1417 * conversion after regular one.
rajathr 0:34ee385f4d2d 1418 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1419 * @param NewState: new state of the selected ADC auto injected conversion
rajathr 0:34ee385f4d2d 1420 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 1421 * @retval None
rajathr 0:34ee385f4d2d 1422 */
rajathr 0:34ee385f4d2d 1423 void ADC_AutoInjectedConvCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 1424 {
rajathr 0:34ee385f4d2d 1425 /* Check the parameters */
rajathr 0:34ee385f4d2d 1426 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1427 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 1428 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 1429 {
rajathr 0:34ee385f4d2d 1430 /* Enable the selected ADC automatic injected group conversion */
rajathr 0:34ee385f4d2d 1431 ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO_MORT;
rajathr 0:34ee385f4d2d 1432 }
rajathr 0:34ee385f4d2d 1433 else
rajathr 0:34ee385f4d2d 1434 {
rajathr 0:34ee385f4d2d 1435 /* Disable the selected ADC automatic injected group conversion */
rajathr 0:34ee385f4d2d 1436 ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO_MORT);
rajathr 0:34ee385f4d2d 1437 }
rajathr 0:34ee385f4d2d 1438 }
rajathr 0:34ee385f4d2d 1439
rajathr 0:34ee385f4d2d 1440 /**
rajathr 0:34ee385f4d2d 1441 * @brief Enables or disables the discontinuous mode for injected group
rajathr 0:34ee385f4d2d 1442 * channel for the specified ADC
rajathr 0:34ee385f4d2d 1443 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1444 * @param NewState: new state of the selected ADC discontinuous mode on injected
rajathr 0:34ee385f4d2d 1445 * group channel.
rajathr 0:34ee385f4d2d 1446 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 1447 * @retval None
rajathr 0:34ee385f4d2d 1448 */
rajathr 0:34ee385f4d2d 1449 void ADC_InjectedDiscModeCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 1450 {
rajathr 0:34ee385f4d2d 1451 /* Check the parameters */
rajathr 0:34ee385f4d2d 1452 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1453 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 1454 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 1455 {
rajathr 0:34ee385f4d2d 1456 /* Enable the selected ADC injected discontinuous mode */
rajathr 0:34ee385f4d2d 1457 ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN_MORT;
rajathr 0:34ee385f4d2d 1458 }
rajathr 0:34ee385f4d2d 1459 else
rajathr 0:34ee385f4d2d 1460 {
rajathr 0:34ee385f4d2d 1461 /* Disable the selected ADC injected discontinuous mode */
rajathr 0:34ee385f4d2d 1462 ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN_MORT);
rajathr 0:34ee385f4d2d 1463 }
rajathr 0:34ee385f4d2d 1464 }
rajathr 0:34ee385f4d2d 1465
rajathr 0:34ee385f4d2d 1466 /**
rajathr 0:34ee385f4d2d 1467 * @brief Returns the ADC injected channel conversion result
rajathr 0:34ee385f4d2d 1468 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1469 * @param ADC_InjectedChannel: the converted ADC injected channel.
rajathr 0:34ee385f4d2d 1470 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1471 * @arg ADC_InjectedChannel_1: Injected Channel1 selected
rajathr 0:34ee385f4d2d 1472 * @arg ADC_InjectedChannel_2: Injected Channel2 selected
rajathr 0:34ee385f4d2d 1473 * @arg ADC_InjectedChannel_3: Injected Channel3 selected
rajathr 0:34ee385f4d2d 1474 * @arg ADC_InjectedChannel_4: Injected Channel4 selected
rajathr 0:34ee385f4d2d 1475 * @retval The Data conversion value.
rajathr 0:34ee385f4d2d 1476 */
rajathr 0:34ee385f4d2d 1477 uint16_t ADC_GetInjectedConversionValue_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_InjectedChannel)
rajathr 0:34ee385f4d2d 1478 {
rajathr 0:34ee385f4d2d 1479 __IO uint32_t tmp = 0;
rajathr 0:34ee385f4d2d 1480
rajathr 0:34ee385f4d2d 1481 /* Check the parameters */
rajathr 0:34ee385f4d2d 1482 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1483 assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
rajathr 0:34ee385f4d2d 1484
rajathr 0:34ee385f4d2d 1485 tmp = (uint32_t)ADCx;
rajathr 0:34ee385f4d2d 1486 tmp += ADC_InjectedChannel + JDR_OFFSET;
rajathr 0:34ee385f4d2d 1487
rajathr 0:34ee385f4d2d 1488 /* Returns the selected injected channel conversion data value */
rajathr 0:34ee385f4d2d 1489 return (uint16_t) (*(__IO uint32_t*) tmp);
rajathr 0:34ee385f4d2d 1490 }
rajathr 0:34ee385f4d2d 1491 /**
rajathr 0:34ee385f4d2d 1492 * @}
rajathr 0:34ee385f4d2d 1493 */
rajathr 0:34ee385f4d2d 1494
rajathr 0:34ee385f4d2d 1495 /** @defgroup ADC_Group7 Interrupts and flags management functions
rajathr 0:34ee385f4d2d 1496 * @brief Interrupts and flags management functions
rajathr 0:34ee385f4d2d 1497 *
rajathr 0:34ee385f4d2d 1498 @verbatim
rajathr 0:34ee385f4d2d 1499 ===============================================================================
rajathr 0:34ee385f4d2d 1500 ##### Interrupts and flags management functions #####
rajathr 0:34ee385f4d2d 1501 ===============================================================================
rajathr 0:34ee385f4d2d 1502
rajathr 0:34ee385f4d2d 1503 [..] This section provides functions allowing to configure the ADC Interrupts
rajathr 0:34ee385f4d2d 1504 and to get the status and clear flags and Interrupts pending bits.
rajathr 0:34ee385f4d2d 1505
rajathr 0:34ee385f4d2d 1506 [..] Each ADC provides 4 Interrupts sources and 6 Flags which can be divided
rajathr 0:34ee385f4d2d 1507 into 3 groups:
rajathr 0:34ee385f4d2d 1508
rajathr 0:34ee385f4d2d 1509 *** Flags and Interrupts for ADC regular channels ***
rajathr 0:34ee385f4d2d 1510 =====================================================
rajathr 0:34ee385f4d2d 1511 [..]
rajathr 0:34ee385f4d2d 1512 (+) Flags :
rajathr 0:34ee385f4d2d 1513 (##) ADC_FLAG_OVR_MORT : Overrun detection when regular converted data are lost
rajathr 0:34ee385f4d2d 1514
rajathr 0:34ee385f4d2d 1515 (##) ADC_FLAG_EOC_MORT : Regular channel end of conversion ==> to indicate
rajathr 0:34ee385f4d2d 1516 (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() )
rajathr 0:34ee385f4d2d 1517 the end of:
rajathr 0:34ee385f4d2d 1518 (+++) a regular CHANNEL conversion
rajathr 0:34ee385f4d2d 1519 (+++) sequence of regular GROUP conversions .
rajathr 0:34ee385f4d2d 1520
rajathr 0:34ee385f4d2d 1521 (##) ADC_FLAG_STRT_MORT: Regular channel start ==> to indicate when regular
rajathr 0:34ee385f4d2d 1522 CHANNEL conversion starts.
rajathr 0:34ee385f4d2d 1523 [..]
rajathr 0:34ee385f4d2d 1524 (+) Interrupts :
rajathr 0:34ee385f4d2d 1525 (##) ADC_IT_OVR_MORT : specifies the interrupt source for Overrun detection
rajathr 0:34ee385f4d2d 1526 event.
rajathr 0:34ee385f4d2d 1527 (##) ADC_IT_EOC_MORT : specifies the interrupt source for Regular channel end
rajathr 0:34ee385f4d2d 1528 of conversion event.
rajathr 0:34ee385f4d2d 1529
rajathr 0:34ee385f4d2d 1530
rajathr 0:34ee385f4d2d 1531 *** Flags and Interrupts for ADC Injected channels ***
rajathr 0:34ee385f4d2d 1532 ======================================================
rajathr 0:34ee385f4d2d 1533 [..]
rajathr 0:34ee385f4d2d 1534 (+) Flags :
rajathr 0:34ee385f4d2d 1535 (##) ADC_FLAG_JEOC_MORT : Injected channel end of conversion ==> to indicate
rajathr 0:34ee385f4d2d 1536 at the end of injected GROUP conversion
rajathr 0:34ee385f4d2d 1537
rajathr 0:34ee385f4d2d 1538 (##) ADC_FLAG_JSTRT_MORT: Injected channel start ==> to indicate hardware when
rajathr 0:34ee385f4d2d 1539 injected GROUP conversion starts.
rajathr 0:34ee385f4d2d 1540 [..]
rajathr 0:34ee385f4d2d 1541 (+) Interrupts :
rajathr 0:34ee385f4d2d 1542 (##) ADC_IT_JEOC_MORT : specifies the interrupt source for Injected channel
rajathr 0:34ee385f4d2d 1543 end of conversion event.
rajathr 0:34ee385f4d2d 1544
rajathr 0:34ee385f4d2d 1545 *** General Flags and Interrupts for the ADC ***
rajathr 0:34ee385f4d2d 1546 ================================================
rajathr 0:34ee385f4d2d 1547 [..]
rajathr 0:34ee385f4d2d 1548 (+)Flags :
rajathr 0:34ee385f4d2d 1549 (##) ADC_FLAG_AWD_MORT: Analog watchdog ==> to indicate if the converted voltage
rajathr 0:34ee385f4d2d 1550 crosses the programmed thresholds values.
rajathr 0:34ee385f4d2d 1551 [..]
rajathr 0:34ee385f4d2d 1552 (+) Interrupts :
rajathr 0:34ee385f4d2d 1553 (##) ADC_IT_AWD_MORT : specifies the interrupt source for Analog watchdog event.
rajathr 0:34ee385f4d2d 1554
rajathr 0:34ee385f4d2d 1555
rajathr 0:34ee385f4d2d 1556 [..] The user should identify which mode will be used in his application to
rajathr 0:34ee385f4d2d 1557 manage the ADC controller events: Polling mode or Interrupt mode.
rajathr 0:34ee385f4d2d 1558
rajathr 0:34ee385f4d2d 1559 [..] In the Polling Mode it is advised to use the following functions:
rajathr 0:34ee385f4d2d 1560 (+) ADC_GetFlagStatus() : to check if flags events occur.
rajathr 0:34ee385f4d2d 1561 (+) ADC_ClearFlag() : to clear the flags events.
rajathr 0:34ee385f4d2d 1562
rajathr 0:34ee385f4d2d 1563 [..] In the Interrupt Mode it is advised to use the following functions:
rajathr 0:34ee385f4d2d 1564 (+) ADC_ITConfig() : to enable or disable the interrupt source.
rajathr 0:34ee385f4d2d 1565 (+) ADC_GetITStatus() : to check if Interrupt occurs.
rajathr 0:34ee385f4d2d 1566 (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
rajathr 0:34ee385f4d2d 1567 (corresponding Flag).
rajathr 0:34ee385f4d2d 1568 @endverbatim
rajathr 0:34ee385f4d2d 1569 * @{
rajathr 0:34ee385f4d2d 1570 */
rajathr 0:34ee385f4d2d 1571 /**
rajathr 0:34ee385f4d2d 1572 * @brief Enables or disables the specified ADC interrupts.
rajathr 0:34ee385f4d2d 1573 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1574 * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
rajathr 0:34ee385f4d2d 1575 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1576 * @arg ADC_IT_EOC_MORT: End of conversion interrupt mask
rajathr 0:34ee385f4d2d 1577 * @arg ADC_IT_AWD_MORT: Analog watchdog interrupt mask
rajathr 0:34ee385f4d2d 1578 * @arg ADC_IT_JEOC_MORT: End of injected conversion interrupt mask
rajathr 0:34ee385f4d2d 1579 * @arg ADC_IT_OVR_MORT: Overrun interrupt enable
rajathr 0:34ee385f4d2d 1580 * @param NewState: new state of the specified ADC interrupts.
rajathr 0:34ee385f4d2d 1581 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 1582 * @retval None
rajathr 0:34ee385f4d2d 1583 */
rajathr 0:34ee385f4d2d 1584 void ADC_ITConfig_mort(ADC_TypeDef_mort* ADCx, uint16_t ADC_IT, FunctionalState NewState)
rajathr 0:34ee385f4d2d 1585 {
rajathr 0:34ee385f4d2d 1586 uint32_t itmask = 0;
rajathr 0:34ee385f4d2d 1587 /* Check the parameters */
rajathr 0:34ee385f4d2d 1588 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1589 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 1590 assert_param(IS_ADC_IT(ADC_IT));
rajathr 0:34ee385f4d2d 1591
rajathr 0:34ee385f4d2d 1592 /* Get the ADC IT index */
rajathr 0:34ee385f4d2d 1593 itmask = (uint8_t)ADC_IT;
rajathr 0:34ee385f4d2d 1594 itmask = (uint32_t)0x01 << itmask;
rajathr 0:34ee385f4d2d 1595
rajathr 0:34ee385f4d2d 1596 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 1597 {
rajathr 0:34ee385f4d2d 1598 /* Enable the selected ADC interrupts */
rajathr 0:34ee385f4d2d 1599 ADCx->CR1 |= itmask;
rajathr 0:34ee385f4d2d 1600 }
rajathr 0:34ee385f4d2d 1601 else
rajathr 0:34ee385f4d2d 1602 {
rajathr 0:34ee385f4d2d 1603 /* Disable the selected ADC interrupts */
rajathr 0:34ee385f4d2d 1604 ADCx->CR1 &= (~(uint32_t)itmask);
rajathr 0:34ee385f4d2d 1605 }
rajathr 0:34ee385f4d2d 1606 }
rajathr 0:34ee385f4d2d 1607
rajathr 0:34ee385f4d2d 1608 /**
rajathr 0:34ee385f4d2d 1609 * @brief Checks whether the specified ADC flag is set or not.
rajathr 0:34ee385f4d2d 1610 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1611 * @param ADC_FLAG: specifies the flag to check.
rajathr 0:34ee385f4d2d 1612 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1613 * @arg ADC_FLAG_AWD_MORT: Analog watchdog flag
rajathr 0:34ee385f4d2d 1614 * @arg ADC_FLAG_EOC_MORT: End of conversion flag
rajathr 0:34ee385f4d2d 1615 * @arg ADC_FLAG_JEOC_MORT: End of injected group conversion flag
rajathr 0:34ee385f4d2d 1616 * @arg ADC_FLAG_JSTRT_MORT: Start of injected group conversion flag
rajathr 0:34ee385f4d2d 1617 * @arg ADC_FLAG_STRT_MORT: Start of regular group conversion flag
rajathr 0:34ee385f4d2d 1618 * @arg ADC_FLAG_OVR_MORT: Overrun flag
rajathr 0:34ee385f4d2d 1619 * @retval The new state of ADC_FLAG (SET or RESET).
rajathr 0:34ee385f4d2d 1620 */
rajathr 0:34ee385f4d2d 1621 FlagStatus ADC_GetFlagStatus_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_FLAG)
rajathr 0:34ee385f4d2d 1622 {
rajathr 0:34ee385f4d2d 1623 FlagStatus bitstatus = RESET;
rajathr 0:34ee385f4d2d 1624 /* Check the parameters */
rajathr 0:34ee385f4d2d 1625 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1626 assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
rajathr 0:34ee385f4d2d 1627
rajathr 0:34ee385f4d2d 1628 /* Check the status of the specified ADC flag */
rajathr 0:34ee385f4d2d 1629 if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
rajathr 0:34ee385f4d2d 1630 {
rajathr 0:34ee385f4d2d 1631 /* ADC_FLAG is set */
rajathr 0:34ee385f4d2d 1632 bitstatus = SET;
rajathr 0:34ee385f4d2d 1633 }
rajathr 0:34ee385f4d2d 1634 else
rajathr 0:34ee385f4d2d 1635 {
rajathr 0:34ee385f4d2d 1636 /* ADC_FLAG is reset */
rajathr 0:34ee385f4d2d 1637 bitstatus = RESET;
rajathr 0:34ee385f4d2d 1638 }
rajathr 0:34ee385f4d2d 1639 /* Return the ADC_FLAG status */
rajathr 0:34ee385f4d2d 1640 return bitstatus;
rajathr 0:34ee385f4d2d 1641 }
rajathr 0:34ee385f4d2d 1642
rajathr 0:34ee385f4d2d 1643 /**
rajathr 0:34ee385f4d2d 1644 * @brief Clears the ADCx's pending flags.
rajathr 0:34ee385f4d2d 1645 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1646 * @param ADC_FLAG: specifies the flag to clear.
rajathr 0:34ee385f4d2d 1647 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 1648 * @arg ADC_FLAG_AWD_MORT: Analog watchdog flag
rajathr 0:34ee385f4d2d 1649 * @arg ADC_FLAG_EOC_MORT: End of conversion flag
rajathr 0:34ee385f4d2d 1650 * @arg ADC_FLAG_JEOC_MORT: End of injected group conversion flag
rajathr 0:34ee385f4d2d 1651 * @arg ADC_FLAG_JSTRT_MORT: Start of injected group conversion flag
rajathr 0:34ee385f4d2d 1652 * @arg ADC_FLAG_STRT_MORT: Start of regular group conversion flag
rajathr 0:34ee385f4d2d 1653 * @arg ADC_FLAG_OVR_MORT: Overrun flag
rajathr 0:34ee385f4d2d 1654 * @retval None
rajathr 0:34ee385f4d2d 1655 */
rajathr 0:34ee385f4d2d 1656 void ADC_ClearFlag_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_FLAG)
rajathr 0:34ee385f4d2d 1657 {
rajathr 0:34ee385f4d2d 1658 /* Check the parameters */
rajathr 0:34ee385f4d2d 1659 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1660 assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
rajathr 0:34ee385f4d2d 1661
rajathr 0:34ee385f4d2d 1662 /* Clear the selected ADC flags */
rajathr 0:34ee385f4d2d 1663 ADCx->SR = ~(uint32_t)ADC_FLAG;
rajathr 0:34ee385f4d2d 1664 }
rajathr 0:34ee385f4d2d 1665
rajathr 0:34ee385f4d2d 1666 /**
rajathr 0:34ee385f4d2d 1667 * @brief Checks whether the specified ADC interrupt has occurred or not.
rajathr 0:34ee385f4d2d 1668 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1669 * @param ADC_IT: specifies the ADC interrupt source to check.
rajathr 0:34ee385f4d2d 1670 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1671 * @arg ADC_IT_EOC_MORT: End of conversion interrupt mask
rajathr 0:34ee385f4d2d 1672 * @arg ADC_IT_AWD_MORT: Analog watchdog interrupt mask
rajathr 0:34ee385f4d2d 1673 * @arg ADC_IT_JEOC_MORT: End of injected conversion interrupt mask
rajathr 0:34ee385f4d2d 1674 * @arg ADC_IT_OVR_MORT: Overrun interrupt mask
rajathr 0:34ee385f4d2d 1675 * @retval The new state of ADC_IT (SET or RESET).
rajathr 0:34ee385f4d2d 1676 */
rajathr 0:34ee385f4d2d 1677 ITStatus ADC_GetITStatus_mort(ADC_TypeDef_mort* ADCx, uint16_t ADC_IT)
rajathr 0:34ee385f4d2d 1678 {
rajathr 0:34ee385f4d2d 1679 ITStatus bitstatus = RESET;
rajathr 0:34ee385f4d2d 1680 uint32_t itmask = 0, enablestatus = 0;
rajathr 0:34ee385f4d2d 1681
rajathr 0:34ee385f4d2d 1682 /* Check the parameters */
rajathr 0:34ee385f4d2d 1683 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1684 assert_param(IS_ADC_IT(ADC_IT));
rajathr 0:34ee385f4d2d 1685
rajathr 0:34ee385f4d2d 1686 /* Get the ADC IT index */
rajathr 0:34ee385f4d2d 1687 itmask = ADC_IT >> 8;
rajathr 0:34ee385f4d2d 1688
rajathr 0:34ee385f4d2d 1689 /* Get the ADC_IT enable bit status */
rajathr 0:34ee385f4d2d 1690 enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ;
rajathr 0:34ee385f4d2d 1691
rajathr 0:34ee385f4d2d 1692 /* Check the status of the specified ADC interrupt */
rajathr 0:34ee385f4d2d 1693 if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
rajathr 0:34ee385f4d2d 1694 {
rajathr 0:34ee385f4d2d 1695 /* ADC_IT is set */
rajathr 0:34ee385f4d2d 1696 bitstatus = SET;
rajathr 0:34ee385f4d2d 1697 }
rajathr 0:34ee385f4d2d 1698 else
rajathr 0:34ee385f4d2d 1699 {
rajathr 0:34ee385f4d2d 1700 /* ADC_IT is reset */
rajathr 0:34ee385f4d2d 1701 bitstatus = RESET;
rajathr 0:34ee385f4d2d 1702 }
rajathr 0:34ee385f4d2d 1703 /* Return the ADC_IT status */
rajathr 0:34ee385f4d2d 1704 return bitstatus;
rajathr 0:34ee385f4d2d 1705 }
rajathr 0:34ee385f4d2d 1706
rajathr 0:34ee385f4d2d 1707 /**
rajathr 0:34ee385f4d2d 1708 * @brief Clears the ADCx's interrupt pending bits.
rajathr 0:34ee385f4d2d 1709 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
rajathr 0:34ee385f4d2d 1710 * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
rajathr 0:34ee385f4d2d 1711 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1712 * @arg ADC_IT_EOC_MORT: End of conversion interrupt mask
rajathr 0:34ee385f4d2d 1713 * @arg ADC_IT_AWD_MORT: Analog watchdog interrupt mask
rajathr 0:34ee385f4d2d 1714 * @arg ADC_IT_JEOC_MORT: End of injected conversion interrupt mask
rajathr 0:34ee385f4d2d 1715 * @arg ADC_IT_OVR_MORT: Overrun interrupt mask
rajathr 0:34ee385f4d2d 1716 * @retval None
rajathr 0:34ee385f4d2d 1717 */
rajathr 0:34ee385f4d2d 1718 void ADC_ClearITPendingBit_mort(ADC_TypeDef_mort* ADCx, uint16_t ADC_IT)
rajathr 0:34ee385f4d2d 1719 {
rajathr 0:34ee385f4d2d 1720 uint8_t itmask = 0;
rajathr 0:34ee385f4d2d 1721 /* Check the parameters */
rajathr 0:34ee385f4d2d 1722 assert_param(IS_ADC_ALL_PERIPH(ADCx));
rajathr 0:34ee385f4d2d 1723 assert_param(IS_ADC_IT(ADC_IT));
rajathr 0:34ee385f4d2d 1724 /* Get the ADC IT index */
rajathr 0:34ee385f4d2d 1725 itmask = (uint8_t)(ADC_IT >> 8);
rajathr 0:34ee385f4d2d 1726 /* Clear the selected ADC interrupt pending bits */
rajathr 0:34ee385f4d2d 1727 ADCx->SR = ~(uint32_t)itmask;
rajathr 0:34ee385f4d2d 1728 }
rajathr 0:34ee385f4d2d 1729 /**
rajathr 0:34ee385f4d2d 1730 * @}
rajathr 0:34ee385f4d2d 1731 */
rajathr 0:34ee385f4d2d 1732
rajathr 0:34ee385f4d2d 1733 /**
rajathr 0:34ee385f4d2d 1734 * @}
rajathr 0:34ee385f4d2d 1735 */
rajathr 0:34ee385f4d2d 1736
rajathr 0:34ee385f4d2d 1737 /**
rajathr 0:34ee385f4d2d 1738 * @}
rajathr 0:34ee385f4d2d 1739 */
rajathr 0:34ee385f4d2d 1740
rajathr 0:34ee385f4d2d 1741 /**
rajathr 0:34ee385f4d2d 1742 * @}
rajathr 0:34ee385f4d2d 1743 */
rajathr 0:34ee385f4d2d 1744
rajathr 0:34ee385f4d2d 1745 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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