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Dependencies:   mbed

stm32f4xx_tim_mort.h@0:34ee385f4d2d, 2021-10-23 (annotated)

Committer:
rajathr
Date:
Sat Oct 23 05:49:09 2021 +0000
Revision:
0:34ee385f4d2d
At 23rd Oct 21 - All Code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rajathr 0:34ee385f4d2d 1 /**
rajathr 0:34ee385f4d2d 2 ******************************************************************************
rajathr 0:34ee385f4d2d 3 * @file stm32f4xx_tim.h
rajathr 0:34ee385f4d2d 4 * @author MCD Application Team
rajathr 0:34ee385f4d2d 5 * @version V1.8.0
rajathr 0:34ee385f4d2d 6 * @date 04-November-2016
rajathr 0:34ee385f4d2d 7 * @brief This file contains all the functions prototypes for the TIM firmware
rajathr 0:34ee385f4d2d 8 * library.
rajathr 0:34ee385f4d2d 9 ******************************************************************************
rajathr 0:34ee385f4d2d 10 * @attention
rajathr 0:34ee385f4d2d 11 *
rajathr 0:34ee385f4d2d 12 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
rajathr 0:34ee385f4d2d 13 *
rajathr 0:34ee385f4d2d 14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
rajathr 0:34ee385f4d2d 15 * You may not use this file except in compliance with the License.
rajathr 0:34ee385f4d2d 16 * You may obtain a copy of the License at:
rajathr 0:34ee385f4d2d 17 *
rajathr 0:34ee385f4d2d 18 * http://www.st.com/software_license_agreement_liberty_v2
rajathr 0:34ee385f4d2d 19 *
rajathr 0:34ee385f4d2d 20 * Unless required by applicable law or agreed to in writing, software
rajathr 0:34ee385f4d2d 21 * distributed under the License is distributed on an "AS IS" BASIS,
rajathr 0:34ee385f4d2d 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
rajathr 0:34ee385f4d2d 23 * See the License for the specific language governing permissions and
rajathr 0:34ee385f4d2d 24 * limitations under the License.
rajathr 0:34ee385f4d2d 25 *
rajathr 0:34ee385f4d2d 26 ******************************************************************************
rajathr 0:34ee385f4d2d 27 */
rajathr 0:34ee385f4d2d 28
rajathr 0:34ee385f4d2d 29 /* Define to prevent recursive inclusion -------------------------------------*/
rajathr 0:34ee385f4d2d 30 #ifndef __STM32F4xx_TIM_H_MORT_
rajathr 0:34ee385f4d2d 31 #define __STM32F4xx_TIM_H_MORT_
rajathr 0:34ee385f4d2d 32
rajathr 0:34ee385f4d2d 33 #ifdef __cplusplus
rajathr 0:34ee385f4d2d 34 extern "C" {
rajathr 0:34ee385f4d2d 35 #endif
rajathr 0:34ee385f4d2d 36
rajathr 0:34ee385f4d2d 37 /* Includes ------------------------------------------------------------------*/
rajathr 0:34ee385f4d2d 38 #include "stm32f4xx_mort2.h"
rajathr 0:34ee385f4d2d 39
rajathr 0:34ee385f4d2d 40 /** @addtogroup STM32F4xx_StdPeriph_Driver
rajathr 0:34ee385f4d2d 41 * @{
rajathr 0:34ee385f4d2d 42 */
rajathr 0:34ee385f4d2d 43
rajathr 0:34ee385f4d2d 44 /** @addtogroup TIM
rajathr 0:34ee385f4d2d 45 * @{
rajathr 0:34ee385f4d2d 46 */
rajathr 0:34ee385f4d2d 47
rajathr 0:34ee385f4d2d 48 /* Exported types ------------------------------------------------------------*/
rajathr 0:34ee385f4d2d 49
rajathr 0:34ee385f4d2d 50 /**
rajathr 0:34ee385f4d2d 51 * @brief TIM Time Base Init structure definition
rajathr 0:34ee385f4d2d 52 * @note This structure is used with all TIMx except for TIM6_MORT and TIM7_MORT.
rajathr 0:34ee385f4d2d 53 */
rajathr 0:34ee385f4d2d 54
rajathr 0:34ee385f4d2d 55 typedef struct
rajathr 0:34ee385f4d2d 56 {
rajathr 0:34ee385f4d2d 57 uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
rajathr 0:34ee385f4d2d 58 This parameter can be a number between 0x0000 and 0xFFFF */
rajathr 0:34ee385f4d2d 59
rajathr 0:34ee385f4d2d 60 uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
rajathr 0:34ee385f4d2d 61 This parameter can be a value of @ref TIM_Counter_Mode */
rajathr 0:34ee385f4d2d 62
rajathr 0:34ee385f4d2d 63 uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
rajathr 0:34ee385f4d2d 64 Auto-Reload Register at the next update event.
rajathr 0:34ee385f4d2d 65 This parameter must be a number between 0x0000 and 0xFFFF. */
rajathr 0:34ee385f4d2d 66
rajathr 0:34ee385f4d2d 67 uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
rajathr 0:34ee385f4d2d 68 This parameter can be a value of @ref TIM_Clock_Division_CKD */
rajathr 0:34ee385f4d2d 69
rajathr 0:34ee385f4d2d 70 uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
rajathr 0:34ee385f4d2d 71 reaches zero, an update event is generated and counting restarts
rajathr 0:34ee385f4d2d 72 from the RCR value (N).
rajathr 0:34ee385f4d2d 73 This means in PWM mode that (N+1) corresponds to:
rajathr 0:34ee385f4d2d 74 - the number of PWM periods in edge-aligned mode
rajathr 0:34ee385f4d2d 75 - the number of half PWM period in center-aligned mode
rajathr 0:34ee385f4d2d 76 This parameter must be a number between 0x00 and 0xFF.
rajathr 0:34ee385f4d2d 77 @note This parameter is valid only for TIM1_MORT and TIM8_MORT. */
rajathr 0:34ee385f4d2d 78 } TIM_TimeBaseInitTypeDef_mort;
rajathr 0:34ee385f4d2d 79
rajathr 0:34ee385f4d2d 80 /**
rajathr 0:34ee385f4d2d 81 * @brief TIM Output Compare Init structure definition
rajathr 0:34ee385f4d2d 82 */
rajathr 0:34ee385f4d2d 83
rajathr 0:34ee385f4d2d 84 typedef struct
rajathr 0:34ee385f4d2d 85 {
rajathr 0:34ee385f4d2d 86 uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
rajathr 0:34ee385f4d2d 87 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
rajathr 0:34ee385f4d2d 88
rajathr 0:34ee385f4d2d 89 uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
rajathr 0:34ee385f4d2d 90 This parameter can be a value of @ref TIM_Output_Compare_State */
rajathr 0:34ee385f4d2d 91
rajathr 0:34ee385f4d2d 92 uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
rajathr 0:34ee385f4d2d 93 This parameter can be a value of @ref TIM_Output_Compare_N_State
rajathr 0:34ee385f4d2d 94 @note This parameter is valid only for TIM1_MORT and TIM8_MORT. */
rajathr 0:34ee385f4d2d 95
rajathr 0:34ee385f4d2d 96 uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
rajathr 0:34ee385f4d2d 97 This parameter can be a number between 0x0000 and 0xFFFF */
rajathr 0:34ee385f4d2d 98
rajathr 0:34ee385f4d2d 99 uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
rajathr 0:34ee385f4d2d 100 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
rajathr 0:34ee385f4d2d 101
rajathr 0:34ee385f4d2d 102 uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
rajathr 0:34ee385f4d2d 103 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
rajathr 0:34ee385f4d2d 104 @note This parameter is valid only for TIM1_MORT and TIM8_MORT. */
rajathr 0:34ee385f4d2d 105
rajathr 0:34ee385f4d2d 106 uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
rajathr 0:34ee385f4d2d 107 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
rajathr 0:34ee385f4d2d 108 @note This parameter is valid only for TIM1_MORT and TIM8_MORT. */
rajathr 0:34ee385f4d2d 109
rajathr 0:34ee385f4d2d 110 uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
rajathr 0:34ee385f4d2d 111 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
rajathr 0:34ee385f4d2d 112 @note This parameter is valid only for TIM1_MORT and TIM8_MORT. */
rajathr 0:34ee385f4d2d 113 } TIM_OCInitTypeDef_mort;
rajathr 0:34ee385f4d2d 114
rajathr 0:34ee385f4d2d 115 /**
rajathr 0:34ee385f4d2d 116 * @brief TIM Input Capture Init structure definition
rajathr 0:34ee385f4d2d 117 */
rajathr 0:34ee385f4d2d 118
rajathr 0:34ee385f4d2d 119 typedef struct
rajathr 0:34ee385f4d2d 120 {
rajathr 0:34ee385f4d2d 121
rajathr 0:34ee385f4d2d 122 uint16_t TIM_Channel; /*!< Specifies the TIM channel.
rajathr 0:34ee385f4d2d 123 This parameter can be a value of @ref TIM_Channel */
rajathr 0:34ee385f4d2d 124
rajathr 0:34ee385f4d2d 125 uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
rajathr 0:34ee385f4d2d 126 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
rajathr 0:34ee385f4d2d 127
rajathr 0:34ee385f4d2d 128 uint16_t TIM_ICSelection; /*!< Specifies the input.
rajathr 0:34ee385f4d2d 129 This parameter can be a value of @ref TIM_Input_Capture_Selection */
rajathr 0:34ee385f4d2d 130
rajathr 0:34ee385f4d2d 131 uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
rajathr 0:34ee385f4d2d 132 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
rajathr 0:34ee385f4d2d 133
rajathr 0:34ee385f4d2d 134 uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
rajathr 0:34ee385f4d2d 135 This parameter can be a number between 0x0 and 0xF */
rajathr 0:34ee385f4d2d 136 } TIM_ICInitTypeDef_mort;
rajathr 0:34ee385f4d2d 137
rajathr 0:34ee385f4d2d 138 /**
rajathr 0:34ee385f4d2d 139 * @brief BDTR structure definition
rajathr 0:34ee385f4d2d 140 * @note This structure is used only with TIM1_MORT and TIM8_MORT.
rajathr 0:34ee385f4d2d 141 */
rajathr 0:34ee385f4d2d 142
rajathr 0:34ee385f4d2d 143 typedef struct
rajathr 0:34ee385f4d2d 144 {
rajathr 0:34ee385f4d2d 145
rajathr 0:34ee385f4d2d 146 uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
rajathr 0:34ee385f4d2d 147 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
rajathr 0:34ee385f4d2d 148
rajathr 0:34ee385f4d2d 149 uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
rajathr 0:34ee385f4d2d 150 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
rajathr 0:34ee385f4d2d 151
rajathr 0:34ee385f4d2d 152 uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
rajathr 0:34ee385f4d2d 153 This parameter can be a value of @ref TIM_Lock_level */
rajathr 0:34ee385f4d2d 154
rajathr 0:34ee385f4d2d 155 uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
rajathr 0:34ee385f4d2d 156 switching-on of the outputs.
rajathr 0:34ee385f4d2d 157 This parameter can be a number between 0x00 and 0xFF */
rajathr 0:34ee385f4d2d 158
rajathr 0:34ee385f4d2d 159 uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
rajathr 0:34ee385f4d2d 160 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
rajathr 0:34ee385f4d2d 161
rajathr 0:34ee385f4d2d 162 uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
rajathr 0:34ee385f4d2d 163 This parameter can be a value of @ref TIM_Break_Polarity */
rajathr 0:34ee385f4d2d 164
rajathr 0:34ee385f4d2d 165 uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
rajathr 0:34ee385f4d2d 166 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
rajathr 0:34ee385f4d2d 167 } TIM_BDTRInitTypeDef_mort;
rajathr 0:34ee385f4d2d 168
rajathr 0:34ee385f4d2d 169 /* Exported constants --------------------------------------------------------*/
rajathr 0:34ee385f4d2d 170
rajathr 0:34ee385f4d2d 171 /** @defgroup TIM_Exported_constants
rajathr 0:34ee385f4d2d 172 * @{
rajathr 0:34ee385f4d2d 173 */
rajathr 0:34ee385f4d2d 174
rajathr 0:34ee385f4d2d 175 #define IS_TIM_ALL_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \
rajathr 0:34ee385f4d2d 176 ((PERIPH) == TIM2_MORT) || \
rajathr 0:34ee385f4d2d 177 ((PERIPH) == TIM3_MORT) || \
rajathr 0:34ee385f4d2d 178 ((PERIPH) == TIM4_MORT) || \
rajathr 0:34ee385f4d2d 179 ((PERIPH) == TIM5_MORT) || \
rajathr 0:34ee385f4d2d 180 ((PERIPH) == TIM6_MORT) || \
rajathr 0:34ee385f4d2d 181 ((PERIPH) == TIM7_MORT) || \
rajathr 0:34ee385f4d2d 182 ((PERIPH) == TIM8_MORT) || \
rajathr 0:34ee385f4d2d 183 ((PERIPH) == TIM9_MORT) || \
rajathr 0:34ee385f4d2d 184 ((PERIPH) == TIM10_MORT) || \
rajathr 0:34ee385f4d2d 185 ((PERIPH) == TIM11_MORT) || \
rajathr 0:34ee385f4d2d 186 ((PERIPH) == TIM12_MORT) || \
rajathr 0:34ee385f4d2d 187 (((PERIPH) == TIM13_MORT) || \
rajathr 0:34ee385f4d2d 188 ((PERIPH) == TIM14_MORT)))
rajathr 0:34ee385f4d2d 189 /* LIST1: TIM1_MORT, TIM2_MORT, TIM3_MORT, TIM4_MORT, TIM5_MORT, TIM8_MORT, TIM9_MORT, TIM10_MORT, TIM11_MORT, TIM12_MORT, TIM13_MORT and TIM14_MORT */
rajathr 0:34ee385f4d2d 190 #define IS_TIM_LIST1_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \
rajathr 0:34ee385f4d2d 191 ((PERIPH) == TIM2_MORT) || \
rajathr 0:34ee385f4d2d 192 ((PERIPH) == TIM3_MORT) || \
rajathr 0:34ee385f4d2d 193 ((PERIPH) == TIM4_MORT) || \
rajathr 0:34ee385f4d2d 194 ((PERIPH) == TIM5_MORT) || \
rajathr 0:34ee385f4d2d 195 ((PERIPH) == TIM8_MORT) || \
rajathr 0:34ee385f4d2d 196 ((PERIPH) == TIM9_MORT) || \
rajathr 0:34ee385f4d2d 197 ((PERIPH) == TIM10_MORT) || \
rajathr 0:34ee385f4d2d 198 ((PERIPH) == TIM11_MORT) || \
rajathr 0:34ee385f4d2d 199 ((PERIPH) == TIM12_MORT) || \
rajathr 0:34ee385f4d2d 200 ((PERIPH) == TIM13_MORT) || \
rajathr 0:34ee385f4d2d 201 ((PERIPH) == TIM14_MORT))
rajathr 0:34ee385f4d2d 202
rajathr 0:34ee385f4d2d 203 /* LIST2: TIM1_MORT, TIM2_MORT, TIM3_MORT, TIM4_MORT, TIM5_MORT, TIM8_MORT, TIM9_MORT and TIM12_MORT */
rajathr 0:34ee385f4d2d 204 #define IS_TIM_LIST2_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \
rajathr 0:34ee385f4d2d 205 ((PERIPH) == TIM2_MORT) || \
rajathr 0:34ee385f4d2d 206 ((PERIPH) == TIM3_MORT) || \
rajathr 0:34ee385f4d2d 207 ((PERIPH) == TIM4_MORT) || \
rajathr 0:34ee385f4d2d 208 ((PERIPH) == TIM5_MORT) || \
rajathr 0:34ee385f4d2d 209 ((PERIPH) == TIM8_MORT) || \
rajathr 0:34ee385f4d2d 210 ((PERIPH) == TIM9_MORT) || \
rajathr 0:34ee385f4d2d 211 ((PERIPH) == TIM12_MORT))
rajathr 0:34ee385f4d2d 212 /* LIST3: TIM1_MORT, TIM2_MORT, TIM3_MORT, TIM4_MORT, TIM5_MORT and TIM8_MORT */
rajathr 0:34ee385f4d2d 213 #define IS_TIM_LIST3_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \
rajathr 0:34ee385f4d2d 214 ((PERIPH) == TIM2_MORT) || \
rajathr 0:34ee385f4d2d 215 ((PERIPH) == TIM3_MORT) || \
rajathr 0:34ee385f4d2d 216 ((PERIPH) == TIM4_MORT) || \
rajathr 0:34ee385f4d2d 217 ((PERIPH) == TIM5_MORT) || \
rajathr 0:34ee385f4d2d 218 ((PERIPH) == TIM8_MORT))
rajathr 0:34ee385f4d2d 219 /* LIST4: TIM1_MORT and TIM8_MORT */
rajathr 0:34ee385f4d2d 220 #define IS_TIM_LIST4_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \
rajathr 0:34ee385f4d2d 221 ((PERIPH) == TIM8_MORT))
rajathr 0:34ee385f4d2d 222 /* LIST5: TIM1_MORT, TIM2_MORT, TIM3_MORT, TIM4_MORT, TIM5_MORT, TIM6_MORT, TIM7_MORT and TIM8_MORT */
rajathr 0:34ee385f4d2d 223 #define IS_TIM_LIST5_PERIPH_MORT(PERIPH) (((PERIPH) == TIM1_MORT) || \
rajathr 0:34ee385f4d2d 224 ((PERIPH) == TIM2_MORT) || \
rajathr 0:34ee385f4d2d 225 ((PERIPH) == TIM3_MORT) || \
rajathr 0:34ee385f4d2d 226 ((PERIPH) == TIM4_MORT) || \
rajathr 0:34ee385f4d2d 227 ((PERIPH) == TIM5_MORT) || \
rajathr 0:34ee385f4d2d 228 ((PERIPH) == TIM6_MORT) || \
rajathr 0:34ee385f4d2d 229 ((PERIPH) == TIM7_MORT) || \
rajathr 0:34ee385f4d2d 230 ((PERIPH) == TIM8_MORT))
rajathr 0:34ee385f4d2d 231 /* LIST6: TIM2_MORT, TIM5_MORT and TIM11_MORT */
rajathr 0:34ee385f4d2d 232 #define IS_TIM_LIST6_PERIPH_MORT(TIMx)(((TIMx) == TIM2_MORT) || \
rajathr 0:34ee385f4d2d 233 ((TIMx) == TIM5_MORT) || \
rajathr 0:34ee385f4d2d 234 ((TIMx) == TIM11_MORT))
rajathr 0:34ee385f4d2d 235
rajathr 0:34ee385f4d2d 236 /** @defgroup TIM_Output_Compare_and_PWM_modes
rajathr 0:34ee385f4d2d 237 * @{
rajathr 0:34ee385f4d2d 238 */
rajathr 0:34ee385f4d2d 239
rajathr 0:34ee385f4d2d 240 #define TIM_OCMode_Timing_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 241 #define TIM_OCMode_Active_MORT ((uint16_t)0x0010)
rajathr 0:34ee385f4d2d 242 #define TIM_OCMode_Inactive_MORT ((uint16_t)0x0020)
rajathr 0:34ee385f4d2d 243 #define TIM_OCMode_Toggle_MORT ((uint16_t)0x0030)
rajathr 0:34ee385f4d2d 244 #define TIM_OCMode_PWM1_MORT ((uint16_t)0x0060)
rajathr 0:34ee385f4d2d 245 #define TIM_OCMode_PWM2_MORT ((uint16_t)0x0070)
rajathr 0:34ee385f4d2d 246 #define IS_TIM_OC_MODE_MORT(MODE) (((MODE) == TIM_OCMode_Timing_MORT) || \
rajathr 0:34ee385f4d2d 247 ((MODE) == TIM_OCMode_Active_MORT) || \
rajathr 0:34ee385f4d2d 248 ((MODE) == TIM_OCMode_Inactive_MORT) || \
rajathr 0:34ee385f4d2d 249 ((MODE) == TIM_OCMode_Toggle_MORT)|| \
rajathr 0:34ee385f4d2d 250 ((MODE) == TIM_OCMode_PWM1_MORT) || \
rajathr 0:34ee385f4d2d 251 ((MODE) == TIM_OCMode_PWM2_MORT))
rajathr 0:34ee385f4d2d 252 #define IS_TIM_OCM_MORT(MODE) (((MODE) == TIM_OCMode_Timing_MORT) || \
rajathr 0:34ee385f4d2d 253 ((MODE) == TIM_OCMode_Active_MORT) || \
rajathr 0:34ee385f4d2d 254 ((MODE) == TIM_OCMode_Inactive_MORT) || \
rajathr 0:34ee385f4d2d 255 ((MODE) == TIM_OCMode_Toggle_MORT)|| \
rajathr 0:34ee385f4d2d 256 ((MODE) == TIM_OCMode_PWM1_MORT) || \
rajathr 0:34ee385f4d2d 257 ((MODE) == TIM_OCMode_PWM2_MORT) || \
rajathr 0:34ee385f4d2d 258 ((MODE) == TIM_ForcedAction_Active_MORT) || \
rajathr 0:34ee385f4d2d 259 ((MODE) == TIM_ForcedAction_InActive_MORT))
rajathr 0:34ee385f4d2d 260 /**
rajathr 0:34ee385f4d2d 261 * @}
rajathr 0:34ee385f4d2d 262 */
rajathr 0:34ee385f4d2d 263
rajathr 0:34ee385f4d2d 264 /** @defgroup TIM_One_Pulse_Mode
rajathr 0:34ee385f4d2d 265 * @{
rajathr 0:34ee385f4d2d 266 */
rajathr 0:34ee385f4d2d 267
rajathr 0:34ee385f4d2d 268 #define TIM_OPMode_Single_MORT ((uint16_t)0x0008)
rajathr 0:34ee385f4d2d 269 #define TIM_OPMode_Repetitive_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 270 #define IS_TIM_OPM_MODE_MORT(MODE) (((MODE) == TIM_OPMode_Single_MORT) || \
rajathr 0:34ee385f4d2d 271 ((MODE) == TIM_OPMode_Repetitive_MORT))
rajathr 0:34ee385f4d2d 272 /**
rajathr 0:34ee385f4d2d 273 * @}
rajathr 0:34ee385f4d2d 274 */
rajathr 0:34ee385f4d2d 275
rajathr 0:34ee385f4d2d 276 /** @defgroup TIM_Channel
rajathr 0:34ee385f4d2d 277 * @{
rajathr 0:34ee385f4d2d 278 */
rajathr 0:34ee385f4d2d 279
rajathr 0:34ee385f4d2d 280 #define TIM_Channel_1_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 281 #define TIM_Channel_2_MORT ((uint16_t)0x0004)
rajathr 0:34ee385f4d2d 282 #define TIM_Channel_3_MORT ((uint16_t)0x0008)
rajathr 0:34ee385f4d2d 283 #define TIM_Channel_4_MORT ((uint16_t)0x000C)
rajathr 0:34ee385f4d2d 284
rajathr 0:34ee385f4d2d 285 #define IS_TIM_CHANNEL_MORT(CHANNEL) (((CHANNEL) == TIM_Channel_1_MORT) || \
rajathr 0:34ee385f4d2d 286 ((CHANNEL) == TIM_Channel_2_MORT) || \
rajathr 0:34ee385f4d2d 287 ((CHANNEL) == TIM_Channel_3_MORT) || \
rajathr 0:34ee385f4d2d 288 ((CHANNEL) == TIM_Channel_4_MORT))
rajathr 0:34ee385f4d2d 289
rajathr 0:34ee385f4d2d 290 #define IS_TIM_PWMI_CHANNEL_MORT(CHANNEL) (((CHANNEL) == TIM_Channel_1_MORT) || \
rajathr 0:34ee385f4d2d 291 ((CHANNEL) == TIM_Channel_2_MORT))
rajathr 0:34ee385f4d2d 292 #define IS_TIM_COMPLEMENTARY_CHANNEL_MORT(CHANNEL) (((CHANNEL) == TIM_Channel_1_MORT) || \
rajathr 0:34ee385f4d2d 293 ((CHANNEL) == TIM_Channel_2_MORT) || \
rajathr 0:34ee385f4d2d 294 ((CHANNEL) == TIM_Channel_3_MORT))
rajathr 0:34ee385f4d2d 295 /**
rajathr 0:34ee385f4d2d 296 * @}
rajathr 0:34ee385f4d2d 297 */
rajathr 0:34ee385f4d2d 298
rajathr 0:34ee385f4d2d 299 /** @defgroup TIM_Clock_Division_CKD
rajathr 0:34ee385f4d2d 300 * @{
rajathr 0:34ee385f4d2d 301 */
rajathr 0:34ee385f4d2d 302
rajathr 0:34ee385f4d2d 303 #define TIM_CKD_DIV1_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 304 #define TIM_CKD_DIV2_MORT ((uint16_t)0x0100)
rajathr 0:34ee385f4d2d 305 #define TIM_CKD_DIV4_MORT ((uint16_t)0x0200)
rajathr 0:34ee385f4d2d 306 #define IS_TIM_CKD_DIV_MORT(DIV) (((DIV) == TIM_CKD_DIV1_MORT) || \
rajathr 0:34ee385f4d2d 307 ((DIV) == TIM_CKD_DIV2_MORT) || \
rajathr 0:34ee385f4d2d 308 ((DIV) == TIM_CKD_DIV4_MORT))
rajathr 0:34ee385f4d2d 309 /**
rajathr 0:34ee385f4d2d 310 * @}
rajathr 0:34ee385f4d2d 311 */
rajathr 0:34ee385f4d2d 312
rajathr 0:34ee385f4d2d 313 /** @defgroup TIM_Counter_Mode
rajathr 0:34ee385f4d2d 314 * @{
rajathr 0:34ee385f4d2d 315 */
rajathr 0:34ee385f4d2d 316
rajathr 0:34ee385f4d2d 317 #define TIM_CounterMode_Up_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 318 #define TIM_CounterMode_Down_MORT ((uint16_t)0x0010)
rajathr 0:34ee385f4d2d 319 #define TIM_CounterMode_CenterAligned1_MORT ((uint16_t)0x0020)
rajathr 0:34ee385f4d2d 320 #define TIM_CounterMode_CenterAligned2_MORT ((uint16_t)0x0040)
rajathr 0:34ee385f4d2d 321 #define TIM_CounterMode_CenterAligned3_MORT ((uint16_t)0x0060)
rajathr 0:34ee385f4d2d 322 #define IS_TIM_COUNTER_MODE_MORT(MODE) (((MODE) == TIM_CounterMode_Up_MORT) || \
rajathr 0:34ee385f4d2d 323 ((MODE) == TIM_CounterMode_Down_MORT) || \
rajathr 0:34ee385f4d2d 324 ((MODE) == TIM_CounterMode_CenterAligned1_MORT) || \
rajathr 0:34ee385f4d2d 325 ((MODE) == TIM_CounterMode_CenterAligned2_MORT) || \
rajathr 0:34ee385f4d2d 326 ((MODE) == TIM_CounterMode_CenterAligned3_MORT))
rajathr 0:34ee385f4d2d 327 /**
rajathr 0:34ee385f4d2d 328 * @}
rajathr 0:34ee385f4d2d 329 */
rajathr 0:34ee385f4d2d 330
rajathr 0:34ee385f4d2d 331 /** @defgroup TIM_Output_Compare_Polarity
rajathr 0:34ee385f4d2d 332 * @{
rajathr 0:34ee385f4d2d 333 */
rajathr 0:34ee385f4d2d 334
rajathr 0:34ee385f4d2d 335 #define TIM_OCPolarity_High_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 336 #define TIM_OCPolarity_Low_MORT ((uint16_t)0x0002)
rajathr 0:34ee385f4d2d 337 #define IS_TIM_OC_POLARITY_MORT(POLARITY) (((POLARITY) == TIM_OCPolarity_High_MORT) || \
rajathr 0:34ee385f4d2d 338 ((POLARITY) == TIM_OCPolarity_Low_MORT))
rajathr 0:34ee385f4d2d 339 /**
rajathr 0:34ee385f4d2d 340 * @}
rajathr 0:34ee385f4d2d 341 */
rajathr 0:34ee385f4d2d 342
rajathr 0:34ee385f4d2d 343 /** @defgroup TIM_Output_Compare_N_Polarity
rajathr 0:34ee385f4d2d 344 * @{
rajathr 0:34ee385f4d2d 345 */
rajathr 0:34ee385f4d2d 346
rajathr 0:34ee385f4d2d 347 #define TIM_OCNPolarity_High_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 348 #define TIM_OCNPolarity_Low_MORT ((uint16_t)0x0008)
rajathr 0:34ee385f4d2d 349 #define IS_TIM_OCN_POLARITY_MORT(POLARITY) (((POLARITY) == TIM_OCNPolarity_High_MORT) || \
rajathr 0:34ee385f4d2d 350 ((POLARITY) == TIM_OCNPolarity_Low_MORT))
rajathr 0:34ee385f4d2d 351 /**
rajathr 0:34ee385f4d2d 352 * @}
rajathr 0:34ee385f4d2d 353 */
rajathr 0:34ee385f4d2d 354
rajathr 0:34ee385f4d2d 355 /** @defgroup TIM_Output_Compare_State
rajathr 0:34ee385f4d2d 356 * @{
rajathr 0:34ee385f4d2d 357 */
rajathr 0:34ee385f4d2d 358
rajathr 0:34ee385f4d2d 359 #define TIM_OutputState_Disable_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 360 #define TIM_OutputState_Enable_MORT ((uint16_t)0x0001)
rajathr 0:34ee385f4d2d 361 #define IS_TIM_OUTPUT_STATE_MORT(STATE) (((STATE) == TIM_OutputState_Disable_MORT) || \
rajathr 0:34ee385f4d2d 362 ((STATE) == TIM_OutputState_Enable_MORT))
rajathr 0:34ee385f4d2d 363 /**
rajathr 0:34ee385f4d2d 364 * @}
rajathr 0:34ee385f4d2d 365 */
rajathr 0:34ee385f4d2d 366
rajathr 0:34ee385f4d2d 367 /** @defgroup TIM_Output_Compare_N_State
rajathr 0:34ee385f4d2d 368 * @{
rajathr 0:34ee385f4d2d 369 */
rajathr 0:34ee385f4d2d 370
rajathr 0:34ee385f4d2d 371 #define TIM_OutputNState_Disable_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 372 #define TIM_OutputNState_Enable_MORT ((uint16_t)0x0004)
rajathr 0:34ee385f4d2d 373 #define IS_TIM_OUTPUTN_STATE_MORT(STATE) (((STATE) == TIM_OutputNState_Disable_MORT) || \
rajathr 0:34ee385f4d2d 374 ((STATE) == TIM_OutputNState_Enable_MORT))
rajathr 0:34ee385f4d2d 375 /**
rajathr 0:34ee385f4d2d 376 * @}
rajathr 0:34ee385f4d2d 377 */
rajathr 0:34ee385f4d2d 378
rajathr 0:34ee385f4d2d 379 /** @defgroup TIM_Capture_Compare_State
rajathr 0:34ee385f4d2d 380 * @{
rajathr 0:34ee385f4d2d 381 */
rajathr 0:34ee385f4d2d 382
rajathr 0:34ee385f4d2d 383 #define TIM_CCx_Enable_MORT ((uint16_t)0x0001)
rajathr 0:34ee385f4d2d 384 #define TIM_CCx_Disable_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 385 #define IS_TIM_CCX_MORT(CCX) (((CCX) == TIM_CCx_Enable_MORT) || \
rajathr 0:34ee385f4d2d 386 ((CCX) == TIM_CCx_Disable_MORT))
rajathr 0:34ee385f4d2d 387 /**
rajathr 0:34ee385f4d2d 388 * @}
rajathr 0:34ee385f4d2d 389 */
rajathr 0:34ee385f4d2d 390
rajathr 0:34ee385f4d2d 391 /** @defgroup TIM_Capture_Compare_N_State
rajathr 0:34ee385f4d2d 392 * @{
rajathr 0:34ee385f4d2d 393 */
rajathr 0:34ee385f4d2d 394
rajathr 0:34ee385f4d2d 395 #define TIM_CCxN_Enable_MORT ((uint16_t)0x0004)
rajathr 0:34ee385f4d2d 396 #define TIM_CCxN_Disable_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 397 #define IS_TIM_CCXN_MORT(CCXN) (((CCXN) == TIM_CCxN_Enable_MORT) || \
rajathr 0:34ee385f4d2d 398 ((CCXN) == TIM_CCxN_Disable_MORT))
rajathr 0:34ee385f4d2d 399 /**
rajathr 0:34ee385f4d2d 400 * @}
rajathr 0:34ee385f4d2d 401 */
rajathr 0:34ee385f4d2d 402
rajathr 0:34ee385f4d2d 403 /** @defgroup TIM_Break_Input_enable_disable
rajathr 0:34ee385f4d2d 404 * @{
rajathr 0:34ee385f4d2d 405 */
rajathr 0:34ee385f4d2d 406
rajathr 0:34ee385f4d2d 407 #define TIM_Break_Enable_MORT ((uint16_t)0x1000)
rajathr 0:34ee385f4d2d 408 #define TIM_Break_Disable_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 409 #define IS_TIM_BREAK_STATE_MORT(STATE) (((STATE) == TIM_Break_Enable_MORT) || \
rajathr 0:34ee385f4d2d 410 ((STATE) == TIM_Break_Disable_MORT))
rajathr 0:34ee385f4d2d 411 /**
rajathr 0:34ee385f4d2d 412 * @}
rajathr 0:34ee385f4d2d 413 */
rajathr 0:34ee385f4d2d 414
rajathr 0:34ee385f4d2d 415 /** @defgroup TIM_Break_Polarity
rajathr 0:34ee385f4d2d 416 * @{
rajathr 0:34ee385f4d2d 417 */
rajathr 0:34ee385f4d2d 418
rajathr 0:34ee385f4d2d 419 #define TIM_BreakPolarity_Low_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 420 #define TIM_BreakPolarity_High_MORT ((uint16_t)0x2000)
rajathr 0:34ee385f4d2d 421 #define IS_TIM_BREAK_POLARITY_MORT(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low_MORT) || \
rajathr 0:34ee385f4d2d 422 ((POLARITY) == TIM_BreakPolarity_High_MORT))
rajathr 0:34ee385f4d2d 423 /**
rajathr 0:34ee385f4d2d 424 * @}
rajathr 0:34ee385f4d2d 425 */
rajathr 0:34ee385f4d2d 426
rajathr 0:34ee385f4d2d 427 /** @defgroup TIM_AOE_Bit_Set_Reset
rajathr 0:34ee385f4d2d 428 * @{
rajathr 0:34ee385f4d2d 429 */
rajathr 0:34ee385f4d2d 430
rajathr 0:34ee385f4d2d 431 #define TIM_AutomaticOutput_Enable_MORT ((uint16_t)0x4000)
rajathr 0:34ee385f4d2d 432 #define TIM_AutomaticOutput_Disable_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 433 #define IS_TIM_AUTOMATIC_OUTPUT_STATE_MORT(STATE) (((STATE) == TIM_AutomaticOutput_Enable_MORT) || \
rajathr 0:34ee385f4d2d 434 ((STATE) == TIM_AutomaticOutput_Disable_MORT))
rajathr 0:34ee385f4d2d 435 /**
rajathr 0:34ee385f4d2d 436 * @}
rajathr 0:34ee385f4d2d 437 */
rajathr 0:34ee385f4d2d 438
rajathr 0:34ee385f4d2d 439 /** @defgroup TIM_Lock_level
rajathr 0:34ee385f4d2d 440 * @{
rajathr 0:34ee385f4d2d 441 */
rajathr 0:34ee385f4d2d 442
rajathr 0:34ee385f4d2d 443 #define TIM_LOCKLevel_OFF_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 444 #define TIM_LOCKLevel_1_MORT ((uint16_t)0x0100)
rajathr 0:34ee385f4d2d 445 #define TIM_LOCKLevel_2_MORT ((uint16_t)0x0200)
rajathr 0:34ee385f4d2d 446 #define TIM_LOCKLevel_3_MORT ((uint16_t)0x0300)
rajathr 0:34ee385f4d2d 447 #define IS_TIM_LOCK_LEVEL_MORT(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF_MORT) || \
rajathr 0:34ee385f4d2d 448 ((LEVEL) == TIM_LOCKLevel_1_MORT) || \
rajathr 0:34ee385f4d2d 449 ((LEVEL) == TIM_LOCKLevel_2_MORT) || \
rajathr 0:34ee385f4d2d 450 ((LEVEL) == TIM_LOCKLevel_3_MORT))
rajathr 0:34ee385f4d2d 451 /**
rajathr 0:34ee385f4d2d 452 * @}
rajathr 0:34ee385f4d2d 453 */
rajathr 0:34ee385f4d2d 454
rajathr 0:34ee385f4d2d 455 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
rajathr 0:34ee385f4d2d 456 * @{
rajathr 0:34ee385f4d2d 457 */
rajathr 0:34ee385f4d2d 458
rajathr 0:34ee385f4d2d 459 #define TIM_OSSIState_Enable_MORT ((uint16_t)0x0400)
rajathr 0:34ee385f4d2d 460 #define TIM_OSSIState_Disable_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 461 #define IS_TIM_OSSI_STATE_MORT(STATE) (((STATE) == TIM_OSSIState_Enable_MORT) || \
rajathr 0:34ee385f4d2d 462 ((STATE) == TIM_OSSIState_Disable_MORT))
rajathr 0:34ee385f4d2d 463 /**
rajathr 0:34ee385f4d2d 464 * @}
rajathr 0:34ee385f4d2d 465 */
rajathr 0:34ee385f4d2d 466
rajathr 0:34ee385f4d2d 467 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
rajathr 0:34ee385f4d2d 468 * @{
rajathr 0:34ee385f4d2d 469 */
rajathr 0:34ee385f4d2d 470
rajathr 0:34ee385f4d2d 471 #define TIM_OSSRState_Enable_MORT ((uint16_t)0x0800)
rajathr 0:34ee385f4d2d 472 #define TIM_OSSRState_Disable_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 473 #define IS_TIM_OSSR_STATE_MORT(STATE) (((STATE) == TIM_OSSRState_Enable_MORT) || \
rajathr 0:34ee385f4d2d 474 ((STATE) == TIM_OSSRState_Disable_MORT))
rajathr 0:34ee385f4d2d 475 /**
rajathr 0:34ee385f4d2d 476 * @}
rajathr 0:34ee385f4d2d 477 */
rajathr 0:34ee385f4d2d 478
rajathr 0:34ee385f4d2d 479 /** @defgroup TIM_Output_Compare_Idle_State
rajathr 0:34ee385f4d2d 480 * @{
rajathr 0:34ee385f4d2d 481 */
rajathr 0:34ee385f4d2d 482
rajathr 0:34ee385f4d2d 483 #define TIM_OCIdleState_Set_MORT ((uint16_t)0x0100)
rajathr 0:34ee385f4d2d 484 #define TIM_OCIdleState_Reset_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 485 #define IS_TIM_OCIDLE_STATE_MORT(STATE) (((STATE) == TIM_OCIdleState_Set_MORT) || \
rajathr 0:34ee385f4d2d 486 ((STATE) == TIM_OCIdleState_Reset_MORT))
rajathr 0:34ee385f4d2d 487 /**
rajathr 0:34ee385f4d2d 488 * @}
rajathr 0:34ee385f4d2d 489 */
rajathr 0:34ee385f4d2d 490
rajathr 0:34ee385f4d2d 491 /** @defgroup TIM_Output_Compare_N_Idle_State
rajathr 0:34ee385f4d2d 492 * @{
rajathr 0:34ee385f4d2d 493 */
rajathr 0:34ee385f4d2d 494
rajathr 0:34ee385f4d2d 495 #define TIM_OCNIdleState_Set_MORT ((uint16_t)0x0200)
rajathr 0:34ee385f4d2d 496 #define TIM_OCNIdleState_Reset_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 497 #define IS_TIM_OCNIDLE_STATE_MORT(STATE) (((STATE) == TIM_OCNIdleState_Set_MORT) || \
rajathr 0:34ee385f4d2d 498 ((STATE) == TIM_OCNIdleState_Reset_MORT))
rajathr 0:34ee385f4d2d 499 /**
rajathr 0:34ee385f4d2d 500 * @}
rajathr 0:34ee385f4d2d 501 */
rajathr 0:34ee385f4d2d 502
rajathr 0:34ee385f4d2d 503 /** @defgroup TIM_Input_Capture_Polarity
rajathr 0:34ee385f4d2d 504 * @{
rajathr 0:34ee385f4d2d 505 */
rajathr 0:34ee385f4d2d 506
rajathr 0:34ee385f4d2d 507 #define TIM_ICPolarity_Rising_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 508 #define TIM_ICPolarity_Falling_MORT ((uint16_t)0x0002)
rajathr 0:34ee385f4d2d 509 #define TIM_ICPolarity_BothEdge_MORT ((uint16_t)0x000A)
rajathr 0:34ee385f4d2d 510 #define IS_TIM_IC_POLARITY_MORT(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising_MORT) || \
rajathr 0:34ee385f4d2d 511 ((POLARITY) == TIM_ICPolarity_Falling_MORT)|| \
rajathr 0:34ee385f4d2d 512 ((POLARITY) == TIM_ICPolarity_BothEdge_MORT))
rajathr 0:34ee385f4d2d 513 /**
rajathr 0:34ee385f4d2d 514 * @}
rajathr 0:34ee385f4d2d 515 */
rajathr 0:34ee385f4d2d 516
rajathr 0:34ee385f4d2d 517 /** @defgroup TIM_Input_Capture_Selection
rajathr 0:34ee385f4d2d 518 * @{
rajathr 0:34ee385f4d2d 519 */
rajathr 0:34ee385f4d2d 520
rajathr 0:34ee385f4d2d 521 #define TIM_ICSelection_DirectTI_MORT ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
rajathr 0:34ee385f4d2d 522 connected to IC1, IC2, IC3 or IC4, respectively */
rajathr 0:34ee385f4d2d 523 #define TIM_ICSelection_IndirectTI_MORT ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
rajathr 0:34ee385f4d2d 524 connected to IC2, IC1, IC4 or IC3, respectively. */
rajathr 0:34ee385f4d2d 525 #define TIM_ICSelection_TRC_MORT ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
rajathr 0:34ee385f4d2d 526 #define IS_TIM_IC_SELECTION_MORT(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI_MORT) || \
rajathr 0:34ee385f4d2d 527 ((SELECTION) == TIM_ICSelection_IndirectTI_MORT) || \
rajathr 0:34ee385f4d2d 528 ((SELECTION) == TIM_ICSelection_TRC_MORT))
rajathr 0:34ee385f4d2d 529 /**
rajathr 0:34ee385f4d2d 530 * @}
rajathr 0:34ee385f4d2d 531 */
rajathr 0:34ee385f4d2d 532
rajathr 0:34ee385f4d2d 533 /** @defgroup TIM_Input_Capture_Prescaler
rajathr 0:34ee385f4d2d 534 * @{
rajathr 0:34ee385f4d2d 535 */
rajathr 0:34ee385f4d2d 536
rajathr 0:34ee385f4d2d 537 #define TIM_ICPSC_DIV1_MORT ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
rajathr 0:34ee385f4d2d 538 #define TIM_ICPSC_DIV2_MORT ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
rajathr 0:34ee385f4d2d 539 #define TIM_ICPSC_DIV4_MORT ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
rajathr 0:34ee385f4d2d 540 #define TIM_ICPSC_DIV8_MORT ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
rajathr 0:34ee385f4d2d 541 #define IS_TIM_IC_PRESCALER_MORT(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1_MORT) || \
rajathr 0:34ee385f4d2d 542 ((PRESCALER) == TIM_ICPSC_DIV2_MORT) || \
rajathr 0:34ee385f4d2d 543 ((PRESCALER) == TIM_ICPSC_DIV4_MORT) || \
rajathr 0:34ee385f4d2d 544 ((PRESCALER) == TIM_ICPSC_DIV8_MORT))
rajathr 0:34ee385f4d2d 545 /**
rajathr 0:34ee385f4d2d 546 * @}
rajathr 0:34ee385f4d2d 547 */
rajathr 0:34ee385f4d2d 548
rajathr 0:34ee385f4d2d 549 /** @defgroup TIM_interrupt_sources
rajathr 0:34ee385f4d2d 550 * @{
rajathr 0:34ee385f4d2d 551 */
rajathr 0:34ee385f4d2d 552
rajathr 0:34ee385f4d2d 553 #define TIM_IT_Update_MORT ((uint16_t)0x0001)
rajathr 0:34ee385f4d2d 554 #define TIM_IT_CC1_MORT ((uint16_t)0x0002)
rajathr 0:34ee385f4d2d 555 #define TIM_IT_CC2_MORT ((uint16_t)0x0004)
rajathr 0:34ee385f4d2d 556 #define TIM_IT_CC3_MORT ((uint16_t)0x0008)
rajathr 0:34ee385f4d2d 557 #define TIM_IT_CC4_MORT ((uint16_t)0x0010)
rajathr 0:34ee385f4d2d 558 #define TIM_IT_COM_MORT ((uint16_t)0x0020)
rajathr 0:34ee385f4d2d 559 #define TIM_IT_Trigger_MORT ((uint16_t)0x0040)
rajathr 0:34ee385f4d2d 560 #define TIM_IT_Break_MORT ((uint16_t)0x0080)
rajathr 0:34ee385f4d2d 561 #define IS_TIM_IT_MORT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
rajathr 0:34ee385f4d2d 562
rajathr 0:34ee385f4d2d 563 #define IS_TIM_GET_IT_MORT(IT) (((IT) == TIM_IT_Update_MORT) || \
rajathr 0:34ee385f4d2d 564 ((IT) == TIM_IT_CC1_MORT) || \
rajathr 0:34ee385f4d2d 565 ((IT) == TIM_IT_CC2_MORT) || \
rajathr 0:34ee385f4d2d 566 ((IT) == TIM_IT_CC3_MORT) || \
rajathr 0:34ee385f4d2d 567 ((IT) == TIM_IT_CC4_MORT) || \
rajathr 0:34ee385f4d2d 568 ((IT) == TIM_IT_COM_MORT) || \
rajathr 0:34ee385f4d2d 569 ((IT) == TIM_IT_Trigger_MORT) || \
rajathr 0:34ee385f4d2d 570 ((IT) == TIM_IT_Break_MORT))
rajathr 0:34ee385f4d2d 571 /**
rajathr 0:34ee385f4d2d 572 * @}
rajathr 0:34ee385f4d2d 573 */
rajathr 0:34ee385f4d2d 574
rajathr 0:34ee385f4d2d 575 /** @defgroup TIM_DMA_Base_address
rajathr 0:34ee385f4d2d 576 * @{
rajathr 0:34ee385f4d2d 577 */
rajathr 0:34ee385f4d2d 578
rajathr 0:34ee385f4d2d 579 #define TIM_DMABase_CR1_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 580 #define TIM_DMABase_CR2_MORT ((uint16_t)0x0001)
rajathr 0:34ee385f4d2d 581 #define TIM_DMABase_SMCR_MORT ((uint16_t)0x0002)
rajathr 0:34ee385f4d2d 582 #define TIM_DMABase_DIER_MORT ((uint16_t)0x0003)
rajathr 0:34ee385f4d2d 583 #define TIM_DMABase_SR_MORT ((uint16_t)0x0004)
rajathr 0:34ee385f4d2d 584 #define TIM_DMABase_EGR_MORT ((uint16_t)0x0005)
rajathr 0:34ee385f4d2d 585 #define TIM_DMABase_CCMR1_MORT ((uint16_t)0x0006)
rajathr 0:34ee385f4d2d 586 #define TIM_DMABase_CCMR2_MORT ((uint16_t)0x0007)
rajathr 0:34ee385f4d2d 587 #define TIM_DMABase_CCER_MORT ((uint16_t)0x0008)
rajathr 0:34ee385f4d2d 588 #define TIM_DMABase_CNT_MORT ((uint16_t)0x0009)
rajathr 0:34ee385f4d2d 589 #define TIM_DMABase_PSC_MORT ((uint16_t)0x000A)
rajathr 0:34ee385f4d2d 590 #define TIM_DMABase_ARR_MORT ((uint16_t)0x000B)
rajathr 0:34ee385f4d2d 591 #define TIM_DMABase_RCR_MORT ((uint16_t)0x000C)
rajathr 0:34ee385f4d2d 592 #define TIM_DMABase_CCR1_MORT ((uint16_t)0x000D)
rajathr 0:34ee385f4d2d 593 #define TIM_DMABase_CCR2_MORT ((uint16_t)0x000E)
rajathr 0:34ee385f4d2d 594 #define TIM_DMABase_CCR3_MORT ((uint16_t)0x000F)
rajathr 0:34ee385f4d2d 595 #define TIM_DMABase_CCR4_MORT ((uint16_t)0x0010)
rajathr 0:34ee385f4d2d 596 #define TIM_DMABase_BDTR_MORT ((uint16_t)0x0011)
rajathr 0:34ee385f4d2d 597 #define TIM_DMABase_DCR_MORT ((uint16_t)0x0012)
rajathr 0:34ee385f4d2d 598 #define TIM_DMABase_OR_MORT ((uint16_t)0x0013)
rajathr 0:34ee385f4d2d 599 #define IS_TIM_DMA_BASE_MORT(BASE) (((BASE) == TIM_DMABase_CR1_MORT) || \
rajathr 0:34ee385f4d2d 600 ((BASE) == TIM_DMABase_CR2_MORT) || \
rajathr 0:34ee385f4d2d 601 ((BASE) == TIM_DMABase_SMCR_MORT) || \
rajathr 0:34ee385f4d2d 602 ((BASE) == TIM_DMABase_DIER_MORT) || \
rajathr 0:34ee385f4d2d 603 ((BASE) == TIM_DMABase_SR_MORT) || \
rajathr 0:34ee385f4d2d 604 ((BASE) == TIM_DMABase_EGR_MORT) || \
rajathr 0:34ee385f4d2d 605 ((BASE) == TIM_DMABase_CCMR1_MORT) || \
rajathr 0:34ee385f4d2d 606 ((BASE) == TIM_DMABase_CCMR2_MORT) || \
rajathr 0:34ee385f4d2d 607 ((BASE) == TIM_DMABase_CCER_MORT) || \
rajathr 0:34ee385f4d2d 608 ((BASE) == TIM_DMABase_CNT_MORT) || \
rajathr 0:34ee385f4d2d 609 ((BASE) == TIM_DMABase_PSC_MORT) || \
rajathr 0:34ee385f4d2d 610 ((BASE) == TIM_DMABase_ARR_MORT) || \
rajathr 0:34ee385f4d2d 611 ((BASE) == TIM_DMABase_RCR_MORT) || \
rajathr 0:34ee385f4d2d 612 ((BASE) == TIM_DMABase_CCR1_MORT) || \
rajathr 0:34ee385f4d2d 613 ((BASE) == TIM_DMABase_CCR2_MORT) || \
rajathr 0:34ee385f4d2d 614 ((BASE) == TIM_DMABase_CCR3_MORT) || \
rajathr 0:34ee385f4d2d 615 ((BASE) == TIM_DMABase_CCR4_MORT) || \
rajathr 0:34ee385f4d2d 616 ((BASE) == TIM_DMABase_BDTR_MORT) || \
rajathr 0:34ee385f4d2d 617 ((BASE) == TIM_DMABase_DCR_MORT) || \
rajathr 0:34ee385f4d2d 618 ((BASE) == TIM_DMABase_OR_MORT))
rajathr 0:34ee385f4d2d 619 /**
rajathr 0:34ee385f4d2d 620 * @}
rajathr 0:34ee385f4d2d 621 */
rajathr 0:34ee385f4d2d 622
rajathr 0:34ee385f4d2d 623 /** @defgroup TIM_DMA_Burst_Length
rajathr 0:34ee385f4d2d 624 * @{
rajathr 0:34ee385f4d2d 625 */
rajathr 0:34ee385f4d2d 626
rajathr 0:34ee385f4d2d 627 #define TIM_DMABurstLength_1Transfer_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 628 #define TIM_DMABurstLength_2Transfers_MORT ((uint16_t)0x0100)
rajathr 0:34ee385f4d2d 629 #define TIM_DMABurstLength_3Transfers_MORT ((uint16_t)0x0200)
rajathr 0:34ee385f4d2d 630 #define TIM_DMABurstLength_4Transfers_MORT ((uint16_t)0x0300)
rajathr 0:34ee385f4d2d 631 #define TIM_DMABurstLength_5Transfers_MORT ((uint16_t)0x0400)
rajathr 0:34ee385f4d2d 632 #define TIM_DMABurstLength_6Transfers_MORT ((uint16_t)0x0500)
rajathr 0:34ee385f4d2d 633 #define TIM_DMABurstLength_7Transfers_MORT ((uint16_t)0x0600)
rajathr 0:34ee385f4d2d 634 #define TIM_DMABurstLength_8Transfers_MORT ((uint16_t)0x0700)
rajathr 0:34ee385f4d2d 635 #define TIM_DMABurstLength_9Transfers_MORT ((uint16_t)0x0800)
rajathr 0:34ee385f4d2d 636 #define TIM_DMABurstLength_10Transfers_MORT ((uint16_t)0x0900)
rajathr 0:34ee385f4d2d 637 #define TIM_DMABurstLength_11Transfers_MORT ((uint16_t)0x0A00)
rajathr 0:34ee385f4d2d 638 #define TIM_DMABurstLength_12Transfers_MORT ((uint16_t)0x0B00)
rajathr 0:34ee385f4d2d 639 #define TIM_DMABurstLength_13Transfers_MORT ((uint16_t)0x0C00)
rajathr 0:34ee385f4d2d 640 #define TIM_DMABurstLength_14Transfers_MORT ((uint16_t)0x0D00)
rajathr 0:34ee385f4d2d 641 #define TIM_DMABurstLength_15Transfers_MORT ((uint16_t)0x0E00)
rajathr 0:34ee385f4d2d 642 #define TIM_DMABurstLength_16Transfers_MORT ((uint16_t)0x0F00)
rajathr 0:34ee385f4d2d 643 #define TIM_DMABurstLength_17Transfers_MORT ((uint16_t)0x1000)
rajathr 0:34ee385f4d2d 644 #define TIM_DMABurstLength_18Transfers_MORT ((uint16_t)0x1100)
rajathr 0:34ee385f4d2d 645 #define IS_TIM_DMA_LENGTH_MORT(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer_MORT) || \
rajathr 0:34ee385f4d2d 646 ((LENGTH) == TIM_DMABurstLength_2Transfers_MORT) || \
rajathr 0:34ee385f4d2d 647 ((LENGTH) == TIM_DMABurstLength_3Transfers_MORT) || \
rajathr 0:34ee385f4d2d 648 ((LENGTH) == TIM_DMABurstLength_4Transfers_MORT) || \
rajathr 0:34ee385f4d2d 649 ((LENGTH) == TIM_DMABurstLength_5Transfers_MORT) || \
rajathr 0:34ee385f4d2d 650 ((LENGTH) == TIM_DMABurstLength_6Transfers_MORT) || \
rajathr 0:34ee385f4d2d 651 ((LENGTH) == TIM_DMABurstLength_7Transfers_MORT) || \
rajathr 0:34ee385f4d2d 652 ((LENGTH) == TIM_DMABurstLength_8Transfers_MORT) || \
rajathr 0:34ee385f4d2d 653 ((LENGTH) == TIM_DMABurstLength_9Transfers_MORT) || \
rajathr 0:34ee385f4d2d 654 ((LENGTH) == TIM_DMABurstLength_10Transfers_MORT) || \
rajathr 0:34ee385f4d2d 655 ((LENGTH) == TIM_DMABurstLength_11Transfers_MORT) || \
rajathr 0:34ee385f4d2d 656 ((LENGTH) == TIM_DMABurstLength_12Transfers_MORT) || \
rajathr 0:34ee385f4d2d 657 ((LENGTH) == TIM_DMABurstLength_13Transfers_MORT) || \
rajathr 0:34ee385f4d2d 658 ((LENGTH) == TIM_DMABurstLength_14Transfers_MORT) || \
rajathr 0:34ee385f4d2d 659 ((LENGTH) == TIM_DMABurstLength_15Transfers_MORT) || \
rajathr 0:34ee385f4d2d 660 ((LENGTH) == TIM_DMABurstLength_16Transfers_MORT) || \
rajathr 0:34ee385f4d2d 661 ((LENGTH) == TIM_DMABurstLength_17Transfers_MORT) || \
rajathr 0:34ee385f4d2d 662 ((LENGTH) == TIM_DMABurstLength_18Transfers_MORT))
rajathr 0:34ee385f4d2d 663 /**
rajathr 0:34ee385f4d2d 664 * @}
rajathr 0:34ee385f4d2d 665 */
rajathr 0:34ee385f4d2d 666
rajathr 0:34ee385f4d2d 667 /** @defgroup TIM_DMA_sources
rajathr 0:34ee385f4d2d 668 * @{
rajathr 0:34ee385f4d2d 669 */
rajathr 0:34ee385f4d2d 670
rajathr 0:34ee385f4d2d 671 #define TIM_DMA_Update_MORT ((uint16_t)0x0100)
rajathr 0:34ee385f4d2d 672 #define TIM_DMA_CC1_MORT ((uint16_t)0x0200)
rajathr 0:34ee385f4d2d 673 #define TIM_DMA_CC2_MORT ((uint16_t)0x0400)
rajathr 0:34ee385f4d2d 674 #define TIM_DMA_CC3_MORT ((uint16_t)0x0800)
rajathr 0:34ee385f4d2d 675 #define TIM_DMA_CC4_MORT ((uint16_t)0x1000)
rajathr 0:34ee385f4d2d 676 #define TIM_DMA_COM_MORT ((uint16_t)0x2000)
rajathr 0:34ee385f4d2d 677 #define TIM_DMA_Trigger_MORT ((uint16_t)0x4000)
rajathr 0:34ee385f4d2d 678 #define IS_TIM_DMA_SOURCE_MORT(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
rajathr 0:34ee385f4d2d 679
rajathr 0:34ee385f4d2d 680 /**
rajathr 0:34ee385f4d2d 681 * @}
rajathr 0:34ee385f4d2d 682 */
rajathr 0:34ee385f4d2d 683
rajathr 0:34ee385f4d2d 684 /** @defgroup TIM_External_Trigger_Prescaler
rajathr 0:34ee385f4d2d 685 * @{
rajathr 0:34ee385f4d2d 686 */
rajathr 0:34ee385f4d2d 687
rajathr 0:34ee385f4d2d 688 #define TIM_ExtTRGPSC_OFF_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 689 #define TIM_ExtTRGPSC_DIV2_MORT ((uint16_t)0x1000)
rajathr 0:34ee385f4d2d 690 #define TIM_ExtTRGPSC_DIV4_MORT ((uint16_t)0x2000)
rajathr 0:34ee385f4d2d 691 #define TIM_ExtTRGPSC_DIV8_MORT ((uint16_t)0x3000)
rajathr 0:34ee385f4d2d 692 #define IS_TIM_EXT_PRESCALER_MORT(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF_MORT) || \
rajathr 0:34ee385f4d2d 693 ((PRESCALER) == TIM_ExtTRGPSC_DIV2_MORT) || \
rajathr 0:34ee385f4d2d 694 ((PRESCALER) == TIM_ExtTRGPSC_DIV4_MORT) || \
rajathr 0:34ee385f4d2d 695 ((PRESCALER) == TIM_ExtTRGPSC_DIV8_MORT))
rajathr 0:34ee385f4d2d 696 /**
rajathr 0:34ee385f4d2d 697 * @}
rajathr 0:34ee385f4d2d 698 */
rajathr 0:34ee385f4d2d 699
rajathr 0:34ee385f4d2d 700 /** @defgroup TIM_Internal_Trigger_Selection
rajathr 0:34ee385f4d2d 701 * @{
rajathr 0:34ee385f4d2d 702 */
rajathr 0:34ee385f4d2d 703
rajathr 0:34ee385f4d2d 704 #define TIM_TS_ITR0_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 705 #define TIM_TS_ITR1_MORT ((uint16_t)0x0010)
rajathr 0:34ee385f4d2d 706 #define TIM_TS_ITR2_MORT ((uint16_t)0x0020)
rajathr 0:34ee385f4d2d 707 #define TIM_TS_ITR3_MORT ((uint16_t)0x0030)
rajathr 0:34ee385f4d2d 708 #define TIM_TS_TI1F_ED_MORT ((uint16_t)0x0040)
rajathr 0:34ee385f4d2d 709 #define TIM_TS_TI1FP1_MORT ((uint16_t)0x0050)
rajathr 0:34ee385f4d2d 710 #define TIM_TS_TI2FP2_MORT ((uint16_t)0x0060)
rajathr 0:34ee385f4d2d 711 #define TIM_TS_ETRF_MORT ((uint16_t)0x0070)
rajathr 0:34ee385f4d2d 712 #define IS_TIM_TRIGGER_SELECTION_MORT(SELECTION) (((SELECTION) == TIM_TS_ITR0_MORT) || \
rajathr 0:34ee385f4d2d 713 ((SELECTION) == TIM_TS_ITR1_MORT) || \
rajathr 0:34ee385f4d2d 714 ((SELECTION) == TIM_TS_ITR2_MORT) || \
rajathr 0:34ee385f4d2d 715 ((SELECTION) == TIM_TS_ITR3_MORT) || \
rajathr 0:34ee385f4d2d 716 ((SELECTION) == TIM_TS_TI1F_ED_MORT) || \
rajathr 0:34ee385f4d2d 717 ((SELECTION) == TIM_TS_TI1FP1_MORT) || \
rajathr 0:34ee385f4d2d 718 ((SELECTION) == TIM_TS_TI2FP2_MORT) || \
rajathr 0:34ee385f4d2d 719 ((SELECTION) == TIM_TS_ETRF_MORT))
rajathr 0:34ee385f4d2d 720 #define IS_TIM_INTERNAL_TRIGGER_SELECTION_MORT(SELECTION) (((SELECTION) == TIM_TS_ITR0_MORT) || \
rajathr 0:34ee385f4d2d 721 ((SELECTION) == TIM_TS_ITR1_MORT) || \
rajathr 0:34ee385f4d2d 722 ((SELECTION) == TIM_TS_ITR2_MORT) || \
rajathr 0:34ee385f4d2d 723 ((SELECTION) == TIM_TS_ITR3_MORT))
rajathr 0:34ee385f4d2d 724 /**
rajathr 0:34ee385f4d2d 725 * @}
rajathr 0:34ee385f4d2d 726 */
rajathr 0:34ee385f4d2d 727
rajathr 0:34ee385f4d2d 728 /** @defgroup TIM_TIx_External_Clock_Source
rajathr 0:34ee385f4d2d 729 * @{
rajathr 0:34ee385f4d2d 730 */
rajathr 0:34ee385f4d2d 731
rajathr 0:34ee385f4d2d 732 #define TIM_TIxExternalCLK1Source_TI1_MORT ((uint16_t)0x0050)
rajathr 0:34ee385f4d2d 733 #define TIM_TIxExternalCLK1Source_TI2_MORT ((uint16_t)0x0060)
rajathr 0:34ee385f4d2d 734 #define TIM_TIxExternalCLK1Source_TI1ED_MORT ((uint16_t)0x0040)
rajathr 0:34ee385f4d2d 735
rajathr 0:34ee385f4d2d 736 /**
rajathr 0:34ee385f4d2d 737 * @}
rajathr 0:34ee385f4d2d 738 */
rajathr 0:34ee385f4d2d 739
rajathr 0:34ee385f4d2d 740 /** @defgroup TIM_External_Trigger_Polarity
rajathr 0:34ee385f4d2d 741 * @{
rajathr 0:34ee385f4d2d 742 */
rajathr 0:34ee385f4d2d 743 #define TIM_ExtTRGPolarity_Inverted_MORT ((uint16_t)0x8000)
rajathr 0:34ee385f4d2d 744 #define TIM_ExtTRGPolarity_NonInverted_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 745 #define IS_TIM_EXT_POLARITY_MORT(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted_MORT) || \
rajathr 0:34ee385f4d2d 746 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted_MORT))
rajathr 0:34ee385f4d2d 747 /**
rajathr 0:34ee385f4d2d 748 * @}
rajathr 0:34ee385f4d2d 749 */
rajathr 0:34ee385f4d2d 750
rajathr 0:34ee385f4d2d 751 /** @defgroup TIM_Prescaler_Reload_Mode
rajathr 0:34ee385f4d2d 752 * @{
rajathr 0:34ee385f4d2d 753 */
rajathr 0:34ee385f4d2d 754
rajathr 0:34ee385f4d2d 755 #define TIM_PSCReloadMode_Update_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 756 #define TIM_PSCReloadMode_Immediate_MORT ((uint16_t)0x0001)
rajathr 0:34ee385f4d2d 757 #define IS_TIM_PRESCALER_RELOAD_MORT(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update_MORT) || \
rajathr 0:34ee385f4d2d 758 ((RELOAD) == TIM_PSCReloadMode_Immediate_MORT))
rajathr 0:34ee385f4d2d 759 /**
rajathr 0:34ee385f4d2d 760 * @}
rajathr 0:34ee385f4d2d 761 */
rajathr 0:34ee385f4d2d 762
rajathr 0:34ee385f4d2d 763 /** @defgroup TIM_Forced_Action
rajathr 0:34ee385f4d2d 764 * @{
rajathr 0:34ee385f4d2d 765 */
rajathr 0:34ee385f4d2d 766
rajathr 0:34ee385f4d2d 767 #define TIM_ForcedAction_Active_MORT ((uint16_t)0x0050)
rajathr 0:34ee385f4d2d 768 #define TIM_ForcedAction_InActive_MORT ((uint16_t)0x0040)
rajathr 0:34ee385f4d2d 769 #define IS_TIM_FORCED_ACTION_MORT(ACTION) (((ACTION) == TIM_ForcedAction_Active_MORT) || \
rajathr 0:34ee385f4d2d 770 ((ACTION) == TIM_ForcedAction_InActive_MORT))
rajathr 0:34ee385f4d2d 771 /**
rajathr 0:34ee385f4d2d 772 * @}
rajathr 0:34ee385f4d2d 773 */
rajathr 0:34ee385f4d2d 774
rajathr 0:34ee385f4d2d 775 /** @defgroup TIM_Encoder_Mode
rajathr 0:34ee385f4d2d 776 * @{
rajathr 0:34ee385f4d2d 777 */
rajathr 0:34ee385f4d2d 778
rajathr 0:34ee385f4d2d 779 #define TIM_EncoderMode_TI1_MORT ((uint16_t)0x0001)
rajathr 0:34ee385f4d2d 780 #define TIM_EncoderMode_TI2_MORT ((uint16_t)0x0002)
rajathr 0:34ee385f4d2d 781 #define TIM_EncoderMode_TI12_MORT ((uint16_t)0x0003)
rajathr 0:34ee385f4d2d 782 #define IS_TIM_ENCODER_MODE_MORT(MODE) (((MODE) == TIM_EncoderMode_TI1_MORT) || \
rajathr 0:34ee385f4d2d 783 ((MODE) == TIM_EncoderMode_TI2_MORT) || \
rajathr 0:34ee385f4d2d 784 ((MODE) == TIM_EncoderMode_TI12_MORT))
rajathr 0:34ee385f4d2d 785 /**
rajathr 0:34ee385f4d2d 786 * @}
rajathr 0:34ee385f4d2d 787 */
rajathr 0:34ee385f4d2d 788
rajathr 0:34ee385f4d2d 789
rajathr 0:34ee385f4d2d 790 /** @defgroup TIM_Event_Source
rajathr 0:34ee385f4d2d 791 * @{
rajathr 0:34ee385f4d2d 792 */
rajathr 0:34ee385f4d2d 793
rajathr 0:34ee385f4d2d 794 #define TIM_EventSource_Update_MORT ((uint16_t)0x0001)
rajathr 0:34ee385f4d2d 795 #define TIM_EventSource_CC1_MORT ((uint16_t)0x0002)
rajathr 0:34ee385f4d2d 796 #define TIM_EventSource_CC2_MORT ((uint16_t)0x0004)
rajathr 0:34ee385f4d2d 797 #define TIM_EventSource_CC3_MORT ((uint16_t)0x0008)
rajathr 0:34ee385f4d2d 798 #define TIM_EventSource_CC4_MORT ((uint16_t)0x0010)
rajathr 0:34ee385f4d2d 799 #define TIM_EventSource_COM_MORT ((uint16_t)0x0020)
rajathr 0:34ee385f4d2d 800 #define TIM_EventSource_Trigger_MORT ((uint16_t)0x0040)
rajathr 0:34ee385f4d2d 801 #define TIM_EventSource_Break_MORT ((uint16_t)0x0080)
rajathr 0:34ee385f4d2d 802 #define IS_TIM_EVENT_SOURCE_MORT(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
rajathr 0:34ee385f4d2d 803
rajathr 0:34ee385f4d2d 804 /**
rajathr 0:34ee385f4d2d 805 * @}
rajathr 0:34ee385f4d2d 806 */
rajathr 0:34ee385f4d2d 807
rajathr 0:34ee385f4d2d 808 /** @defgroup TIM_Update_Source
rajathr 0:34ee385f4d2d 809 * @{
rajathr 0:34ee385f4d2d 810 */
rajathr 0:34ee385f4d2d 811
rajathr 0:34ee385f4d2d 812 #define TIM_UpdateSource_Global_MORT ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
rajathr 0:34ee385f4d2d 813 or the setting of UG bit, or an update generation
rajathr 0:34ee385f4d2d 814 through the slave mode controller. */
rajathr 0:34ee385f4d2d 815 #define TIM_UpdateSource_Regular_MORT ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
rajathr 0:34ee385f4d2d 816 #define IS_TIM_UPDATE_SOURCE_MORT(SOURCE) (((SOURCE) == TIM_UpdateSource_Global_MORT) || \
rajathr 0:34ee385f4d2d 817 ((SOURCE) == TIM_UpdateSource_Regular_MORT))
rajathr 0:34ee385f4d2d 818 /**
rajathr 0:34ee385f4d2d 819 * @}
rajathr 0:34ee385f4d2d 820 */
rajathr 0:34ee385f4d2d 821
rajathr 0:34ee385f4d2d 822 /** @defgroup TIM_Output_Compare_Preload_State
rajathr 0:34ee385f4d2d 823 * @{
rajathr 0:34ee385f4d2d 824 */
rajathr 0:34ee385f4d2d 825
rajathr 0:34ee385f4d2d 826 #define TIM_OCPreload_Enable_MORT ((uint16_t)0x0008)
rajathr 0:34ee385f4d2d 827 #define TIM_OCPreload_Disable_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 828 #define IS_TIM_OCPRELOAD_STATE_MORT(STATE) (((STATE) == TIM_OCPreload_Enable_MORT) || \
rajathr 0:34ee385f4d2d 829 ((STATE) == TIM_OCPreload_Disable_MORT))
rajathr 0:34ee385f4d2d 830 /**
rajathr 0:34ee385f4d2d 831 * @}
rajathr 0:34ee385f4d2d 832 */
rajathr 0:34ee385f4d2d 833
rajathr 0:34ee385f4d2d 834 /** @defgroup TIM_Output_Compare_Fast_State
rajathr 0:34ee385f4d2d 835 * @{
rajathr 0:34ee385f4d2d 836 */
rajathr 0:34ee385f4d2d 837
rajathr 0:34ee385f4d2d 838 #define TIM_OCFast_Enable_MORT ((uint16_t)0x0004)
rajathr 0:34ee385f4d2d 839 #define TIM_OCFast_Disable_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 840 #define IS_TIM_OCFAST_STATE_MORT(STATE) (((STATE) == TIM_OCFast_Enable_MORT) || \
rajathr 0:34ee385f4d2d 841 ((STATE) == TIM_OCFast_Disable_MORT))
rajathr 0:34ee385f4d2d 842
rajathr 0:34ee385f4d2d 843 /**
rajathr 0:34ee385f4d2d 844 * @}
rajathr 0:34ee385f4d2d 845 */
rajathr 0:34ee385f4d2d 846
rajathr 0:34ee385f4d2d 847 /** @defgroup TIM_Output_Compare_Clear_State
rajathr 0:34ee385f4d2d 848 * @{
rajathr 0:34ee385f4d2d 849 */
rajathr 0:34ee385f4d2d 850
rajathr 0:34ee385f4d2d 851 #define TIM_OCClear_Enable_MORT ((uint16_t)0x0080)
rajathr 0:34ee385f4d2d 852 #define TIM_OCClear_Disable_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 853 #define IS_TIM_OCCLEAR_STATE_MORT(STATE) (((STATE) == TIM_OCClear_Enable_MORT) || \
rajathr 0:34ee385f4d2d 854 ((STATE) == TIM_OCClear_Disable_MORT))
rajathr 0:34ee385f4d2d 855 /**
rajathr 0:34ee385f4d2d 856 * @}
rajathr 0:34ee385f4d2d 857 */
rajathr 0:34ee385f4d2d 858
rajathr 0:34ee385f4d2d 859 /** @defgroup TIM_Trigger_Output_Source
rajathr 0:34ee385f4d2d 860 * @{
rajathr 0:34ee385f4d2d 861 */
rajathr 0:34ee385f4d2d 862
rajathr 0:34ee385f4d2d 863 #define TIM_TRGOSource_Reset_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 864 #define TIM_TRGOSource_Enable_MORT ((uint16_t)0x0010)
rajathr 0:34ee385f4d2d 865 #define TIM_TRGOSource_Update_MORT ((uint16_t)0x0020)
rajathr 0:34ee385f4d2d 866 #define TIM_TRGOSource_OC1_MORT ((uint16_t)0x0030)
rajathr 0:34ee385f4d2d 867 #define TIM_TRGOSource_OC1Ref_MORT ((uint16_t)0x0040)
rajathr 0:34ee385f4d2d 868 #define TIM_TRGOSource_OC2Ref_MORT ((uint16_t)0x0050)
rajathr 0:34ee385f4d2d 869 #define TIM_TRGOSource_OC3Ref_MORT ((uint16_t)0x0060)
rajathr 0:34ee385f4d2d 870 #define TIM_TRGOSource_OC4Ref_MORT ((uint16_t)0x0070)
rajathr 0:34ee385f4d2d 871 #define IS_TIM_TRGO_SOURCE_MORT(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset_MORT) || \
rajathr 0:34ee385f4d2d 872 ((SOURCE) == TIM_TRGOSource_Enable_MORT) || \
rajathr 0:34ee385f4d2d 873 ((SOURCE) == TIM_TRGOSource_Update_MORT) || \
rajathr 0:34ee385f4d2d 874 ((SOURCE) == TIM_TRGOSource_OC1_MORT) || \
rajathr 0:34ee385f4d2d 875 ((SOURCE) == TIM_TRGOSource_OC1Ref_MORT) || \
rajathr 0:34ee385f4d2d 876 ((SOURCE) == TIM_TRGOSource_OC2Ref_MORT) || \
rajathr 0:34ee385f4d2d 877 ((SOURCE) == TIM_TRGOSource_OC3Ref_MORT) || \
rajathr 0:34ee385f4d2d 878 ((SOURCE) == TIM_TRGOSource_OC4Ref_MORT))
rajathr 0:34ee385f4d2d 879 /**
rajathr 0:34ee385f4d2d 880 * @}
rajathr 0:34ee385f4d2d 881 */
rajathr 0:34ee385f4d2d 882
rajathr 0:34ee385f4d2d 883 /** @defgroup TIM_Slave_Mode
rajathr 0:34ee385f4d2d 884 * @{
rajathr 0:34ee385f4d2d 885 */
rajathr 0:34ee385f4d2d 886
rajathr 0:34ee385f4d2d 887 #define TIM_SlaveMode_Reset_MORT ((uint16_t)0x0004)
rajathr 0:34ee385f4d2d 888 #define TIM_SlaveMode_Gated_MORT ((uint16_t)0x0005)
rajathr 0:34ee385f4d2d 889 #define TIM_SlaveMode_Trigger_MORT ((uint16_t)0x0006)
rajathr 0:34ee385f4d2d 890 #define TIM_SlaveMode_External1_MORT ((uint16_t)0x0007)
rajathr 0:34ee385f4d2d 891 #define IS_TIM_SLAVE_MODE_MORT(MODE) (((MODE) == TIM_SlaveMode_Reset_MORT) || \
rajathr 0:34ee385f4d2d 892 ((MODE) == TIM_SlaveMode_Gated_MORT) || \
rajathr 0:34ee385f4d2d 893 ((MODE) == TIM_SlaveMode_Trigger_MORT) || \
rajathr 0:34ee385f4d2d 894 ((MODE) == TIM_SlaveMode_External1_MORT))
rajathr 0:34ee385f4d2d 895 /**
rajathr 0:34ee385f4d2d 896 * @}
rajathr 0:34ee385f4d2d 897 */
rajathr 0:34ee385f4d2d 898
rajathr 0:34ee385f4d2d 899 /** @defgroup TIM_Master_Slave_Mode
rajathr 0:34ee385f4d2d 900 * @{
rajathr 0:34ee385f4d2d 901 */
rajathr 0:34ee385f4d2d 902
rajathr 0:34ee385f4d2d 903 #define TIM_MasterSlaveMode_Enable_MORT ((uint16_t)0x0080)
rajathr 0:34ee385f4d2d 904 #define TIM_MasterSlaveMode_Disable_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 905 #define IS_TIM_MSM_STATE_MORT(STATE) (((STATE) == TIM_MasterSlaveMode_Enable_MORT) || \
rajathr 0:34ee385f4d2d 906 ((STATE) == TIM_MasterSlaveMode_Disable_MORT))
rajathr 0:34ee385f4d2d 907 /**
rajathr 0:34ee385f4d2d 908 * @}
rajathr 0:34ee385f4d2d 909 */
rajathr 0:34ee385f4d2d 910 /** @defgroup TIM_Remap
rajathr 0:34ee385f4d2d 911 * @{
rajathr 0:34ee385f4d2d 912 */
rajathr 0:34ee385f4d2d 913
rajathr 0:34ee385f4d2d 914 #define TIM2_TIM8_TRGO_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 915 #define TIM2_ETH_PTP_MORT ((uint16_t)0x0400)
rajathr 0:34ee385f4d2d 916 #define TIM2_USBFS_SOF_MORT ((uint16_t)0x0800)
rajathr 0:34ee385f4d2d 917 #define TIM2_USBHS_SOF_MORT ((uint16_t)0x0C00)
rajathr 0:34ee385f4d2d 918
rajathr 0:34ee385f4d2d 919 #define TIM5_GPIO_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 920 #define TIM5_LSI_MORT ((uint16_t)0x0040)
rajathr 0:34ee385f4d2d 921 #define TIM5_LSE_MORT ((uint16_t)0x0080)
rajathr 0:34ee385f4d2d 922 #define TIM5_RTC_MORT ((uint16_t)0x00C0)
rajathr 0:34ee385f4d2d 923
rajathr 0:34ee385f4d2d 924 #define TIM11_GPIO_MORT ((uint16_t)0x0000)
rajathr 0:34ee385f4d2d 925 #define TIM11_HSE_MORT ((uint16_t)0x0002)
rajathr 0:34ee385f4d2d 926
rajathr 0:34ee385f4d2d 927 #define IS_TIM_REMAP_MORT(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO_MORT)||\
rajathr 0:34ee385f4d2d 928 ((TIM_REMAP) == TIM2_ETH_PTP_MORT)||\
rajathr 0:34ee385f4d2d 929 ((TIM_REMAP) == TIM2_USBFS_SOF_MORT)||\
rajathr 0:34ee385f4d2d 930 ((TIM_REMAP) == TIM2_USBHS_SOF_MORT)||\
rajathr 0:34ee385f4d2d 931 ((TIM_REMAP) == TIM5_GPIO_MORT)||\
rajathr 0:34ee385f4d2d 932 ((TIM_REMAP) == TIM5_LSI_MORT)||\
rajathr 0:34ee385f4d2d 933 ((TIM_REMAP) == TIM5_LSE_MORT)||\
rajathr 0:34ee385f4d2d 934 ((TIM_REMAP) == TIM5_RTC_MORT)||\
rajathr 0:34ee385f4d2d 935 ((TIM_REMAP) == TIM11_GPIO_MORT)||\
rajathr 0:34ee385f4d2d 936 ((TIM_REMAP) == TIM11_HSE_MORT))
rajathr 0:34ee385f4d2d 937
rajathr 0:34ee385f4d2d 938 /**
rajathr 0:34ee385f4d2d 939 * @}
rajathr 0:34ee385f4d2d 940 */
rajathr 0:34ee385f4d2d 941 /** @defgroup TIM_Flags
rajathr 0:34ee385f4d2d 942 * @{
rajathr 0:34ee385f4d2d 943 */
rajathr 0:34ee385f4d2d 944
rajathr 0:34ee385f4d2d 945 #define TIM_FLAG_Update_MORT ((uint16_t)0x0001)
rajathr 0:34ee385f4d2d 946 #define TIM_FLAG_CC1_MORT ((uint16_t)0x0002)
rajathr 0:34ee385f4d2d 947 #define TIM_FLAG_CC2_MORT ((uint16_t)0x0004)
rajathr 0:34ee385f4d2d 948 #define TIM_FLAG_CC3_MORT ((uint16_t)0x0008)
rajathr 0:34ee385f4d2d 949 #define TIM_FLAG_CC4_MORT ((uint16_t)0x0010)
rajathr 0:34ee385f4d2d 950 #define TIM_FLAG_COM_MORT ((uint16_t)0x0020)
rajathr 0:34ee385f4d2d 951 #define TIM_FLAG_Trigger_MORT ((uint16_t)0x0040)
rajathr 0:34ee385f4d2d 952 #define TIM_FLAG_Break_MORT ((uint16_t)0x0080)
rajathr 0:34ee385f4d2d 953 #define TIM_FLAG_CC1OF_MORT ((uint16_t)0x0200)
rajathr 0:34ee385f4d2d 954 #define TIM_FLAG_CC2OF_MORT ((uint16_t)0x0400)
rajathr 0:34ee385f4d2d 955 #define TIM_FLAG_CC3OF_MORT ((uint16_t)0x0800)
rajathr 0:34ee385f4d2d 956 #define TIM_FLAG_CC4OF_MORT ((uint16_t)0x1000)
rajathr 0:34ee385f4d2d 957 #define IS_TIM_GET_FLAG_MORT(FLAG) (((FLAG) == TIM_FLAG_Update_MORT) || \
rajathr 0:34ee385f4d2d 958 ((FLAG) == TIM_FLAG_CC1_MORT) || \
rajathr 0:34ee385f4d2d 959 ((FLAG) == TIM_FLAG_CC2_MORT) || \
rajathr 0:34ee385f4d2d 960 ((FLAG) == TIM_FLAG_CC3_MORT) || \
rajathr 0:34ee385f4d2d 961 ((FLAG) == TIM_FLAG_CC4_MORT) || \
rajathr 0:34ee385f4d2d 962 ((FLAG) == TIM_FLAG_COM_MORT) || \
rajathr 0:34ee385f4d2d 963 ((FLAG) == TIM_FLAG_Trigger_MORT) || \
rajathr 0:34ee385f4d2d 964 ((FLAG) == TIM_FLAG_Break_MORT) || \
rajathr 0:34ee385f4d2d 965 ((FLAG) == TIM_FLAG_CC1OF_MORT) || \
rajathr 0:34ee385f4d2d 966 ((FLAG) == TIM_FLAG_CC2OF_MORT) || \
rajathr 0:34ee385f4d2d 967 ((FLAG) == TIM_FLAG_CC3OF_MORT) || \
rajathr 0:34ee385f4d2d 968 ((FLAG) == TIM_FLAG_CC4OF_MORT))
rajathr 0:34ee385f4d2d 969
rajathr 0:34ee385f4d2d 970 /**
rajathr 0:34ee385f4d2d 971 * @}
rajathr 0:34ee385f4d2d 972 */
rajathr 0:34ee385f4d2d 973
rajathr 0:34ee385f4d2d 974 /** @defgroup TIM_Input_Capture_Filer_Value
rajathr 0:34ee385f4d2d 975 * @{
rajathr 0:34ee385f4d2d 976 */
rajathr 0:34ee385f4d2d 977
rajathr 0:34ee385f4d2d 978 #define IS_TIM_IC_FILTER_MORT(ICFILTER) ((ICFILTER) <= 0xF)
rajathr 0:34ee385f4d2d 979 /**
rajathr 0:34ee385f4d2d 980 * @}
rajathr 0:34ee385f4d2d 981 */
rajathr 0:34ee385f4d2d 982
rajathr 0:34ee385f4d2d 983 /** @defgroup TIM_External_Trigger_Filter
rajathr 0:34ee385f4d2d 984 * @{
rajathr 0:34ee385f4d2d 985 */
rajathr 0:34ee385f4d2d 986
rajathr 0:34ee385f4d2d 987 #define IS_TIM_EXT_FILTER_MORT(EXTFILTER) ((EXTFILTER) <= 0xF)
rajathr 0:34ee385f4d2d 988 /**
rajathr 0:34ee385f4d2d 989 * @}
rajathr 0:34ee385f4d2d 990 */
rajathr 0:34ee385f4d2d 991
rajathr 0:34ee385f4d2d 992 /** @defgroup TIM_Legacy
rajathr 0:34ee385f4d2d 993 * @{
rajathr 0:34ee385f4d2d 994 */
rajathr 0:34ee385f4d2d 995
rajathr 0:34ee385f4d2d 996 #define TIM_DMABurstLength_1Byte_MORT TIM_DMABurstLength_1Transfer_MORT
rajathr 0:34ee385f4d2d 997 #define TIM_DMABurstLength_2Bytes_MORT TIM_DMABurstLength_2Transfers_MORT
rajathr 0:34ee385f4d2d 998 #define TIM_DMABurstLength_3Bytes_MORT TIM_DMABurstLength_3Transfers_MORT
rajathr 0:34ee385f4d2d 999 #define TIM_DMABurstLength_4Bytes_MORT TIM_DMABurstLength_4Transfers_MORT
rajathr 0:34ee385f4d2d 1000 #define TIM_DMABurstLength_5Bytes_MORT TIM_DMABurstLength_5Transfers_MORT
rajathr 0:34ee385f4d2d 1001 #define TIM_DMABurstLength_6Bytes_MORT TIM_DMABurstLength_6Transfers_MORT
rajathr 0:34ee385f4d2d 1002 #define TIM_DMABurstLength_7Bytes_MORT TIM_DMABurstLength_7Transfers_MORT
rajathr 0:34ee385f4d2d 1003 #define TIM_DMABurstLength_8Bytes_MORT TIM_DMABurstLength_8Transfers_MORT
rajathr 0:34ee385f4d2d 1004 #define TIM_DMABurstLength_9Bytes_MORT TIM_DMABurstLength_9Transfers_MORT
rajathr 0:34ee385f4d2d 1005 #define TIM_DMABurstLength_10Bytes_MORT TIM_DMABurstLength_10Transfers_MORT
rajathr 0:34ee385f4d2d 1006 #define TIM_DMABurstLength_11Bytes_MORT TIM_DMABurstLength_11Transfers_MORT
rajathr 0:34ee385f4d2d 1007 #define TIM_DMABurstLength_12Bytes_MORT TIM_DMABurstLength_12Transfers_MORT
rajathr 0:34ee385f4d2d 1008 #define TIM_DMABurstLength_13Bytes_MORT TIM_DMABurstLength_13Transfers_MORT
rajathr 0:34ee385f4d2d 1009 #define TIM_DMABurstLength_14Bytes_MORT TIM_DMABurstLength_14Transfers_MORT
rajathr 0:34ee385f4d2d 1010 #define TIM_DMABurstLength_15Bytes_MORT TIM_DMABurstLength_15Transfers_MORT
rajathr 0:34ee385f4d2d 1011 #define TIM_DMABurstLength_16Bytes_MORT TIM_DMABurstLength_16Transfers_MORT
rajathr 0:34ee385f4d2d 1012 #define TIM_DMABurstLength_17Bytes_MORT TIM_DMABurstLength_17Transfers_MORT
rajathr 0:34ee385f4d2d 1013 #define TIM_DMABurstLength_18Bytes_MORT TIM_DMABurstLength_18Transfers_MORT
rajathr 0:34ee385f4d2d 1014 /**
rajathr 0:34ee385f4d2d 1015 * @}
rajathr 0:34ee385f4d2d 1016 */
rajathr 0:34ee385f4d2d 1017
rajathr 0:34ee385f4d2d 1018 /**
rajathr 0:34ee385f4d2d 1019 * @}
rajathr 0:34ee385f4d2d 1020 */
rajathr 0:34ee385f4d2d 1021
rajathr 0:34ee385f4d2d 1022 /* Exported macro ------------------------------------------------------------*/
rajathr 0:34ee385f4d2d 1023 /* Exported functions --------------------------------------------------------*/
rajathr 0:34ee385f4d2d 1024
rajathr 0:34ee385f4d2d 1025 /* TimeBase management ********************************************************/
rajathr 0:34ee385f4d2d 1026 void TIM_DeInit_mort(TIM_TypeDef_mort* TIMx);
rajathr 0:34ee385f4d2d 1027 void TIM_TimeBaseInit_mort(TIM_TypeDef_mort* TIMx, TIM_TimeBaseInitTypeDef_mort* TIM_TimeBaseInitStruct);
rajathr 0:34ee385f4d2d 1028 void TIM_TimeBaseStructInit_mort(TIM_TimeBaseInitTypeDef_mort* TIM_TimeBaseInitStruct);
rajathr 0:34ee385f4d2d 1029 void TIM_PrescalerConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
rajathr 0:34ee385f4d2d 1030 void TIM_CounterModeConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_CounterMode);
rajathr 0:34ee385f4d2d 1031 void TIM_SetCounter_mort(TIM_TypeDef_mort* TIMx, uint32_t Counter);
rajathr 0:34ee385f4d2d 1032 void TIM_SetAutoreload_mort(TIM_TypeDef_mort* TIMx, uint32_t Autoreload);
rajathr 0:34ee385f4d2d 1033 uint32_t TIM_GetCounter_mort(TIM_TypeDef_mort* TIMx);
rajathr 0:34ee385f4d2d 1034 uint16_t TIM_GetPrescaler_mort(TIM_TypeDef_mort* TIMx);
rajathr 0:34ee385f4d2d 1035 void TIM_UpdateDisableConfig_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
rajathr 0:34ee385f4d2d 1036 void TIM_UpdateRequestConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_UpdateSource);
rajathr 0:34ee385f4d2d 1037 void TIM_ARRPreloadConfig_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
rajathr 0:34ee385f4d2d 1038 void TIM_SelectOnePulseMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OPMode);
rajathr 0:34ee385f4d2d 1039 void TIM_SetClockDivision_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_CKD);
rajathr 0:34ee385f4d2d 1040 void TIM_Cmd_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
rajathr 0:34ee385f4d2d 1041
rajathr 0:34ee385f4d2d 1042 /* Output Compare management **************************************************/
rajathr 0:34ee385f4d2d 1043 void TIM_OC1Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct);
rajathr 0:34ee385f4d2d 1044 void TIM_OC2Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct);
rajathr 0:34ee385f4d2d 1045 void TIM_OC3Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct);
rajathr 0:34ee385f4d2d 1046 void TIM_OC4Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct);
rajathr 0:34ee385f4d2d 1047 void TIM_OCStructInit_mort(TIM_OCInitTypeDef_mort* TIM_OCInitStruct);
rajathr 0:34ee385f4d2d 1048 void TIM_SelectOCxM_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
rajathr 0:34ee385f4d2d 1049 void TIM_SetCompare1_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare1);
rajathr 0:34ee385f4d2d 1050 void TIM_SetCompare2_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare2);
rajathr 0:34ee385f4d2d 1051 void TIM_SetCompare3_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare3);
rajathr 0:34ee385f4d2d 1052 void TIM_SetCompare4_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare4);
rajathr 0:34ee385f4d2d 1053 void TIM_ForcedOC1Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction);
rajathr 0:34ee385f4d2d 1054 void TIM_ForcedOC2Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction);
rajathr 0:34ee385f4d2d 1055 void TIM_ForcedOC3Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction);
rajathr 0:34ee385f4d2d 1056 void TIM_ForcedOC4Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction);
rajathr 0:34ee385f4d2d 1057 void TIM_OC1PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload);
rajathr 0:34ee385f4d2d 1058 void TIM_OC2PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload);
rajathr 0:34ee385f4d2d 1059 void TIM_OC3PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload);
rajathr 0:34ee385f4d2d 1060 void TIM_OC4PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload);
rajathr 0:34ee385f4d2d 1061 void TIM_OC1FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast);
rajathr 0:34ee385f4d2d 1062 void TIM_OC2FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast);
rajathr 0:34ee385f4d2d 1063 void TIM_OC3FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast);
rajathr 0:34ee385f4d2d 1064 void TIM_OC4FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast);
rajathr 0:34ee385f4d2d 1065 void TIM_ClearOC1Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear);
rajathr 0:34ee385f4d2d 1066 void TIM_ClearOC2Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear);
rajathr 0:34ee385f4d2d 1067 void TIM_ClearOC3Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear);
rajathr 0:34ee385f4d2d 1068 void TIM_ClearOC4Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear);
rajathr 0:34ee385f4d2d 1069 void TIM_OC1PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity);
rajathr 0:34ee385f4d2d 1070 void TIM_OC1NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity);
rajathr 0:34ee385f4d2d 1071 void TIM_OC2PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity);
rajathr 0:34ee385f4d2d 1072 void TIM_OC2NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity);
rajathr 0:34ee385f4d2d 1073 void TIM_OC3PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity);
rajathr 0:34ee385f4d2d 1074 void TIM_OC3NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity);
rajathr 0:34ee385f4d2d 1075 void TIM_OC4PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity);
rajathr 0:34ee385f4d2d 1076 void TIM_CCxCmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
rajathr 0:34ee385f4d2d 1077 void TIM_CCxNCmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
rajathr 0:34ee385f4d2d 1078
rajathr 0:34ee385f4d2d 1079 /* Input Capture management ***************************************************/
rajathr 0:34ee385f4d2d 1080 void TIM_ICInit_mort(TIM_TypeDef_mort* TIMx, TIM_ICInitTypeDef_mort* TIM_ICInitStruct);
rajathr 0:34ee385f4d2d 1081 void TIM_ICStructInit_mort(TIM_ICInitTypeDef_mort* TIM_ICInitStruct);
rajathr 0:34ee385f4d2d 1082 void TIM_PWMIConfig_mort(TIM_TypeDef_mort* TIMx, TIM_ICInitTypeDef_mort* TIM_ICInitStruct);
rajathr 0:34ee385f4d2d 1083 uint32_t TIM_GetCapture1_mort(TIM_TypeDef_mort* TIMx);
rajathr 0:34ee385f4d2d 1084 uint32_t TIM_GetCapture2_mort(TIM_TypeDef_mort* TIMx);
rajathr 0:34ee385f4d2d 1085 uint32_t TIM_GetCapture3_mort(TIM_TypeDef_mort* TIMx);
rajathr 0:34ee385f4d2d 1086 uint32_t TIM_GetCapture4_mort(TIM_TypeDef_mort* TIMx);
rajathr 0:34ee385f4d2d 1087 void TIM_SetIC1Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC);
rajathr 0:34ee385f4d2d 1088 void TIM_SetIC2Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC);
rajathr 0:34ee385f4d2d 1089 void TIM_SetIC3Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC);
rajathr 0:34ee385f4d2d 1090 void TIM_SetIC4Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC);
rajathr 0:34ee385f4d2d 1091
rajathr 0:34ee385f4d2d 1092 /* Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features ******************/
rajathr 0:34ee385f4d2d 1093 void TIM_BDTRConfig_mort(TIM_TypeDef_mort* TIMx, TIM_BDTRInitTypeDef_mort *TIM_BDTRInitStruct);
rajathr 0:34ee385f4d2d 1094 void TIM_BDTRStructInit_mort(TIM_BDTRInitTypeDef_mort* TIM_BDTRInitStruct);
rajathr 0:34ee385f4d2d 1095 void TIM_CtrlPWMOutputs_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
rajathr 0:34ee385f4d2d 1096 void TIM_SelectCOM_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
rajathr 0:34ee385f4d2d 1097 void TIM_CCPreloadControl_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
rajathr 0:34ee385f4d2d 1098
rajathr 0:34ee385f4d2d 1099 /* Interrupts, DMA and flags management ***************************************/
rajathr 0:34ee385f4d2d 1100 void TIM_ITConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT, FunctionalState NewState);
rajathr 0:34ee385f4d2d 1101 void TIM_GenerateEvent_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_EventSource);
rajathr 0:34ee385f4d2d 1102 FlagStatus TIM_GetFlagStatus_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_FLAG);
rajathr 0:34ee385f4d2d 1103 void TIM_ClearFlag_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_FLAG);
rajathr 0:34ee385f4d2d 1104 ITStatus TIM_GetITStatus_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT);
rajathr 0:34ee385f4d2d 1105 void TIM_ClearITPendingBit_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT);
rajathr 0:34ee385f4d2d 1106 void TIM_DMAConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
rajathr 0:34ee385f4d2d 1107 void TIM_DMACmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
rajathr 0:34ee385f4d2d 1108 void TIM_SelectCCDMA_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
rajathr 0:34ee385f4d2d 1109
rajathr 0:34ee385f4d2d 1110 /* Clocks management **********************************************************/
rajathr 0:34ee385f4d2d 1111 void TIM_InternalClockConfig_mort(TIM_TypeDef_mort* TIMx);
rajathr 0:34ee385f4d2d 1112 void TIM_ITRxExternalClockConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource);
rajathr 0:34ee385f4d2d 1113 void TIM_TIxExternalClockConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_TIxExternalCLKSource,
rajathr 0:34ee385f4d2d 1114 uint16_t TIM_ICPolarity, uint16_t ICFilter);
rajathr 0:34ee385f4d2d 1115 void TIM_ETRClockMode1Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
rajathr 0:34ee385f4d2d 1116 uint16_t ExtTRGFilter);
rajathr 0:34ee385f4d2d 1117 void TIM_ETRClockMode2Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler,
rajathr 0:34ee385f4d2d 1118 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
rajathr 0:34ee385f4d2d 1119
rajathr 0:34ee385f4d2d 1120 /* Synchronization management *************************************************/
rajathr 0:34ee385f4d2d 1121 void TIM_SelectInputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource);
rajathr 0:34ee385f4d2d 1122 void TIM_SelectOutputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_TRGOSource);
rajathr 0:34ee385f4d2d 1123 void TIM_SelectSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_SlaveMode);
rajathr 0:34ee385f4d2d 1124 void TIM_SelectMasterSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_MasterSlaveMode);
rajathr 0:34ee385f4d2d 1125 void TIM_ETRConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
rajathr 0:34ee385f4d2d 1126 uint16_t ExtTRGFilter);
rajathr 0:34ee385f4d2d 1127
rajathr 0:34ee385f4d2d 1128 /* Specific interface management **********************************************/
rajathr 0:34ee385f4d2d 1129 void TIM_EncoderInterfaceConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_EncoderMode,
rajathr 0:34ee385f4d2d 1130 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
rajathr 0:34ee385f4d2d 1131 void TIM_SelectHallSensor_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState);
rajathr 0:34ee385f4d2d 1132
rajathr 0:34ee385f4d2d 1133 /* Specific remapping management **********************************************/
rajathr 0:34ee385f4d2d 1134 void TIM_RemapConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Remap);
rajathr 0:34ee385f4d2d 1135
rajathr 0:34ee385f4d2d 1136 #ifdef __cplusplus
rajathr 0:34ee385f4d2d 1137 }
rajathr 0:34ee385f4d2d 1138 #endif
rajathr 0:34ee385f4d2d 1139
rajathr 0:34ee385f4d2d 1140 #endif /*__STM32F4xx_TIM_H */
rajathr 0:34ee385f4d2d 1141
rajathr 0:34ee385f4d2d 1142 /**
rajathr 0:34ee385f4d2d 1143 * @}
rajathr 0:34ee385f4d2d 1144 */
rajathr 0:34ee385f4d2d 1145
rajathr 0:34ee385f4d2d 1146 /**
rajathr 0:34ee385f4d2d 1147 * @}
rajathr 0:34ee385f4d2d 1148 */
rajathr 0:34ee385f4d2d 1149
rajathr 0:34ee385f4d2d 1150 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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