Rajath Ravi
/
ravi_blinkycode
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stm32f4xx_dma_mort.h@0:34ee385f4d2d, 2021-10-23 (annotated)
- Committer:
- rajathr
- Date:
- Sat Oct 23 05:49:09 2021 +0000
- Revision:
- 0:34ee385f4d2d
At 23rd Oct 21 - All Code
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| rajathr | 0:34ee385f4d2d | 1 | /** |
| rajathr | 0:34ee385f4d2d | 2 | ****************************************************************************** |
| rajathr | 0:34ee385f4d2d | 3 | * @file stm32f4xx_dma_mort.h |
| rajathr | 0:34ee385f4d2d | 4 | * @author MCD Application Team |
| rajathr | 0:34ee385f4d2d | 5 | * @version V1.8.0 |
| rajathr | 0:34ee385f4d2d | 6 | * @date 04-November-2016 |
| rajathr | 0:34ee385f4d2d | 7 | * @brief This file contains all the functions prototypes for the DMA firmware |
| rajathr | 0:34ee385f4d2d | 8 | * library. |
| rajathr | 0:34ee385f4d2d | 9 | ****************************************************************************** |
| rajathr | 0:34ee385f4d2d | 10 | * @attention |
| rajathr | 0:34ee385f4d2d | 11 | * |
| rajathr | 0:34ee385f4d2d | 12 | * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> |
| rajathr | 0:34ee385f4d2d | 13 | * |
| rajathr | 0:34ee385f4d2d | 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); |
| rajathr | 0:34ee385f4d2d | 15 | * You may not use this file except in compliance with the License. |
| rajathr | 0:34ee385f4d2d | 16 | * You may obtain a copy of the License at: |
| rajathr | 0:34ee385f4d2d | 17 | * |
| rajathr | 0:34ee385f4d2d | 18 | * http://www.st.com/software_license_agreement_liberty_v2 |
| rajathr | 0:34ee385f4d2d | 19 | * |
| rajathr | 0:34ee385f4d2d | 20 | * Unless required by applicable law or agreed to in writing, software |
| rajathr | 0:34ee385f4d2d | 21 | * distributed under the License is distributed on an "AS IS" BASIS, |
| rajathr | 0:34ee385f4d2d | 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| rajathr | 0:34ee385f4d2d | 23 | * See the License for the specific language governing permissions and |
| rajathr | 0:34ee385f4d2d | 24 | * limitations under the License. |
| rajathr | 0:34ee385f4d2d | 25 | * |
| rajathr | 0:34ee385f4d2d | 26 | ****************************************************************************** |
| rajathr | 0:34ee385f4d2d | 27 | */ |
| rajathr | 0:34ee385f4d2d | 28 | |
| rajathr | 0:34ee385f4d2d | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| rajathr | 0:34ee385f4d2d | 30 | #ifndef __STM32F4xx_DMA_H_MORT |
| rajathr | 0:34ee385f4d2d | 31 | #define __STM32F4xx_DMA_H_MORT |
| rajathr | 0:34ee385f4d2d | 32 | |
| rajathr | 0:34ee385f4d2d | 33 | #ifdef __cplusplus |
| rajathr | 0:34ee385f4d2d | 34 | extern "C" { |
| rajathr | 0:34ee385f4d2d | 35 | #endif |
| rajathr | 0:34ee385f4d2d | 36 | |
| rajathr | 0:34ee385f4d2d | 37 | /* Includes ------------------------------------------------------------------*/ |
| rajathr | 0:34ee385f4d2d | 38 | #include "stm32f4xx_mort2.h" |
| rajathr | 0:34ee385f4d2d | 39 | |
| rajathr | 0:34ee385f4d2d | 40 | /** @addtogroup STM32F4xx_StdPeriph_Driver |
| rajathr | 0:34ee385f4d2d | 41 | * @{ |
| rajathr | 0:34ee385f4d2d | 42 | */ |
| rajathr | 0:34ee385f4d2d | 43 | |
| rajathr | 0:34ee385f4d2d | 44 | /** @addtogroup DMA |
| rajathr | 0:34ee385f4d2d | 45 | * @{ |
| rajathr | 0:34ee385f4d2d | 46 | */ |
| rajathr | 0:34ee385f4d2d | 47 | |
| rajathr | 0:34ee385f4d2d | 48 | /* Exported types ------------------------------------------------------------*/ |
| rajathr | 0:34ee385f4d2d | 49 | |
| rajathr | 0:34ee385f4d2d | 50 | /** |
| rajathr | 0:34ee385f4d2d | 51 | * @brief DMA Init structure definition |
| rajathr | 0:34ee385f4d2d | 52 | */ |
| rajathr | 0:34ee385f4d2d | 53 | |
| rajathr | 0:34ee385f4d2d | 54 | typedef struct |
| rajathr | 0:34ee385f4d2d | 55 | { |
| rajathr | 0:34ee385f4d2d | 56 | uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream. |
| rajathr | 0:34ee385f4d2d | 57 | This parameter can be a value of @ref DMA_channel */ |
| rajathr | 0:34ee385f4d2d | 58 | |
| rajathr | 0:34ee385f4d2d | 59 | uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */ |
| rajathr | 0:34ee385f4d2d | 60 | |
| rajathr | 0:34ee385f4d2d | 61 | uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx. |
| rajathr | 0:34ee385f4d2d | 62 | This memory is the default memory used when double buffer mode is |
| rajathr | 0:34ee385f4d2d | 63 | not enabled. */ |
| rajathr | 0:34ee385f4d2d | 64 | |
| rajathr | 0:34ee385f4d2d | 65 | uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral, |
| rajathr | 0:34ee385f4d2d | 66 | from memory to memory or from peripheral to memory. |
| rajathr | 0:34ee385f4d2d | 67 | This parameter can be a value of @ref DMA_data_transfer_direction */ |
| rajathr | 0:34ee385f4d2d | 68 | |
| rajathr | 0:34ee385f4d2d | 69 | uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream. |
| rajathr | 0:34ee385f4d2d | 70 | The data unit is equal to the configuration set in DMA_PeripheralDataSize |
| rajathr | 0:34ee385f4d2d | 71 | or DMA_MemoryDataSize members depending in the transfer direction. */ |
| rajathr | 0:34ee385f4d2d | 72 | |
| rajathr | 0:34ee385f4d2d | 73 | uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| rajathr | 0:34ee385f4d2d | 74 | This parameter can be a value of @ref DMA_peripheral_incremented_mode */ |
| rajathr | 0:34ee385f4d2d | 75 | |
| rajathr | 0:34ee385f4d2d | 76 | uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not. |
| rajathr | 0:34ee385f4d2d | 77 | This parameter can be a value of @ref DMA_memory_incremented_mode */ |
| rajathr | 0:34ee385f4d2d | 78 | |
| rajathr | 0:34ee385f4d2d | 79 | uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. |
| rajathr | 0:34ee385f4d2d | 80 | This parameter can be a value of @ref DMA_peripheral_data_size */ |
| rajathr | 0:34ee385f4d2d | 81 | |
| rajathr | 0:34ee385f4d2d | 82 | uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. |
| rajathr | 0:34ee385f4d2d | 83 | This parameter can be a value of @ref DMA_memory_data_size */ |
| rajathr | 0:34ee385f4d2d | 84 | |
| rajathr | 0:34ee385f4d2d | 85 | uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx. |
| rajathr | 0:34ee385f4d2d | 86 | This parameter can be a value of @ref DMA_circular_normal_mode |
| rajathr | 0:34ee385f4d2d | 87 | @note The circular buffer mode cannot be used if the memory-to-memory |
| rajathr | 0:34ee385f4d2d | 88 | data transfer is configured on the selected Stream */ |
| rajathr | 0:34ee385f4d2d | 89 | |
| rajathr | 0:34ee385f4d2d | 90 | uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx. |
| rajathr | 0:34ee385f4d2d | 91 | This parameter can be a value of @ref DMA_priority_level */ |
| rajathr | 0:34ee385f4d2d | 92 | |
| rajathr | 0:34ee385f4d2d | 93 | uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream. |
| rajathr | 0:34ee385f4d2d | 94 | This parameter can be a value of @ref DMA_fifo_direct_mode |
| rajathr | 0:34ee385f4d2d | 95 | @note The Direct mode (FIFO mode disabled) cannot be used if the |
| rajathr | 0:34ee385f4d2d | 96 | memory-to-memory data transfer is configured on the selected Stream */ |
| rajathr | 0:34ee385f4d2d | 97 | |
| rajathr | 0:34ee385f4d2d | 98 | uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level. |
| rajathr | 0:34ee385f4d2d | 99 | This parameter can be a value of @ref DMA_fifo_threshold_level */ |
| rajathr | 0:34ee385f4d2d | 100 | |
| rajathr | 0:34ee385f4d2d | 101 | uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. |
| rajathr | 0:34ee385f4d2d | 102 | It specifies the amount of data to be transferred in a single non interruptable |
| rajathr | 0:34ee385f4d2d | 103 | transaction. This parameter can be a value of @ref DMA_memory_burst |
| rajathr | 0:34ee385f4d2d | 104 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
| rajathr | 0:34ee385f4d2d | 105 | |
| rajathr | 0:34ee385f4d2d | 106 | uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. |
| rajathr | 0:34ee385f4d2d | 107 | It specifies the amount of data to be transferred in a single non interruptable |
| rajathr | 0:34ee385f4d2d | 108 | transaction. This parameter can be a value of @ref DMA_peripheral_burst |
| rajathr | 0:34ee385f4d2d | 109 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
| rajathr | 0:34ee385f4d2d | 110 | }DMA_InitTypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 111 | |
| rajathr | 0:34ee385f4d2d | 112 | /* Exported constants --------------------------------------------------------*/ |
| rajathr | 0:34ee385f4d2d | 113 | |
| rajathr | 0:34ee385f4d2d | 114 | /** @defgroup DMA_Exported_Constants |
| rajathr | 0:34ee385f4d2d | 115 | * @{ |
| rajathr | 0:34ee385f4d2d | 116 | */ |
| rajathr | 0:34ee385f4d2d | 117 | |
| rajathr | 0:34ee385f4d2d | 118 | #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \ |
| rajathr | 0:34ee385f4d2d | 119 | ((PERIPH) == DMA1_Stream1) || \ |
| rajathr | 0:34ee385f4d2d | 120 | ((PERIPH) == DMA1_Stream2) || \ |
| rajathr | 0:34ee385f4d2d | 121 | ((PERIPH) == DMA1_Stream3) || \ |
| rajathr | 0:34ee385f4d2d | 122 | ((PERIPH) == DMA1_Stream4) || \ |
| rajathr | 0:34ee385f4d2d | 123 | ((PERIPH) == DMA1_Stream5) || \ |
| rajathr | 0:34ee385f4d2d | 124 | ((PERIPH) == DMA1_Stream6) || \ |
| rajathr | 0:34ee385f4d2d | 125 | ((PERIPH) == DMA1_Stream7) || \ |
| rajathr | 0:34ee385f4d2d | 126 | ((PERIPH) == DMA2_Stream0) || \ |
| rajathr | 0:34ee385f4d2d | 127 | ((PERIPH) == DMA2_Stream1) || \ |
| rajathr | 0:34ee385f4d2d | 128 | ((PERIPH) == DMA2_Stream2) || \ |
| rajathr | 0:34ee385f4d2d | 129 | ((PERIPH) == DMA2_Stream3) || \ |
| rajathr | 0:34ee385f4d2d | 130 | ((PERIPH) == DMA2_Stream4) || \ |
| rajathr | 0:34ee385f4d2d | 131 | ((PERIPH) == DMA2_Stream5) || \ |
| rajathr | 0:34ee385f4d2d | 132 | ((PERIPH) == DMA2_Stream6) || \ |
| rajathr | 0:34ee385f4d2d | 133 | ((PERIPH) == DMA2_Stream7)) |
| rajathr | 0:34ee385f4d2d | 134 | |
| rajathr | 0:34ee385f4d2d | 135 | #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1_MORT) || \ |
| rajathr | 0:34ee385f4d2d | 136 | ((CONTROLLER) == DMA2_MORT)) |
| rajathr | 0:34ee385f4d2d | 137 | |
| rajathr | 0:34ee385f4d2d | 138 | /** @defgroup DMA_channel |
| rajathr | 0:34ee385f4d2d | 139 | * @{ |
| rajathr | 0:34ee385f4d2d | 140 | */ |
| rajathr | 0:34ee385f4d2d | 141 | #define DMA_Channel_0 ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 142 | #define DMA_Channel_1 ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 143 | #define DMA_Channel_2 ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 144 | #define DMA_Channel_3 ((uint32_t)0x06000000) |
| rajathr | 0:34ee385f4d2d | 145 | #define DMA_Channel_4 ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 146 | #define DMA_Channel_5 ((uint32_t)0x0A000000) |
| rajathr | 0:34ee385f4d2d | 147 | #define DMA_Channel_6 ((uint32_t)0x0C000000) |
| rajathr | 0:34ee385f4d2d | 148 | #define DMA_Channel_7 ((uint32_t)0x0E000000) |
| rajathr | 0:34ee385f4d2d | 149 | |
| rajathr | 0:34ee385f4d2d | 150 | #define IS_DMA_CHANNEL_MORT(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \ |
| rajathr | 0:34ee385f4d2d | 151 | ((CHANNEL) == DMA_Channel_1) || \ |
| rajathr | 0:34ee385f4d2d | 152 | ((CHANNEL) == DMA_Channel_2) || \ |
| rajathr | 0:34ee385f4d2d | 153 | ((CHANNEL) == DMA_Channel_3) || \ |
| rajathr | 0:34ee385f4d2d | 154 | ((CHANNEL) == DMA_Channel_4) || \ |
| rajathr | 0:34ee385f4d2d | 155 | ((CHANNEL) == DMA_Channel_5) || \ |
| rajathr | 0:34ee385f4d2d | 156 | ((CHANNEL) == DMA_Channel_6) || \ |
| rajathr | 0:34ee385f4d2d | 157 | ((CHANNEL) == DMA_Channel_7)) |
| rajathr | 0:34ee385f4d2d | 158 | /** |
| rajathr | 0:34ee385f4d2d | 159 | * @} |
| rajathr | 0:34ee385f4d2d | 160 | */ |
| rajathr | 0:34ee385f4d2d | 161 | |
| rajathr | 0:34ee385f4d2d | 162 | |
| rajathr | 0:34ee385f4d2d | 163 | /** @defgroup DMA_data_transfer_direction |
| rajathr | 0:34ee385f4d2d | 164 | * @{ |
| rajathr | 0:34ee385f4d2d | 165 | */ |
| rajathr | 0:34ee385f4d2d | 166 | #define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 167 | #define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 168 | #define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 169 | |
| rajathr | 0:34ee385f4d2d | 170 | #define IS_DMA_DIRECTION_MORT(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \ |
| rajathr | 0:34ee385f4d2d | 171 | ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \ |
| rajathr | 0:34ee385f4d2d | 172 | ((DIRECTION) == DMA_DIR_MemoryToMemory)) |
| rajathr | 0:34ee385f4d2d | 173 | /** |
| rajathr | 0:34ee385f4d2d | 174 | * @} |
| rajathr | 0:34ee385f4d2d | 175 | */ |
| rajathr | 0:34ee385f4d2d | 176 | |
| rajathr | 0:34ee385f4d2d | 177 | |
| rajathr | 0:34ee385f4d2d | 178 | /** @defgroup DMA_data_buffer_size |
| rajathr | 0:34ee385f4d2d | 179 | * @{ |
| rajathr | 0:34ee385f4d2d | 180 | */ |
| rajathr | 0:34ee385f4d2d | 181 | #define IS_DMA_BUFFER_SIZE_MORT(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
| rajathr | 0:34ee385f4d2d | 182 | /** |
| rajathr | 0:34ee385f4d2d | 183 | * @} |
| rajathr | 0:34ee385f4d2d | 184 | */ |
| rajathr | 0:34ee385f4d2d | 185 | |
| rajathr | 0:34ee385f4d2d | 186 | |
| rajathr | 0:34ee385f4d2d | 187 | /** @defgroup DMA_peripheral_incremented_mode |
| rajathr | 0:34ee385f4d2d | 188 | * @{ |
| rajathr | 0:34ee385f4d2d | 189 | */ |
| rajathr | 0:34ee385f4d2d | 190 | #define DMA_PeripheralInc_Enable ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 191 | #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 192 | |
| rajathr | 0:34ee385f4d2d | 193 | #define IS_DMA_PERIPHERAL_INC_STATE_MORT(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ |
| rajathr | 0:34ee385f4d2d | 194 | ((STATE) == DMA_PeripheralInc_Disable)) |
| rajathr | 0:34ee385f4d2d | 195 | /** |
| rajathr | 0:34ee385f4d2d | 196 | * @} |
| rajathr | 0:34ee385f4d2d | 197 | */ |
| rajathr | 0:34ee385f4d2d | 198 | |
| rajathr | 0:34ee385f4d2d | 199 | |
| rajathr | 0:34ee385f4d2d | 200 | /** @defgroup DMA_memory_incremented_mode |
| rajathr | 0:34ee385f4d2d | 201 | * @{ |
| rajathr | 0:34ee385f4d2d | 202 | */ |
| rajathr | 0:34ee385f4d2d | 203 | #define DMA_MemoryInc_Enable ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 204 | #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 205 | |
| rajathr | 0:34ee385f4d2d | 206 | #define IS_DMA_MEMORY_INC_STATE_MORT(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ |
| rajathr | 0:34ee385f4d2d | 207 | ((STATE) == DMA_MemoryInc_Disable)) |
| rajathr | 0:34ee385f4d2d | 208 | /** |
| rajathr | 0:34ee385f4d2d | 209 | * @} |
| rajathr | 0:34ee385f4d2d | 210 | */ |
| rajathr | 0:34ee385f4d2d | 211 | |
| rajathr | 0:34ee385f4d2d | 212 | |
| rajathr | 0:34ee385f4d2d | 213 | /** @defgroup DMA_peripheral_data_size |
| rajathr | 0:34ee385f4d2d | 214 | * @{ |
| rajathr | 0:34ee385f4d2d | 215 | */ |
| rajathr | 0:34ee385f4d2d | 216 | #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 217 | #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 218 | #define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 219 | |
| rajathr | 0:34ee385f4d2d | 220 | #define IS_DMA_PERIPHERAL_DATA_SIZE_MORT(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ |
| rajathr | 0:34ee385f4d2d | 221 | ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ |
| rajathr | 0:34ee385f4d2d | 222 | ((SIZE) == DMA_PeripheralDataSize_Word)) |
| rajathr | 0:34ee385f4d2d | 223 | /** |
| rajathr | 0:34ee385f4d2d | 224 | * @} |
| rajathr | 0:34ee385f4d2d | 225 | */ |
| rajathr | 0:34ee385f4d2d | 226 | |
| rajathr | 0:34ee385f4d2d | 227 | |
| rajathr | 0:34ee385f4d2d | 228 | /** @defgroup DMA_memory_data_size |
| rajathr | 0:34ee385f4d2d | 229 | * @{ |
| rajathr | 0:34ee385f4d2d | 230 | */ |
| rajathr | 0:34ee385f4d2d | 231 | #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 232 | #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 233 | #define DMA_MemoryDataSize_Word ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 234 | |
| rajathr | 0:34ee385f4d2d | 235 | #define IS_DMA_MEMORY_DATA_SIZE_MORT(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ |
| rajathr | 0:34ee385f4d2d | 236 | ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ |
| rajathr | 0:34ee385f4d2d | 237 | ((SIZE) == DMA_MemoryDataSize_Word )) |
| rajathr | 0:34ee385f4d2d | 238 | /** |
| rajathr | 0:34ee385f4d2d | 239 | * @} |
| rajathr | 0:34ee385f4d2d | 240 | */ |
| rajathr | 0:34ee385f4d2d | 241 | |
| rajathr | 0:34ee385f4d2d | 242 | |
| rajathr | 0:34ee385f4d2d | 243 | /** @defgroup DMA_circular_normal_mode |
| rajathr | 0:34ee385f4d2d | 244 | * @{ |
| rajathr | 0:34ee385f4d2d | 245 | */ |
| rajathr | 0:34ee385f4d2d | 246 | #define DMA_Mode_Normal ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 247 | #define DMA_Mode_Circular ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 248 | |
| rajathr | 0:34ee385f4d2d | 249 | #define IS_DMA_MODE_MORT(MODE) (((MODE) == DMA_Mode_Normal ) || \ |
| rajathr | 0:34ee385f4d2d | 250 | ((MODE) == DMA_Mode_Circular)) |
| rajathr | 0:34ee385f4d2d | 251 | /** |
| rajathr | 0:34ee385f4d2d | 252 | * @} |
| rajathr | 0:34ee385f4d2d | 253 | */ |
| rajathr | 0:34ee385f4d2d | 254 | |
| rajathr | 0:34ee385f4d2d | 255 | |
| rajathr | 0:34ee385f4d2d | 256 | /** @defgroup DMA_priority_level |
| rajathr | 0:34ee385f4d2d | 257 | * @{ |
| rajathr | 0:34ee385f4d2d | 258 | */ |
| rajathr | 0:34ee385f4d2d | 259 | #define DMA_Priority_Low ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 260 | #define DMA_Priority_Medium ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 261 | #define DMA_Priority_High ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 262 | #define DMA_Priority_VeryHigh ((uint32_t)0x00030000) |
| rajathr | 0:34ee385f4d2d | 263 | |
| rajathr | 0:34ee385f4d2d | 264 | #define IS_DMA_PRIORITY_MORT(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \ |
| rajathr | 0:34ee385f4d2d | 265 | ((PRIORITY) == DMA_Priority_Medium) || \ |
| rajathr | 0:34ee385f4d2d | 266 | ((PRIORITY) == DMA_Priority_High) || \ |
| rajathr | 0:34ee385f4d2d | 267 | ((PRIORITY) == DMA_Priority_VeryHigh)) |
| rajathr | 0:34ee385f4d2d | 268 | /** |
| rajathr | 0:34ee385f4d2d | 269 | * @} |
| rajathr | 0:34ee385f4d2d | 270 | */ |
| rajathr | 0:34ee385f4d2d | 271 | |
| rajathr | 0:34ee385f4d2d | 272 | |
| rajathr | 0:34ee385f4d2d | 273 | /** @defgroup DMA_fifo_direct_mode |
| rajathr | 0:34ee385f4d2d | 274 | * @{ |
| rajathr | 0:34ee385f4d2d | 275 | */ |
| rajathr | 0:34ee385f4d2d | 276 | #define DMA_FIFOMode_Disable ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 277 | #define DMA_FIFOMode_Enable ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 278 | |
| rajathr | 0:34ee385f4d2d | 279 | #define IS_DMA_FIFO_MODE_STATE_MORT(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \ |
| rajathr | 0:34ee385f4d2d | 280 | ((STATE) == DMA_FIFOMode_Enable)) |
| rajathr | 0:34ee385f4d2d | 281 | /** |
| rajathr | 0:34ee385f4d2d | 282 | * @} |
| rajathr | 0:34ee385f4d2d | 283 | */ |
| rajathr | 0:34ee385f4d2d | 284 | |
| rajathr | 0:34ee385f4d2d | 285 | |
| rajathr | 0:34ee385f4d2d | 286 | /** @defgroup DMA_fifo_threshold_level |
| rajathr | 0:34ee385f4d2d | 287 | * @{ |
| rajathr | 0:34ee385f4d2d | 288 | */ |
| rajathr | 0:34ee385f4d2d | 289 | #define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 290 | #define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 291 | #define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 292 | #define DMA_FIFOThreshold_Full ((uint32_t)0x00000003) |
| rajathr | 0:34ee385f4d2d | 293 | |
| rajathr | 0:34ee385f4d2d | 294 | #define IS_DMA_FIFO_THRESHOLD_MORT(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \ |
| rajathr | 0:34ee385f4d2d | 295 | ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \ |
| rajathr | 0:34ee385f4d2d | 296 | ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \ |
| rajathr | 0:34ee385f4d2d | 297 | ((THRESHOLD) == DMA_FIFOThreshold_Full)) |
| rajathr | 0:34ee385f4d2d | 298 | /** |
| rajathr | 0:34ee385f4d2d | 299 | * @} |
| rajathr | 0:34ee385f4d2d | 300 | */ |
| rajathr | 0:34ee385f4d2d | 301 | |
| rajathr | 0:34ee385f4d2d | 302 | |
| rajathr | 0:34ee385f4d2d | 303 | /** @defgroup DMA_memory_burst |
| rajathr | 0:34ee385f4d2d | 304 | * @{ |
| rajathr | 0:34ee385f4d2d | 305 | */ |
| rajathr | 0:34ee385f4d2d | 306 | #define DMA_MemoryBurst_Single ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 307 | #define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 308 | #define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 309 | #define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000) |
| rajathr | 0:34ee385f4d2d | 310 | |
| rajathr | 0:34ee385f4d2d | 311 | #define IS_DMA_MEMORY_BURST_MORT(BURST) (((BURST) == DMA_MemoryBurst_Single) || \ |
| rajathr | 0:34ee385f4d2d | 312 | ((BURST) == DMA_MemoryBurst_INC4) || \ |
| rajathr | 0:34ee385f4d2d | 313 | ((BURST) == DMA_MemoryBurst_INC8) || \ |
| rajathr | 0:34ee385f4d2d | 314 | ((BURST) == DMA_MemoryBurst_INC16)) |
| rajathr | 0:34ee385f4d2d | 315 | /** |
| rajathr | 0:34ee385f4d2d | 316 | * @} |
| rajathr | 0:34ee385f4d2d | 317 | */ |
| rajathr | 0:34ee385f4d2d | 318 | |
| rajathr | 0:34ee385f4d2d | 319 | |
| rajathr | 0:34ee385f4d2d | 320 | /** @defgroup DMA_peripheral_burst |
| rajathr | 0:34ee385f4d2d | 321 | * @{ |
| rajathr | 0:34ee385f4d2d | 322 | */ |
| rajathr | 0:34ee385f4d2d | 323 | #define DMA_PeripheralBurst_Single ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 324 | #define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 325 | #define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 326 | #define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000) |
| rajathr | 0:34ee385f4d2d | 327 | |
| rajathr | 0:34ee385f4d2d | 328 | #define IS_DMA_PERIPHERAL_BURST_MORT(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \ |
| rajathr | 0:34ee385f4d2d | 329 | ((BURST) == DMA_PeripheralBurst_INC4) || \ |
| rajathr | 0:34ee385f4d2d | 330 | ((BURST) == DMA_PeripheralBurst_INC8) || \ |
| rajathr | 0:34ee385f4d2d | 331 | ((BURST) == DMA_PeripheralBurst_INC16)) |
| rajathr | 0:34ee385f4d2d | 332 | /** |
| rajathr | 0:34ee385f4d2d | 333 | * @} |
| rajathr | 0:34ee385f4d2d | 334 | */ |
| rajathr | 0:34ee385f4d2d | 335 | |
| rajathr | 0:34ee385f4d2d | 336 | |
| rajathr | 0:34ee385f4d2d | 337 | /** @defgroup DMA_fifo_status_level |
| rajathr | 0:34ee385f4d2d | 338 | * @{ |
| rajathr | 0:34ee385f4d2d | 339 | */ |
| rajathr | 0:34ee385f4d2d | 340 | #define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3) |
| rajathr | 0:34ee385f4d2d | 341 | #define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3) |
| rajathr | 0:34ee385f4d2d | 342 | #define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) |
| rajathr | 0:34ee385f4d2d | 343 | #define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3) |
| rajathr | 0:34ee385f4d2d | 344 | #define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3) |
| rajathr | 0:34ee385f4d2d | 345 | #define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3) |
| rajathr | 0:34ee385f4d2d | 346 | |
| rajathr | 0:34ee385f4d2d | 347 | #define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \ |
| rajathr | 0:34ee385f4d2d | 348 | ((STATUS) == DMA_FIFOStatus_HalfFull) || \ |
| rajathr | 0:34ee385f4d2d | 349 | ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \ |
| rajathr | 0:34ee385f4d2d | 350 | ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \ |
| rajathr | 0:34ee385f4d2d | 351 | ((STATUS) == DMA_FIFOStatus_Full) || \ |
| rajathr | 0:34ee385f4d2d | 352 | ((STATUS) == DMA_FIFOStatus_Empty)) |
| rajathr | 0:34ee385f4d2d | 353 | /** |
| rajathr | 0:34ee385f4d2d | 354 | * @} |
| rajathr | 0:34ee385f4d2d | 355 | */ |
| rajathr | 0:34ee385f4d2d | 356 | |
| rajathr | 0:34ee385f4d2d | 357 | /** @defgroup DMA_flags_definition |
| rajathr | 0:34ee385f4d2d | 358 | * @{ |
| rajathr | 0:34ee385f4d2d | 359 | */ |
| rajathr | 0:34ee385f4d2d | 360 | #define DMA_FLAG_FEIF0 ((uint32_t)0x10800001) |
| rajathr | 0:34ee385f4d2d | 361 | #define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004) |
| rajathr | 0:34ee385f4d2d | 362 | #define DMA_FLAG_TEIF0 ((uint32_t)0x10000008) |
| rajathr | 0:34ee385f4d2d | 363 | #define DMA_FLAG_HTIF0 ((uint32_t)0x10000010) |
| rajathr | 0:34ee385f4d2d | 364 | #define DMA_FLAG_TCIF0 ((uint32_t)0x10000020) |
| rajathr | 0:34ee385f4d2d | 365 | #define DMA_FLAG_FEIF1 ((uint32_t)0x10000040) |
| rajathr | 0:34ee385f4d2d | 366 | #define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100) |
| rajathr | 0:34ee385f4d2d | 367 | #define DMA_FLAG_TEIF1 ((uint32_t)0x10000200) |
| rajathr | 0:34ee385f4d2d | 368 | #define DMA_FLAG_HTIF1 ((uint32_t)0x10000400) |
| rajathr | 0:34ee385f4d2d | 369 | #define DMA_FLAG_TCIF1 ((uint32_t)0x10000800) |
| rajathr | 0:34ee385f4d2d | 370 | #define DMA_FLAG_FEIF2 ((uint32_t)0x10010000) |
| rajathr | 0:34ee385f4d2d | 371 | #define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000) |
| rajathr | 0:34ee385f4d2d | 372 | #define DMA_FLAG_TEIF2 ((uint32_t)0x10080000) |
| rajathr | 0:34ee385f4d2d | 373 | #define DMA_FLAG_HTIF2 ((uint32_t)0x10100000) |
| rajathr | 0:34ee385f4d2d | 374 | #define DMA_FLAG_TCIF2 ((uint32_t)0x10200000) |
| rajathr | 0:34ee385f4d2d | 375 | #define DMA_FLAG_FEIF3 ((uint32_t)0x10400000) |
| rajathr | 0:34ee385f4d2d | 376 | #define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000) |
| rajathr | 0:34ee385f4d2d | 377 | #define DMA_FLAG_TEIF3 ((uint32_t)0x12000000) |
| rajathr | 0:34ee385f4d2d | 378 | #define DMA_FLAG_HTIF3 ((uint32_t)0x14000000) |
| rajathr | 0:34ee385f4d2d | 379 | #define DMA_FLAG_TCIF3 ((uint32_t)0x18000000) |
| rajathr | 0:34ee385f4d2d | 380 | #define DMA_FLAG_FEIF4 ((uint32_t)0x20000001) |
| rajathr | 0:34ee385f4d2d | 381 | #define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004) |
| rajathr | 0:34ee385f4d2d | 382 | #define DMA_FLAG_TEIF4 ((uint32_t)0x20000008) |
| rajathr | 0:34ee385f4d2d | 383 | #define DMA_FLAG_HTIF4 ((uint32_t)0x20000010) |
| rajathr | 0:34ee385f4d2d | 384 | #define DMA_FLAG_TCIF4 ((uint32_t)0x20000020) |
| rajathr | 0:34ee385f4d2d | 385 | #define DMA_FLAG_FEIF5 ((uint32_t)0x20000040) |
| rajathr | 0:34ee385f4d2d | 386 | #define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100) |
| rajathr | 0:34ee385f4d2d | 387 | #define DMA_FLAG_TEIF5 ((uint32_t)0x20000200) |
| rajathr | 0:34ee385f4d2d | 388 | #define DMA_FLAG_HTIF5 ((uint32_t)0x20000400) |
| rajathr | 0:34ee385f4d2d | 389 | #define DMA_FLAG_TCIF5 ((uint32_t)0x20000800) |
| rajathr | 0:34ee385f4d2d | 390 | #define DMA_FLAG_FEIF6 ((uint32_t)0x20010000) |
| rajathr | 0:34ee385f4d2d | 391 | #define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000) |
| rajathr | 0:34ee385f4d2d | 392 | #define DMA_FLAG_TEIF6 ((uint32_t)0x20080000) |
| rajathr | 0:34ee385f4d2d | 393 | #define DMA_FLAG_HTIF6 ((uint32_t)0x20100000) |
| rajathr | 0:34ee385f4d2d | 394 | #define DMA_FLAG_TCIF6 ((uint32_t)0x20200000) |
| rajathr | 0:34ee385f4d2d | 395 | #define DMA_FLAG_FEIF7 ((uint32_t)0x20400000) |
| rajathr | 0:34ee385f4d2d | 396 | #define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000) |
| rajathr | 0:34ee385f4d2d | 397 | #define DMA_FLAG_TEIF7 ((uint32_t)0x22000000) |
| rajathr | 0:34ee385f4d2d | 398 | #define DMA_FLAG_HTIF7 ((uint32_t)0x24000000) |
| rajathr | 0:34ee385f4d2d | 399 | #define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) |
| rajathr | 0:34ee385f4d2d | 400 | |
| rajathr | 0:34ee385f4d2d | 401 | #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ |
| rajathr | 0:34ee385f4d2d | 402 | (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00)) |
| rajathr | 0:34ee385f4d2d | 403 | |
| rajathr | 0:34ee385f4d2d | 404 | #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \ |
| rajathr | 0:34ee385f4d2d | 405 | ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ |
| rajathr | 0:34ee385f4d2d | 406 | ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \ |
| rajathr | 0:34ee385f4d2d | 407 | ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \ |
| rajathr | 0:34ee385f4d2d | 408 | ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \ |
| rajathr | 0:34ee385f4d2d | 409 | ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \ |
| rajathr | 0:34ee385f4d2d | 410 | ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \ |
| rajathr | 0:34ee385f4d2d | 411 | ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \ |
| rajathr | 0:34ee385f4d2d | 412 | ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \ |
| rajathr | 0:34ee385f4d2d | 413 | ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \ |
| rajathr | 0:34ee385f4d2d | 414 | ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \ |
| rajathr | 0:34ee385f4d2d | 415 | ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \ |
| rajathr | 0:34ee385f4d2d | 416 | ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \ |
| rajathr | 0:34ee385f4d2d | 417 | ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \ |
| rajathr | 0:34ee385f4d2d | 418 | ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \ |
| rajathr | 0:34ee385f4d2d | 419 | ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \ |
| rajathr | 0:34ee385f4d2d | 420 | ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \ |
| rajathr | 0:34ee385f4d2d | 421 | ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \ |
| rajathr | 0:34ee385f4d2d | 422 | ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \ |
| rajathr | 0:34ee385f4d2d | 423 | ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7)) |
| rajathr | 0:34ee385f4d2d | 424 | /** |
| rajathr | 0:34ee385f4d2d | 425 | * @} |
| rajathr | 0:34ee385f4d2d | 426 | */ |
| rajathr | 0:34ee385f4d2d | 427 | |
| rajathr | 0:34ee385f4d2d | 428 | |
| rajathr | 0:34ee385f4d2d | 429 | /** @defgroup DMA_interrupt_enable_definitions |
| rajathr | 0:34ee385f4d2d | 430 | * @{ |
| rajathr | 0:34ee385f4d2d | 431 | */ |
| rajathr | 0:34ee385f4d2d | 432 | #define DMA_IT_TC_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 433 | #define DMA_IT_HT_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 434 | #define DMA_IT_TE_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 435 | #define DMA_IT_DME_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 436 | #define DMA_IT_FE_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 437 | |
| rajathr | 0:34ee385f4d2d | 438 | #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00)) |
| rajathr | 0:34ee385f4d2d | 439 | /** |
| rajathr | 0:34ee385f4d2d | 440 | * @} |
| rajathr | 0:34ee385f4d2d | 441 | */ |
| rajathr | 0:34ee385f4d2d | 442 | |
| rajathr | 0:34ee385f4d2d | 443 | |
| rajathr | 0:34ee385f4d2d | 444 | /** @defgroup DMA_interrupts_definitions |
| rajathr | 0:34ee385f4d2d | 445 | * @{ |
| rajathr | 0:34ee385f4d2d | 446 | */ |
| rajathr | 0:34ee385f4d2d | 447 | #define DMA_IT_FEIF0 ((uint32_t)0x90000001) |
| rajathr | 0:34ee385f4d2d | 448 | #define DMA_IT_DMEIF0 ((uint32_t)0x10001004) |
| rajathr | 0:34ee385f4d2d | 449 | #define DMA_IT_TEIF0 ((uint32_t)0x10002008) |
| rajathr | 0:34ee385f4d2d | 450 | #define DMA_IT_HTIF0 ((uint32_t)0x10004010) |
| rajathr | 0:34ee385f4d2d | 451 | #define DMA_IT_TC_MORTIF0 ((uint32_t)0x10008020) |
| rajathr | 0:34ee385f4d2d | 452 | #define DMA_IT_FEIF1 ((uint32_t)0x90000040) |
| rajathr | 0:34ee385f4d2d | 453 | #define DMA_IT_DMEIF1 ((uint32_t)0x10001100) |
| rajathr | 0:34ee385f4d2d | 454 | #define DMA_IT_TEIF1 ((uint32_t)0x10002200) |
| rajathr | 0:34ee385f4d2d | 455 | #define DMA_IT_HTIF1 ((uint32_t)0x10004400) |
| rajathr | 0:34ee385f4d2d | 456 | #define DMA_IT_TC_MORTIF1 ((uint32_t)0x10008800) |
| rajathr | 0:34ee385f4d2d | 457 | #define DMA_IT_FEIF2 ((uint32_t)0x90010000) |
| rajathr | 0:34ee385f4d2d | 458 | #define DMA_IT_DMEIF2 ((uint32_t)0x10041000) |
| rajathr | 0:34ee385f4d2d | 459 | #define DMA_IT_TEIF2 ((uint32_t)0x10082000) |
| rajathr | 0:34ee385f4d2d | 460 | #define DMA_IT_HTIF2 ((uint32_t)0x10104000) |
| rajathr | 0:34ee385f4d2d | 461 | #define DMA_IT_TC_MORTIF2 ((uint32_t)0x10208000) |
| rajathr | 0:34ee385f4d2d | 462 | #define DMA_IT_FEIF3 ((uint32_t)0x90400000) |
| rajathr | 0:34ee385f4d2d | 463 | #define DMA_IT_DMEIF3 ((uint32_t)0x11001000) |
| rajathr | 0:34ee385f4d2d | 464 | #define DMA_IT_TEIF3 ((uint32_t)0x12002000) |
| rajathr | 0:34ee385f4d2d | 465 | #define DMA_IT_HTIF3 ((uint32_t)0x14004000) |
| rajathr | 0:34ee385f4d2d | 466 | #define DMA_IT_TC_MORTIF3 ((uint32_t)0x18008000) |
| rajathr | 0:34ee385f4d2d | 467 | #define DMA_IT_FEIF4 ((uint32_t)0xA0000001) |
| rajathr | 0:34ee385f4d2d | 468 | #define DMA_IT_DMEIF4 ((uint32_t)0x20001004) |
| rajathr | 0:34ee385f4d2d | 469 | #define DMA_IT_TEIF4 ((uint32_t)0x20002008) |
| rajathr | 0:34ee385f4d2d | 470 | #define DMA_IT_HTIF4 ((uint32_t)0x20004010) |
| rajathr | 0:34ee385f4d2d | 471 | #define DMA_IT_TC_MORTIF4 ((uint32_t)0x20008020) |
| rajathr | 0:34ee385f4d2d | 472 | #define DMA_IT_FEIF5 ((uint32_t)0xA0000040) |
| rajathr | 0:34ee385f4d2d | 473 | #define DMA_IT_DMEIF5 ((uint32_t)0x20001100) |
| rajathr | 0:34ee385f4d2d | 474 | #define DMA_IT_TEIF5 ((uint32_t)0x20002200) |
| rajathr | 0:34ee385f4d2d | 475 | #define DMA_IT_HTIF5 ((uint32_t)0x20004400) |
| rajathr | 0:34ee385f4d2d | 476 | #define DMA_IT_TC_MORTIF5 ((uint32_t)0x20008800) |
| rajathr | 0:34ee385f4d2d | 477 | #define DMA_IT_FEIF6 ((uint32_t)0xA0010000) |
| rajathr | 0:34ee385f4d2d | 478 | #define DMA_IT_DMEIF6 ((uint32_t)0x20041000) |
| rajathr | 0:34ee385f4d2d | 479 | #define DMA_IT_TEIF6 ((uint32_t)0x20082000) |
| rajathr | 0:34ee385f4d2d | 480 | #define DMA_IT_HTIF6 ((uint32_t)0x20104000) |
| rajathr | 0:34ee385f4d2d | 481 | #define DMA_IT_TC_MORTIF6 ((uint32_t)0x20208000) |
| rajathr | 0:34ee385f4d2d | 482 | #define DMA_IT_FEIF7 ((uint32_t)0xA0400000) |
| rajathr | 0:34ee385f4d2d | 483 | #define DMA_IT_DMEIF7 ((uint32_t)0x21001000) |
| rajathr | 0:34ee385f4d2d | 484 | #define DMA_IT_TEIF7 ((uint32_t)0x22002000) |
| rajathr | 0:34ee385f4d2d | 485 | #define DMA_IT_HTIF7 ((uint32_t)0x24004000) |
| rajathr | 0:34ee385f4d2d | 486 | #define DMA_IT_TC_MORTIF7 ((uint32_t)0x28008000) |
| rajathr | 0:34ee385f4d2d | 487 | |
| rajathr | 0:34ee385f4d2d | 488 | #define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \ |
| rajathr | 0:34ee385f4d2d | 489 | (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \ |
| rajathr | 0:34ee385f4d2d | 490 | (((IT) & 0x40820082) == 0x00)) |
| rajathr | 0:34ee385f4d2d | 491 | |
| rajathr | 0:34ee385f4d2d | 492 | #define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TC_MORT_MORT_MORTIF0) || ((IT) == DMA_IT_HTIF0) || \ |
| rajathr | 0:34ee385f4d2d | 493 | ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \ |
| rajathr | 0:34ee385f4d2d | 494 | ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TC_MORT_MORT_MORT_MORT_MORTIF1) || \ |
| rajathr | 0:34ee385f4d2d | 495 | ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \ |
| rajathr | 0:34ee385f4d2d | 496 | ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \ |
| rajathr | 0:34ee385f4d2d | 497 | ((IT) == DMA_IT_TC_MORT_MORT_MORTIF2) || ((IT) == DMA_IT_HTIF2) || \ |
| rajathr | 0:34ee385f4d2d | 498 | ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \ |
| rajathr | 0:34ee385f4d2d | 499 | ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TC_MORT_MORT_MORT_MORT_MORTIF3) || \ |
| rajathr | 0:34ee385f4d2d | 500 | ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \ |
| rajathr | 0:34ee385f4d2d | 501 | ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \ |
| rajathr | 0:34ee385f4d2d | 502 | ((IT) == DMA_IT_TC_MORT_MORT_MORTIF4) || ((IT) == DMA_IT_HTIF4) || \ |
| rajathr | 0:34ee385f4d2d | 503 | ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \ |
| rajathr | 0:34ee385f4d2d | 504 | ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TC_MORT_MORT_MORT_MORT_MORTIF5) || \ |
| rajathr | 0:34ee385f4d2d | 505 | ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \ |
| rajathr | 0:34ee385f4d2d | 506 | ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \ |
| rajathr | 0:34ee385f4d2d | 507 | ((IT) == DMA_IT_TC_MORT_MORT_MORTIF6) || ((IT) == DMA_IT_HTIF6) || \ |
| rajathr | 0:34ee385f4d2d | 508 | ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \ |
| rajathr | 0:34ee385f4d2d | 509 | ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TC_MORT_MORT_MORT_MORT_MORTIF7) || \ |
| rajathr | 0:34ee385f4d2d | 510 | ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \ |
| rajathr | 0:34ee385f4d2d | 511 | ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7)) |
| rajathr | 0:34ee385f4d2d | 512 | /** |
| rajathr | 0:34ee385f4d2d | 513 | * @} |
| rajathr | 0:34ee385f4d2d | 514 | */ |
| rajathr | 0:34ee385f4d2d | 515 | |
| rajathr | 0:34ee385f4d2d | 516 | |
| rajathr | 0:34ee385f4d2d | 517 | /** @defgroup DMA_peripheral_increment_offset |
| rajathr | 0:34ee385f4d2d | 518 | * @{ |
| rajathr | 0:34ee385f4d2d | 519 | */ |
| rajathr | 0:34ee385f4d2d | 520 | #define DMA_PINCOS_Psize ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 521 | #define DMA_PINCOS_WordAligned ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 522 | |
| rajathr | 0:34ee385f4d2d | 523 | #define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \ |
| rajathr | 0:34ee385f4d2d | 524 | ((SIZE) == DMA_PINCOS_WordAligned)) |
| rajathr | 0:34ee385f4d2d | 525 | /** |
| rajathr | 0:34ee385f4d2d | 526 | * @} |
| rajathr | 0:34ee385f4d2d | 527 | */ |
| rajathr | 0:34ee385f4d2d | 528 | |
| rajathr | 0:34ee385f4d2d | 529 | |
| rajathr | 0:34ee385f4d2d | 530 | /** @defgroup DMA_flow_controller_definitions |
| rajathr | 0:34ee385f4d2d | 531 | * @{ |
| rajathr | 0:34ee385f4d2d | 532 | */ |
| rajathr | 0:34ee385f4d2d | 533 | #define DMA_FlowCtrl_Memory ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 534 | #define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 535 | |
| rajathr | 0:34ee385f4d2d | 536 | #define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \ |
| rajathr | 0:34ee385f4d2d | 537 | ((CTRL) == DMA_FlowCtrl_Peripheral)) |
| rajathr | 0:34ee385f4d2d | 538 | /** |
| rajathr | 0:34ee385f4d2d | 539 | * @} |
| rajathr | 0:34ee385f4d2d | 540 | */ |
| rajathr | 0:34ee385f4d2d | 541 | |
| rajathr | 0:34ee385f4d2d | 542 | |
| rajathr | 0:34ee385f4d2d | 543 | /** @defgroup DMA_memory_targets_definitions |
| rajathr | 0:34ee385f4d2d | 544 | * @{ |
| rajathr | 0:34ee385f4d2d | 545 | */ |
| rajathr | 0:34ee385f4d2d | 546 | #define DMA_Memory_0 ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 547 | #define DMA_Memory_1 ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 548 | |
| rajathr | 0:34ee385f4d2d | 549 | #define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1)) |
| rajathr | 0:34ee385f4d2d | 550 | /** |
| rajathr | 0:34ee385f4d2d | 551 | * @} |
| rajathr | 0:34ee385f4d2d | 552 | */ |
| rajathr | 0:34ee385f4d2d | 553 | |
| rajathr | 0:34ee385f4d2d | 554 | /** |
| rajathr | 0:34ee385f4d2d | 555 | * @} |
| rajathr | 0:34ee385f4d2d | 556 | */ |
| rajathr | 0:34ee385f4d2d | 557 | |
| rajathr | 0:34ee385f4d2d | 558 | /* Exported macro ------------------------------------------------------------*/ |
| rajathr | 0:34ee385f4d2d | 559 | /* Exported functions --------------------------------------------------------*/ |
| rajathr | 0:34ee385f4d2d | 560 | |
| rajathr | 0:34ee385f4d2d | 561 | /* Function used to set the DMA configuration to the default reset state *****/ |
| rajathr | 0:34ee385f4d2d | 562 | void DMA_DeInit_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx); |
| rajathr | 0:34ee385f4d2d | 563 | |
| rajathr | 0:34ee385f4d2d | 564 | /* Initialization and Configuration functions *********************************/ |
| rajathr | 0:34ee385f4d2d | 565 | void DMA_Init_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, DMA_InitTypeDef_mort* DMA_InitStruct); |
| rajathr | 0:34ee385f4d2d | 566 | void DMA_StructInit_mort(DMA_InitTypeDef_mort* DMA_InitStruct); |
| rajathr | 0:34ee385f4d2d | 567 | void DMA_Cmd_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, FunctionalState NewState); |
| rajathr | 0:34ee385f4d2d | 568 | |
| rajathr | 0:34ee385f4d2d | 569 | /* Optional Configuration functions *******************************************/ |
| rajathr | 0:34ee385f4d2d | 570 | void DMA_PeriphIncOffsetSizeConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_Pincos); |
| rajathr | 0:34ee385f4d2d | 571 | void DMA_FlowControllerConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FlowCtrl); |
| rajathr | 0:34ee385f4d2d | 572 | |
| rajathr | 0:34ee385f4d2d | 573 | /* Data Counter functions *****************************************************/ |
| rajathr | 0:34ee385f4d2d | 574 | void DMA_SetCurrDataCounter_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint16_t Counter); |
| rajathr | 0:34ee385f4d2d | 575 | uint16_t DMA_GetCurrDataCounter_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx); |
| rajathr | 0:34ee385f4d2d | 576 | |
| rajathr | 0:34ee385f4d2d | 577 | /* Double Buffer mode functions ***********************************************/ |
| rajathr | 0:34ee385f4d2d | 578 | void DMA_DoubleBufferModeConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t Memory1BaseAddr, |
| rajathr | 0:34ee385f4d2d | 579 | uint32_t DMA_CurrentMemory); |
| rajathr | 0:34ee385f4d2d | 580 | void DMA_DoubleBufferModeCmd_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, FunctionalState NewState); |
| rajathr | 0:34ee385f4d2d | 581 | void DMA_MemoryTargetConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t MemoryBaseAddr, |
| rajathr | 0:34ee385f4d2d | 582 | uint32_t DMA_MemoryTarget); |
| rajathr | 0:34ee385f4d2d | 583 | uint32_t DMA_GetCurrentMemoryTarget_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx); |
| rajathr | 0:34ee385f4d2d | 584 | |
| rajathr | 0:34ee385f4d2d | 585 | /* Interrupts and flags management functions **********************************/ |
| rajathr | 0:34ee385f4d2d | 586 | FunctionalState DMA_GetCmdStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx); |
| rajathr | 0:34ee385f4d2d | 587 | uint32_t DMA_GetFIFOStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx); |
| rajathr | 0:34ee385f4d2d | 588 | FlagStatus DMA_GetFlagStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FLAG); |
| rajathr | 0:34ee385f4d2d | 589 | void DMA_ClearFlag_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_FLAG); |
| rajathr | 0:34ee385f4d2d | 590 | void DMA_ITConfig_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); |
| rajathr | 0:34ee385f4d2d | 591 | ITStatus DMA_GetITStatus_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT); |
| rajathr | 0:34ee385f4d2d | 592 | void DMA_ClearITPendingBit_mort(DMA_Stream_TypeDef_mort* DMAy_Streamx, uint32_t DMA_IT); |
| rajathr | 0:34ee385f4d2d | 593 | |
| rajathr | 0:34ee385f4d2d | 594 | #ifdef __cplusplus |
| rajathr | 0:34ee385f4d2d | 595 | } |
| rajathr | 0:34ee385f4d2d | 596 | #endif |
| rajathr | 0:34ee385f4d2d | 597 | |
| rajathr | 0:34ee385f4d2d | 598 | #endif /*__STM32F4xx_DMA_H_MORT */ |
| rajathr | 0:34ee385f4d2d | 599 | |
| rajathr | 0:34ee385f4d2d | 600 | /** |
| rajathr | 0:34ee385f4d2d | 601 | * @} |
| rajathr | 0:34ee385f4d2d | 602 | */ |
| rajathr | 0:34ee385f4d2d | 603 | |
| rajathr | 0:34ee385f4d2d | 604 | /** |
| rajathr | 0:34ee385f4d2d | 605 | * @} |
| rajathr | 0:34ee385f4d2d | 606 | */ |
| rajathr | 0:34ee385f4d2d | 607 | |
| rajathr | 0:34ee385f4d2d | 608 | |
| rajathr | 0:34ee385f4d2d | 609 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| rajathr | 0:34ee385f4d2d | 610 | |
| rajathr | 0:34ee385f4d2d | 611 | |
| rajathr | 0:34ee385f4d2d | 612 | |
| rajathr | 0:34ee385f4d2d | 613 | |
| rajathr | 0:34ee385f4d2d | 614 |