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Dependencies:   mbed

stm32f4xx_tim_mort.c@0:34ee385f4d2d, 2021-10-23 (annotated)

Committer:
rajathr
Date:
Sat Oct 23 05:49:09 2021 +0000
Revision:
0:34ee385f4d2d
At 23rd Oct 21 - All Code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rajathr 0:34ee385f4d2d 1 /**
rajathr 0:34ee385f4d2d 2 ******************************************************************************
rajathr 0:34ee385f4d2d 3 * @file stm32f4xx_tim.c
rajathr 0:34ee385f4d2d 4 * @author MCD Application Team
rajathr 0:34ee385f4d2d 5 * @version V1.8.0
rajathr 0:34ee385f4d2d 6 * @date 04-November-2016
rajathr 0:34ee385f4d2d 7 * @brief This file provides firmware functions to manage the following
rajathr 0:34ee385f4d2d 8 * functionalities of the TIM peripheral:
rajathr 0:34ee385f4d2d 9 * + TimeBase management
rajathr 0:34ee385f4d2d 10 * + Output Compare management
rajathr 0:34ee385f4d2d 11 * + Input Capture management
rajathr 0:34ee385f4d2d 12 * + Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features
rajathr 0:34ee385f4d2d 13 * + Interrupts, DMA and flags management
rajathr 0:34ee385f4d2d 14 * + Clocks management
rajathr 0:34ee385f4d2d 15 * + Synchronization management
rajathr 0:34ee385f4d2d 16 * + Specific interface management
rajathr 0:34ee385f4d2d 17 * + Specific remapping management
rajathr 0:34ee385f4d2d 18 *
rajathr 0:34ee385f4d2d 19 @verbatim
rajathr 0:34ee385f4d2d 20 ===============================================================================
rajathr 0:34ee385f4d2d 21 ##### How to use this driver #####
rajathr 0:34ee385f4d2d 22 ===============================================================================
rajathr 0:34ee385f4d2d 23 [..]
rajathr 0:34ee385f4d2d 24 This driver provides functions to configure and program the TIM
rajathr 0:34ee385f4d2d 25 of all STM32F4xx devices.
rajathr 0:34ee385f4d2d 26 These functions are split in 9 groups:
rajathr 0:34ee385f4d2d 27
rajathr 0:34ee385f4d2d 28 (#) TIM TimeBase management: this group includes all needed functions
rajathr 0:34ee385f4d2d 29 to configure the TM Timebase unit:
rajathr 0:34ee385f4d2d 30 (++) Set/Get Prescaler
rajathr 0:34ee385f4d2d 31 (++) Set/Get Autoreload
rajathr 0:34ee385f4d2d 32 (++) Counter modes configuration
rajathr 0:34ee385f4d2d 33 (++) Set Clock division
rajathr 0:34ee385f4d2d 34 (++) Select the One Pulse mode
rajathr 0:34ee385f4d2d 35 (++) Update Request Configuration
rajathr 0:34ee385f4d2d 36 (++) Update Disable Configuration
rajathr 0:34ee385f4d2d 37 (++) Auto-Preload Configuration
rajathr 0:34ee385f4d2d 38 (++) Enable/Disable the counter
rajathr 0:34ee385f4d2d 39
rajathr 0:34ee385f4d2d 40 (#) TIM Output Compare management: this group includes all needed
rajathr 0:34ee385f4d2d 41 functions to configure the Capture/Compare unit used in Output
rajathr 0:34ee385f4d2d 42 compare mode:
rajathr 0:34ee385f4d2d 43 (++) Configure each channel, independently, in Output Compare mode
rajathr 0:34ee385f4d2d 44 (++) Select the output compare modes
rajathr 0:34ee385f4d2d 45 (++) Select the Polarities of each channel
rajathr 0:34ee385f4d2d 46 (++) Set/Get the Capture/Compare register values
rajathr 0:34ee385f4d2d 47 (++) Select the Output Compare Fast mode
rajathr 0:34ee385f4d2d 48 (++) Select the Output Compare Forced mode
rajathr 0:34ee385f4d2d 49 (++) Output Compare-Preload Configuration
rajathr 0:34ee385f4d2d 50 (++) Clear Output Compare Reference
rajathr 0:34ee385f4d2d 51 (++) Select the OCREF Clear signal
rajathr 0:34ee385f4d2d 52 (++) Enable/Disable the Capture/Compare Channels
rajathr 0:34ee385f4d2d 53
rajathr 0:34ee385f4d2d 54 (#) TIM Input Capture management: this group includes all needed
rajathr 0:34ee385f4d2d 55 functions to configure the Capture/Compare unit used in
rajathr 0:34ee385f4d2d 56 Input Capture mode:
rajathr 0:34ee385f4d2d 57 (++) Configure each channel in input capture mode
rajathr 0:34ee385f4d2d 58 (++) Configure Channel1/2 in PWM Input mode
rajathr 0:34ee385f4d2d 59 (++) Set the Input Capture Prescaler
rajathr 0:34ee385f4d2d 60 (++) Get the Capture/Compare values
rajathr 0:34ee385f4d2d 61
rajathr 0:34ee385f4d2d 62 (#) Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features
rajathr 0:34ee385f4d2d 63 (++) Configures the Break input, dead time, Lock level, the OSSI,
rajathr 0:34ee385f4d2d 64 the OSSR State and the AOE(automatic output enable)
rajathr 0:34ee385f4d2d 65 (++) Enable/Disable the TIM peripheral Main Outputs
rajathr 0:34ee385f4d2d 66 (++) Select the Commutation event
rajathr 0:34ee385f4d2d 67 (++) Set/Reset the Capture Compare Preload Control bit
rajathr 0:34ee385f4d2d 68
rajathr 0:34ee385f4d2d 69 (#) TIM interrupts, DMA and flags management
rajathr 0:34ee385f4d2d 70 (++) Enable/Disable interrupt sources
rajathr 0:34ee385f4d2d 71 (++) Get flags status
rajathr 0:34ee385f4d2d 72 (++) Clear flags/ Pending bits
rajathr 0:34ee385f4d2d 73 (++) Enable/Disable DMA requests
rajathr 0:34ee385f4d2d 74 (++) Configure DMA burst mode
rajathr 0:34ee385f4d2d 75 (++) Select CaptureCompare DMA request
rajathr 0:34ee385f4d2d 76
rajathr 0:34ee385f4d2d 77 (#) TIM clocks management: this group includes all needed functions
rajathr 0:34ee385f4d2d 78 to configure the clock controller unit:
rajathr 0:34ee385f4d2d 79 (++) Select internal/External clock
rajathr 0:34ee385f4d2d 80 (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
rajathr 0:34ee385f4d2d 81
rajathr 0:34ee385f4d2d 82 (#) TIM synchronization management: this group includes all needed
rajathr 0:34ee385f4d2d 83 functions to configure the Synchronization unit:
rajathr 0:34ee385f4d2d 84 (++) Select Input Trigger
rajathr 0:34ee385f4d2d 85 (++) Select Output Trigger
rajathr 0:34ee385f4d2d 86 (++) Select Master Slave Mode
rajathr 0:34ee385f4d2d 87 (++) ETR Configuration when used as external trigger
rajathr 0:34ee385f4d2d 88
rajathr 0:34ee385f4d2d 89 (#) TIM specific interface management, this group includes all
rajathr 0:34ee385f4d2d 90 needed functions to use the specific TIM interface:
rajathr 0:34ee385f4d2d 91 (++) Encoder Interface Configuration
rajathr 0:34ee385f4d2d 92 (++) Select Hall Sensor
rajathr 0:34ee385f4d2d 93
rajathr 0:34ee385f4d2d 94 (#) TIM specific remapping management includes the Remapping
rajathr 0:34ee385f4d2d 95 configuration of specific timers
rajathr 0:34ee385f4d2d 96
rajathr 0:34ee385f4d2d 97 @endverbatim
rajathr 0:34ee385f4d2d 98 ******************************************************************************
rajathr 0:34ee385f4d2d 99 * @attention
rajathr 0:34ee385f4d2d 100 *
rajathr 0:34ee385f4d2d 101 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
rajathr 0:34ee385f4d2d 102 *
rajathr 0:34ee385f4d2d 103 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
rajathr 0:34ee385f4d2d 104 * You may not use this file except in compliance with the License.
rajathr 0:34ee385f4d2d 105 * You may obtain a copy of the License at:
rajathr 0:34ee385f4d2d 106 *
rajathr 0:34ee385f4d2d 107 * http://www.st.com/software_license_agreement_liberty_v2
rajathr 0:34ee385f4d2d 108 *
rajathr 0:34ee385f4d2d 109 * Unless required by applicable law or agreed to in writing, software
rajathr 0:34ee385f4d2d 110 * distributed under the License is distributed on an "AS IS" BASIS,
rajathr 0:34ee385f4d2d 111 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
rajathr 0:34ee385f4d2d 112 * See the License for the specific language governing permissions and
rajathr 0:34ee385f4d2d 113 * limitations under the License.
rajathr 0:34ee385f4d2d 114 *
rajathr 0:34ee385f4d2d 115 ******************************************************************************
rajathr 0:34ee385f4d2d 116 */
rajathr 0:34ee385f4d2d 117
rajathr 0:34ee385f4d2d 118 /* Includes ------------------------------------------------------------------*/
rajathr 0:34ee385f4d2d 119 #include "stm32f4xx_tim_mort.h"
rajathr 0:34ee385f4d2d 120 #include "stm32f4xx_rcc_mort.h"
rajathr 0:34ee385f4d2d 121
rajathr 0:34ee385f4d2d 122 /** @addtogroup STM32F4xx_StdPeriph_Driver
rajathr 0:34ee385f4d2d 123 * @{
rajathr 0:34ee385f4d2d 124 */
rajathr 0:34ee385f4d2d 125
rajathr 0:34ee385f4d2d 126 /** @defgroup TIM
rajathr 0:34ee385f4d2d 127 * @brief TIM driver modules
rajathr 0:34ee385f4d2d 128 * @{
rajathr 0:34ee385f4d2d 129 */
rajathr 0:34ee385f4d2d 130
rajathr 0:34ee385f4d2d 131 /* Private typedef -----------------------------------------------------------*/
rajathr 0:34ee385f4d2d 132 /* Private define ------------------------------------------------------------*/
rajathr 0:34ee385f4d2d 133
rajathr 0:34ee385f4d2d 134 /* ---------------------- TIM registers bit mask ------------------------ */
rajathr 0:34ee385f4d2d 135 #define SMCR_ETR_MASK_MORT ((uint16_t)0x00FF)
rajathr 0:34ee385f4d2d 136 #define CCMR_OFFSET_MORT ((uint16_t)0x0018)
rajathr 0:34ee385f4d2d 137 #define CCER_CCE_SET_MORT ((uint16_t)0x0001)
rajathr 0:34ee385f4d2d 138 #define CCER_CCNE_SET_MORT ((uint16_t)0x0004)
rajathr 0:34ee385f4d2d 139 #define CCMR_OC13M_MASK_MORT ((uint16_t)0xFF8F)
rajathr 0:34ee385f4d2d 140 #define CCMR_OC24M_MASK_MORT ((uint16_t)0x8FFF)
rajathr 0:34ee385f4d2d 141
rajathr 0:34ee385f4d2d 142 /* Private macro -------------------------------------------------------------*/
rajathr 0:34ee385f4d2d 143 /* Private variables ---------------------------------------------------------*/
rajathr 0:34ee385f4d2d 144 /* Private function prototypes -----------------------------------------------*/
rajathr 0:34ee385f4d2d 145 static void TI1_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
rajathr 0:34ee385f4d2d 146 uint16_t TIM_ICFilter);
rajathr 0:34ee385f4d2d 147 static void TI2_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
rajathr 0:34ee385f4d2d 148 uint16_t TIM_ICFilter);
rajathr 0:34ee385f4d2d 149 static void TI3_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
rajathr 0:34ee385f4d2d 150 uint16_t TIM_ICFilter);
rajathr 0:34ee385f4d2d 151 static void TI4_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
rajathr 0:34ee385f4d2d 152 uint16_t TIM_ICFilter);
rajathr 0:34ee385f4d2d 153
rajathr 0:34ee385f4d2d 154 /* Private functions ---------------------------------------------------------*/
rajathr 0:34ee385f4d2d 155
rajathr 0:34ee385f4d2d 156 /** @defgroup TIM_Private_Functions
rajathr 0:34ee385f4d2d 157 * @{
rajathr 0:34ee385f4d2d 158 */
rajathr 0:34ee385f4d2d 159
rajathr 0:34ee385f4d2d 160 /** @defgroup TIM_Group1 TimeBase management functions
rajathr 0:34ee385f4d2d 161 * @brief TimeBase management functions
rajathr 0:34ee385f4d2d 162 *
rajathr 0:34ee385f4d2d 163 @verbatim
rajathr 0:34ee385f4d2d 164 ===============================================================================
rajathr 0:34ee385f4d2d 165 ##### TimeBase management functions #####
rajathr 0:34ee385f4d2d 166 ===============================================================================
rajathr 0:34ee385f4d2d 167
rajathr 0:34ee385f4d2d 168
rajathr 0:34ee385f4d2d 169 ##### TIM Driver: how to use it in Timing(Time base) Mode #####
rajathr 0:34ee385f4d2d 170 ===============================================================================
rajathr 0:34ee385f4d2d 171 [..]
rajathr 0:34ee385f4d2d 172 To use the Timer in Timing(Time base) mode, the following steps are mandatory:
rajathr 0:34ee385f4d2d 173
rajathr 0:34ee385f4d2d 174 (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
rajathr 0:34ee385f4d2d 175
rajathr 0:34ee385f4d2d 176 (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
rajathr 0:34ee385f4d2d 177
rajathr 0:34ee385f4d2d 178 (#) Call TIM_TimeBaseInit_mort(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit
rajathr 0:34ee385f4d2d 179 with the corresponding configuration
rajathr 0:34ee385f4d2d 180
rajathr 0:34ee385f4d2d 181 (#) Enable the NVIC if you need to generate the update interrupt.
rajathr 0:34ee385f4d2d 182
rajathr 0:34ee385f4d2d 183 (#) Enable the corresponding interrupt using the function TIM_ITConfig_mort(TIMx, TIM_IT_Update_MORT)
rajathr 0:34ee385f4d2d 184
rajathr 0:34ee385f4d2d 185 (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
rajathr 0:34ee385f4d2d 186
rajathr 0:34ee385f4d2d 187 -@- All other functions can be used separately to modify, if needed,
rajathr 0:34ee385f4d2d 188 a specific feature of the Timer.
rajathr 0:34ee385f4d2d 189
rajathr 0:34ee385f4d2d 190 @endverbatim
rajathr 0:34ee385f4d2d 191 * @{
rajathr 0:34ee385f4d2d 192 */
rajathr 0:34ee385f4d2d 193
rajathr 0:34ee385f4d2d 194 /**
rajathr 0:34ee385f4d2d 195 * @brief Deinitializes the TIMx peripheral registers to their default reset values.
rajathr 0:34ee385f4d2d 196 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 197 * @retval None
rajathr 0:34ee385f4d2d 198
rajathr 0:34ee385f4d2d 199 */
rajathr 0:34ee385f4d2d 200 void TIM_DeInit_mort(TIM_TypeDef_mort* TIMx)
rajathr 0:34ee385f4d2d 201 {
rajathr 0:34ee385f4d2d 202 /* Check the parameters */
rajathr 0:34ee385f4d2d 203 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 204
rajathr 0:34ee385f4d2d 205 if (TIMx == TIM1_MORT)
rajathr 0:34ee385f4d2d 206 {
rajathr 0:34ee385f4d2d 207 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
rajathr 0:34ee385f4d2d 208 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
rajathr 0:34ee385f4d2d 209 }
rajathr 0:34ee385f4d2d 210 else if (TIMx == TIM2_MORT)
rajathr 0:34ee385f4d2d 211 {
rajathr 0:34ee385f4d2d 212 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
rajathr 0:34ee385f4d2d 213 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
rajathr 0:34ee385f4d2d 214 }
rajathr 0:34ee385f4d2d 215 else if (TIMx == TIM3_MORT)
rajathr 0:34ee385f4d2d 216 {
rajathr 0:34ee385f4d2d 217 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
rajathr 0:34ee385f4d2d 218 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
rajathr 0:34ee385f4d2d 219 }
rajathr 0:34ee385f4d2d 220 else if (TIMx == TIM4_MORT)
rajathr 0:34ee385f4d2d 221 {
rajathr 0:34ee385f4d2d 222 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
rajathr 0:34ee385f4d2d 223 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
rajathr 0:34ee385f4d2d 224 }
rajathr 0:34ee385f4d2d 225 else if (TIMx == TIM5_MORT)
rajathr 0:34ee385f4d2d 226 {
rajathr 0:34ee385f4d2d 227 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
rajathr 0:34ee385f4d2d 228 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
rajathr 0:34ee385f4d2d 229 }
rajathr 0:34ee385f4d2d 230 else if (TIMx == TIM6_MORT)
rajathr 0:34ee385f4d2d 231 {
rajathr 0:34ee385f4d2d 232 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
rajathr 0:34ee385f4d2d 233 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
rajathr 0:34ee385f4d2d 234 }
rajathr 0:34ee385f4d2d 235 else if (TIMx == TIM7_MORT)
rajathr 0:34ee385f4d2d 236 {
rajathr 0:34ee385f4d2d 237 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
rajathr 0:34ee385f4d2d 238 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
rajathr 0:34ee385f4d2d 239 }
rajathr 0:34ee385f4d2d 240 else if (TIMx == TIM8_MORT)
rajathr 0:34ee385f4d2d 241 {
rajathr 0:34ee385f4d2d 242 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
rajathr 0:34ee385f4d2d 243 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
rajathr 0:34ee385f4d2d 244 }
rajathr 0:34ee385f4d2d 245 else if (TIMx == TIM9_MORT)
rajathr 0:34ee385f4d2d 246 {
rajathr 0:34ee385f4d2d 247 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
rajathr 0:34ee385f4d2d 248 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
rajathr 0:34ee385f4d2d 249 }
rajathr 0:34ee385f4d2d 250 else if (TIMx == TIM10_MORT)
rajathr 0:34ee385f4d2d 251 {
rajathr 0:34ee385f4d2d 252 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
rajathr 0:34ee385f4d2d 253 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
rajathr 0:34ee385f4d2d 254 }
rajathr 0:34ee385f4d2d 255 else if (TIMx == TIM11_MORT)
rajathr 0:34ee385f4d2d 256 {
rajathr 0:34ee385f4d2d 257 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
rajathr 0:34ee385f4d2d 258 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
rajathr 0:34ee385f4d2d 259 }
rajathr 0:34ee385f4d2d 260 else if (TIMx == TIM12_MORT)
rajathr 0:34ee385f4d2d 261 {
rajathr 0:34ee385f4d2d 262 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
rajathr 0:34ee385f4d2d 263 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
rajathr 0:34ee385f4d2d 264 }
rajathr 0:34ee385f4d2d 265 else if (TIMx == TIM13_MORT)
rajathr 0:34ee385f4d2d 266 {
rajathr 0:34ee385f4d2d 267 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
rajathr 0:34ee385f4d2d 268 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
rajathr 0:34ee385f4d2d 269 }
rajathr 0:34ee385f4d2d 270 else
rajathr 0:34ee385f4d2d 271 {
rajathr 0:34ee385f4d2d 272 if (TIMx == TIM14_MORT)
rajathr 0:34ee385f4d2d 273 {
rajathr 0:34ee385f4d2d 274 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
rajathr 0:34ee385f4d2d 275 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
rajathr 0:34ee385f4d2d 276 }
rajathr 0:34ee385f4d2d 277 }
rajathr 0:34ee385f4d2d 278 }
rajathr 0:34ee385f4d2d 279
rajathr 0:34ee385f4d2d 280 /**
rajathr 0:34ee385f4d2d 281 * @brief Initializes the TIMx Time Base Unit peripheral according to
rajathr 0:34ee385f4d2d 282 * the specified parameters in the TIM_TimeBaseInitStruct.
rajathr 0:34ee385f4d2d 283 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 284 * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef_mort structure
rajathr 0:34ee385f4d2d 285 * that contains the configuration information for the specified TIM peripheral.
rajathr 0:34ee385f4d2d 286 * @retval None
rajathr 0:34ee385f4d2d 287 */
rajathr 0:34ee385f4d2d 288 void TIM_TimeBaseInit_mort(TIM_TypeDef_mort* TIMx, TIM_TimeBaseInitTypeDef_mort* TIM_TimeBaseInitStruct)
rajathr 0:34ee385f4d2d 289 {
rajathr 0:34ee385f4d2d 290 uint16_t tmpcr1 = 0;
rajathr 0:34ee385f4d2d 291
rajathr 0:34ee385f4d2d 292 /* Check the parameters */
rajathr 0:34ee385f4d2d 293 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 294 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
rajathr 0:34ee385f4d2d 295 assert_param(IS_TIM_CKD_DIV_MORT(TIM_TimeBaseInitStruct->TIM_ClockDivision));
rajathr 0:34ee385f4d2d 296
rajathr 0:34ee385f4d2d 297 tmpcr1 = TIMx->CR1;
rajathr 0:34ee385f4d2d 298
rajathr 0:34ee385f4d2d 299 if((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT)||
rajathr 0:34ee385f4d2d 300 (TIMx == TIM2_MORT) || (TIMx == TIM3_MORT)||
rajathr 0:34ee385f4d2d 301 (TIMx == TIM4_MORT) || (TIMx == TIM5_MORT))
rajathr 0:34ee385f4d2d 302 {
rajathr 0:34ee385f4d2d 303 /* Select the Counter Mode */
rajathr 0:34ee385f4d2d 304 tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR_MORT | TIM_CR1_CMS_MORT));
rajathr 0:34ee385f4d2d 305 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
rajathr 0:34ee385f4d2d 306 }
rajathr 0:34ee385f4d2d 307
rajathr 0:34ee385f4d2d 308 if((TIMx != TIM6_MORT) && (TIMx != TIM7_MORT))
rajathr 0:34ee385f4d2d 309 {
rajathr 0:34ee385f4d2d 310 /* Set the clock division */
rajathr 0:34ee385f4d2d 311 tmpcr1 &= (uint16_t)(~TIM_CR1_CKD_MORT);
rajathr 0:34ee385f4d2d 312 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
rajathr 0:34ee385f4d2d 313 }
rajathr 0:34ee385f4d2d 314
rajathr 0:34ee385f4d2d 315 TIMx->CR1 = tmpcr1;
rajathr 0:34ee385f4d2d 316
rajathr 0:34ee385f4d2d 317 /* Set the Autoreload value */
rajathr 0:34ee385f4d2d 318 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
rajathr 0:34ee385f4d2d 319
rajathr 0:34ee385f4d2d 320 /* Set the Prescaler value */
rajathr 0:34ee385f4d2d 321 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
rajathr 0:34ee385f4d2d 322
rajathr 0:34ee385f4d2d 323 if ((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT))
rajathr 0:34ee385f4d2d 324 {
rajathr 0:34ee385f4d2d 325 /* Set the Repetition Counter value */
rajathr 0:34ee385f4d2d 326 TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
rajathr 0:34ee385f4d2d 327 }
rajathr 0:34ee385f4d2d 328
rajathr 0:34ee385f4d2d 329 /* Generate an update event to reload the Prescaler
rajathr 0:34ee385f4d2d 330 and the repetition counter(only for TIM1_MORT and TIM8_MORT) value immediately */
rajathr 0:34ee385f4d2d 331 TIMx->EGR = TIM_PSCReloadMode_Immediate_MORT;
rajathr 0:34ee385f4d2d 332 }
rajathr 0:34ee385f4d2d 333
rajathr 0:34ee385f4d2d 334 /**
rajathr 0:34ee385f4d2d 335 * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
rajathr 0:34ee385f4d2d 336 * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef_mort
rajathr 0:34ee385f4d2d 337 * structure which will be initialized.
rajathr 0:34ee385f4d2d 338 * @retval None
rajathr 0:34ee385f4d2d 339 */
rajathr 0:34ee385f4d2d 340 void TIM_TimeBaseStructInit_mort(TIM_TimeBaseInitTypeDef_mort* TIM_TimeBaseInitStruct)
rajathr 0:34ee385f4d2d 341 {
rajathr 0:34ee385f4d2d 342 /* Set the default configuration */
rajathr 0:34ee385f4d2d 343 TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
rajathr 0:34ee385f4d2d 344 TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
rajathr 0:34ee385f4d2d 345 TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1_MORT;
rajathr 0:34ee385f4d2d 346 TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up_MORT;
rajathr 0:34ee385f4d2d 347 TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
rajathr 0:34ee385f4d2d 348 }
rajathr 0:34ee385f4d2d 349
rajathr 0:34ee385f4d2d 350 /**
rajathr 0:34ee385f4d2d 351 * @brief Configures the TIMx Prescaler.
rajathr 0:34ee385f4d2d 352 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 353 * @param Prescaler: specifies the Prescaler Register value
rajathr 0:34ee385f4d2d 354 * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
rajathr 0:34ee385f4d2d 355 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 356 * @arg TIM_PSCReloadMode_Update_MORT: The Prescaler is loaded at the update event.
rajathr 0:34ee385f4d2d 357 * @arg TIM_PSCReloadMode_Immediate_MORT: The Prescaler is loaded immediately.
rajathr 0:34ee385f4d2d 358 * @retval None
rajathr 0:34ee385f4d2d 359 */
rajathr 0:34ee385f4d2d 360 void TIM_PrescalerConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
rajathr 0:34ee385f4d2d 361 {
rajathr 0:34ee385f4d2d 362 /* Check the parameters */
rajathr 0:34ee385f4d2d 363 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 364 assert_param(IS_TIM_PRESCALER_RELOAD_MORT(TIM_PSCReloadMode));
rajathr 0:34ee385f4d2d 365 /* Set the Prescaler value */
rajathr 0:34ee385f4d2d 366 TIMx->PSC = Prescaler;
rajathr 0:34ee385f4d2d 367 /* Set or reset the UG Bit */
rajathr 0:34ee385f4d2d 368 TIMx->EGR = TIM_PSCReloadMode;
rajathr 0:34ee385f4d2d 369 }
rajathr 0:34ee385f4d2d 370
rajathr 0:34ee385f4d2d 371 /**
rajathr 0:34ee385f4d2d 372 * @brief Specifies the TIMx Counter Mode to be used.
rajathr 0:34ee385f4d2d 373 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 374 * @param TIM_CounterMode: specifies the Counter Mode to be used
rajathr 0:34ee385f4d2d 375 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 376 * @arg TIM_CounterMode_Up_MORT: TIM Up Counting Mode
rajathr 0:34ee385f4d2d 377 * @arg TIM_CounterMode_Down_MORT: TIM Down Counting Mode
rajathr 0:34ee385f4d2d 378 * @arg TIM_CounterMode_CenterAligned1_MORT: TIM Center Aligned Mode1
rajathr 0:34ee385f4d2d 379 * @arg TIM_CounterMode_CenterAligned2_MORT: TIM Center Aligned Mode2
rajathr 0:34ee385f4d2d 380 * @arg TIM_CounterMode_CenterAligned3_MORT: TIM Center Aligned Mode3
rajathr 0:34ee385f4d2d 381 * @retval None
rajathr 0:34ee385f4d2d 382 */
rajathr 0:34ee385f4d2d 383 void TIM_CounterModeConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_CounterMode)
rajathr 0:34ee385f4d2d 384 {
rajathr 0:34ee385f4d2d 385 uint16_t tmpcr1 = 0;
rajathr 0:34ee385f4d2d 386
rajathr 0:34ee385f4d2d 387 /* Check the parameters */
rajathr 0:34ee385f4d2d 388 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 389 assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
rajathr 0:34ee385f4d2d 390
rajathr 0:34ee385f4d2d 391 tmpcr1 = TIMx->CR1;
rajathr 0:34ee385f4d2d 392
rajathr 0:34ee385f4d2d 393 /* Reset the CMS and DIR Bits */
rajathr 0:34ee385f4d2d 394 tmpcr1 &= (uint16_t)~(TIM_CR1_DIR_MORT | TIM_CR1_CMS_MORT);
rajathr 0:34ee385f4d2d 395
rajathr 0:34ee385f4d2d 396 /* Set the Counter Mode */
rajathr 0:34ee385f4d2d 397 tmpcr1 |= TIM_CounterMode;
rajathr 0:34ee385f4d2d 398
rajathr 0:34ee385f4d2d 399 /* Write to TIMx CR1 register */
rajathr 0:34ee385f4d2d 400 TIMx->CR1 = tmpcr1;
rajathr 0:34ee385f4d2d 401 }
rajathr 0:34ee385f4d2d 402
rajathr 0:34ee385f4d2d 403 /**
rajathr 0:34ee385f4d2d 404 * @brief Sets the TIMx Counter Register value
rajathr 0:34ee385f4d2d 405 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 406 * @param Counter: specifies the Counter register new value.
rajathr 0:34ee385f4d2d 407 * @retval None
rajathr 0:34ee385f4d2d 408 */
rajathr 0:34ee385f4d2d 409 void TIM_SetCounter_mort(TIM_TypeDef_mort* TIMx, uint32_t Counter)
rajathr 0:34ee385f4d2d 410 {
rajathr 0:34ee385f4d2d 411 /* Check the parameters */
rajathr 0:34ee385f4d2d 412 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 413
rajathr 0:34ee385f4d2d 414 /* Set the Counter Register value */
rajathr 0:34ee385f4d2d 415 TIMx->CNT = Counter;
rajathr 0:34ee385f4d2d 416 }
rajathr 0:34ee385f4d2d 417
rajathr 0:34ee385f4d2d 418 /**
rajathr 0:34ee385f4d2d 419 * @brief Sets the TIMx Autoreload Register value
rajathr 0:34ee385f4d2d 420 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 421 * @param Autoreload: specifies the Autoreload register new value.
rajathr 0:34ee385f4d2d 422 * @retval None
rajathr 0:34ee385f4d2d 423 */
rajathr 0:34ee385f4d2d 424 void TIM_SetAutoreload_mort(TIM_TypeDef_mort* TIMx, uint32_t Autoreload)
rajathr 0:34ee385f4d2d 425 {
rajathr 0:34ee385f4d2d 426 /* Check the parameters */
rajathr 0:34ee385f4d2d 427 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 428
rajathr 0:34ee385f4d2d 429 /* Set the Autoreload Register value */
rajathr 0:34ee385f4d2d 430 TIMx->ARR = Autoreload;
rajathr 0:34ee385f4d2d 431 }
rajathr 0:34ee385f4d2d 432
rajathr 0:34ee385f4d2d 433 /**
rajathr 0:34ee385f4d2d 434 * @brief Gets the TIMx Counter value.
rajathr 0:34ee385f4d2d 435 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 436 * @retval Counter Register value
rajathr 0:34ee385f4d2d 437 */
rajathr 0:34ee385f4d2d 438 uint32_t TIM_GetCounter_mort(TIM_TypeDef_mort* TIMx)
rajathr 0:34ee385f4d2d 439 {
rajathr 0:34ee385f4d2d 440 /* Check the parameters */
rajathr 0:34ee385f4d2d 441 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 442
rajathr 0:34ee385f4d2d 443 /* Get the Counter Register value */
rajathr 0:34ee385f4d2d 444 return TIMx->CNT;
rajathr 0:34ee385f4d2d 445 }
rajathr 0:34ee385f4d2d 446
rajathr 0:34ee385f4d2d 447 /**
rajathr 0:34ee385f4d2d 448 * @brief Gets the TIMx Prescaler value.
rajathr 0:34ee385f4d2d 449 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 450 * @retval Prescaler Register value.
rajathr 0:34ee385f4d2d 451 */
rajathr 0:34ee385f4d2d 452 uint16_t TIM_GetPrescaler_mort(TIM_TypeDef_mort* TIMx)
rajathr 0:34ee385f4d2d 453 {
rajathr 0:34ee385f4d2d 454 /* Check the parameters */
rajathr 0:34ee385f4d2d 455 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 456
rajathr 0:34ee385f4d2d 457 /* Get the Prescaler Register value */
rajathr 0:34ee385f4d2d 458 return TIMx->PSC;
rajathr 0:34ee385f4d2d 459 }
rajathr 0:34ee385f4d2d 460
rajathr 0:34ee385f4d2d 461 /**
rajathr 0:34ee385f4d2d 462 * @brief Enables or Disables the TIMx Update event.
rajathr 0:34ee385f4d2d 463 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 464 * @param NewState: new state of the TIMx UDIS bit
rajathr 0:34ee385f4d2d 465 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 466 * @retval None
rajathr 0:34ee385f4d2d 467 */
rajathr 0:34ee385f4d2d 468 void TIM_UpdateDisableConfig_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 469 {
rajathr 0:34ee385f4d2d 470 /* Check the parameters */
rajathr 0:34ee385f4d2d 471 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 472 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 473
rajathr 0:34ee385f4d2d 474 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 475 {
rajathr 0:34ee385f4d2d 476 /* Set the Update Disable Bit */
rajathr 0:34ee385f4d2d 477 TIMx->CR1 |= TIM_CR1_UDIS_MORT;
rajathr 0:34ee385f4d2d 478 }
rajathr 0:34ee385f4d2d 479 else
rajathr 0:34ee385f4d2d 480 {
rajathr 0:34ee385f4d2d 481 /* Reset the Update Disable Bit */
rajathr 0:34ee385f4d2d 482 TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS_MORT;
rajathr 0:34ee385f4d2d 483 }
rajathr 0:34ee385f4d2d 484 }
rajathr 0:34ee385f4d2d 485
rajathr 0:34ee385f4d2d 486 /**
rajathr 0:34ee385f4d2d 487 * @brief Configures the TIMx Update Request Interrupt source.
rajathr 0:34ee385f4d2d 488 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 489 * @param TIM_UpdateSource: specifies the Update source.
rajathr 0:34ee385f4d2d 490 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 491 * @arg TIM_UpdateSource_Global_MORT: Source of update is the counter
rajathr 0:34ee385f4d2d 492 * overflow/underflow or the setting of UG bit, or an update
rajathr 0:34ee385f4d2d 493 * generation through the slave mode controller.
rajathr 0:34ee385f4d2d 494 * @arg TIM_UpdateSource_Regular_MORT: Source of update is counter overflow/underflow.
rajathr 0:34ee385f4d2d 495 * @retval None
rajathr 0:34ee385f4d2d 496 */
rajathr 0:34ee385f4d2d 497 void TIM_UpdateRequestConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_UpdateSource)
rajathr 0:34ee385f4d2d 498 {
rajathr 0:34ee385f4d2d 499 /* Check the parameters */
rajathr 0:34ee385f4d2d 500 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 501 assert_param(IS_TIM_UPDATE_SOURCE_MORT(TIM_UpdateSource));
rajathr 0:34ee385f4d2d 502
rajathr 0:34ee385f4d2d 503 if (TIM_UpdateSource != TIM_UpdateSource_Global_MORT)
rajathr 0:34ee385f4d2d 504 {
rajathr 0:34ee385f4d2d 505 /* Set the URS Bit */
rajathr 0:34ee385f4d2d 506 TIMx->CR1 |= TIM_CR1_URS_MORT;
rajathr 0:34ee385f4d2d 507 }
rajathr 0:34ee385f4d2d 508 else
rajathr 0:34ee385f4d2d 509 {
rajathr 0:34ee385f4d2d 510 /* Reset the URS Bit */
rajathr 0:34ee385f4d2d 511 TIMx->CR1 &= (uint16_t)~TIM_CR1_URS_MORT;
rajathr 0:34ee385f4d2d 512 }
rajathr 0:34ee385f4d2d 513 }
rajathr 0:34ee385f4d2d 514
rajathr 0:34ee385f4d2d 515 /**
rajathr 0:34ee385f4d2d 516 * @brief Enables or disables TIMx peripheral Preload register on ARR.
rajathr 0:34ee385f4d2d 517 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 518 * @param NewState: new state of the TIMx peripheral Preload register
rajathr 0:34ee385f4d2d 519 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 520 * @retval None
rajathr 0:34ee385f4d2d 521 */
rajathr 0:34ee385f4d2d 522 void TIM_ARRPreloadConfig_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 523 {
rajathr 0:34ee385f4d2d 524 /* Check the parameters */
rajathr 0:34ee385f4d2d 525 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 526 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 527
rajathr 0:34ee385f4d2d 528 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 529 {
rajathr 0:34ee385f4d2d 530 /* Set the ARR Preload Bit */
rajathr 0:34ee385f4d2d 531 TIMx->CR1 |= TIM_CR1_ARPE_MORT;
rajathr 0:34ee385f4d2d 532 }
rajathr 0:34ee385f4d2d 533 else
rajathr 0:34ee385f4d2d 534 {
rajathr 0:34ee385f4d2d 535 /* Reset the ARR Preload Bit */
rajathr 0:34ee385f4d2d 536 TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE_MORT;
rajathr 0:34ee385f4d2d 537 }
rajathr 0:34ee385f4d2d 538 }
rajathr 0:34ee385f4d2d 539
rajathr 0:34ee385f4d2d 540 /**
rajathr 0:34ee385f4d2d 541 * @brief Selects the TIMx's One Pulse Mode.
rajathr 0:34ee385f4d2d 542 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 543 * @param TIM_OPMode: specifies the OPM Mode to be used.
rajathr 0:34ee385f4d2d 544 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 545 * @arg TIM_OPMode_Single_MORT
rajathr 0:34ee385f4d2d 546 * @arg TIM_OPMode_Repetitive_MORT
rajathr 0:34ee385f4d2d 547 * @retval None
rajathr 0:34ee385f4d2d 548 */
rajathr 0:34ee385f4d2d 549 void TIM_SelectOnePulseMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OPMode)
rajathr 0:34ee385f4d2d 550 {
rajathr 0:34ee385f4d2d 551 /* Check the parameters */
rajathr 0:34ee385f4d2d 552 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 553 assert_param(IS_TIM_OPM_MODE_MORT(TIM_OPMode));
rajathr 0:34ee385f4d2d 554
rajathr 0:34ee385f4d2d 555 /* Reset the OPM Bit */
rajathr 0:34ee385f4d2d 556 TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM_MORT;
rajathr 0:34ee385f4d2d 557
rajathr 0:34ee385f4d2d 558 /* Configure the OPM Mode */
rajathr 0:34ee385f4d2d 559 TIMx->CR1 |= TIM_OPMode;
rajathr 0:34ee385f4d2d 560 }
rajathr 0:34ee385f4d2d 561
rajathr 0:34ee385f4d2d 562 /**
rajathr 0:34ee385f4d2d 563 * @brief Sets the TIMx Clock Division value.
rajathr 0:34ee385f4d2d 564 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
rajathr 0:34ee385f4d2d 565 * @param TIM_CKD: specifies the clock division value.
rajathr 0:34ee385f4d2d 566 * This parameter can be one of the following value:
rajathr 0:34ee385f4d2d 567 * @arg TIM_CKD_DIV1_MORT: TDTS = Tck_tim
rajathr 0:34ee385f4d2d 568 * @arg TIM_CKD_DIV2_MORT: TDTS = 2*Tck_tim
rajathr 0:34ee385f4d2d 569 * @arg TIM_CKD_DIV4_MORT: TDTS = 4*Tck_tim
rajathr 0:34ee385f4d2d 570 * @retval None
rajathr 0:34ee385f4d2d 571 */
rajathr 0:34ee385f4d2d 572 void TIM_SetClockDivision_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_CKD)
rajathr 0:34ee385f4d2d 573 {
rajathr 0:34ee385f4d2d 574 /* Check the parameters */
rajathr 0:34ee385f4d2d 575 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 576 assert_param(IS_TIM_CKD_DIV_MORT(TIM_CKD));
rajathr 0:34ee385f4d2d 577
rajathr 0:34ee385f4d2d 578 /* Reset the CKD Bits */
rajathr 0:34ee385f4d2d 579 TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD_MORT);
rajathr 0:34ee385f4d2d 580
rajathr 0:34ee385f4d2d 581 /* Set the CKD value */
rajathr 0:34ee385f4d2d 582 TIMx->CR1 |= TIM_CKD;
rajathr 0:34ee385f4d2d 583 }
rajathr 0:34ee385f4d2d 584
rajathr 0:34ee385f4d2d 585 /**
rajathr 0:34ee385f4d2d 586 * @brief Enables or disables the specified TIM peripheral.
rajathr 0:34ee385f4d2d 587 * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
rajathr 0:34ee385f4d2d 588 * @param NewState: new state of the TIMx peripheral.
rajathr 0:34ee385f4d2d 589 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 590 * @retval None
rajathr 0:34ee385f4d2d 591 */
rajathr 0:34ee385f4d2d 592 void TIM_Cmd_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 593 {
rajathr 0:34ee385f4d2d 594 /* Check the parameters */
rajathr 0:34ee385f4d2d 595 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 596 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 597
rajathr 0:34ee385f4d2d 598 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 599 {
rajathr 0:34ee385f4d2d 600 /* Enable the TIM Counter */
rajathr 0:34ee385f4d2d 601 TIMx->CR1 |= TIM_CR1_CEN_MORT;
rajathr 0:34ee385f4d2d 602 }
rajathr 0:34ee385f4d2d 603 else
rajathr 0:34ee385f4d2d 604 {
rajathr 0:34ee385f4d2d 605 /* Disable the TIM Counter */
rajathr 0:34ee385f4d2d 606 TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN_MORT;
rajathr 0:34ee385f4d2d 607 }
rajathr 0:34ee385f4d2d 608 }
rajathr 0:34ee385f4d2d 609 /**
rajathr 0:34ee385f4d2d 610 * @}
rajathr 0:34ee385f4d2d 611 */
rajathr 0:34ee385f4d2d 612
rajathr 0:34ee385f4d2d 613 /** @defgroup TIM_Group2 Output Compare management functions
rajathr 0:34ee385f4d2d 614 * @brief Output Compare management functions
rajathr 0:34ee385f4d2d 615 *
rajathr 0:34ee385f4d2d 616 @verbatim
rajathr 0:34ee385f4d2d 617 ===============================================================================
rajathr 0:34ee385f4d2d 618 ##### Output Compare management functions #####
rajathr 0:34ee385f4d2d 619 ===============================================================================
rajathr 0:34ee385f4d2d 620
rajathr 0:34ee385f4d2d 621
rajathr 0:34ee385f4d2d 622 ##### TIM Driver: how to use it in Output Compare Mode #####
rajathr 0:34ee385f4d2d 623 ===============================================================================
rajathr 0:34ee385f4d2d 624 [..]
rajathr 0:34ee385f4d2d 625 To use the Timer in Output Compare mode, the following steps are mandatory:
rajathr 0:34ee385f4d2d 626
rajathr 0:34ee385f4d2d 627 (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
rajathr 0:34ee385f4d2d 628 function
rajathr 0:34ee385f4d2d 629
rajathr 0:34ee385f4d2d 630 (#) Configure the TIM pins by configuring the corresponding GPIO pins
rajathr 0:34ee385f4d2d 631
rajathr 0:34ee385f4d2d 632 (#) Configure the Time base unit as described in the first part of this driver,
rajathr 0:34ee385f4d2d 633 (++) if needed, else the Timer will run with the default configuration:
rajathr 0:34ee385f4d2d 634 Autoreload value = 0xFFFF
rajathr 0:34ee385f4d2d 635 (++) Prescaler value = 0x0000
rajathr 0:34ee385f4d2d 636 (++) Counter mode = Up counting
rajathr 0:34ee385f4d2d 637 (++) Clock Division = TIM_CKD_DIV1_MORT
rajathr 0:34ee385f4d2d 638
rajathr 0:34ee385f4d2d 639 (#) Fill the TIM_OCInitStruct with the desired parameters including:
rajathr 0:34ee385f4d2d 640 (++) The TIM Output Compare mode: TIM_OCMode
rajathr 0:34ee385f4d2d 641 (++) TIM Output State: TIM_OutputState
rajathr 0:34ee385f4d2d 642 (++) TIM Pulse value: TIM_Pulse
rajathr 0:34ee385f4d2d 643 (++) TIM Output Compare Polarity : TIM_OCPolarity
rajathr 0:34ee385f4d2d 644
rajathr 0:34ee385f4d2d 645 (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired
rajathr 0:34ee385f4d2d 646 channel with the corresponding configuration
rajathr 0:34ee385f4d2d 647
rajathr 0:34ee385f4d2d 648 (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
rajathr 0:34ee385f4d2d 649
rajathr 0:34ee385f4d2d 650 -@- All other functions can be used separately to modify, if needed,
rajathr 0:34ee385f4d2d 651 a specific feature of the Timer.
rajathr 0:34ee385f4d2d 652
rajathr 0:34ee385f4d2d 653 -@- In case of PWM mode, this function is mandatory:
rajathr 0:34ee385f4d2d 654 TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_Enable_MORT);
rajathr 0:34ee385f4d2d 655
rajathr 0:34ee385f4d2d 656 -@- If the corresponding interrupt or DMA request are needed, the user should:
rajathr 0:34ee385f4d2d 657 (+@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
rajathr 0:34ee385f4d2d 658 (+@) Enable the corresponding interrupt (or DMA request) using the function
rajathr 0:34ee385f4d2d 659 TIM_ITConfig_mort(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
rajathr 0:34ee385f4d2d 660
rajathr 0:34ee385f4d2d 661 @endverbatim
rajathr 0:34ee385f4d2d 662 * @{
rajathr 0:34ee385f4d2d 663 */
rajathr 0:34ee385f4d2d 664
rajathr 0:34ee385f4d2d 665 /**
rajathr 0:34ee385f4d2d 666 * @brief Initializes the TIMx Channel1 according to the specified parameters in
rajathr 0:34ee385f4d2d 667 * the TIM_OCInitStruct.
rajathr 0:34ee385f4d2d 668 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
rajathr 0:34ee385f4d2d 669 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef_mort structure that contains
rajathr 0:34ee385f4d2d 670 * the configuration information for the specified TIM peripheral.
rajathr 0:34ee385f4d2d 671 * @retval None
rajathr 0:34ee385f4d2d 672 */
rajathr 0:34ee385f4d2d 673 void TIM_OC1Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct)
rajathr 0:34ee385f4d2d 674 {
rajathr 0:34ee385f4d2d 675 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
rajathr 0:34ee385f4d2d 676
rajathr 0:34ee385f4d2d 677 /* Check the parameters */
rajathr 0:34ee385f4d2d 678 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 679 assert_param(IS_TIM_OC_MODE_MORT(TIM_OCInitStruct->TIM_OCMode));
rajathr 0:34ee385f4d2d 680 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
rajathr 0:34ee385f4d2d 681 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
rajathr 0:34ee385f4d2d 682
rajathr 0:34ee385f4d2d 683 /* Disable the Channel 1: Reset the CC1E Bit */
rajathr 0:34ee385f4d2d 684 TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E_MORT;
rajathr 0:34ee385f4d2d 685
rajathr 0:34ee385f4d2d 686 /* Get the TIMx CCER register value */
rajathr 0:34ee385f4d2d 687 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 688 /* Get the TIMx CR2 register value */
rajathr 0:34ee385f4d2d 689 tmpcr2 = TIMx->CR2;
rajathr 0:34ee385f4d2d 690
rajathr 0:34ee385f4d2d 691 /* Get the TIMx CCMR1 register value */
rajathr 0:34ee385f4d2d 692 tmpccmrx = TIMx->CCMR1;
rajathr 0:34ee385f4d2d 693
rajathr 0:34ee385f4d2d 694 /* Reset the Output Compare Mode Bits */
rajathr 0:34ee385f4d2d 695 tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M_MORT;
rajathr 0:34ee385f4d2d 696 tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S_MORT;
rajathr 0:34ee385f4d2d 697 /* Select the Output Compare Mode */
rajathr 0:34ee385f4d2d 698 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
rajathr 0:34ee385f4d2d 699
rajathr 0:34ee385f4d2d 700 /* Reset the Output Polarity level */
rajathr 0:34ee385f4d2d 701 tmpccer &= (uint16_t)~TIM_CCER_CC1P_MORT;
rajathr 0:34ee385f4d2d 702 /* Set the Output Compare Polarity */
rajathr 0:34ee385f4d2d 703 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
rajathr 0:34ee385f4d2d 704
rajathr 0:34ee385f4d2d 705 /* Set the Output State */
rajathr 0:34ee385f4d2d 706 tmpccer |= TIM_OCInitStruct->TIM_OutputState;
rajathr 0:34ee385f4d2d 707
rajathr 0:34ee385f4d2d 708 if((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT))
rajathr 0:34ee385f4d2d 709 {
rajathr 0:34ee385f4d2d 710 assert_param(IS_TIM_OUTPUTN_STATE_MORT(TIM_OCInitStruct->TIM_OutputNState));
rajathr 0:34ee385f4d2d 711 assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCInitStruct->TIM_OCNPolarity));
rajathr 0:34ee385f4d2d 712 assert_param(IS_TIM_OCNIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCNIdleState));
rajathr 0:34ee385f4d2d 713 assert_param(IS_TIM_OCIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCIdleState));
rajathr 0:34ee385f4d2d 714
rajathr 0:34ee385f4d2d 715 /* Reset the Output N Polarity level */
rajathr 0:34ee385f4d2d 716 tmpccer &= (uint16_t)~TIM_CCER_CC1NP_MORT;
rajathr 0:34ee385f4d2d 717 /* Set the Output N Polarity */
rajathr 0:34ee385f4d2d 718 tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
rajathr 0:34ee385f4d2d 719 /* Reset the Output N State */
rajathr 0:34ee385f4d2d 720 tmpccer &= (uint16_t)~TIM_CCER_CC1NE_MORT;
rajathr 0:34ee385f4d2d 721
rajathr 0:34ee385f4d2d 722 /* Set the Output N State */
rajathr 0:34ee385f4d2d 723 tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
rajathr 0:34ee385f4d2d 724 /* Reset the Output Compare and Output Compare N IDLE State */
rajathr 0:34ee385f4d2d 725 tmpcr2 &= (uint16_t)~TIM_CR2_OIS1_MORT;
rajathr 0:34ee385f4d2d 726 tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N_MORT;
rajathr 0:34ee385f4d2d 727 /* Set the Output Idle state */
rajathr 0:34ee385f4d2d 728 tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
rajathr 0:34ee385f4d2d 729 /* Set the Output N Idle state */
rajathr 0:34ee385f4d2d 730 tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
rajathr 0:34ee385f4d2d 731 }
rajathr 0:34ee385f4d2d 732 /* Write to TIMx CR2 */
rajathr 0:34ee385f4d2d 733 TIMx->CR2 = tmpcr2;
rajathr 0:34ee385f4d2d 734
rajathr 0:34ee385f4d2d 735 /* Write to TIMx CCMR1 */
rajathr 0:34ee385f4d2d 736 TIMx->CCMR1 = tmpccmrx;
rajathr 0:34ee385f4d2d 737
rajathr 0:34ee385f4d2d 738 /* Set the Capture Compare Register value */
rajathr 0:34ee385f4d2d 739 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
rajathr 0:34ee385f4d2d 740
rajathr 0:34ee385f4d2d 741 /* Write to TIMx CCER */
rajathr 0:34ee385f4d2d 742 TIMx->CCER = tmpccer;
rajathr 0:34ee385f4d2d 743 }
rajathr 0:34ee385f4d2d 744
rajathr 0:34ee385f4d2d 745 /**
rajathr 0:34ee385f4d2d 746 * @brief Initializes the TIMx Channel2 according to the specified parameters
rajathr 0:34ee385f4d2d 747 * in the TIM_OCInitStruct.
rajathr 0:34ee385f4d2d 748 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
rajathr 0:34ee385f4d2d 749 * peripheral.
rajathr 0:34ee385f4d2d 750 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef_mort structure that contains
rajathr 0:34ee385f4d2d 751 * the configuration information for the specified TIM peripheral.
rajathr 0:34ee385f4d2d 752 * @retval None
rajathr 0:34ee385f4d2d 753 */
rajathr 0:34ee385f4d2d 754 void TIM_OC2Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct)
rajathr 0:34ee385f4d2d 755 {
rajathr 0:34ee385f4d2d 756 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
rajathr 0:34ee385f4d2d 757
rajathr 0:34ee385f4d2d 758 /* Check the parameters */
rajathr 0:34ee385f4d2d 759 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 760 assert_param(IS_TIM_OC_MODE_MORT(TIM_OCInitStruct->TIM_OCMode));
rajathr 0:34ee385f4d2d 761 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
rajathr 0:34ee385f4d2d 762 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
rajathr 0:34ee385f4d2d 763
rajathr 0:34ee385f4d2d 764 /* Disable the Channel 2: Reset the CC2E Bit */
rajathr 0:34ee385f4d2d 765 TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E_MORT;
rajathr 0:34ee385f4d2d 766
rajathr 0:34ee385f4d2d 767 /* Get the TIMx CCER register value */
rajathr 0:34ee385f4d2d 768 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 769 /* Get the TIMx CR2 register value */
rajathr 0:34ee385f4d2d 770 tmpcr2 = TIMx->CR2;
rajathr 0:34ee385f4d2d 771
rajathr 0:34ee385f4d2d 772 /* Get the TIMx CCMR1 register value */
rajathr 0:34ee385f4d2d 773 tmpccmrx = TIMx->CCMR1;
rajathr 0:34ee385f4d2d 774
rajathr 0:34ee385f4d2d 775 /* Reset the Output Compare mode and Capture/Compare selection Bits */
rajathr 0:34ee385f4d2d 776 tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M_MORT;
rajathr 0:34ee385f4d2d 777 tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S_MORT;
rajathr 0:34ee385f4d2d 778
rajathr 0:34ee385f4d2d 779 /* Select the Output Compare Mode */
rajathr 0:34ee385f4d2d 780 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
rajathr 0:34ee385f4d2d 781
rajathr 0:34ee385f4d2d 782 /* Reset the Output Polarity level */
rajathr 0:34ee385f4d2d 783 tmpccer &= (uint16_t)~TIM_CCER_CC2P_MORT;
rajathr 0:34ee385f4d2d 784 /* Set the Output Compare Polarity */
rajathr 0:34ee385f4d2d 785 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
rajathr 0:34ee385f4d2d 786
rajathr 0:34ee385f4d2d 787 /* Set the Output State */
rajathr 0:34ee385f4d2d 788 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
rajathr 0:34ee385f4d2d 789
rajathr 0:34ee385f4d2d 790 if((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT))
rajathr 0:34ee385f4d2d 791 {
rajathr 0:34ee385f4d2d 792 assert_param(IS_TIM_OUTPUTN_STATE_MORT(TIM_OCInitStruct->TIM_OutputNState));
rajathr 0:34ee385f4d2d 793 assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCInitStruct->TIM_OCNPolarity));
rajathr 0:34ee385f4d2d 794 assert_param(IS_TIM_OCNIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCNIdleState));
rajathr 0:34ee385f4d2d 795 assert_param(IS_TIM_OCIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCIdleState));
rajathr 0:34ee385f4d2d 796
rajathr 0:34ee385f4d2d 797 /* Reset the Output N Polarity level */
rajathr 0:34ee385f4d2d 798 tmpccer &= (uint16_t)~TIM_CCER_CC2NP_MORT;
rajathr 0:34ee385f4d2d 799 /* Set the Output N Polarity */
rajathr 0:34ee385f4d2d 800 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
rajathr 0:34ee385f4d2d 801 /* Reset the Output N State */
rajathr 0:34ee385f4d2d 802 tmpccer &= (uint16_t)~TIM_CCER_CC2NE_MORT;
rajathr 0:34ee385f4d2d 803
rajathr 0:34ee385f4d2d 804 /* Set the Output N State */
rajathr 0:34ee385f4d2d 805 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
rajathr 0:34ee385f4d2d 806 /* Reset the Output Compare and Output Compare N IDLE State */
rajathr 0:34ee385f4d2d 807 tmpcr2 &= (uint16_t)~TIM_CR2_OIS2_MORT;
rajathr 0:34ee385f4d2d 808 tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N_MORT;
rajathr 0:34ee385f4d2d 809 /* Set the Output Idle state */
rajathr 0:34ee385f4d2d 810 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
rajathr 0:34ee385f4d2d 811 /* Set the Output N Idle state */
rajathr 0:34ee385f4d2d 812 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
rajathr 0:34ee385f4d2d 813 }
rajathr 0:34ee385f4d2d 814 /* Write to TIMx CR2 */
rajathr 0:34ee385f4d2d 815 TIMx->CR2 = tmpcr2;
rajathr 0:34ee385f4d2d 816
rajathr 0:34ee385f4d2d 817 /* Write to TIMx CCMR1 */
rajathr 0:34ee385f4d2d 818 TIMx->CCMR1 = tmpccmrx;
rajathr 0:34ee385f4d2d 819
rajathr 0:34ee385f4d2d 820 /* Set the Capture Compare Register value */
rajathr 0:34ee385f4d2d 821 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
rajathr 0:34ee385f4d2d 822
rajathr 0:34ee385f4d2d 823 /* Write to TIMx CCER */
rajathr 0:34ee385f4d2d 824 TIMx->CCER = tmpccer;
rajathr 0:34ee385f4d2d 825 }
rajathr 0:34ee385f4d2d 826
rajathr 0:34ee385f4d2d 827 /**
rajathr 0:34ee385f4d2d 828 * @brief Initializes the TIMx Channel3 according to the specified parameters
rajathr 0:34ee385f4d2d 829 * in the TIM_OCInitStruct.
rajathr 0:34ee385f4d2d 830 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 831 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef_mort structure that contains
rajathr 0:34ee385f4d2d 832 * the configuration information for the specified TIM peripheral.
rajathr 0:34ee385f4d2d 833 * @retval None
rajathr 0:34ee385f4d2d 834 */
rajathr 0:34ee385f4d2d 835 void TIM_OC3Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct)
rajathr 0:34ee385f4d2d 836 {
rajathr 0:34ee385f4d2d 837 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
rajathr 0:34ee385f4d2d 838
rajathr 0:34ee385f4d2d 839 /* Check the parameters */
rajathr 0:34ee385f4d2d 840 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 841 assert_param(IS_TIM_OC_MODE_MORT(TIM_OCInitStruct->TIM_OCMode));
rajathr 0:34ee385f4d2d 842 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
rajathr 0:34ee385f4d2d 843 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
rajathr 0:34ee385f4d2d 844
rajathr 0:34ee385f4d2d 845 /* Disable the Channel 3: Reset the CC2E Bit */
rajathr 0:34ee385f4d2d 846 TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E_MORT;
rajathr 0:34ee385f4d2d 847
rajathr 0:34ee385f4d2d 848 /* Get the TIMx CCER register value */
rajathr 0:34ee385f4d2d 849 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 850 /* Get the TIMx CR2 register value */
rajathr 0:34ee385f4d2d 851 tmpcr2 = TIMx->CR2;
rajathr 0:34ee385f4d2d 852
rajathr 0:34ee385f4d2d 853 /* Get the TIMx CCMR2 register value */
rajathr 0:34ee385f4d2d 854 tmpccmrx = TIMx->CCMR2;
rajathr 0:34ee385f4d2d 855
rajathr 0:34ee385f4d2d 856 /* Reset the Output Compare mode and Capture/Compare selection Bits */
rajathr 0:34ee385f4d2d 857 tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M_MORT;
rajathr 0:34ee385f4d2d 858 tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S_MORT;
rajathr 0:34ee385f4d2d 859 /* Select the Output Compare Mode */
rajathr 0:34ee385f4d2d 860 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
rajathr 0:34ee385f4d2d 861
rajathr 0:34ee385f4d2d 862 /* Reset the Output Polarity level */
rajathr 0:34ee385f4d2d 863 tmpccer &= (uint16_t)~TIM_CCER_CC3P_MORT;
rajathr 0:34ee385f4d2d 864 /* Set the Output Compare Polarity */
rajathr 0:34ee385f4d2d 865 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
rajathr 0:34ee385f4d2d 866
rajathr 0:34ee385f4d2d 867 /* Set the Output State */
rajathr 0:34ee385f4d2d 868 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
rajathr 0:34ee385f4d2d 869
rajathr 0:34ee385f4d2d 870 if((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT))
rajathr 0:34ee385f4d2d 871 {
rajathr 0:34ee385f4d2d 872 assert_param(IS_TIM_OUTPUTN_STATE_MORT(TIM_OCInitStruct->TIM_OutputNState));
rajathr 0:34ee385f4d2d 873 assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCInitStruct->TIM_OCNPolarity));
rajathr 0:34ee385f4d2d 874 assert_param(IS_TIM_OCNIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCNIdleState));
rajathr 0:34ee385f4d2d 875 assert_param(IS_TIM_OCIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCIdleState));
rajathr 0:34ee385f4d2d 876
rajathr 0:34ee385f4d2d 877 /* Reset the Output N Polarity level */
rajathr 0:34ee385f4d2d 878 tmpccer &= (uint16_t)~TIM_CCER_CC3NP_MORT;
rajathr 0:34ee385f4d2d 879 /* Set the Output N Polarity */
rajathr 0:34ee385f4d2d 880 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
rajathr 0:34ee385f4d2d 881 /* Reset the Output N State */
rajathr 0:34ee385f4d2d 882 tmpccer &= (uint16_t)~TIM_CCER_CC3NE_MORT;
rajathr 0:34ee385f4d2d 883
rajathr 0:34ee385f4d2d 884 /* Set the Output N State */
rajathr 0:34ee385f4d2d 885 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
rajathr 0:34ee385f4d2d 886 /* Reset the Output Compare and Output Compare N IDLE State */
rajathr 0:34ee385f4d2d 887 tmpcr2 &= (uint16_t)~TIM_CR2_OIS3_MORT;
rajathr 0:34ee385f4d2d 888 tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N_MORT;
rajathr 0:34ee385f4d2d 889 /* Set the Output Idle state */
rajathr 0:34ee385f4d2d 890 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
rajathr 0:34ee385f4d2d 891 /* Set the Output N Idle state */
rajathr 0:34ee385f4d2d 892 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
rajathr 0:34ee385f4d2d 893 }
rajathr 0:34ee385f4d2d 894 /* Write to TIMx CR2 */
rajathr 0:34ee385f4d2d 895 TIMx->CR2 = tmpcr2;
rajathr 0:34ee385f4d2d 896
rajathr 0:34ee385f4d2d 897 /* Write to TIMx CCMR2 */
rajathr 0:34ee385f4d2d 898 TIMx->CCMR2 = tmpccmrx;
rajathr 0:34ee385f4d2d 899
rajathr 0:34ee385f4d2d 900 /* Set the Capture Compare Register value */
rajathr 0:34ee385f4d2d 901 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
rajathr 0:34ee385f4d2d 902
rajathr 0:34ee385f4d2d 903 /* Write to TIMx CCER */
rajathr 0:34ee385f4d2d 904 TIMx->CCER = tmpccer;
rajathr 0:34ee385f4d2d 905 }
rajathr 0:34ee385f4d2d 906
rajathr 0:34ee385f4d2d 907 /**
rajathr 0:34ee385f4d2d 908 * @brief Initializes the TIMx Channel4 according to the specified parameters
rajathr 0:34ee385f4d2d 909 * in the TIM_OCInitStruct.
rajathr 0:34ee385f4d2d 910 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 911 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef_mort structure that contains
rajathr 0:34ee385f4d2d 912 * the configuration information for the specified TIM peripheral.
rajathr 0:34ee385f4d2d 913 * @retval None
rajathr 0:34ee385f4d2d 914 */
rajathr 0:34ee385f4d2d 915 void TIM_OC4Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct)
rajathr 0:34ee385f4d2d 916 {
rajathr 0:34ee385f4d2d 917 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
rajathr 0:34ee385f4d2d 918
rajathr 0:34ee385f4d2d 919 /* Check the parameters */
rajathr 0:34ee385f4d2d 920 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 921 assert_param(IS_TIM_OC_MODE_MORT(TIM_OCInitStruct->TIM_OCMode));
rajathr 0:34ee385f4d2d 922 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
rajathr 0:34ee385f4d2d 923 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
rajathr 0:34ee385f4d2d 924
rajathr 0:34ee385f4d2d 925 /* Disable the Channel 4: Reset the CC4E Bit */
rajathr 0:34ee385f4d2d 926 TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E_MORT;
rajathr 0:34ee385f4d2d 927
rajathr 0:34ee385f4d2d 928 /* Get the TIMx CCER register value */
rajathr 0:34ee385f4d2d 929 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 930 /* Get the TIMx CR2 register value */
rajathr 0:34ee385f4d2d 931 tmpcr2 = TIMx->CR2;
rajathr 0:34ee385f4d2d 932
rajathr 0:34ee385f4d2d 933 /* Get the TIMx CCMR2 register value */
rajathr 0:34ee385f4d2d 934 tmpccmrx = TIMx->CCMR2;
rajathr 0:34ee385f4d2d 935
rajathr 0:34ee385f4d2d 936 /* Reset the Output Compare mode and Capture/Compare selection Bits */
rajathr 0:34ee385f4d2d 937 tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M_MORT;
rajathr 0:34ee385f4d2d 938 tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S_MORT;
rajathr 0:34ee385f4d2d 939
rajathr 0:34ee385f4d2d 940 /* Select the Output Compare Mode */
rajathr 0:34ee385f4d2d 941 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
rajathr 0:34ee385f4d2d 942
rajathr 0:34ee385f4d2d 943 /* Reset the Output Polarity level */
rajathr 0:34ee385f4d2d 944 tmpccer &= (uint16_t)~TIM_CCER_CC4P_MORT;
rajathr 0:34ee385f4d2d 945 /* Set the Output Compare Polarity */
rajathr 0:34ee385f4d2d 946 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
rajathr 0:34ee385f4d2d 947
rajathr 0:34ee385f4d2d 948 /* Set the Output State */
rajathr 0:34ee385f4d2d 949 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
rajathr 0:34ee385f4d2d 950
rajathr 0:34ee385f4d2d 951 if((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT))
rajathr 0:34ee385f4d2d 952 {
rajathr 0:34ee385f4d2d 953 assert_param(IS_TIM_OCIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCIdleState));
rajathr 0:34ee385f4d2d 954 /* Reset the Output Compare IDLE State */
rajathr 0:34ee385f4d2d 955 tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4_MORT;
rajathr 0:34ee385f4d2d 956 /* Set the Output Idle state */
rajathr 0:34ee385f4d2d 957 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
rajathr 0:34ee385f4d2d 958 }
rajathr 0:34ee385f4d2d 959 /* Write to TIMx CR2 */
rajathr 0:34ee385f4d2d 960 TIMx->CR2 = tmpcr2;
rajathr 0:34ee385f4d2d 961
rajathr 0:34ee385f4d2d 962 /* Write to TIMx CCMR2 */
rajathr 0:34ee385f4d2d 963 TIMx->CCMR2 = tmpccmrx;
rajathr 0:34ee385f4d2d 964
rajathr 0:34ee385f4d2d 965 /* Set the Capture Compare Register value */
rajathr 0:34ee385f4d2d 966 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
rajathr 0:34ee385f4d2d 967
rajathr 0:34ee385f4d2d 968 /* Write to TIMx CCER */
rajathr 0:34ee385f4d2d 969 TIMx->CCER = tmpccer;
rajathr 0:34ee385f4d2d 970 }
rajathr 0:34ee385f4d2d 971
rajathr 0:34ee385f4d2d 972 /**
rajathr 0:34ee385f4d2d 973 * @brief Fills each TIM_OCInitStruct member with its default value.
rajathr 0:34ee385f4d2d 974 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef_mort structure which will
rajathr 0:34ee385f4d2d 975 * be initialized.
rajathr 0:34ee385f4d2d 976 * @retval None
rajathr 0:34ee385f4d2d 977 */
rajathr 0:34ee385f4d2d 978 void TIM_OCStructInit_mort(TIM_OCInitTypeDef_mort* TIM_OCInitStruct)
rajathr 0:34ee385f4d2d 979 {
rajathr 0:34ee385f4d2d 980 /* Set the default configuration */
rajathr 0:34ee385f4d2d 981 TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing_MORT;
rajathr 0:34ee385f4d2d 982 TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable_MORT;
rajathr 0:34ee385f4d2d 983 TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable_MORT;
rajathr 0:34ee385f4d2d 984 TIM_OCInitStruct->TIM_Pulse = 0x00000000;
rajathr 0:34ee385f4d2d 985 TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High_MORT;
rajathr 0:34ee385f4d2d 986 TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High_MORT;
rajathr 0:34ee385f4d2d 987 TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset_MORT;
rajathr 0:34ee385f4d2d 988 TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset_MORT;
rajathr 0:34ee385f4d2d 989 }
rajathr 0:34ee385f4d2d 990
rajathr 0:34ee385f4d2d 991 /**
rajathr 0:34ee385f4d2d 992 * @brief Selects the TIM Output Compare Mode.
rajathr 0:34ee385f4d2d 993 * @note This function disables the selected channel before changing the Output
rajathr 0:34ee385f4d2d 994 * Compare Mode. If needed, user has to enable this channel using
rajathr 0:34ee385f4d2d 995 * TIM_CCxCmd_mort() and TIM_CCxNCmd_mort() functions.
rajathr 0:34ee385f4d2d 996 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
rajathr 0:34ee385f4d2d 997 * @param TIM_Channel: specifies the TIM Channel
rajathr 0:34ee385f4d2d 998 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 999 * @arg TIM_Channel_1_MORT: TIM Channel 1
rajathr 0:34ee385f4d2d 1000 * @arg TIM_Channel_2_MORT: TIM Channel 2
rajathr 0:34ee385f4d2d 1001 * @arg TIM_Channel_3_MORT: TIM Channel 3
rajathr 0:34ee385f4d2d 1002 * @arg TIM_Channel_4_MORT: TIM Channel 4
rajathr 0:34ee385f4d2d 1003 * @param TIM_OCMode: specifies the TIM Output Compare Mode.
rajathr 0:34ee385f4d2d 1004 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1005 * @arg TIM_OCMode_Timing_MORT
rajathr 0:34ee385f4d2d 1006 * @arg TIM_OCMode_Active_MORT
rajathr 0:34ee385f4d2d 1007 * @arg TIM_OCMode_Toggle
rajathr 0:34ee385f4d2d 1008 * @arg TIM_OCMode_PWM1_MORT
rajathr 0:34ee385f4d2d 1009 * @arg TIM_OCMode_PWM2_MORT
rajathr 0:34ee385f4d2d 1010 * @arg TIM_ForcedAction_Active_MORT
rajathr 0:34ee385f4d2d 1011 * @arg TIM_ForcedAction_InActive_MORT
rajathr 0:34ee385f4d2d 1012 * @retval None
rajathr 0:34ee385f4d2d 1013 */
rajathr 0:34ee385f4d2d 1014 void TIM_SelectOCxM_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
rajathr 0:34ee385f4d2d 1015 {
rajathr 0:34ee385f4d2d 1016 uint32_t tmp = 0;
rajathr 0:34ee385f4d2d 1017 uint16_t tmp1 = 0;
rajathr 0:34ee385f4d2d 1018
rajathr 0:34ee385f4d2d 1019 /* Check the parameters */
rajathr 0:34ee385f4d2d 1020 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1021 assert_param(IS_TIM_CHANNEL_MORT(TIM_Channel));
rajathr 0:34ee385f4d2d 1022 assert_param(IS_TIM_OCM_MORT(TIM_OCMode));
rajathr 0:34ee385f4d2d 1023
rajathr 0:34ee385f4d2d 1024 tmp = (uint32_t) TIMx;
rajathr 0:34ee385f4d2d 1025 tmp += CCMR_OFFSET_MORT;
rajathr 0:34ee385f4d2d 1026
rajathr 0:34ee385f4d2d 1027 tmp1 = CCER_CCE_SET_MORT << (uint16_t)TIM_Channel;
rajathr 0:34ee385f4d2d 1028
rajathr 0:34ee385f4d2d 1029 /* Disable the Channel: Reset the CCxE Bit */
rajathr 0:34ee385f4d2d 1030 TIMx->CCER &= (uint16_t) ~tmp1;
rajathr 0:34ee385f4d2d 1031
rajathr 0:34ee385f4d2d 1032 if((TIM_Channel == TIM_Channel_1_MORT) ||(TIM_Channel == TIM_Channel_3_MORT))
rajathr 0:34ee385f4d2d 1033 {
rajathr 0:34ee385f4d2d 1034 tmp += (TIM_Channel>>1);
rajathr 0:34ee385f4d2d 1035
rajathr 0:34ee385f4d2d 1036 /* Reset the OCxM bits in the CCMRx register */
rajathr 0:34ee385f4d2d 1037 *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK_MORT;
rajathr 0:34ee385f4d2d 1038
rajathr 0:34ee385f4d2d 1039 /* Configure the OCxM bits in the CCMRx register */
rajathr 0:34ee385f4d2d 1040 *(__IO uint32_t *) tmp |= TIM_OCMode;
rajathr 0:34ee385f4d2d 1041 }
rajathr 0:34ee385f4d2d 1042 else
rajathr 0:34ee385f4d2d 1043 {
rajathr 0:34ee385f4d2d 1044 tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
rajathr 0:34ee385f4d2d 1045
rajathr 0:34ee385f4d2d 1046 /* Reset the OCxM bits in the CCMRx register */
rajathr 0:34ee385f4d2d 1047 *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK_MORT;
rajathr 0:34ee385f4d2d 1048
rajathr 0:34ee385f4d2d 1049 /* Configure the OCxM bits in the CCMRx register */
rajathr 0:34ee385f4d2d 1050 *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
rajathr 0:34ee385f4d2d 1051 }
rajathr 0:34ee385f4d2d 1052 }
rajathr 0:34ee385f4d2d 1053
rajathr 0:34ee385f4d2d 1054 /**
rajathr 0:34ee385f4d2d 1055 * @brief Sets the TIMx Capture Compare1 Register value
rajathr 0:34ee385f4d2d 1056 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1057 * @param Compare1: specifies the Capture Compare1 register new value.
rajathr 0:34ee385f4d2d 1058 * @retval None
rajathr 0:34ee385f4d2d 1059 */
rajathr 0:34ee385f4d2d 1060 void TIM_SetCompare1_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare1)
rajathr 0:34ee385f4d2d 1061 {
rajathr 0:34ee385f4d2d 1062 /* Check the parameters */
rajathr 0:34ee385f4d2d 1063 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1064
rajathr 0:34ee385f4d2d 1065 /* Set the Capture Compare1 Register value */
rajathr 0:34ee385f4d2d 1066 TIMx->CCR1 = Compare1;
rajathr 0:34ee385f4d2d 1067 }
rajathr 0:34ee385f4d2d 1068
rajathr 0:34ee385f4d2d 1069 /**
rajathr 0:34ee385f4d2d 1070 * @brief Sets the TIMx Capture Compare2 Register value
rajathr 0:34ee385f4d2d 1071 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
rajathr 0:34ee385f4d2d 1072 * peripheral.
rajathr 0:34ee385f4d2d 1073 * @param Compare2: specifies the Capture Compare2 register new value.
rajathr 0:34ee385f4d2d 1074 * @retval None
rajathr 0:34ee385f4d2d 1075 */
rajathr 0:34ee385f4d2d 1076 void TIM_SetCompare2_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare2)
rajathr 0:34ee385f4d2d 1077 {
rajathr 0:34ee385f4d2d 1078 /* Check the parameters */
rajathr 0:34ee385f4d2d 1079 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1080
rajathr 0:34ee385f4d2d 1081 /* Set the Capture Compare2 Register value */
rajathr 0:34ee385f4d2d 1082 TIMx->CCR2 = Compare2;
rajathr 0:34ee385f4d2d 1083 }
rajathr 0:34ee385f4d2d 1084
rajathr 0:34ee385f4d2d 1085 /**
rajathr 0:34ee385f4d2d 1086 * @brief Sets the TIMx Capture Compare3 Register value
rajathr 0:34ee385f4d2d 1087 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1088 * @param Compare3: specifies the Capture Compare3 register new value.
rajathr 0:34ee385f4d2d 1089 * @retval None
rajathr 0:34ee385f4d2d 1090 */
rajathr 0:34ee385f4d2d 1091 void TIM_SetCompare3_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare3)
rajathr 0:34ee385f4d2d 1092 {
rajathr 0:34ee385f4d2d 1093 /* Check the parameters */
rajathr 0:34ee385f4d2d 1094 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1095
rajathr 0:34ee385f4d2d 1096 /* Set the Capture Compare3 Register value */
rajathr 0:34ee385f4d2d 1097 TIMx->CCR3 = Compare3;
rajathr 0:34ee385f4d2d 1098 }
rajathr 0:34ee385f4d2d 1099
rajathr 0:34ee385f4d2d 1100 /**
rajathr 0:34ee385f4d2d 1101 * @brief Sets the TIMx Capture Compare4 Register value
rajathr 0:34ee385f4d2d 1102 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1103 * @param Compare4: specifies the Capture Compare4 register new value.
rajathr 0:34ee385f4d2d 1104 * @retval None
rajathr 0:34ee385f4d2d 1105 */
rajathr 0:34ee385f4d2d 1106 void TIM_SetCompare4_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare4)
rajathr 0:34ee385f4d2d 1107 {
rajathr 0:34ee385f4d2d 1108 /* Check the parameters */
rajathr 0:34ee385f4d2d 1109 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1110
rajathr 0:34ee385f4d2d 1111 /* Set the Capture Compare4 Register value */
rajathr 0:34ee385f4d2d 1112 TIMx->CCR4 = Compare4;
rajathr 0:34ee385f4d2d 1113 }
rajathr 0:34ee385f4d2d 1114
rajathr 0:34ee385f4d2d 1115 /**
rajathr 0:34ee385f4d2d 1116 * @brief Forces the TIMx output 1 waveform to active or inactive level.
rajathr 0:34ee385f4d2d 1117 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1118 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
rajathr 0:34ee385f4d2d 1119 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1120 * @arg TIM_ForcedAction_Active_MORT: Force active level on OC1REF
rajathr 0:34ee385f4d2d 1121 * @arg TIM_ForcedAction_InActive_MORT: Force inactive level on OC1REF.
rajathr 0:34ee385f4d2d 1122 * @retval None
rajathr 0:34ee385f4d2d 1123 */
rajathr 0:34ee385f4d2d 1124 void TIM_ForcedOC1Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction)
rajathr 0:34ee385f4d2d 1125 {
rajathr 0:34ee385f4d2d 1126 uint16_t tmpccmr1 = 0;
rajathr 0:34ee385f4d2d 1127
rajathr 0:34ee385f4d2d 1128 /* Check the parameters */
rajathr 0:34ee385f4d2d 1129 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1130 assert_param(IS_TIM_FORCED_ACTION_MORT(TIM_ForcedAction));
rajathr 0:34ee385f4d2d 1131 tmpccmr1 = TIMx->CCMR1;
rajathr 0:34ee385f4d2d 1132
rajathr 0:34ee385f4d2d 1133 /* Reset the OC1M Bits */
rajathr 0:34ee385f4d2d 1134 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M_MORT;
rajathr 0:34ee385f4d2d 1135
rajathr 0:34ee385f4d2d 1136 /* Configure The Forced output Mode */
rajathr 0:34ee385f4d2d 1137 tmpccmr1 |= TIM_ForcedAction;
rajathr 0:34ee385f4d2d 1138
rajathr 0:34ee385f4d2d 1139 /* Write to TIMx CCMR1 register */
rajathr 0:34ee385f4d2d 1140 TIMx->CCMR1 = tmpccmr1;
rajathr 0:34ee385f4d2d 1141 }
rajathr 0:34ee385f4d2d 1142
rajathr 0:34ee385f4d2d 1143 /**
rajathr 0:34ee385f4d2d 1144 * @brief Forces the TIMx output 2 waveform to active or inactive level.
rajathr 0:34ee385f4d2d 1145 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
rajathr 0:34ee385f4d2d 1146 * peripheral.
rajathr 0:34ee385f4d2d 1147 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
rajathr 0:34ee385f4d2d 1148 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1149 * @arg TIM_ForcedAction_Active_MORT: Force active level on OC2REF
rajathr 0:34ee385f4d2d 1150 * @arg TIM_ForcedAction_InActive_MORT: Force inactive level on OC2REF.
rajathr 0:34ee385f4d2d 1151 * @retval None
rajathr 0:34ee385f4d2d 1152 */
rajathr 0:34ee385f4d2d 1153 void TIM_ForcedOC2Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction)
rajathr 0:34ee385f4d2d 1154 {
rajathr 0:34ee385f4d2d 1155 uint16_t tmpccmr1 = 0;
rajathr 0:34ee385f4d2d 1156
rajathr 0:34ee385f4d2d 1157 /* Check the parameters */
rajathr 0:34ee385f4d2d 1158 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1159 assert_param(IS_TIM_FORCED_ACTION_MORT(TIM_ForcedAction));
rajathr 0:34ee385f4d2d 1160 tmpccmr1 = TIMx->CCMR1;
rajathr 0:34ee385f4d2d 1161
rajathr 0:34ee385f4d2d 1162 /* Reset the OC2M Bits */
rajathr 0:34ee385f4d2d 1163 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M_MORT;
rajathr 0:34ee385f4d2d 1164
rajathr 0:34ee385f4d2d 1165 /* Configure The Forced output Mode */
rajathr 0:34ee385f4d2d 1166 tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
rajathr 0:34ee385f4d2d 1167
rajathr 0:34ee385f4d2d 1168 /* Write to TIMx CCMR1 register */
rajathr 0:34ee385f4d2d 1169 TIMx->CCMR1 = tmpccmr1;
rajathr 0:34ee385f4d2d 1170 }
rajathr 0:34ee385f4d2d 1171
rajathr 0:34ee385f4d2d 1172 /**
rajathr 0:34ee385f4d2d 1173 * @brief Forces the TIMx output 3 waveform to active or inactive level.
rajathr 0:34ee385f4d2d 1174 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1175 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
rajathr 0:34ee385f4d2d 1176 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1177 * @arg TIM_ForcedAction_Active_MORT: Force active level on OC3REF
rajathr 0:34ee385f4d2d 1178 * @arg TIM_ForcedAction_InActive_MORT: Force inactive level on OC3REF.
rajathr 0:34ee385f4d2d 1179 * @retval None
rajathr 0:34ee385f4d2d 1180 */
rajathr 0:34ee385f4d2d 1181 void TIM_ForcedOC3Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction)
rajathr 0:34ee385f4d2d 1182 {
rajathr 0:34ee385f4d2d 1183 uint16_t tmpccmr2 = 0;
rajathr 0:34ee385f4d2d 1184
rajathr 0:34ee385f4d2d 1185 /* Check the parameters */
rajathr 0:34ee385f4d2d 1186 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1187 assert_param(IS_TIM_FORCED_ACTION_MORT(TIM_ForcedAction));
rajathr 0:34ee385f4d2d 1188
rajathr 0:34ee385f4d2d 1189 tmpccmr2 = TIMx->CCMR2;
rajathr 0:34ee385f4d2d 1190
rajathr 0:34ee385f4d2d 1191 /* Reset the OC1M Bits */
rajathr 0:34ee385f4d2d 1192 tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M_MORT;
rajathr 0:34ee385f4d2d 1193
rajathr 0:34ee385f4d2d 1194 /* Configure The Forced output Mode */
rajathr 0:34ee385f4d2d 1195 tmpccmr2 |= TIM_ForcedAction;
rajathr 0:34ee385f4d2d 1196
rajathr 0:34ee385f4d2d 1197 /* Write to TIMx CCMR2 register */
rajathr 0:34ee385f4d2d 1198 TIMx->CCMR2 = tmpccmr2;
rajathr 0:34ee385f4d2d 1199 }
rajathr 0:34ee385f4d2d 1200
rajathr 0:34ee385f4d2d 1201 /**
rajathr 0:34ee385f4d2d 1202 * @brief Forces the TIMx output 4 waveform to active or inactive level.
rajathr 0:34ee385f4d2d 1203 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1204 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
rajathr 0:34ee385f4d2d 1205 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1206 * @arg TIM_ForcedAction_Active_MORT: Force active level on OC4REF
rajathr 0:34ee385f4d2d 1207 * @arg TIM_ForcedAction_InActive_MORT: Force inactive level on OC4REF.
rajathr 0:34ee385f4d2d 1208 * @retval None
rajathr 0:34ee385f4d2d 1209 */
rajathr 0:34ee385f4d2d 1210 void TIM_ForcedOC4Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction)
rajathr 0:34ee385f4d2d 1211 {
rajathr 0:34ee385f4d2d 1212 uint16_t tmpccmr2 = 0;
rajathr 0:34ee385f4d2d 1213
rajathr 0:34ee385f4d2d 1214 /* Check the parameters */
rajathr 0:34ee385f4d2d 1215 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1216 assert_param(IS_TIM_FORCED_ACTION_MORT(TIM_ForcedAction));
rajathr 0:34ee385f4d2d 1217 tmpccmr2 = TIMx->CCMR2;
rajathr 0:34ee385f4d2d 1218
rajathr 0:34ee385f4d2d 1219 /* Reset the OC2M Bits */
rajathr 0:34ee385f4d2d 1220 tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M_MORT;
rajathr 0:34ee385f4d2d 1221
rajathr 0:34ee385f4d2d 1222 /* Configure The Forced output Mode */
rajathr 0:34ee385f4d2d 1223 tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
rajathr 0:34ee385f4d2d 1224
rajathr 0:34ee385f4d2d 1225 /* Write to TIMx CCMR2 register */
rajathr 0:34ee385f4d2d 1226 TIMx->CCMR2 = tmpccmr2;
rajathr 0:34ee385f4d2d 1227 }
rajathr 0:34ee385f4d2d 1228
rajathr 0:34ee385f4d2d 1229 /**
rajathr 0:34ee385f4d2d 1230 * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
rajathr 0:34ee385f4d2d 1231 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1232 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
rajathr 0:34ee385f4d2d 1233 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1234 * @arg TIM_OCPreload_Enable_MORT
rajathr 0:34ee385f4d2d 1235 * @arg TIM_OCPreload_Disable_MORT
rajathr 0:34ee385f4d2d 1236 * @retval None
rajathr 0:34ee385f4d2d 1237 */
rajathr 0:34ee385f4d2d 1238 void TIM_OC1PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload)
rajathr 0:34ee385f4d2d 1239 {
rajathr 0:34ee385f4d2d 1240 uint16_t tmpccmr1 = 0;
rajathr 0:34ee385f4d2d 1241
rajathr 0:34ee385f4d2d 1242 /* Check the parameters */
rajathr 0:34ee385f4d2d 1243 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1244 assert_param(IS_TIM_OCPRELOAD_STATE_MORT(TIM_OCPreload));
rajathr 0:34ee385f4d2d 1245
rajathr 0:34ee385f4d2d 1246 tmpccmr1 = TIMx->CCMR1;
rajathr 0:34ee385f4d2d 1247
rajathr 0:34ee385f4d2d 1248 /* Reset the OC1PE Bit */
rajathr 0:34ee385f4d2d 1249 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE_MORT);
rajathr 0:34ee385f4d2d 1250
rajathr 0:34ee385f4d2d 1251 /* Enable or Disable the Output Compare Preload feature */
rajathr 0:34ee385f4d2d 1252 tmpccmr1 |= TIM_OCPreload;
rajathr 0:34ee385f4d2d 1253
rajathr 0:34ee385f4d2d 1254 /* Write to TIMx CCMR1 register */
rajathr 0:34ee385f4d2d 1255 TIMx->CCMR1 = tmpccmr1;
rajathr 0:34ee385f4d2d 1256 }
rajathr 0:34ee385f4d2d 1257
rajathr 0:34ee385f4d2d 1258 /**
rajathr 0:34ee385f4d2d 1259 * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
rajathr 0:34ee385f4d2d 1260 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
rajathr 0:34ee385f4d2d 1261 * peripheral.
rajathr 0:34ee385f4d2d 1262 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
rajathr 0:34ee385f4d2d 1263 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1264 * @arg TIM_OCPreload_Enable_MORT
rajathr 0:34ee385f4d2d 1265 * @arg TIM_OCPreload_Disable_MORT
rajathr 0:34ee385f4d2d 1266 * @retval None
rajathr 0:34ee385f4d2d 1267 */
rajathr 0:34ee385f4d2d 1268 void TIM_OC2PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload)
rajathr 0:34ee385f4d2d 1269 {
rajathr 0:34ee385f4d2d 1270 uint16_t tmpccmr1 = 0;
rajathr 0:34ee385f4d2d 1271
rajathr 0:34ee385f4d2d 1272 /* Check the parameters */
rajathr 0:34ee385f4d2d 1273 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1274 assert_param(IS_TIM_OCPRELOAD_STATE_MORT(TIM_OCPreload));
rajathr 0:34ee385f4d2d 1275
rajathr 0:34ee385f4d2d 1276 tmpccmr1 = TIMx->CCMR1;
rajathr 0:34ee385f4d2d 1277
rajathr 0:34ee385f4d2d 1278 /* Reset the OC2PE Bit */
rajathr 0:34ee385f4d2d 1279 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE_MORT);
rajathr 0:34ee385f4d2d 1280
rajathr 0:34ee385f4d2d 1281 /* Enable or Disable the Output Compare Preload feature */
rajathr 0:34ee385f4d2d 1282 tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
rajathr 0:34ee385f4d2d 1283
rajathr 0:34ee385f4d2d 1284 /* Write to TIMx CCMR1 register */
rajathr 0:34ee385f4d2d 1285 TIMx->CCMR1 = tmpccmr1;
rajathr 0:34ee385f4d2d 1286 }
rajathr 0:34ee385f4d2d 1287
rajathr 0:34ee385f4d2d 1288 /**
rajathr 0:34ee385f4d2d 1289 * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
rajathr 0:34ee385f4d2d 1290 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1291 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
rajathr 0:34ee385f4d2d 1292 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1293 * @arg TIM_OCPreload_Enable_MORT
rajathr 0:34ee385f4d2d 1294 * @arg TIM_OCPreload_Disable_MORT
rajathr 0:34ee385f4d2d 1295 * @retval None
rajathr 0:34ee385f4d2d 1296 */
rajathr 0:34ee385f4d2d 1297 void TIM_OC3PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload)
rajathr 0:34ee385f4d2d 1298 {
rajathr 0:34ee385f4d2d 1299 uint16_t tmpccmr2 = 0;
rajathr 0:34ee385f4d2d 1300
rajathr 0:34ee385f4d2d 1301 /* Check the parameters */
rajathr 0:34ee385f4d2d 1302 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1303 assert_param(IS_TIM_OCPRELOAD_STATE_MORT(TIM_OCPreload));
rajathr 0:34ee385f4d2d 1304
rajathr 0:34ee385f4d2d 1305 tmpccmr2 = TIMx->CCMR2;
rajathr 0:34ee385f4d2d 1306
rajathr 0:34ee385f4d2d 1307 /* Reset the OC3PE Bit */
rajathr 0:34ee385f4d2d 1308 tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE_MORT);
rajathr 0:34ee385f4d2d 1309
rajathr 0:34ee385f4d2d 1310 /* Enable or Disable the Output Compare Preload feature */
rajathr 0:34ee385f4d2d 1311 tmpccmr2 |= TIM_OCPreload;
rajathr 0:34ee385f4d2d 1312
rajathr 0:34ee385f4d2d 1313 /* Write to TIMx CCMR2 register */
rajathr 0:34ee385f4d2d 1314 TIMx->CCMR2 = tmpccmr2;
rajathr 0:34ee385f4d2d 1315 }
rajathr 0:34ee385f4d2d 1316
rajathr 0:34ee385f4d2d 1317 /**
rajathr 0:34ee385f4d2d 1318 * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
rajathr 0:34ee385f4d2d 1319 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1320 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
rajathr 0:34ee385f4d2d 1321 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1322 * @arg TIM_OCPreload_Enable_MORT
rajathr 0:34ee385f4d2d 1323 * @arg TIM_OCPreload_Disable_MORT
rajathr 0:34ee385f4d2d 1324 * @retval None
rajathr 0:34ee385f4d2d 1325 */
rajathr 0:34ee385f4d2d 1326 void TIM_OC4PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload)
rajathr 0:34ee385f4d2d 1327 {
rajathr 0:34ee385f4d2d 1328 uint16_t tmpccmr2 = 0;
rajathr 0:34ee385f4d2d 1329
rajathr 0:34ee385f4d2d 1330 /* Check the parameters */
rajathr 0:34ee385f4d2d 1331 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1332 assert_param(IS_TIM_OCPRELOAD_STATE_MORT(TIM_OCPreload));
rajathr 0:34ee385f4d2d 1333
rajathr 0:34ee385f4d2d 1334 tmpccmr2 = TIMx->CCMR2;
rajathr 0:34ee385f4d2d 1335
rajathr 0:34ee385f4d2d 1336 /* Reset the OC4PE Bit */
rajathr 0:34ee385f4d2d 1337 tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE_MORT);
rajathr 0:34ee385f4d2d 1338
rajathr 0:34ee385f4d2d 1339 /* Enable or Disable the Output Compare Preload feature */
rajathr 0:34ee385f4d2d 1340 tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
rajathr 0:34ee385f4d2d 1341
rajathr 0:34ee385f4d2d 1342 /* Write to TIMx CCMR2 register */
rajathr 0:34ee385f4d2d 1343 TIMx->CCMR2 = tmpccmr2;
rajathr 0:34ee385f4d2d 1344 }
rajathr 0:34ee385f4d2d 1345
rajathr 0:34ee385f4d2d 1346 /**
rajathr 0:34ee385f4d2d 1347 * @brief Configures the TIMx Output Compare 1 Fast feature.
rajathr 0:34ee385f4d2d 1348 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1349 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
rajathr 0:34ee385f4d2d 1350 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1351 * @arg TIM_OCFast_Enable_MORT: TIM output compare fast enable
rajathr 0:34ee385f4d2d 1352 * @arg TIM_OCFast_Disable: TIM output compare fast disable
rajathr 0:34ee385f4d2d 1353 * @retval None
rajathr 0:34ee385f4d2d 1354 */
rajathr 0:34ee385f4d2d 1355 void TIM_OC1FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast)
rajathr 0:34ee385f4d2d 1356 {
rajathr 0:34ee385f4d2d 1357 uint16_t tmpccmr1 = 0;
rajathr 0:34ee385f4d2d 1358
rajathr 0:34ee385f4d2d 1359 /* Check the parameters */
rajathr 0:34ee385f4d2d 1360 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1361 assert_param(IS_TIM_OCFAST_STATE_MORT(TIM_OCFast));
rajathr 0:34ee385f4d2d 1362
rajathr 0:34ee385f4d2d 1363 /* Get the TIMx CCMR1 register value */
rajathr 0:34ee385f4d2d 1364 tmpccmr1 = TIMx->CCMR1;
rajathr 0:34ee385f4d2d 1365
rajathr 0:34ee385f4d2d 1366 /* Reset the OC1FE Bit */
rajathr 0:34ee385f4d2d 1367 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE_MORT;
rajathr 0:34ee385f4d2d 1368
rajathr 0:34ee385f4d2d 1369 /* Enable or Disable the Output Compare Fast Bit */
rajathr 0:34ee385f4d2d 1370 tmpccmr1 |= TIM_OCFast;
rajathr 0:34ee385f4d2d 1371
rajathr 0:34ee385f4d2d 1372 /* Write to TIMx CCMR1 */
rajathr 0:34ee385f4d2d 1373 TIMx->CCMR1 = tmpccmr1;
rajathr 0:34ee385f4d2d 1374 }
rajathr 0:34ee385f4d2d 1375
rajathr 0:34ee385f4d2d 1376 /**
rajathr 0:34ee385f4d2d 1377 * @brief Configures the TIMx Output Compare 2 Fast feature.
rajathr 0:34ee385f4d2d 1378 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
rajathr 0:34ee385f4d2d 1379 * peripheral.
rajathr 0:34ee385f4d2d 1380 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
rajathr 0:34ee385f4d2d 1381 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1382 * @arg TIM_OCFast_Enable_MORT: TIM output compare fast enable
rajathr 0:34ee385f4d2d 1383 * @arg TIM_OCFast_Disable: TIM output compare fast disable
rajathr 0:34ee385f4d2d 1384 * @retval None
rajathr 0:34ee385f4d2d 1385 */
rajathr 0:34ee385f4d2d 1386 void TIM_OC2FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast)
rajathr 0:34ee385f4d2d 1387 {
rajathr 0:34ee385f4d2d 1388 uint16_t tmpccmr1 = 0;
rajathr 0:34ee385f4d2d 1389
rajathr 0:34ee385f4d2d 1390 /* Check the parameters */
rajathr 0:34ee385f4d2d 1391 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1392 assert_param(IS_TIM_OCFAST_STATE_MORT(TIM_OCFast));
rajathr 0:34ee385f4d2d 1393
rajathr 0:34ee385f4d2d 1394 /* Get the TIMx CCMR1 register value */
rajathr 0:34ee385f4d2d 1395 tmpccmr1 = TIMx->CCMR1;
rajathr 0:34ee385f4d2d 1396
rajathr 0:34ee385f4d2d 1397 /* Reset the OC2FE Bit */
rajathr 0:34ee385f4d2d 1398 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE_MORT);
rajathr 0:34ee385f4d2d 1399
rajathr 0:34ee385f4d2d 1400 /* Enable or Disable the Output Compare Fast Bit */
rajathr 0:34ee385f4d2d 1401 tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
rajathr 0:34ee385f4d2d 1402
rajathr 0:34ee385f4d2d 1403 /* Write to TIMx CCMR1 */
rajathr 0:34ee385f4d2d 1404 TIMx->CCMR1 = tmpccmr1;
rajathr 0:34ee385f4d2d 1405 }
rajathr 0:34ee385f4d2d 1406
rajathr 0:34ee385f4d2d 1407 /**
rajathr 0:34ee385f4d2d 1408 * @brief Configures the TIMx Output Compare 3 Fast feature.
rajathr 0:34ee385f4d2d 1409 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1410 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
rajathr 0:34ee385f4d2d 1411 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1412 * @arg TIM_OCFast_Enable_MORT: TIM output compare fast enable
rajathr 0:34ee385f4d2d 1413 * @arg TIM_OCFast_Disable: TIM output compare fast disable
rajathr 0:34ee385f4d2d 1414 * @retval None
rajathr 0:34ee385f4d2d 1415 */
rajathr 0:34ee385f4d2d 1416 void TIM_OC3FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast)
rajathr 0:34ee385f4d2d 1417 {
rajathr 0:34ee385f4d2d 1418 uint16_t tmpccmr2 = 0;
rajathr 0:34ee385f4d2d 1419
rajathr 0:34ee385f4d2d 1420 /* Check the parameters */
rajathr 0:34ee385f4d2d 1421 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1422 assert_param(IS_TIM_OCFAST_STATE_MORT(TIM_OCFast));
rajathr 0:34ee385f4d2d 1423
rajathr 0:34ee385f4d2d 1424 /* Get the TIMx CCMR2 register value */
rajathr 0:34ee385f4d2d 1425 tmpccmr2 = TIMx->CCMR2;
rajathr 0:34ee385f4d2d 1426
rajathr 0:34ee385f4d2d 1427 /* Reset the OC3FE Bit */
rajathr 0:34ee385f4d2d 1428 tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE_MORT;
rajathr 0:34ee385f4d2d 1429
rajathr 0:34ee385f4d2d 1430 /* Enable or Disable the Output Compare Fast Bit */
rajathr 0:34ee385f4d2d 1431 tmpccmr2 |= TIM_OCFast;
rajathr 0:34ee385f4d2d 1432
rajathr 0:34ee385f4d2d 1433 /* Write to TIMx CCMR2 */
rajathr 0:34ee385f4d2d 1434 TIMx->CCMR2 = tmpccmr2;
rajathr 0:34ee385f4d2d 1435 }
rajathr 0:34ee385f4d2d 1436
rajathr 0:34ee385f4d2d 1437 /**
rajathr 0:34ee385f4d2d 1438 * @brief Configures the TIMx Output Compare 4 Fast feature.
rajathr 0:34ee385f4d2d 1439 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1440 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
rajathr 0:34ee385f4d2d 1441 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1442 * @arg TIM_OCFast_Enable_MORT: TIM output compare fast enable
rajathr 0:34ee385f4d2d 1443 * @arg TIM_OCFast_Disable: TIM output compare fast disable
rajathr 0:34ee385f4d2d 1444 * @retval None
rajathr 0:34ee385f4d2d 1445 */
rajathr 0:34ee385f4d2d 1446 void TIM_OC4FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast)
rajathr 0:34ee385f4d2d 1447 {
rajathr 0:34ee385f4d2d 1448 uint16_t tmpccmr2 = 0;
rajathr 0:34ee385f4d2d 1449
rajathr 0:34ee385f4d2d 1450 /* Check the parameters */
rajathr 0:34ee385f4d2d 1451 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1452 assert_param(IS_TIM_OCFAST_STATE_MORT(TIM_OCFast));
rajathr 0:34ee385f4d2d 1453
rajathr 0:34ee385f4d2d 1454 /* Get the TIMx CCMR2 register value */
rajathr 0:34ee385f4d2d 1455 tmpccmr2 = TIMx->CCMR2;
rajathr 0:34ee385f4d2d 1456
rajathr 0:34ee385f4d2d 1457 /* Reset the OC4FE Bit */
rajathr 0:34ee385f4d2d 1458 tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE_MORT);
rajathr 0:34ee385f4d2d 1459
rajathr 0:34ee385f4d2d 1460 /* Enable or Disable the Output Compare Fast Bit */
rajathr 0:34ee385f4d2d 1461 tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
rajathr 0:34ee385f4d2d 1462
rajathr 0:34ee385f4d2d 1463 /* Write to TIMx CCMR2 */
rajathr 0:34ee385f4d2d 1464 TIMx->CCMR2 = tmpccmr2;
rajathr 0:34ee385f4d2d 1465 }
rajathr 0:34ee385f4d2d 1466
rajathr 0:34ee385f4d2d 1467 /**
rajathr 0:34ee385f4d2d 1468 * @brief Clears or safeguards the OCREF1 signal on an external event
rajathr 0:34ee385f4d2d 1469 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1470 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
rajathr 0:34ee385f4d2d 1471 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1472 * @arg TIM_OCClear_Enable_MORT: TIM Output clear enable
rajathr 0:34ee385f4d2d 1473 * @arg TIM_OCClear_Disable_MORT: TIM Output clear disable
rajathr 0:34ee385f4d2d 1474 * @retval None
rajathr 0:34ee385f4d2d 1475 */
rajathr 0:34ee385f4d2d 1476 void TIM_ClearOC1Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear)
rajathr 0:34ee385f4d2d 1477 {
rajathr 0:34ee385f4d2d 1478 uint16_t tmpccmr1 = 0;
rajathr 0:34ee385f4d2d 1479
rajathr 0:34ee385f4d2d 1480 /* Check the parameters */
rajathr 0:34ee385f4d2d 1481 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1482 assert_param(IS_TIM_OCCLEAR_STATE_MORT(TIM_OCClear));
rajathr 0:34ee385f4d2d 1483
rajathr 0:34ee385f4d2d 1484 tmpccmr1 = TIMx->CCMR1;
rajathr 0:34ee385f4d2d 1485
rajathr 0:34ee385f4d2d 1486 /* Reset the OC1CE Bit */
rajathr 0:34ee385f4d2d 1487 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE_MORT;
rajathr 0:34ee385f4d2d 1488
rajathr 0:34ee385f4d2d 1489 /* Enable or Disable the Output Compare Clear Bit */
rajathr 0:34ee385f4d2d 1490 tmpccmr1 |= TIM_OCClear;
rajathr 0:34ee385f4d2d 1491
rajathr 0:34ee385f4d2d 1492 /* Write to TIMx CCMR1 register */
rajathr 0:34ee385f4d2d 1493 TIMx->CCMR1 = tmpccmr1;
rajathr 0:34ee385f4d2d 1494 }
rajathr 0:34ee385f4d2d 1495
rajathr 0:34ee385f4d2d 1496 /**
rajathr 0:34ee385f4d2d 1497 * @brief Clears or safeguards the OCREF2 signal on an external event
rajathr 0:34ee385f4d2d 1498 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
rajathr 0:34ee385f4d2d 1499 * peripheral.
rajathr 0:34ee385f4d2d 1500 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
rajathr 0:34ee385f4d2d 1501 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1502 * @arg TIM_OCClear_Enable_MORT: TIM Output clear enable
rajathr 0:34ee385f4d2d 1503 * @arg TIM_OCClear_Disable_MORT: TIM Output clear disable
rajathr 0:34ee385f4d2d 1504 * @retval None
rajathr 0:34ee385f4d2d 1505 */
rajathr 0:34ee385f4d2d 1506 void TIM_ClearOC2Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear)
rajathr 0:34ee385f4d2d 1507 {
rajathr 0:34ee385f4d2d 1508 uint16_t tmpccmr1 = 0;
rajathr 0:34ee385f4d2d 1509
rajathr 0:34ee385f4d2d 1510 /* Check the parameters */
rajathr 0:34ee385f4d2d 1511 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1512 assert_param(IS_TIM_OCCLEAR_STATE_MORT(TIM_OCClear));
rajathr 0:34ee385f4d2d 1513
rajathr 0:34ee385f4d2d 1514 tmpccmr1 = TIMx->CCMR1;
rajathr 0:34ee385f4d2d 1515
rajathr 0:34ee385f4d2d 1516 /* Reset the OC2CE Bit */
rajathr 0:34ee385f4d2d 1517 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE_MORT;
rajathr 0:34ee385f4d2d 1518
rajathr 0:34ee385f4d2d 1519 /* Enable or Disable the Output Compare Clear Bit */
rajathr 0:34ee385f4d2d 1520 tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
rajathr 0:34ee385f4d2d 1521
rajathr 0:34ee385f4d2d 1522 /* Write to TIMx CCMR1 register */
rajathr 0:34ee385f4d2d 1523 TIMx->CCMR1 = tmpccmr1;
rajathr 0:34ee385f4d2d 1524 }
rajathr 0:34ee385f4d2d 1525
rajathr 0:34ee385f4d2d 1526 /**
rajathr 0:34ee385f4d2d 1527 * @brief Clears or safeguards the OCREF3 signal on an external event
rajathr 0:34ee385f4d2d 1528 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1529 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
rajathr 0:34ee385f4d2d 1530 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1531 * @arg TIM_OCClear_Enable_MORT: TIM Output clear enable
rajathr 0:34ee385f4d2d 1532 * @arg TIM_OCClear_Disable_MORT: TIM Output clear disable
rajathr 0:34ee385f4d2d 1533 * @retval None
rajathr 0:34ee385f4d2d 1534 */
rajathr 0:34ee385f4d2d 1535 void TIM_ClearOC3Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear)
rajathr 0:34ee385f4d2d 1536 {
rajathr 0:34ee385f4d2d 1537 uint16_t tmpccmr2 = 0;
rajathr 0:34ee385f4d2d 1538
rajathr 0:34ee385f4d2d 1539 /* Check the parameters */
rajathr 0:34ee385f4d2d 1540 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1541 assert_param(IS_TIM_OCCLEAR_STATE_MORT(TIM_OCClear));
rajathr 0:34ee385f4d2d 1542
rajathr 0:34ee385f4d2d 1543 tmpccmr2 = TIMx->CCMR2;
rajathr 0:34ee385f4d2d 1544
rajathr 0:34ee385f4d2d 1545 /* Reset the OC3CE Bit */
rajathr 0:34ee385f4d2d 1546 tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE_MORT;
rajathr 0:34ee385f4d2d 1547
rajathr 0:34ee385f4d2d 1548 /* Enable or Disable the Output Compare Clear Bit */
rajathr 0:34ee385f4d2d 1549 tmpccmr2 |= TIM_OCClear;
rajathr 0:34ee385f4d2d 1550
rajathr 0:34ee385f4d2d 1551 /* Write to TIMx CCMR2 register */
rajathr 0:34ee385f4d2d 1552 TIMx->CCMR2 = tmpccmr2;
rajathr 0:34ee385f4d2d 1553 }
rajathr 0:34ee385f4d2d 1554
rajathr 0:34ee385f4d2d 1555 /**
rajathr 0:34ee385f4d2d 1556 * @brief Clears or safeguards the OCREF4 signal on an external event
rajathr 0:34ee385f4d2d 1557 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1558 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
rajathr 0:34ee385f4d2d 1559 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1560 * @arg TIM_OCClear_Enable_MORT: TIM Output clear enable
rajathr 0:34ee385f4d2d 1561 * @arg TIM_OCClear_Disable_MORT: TIM Output clear disable
rajathr 0:34ee385f4d2d 1562 * @retval None
rajathr 0:34ee385f4d2d 1563 */
rajathr 0:34ee385f4d2d 1564 void TIM_ClearOC4Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear)
rajathr 0:34ee385f4d2d 1565 {
rajathr 0:34ee385f4d2d 1566 uint16_t tmpccmr2 = 0;
rajathr 0:34ee385f4d2d 1567
rajathr 0:34ee385f4d2d 1568 /* Check the parameters */
rajathr 0:34ee385f4d2d 1569 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1570 assert_param(IS_TIM_OCCLEAR_STATE_MORT(TIM_OCClear));
rajathr 0:34ee385f4d2d 1571
rajathr 0:34ee385f4d2d 1572 tmpccmr2 = TIMx->CCMR2;
rajathr 0:34ee385f4d2d 1573
rajathr 0:34ee385f4d2d 1574 /* Reset the OC4CE Bit */
rajathr 0:34ee385f4d2d 1575 tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE_MORT;
rajathr 0:34ee385f4d2d 1576
rajathr 0:34ee385f4d2d 1577 /* Enable or Disable the Output Compare Clear Bit */
rajathr 0:34ee385f4d2d 1578 tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
rajathr 0:34ee385f4d2d 1579
rajathr 0:34ee385f4d2d 1580 /* Write to TIMx CCMR2 register */
rajathr 0:34ee385f4d2d 1581 TIMx->CCMR2 = tmpccmr2;
rajathr 0:34ee385f4d2d 1582 }
rajathr 0:34ee385f4d2d 1583
rajathr 0:34ee385f4d2d 1584 /**
rajathr 0:34ee385f4d2d 1585 * @brief Configures the TIMx channel 1 polarity.
rajathr 0:34ee385f4d2d 1586 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1587 * @param TIM_OCPolarity: specifies the OC1 Polarity
rajathr 0:34ee385f4d2d 1588 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1589 * @arg TIM_OCPolarity_High_MORT: Output Compare active high
rajathr 0:34ee385f4d2d 1590 * @arg TIM_OCPolarity_Low_MORT: Output Compare active low
rajathr 0:34ee385f4d2d 1591 * @retval None
rajathr 0:34ee385f4d2d 1592 */
rajathr 0:34ee385f4d2d 1593 void TIM_OC1PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity)
rajathr 0:34ee385f4d2d 1594 {
rajathr 0:34ee385f4d2d 1595 uint16_t tmpccer = 0;
rajathr 0:34ee385f4d2d 1596
rajathr 0:34ee385f4d2d 1597 /* Check the parameters */
rajathr 0:34ee385f4d2d 1598 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1599 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
rajathr 0:34ee385f4d2d 1600
rajathr 0:34ee385f4d2d 1601 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 1602
rajathr 0:34ee385f4d2d 1603 /* Set or Reset the CC1P Bit */
rajathr 0:34ee385f4d2d 1604 tmpccer &= (uint16_t)(~TIM_CCER_CC1P_MORT);
rajathr 0:34ee385f4d2d 1605 tmpccer |= TIM_OCPolarity;
rajathr 0:34ee385f4d2d 1606
rajathr 0:34ee385f4d2d 1607 /* Write to TIMx CCER register */
rajathr 0:34ee385f4d2d 1608 TIMx->CCER = tmpccer;
rajathr 0:34ee385f4d2d 1609 }
rajathr 0:34ee385f4d2d 1610
rajathr 0:34ee385f4d2d 1611 /**
rajathr 0:34ee385f4d2d 1612 * @brief Configures the TIMx Channel 1N polarity.
rajathr 0:34ee385f4d2d 1613 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1614 * @param TIM_OCNPolarity: specifies the OC1N Polarity
rajathr 0:34ee385f4d2d 1615 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1616 * @arg TIM_OCNPolarity_High_MORT: Output Compare active high
rajathr 0:34ee385f4d2d 1617 * @arg TIM_OCNPolarity_Low_MORT: Output Compare active low
rajathr 0:34ee385f4d2d 1618 * @retval None
rajathr 0:34ee385f4d2d 1619 */
rajathr 0:34ee385f4d2d 1620 void TIM_OC1NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity)
rajathr 0:34ee385f4d2d 1621 {
rajathr 0:34ee385f4d2d 1622 uint16_t tmpccer = 0;
rajathr 0:34ee385f4d2d 1623 /* Check the parameters */
rajathr 0:34ee385f4d2d 1624 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1625 assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCNPolarity));
rajathr 0:34ee385f4d2d 1626
rajathr 0:34ee385f4d2d 1627 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 1628
rajathr 0:34ee385f4d2d 1629 /* Set or Reset the CC1NP Bit */
rajathr 0:34ee385f4d2d 1630 tmpccer &= (uint16_t)~TIM_CCER_CC1NP_MORT;
rajathr 0:34ee385f4d2d 1631 tmpccer |= TIM_OCNPolarity;
rajathr 0:34ee385f4d2d 1632
rajathr 0:34ee385f4d2d 1633 /* Write to TIMx CCER register */
rajathr 0:34ee385f4d2d 1634 TIMx->CCER = tmpccer;
rajathr 0:34ee385f4d2d 1635 }
rajathr 0:34ee385f4d2d 1636
rajathr 0:34ee385f4d2d 1637 /**
rajathr 0:34ee385f4d2d 1638 * @brief Configures the TIMx channel 2 polarity.
rajathr 0:34ee385f4d2d 1639 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
rajathr 0:34ee385f4d2d 1640 * peripheral.
rajathr 0:34ee385f4d2d 1641 * @param TIM_OCPolarity: specifies the OC2 Polarity
rajathr 0:34ee385f4d2d 1642 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1643 * @arg TIM_OCPolarity_High_MORT: Output Compare active high
rajathr 0:34ee385f4d2d 1644 * @arg TIM_OCPolarity_Low_MORT: Output Compare active low
rajathr 0:34ee385f4d2d 1645 * @retval None
rajathr 0:34ee385f4d2d 1646 */
rajathr 0:34ee385f4d2d 1647 void TIM_OC2PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity)
rajathr 0:34ee385f4d2d 1648 {
rajathr 0:34ee385f4d2d 1649 uint16_t tmpccer = 0;
rajathr 0:34ee385f4d2d 1650
rajathr 0:34ee385f4d2d 1651 /* Check the parameters */
rajathr 0:34ee385f4d2d 1652 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1653 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
rajathr 0:34ee385f4d2d 1654
rajathr 0:34ee385f4d2d 1655 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 1656
rajathr 0:34ee385f4d2d 1657 /* Set or Reset the CC2P Bit */
rajathr 0:34ee385f4d2d 1658 tmpccer &= (uint16_t)(~TIM_CCER_CC2P_MORT);
rajathr 0:34ee385f4d2d 1659 tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
rajathr 0:34ee385f4d2d 1660
rajathr 0:34ee385f4d2d 1661 /* Write to TIMx CCER register */
rajathr 0:34ee385f4d2d 1662 TIMx->CCER = tmpccer;
rajathr 0:34ee385f4d2d 1663 }
rajathr 0:34ee385f4d2d 1664
rajathr 0:34ee385f4d2d 1665 /**
rajathr 0:34ee385f4d2d 1666 * @brief Configures the TIMx Channel 2N polarity.
rajathr 0:34ee385f4d2d 1667 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1668 * @param TIM_OCNPolarity: specifies the OC2N Polarity
rajathr 0:34ee385f4d2d 1669 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1670 * @arg TIM_OCNPolarity_High_MORT: Output Compare active high
rajathr 0:34ee385f4d2d 1671 * @arg TIM_OCNPolarity_Low_MORT: Output Compare active low
rajathr 0:34ee385f4d2d 1672 * @retval None
rajathr 0:34ee385f4d2d 1673 */
rajathr 0:34ee385f4d2d 1674 void TIM_OC2NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity)
rajathr 0:34ee385f4d2d 1675 {
rajathr 0:34ee385f4d2d 1676 uint16_t tmpccer = 0;
rajathr 0:34ee385f4d2d 1677
rajathr 0:34ee385f4d2d 1678 /* Check the parameters */
rajathr 0:34ee385f4d2d 1679 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1680 assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCNPolarity));
rajathr 0:34ee385f4d2d 1681
rajathr 0:34ee385f4d2d 1682 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 1683
rajathr 0:34ee385f4d2d 1684 /* Set or Reset the CC2NP Bit */
rajathr 0:34ee385f4d2d 1685 tmpccer &= (uint16_t)~TIM_CCER_CC2NP_MORT;
rajathr 0:34ee385f4d2d 1686 tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
rajathr 0:34ee385f4d2d 1687
rajathr 0:34ee385f4d2d 1688 /* Write to TIMx CCER register */
rajathr 0:34ee385f4d2d 1689 TIMx->CCER = tmpccer;
rajathr 0:34ee385f4d2d 1690 }
rajathr 0:34ee385f4d2d 1691
rajathr 0:34ee385f4d2d 1692 /**
rajathr 0:34ee385f4d2d 1693 * @brief Configures the TIMx channel 3 polarity.
rajathr 0:34ee385f4d2d 1694 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1695 * @param TIM_OCPolarity: specifies the OC3 Polarity
rajathr 0:34ee385f4d2d 1696 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1697 * @arg TIM_OCPolarity_High_MORT: Output Compare active high
rajathr 0:34ee385f4d2d 1698 * @arg TIM_OCPolarity_Low_MORT: Output Compare active low
rajathr 0:34ee385f4d2d 1699 * @retval None
rajathr 0:34ee385f4d2d 1700 */
rajathr 0:34ee385f4d2d 1701 void TIM_OC3PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity)
rajathr 0:34ee385f4d2d 1702 {
rajathr 0:34ee385f4d2d 1703 uint16_t tmpccer = 0;
rajathr 0:34ee385f4d2d 1704
rajathr 0:34ee385f4d2d 1705 /* Check the parameters */
rajathr 0:34ee385f4d2d 1706 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1707 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
rajathr 0:34ee385f4d2d 1708
rajathr 0:34ee385f4d2d 1709 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 1710
rajathr 0:34ee385f4d2d 1711 /* Set or Reset the CC3P Bit */
rajathr 0:34ee385f4d2d 1712 tmpccer &= (uint16_t)~TIM_CCER_CC3P_MORT;
rajathr 0:34ee385f4d2d 1713 tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
rajathr 0:34ee385f4d2d 1714
rajathr 0:34ee385f4d2d 1715 /* Write to TIMx CCER register */
rajathr 0:34ee385f4d2d 1716 TIMx->CCER = tmpccer;
rajathr 0:34ee385f4d2d 1717 }
rajathr 0:34ee385f4d2d 1718
rajathr 0:34ee385f4d2d 1719 /**
rajathr 0:34ee385f4d2d 1720 * @brief Configures the TIMx Channel 3N polarity.
rajathr 0:34ee385f4d2d 1721 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1722 * @param TIM_OCNPolarity: specifies the OC3N Polarity
rajathr 0:34ee385f4d2d 1723 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1724 * @arg TIM_OCNPolarity_High_MORT: Output Compare active high
rajathr 0:34ee385f4d2d 1725 * @arg TIM_OCNPolarity_Low_MORT: Output Compare active low
rajathr 0:34ee385f4d2d 1726 * @retval None
rajathr 0:34ee385f4d2d 1727 */
rajathr 0:34ee385f4d2d 1728 void TIM_OC3NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity)
rajathr 0:34ee385f4d2d 1729 {
rajathr 0:34ee385f4d2d 1730 uint16_t tmpccer = 0;
rajathr 0:34ee385f4d2d 1731
rajathr 0:34ee385f4d2d 1732 /* Check the parameters */
rajathr 0:34ee385f4d2d 1733 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1734 assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCNPolarity));
rajathr 0:34ee385f4d2d 1735
rajathr 0:34ee385f4d2d 1736 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 1737
rajathr 0:34ee385f4d2d 1738 /* Set or Reset the CC3NP Bit */
rajathr 0:34ee385f4d2d 1739 tmpccer &= (uint16_t)~TIM_CCER_CC3NP_MORT;
rajathr 0:34ee385f4d2d 1740 tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
rajathr 0:34ee385f4d2d 1741
rajathr 0:34ee385f4d2d 1742 /* Write to TIMx CCER register */
rajathr 0:34ee385f4d2d 1743 TIMx->CCER = tmpccer;
rajathr 0:34ee385f4d2d 1744 }
rajathr 0:34ee385f4d2d 1745
rajathr 0:34ee385f4d2d 1746 /**
rajathr 0:34ee385f4d2d 1747 * @brief Configures the TIMx channel 4 polarity.
rajathr 0:34ee385f4d2d 1748 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1749 * @param TIM_OCPolarity: specifies the OC4 Polarity
rajathr 0:34ee385f4d2d 1750 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1751 * @arg TIM_OCPolarity_High_MORT: Output Compare active high
rajathr 0:34ee385f4d2d 1752 * @arg TIM_OCPolarity_Low_MORT: Output Compare active low
rajathr 0:34ee385f4d2d 1753 * @retval None
rajathr 0:34ee385f4d2d 1754 */
rajathr 0:34ee385f4d2d 1755 void TIM_OC4PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity)
rajathr 0:34ee385f4d2d 1756 {
rajathr 0:34ee385f4d2d 1757 uint16_t tmpccer = 0;
rajathr 0:34ee385f4d2d 1758
rajathr 0:34ee385f4d2d 1759 /* Check the parameters */
rajathr 0:34ee385f4d2d 1760 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1761 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
rajathr 0:34ee385f4d2d 1762
rajathr 0:34ee385f4d2d 1763 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 1764
rajathr 0:34ee385f4d2d 1765 /* Set or Reset the CC4P Bit */
rajathr 0:34ee385f4d2d 1766 tmpccer &= (uint16_t)~TIM_CCER_CC4P_MORT;
rajathr 0:34ee385f4d2d 1767 tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
rajathr 0:34ee385f4d2d 1768
rajathr 0:34ee385f4d2d 1769 /* Write to TIMx CCER register */
rajathr 0:34ee385f4d2d 1770 TIMx->CCER = tmpccer;
rajathr 0:34ee385f4d2d 1771 }
rajathr 0:34ee385f4d2d 1772
rajathr 0:34ee385f4d2d 1773 /**
rajathr 0:34ee385f4d2d 1774 * @brief Enables or disables the TIM Capture Compare Channel x.
rajathr 0:34ee385f4d2d 1775 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1776 * @param TIM_Channel: specifies the TIM Channel
rajathr 0:34ee385f4d2d 1777 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1778 * @arg TIM_Channel_1_MORT: TIM Channel 1
rajathr 0:34ee385f4d2d 1779 * @arg TIM_Channel_2_MORT: TIM Channel 2
rajathr 0:34ee385f4d2d 1780 * @arg TIM_Channel_3_MORT: TIM Channel 3
rajathr 0:34ee385f4d2d 1781 * @arg TIM_Channel_4_MORT: TIM Channel 4
rajathr 0:34ee385f4d2d 1782 * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
rajathr 0:34ee385f4d2d 1783 * This parameter can be: TIM_CCx_Enable_MORT or TIM_CCx_Disable_MORT.
rajathr 0:34ee385f4d2d 1784 * @retval None
rajathr 0:34ee385f4d2d 1785 */
rajathr 0:34ee385f4d2d 1786 void TIM_CCxCmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
rajathr 0:34ee385f4d2d 1787 {
rajathr 0:34ee385f4d2d 1788 uint16_t tmp = 0;
rajathr 0:34ee385f4d2d 1789
rajathr 0:34ee385f4d2d 1790 /* Check the parameters */
rajathr 0:34ee385f4d2d 1791 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1792 assert_param(IS_TIM_CHANNEL_MORT(TIM_Channel));
rajathr 0:34ee385f4d2d 1793 assert_param(IS_TIM_CCX_MORT(TIM_CCx));
rajathr 0:34ee385f4d2d 1794
rajathr 0:34ee385f4d2d 1795 tmp = CCER_CCE_SET_MORT << TIM_Channel;
rajathr 0:34ee385f4d2d 1796
rajathr 0:34ee385f4d2d 1797 /* Reset the CCxE Bit */
rajathr 0:34ee385f4d2d 1798 TIMx->CCER &= (uint16_t)~ tmp;
rajathr 0:34ee385f4d2d 1799
rajathr 0:34ee385f4d2d 1800 /* Set or reset the CCxE Bit */
rajathr 0:34ee385f4d2d 1801 TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
rajathr 0:34ee385f4d2d 1802 }
rajathr 0:34ee385f4d2d 1803
rajathr 0:34ee385f4d2d 1804 /**
rajathr 0:34ee385f4d2d 1805 * @brief Enables or disables the TIM Capture Compare Channel xN.
rajathr 0:34ee385f4d2d 1806 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1807 * @param TIM_Channel: specifies the TIM Channel
rajathr 0:34ee385f4d2d 1808 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1809 * @arg TIM_Channel_1_MORT: TIM Channel 1
rajathr 0:34ee385f4d2d 1810 * @arg TIM_Channel_2_MORT: TIM Channel 2
rajathr 0:34ee385f4d2d 1811 * @arg TIM_Channel_3_MORT: TIM Channel 3
rajathr 0:34ee385f4d2d 1812 * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
rajathr 0:34ee385f4d2d 1813 * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
rajathr 0:34ee385f4d2d 1814 * @retval None
rajathr 0:34ee385f4d2d 1815 */
rajathr 0:34ee385f4d2d 1816 void TIM_CCxNCmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
rajathr 0:34ee385f4d2d 1817 {
rajathr 0:34ee385f4d2d 1818 uint16_t tmp = 0;
rajathr 0:34ee385f4d2d 1819
rajathr 0:34ee385f4d2d 1820 /* Check the parameters */
rajathr 0:34ee385f4d2d 1821 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1822 assert_param(IS_TIM_COMPLEMENTARY_CHANNEL_MORT(TIM_Channel));
rajathr 0:34ee385f4d2d 1823 assert_param(IS_TIM_CCXN_MORT(TIM_CCxN));
rajathr 0:34ee385f4d2d 1824
rajathr 0:34ee385f4d2d 1825 tmp = CCER_CCNE_SET_MORT << TIM_Channel;
rajathr 0:34ee385f4d2d 1826
rajathr 0:34ee385f4d2d 1827 /* Reset the CCxNE Bit */
rajathr 0:34ee385f4d2d 1828 TIMx->CCER &= (uint16_t) ~tmp;
rajathr 0:34ee385f4d2d 1829
rajathr 0:34ee385f4d2d 1830 /* Set or reset the CCxNE Bit */
rajathr 0:34ee385f4d2d 1831 TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
rajathr 0:34ee385f4d2d 1832 }
rajathr 0:34ee385f4d2d 1833 /**
rajathr 0:34ee385f4d2d 1834 * @}
rajathr 0:34ee385f4d2d 1835 */
rajathr 0:34ee385f4d2d 1836
rajathr 0:34ee385f4d2d 1837 /** @defgroup TIM_Group3 Input Capture management functions
rajathr 0:34ee385f4d2d 1838 * @brief Input Capture management functions
rajathr 0:34ee385f4d2d 1839 *
rajathr 0:34ee385f4d2d 1840 @verbatim
rajathr 0:34ee385f4d2d 1841 ===============================================================================
rajathr 0:34ee385f4d2d 1842 ##### Input Capture management functions #####
rajathr 0:34ee385f4d2d 1843 ===============================================================================
rajathr 0:34ee385f4d2d 1844
rajathr 0:34ee385f4d2d 1845 ##### TIM Driver: how to use it in Input Capture Mode #####
rajathr 0:34ee385f4d2d 1846 ===============================================================================
rajathr 0:34ee385f4d2d 1847 [..]
rajathr 0:34ee385f4d2d 1848 To use the Timer in Input Capture mode, the following steps are mandatory:
rajathr 0:34ee385f4d2d 1849
rajathr 0:34ee385f4d2d 1850 (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
rajathr 0:34ee385f4d2d 1851 function
rajathr 0:34ee385f4d2d 1852
rajathr 0:34ee385f4d2d 1853 (#) Configure the TIM pins by configuring the corresponding GPIO pins
rajathr 0:34ee385f4d2d 1854
rajathr 0:34ee385f4d2d 1855 (#) Configure the Time base unit as described in the first part of this driver,
rajathr 0:34ee385f4d2d 1856 if needed, else the Timer will run with the default configuration:
rajathr 0:34ee385f4d2d 1857 (++) Autoreload value = 0xFFFF
rajathr 0:34ee385f4d2d 1858 (++) Prescaler value = 0x0000
rajathr 0:34ee385f4d2d 1859 (++) Counter mode = Up counting
rajathr 0:34ee385f4d2d 1860 (++) Clock Division = TIM_CKD_DIV1_MORT
rajathr 0:34ee385f4d2d 1861
rajathr 0:34ee385f4d2d 1862 (#) Fill the TIM_ICInitStruct with the desired parameters including:
rajathr 0:34ee385f4d2d 1863 (++) TIM Channel: TIM_Channel
rajathr 0:34ee385f4d2d 1864 (++) TIM Input Capture polarity: TIM_ICPolarity
rajathr 0:34ee385f4d2d 1865 (++) TIM Input Capture selection: TIM_ICSelection
rajathr 0:34ee385f4d2d 1866 (++) TIM Input Capture Prescaler: TIM_ICPrescaler
rajathr 0:34ee385f4d2d 1867 (++) TIM Input Capture filter value: TIM_ICFilter
rajathr 0:34ee385f4d2d 1868
rajathr 0:34ee385f4d2d 1869 (#) Call TIM_ICInit_mort(TIMx, &TIM_ICInitStruct) to configure the desired channel
rajathr 0:34ee385f4d2d 1870 with the corresponding configuration and to measure only frequency
rajathr 0:34ee385f4d2d 1871 or duty cycle of the input signal, or, Call TIM_PWMIConfig_mort(TIMx, &TIM_ICInitStruct)
rajathr 0:34ee385f4d2d 1872 to configure the desired channels with the corresponding configuration
rajathr 0:34ee385f4d2d 1873 and to measure the frequency and the duty cycle of the input signal
rajathr 0:34ee385f4d2d 1874
rajathr 0:34ee385f4d2d 1875 (#) Enable the NVIC or the DMA to read the measured frequency.
rajathr 0:34ee385f4d2d 1876
rajathr 0:34ee385f4d2d 1877 (#) Enable the corresponding interrupt (or DMA request) to read the Captured
rajathr 0:34ee385f4d2d 1878 value, using the function TIM_ITConfig_mort(TIMx, TIM_IT_CCx)
rajathr 0:34ee385f4d2d 1879 (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
rajathr 0:34ee385f4d2d 1880
rajathr 0:34ee385f4d2d 1881 (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
rajathr 0:34ee385f4d2d 1882
rajathr 0:34ee385f4d2d 1883 (#) Use TIM_GetCapturex(TIMx); to read the captured value.
rajathr 0:34ee385f4d2d 1884
rajathr 0:34ee385f4d2d 1885 -@- All other functions can be used separately to modify, if needed,
rajathr 0:34ee385f4d2d 1886 a specific feature of the Timer.
rajathr 0:34ee385f4d2d 1887
rajathr 0:34ee385f4d2d 1888 @endverbatim
rajathr 0:34ee385f4d2d 1889 * @{
rajathr 0:34ee385f4d2d 1890 */
rajathr 0:34ee385f4d2d 1891
rajathr 0:34ee385f4d2d 1892 /**
rajathr 0:34ee385f4d2d 1893 * @brief Initializes the TIM peripheral according to the specified parameters
rajathr 0:34ee385f4d2d 1894 * in the TIM_ICInitStruct.
rajathr 0:34ee385f4d2d 1895 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
rajathr 0:34ee385f4d2d 1896 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef_mort structure that contains
rajathr 0:34ee385f4d2d 1897 * the configuration information for the specified TIM peripheral.
rajathr 0:34ee385f4d2d 1898 * @retval None
rajathr 0:34ee385f4d2d 1899 */
rajathr 0:34ee385f4d2d 1900 void TIM_ICInit_mort(TIM_TypeDef_mort* TIMx, TIM_ICInitTypeDef_mort* TIM_ICInitStruct)
rajathr 0:34ee385f4d2d 1901 {
rajathr 0:34ee385f4d2d 1902 /* Check the parameters */
rajathr 0:34ee385f4d2d 1903 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1904 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
rajathr 0:34ee385f4d2d 1905 assert_param(IS_TIM_IC_SELECTION_MORT(TIM_ICInitStruct->TIM_ICSelection));
rajathr 0:34ee385f4d2d 1906 assert_param(IS_TIM_IC_PRESCALER_MORT(TIM_ICInitStruct->TIM_ICPrescaler));
rajathr 0:34ee385f4d2d 1907 assert_param(IS_TIM_IC_FILTER_MORT(TIM_ICInitStruct->TIM_ICFilter));
rajathr 0:34ee385f4d2d 1908
rajathr 0:34ee385f4d2d 1909 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1_MORT)
rajathr 0:34ee385f4d2d 1910 {
rajathr 0:34ee385f4d2d 1911 /* TI1 Configuration */
rajathr 0:34ee385f4d2d 1912 TI1_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
rajathr 0:34ee385f4d2d 1913 TIM_ICInitStruct->TIM_ICSelection,
rajathr 0:34ee385f4d2d 1914 TIM_ICInitStruct->TIM_ICFilter);
rajathr 0:34ee385f4d2d 1915 /* Set the Input Capture Prescaler value */
rajathr 0:34ee385f4d2d 1916 TIM_SetIC1Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
rajathr 0:34ee385f4d2d 1917 }
rajathr 0:34ee385f4d2d 1918 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2_MORT)
rajathr 0:34ee385f4d2d 1919 {
rajathr 0:34ee385f4d2d 1920 /* TI2 Configuration */
rajathr 0:34ee385f4d2d 1921 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1922 TI2_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
rajathr 0:34ee385f4d2d 1923 TIM_ICInitStruct->TIM_ICSelection,
rajathr 0:34ee385f4d2d 1924 TIM_ICInitStruct->TIM_ICFilter);
rajathr 0:34ee385f4d2d 1925 /* Set the Input Capture Prescaler value */
rajathr 0:34ee385f4d2d 1926 TIM_SetIC2Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
rajathr 0:34ee385f4d2d 1927 }
rajathr 0:34ee385f4d2d 1928 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3_MORT)
rajathr 0:34ee385f4d2d 1929 {
rajathr 0:34ee385f4d2d 1930 /* TI3 Configuration */
rajathr 0:34ee385f4d2d 1931 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1932 TI3_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
rajathr 0:34ee385f4d2d 1933 TIM_ICInitStruct->TIM_ICSelection,
rajathr 0:34ee385f4d2d 1934 TIM_ICInitStruct->TIM_ICFilter);
rajathr 0:34ee385f4d2d 1935 /* Set the Input Capture Prescaler value */
rajathr 0:34ee385f4d2d 1936 TIM_SetIC3Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
rajathr 0:34ee385f4d2d 1937 }
rajathr 0:34ee385f4d2d 1938 else
rajathr 0:34ee385f4d2d 1939 {
rajathr 0:34ee385f4d2d 1940 /* TI4 Configuration */
rajathr 0:34ee385f4d2d 1941 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1942 TI4_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
rajathr 0:34ee385f4d2d 1943 TIM_ICInitStruct->TIM_ICSelection,
rajathr 0:34ee385f4d2d 1944 TIM_ICInitStruct->TIM_ICFilter);
rajathr 0:34ee385f4d2d 1945 /* Set the Input Capture Prescaler value */
rajathr 0:34ee385f4d2d 1946 TIM_SetIC4Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
rajathr 0:34ee385f4d2d 1947 }
rajathr 0:34ee385f4d2d 1948 }
rajathr 0:34ee385f4d2d 1949
rajathr 0:34ee385f4d2d 1950 /**
rajathr 0:34ee385f4d2d 1951 * @brief Fills each TIM_ICInitStruct member with its default value.
rajathr 0:34ee385f4d2d 1952 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef_mort structure which will
rajathr 0:34ee385f4d2d 1953 * be initialized.
rajathr 0:34ee385f4d2d 1954 * @retval None
rajathr 0:34ee385f4d2d 1955 */
rajathr 0:34ee385f4d2d 1956 void TIM_ICStructInit_mort(TIM_ICInitTypeDef_mort* TIM_ICInitStruct)
rajathr 0:34ee385f4d2d 1957 {
rajathr 0:34ee385f4d2d 1958 /* Set the default configuration */
rajathr 0:34ee385f4d2d 1959 TIM_ICInitStruct->TIM_Channel = TIM_Channel_1_MORT;
rajathr 0:34ee385f4d2d 1960 TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising_MORT;
rajathr 0:34ee385f4d2d 1961 TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI_MORT;
rajathr 0:34ee385f4d2d 1962 TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1_MORT;
rajathr 0:34ee385f4d2d 1963 TIM_ICInitStruct->TIM_ICFilter = 0x00;
rajathr 0:34ee385f4d2d 1964 }
rajathr 0:34ee385f4d2d 1965
rajathr 0:34ee385f4d2d 1966 /**
rajathr 0:34ee385f4d2d 1967 * @brief Configures the TIM peripheral according to the specified parameters
rajathr 0:34ee385f4d2d 1968 * in the TIM_ICInitStruct to measure an external PWM signal.
rajathr 0:34ee385f4d2d 1969 * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM
rajathr 0:34ee385f4d2d 1970 * peripheral.
rajathr 0:34ee385f4d2d 1971 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef_mort structure that contains
rajathr 0:34ee385f4d2d 1972 * the configuration information for the specified TIM peripheral.
rajathr 0:34ee385f4d2d 1973 * @retval None
rajathr 0:34ee385f4d2d 1974 */
rajathr 0:34ee385f4d2d 1975 void TIM_PWMIConfig_mort(TIM_TypeDef_mort* TIMx, TIM_ICInitTypeDef_mort* TIM_ICInitStruct)
rajathr 0:34ee385f4d2d 1976 {
rajathr 0:34ee385f4d2d 1977 uint16_t icoppositepolarity = TIM_ICPolarity_Rising_MORT;
rajathr 0:34ee385f4d2d 1978 uint16_t icoppositeselection = TIM_ICSelection_DirectTI_MORT;
rajathr 0:34ee385f4d2d 1979
rajathr 0:34ee385f4d2d 1980 /* Check the parameters */
rajathr 0:34ee385f4d2d 1981 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 1982
rajathr 0:34ee385f4d2d 1983 /* Select the Opposite Input Polarity */
rajathr 0:34ee385f4d2d 1984 if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising_MORT)
rajathr 0:34ee385f4d2d 1985 {
rajathr 0:34ee385f4d2d 1986 icoppositepolarity = TIM_ICPolarity_Falling_MORT;
rajathr 0:34ee385f4d2d 1987 }
rajathr 0:34ee385f4d2d 1988 else
rajathr 0:34ee385f4d2d 1989 {
rajathr 0:34ee385f4d2d 1990 icoppositepolarity = TIM_ICPolarity_Rising_MORT;
rajathr 0:34ee385f4d2d 1991 }
rajathr 0:34ee385f4d2d 1992 /* Select the Opposite Input */
rajathr 0:34ee385f4d2d 1993 if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI_MORT)
rajathr 0:34ee385f4d2d 1994 {
rajathr 0:34ee385f4d2d 1995 icoppositeselection = TIM_ICSelection_IndirectTI_MORT;
rajathr 0:34ee385f4d2d 1996 }
rajathr 0:34ee385f4d2d 1997 else
rajathr 0:34ee385f4d2d 1998 {
rajathr 0:34ee385f4d2d 1999 icoppositeselection = TIM_ICSelection_DirectTI_MORT;
rajathr 0:34ee385f4d2d 2000 }
rajathr 0:34ee385f4d2d 2001 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1_MORT)
rajathr 0:34ee385f4d2d 2002 {
rajathr 0:34ee385f4d2d 2003 /* TI1 Configuration */
rajathr 0:34ee385f4d2d 2004 TI1_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
rajathr 0:34ee385f4d2d 2005 TIM_ICInitStruct->TIM_ICFilter);
rajathr 0:34ee385f4d2d 2006 /* Set the Input Capture Prescaler value */
rajathr 0:34ee385f4d2d 2007 TIM_SetIC1Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
rajathr 0:34ee385f4d2d 2008 /* TI2 Configuration */
rajathr 0:34ee385f4d2d 2009 TI2_Config_mort(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
rajathr 0:34ee385f4d2d 2010 /* Set the Input Capture Prescaler value */
rajathr 0:34ee385f4d2d 2011 TIM_SetIC2Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
rajathr 0:34ee385f4d2d 2012 }
rajathr 0:34ee385f4d2d 2013 else
rajathr 0:34ee385f4d2d 2014 {
rajathr 0:34ee385f4d2d 2015 /* TI2 Configuration */
rajathr 0:34ee385f4d2d 2016 TI2_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
rajathr 0:34ee385f4d2d 2017 TIM_ICInitStruct->TIM_ICFilter);
rajathr 0:34ee385f4d2d 2018 /* Set the Input Capture Prescaler value */
rajathr 0:34ee385f4d2d 2019 TIM_SetIC2Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
rajathr 0:34ee385f4d2d 2020 /* TI1 Configuration */
rajathr 0:34ee385f4d2d 2021 TI1_Config_mort(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
rajathr 0:34ee385f4d2d 2022 /* Set the Input Capture Prescaler value */
rajathr 0:34ee385f4d2d 2023 TIM_SetIC1Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
rajathr 0:34ee385f4d2d 2024 }
rajathr 0:34ee385f4d2d 2025 }
rajathr 0:34ee385f4d2d 2026
rajathr 0:34ee385f4d2d 2027 /**
rajathr 0:34ee385f4d2d 2028 * @brief Gets the TIMx Input Capture 1 value.
rajathr 0:34ee385f4d2d 2029 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2030 * @retval Capture Compare 1 Register value.
rajathr 0:34ee385f4d2d 2031 */
rajathr 0:34ee385f4d2d 2032 uint32_t TIM_GetCapture1_mort(TIM_TypeDef_mort* TIMx)
rajathr 0:34ee385f4d2d 2033 {
rajathr 0:34ee385f4d2d 2034 /* Check the parameters */
rajathr 0:34ee385f4d2d 2035 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2036
rajathr 0:34ee385f4d2d 2037 /* Get the Capture 1 Register value */
rajathr 0:34ee385f4d2d 2038 return TIMx->CCR1;
rajathr 0:34ee385f4d2d 2039 }
rajathr 0:34ee385f4d2d 2040
rajathr 0:34ee385f4d2d 2041 /**
rajathr 0:34ee385f4d2d 2042 * @brief Gets the TIMx Input Capture 2 value.
rajathr 0:34ee385f4d2d 2043 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
rajathr 0:34ee385f4d2d 2044 * peripheral.
rajathr 0:34ee385f4d2d 2045 * @retval Capture Compare 2 Register value.
rajathr 0:34ee385f4d2d 2046 */
rajathr 0:34ee385f4d2d 2047 uint32_t TIM_GetCapture2_mort(TIM_TypeDef_mort* TIMx)
rajathr 0:34ee385f4d2d 2048 {
rajathr 0:34ee385f4d2d 2049 /* Check the parameters */
rajathr 0:34ee385f4d2d 2050 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2051
rajathr 0:34ee385f4d2d 2052 /* Get the Capture 2 Register value */
rajathr 0:34ee385f4d2d 2053 return TIMx->CCR2;
rajathr 0:34ee385f4d2d 2054 }
rajathr 0:34ee385f4d2d 2055
rajathr 0:34ee385f4d2d 2056 /**
rajathr 0:34ee385f4d2d 2057 * @brief Gets the TIMx Input Capture 3 value.
rajathr 0:34ee385f4d2d 2058 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2059 * @retval Capture Compare 3 Register value.
rajathr 0:34ee385f4d2d 2060 */
rajathr 0:34ee385f4d2d 2061 uint32_t TIM_GetCapture3_mort(TIM_TypeDef_mort* TIMx)
rajathr 0:34ee385f4d2d 2062 {
rajathr 0:34ee385f4d2d 2063 /* Check the parameters */
rajathr 0:34ee385f4d2d 2064 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2065
rajathr 0:34ee385f4d2d 2066 /* Get the Capture 3 Register value */
rajathr 0:34ee385f4d2d 2067 return TIMx->CCR3;
rajathr 0:34ee385f4d2d 2068 }
rajathr 0:34ee385f4d2d 2069
rajathr 0:34ee385f4d2d 2070 /**
rajathr 0:34ee385f4d2d 2071 * @brief Gets the TIMx Input Capture 4 value.
rajathr 0:34ee385f4d2d 2072 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2073 * @retval Capture Compare 4 Register value.
rajathr 0:34ee385f4d2d 2074 */
rajathr 0:34ee385f4d2d 2075 uint32_t TIM_GetCapture4_mort(TIM_TypeDef_mort* TIMx)
rajathr 0:34ee385f4d2d 2076 {
rajathr 0:34ee385f4d2d 2077 /* Check the parameters */
rajathr 0:34ee385f4d2d 2078 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2079
rajathr 0:34ee385f4d2d 2080 /* Get the Capture 4 Register value */
rajathr 0:34ee385f4d2d 2081 return TIMx->CCR4;
rajathr 0:34ee385f4d2d 2082 }
rajathr 0:34ee385f4d2d 2083
rajathr 0:34ee385f4d2d 2084 /**
rajathr 0:34ee385f4d2d 2085 * @brief Sets the TIMx Input Capture 1 prescaler.
rajathr 0:34ee385f4d2d 2086 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2087 * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
rajathr 0:34ee385f4d2d 2088 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2089 * @arg TIM_ICPSC_DIV1_MORT: no prescaler
rajathr 0:34ee385f4d2d 2090 * @arg TIM_ICPSC_DIV2_MORT: capture is done once every 2 events
rajathr 0:34ee385f4d2d 2091 * @arg TIM_ICPSC_DIV4_MORT: capture is done once every 4 events
rajathr 0:34ee385f4d2d 2092 * @arg TIM_ICPSC_DIV8_MORT: capture is done once every 8 events
rajathr 0:34ee385f4d2d 2093 * @retval None
rajathr 0:34ee385f4d2d 2094 */
rajathr 0:34ee385f4d2d 2095 void TIM_SetIC1Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC)
rajathr 0:34ee385f4d2d 2096 {
rajathr 0:34ee385f4d2d 2097 /* Check the parameters */
rajathr 0:34ee385f4d2d 2098 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2099 assert_param(IS_TIM_IC_PRESCALER_MORT(TIM_ICPSC));
rajathr 0:34ee385f4d2d 2100
rajathr 0:34ee385f4d2d 2101 /* Reset the IC1PSC Bits */
rajathr 0:34ee385f4d2d 2102 TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC_MORT;
rajathr 0:34ee385f4d2d 2103
rajathr 0:34ee385f4d2d 2104 /* Set the IC1PSC value */
rajathr 0:34ee385f4d2d 2105 TIMx->CCMR1 |= TIM_ICPSC;
rajathr 0:34ee385f4d2d 2106 }
rajathr 0:34ee385f4d2d 2107
rajathr 0:34ee385f4d2d 2108 /**
rajathr 0:34ee385f4d2d 2109 * @brief Sets the TIMx Input Capture 2 prescaler.
rajathr 0:34ee385f4d2d 2110 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
rajathr 0:34ee385f4d2d 2111 * peripheral.
rajathr 0:34ee385f4d2d 2112 * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
rajathr 0:34ee385f4d2d 2113 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2114 * @arg TIM_ICPSC_DIV1_MORT: no prescaler
rajathr 0:34ee385f4d2d 2115 * @arg TIM_ICPSC_DIV2_MORT: capture is done once every 2 events
rajathr 0:34ee385f4d2d 2116 * @arg TIM_ICPSC_DIV4_MORT: capture is done once every 4 events
rajathr 0:34ee385f4d2d 2117 * @arg TIM_ICPSC_DIV8_MORT: capture is done once every 8 events
rajathr 0:34ee385f4d2d 2118 * @retval None
rajathr 0:34ee385f4d2d 2119 */
rajathr 0:34ee385f4d2d 2120 void TIM_SetIC2Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC)
rajathr 0:34ee385f4d2d 2121 {
rajathr 0:34ee385f4d2d 2122 /* Check the parameters */
rajathr 0:34ee385f4d2d 2123 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2124 assert_param(IS_TIM_IC_PRESCALER_MORT(TIM_ICPSC));
rajathr 0:34ee385f4d2d 2125
rajathr 0:34ee385f4d2d 2126 /* Reset the IC2PSC Bits */
rajathr 0:34ee385f4d2d 2127 TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC_MORT;
rajathr 0:34ee385f4d2d 2128
rajathr 0:34ee385f4d2d 2129 /* Set the IC2PSC value */
rajathr 0:34ee385f4d2d 2130 TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
rajathr 0:34ee385f4d2d 2131 }
rajathr 0:34ee385f4d2d 2132
rajathr 0:34ee385f4d2d 2133 /**
rajathr 0:34ee385f4d2d 2134 * @brief Sets the TIMx Input Capture 3 prescaler.
rajathr 0:34ee385f4d2d 2135 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2136 * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
rajathr 0:34ee385f4d2d 2137 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2138 * @arg TIM_ICPSC_DIV1_MORT: no prescaler
rajathr 0:34ee385f4d2d 2139 * @arg TIM_ICPSC_DIV2_MORT: capture is done once every 2 events
rajathr 0:34ee385f4d2d 2140 * @arg TIM_ICPSC_DIV4_MORT: capture is done once every 4 events
rajathr 0:34ee385f4d2d 2141 * @arg TIM_ICPSC_DIV8_MORT: capture is done once every 8 events
rajathr 0:34ee385f4d2d 2142 * @retval None
rajathr 0:34ee385f4d2d 2143 */
rajathr 0:34ee385f4d2d 2144 void TIM_SetIC3Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC)
rajathr 0:34ee385f4d2d 2145 {
rajathr 0:34ee385f4d2d 2146 /* Check the parameters */
rajathr 0:34ee385f4d2d 2147 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2148 assert_param(IS_TIM_IC_PRESCALER_MORT(TIM_ICPSC));
rajathr 0:34ee385f4d2d 2149
rajathr 0:34ee385f4d2d 2150 /* Reset the IC3PSC Bits */
rajathr 0:34ee385f4d2d 2151 TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC_MORT;
rajathr 0:34ee385f4d2d 2152
rajathr 0:34ee385f4d2d 2153 /* Set the IC3PSC value */
rajathr 0:34ee385f4d2d 2154 TIMx->CCMR2 |= TIM_ICPSC;
rajathr 0:34ee385f4d2d 2155 }
rajathr 0:34ee385f4d2d 2156
rajathr 0:34ee385f4d2d 2157 /**
rajathr 0:34ee385f4d2d 2158 * @brief Sets the TIMx Input Capture 4 prescaler.
rajathr 0:34ee385f4d2d 2159 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2160 * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
rajathr 0:34ee385f4d2d 2161 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2162 * @arg TIM_ICPSC_DIV1_MORT: no prescaler
rajathr 0:34ee385f4d2d 2163 * @arg TIM_ICPSC_DIV2_MORT: capture is done once every 2 events
rajathr 0:34ee385f4d2d 2164 * @arg TIM_ICPSC_DIV4_MORT: capture is done once every 4 events
rajathr 0:34ee385f4d2d 2165 * @arg TIM_ICPSC_DIV8_MORT: capture is done once every 8 events
rajathr 0:34ee385f4d2d 2166 * @retval None
rajathr 0:34ee385f4d2d 2167 */
rajathr 0:34ee385f4d2d 2168 void TIM_SetIC4Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC)
rajathr 0:34ee385f4d2d 2169 {
rajathr 0:34ee385f4d2d 2170 /* Check the parameters */
rajathr 0:34ee385f4d2d 2171 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2172 assert_param(IS_TIM_IC_PRESCALER_MORT(TIM_ICPSC));
rajathr 0:34ee385f4d2d 2173
rajathr 0:34ee385f4d2d 2174 /* Reset the IC4PSC Bits */
rajathr 0:34ee385f4d2d 2175 TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC_MORT;
rajathr 0:34ee385f4d2d 2176
rajathr 0:34ee385f4d2d 2177 /* Set the IC4PSC value */
rajathr 0:34ee385f4d2d 2178 TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
rajathr 0:34ee385f4d2d 2179 }
rajathr 0:34ee385f4d2d 2180 /**
rajathr 0:34ee385f4d2d 2181 * @}
rajathr 0:34ee385f4d2d 2182 */
rajathr 0:34ee385f4d2d 2183
rajathr 0:34ee385f4d2d 2184 /** @defgroup TIM_Group4 Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features
rajathr 0:34ee385f4d2d 2185 * @brief Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features
rajathr 0:34ee385f4d2d 2186 *
rajathr 0:34ee385f4d2d 2187 @verbatim
rajathr 0:34ee385f4d2d 2188 ===============================================================================
rajathr 0:34ee385f4d2d 2189 ##### Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features #####
rajathr 0:34ee385f4d2d 2190 ===============================================================================
rajathr 0:34ee385f4d2d 2191
rajathr 0:34ee385f4d2d 2192 ##### TIM Driver: how to use the Break feature #####
rajathr 0:34ee385f4d2d 2193 ===============================================================================
rajathr 0:34ee385f4d2d 2194 [..]
rajathr 0:34ee385f4d2d 2195 After configuring the Timer channel(s) in the appropriate Output Compare mode:
rajathr 0:34ee385f4d2d 2196
rajathr 0:34ee385f4d2d 2197 (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
rajathr 0:34ee385f4d2d 2198 Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
rajathr 0:34ee385f4d2d 2199 AOE(automatic output enable).
rajathr 0:34ee385f4d2d 2200
rajathr 0:34ee385f4d2d 2201 (#) Call TIM_BDTRConfig_mort(TIMx, &TIM_BDTRInitStruct) to configure the Timer
rajathr 0:34ee385f4d2d 2202
rajathr 0:34ee385f4d2d 2203 (#) Enable the Main Output using TIM_CtrlPWMOutputs_mort(TIM1_MORT, ENABLE)
rajathr 0:34ee385f4d2d 2204
rajathr 0:34ee385f4d2d 2205 (#) Once the break even occurs, the Timer's output signals are put in reset
rajathr 0:34ee385f4d2d 2206 state or in a known state (according to the configuration made in
rajathr 0:34ee385f4d2d 2207 TIM_BDTRConfig_mort() function).
rajathr 0:34ee385f4d2d 2208
rajathr 0:34ee385f4d2d 2209 @endverbatim
rajathr 0:34ee385f4d2d 2210 * @{
rajathr 0:34ee385f4d2d 2211 */
rajathr 0:34ee385f4d2d 2212
rajathr 0:34ee385f4d2d 2213 /**
rajathr 0:34ee385f4d2d 2214 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
rajathr 0:34ee385f4d2d 2215 * and the AOE(automatic output enable).
rajathr 0:34ee385f4d2d 2216 * @param TIMx: where x can be 1 or 8 to select the TIM
rajathr 0:34ee385f4d2d 2217 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef_mort structure that
rajathr 0:34ee385f4d2d 2218 * contains the BDTR Register configuration information for the TIM peripheral.
rajathr 0:34ee385f4d2d 2219 * @retval None
rajathr 0:34ee385f4d2d 2220 */
rajathr 0:34ee385f4d2d 2221 void TIM_BDTRConfig_mort(TIM_TypeDef_mort* TIMx, TIM_BDTRInitTypeDef_mort *TIM_BDTRInitStruct)
rajathr 0:34ee385f4d2d 2222 {
rajathr 0:34ee385f4d2d 2223 /* Check the parameters */
rajathr 0:34ee385f4d2d 2224 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2225 assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
rajathr 0:34ee385f4d2d 2226 assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
rajathr 0:34ee385f4d2d 2227 assert_param(IS_TIM_LOCK_LEVEL_MORT(TIM_BDTRInitStruct->TIM_LOCKLevel));
rajathr 0:34ee385f4d2d 2228 assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
rajathr 0:34ee385f4d2d 2229 assert_param(IS_TIM_BREAK_POLARITY_MORT(TIM_BDTRInitStruct->TIM_BreakPolarity));
rajathr 0:34ee385f4d2d 2230 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE_MORT(TIM_BDTRInitStruct->TIM_AutomaticOutput));
rajathr 0:34ee385f4d2d 2231
rajathr 0:34ee385f4d2d 2232 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
rajathr 0:34ee385f4d2d 2233 the OSSI State, the dead time value and the Automatic Output Enable Bit */
rajathr 0:34ee385f4d2d 2234 TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
rajathr 0:34ee385f4d2d 2235 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
rajathr 0:34ee385f4d2d 2236 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
rajathr 0:34ee385f4d2d 2237 TIM_BDTRInitStruct->TIM_AutomaticOutput;
rajathr 0:34ee385f4d2d 2238 }
rajathr 0:34ee385f4d2d 2239
rajathr 0:34ee385f4d2d 2240 /**
rajathr 0:34ee385f4d2d 2241 * @brief Fills each TIM_BDTRInitStruct member with its default value.
rajathr 0:34ee385f4d2d 2242 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef_mort structure which
rajathr 0:34ee385f4d2d 2243 * will be initialized.
rajathr 0:34ee385f4d2d 2244 * @retval None
rajathr 0:34ee385f4d2d 2245 */
rajathr 0:34ee385f4d2d 2246 void TIM_BDTRStructInit_mort(TIM_BDTRInitTypeDef_mort* TIM_BDTRInitStruct)
rajathr 0:34ee385f4d2d 2247 {
rajathr 0:34ee385f4d2d 2248 /* Set the default configuration */
rajathr 0:34ee385f4d2d 2249 TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable_MORT;
rajathr 0:34ee385f4d2d 2250 TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable_MORT;
rajathr 0:34ee385f4d2d 2251 TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF_MORT;
rajathr 0:34ee385f4d2d 2252 TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
rajathr 0:34ee385f4d2d 2253 TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable_MORT;
rajathr 0:34ee385f4d2d 2254 TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low_MORT;
rajathr 0:34ee385f4d2d 2255 TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable_MORT;
rajathr 0:34ee385f4d2d 2256 }
rajathr 0:34ee385f4d2d 2257
rajathr 0:34ee385f4d2d 2258 /**
rajathr 0:34ee385f4d2d 2259 * @brief Enables or disables the TIM peripheral Main Outputs.
rajathr 0:34ee385f4d2d 2260 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
rajathr 0:34ee385f4d2d 2261 * @param NewState: new state of the TIM peripheral Main Outputs.
rajathr 0:34ee385f4d2d 2262 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2263 * @retval None
rajathr 0:34ee385f4d2d 2264 */
rajathr 0:34ee385f4d2d 2265 void TIM_CtrlPWMOutputs_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2266 {
rajathr 0:34ee385f4d2d 2267 /* Check the parameters */
rajathr 0:34ee385f4d2d 2268 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2269 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2270
rajathr 0:34ee385f4d2d 2271 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2272 {
rajathr 0:34ee385f4d2d 2273 /* Enable the TIM Main Output */
rajathr 0:34ee385f4d2d 2274 TIMx->BDTR |= TIM_BDTR_MOE_MORT;
rajathr 0:34ee385f4d2d 2275 }
rajathr 0:34ee385f4d2d 2276 else
rajathr 0:34ee385f4d2d 2277 {
rajathr 0:34ee385f4d2d 2278 /* Disable the TIM Main Output */
rajathr 0:34ee385f4d2d 2279 TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE_MORT;
rajathr 0:34ee385f4d2d 2280 }
rajathr 0:34ee385f4d2d 2281 }
rajathr 0:34ee385f4d2d 2282
rajathr 0:34ee385f4d2d 2283 /**
rajathr 0:34ee385f4d2d 2284 * @brief Selects the TIM peripheral Commutation event.
rajathr 0:34ee385f4d2d 2285 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
rajathr 0:34ee385f4d2d 2286 * @param NewState: new state of the Commutation event.
rajathr 0:34ee385f4d2d 2287 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2288 * @retval None
rajathr 0:34ee385f4d2d 2289 */
rajathr 0:34ee385f4d2d 2290 void TIM_SelectCOM_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2291 {
rajathr 0:34ee385f4d2d 2292 /* Check the parameters */
rajathr 0:34ee385f4d2d 2293 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2294 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2295
rajathr 0:34ee385f4d2d 2296 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2297 {
rajathr 0:34ee385f4d2d 2298 /* Set the COM Bit */
rajathr 0:34ee385f4d2d 2299 TIMx->CR2 |= TIM_CR2_CCUS_MORT;
rajathr 0:34ee385f4d2d 2300 }
rajathr 0:34ee385f4d2d 2301 else
rajathr 0:34ee385f4d2d 2302 {
rajathr 0:34ee385f4d2d 2303 /* Reset the COM Bit */
rajathr 0:34ee385f4d2d 2304 TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS_MORT;
rajathr 0:34ee385f4d2d 2305 }
rajathr 0:34ee385f4d2d 2306 }
rajathr 0:34ee385f4d2d 2307
rajathr 0:34ee385f4d2d 2308 /**
rajathr 0:34ee385f4d2d 2309 * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
rajathr 0:34ee385f4d2d 2310 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
rajathr 0:34ee385f4d2d 2311 * @param NewState: new state of the Capture Compare Preload Control bit
rajathr 0:34ee385f4d2d 2312 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2313 * @retval None
rajathr 0:34ee385f4d2d 2314 */
rajathr 0:34ee385f4d2d 2315 void TIM_CCPreloadControl_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2316 {
rajathr 0:34ee385f4d2d 2317 /* Check the parameters */
rajathr 0:34ee385f4d2d 2318 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2319 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2320 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2321 {
rajathr 0:34ee385f4d2d 2322 /* Set the CCPC Bit */
rajathr 0:34ee385f4d2d 2323 TIMx->CR2 |= TIM_CR2_CCPC_MORT;
rajathr 0:34ee385f4d2d 2324 }
rajathr 0:34ee385f4d2d 2325 else
rajathr 0:34ee385f4d2d 2326 {
rajathr 0:34ee385f4d2d 2327 /* Reset the CCPC Bit */
rajathr 0:34ee385f4d2d 2328 TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC_MORT;
rajathr 0:34ee385f4d2d 2329 }
rajathr 0:34ee385f4d2d 2330 }
rajathr 0:34ee385f4d2d 2331 /**
rajathr 0:34ee385f4d2d 2332 * @}
rajathr 0:34ee385f4d2d 2333 */
rajathr 0:34ee385f4d2d 2334
rajathr 0:34ee385f4d2d 2335 /** @defgroup TIM_Group5 Interrupts DMA and flags management functions
rajathr 0:34ee385f4d2d 2336 * @brief Interrupts, DMA and flags management functions
rajathr 0:34ee385f4d2d 2337 *
rajathr 0:34ee385f4d2d 2338 @verbatim
rajathr 0:34ee385f4d2d 2339 ===============================================================================
rajathr 0:34ee385f4d2d 2340 ##### Interrupts, DMA and flags management functions #####
rajathr 0:34ee385f4d2d 2341 ===============================================================================
rajathr 0:34ee385f4d2d 2342
rajathr 0:34ee385f4d2d 2343 @endverbatim
rajathr 0:34ee385f4d2d 2344 * @{
rajathr 0:34ee385f4d2d 2345 */
rajathr 0:34ee385f4d2d 2346
rajathr 0:34ee385f4d2d 2347 /**
rajathr 0:34ee385f4d2d 2348 * @brief Enables or disables the specified TIM interrupts.
rajathr 0:34ee385f4d2d 2349 * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
rajathr 0:34ee385f4d2d 2350 * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
rajathr 0:34ee385f4d2d 2351 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2352 * @arg TIM_IT_Update_MORT: TIM update Interrupt source
rajathr 0:34ee385f4d2d 2353 * @arg TIM_IT_CC1_MORT: TIM Capture Compare 1 Interrupt source
rajathr 0:34ee385f4d2d 2354 * @arg TIM_IT_CC2_MORT: TIM Capture Compare 2 Interrupt source
rajathr 0:34ee385f4d2d 2355 * @arg TIM_IT_CC3_MORT: TIM Capture Compare 3 Interrupt source
rajathr 0:34ee385f4d2d 2356 * @arg TIM_IT_CC4_MORT: TIM Capture Compare 4 Interrupt source
rajathr 0:34ee385f4d2d 2357 * @arg TIM_IT_COM_MORT: TIM Commutation Interrupt source
rajathr 0:34ee385f4d2d 2358 * @arg TIM_IT_Trigger_MORT: TIM Trigger Interrupt source
rajathr 0:34ee385f4d2d 2359 * @arg TIM_IT_Break_MORT: TIM Break Interrupt source
rajathr 0:34ee385f4d2d 2360 *
rajathr 0:34ee385f4d2d 2361 * @note For TIM6_MORT and TIM7_MORT only the parameter TIM_IT_Update_MORT can be used
rajathr 0:34ee385f4d2d 2362 * @note For TIM9_MORT and TIM12_MORT only one of the following parameters can be used: TIM_IT_Update_MORT,
rajathr 0:34ee385f4d2d 2363 * TIM_IT_CC1_MORT, TIM_IT_CC2_MORT or TIM_IT_Trigger_MORT.
rajathr 0:34ee385f4d2d 2364 * @note For TIM10_MORT, TIM11_MORT, TIM13_MORT and TIM14_MORT only one of the following parameters can
rajathr 0:34ee385f4d2d 2365 * be used: TIM_IT_Update_MORT or TIM_IT_CC1_MORT
rajathr 0:34ee385f4d2d 2366 * @note TIM_IT_COM_MORT and TIM_IT_Break_MORT can be used only with TIM1_MORT and TIM8_MORT
rajathr 0:34ee385f4d2d 2367 *
rajathr 0:34ee385f4d2d 2368 * @param NewState: new state of the TIM interrupts.
rajathr 0:34ee385f4d2d 2369 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2370 * @retval None
rajathr 0:34ee385f4d2d 2371 */
rajathr 0:34ee385f4d2d 2372 void TIM_ITConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2373 {
rajathr 0:34ee385f4d2d 2374 /* Check the parameters */
rajathr 0:34ee385f4d2d 2375 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2376 assert_param(IS_TIM_IT_MORT(TIM_IT));
rajathr 0:34ee385f4d2d 2377 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2378
rajathr 0:34ee385f4d2d 2379 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2380 {
rajathr 0:34ee385f4d2d 2381 /* Enable the Interrupt sources */
rajathr 0:34ee385f4d2d 2382 TIMx->DIER |= TIM_IT;
rajathr 0:34ee385f4d2d 2383 }
rajathr 0:34ee385f4d2d 2384 else
rajathr 0:34ee385f4d2d 2385 {
rajathr 0:34ee385f4d2d 2386 /* Disable the Interrupt sources */
rajathr 0:34ee385f4d2d 2387 TIMx->DIER &= (uint16_t)~TIM_IT;
rajathr 0:34ee385f4d2d 2388 }
rajathr 0:34ee385f4d2d 2389 }
rajathr 0:34ee385f4d2d 2390
rajathr 0:34ee385f4d2d 2391 /**
rajathr 0:34ee385f4d2d 2392 * @brief Configures the TIMx event to be generate by software.
rajathr 0:34ee385f4d2d 2393 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2394 * @param TIM_EventSource: specifies the event source.
rajathr 0:34ee385f4d2d 2395 * This parameter can be one or more of the following values:
rajathr 0:34ee385f4d2d 2396 * @arg TIM_EventSource_Update_MORT: Timer update Event source
rajathr 0:34ee385f4d2d 2397 * @arg TIM_EventSource_CC1_MORT: Timer Capture Compare 1 Event source
rajathr 0:34ee385f4d2d 2398 * @arg TIM_EventSource_CC2_MORT: Timer Capture Compare 2 Event source
rajathr 0:34ee385f4d2d 2399 * @arg TIM_EventSource_CC3_MORT: Timer Capture Compare 3 Event source
rajathr 0:34ee385f4d2d 2400 * @arg TIM_EventSource_CC4_MORT: Timer Capture Compare 4 Event source
rajathr 0:34ee385f4d2d 2401 * @arg TIM_EventSource_COM_MORT: Timer COM event source
rajathr 0:34ee385f4d2d 2402 * @arg TIM_EventSource_Trigger_MORT: Timer Trigger Event source
rajathr 0:34ee385f4d2d 2403 * @arg TIM_EventSource_Break_MORT: Timer Break event source
rajathr 0:34ee385f4d2d 2404 *
rajathr 0:34ee385f4d2d 2405 * @note TIM6_MORT and TIM7_MORT can only generate an update event.
rajathr 0:34ee385f4d2d 2406 * @note TIM_EventSource_COM_MORT and TIM_EventSource_Break_MORT are used only with TIM1_MORT and TIM8_MORT.
rajathr 0:34ee385f4d2d 2407 *
rajathr 0:34ee385f4d2d 2408 * @retval None
rajathr 0:34ee385f4d2d 2409 */
rajathr 0:34ee385f4d2d 2410 void TIM_GenerateEvent_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_EventSource)
rajathr 0:34ee385f4d2d 2411 {
rajathr 0:34ee385f4d2d 2412 /* Check the parameters */
rajathr 0:34ee385f4d2d 2413 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2414 assert_param(IS_TIM_EVENT_SOURCE_MORT(TIM_EventSource));
rajathr 0:34ee385f4d2d 2415
rajathr 0:34ee385f4d2d 2416 /* Set the event sources */
rajathr 0:34ee385f4d2d 2417 TIMx->EGR = TIM_EventSource;
rajathr 0:34ee385f4d2d 2418 }
rajathr 0:34ee385f4d2d 2419
rajathr 0:34ee385f4d2d 2420 /**
rajathr 0:34ee385f4d2d 2421 * @brief Checks whether the specified TIM flag is set or not.
rajathr 0:34ee385f4d2d 2422 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2423 * @param TIM_FLAG: specifies the flag to check.
rajathr 0:34ee385f4d2d 2424 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2425 * @arg TIM_FLAG_Update_MORT: TIM update Flag
rajathr 0:34ee385f4d2d 2426 * @arg TIM_FLAG_CC1_MORT: TIM Capture Compare 1 Flag
rajathr 0:34ee385f4d2d 2427 * @arg TIM_FLAG_CC2_MORT: TIM Capture Compare 2 Flag
rajathr 0:34ee385f4d2d 2428 * @arg TIM_FLAG_CC3_MORT: TIM Capture Compare 3 Flag
rajathr 0:34ee385f4d2d 2429 * @arg TIM_FLAG_CC4_MORT: TIM Capture Compare 4 Flag
rajathr 0:34ee385f4d2d 2430 * @arg TIM_FLAG_COM_MORT: TIM Commutation Flag
rajathr 0:34ee385f4d2d 2431 * @arg TIM_FLAG_Trigger_MORT: TIM Trigger Flag
rajathr 0:34ee385f4d2d 2432 * @arg TIM_FLAG_Break_MORT: TIM Break Flag
rajathr 0:34ee385f4d2d 2433 * @arg TIM_FLAG_CC1OF_MORT: TIM Capture Compare 1 over capture Flag
rajathr 0:34ee385f4d2d 2434 * @arg TIM_FLAG_CC2OF_MORT: TIM Capture Compare 2 over capture Flag
rajathr 0:34ee385f4d2d 2435 * @arg TIM_FLAG_CC3OF_MORT: TIM Capture Compare 3 over capture Flag
rajathr 0:34ee385f4d2d 2436 * @arg TIM_FLAG_CC4OF_MORT: TIM Capture Compare 4 over capture Flag
rajathr 0:34ee385f4d2d 2437 *
rajathr 0:34ee385f4d2d 2438 * @note TIM6_MORT and TIM7_MORT can have only one update flag.
rajathr 0:34ee385f4d2d 2439 * @note TIM_FLAG_COM_MORT and TIM_FLAG_Break_MORT are used only with TIM1_MORT and TIM8_MORT.
rajathr 0:34ee385f4d2d 2440 *
rajathr 0:34ee385f4d2d 2441 * @retval The new state of TIM_FLAG (SET or RESET).
rajathr 0:34ee385f4d2d 2442 */
rajathr 0:34ee385f4d2d 2443 FlagStatus TIM_GetFlagStatus_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_FLAG)
rajathr 0:34ee385f4d2d 2444 {
rajathr 0:34ee385f4d2d 2445 ITStatus bitstatus = RESET;
rajathr 0:34ee385f4d2d 2446 /* Check the parameters */
rajathr 0:34ee385f4d2d 2447 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2448 assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
rajathr 0:34ee385f4d2d 2449
rajathr 0:34ee385f4d2d 2450
rajathr 0:34ee385f4d2d 2451 if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
rajathr 0:34ee385f4d2d 2452 {
rajathr 0:34ee385f4d2d 2453 bitstatus = SET;
rajathr 0:34ee385f4d2d 2454 }
rajathr 0:34ee385f4d2d 2455 else
rajathr 0:34ee385f4d2d 2456 {
rajathr 0:34ee385f4d2d 2457 bitstatus = RESET;
rajathr 0:34ee385f4d2d 2458 }
rajathr 0:34ee385f4d2d 2459 return bitstatus;
rajathr 0:34ee385f4d2d 2460 }
rajathr 0:34ee385f4d2d 2461
rajathr 0:34ee385f4d2d 2462 /**
rajathr 0:34ee385f4d2d 2463 * @brief Clears the TIMx's pending flags.
rajathr 0:34ee385f4d2d 2464 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2465 * @param TIM_FLAG: specifies the flag bit to clear.
rajathr 0:34ee385f4d2d 2466 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2467 * @arg TIM_FLAG_Update_MORT: TIM update Flag
rajathr 0:34ee385f4d2d 2468 * @arg TIM_FLAG_CC1_MORT: TIM Capture Compare 1 Flag
rajathr 0:34ee385f4d2d 2469 * @arg TIM_FLAG_CC2_MORT: TIM Capture Compare 2 Flag
rajathr 0:34ee385f4d2d 2470 * @arg TIM_FLAG_CC3_MORT: TIM Capture Compare 3 Flag
rajathr 0:34ee385f4d2d 2471 * @arg TIM_FLAG_CC4_MORT: TIM Capture Compare 4 Flag
rajathr 0:34ee385f4d2d 2472 * @arg TIM_FLAG_COM_MORT: TIM Commutation Flag
rajathr 0:34ee385f4d2d 2473 * @arg TIM_FLAG_Trigger_MORT: TIM Trigger Flag
rajathr 0:34ee385f4d2d 2474 * @arg TIM_FLAG_Break_MORT: TIM Break Flag
rajathr 0:34ee385f4d2d 2475 * @arg TIM_FLAG_CC1OF_MORT: TIM Capture Compare 1 over capture Flag
rajathr 0:34ee385f4d2d 2476 * @arg TIM_FLAG_CC2OF_MORT: TIM Capture Compare 2 over capture Flag
rajathr 0:34ee385f4d2d 2477 * @arg TIM_FLAG_CC3OF_MORT: TIM Capture Compare 3 over capture Flag
rajathr 0:34ee385f4d2d 2478 * @arg TIM_FLAG_CC4OF_MORT: TIM Capture Compare 4 over capture Flag
rajathr 0:34ee385f4d2d 2479 *
rajathr 0:34ee385f4d2d 2480 * @note TIM6_MORT and TIM7_MORT can have only one update flag.
rajathr 0:34ee385f4d2d 2481 * @note TIM_FLAG_COM_MORT and TIM_FLAG_Break_MORT are used only with TIM1_MORT and TIM8_MORT.
rajathr 0:34ee385f4d2d 2482 *
rajathr 0:34ee385f4d2d 2483 * @retval None
rajathr 0:34ee385f4d2d 2484 */
rajathr 0:34ee385f4d2d 2485 void TIM_ClearFlag_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_FLAG)
rajathr 0:34ee385f4d2d 2486 {
rajathr 0:34ee385f4d2d 2487 /* Check the parameters */
rajathr 0:34ee385f4d2d 2488 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2489
rajathr 0:34ee385f4d2d 2490 /* Clear the flags */
rajathr 0:34ee385f4d2d 2491 TIMx->SR = (uint16_t)~TIM_FLAG;
rajathr 0:34ee385f4d2d 2492 }
rajathr 0:34ee385f4d2d 2493
rajathr 0:34ee385f4d2d 2494 /**
rajathr 0:34ee385f4d2d 2495 * @brief Checks whether the TIM interrupt has occurred or not.
rajathr 0:34ee385f4d2d 2496 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2497 * @param TIM_IT: specifies the TIM interrupt source to check.
rajathr 0:34ee385f4d2d 2498 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2499 * @arg TIM_IT_Update_MORT: TIM update Interrupt source
rajathr 0:34ee385f4d2d 2500 * @arg TIM_IT_CC1_MORT: TIM Capture Compare 1 Interrupt source
rajathr 0:34ee385f4d2d 2501 * @arg TIM_IT_CC2_MORT: TIM Capture Compare 2 Interrupt source
rajathr 0:34ee385f4d2d 2502 * @arg TIM_IT_CC3_MORT: TIM Capture Compare 3 Interrupt source
rajathr 0:34ee385f4d2d 2503 * @arg TIM_IT_CC4_MORT: TIM Capture Compare 4 Interrupt source
rajathr 0:34ee385f4d2d 2504 * @arg TIM_IT_COM_MORT: TIM Commutation Interrupt source
rajathr 0:34ee385f4d2d 2505 * @arg TIM_IT_Trigger_MORT: TIM Trigger Interrupt source
rajathr 0:34ee385f4d2d 2506 * @arg TIM_IT_Break_MORT: TIM Break Interrupt source
rajathr 0:34ee385f4d2d 2507 *
rajathr 0:34ee385f4d2d 2508 * @note TIM6_MORT and TIM7_MORT can generate only an update interrupt.
rajathr 0:34ee385f4d2d 2509 * @note TIM_IT_COM_MORT and TIM_IT_Break_MORT are used only with TIM1_MORT and TIM8_MORT.
rajathr 0:34ee385f4d2d 2510 *
rajathr 0:34ee385f4d2d 2511 * @retval The new state of the TIM_IT(SET or RESET).
rajathr 0:34ee385f4d2d 2512 */
rajathr 0:34ee385f4d2d 2513 ITStatus TIM_GetITStatus_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT)
rajathr 0:34ee385f4d2d 2514 {
rajathr 0:34ee385f4d2d 2515 ITStatus bitstatus = RESET;
rajathr 0:34ee385f4d2d 2516 uint16_t itstatus = 0x0, itenable = 0x0;
rajathr 0:34ee385f4d2d 2517 /* Check the parameters */
rajathr 0:34ee385f4d2d 2518 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2519 assert_param(IS_TIM_GET_IT_MORT(TIM_IT));
rajathr 0:34ee385f4d2d 2520
rajathr 0:34ee385f4d2d 2521 itstatus = TIMx->SR & TIM_IT;
rajathr 0:34ee385f4d2d 2522
rajathr 0:34ee385f4d2d 2523 itenable = TIMx->DIER & TIM_IT;
rajathr 0:34ee385f4d2d 2524 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
rajathr 0:34ee385f4d2d 2525 {
rajathr 0:34ee385f4d2d 2526 bitstatus = SET;
rajathr 0:34ee385f4d2d 2527 }
rajathr 0:34ee385f4d2d 2528 else
rajathr 0:34ee385f4d2d 2529 {
rajathr 0:34ee385f4d2d 2530 bitstatus = RESET;
rajathr 0:34ee385f4d2d 2531 }
rajathr 0:34ee385f4d2d 2532 return bitstatus;
rajathr 0:34ee385f4d2d 2533 }
rajathr 0:34ee385f4d2d 2534
rajathr 0:34ee385f4d2d 2535 /**
rajathr 0:34ee385f4d2d 2536 * @brief Clears the TIMx's interrupt pending bits.
rajathr 0:34ee385f4d2d 2537 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2538 * @param TIM_IT: specifies the pending bit to clear.
rajathr 0:34ee385f4d2d 2539 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2540 * @arg TIM_IT_Update_MORT: TIM1_MORT update Interrupt source
rajathr 0:34ee385f4d2d 2541 * @arg TIM_IT_CC1_MORT: TIM Capture Compare 1 Interrupt source
rajathr 0:34ee385f4d2d 2542 * @arg TIM_IT_CC2_MORT: TIM Capture Compare 2 Interrupt source
rajathr 0:34ee385f4d2d 2543 * @arg TIM_IT_CC3_MORT: TIM Capture Compare 3 Interrupt source
rajathr 0:34ee385f4d2d 2544 * @arg TIM_IT_CC4_MORT: TIM Capture Compare 4 Interrupt source
rajathr 0:34ee385f4d2d 2545 * @arg TIM_IT_COM_MORT: TIM Commutation Interrupt source
rajathr 0:34ee385f4d2d 2546 * @arg TIM_IT_Trigger_MORT: TIM Trigger Interrupt source
rajathr 0:34ee385f4d2d 2547 * @arg TIM_IT_Break_MORT: TIM Break Interrupt source
rajathr 0:34ee385f4d2d 2548 *
rajathr 0:34ee385f4d2d 2549 * @note TIM6_MORT and TIM7_MORT can generate only an update interrupt.
rajathr 0:34ee385f4d2d 2550 * @note TIM_IT_COM_MORT and TIM_IT_Break_MORT are used only with TIM1_MORT and TIM8_MORT.
rajathr 0:34ee385f4d2d 2551 *
rajathr 0:34ee385f4d2d 2552 * @retval None
rajathr 0:34ee385f4d2d 2553 */
rajathr 0:34ee385f4d2d 2554 void TIM_ClearITPendingBit_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT)
rajathr 0:34ee385f4d2d 2555 {
rajathr 0:34ee385f4d2d 2556 /* Check the parameters */
rajathr 0:34ee385f4d2d 2557 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2558
rajathr 0:34ee385f4d2d 2559 /* Clear the IT pending Bit */
rajathr 0:34ee385f4d2d 2560 TIMx->SR = (uint16_t)~TIM_IT;
rajathr 0:34ee385f4d2d 2561 }
rajathr 0:34ee385f4d2d 2562
rajathr 0:34ee385f4d2d 2563 /**
rajathr 0:34ee385f4d2d 2564 * @brief Configures the TIMx's DMA interface.
rajathr 0:34ee385f4d2d 2565 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2566 * @param TIM_DMABase: DMA Base address.
rajathr 0:34ee385f4d2d 2567 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2568 * @arg TIM_DMABase_CR1_MORT
rajathr 0:34ee385f4d2d 2569 * @arg TIM_DMABase_CR2_MORT
rajathr 0:34ee385f4d2d 2570 * @arg TIM_DMABase_SMCR_MORT
rajathr 0:34ee385f4d2d 2571 * @arg TIM_DMABase_DIER_MORT
rajathr 0:34ee385f4d2d 2572 * @arg TIM1_DMABase_SR
rajathr 0:34ee385f4d2d 2573 * @arg TIM_DMABase_EGR_MORT
rajathr 0:34ee385f4d2d 2574 * @arg TIM_DMABase_CCMR1_MORT
rajathr 0:34ee385f4d2d 2575 * @arg TIM_DMABase_CCMR2_MORT
rajathr 0:34ee385f4d2d 2576 * @arg TIM_DMABase_CCER_MORT
rajathr 0:34ee385f4d2d 2577 * @arg TIM_DMABase_CNT_MORT
rajathr 0:34ee385f4d2d 2578 * @arg TIM_DMABase_PSC_MORT
rajathr 0:34ee385f4d2d 2579 * @arg TIM_DMABase_ARR
rajathr 0:34ee385f4d2d 2580 * @arg TIM_DMABase_RCR_MORT
rajathr 0:34ee385f4d2d 2581 * @arg TIM_DMABase_CCR1_MORT
rajathr 0:34ee385f4d2d 2582 * @arg TIM_DMABase_CCR2_MORT
rajathr 0:34ee385f4d2d 2583 * @arg TIM_DMABase_CCR3_MORT
rajathr 0:34ee385f4d2d 2584 * @arg TIM_DMABase_CCR4_MORT
rajathr 0:34ee385f4d2d 2585 * @arg TIM_DMABase_BDTR_MORT
rajathr 0:34ee385f4d2d 2586 * @arg TIM_DMABase_DCR_MORT
rajathr 0:34ee385f4d2d 2587 * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value
rajathr 0:34ee385f4d2d 2588 * between: TIM_DMABurstLength_1Transfer_MORT and TIM_DMABurstLength_18Transfers_MORT.
rajathr 0:34ee385f4d2d 2589 * @retval None
rajathr 0:34ee385f4d2d 2590 */
rajathr 0:34ee385f4d2d 2591 void TIM_DMAConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
rajathr 0:34ee385f4d2d 2592 {
rajathr 0:34ee385f4d2d 2593 /* Check the parameters */
rajathr 0:34ee385f4d2d 2594 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2595 assert_param(IS_TIM_DMA_BASE_MORT(TIM_DMABase));
rajathr 0:34ee385f4d2d 2596 assert_param(IS_TIM_DMA_LENGTH_MORT(TIM_DMABurstLength));
rajathr 0:34ee385f4d2d 2597
rajathr 0:34ee385f4d2d 2598 /* Set the DMA Base and the DMA Burst Length */
rajathr 0:34ee385f4d2d 2599 TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
rajathr 0:34ee385f4d2d 2600 }
rajathr 0:34ee385f4d2d 2601
rajathr 0:34ee385f4d2d 2602 /**
rajathr 0:34ee385f4d2d 2603 * @brief Enables or disables the TIMx's DMA Requests.
rajathr 0:34ee385f4d2d 2604 * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2605 * @param TIM_DMASource: specifies the DMA Request sources.
rajathr 0:34ee385f4d2d 2606 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2607 * @arg TIM_DMA_Update_MORT: TIM update Interrupt source
rajathr 0:34ee385f4d2d 2608 * @arg TIM_DMA_CC1_MORT: TIM Capture Compare 1 DMA source
rajathr 0:34ee385f4d2d 2609 * @arg TIM_DMA_CC2_MORT: TIM Capture Compare 2 DMA source
rajathr 0:34ee385f4d2d 2610 * @arg TIM_DMA_CC3_MORT: TIM Capture Compare 3 DMA source
rajathr 0:34ee385f4d2d 2611 * @arg TIM_DMA_CC4_MORT: TIM Capture Compare 4 DMA source
rajathr 0:34ee385f4d2d 2612 * @arg TIM_DMA_COM_MORT: TIM Commutation DMA source
rajathr 0:34ee385f4d2d 2613 * @arg TIM_DMA_Trigger_MORT: TIM Trigger DMA source
rajathr 0:34ee385f4d2d 2614 * @param NewState: new state of the DMA Request sources.
rajathr 0:34ee385f4d2d 2615 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2616 * @retval None
rajathr 0:34ee385f4d2d 2617 */
rajathr 0:34ee385f4d2d 2618 void TIM_DMACmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2619 {
rajathr 0:34ee385f4d2d 2620 /* Check the parameters */
rajathr 0:34ee385f4d2d 2621 assert_param(IS_TIM_LIST5_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2622 assert_param(IS_TIM_DMA_SOURCE_MORT(TIM_DMASource));
rajathr 0:34ee385f4d2d 2623 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2624
rajathr 0:34ee385f4d2d 2625 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2626 {
rajathr 0:34ee385f4d2d 2627 /* Enable the DMA sources */
rajathr 0:34ee385f4d2d 2628 TIMx->DIER |= TIM_DMASource;
rajathr 0:34ee385f4d2d 2629 }
rajathr 0:34ee385f4d2d 2630 else
rajathr 0:34ee385f4d2d 2631 {
rajathr 0:34ee385f4d2d 2632 /* Disable the DMA sources */
rajathr 0:34ee385f4d2d 2633 TIMx->DIER &= (uint16_t)~TIM_DMASource;
rajathr 0:34ee385f4d2d 2634 }
rajathr 0:34ee385f4d2d 2635 }
rajathr 0:34ee385f4d2d 2636
rajathr 0:34ee385f4d2d 2637 /**
rajathr 0:34ee385f4d2d 2638 * @brief Selects the TIMx peripheral Capture Compare DMA source.
rajathr 0:34ee385f4d2d 2639 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2640 * @param NewState: new state of the Capture Compare DMA source
rajathr 0:34ee385f4d2d 2641 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2642 * @retval None
rajathr 0:34ee385f4d2d 2643 */
rajathr 0:34ee385f4d2d 2644 void TIM_SelectCCDMA_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2645 {
rajathr 0:34ee385f4d2d 2646 /* Check the parameters */
rajathr 0:34ee385f4d2d 2647 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2648 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2649
rajathr 0:34ee385f4d2d 2650 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2651 {
rajathr 0:34ee385f4d2d 2652 /* Set the CCDS Bit */
rajathr 0:34ee385f4d2d 2653 TIMx->CR2 |= TIM_CR2_CCDS_MORT;
rajathr 0:34ee385f4d2d 2654 }
rajathr 0:34ee385f4d2d 2655 else
rajathr 0:34ee385f4d2d 2656 {
rajathr 0:34ee385f4d2d 2657 /* Reset the CCDS Bit */
rajathr 0:34ee385f4d2d 2658 TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS_MORT;
rajathr 0:34ee385f4d2d 2659 }
rajathr 0:34ee385f4d2d 2660 }
rajathr 0:34ee385f4d2d 2661 /**
rajathr 0:34ee385f4d2d 2662 * @}
rajathr 0:34ee385f4d2d 2663 */
rajathr 0:34ee385f4d2d 2664
rajathr 0:34ee385f4d2d 2665 /** @defgroup TIM_Group6 Clocks management functions
rajathr 0:34ee385f4d2d 2666 * @brief Clocks management functions
rajathr 0:34ee385f4d2d 2667 *
rajathr 0:34ee385f4d2d 2668 @verbatim
rajathr 0:34ee385f4d2d 2669 ===============================================================================
rajathr 0:34ee385f4d2d 2670 ##### Clocks management functions #####
rajathr 0:34ee385f4d2d 2671 ===============================================================================
rajathr 0:34ee385f4d2d 2672
rajathr 0:34ee385f4d2d 2673 @endverbatim
rajathr 0:34ee385f4d2d 2674 * @{
rajathr 0:34ee385f4d2d 2675 */
rajathr 0:34ee385f4d2d 2676
rajathr 0:34ee385f4d2d 2677 /**
rajathr 0:34ee385f4d2d 2678 * @brief Configures the TIMx internal Clock
rajathr 0:34ee385f4d2d 2679 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
rajathr 0:34ee385f4d2d 2680 * peripheral.
rajathr 0:34ee385f4d2d 2681 * @retval None
rajathr 0:34ee385f4d2d 2682 */
rajathr 0:34ee385f4d2d 2683 void TIM_InternalClockConfig_mort(TIM_TypeDef_mort* TIMx)
rajathr 0:34ee385f4d2d 2684 {
rajathr 0:34ee385f4d2d 2685 /* Check the parameters */
rajathr 0:34ee385f4d2d 2686 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2687
rajathr 0:34ee385f4d2d 2688 /* Disable slave mode to clock the prescaler directly with the internal clock */
rajathr 0:34ee385f4d2d 2689 TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS_MORT;
rajathr 0:34ee385f4d2d 2690 }
rajathr 0:34ee385f4d2d 2691
rajathr 0:34ee385f4d2d 2692 /**
rajathr 0:34ee385f4d2d 2693 * @brief Configures the TIMx Internal Trigger as External Clock
rajathr 0:34ee385f4d2d 2694 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
rajathr 0:34ee385f4d2d 2695 * peripheral.
rajathr 0:34ee385f4d2d 2696 * @param TIM_InputTriggerSource: Trigger source.
rajathr 0:34ee385f4d2d 2697 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2698 * @arg TIM_TS_ITR0_MORT: Internal Trigger 0
rajathr 0:34ee385f4d2d 2699 * @arg TIM_TS_ITR1_MORT: Internal Trigger 1
rajathr 0:34ee385f4d2d 2700 * @arg TIM_TS_ITR2_MORT: Internal Trigger 2
rajathr 0:34ee385f4d2d 2701 * @arg TIM_TS_ITR3_MORT: Internal Trigger 3
rajathr 0:34ee385f4d2d 2702 * @retval None
rajathr 0:34ee385f4d2d 2703 */
rajathr 0:34ee385f4d2d 2704 void TIM_ITRxExternalClockConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource)
rajathr 0:34ee385f4d2d 2705 {
rajathr 0:34ee385f4d2d 2706 /* Check the parameters */
rajathr 0:34ee385f4d2d 2707 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2708 assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION_MORT(TIM_InputTriggerSource));
rajathr 0:34ee385f4d2d 2709
rajathr 0:34ee385f4d2d 2710 /* Select the Internal Trigger */
rajathr 0:34ee385f4d2d 2711 TIM_SelectInputTrigger_mort(TIMx, TIM_InputTriggerSource);
rajathr 0:34ee385f4d2d 2712
rajathr 0:34ee385f4d2d 2713 /* Select the External clock mode1 */
rajathr 0:34ee385f4d2d 2714 TIMx->SMCR |= TIM_SlaveMode_External1_MORT;
rajathr 0:34ee385f4d2d 2715 }
rajathr 0:34ee385f4d2d 2716
rajathr 0:34ee385f4d2d 2717 /**
rajathr 0:34ee385f4d2d 2718 * @brief Configures the TIMx Trigger as External Clock
rajathr 0:34ee385f4d2d 2719 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
rajathr 0:34ee385f4d2d 2720 * to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2721 * @param TIM_TIxExternalCLKSource: Trigger source.
rajathr 0:34ee385f4d2d 2722 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2723 * @arg TIM_TIxExternalCLK1Source_TI1ED_MORT: TI1 Edge Detector
rajathr 0:34ee385f4d2d 2724 * @arg TIM_TIxExternalCLK1Source_TI1_MORT: Filtered Timer Input 1
rajathr 0:34ee385f4d2d 2725 * @arg TIM_TIxExternalCLK1Source_TI2_MORT: Filtered Timer Input 2
rajathr 0:34ee385f4d2d 2726 * @param TIM_ICPolarity: specifies the TIx Polarity.
rajathr 0:34ee385f4d2d 2727 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2728 * @arg TIM_ICPolarity_Rising_MORT
rajathr 0:34ee385f4d2d 2729 * @arg TIM_ICPolarity_Falling_MORT
rajathr 0:34ee385f4d2d 2730 * @param ICFilter: specifies the filter value.
rajathr 0:34ee385f4d2d 2731 * This parameter must be a value between 0x0 and 0xF.
rajathr 0:34ee385f4d2d 2732 * @retval None
rajathr 0:34ee385f4d2d 2733 */
rajathr 0:34ee385f4d2d 2734 void TIM_TIxExternalClockConfig(TIM_TypeDef_mort* TIMx, uint16_t TIM_TIxExternalCLKSource,
rajathr 0:34ee385f4d2d 2735 uint16_t TIM_ICPolarity, uint16_t ICFilter)
rajathr 0:34ee385f4d2d 2736 {
rajathr 0:34ee385f4d2d 2737 /* Check the parameters */
rajathr 0:34ee385f4d2d 2738 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2739 assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
rajathr 0:34ee385f4d2d 2740 assert_param(IS_TIM_IC_FILTER_MORT(ICFilter));
rajathr 0:34ee385f4d2d 2741
rajathr 0:34ee385f4d2d 2742 /* Configure the Timer Input Clock Source */
rajathr 0:34ee385f4d2d 2743 if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2_MORT)
rajathr 0:34ee385f4d2d 2744 {
rajathr 0:34ee385f4d2d 2745 TI2_Config_mort(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI_MORT, ICFilter);
rajathr 0:34ee385f4d2d 2746 }
rajathr 0:34ee385f4d2d 2747 else
rajathr 0:34ee385f4d2d 2748 {
rajathr 0:34ee385f4d2d 2749 TI1_Config_mort(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI_MORT, ICFilter);
rajathr 0:34ee385f4d2d 2750 }
rajathr 0:34ee385f4d2d 2751 /* Select the Trigger source */
rajathr 0:34ee385f4d2d 2752 TIM_SelectInputTrigger_mort(TIMx, TIM_TIxExternalCLKSource);
rajathr 0:34ee385f4d2d 2753 /* Select the External clock mode1 */
rajathr 0:34ee385f4d2d 2754 TIMx->SMCR |= TIM_SlaveMode_External1_MORT;
rajathr 0:34ee385f4d2d 2755 }
rajathr 0:34ee385f4d2d 2756
rajathr 0:34ee385f4d2d 2757 /**
rajathr 0:34ee385f4d2d 2758 * @brief Configures the External clock Mode1
rajathr 0:34ee385f4d2d 2759 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2760 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
rajathr 0:34ee385f4d2d 2761 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2762 * @arg TIM_ExtTRGPSC_OFF_MORT: ETRP Prescaler OFF.
rajathr 0:34ee385f4d2d 2763 * @arg TIM_ExtTRGPSC_DIV2_MORT: ETRP frequency divided by 2.
rajathr 0:34ee385f4d2d 2764 * @arg TIM_ExtTRGPSC_DIV4_MORT: ETRP frequency divided by 4.
rajathr 0:34ee385f4d2d 2765 * @arg TIM_ExtTRGPSC_DIV8_MORT: ETRP frequency divided by 8.
rajathr 0:34ee385f4d2d 2766 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
rajathr 0:34ee385f4d2d 2767 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2768 * @arg TIM_ExtTRGPolarity_Inverted_MORT: active low or falling edge active.
rajathr 0:34ee385f4d2d 2769 * @arg TIM_ExtTRGPolarity_NonInverted_MORT: active high or rising edge active.
rajathr 0:34ee385f4d2d 2770 * @param ExtTRGFilter: External Trigger Filter.
rajathr 0:34ee385f4d2d 2771 * This parameter must be a value between 0x00 and 0x0F
rajathr 0:34ee385f4d2d 2772 * @retval None
rajathr 0:34ee385f4d2d 2773 */
rajathr 0:34ee385f4d2d 2774 void TIM_ETRClockMode1Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler,
rajathr 0:34ee385f4d2d 2775 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
rajathr 0:34ee385f4d2d 2776 {
rajathr 0:34ee385f4d2d 2777 uint16_t tmpsmcr = 0;
rajathr 0:34ee385f4d2d 2778
rajathr 0:34ee385f4d2d 2779 /* Check the parameters */
rajathr 0:34ee385f4d2d 2780 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2781 assert_param(IS_TIM_EXT_PRESCALER_MORT(TIM_ExtTRGPrescaler));
rajathr 0:34ee385f4d2d 2782 assert_param(IS_TIM_EXT_POLARITY_MORT(TIM_ExtTRGPolarity));
rajathr 0:34ee385f4d2d 2783 assert_param(IS_TIM_EXT_FILTER_MORT(ExtTRGFilter));
rajathr 0:34ee385f4d2d 2784 /* Configure the ETR Clock source */
rajathr 0:34ee385f4d2d 2785 TIM_ETRConfig_mort(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
rajathr 0:34ee385f4d2d 2786
rajathr 0:34ee385f4d2d 2787 /* Get the TIMx SMCR register value */
rajathr 0:34ee385f4d2d 2788 tmpsmcr = TIMx->SMCR;
rajathr 0:34ee385f4d2d 2789
rajathr 0:34ee385f4d2d 2790 /* Reset the SMS Bits */
rajathr 0:34ee385f4d2d 2791 tmpsmcr &= (uint16_t)~TIM_SMCR_SMS_MORT;
rajathr 0:34ee385f4d2d 2792
rajathr 0:34ee385f4d2d 2793 /* Select the External clock mode1 */
rajathr 0:34ee385f4d2d 2794 tmpsmcr |= TIM_SlaveMode_External1_MORT;
rajathr 0:34ee385f4d2d 2795
rajathr 0:34ee385f4d2d 2796 /* Select the Trigger selection : ETRF */
rajathr 0:34ee385f4d2d 2797 tmpsmcr &= (uint16_t)~TIM_SMCR_TS_MORT;
rajathr 0:34ee385f4d2d 2798 tmpsmcr |= TIM_TS_ETRF_MORT;
rajathr 0:34ee385f4d2d 2799
rajathr 0:34ee385f4d2d 2800 /* Write to TIMx SMCR */
rajathr 0:34ee385f4d2d 2801 TIMx->SMCR = tmpsmcr;
rajathr 0:34ee385f4d2d 2802 }
rajathr 0:34ee385f4d2d 2803
rajathr 0:34ee385f4d2d 2804 /**
rajathr 0:34ee385f4d2d 2805 * @brief Configures the External clock Mode2
rajathr 0:34ee385f4d2d 2806 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2807 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
rajathr 0:34ee385f4d2d 2808 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2809 * @arg TIM_ExtTRGPSC_OFF_MORT: ETRP Prescaler OFF.
rajathr 0:34ee385f4d2d 2810 * @arg TIM_ExtTRGPSC_DIV2_MORT: ETRP frequency divided by 2.
rajathr 0:34ee385f4d2d 2811 * @arg TIM_ExtTRGPSC_DIV4_MORT: ETRP frequency divided by 4.
rajathr 0:34ee385f4d2d 2812 * @arg TIM_ExtTRGPSC_DIV8_MORT: ETRP frequency divided by 8.
rajathr 0:34ee385f4d2d 2813 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
rajathr 0:34ee385f4d2d 2814 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2815 * @arg TIM_ExtTRGPolarity_Inverted_MORT: active low or falling edge active.
rajathr 0:34ee385f4d2d 2816 * @arg TIM_ExtTRGPolarity_NonInverted_MORT: active high or rising edge active.
rajathr 0:34ee385f4d2d 2817 * @param ExtTRGFilter: External Trigger Filter.
rajathr 0:34ee385f4d2d 2818 * This parameter must be a value between 0x00 and 0x0F
rajathr 0:34ee385f4d2d 2819 * @retval None
rajathr 0:34ee385f4d2d 2820 */
rajathr 0:34ee385f4d2d 2821 void TIM_ETRClockMode2Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler,
rajathr 0:34ee385f4d2d 2822 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
rajathr 0:34ee385f4d2d 2823 {
rajathr 0:34ee385f4d2d 2824 /* Check the parameters */
rajathr 0:34ee385f4d2d 2825 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2826 assert_param(IS_TIM_EXT_PRESCALER_MORT(TIM_ExtTRGPrescaler));
rajathr 0:34ee385f4d2d 2827 assert_param(IS_TIM_EXT_POLARITY_MORT(TIM_ExtTRGPolarity));
rajathr 0:34ee385f4d2d 2828 assert_param(IS_TIM_EXT_FILTER_MORT(ExtTRGFilter));
rajathr 0:34ee385f4d2d 2829
rajathr 0:34ee385f4d2d 2830 /* Configure the ETR Clock source */
rajathr 0:34ee385f4d2d 2831 TIM_ETRConfig_mort(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
rajathr 0:34ee385f4d2d 2832
rajathr 0:34ee385f4d2d 2833 /* Enable the External clock mode2 */
rajathr 0:34ee385f4d2d 2834 TIMx->SMCR |= TIM_SMCR_ECE_MORT;
rajathr 0:34ee385f4d2d 2835 }
rajathr 0:34ee385f4d2d 2836 /**
rajathr 0:34ee385f4d2d 2837 * @}
rajathr 0:34ee385f4d2d 2838 */
rajathr 0:34ee385f4d2d 2839
rajathr 0:34ee385f4d2d 2840 /** @defgroup TIM_Group7 Synchronization management functions
rajathr 0:34ee385f4d2d 2841 * @brief Synchronization management functions
rajathr 0:34ee385f4d2d 2842 *
rajathr 0:34ee385f4d2d 2843 @verbatim
rajathr 0:34ee385f4d2d 2844 ===============================================================================
rajathr 0:34ee385f4d2d 2845 ##### Synchronization management functions #####
rajathr 0:34ee385f4d2d 2846 ===============================================================================
rajathr 0:34ee385f4d2d 2847
rajathr 0:34ee385f4d2d 2848 ##### TIM Driver: how to use it in synchronization Mode #####
rajathr 0:34ee385f4d2d 2849 ===============================================================================
rajathr 0:34ee385f4d2d 2850 [..]
rajathr 0:34ee385f4d2d 2851
rajathr 0:34ee385f4d2d 2852 *** Case of two/several Timers ***
rajathr 0:34ee385f4d2d 2853 ==================================
rajathr 0:34ee385f4d2d 2854 [..]
rajathr 0:34ee385f4d2d 2855 (#) Configure the Master Timers using the following functions:
rajathr 0:34ee385f4d2d 2856 (++) void TIM_SelectOutputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_TRGOSource);
rajathr 0:34ee385f4d2d 2857 (++) void TIM_SelectMasterSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_MasterSlaveMode);
rajathr 0:34ee385f4d2d 2858 (#) Configure the Slave Timers using the following functions:
rajathr 0:34ee385f4d2d 2859 (++) void TIM_SelectInputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource);
rajathr 0:34ee385f4d2d 2860 (++) void TIM_SelectSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_SlaveMode);
rajathr 0:34ee385f4d2d 2861
rajathr 0:34ee385f4d2d 2862 *** Case of Timers and external trigger(ETR pin) ***
rajathr 0:34ee385f4d2d 2863 ====================================================
rajathr 0:34ee385f4d2d 2864 [..]
rajathr 0:34ee385f4d2d 2865 (#) Configure the External trigger using this function:
rajathr 0:34ee385f4d2d 2866 (++) void TIM_ETRConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
rajathr 0:34ee385f4d2d 2867 uint16_t ExtTRGFilter);
rajathr 0:34ee385f4d2d 2868 (#) Configure the Slave Timers using the following functions:
rajathr 0:34ee385f4d2d 2869 (++) void TIM_SelectInputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource);
rajathr 0:34ee385f4d2d 2870 (++) void TIM_SelectSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_SlaveMode);
rajathr 0:34ee385f4d2d 2871
rajathr 0:34ee385f4d2d 2872 @endverbatim
rajathr 0:34ee385f4d2d 2873 * @{
rajathr 0:34ee385f4d2d 2874 */
rajathr 0:34ee385f4d2d 2875
rajathr 0:34ee385f4d2d 2876 /**
rajathr 0:34ee385f4d2d 2877 * @brief Selects the Input Trigger source
rajathr 0:34ee385f4d2d 2878 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
rajathr 0:34ee385f4d2d 2879 * to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2880 * @param TIM_InputTriggerSource: The Input Trigger source.
rajathr 0:34ee385f4d2d 2881 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2882 * @arg TIM_TS_ITR0_MORT: Internal Trigger 0
rajathr 0:34ee385f4d2d 2883 * @arg TIM_TS_ITR1_MORT: Internal Trigger 1
rajathr 0:34ee385f4d2d 2884 * @arg TIM_TS_ITR2_MORT: Internal Trigger 2
rajathr 0:34ee385f4d2d 2885 * @arg TIM_TS_ITR3_MORT: Internal Trigger 3
rajathr 0:34ee385f4d2d 2886 * @arg TIM_TS_TI1F_ED_MORT: TI1 Edge Detector
rajathr 0:34ee385f4d2d 2887 * @arg TIM_TS_TI1FP1_MORT: Filtered Timer Input 1
rajathr 0:34ee385f4d2d 2888 * @arg TIM_TS_TI2FP2_MORT: Filtered Timer Input 2
rajathr 0:34ee385f4d2d 2889 * @arg TIM_TS_ETRF_MORT: External Trigger input
rajathr 0:34ee385f4d2d 2890 * @retval None
rajathr 0:34ee385f4d2d 2891 */
rajathr 0:34ee385f4d2d 2892 void TIM_SelectInputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource)
rajathr 0:34ee385f4d2d 2893 {
rajathr 0:34ee385f4d2d 2894 uint16_t tmpsmcr = 0;
rajathr 0:34ee385f4d2d 2895
rajathr 0:34ee385f4d2d 2896 /* Check the parameters */
rajathr 0:34ee385f4d2d 2897 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2898 assert_param(IS_TIM_TRIGGER_SELECTION_MORT(TIM_InputTriggerSource));
rajathr 0:34ee385f4d2d 2899
rajathr 0:34ee385f4d2d 2900 /* Get the TIMx SMCR register value */
rajathr 0:34ee385f4d2d 2901 tmpsmcr = TIMx->SMCR;
rajathr 0:34ee385f4d2d 2902
rajathr 0:34ee385f4d2d 2903 /* Reset the TS Bits */
rajathr 0:34ee385f4d2d 2904 tmpsmcr &= (uint16_t)~TIM_SMCR_TS_MORT;
rajathr 0:34ee385f4d2d 2905
rajathr 0:34ee385f4d2d 2906 /* Set the Input Trigger source */
rajathr 0:34ee385f4d2d 2907 tmpsmcr |= TIM_InputTriggerSource;
rajathr 0:34ee385f4d2d 2908
rajathr 0:34ee385f4d2d 2909 /* Write to TIMx SMCR */
rajathr 0:34ee385f4d2d 2910 TIMx->SMCR = tmpsmcr;
rajathr 0:34ee385f4d2d 2911 }
rajathr 0:34ee385f4d2d 2912
rajathr 0:34ee385f4d2d 2913 /**
rajathr 0:34ee385f4d2d 2914 * @brief Selects the TIMx Trigger Output Mode.
rajathr 0:34ee385f4d2d 2915 * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2916 *
rajathr 0:34ee385f4d2d 2917 * @param TIM_TRGOSource: specifies the Trigger Output source.
rajathr 0:34ee385f4d2d 2918 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2919 *
rajathr 0:34ee385f4d2d 2920 * - For all TIMx
rajathr 0:34ee385f4d2d 2921 * @arg TIM_TRGOSource_Reset_MORT: The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
rajathr 0:34ee385f4d2d 2922 * @arg TIM_TRGOSource_Enable_MORT: The Counter Enable CEN is used as the trigger output(TRGO)
rajathr 0:34ee385f4d2d 2923 * @arg TIM_TRGOSource_Update_MORT: The update event is selected as the trigger output(TRGO)
rajathr 0:34ee385f4d2d 2924 *
rajathr 0:34ee385f4d2d 2925 * - For all TIMx except TIM6_MORT and TIM7_MORT
rajathr 0:34ee385f4d2d 2926 * @arg TIM_TRGOSource_OC1_MORT: The trigger output sends a positive pulse when the CC1IF flag
rajathr 0:34ee385f4d2d 2927 * is to be set, as soon as a capture or compare match occurs(TRGO)
rajathr 0:34ee385f4d2d 2928 * @arg TIM_TRGOSource_OC1Ref_MORT: OC1REF signal is used as the trigger output(TRGO)
rajathr 0:34ee385f4d2d 2929 * @arg TIM_TRGOSource_OC2Ref_MORT: OC2REF signal is used as the trigger output(TRGO)
rajathr 0:34ee385f4d2d 2930 * @arg TIM_TRGOSource_OC3Ref_MORT: OC3REF signal is used as the trigger output(TRGO)
rajathr 0:34ee385f4d2d 2931 * @arg TIM_TRGOSource_OC4Ref_MORT: OC4REF signal is used as the trigger output(TRGO)
rajathr 0:34ee385f4d2d 2932 *
rajathr 0:34ee385f4d2d 2933 * @retval None
rajathr 0:34ee385f4d2d 2934 */
rajathr 0:34ee385f4d2d 2935 void TIM_SelectOutputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_TRGOSource)
rajathr 0:34ee385f4d2d 2936 {
rajathr 0:34ee385f4d2d 2937 /* Check the parameters */
rajathr 0:34ee385f4d2d 2938 assert_param(IS_TIM_LIST5_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2939 assert_param(IS_TIM_TRGO_SOURCE_MORT(TIM_TRGOSource));
rajathr 0:34ee385f4d2d 2940
rajathr 0:34ee385f4d2d 2941 /* Reset the MMS Bits */
rajathr 0:34ee385f4d2d 2942 TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS_MORT;
rajathr 0:34ee385f4d2d 2943 /* Select the TRGO source */
rajathr 0:34ee385f4d2d 2944 TIMx->CR2 |= TIM_TRGOSource;
rajathr 0:34ee385f4d2d 2945 }
rajathr 0:34ee385f4d2d 2946
rajathr 0:34ee385f4d2d 2947 /**
rajathr 0:34ee385f4d2d 2948 * @brief Selects the TIMx Slave Mode.
rajathr 0:34ee385f4d2d 2949 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2950 * @param TIM_SlaveMode: specifies the Timer Slave Mode.
rajathr 0:34ee385f4d2d 2951 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2952 * @arg TIM_SlaveMode_Reset_MORT: Rising edge of the selected trigger signal(TRGI) reinitialize
rajathr 0:34ee385f4d2d 2953 * the counter and triggers an update of the registers
rajathr 0:34ee385f4d2d 2954 * @arg TIM_SlaveMode_Gated_MORT: The counter clock is enabled when the trigger signal (TRGI) is high
rajathr 0:34ee385f4d2d 2955 * @arg TIM_SlaveMode_Trigger_MORT: The counter starts at a rising edge of the trigger TRGI
rajathr 0:34ee385f4d2d 2956 * @arg TIM_SlaveMode_External1_MORT: Rising edges of the selected trigger (TRGI) clock the counter
rajathr 0:34ee385f4d2d 2957 * @retval None
rajathr 0:34ee385f4d2d 2958 */
rajathr 0:34ee385f4d2d 2959 void TIM_SelectSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_SlaveMode)
rajathr 0:34ee385f4d2d 2960 {
rajathr 0:34ee385f4d2d 2961 /* Check the parameters */
rajathr 0:34ee385f4d2d 2962 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2963 assert_param(IS_TIM_SLAVE_MODE_MORT(TIM_SlaveMode));
rajathr 0:34ee385f4d2d 2964
rajathr 0:34ee385f4d2d 2965 /* Reset the SMS Bits */
rajathr 0:34ee385f4d2d 2966 TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS_MORT;
rajathr 0:34ee385f4d2d 2967
rajathr 0:34ee385f4d2d 2968 /* Select the Slave Mode */
rajathr 0:34ee385f4d2d 2969 TIMx->SMCR |= TIM_SlaveMode;
rajathr 0:34ee385f4d2d 2970 }
rajathr 0:34ee385f4d2d 2971
rajathr 0:34ee385f4d2d 2972 /**
rajathr 0:34ee385f4d2d 2973 * @brief Sets or Resets the TIMx Master/Slave Mode.
rajathr 0:34ee385f4d2d 2974 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2975 * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
rajathr 0:34ee385f4d2d 2976 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2977 * @arg TIM_MasterSlaveMode_Enable_MORT: synchronization between the current timer
rajathr 0:34ee385f4d2d 2978 * and its slaves (through TRGO)
rajathr 0:34ee385f4d2d 2979 * @arg TIM_MasterSlaveMode_Disable_MORT: No action
rajathr 0:34ee385f4d2d 2980 * @retval None
rajathr 0:34ee385f4d2d 2981 */
rajathr 0:34ee385f4d2d 2982 void TIM_SelectMasterSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_MasterSlaveMode)
rajathr 0:34ee385f4d2d 2983 {
rajathr 0:34ee385f4d2d 2984 /* Check the parameters */
rajathr 0:34ee385f4d2d 2985 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 2986 assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
rajathr 0:34ee385f4d2d 2987
rajathr 0:34ee385f4d2d 2988 /* Reset the MSM Bit */
rajathr 0:34ee385f4d2d 2989 TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM_MORT;
rajathr 0:34ee385f4d2d 2990
rajathr 0:34ee385f4d2d 2991 /* Set or Reset the MSM Bit */
rajathr 0:34ee385f4d2d 2992 TIMx->SMCR |= TIM_MasterSlaveMode;
rajathr 0:34ee385f4d2d 2993 }
rajathr 0:34ee385f4d2d 2994
rajathr 0:34ee385f4d2d 2995 /**
rajathr 0:34ee385f4d2d 2996 * @brief Configures the TIMx External Trigger (ETR).
rajathr 0:34ee385f4d2d 2997 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 2998 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
rajathr 0:34ee385f4d2d 2999 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3000 * @arg TIM_ExtTRGPSC_OFF_MORT: ETRP Prescaler OFF.
rajathr 0:34ee385f4d2d 3001 * @arg TIM_ExtTRGPSC_DIV2_MORT: ETRP frequency divided by 2.
rajathr 0:34ee385f4d2d 3002 * @arg TIM_ExtTRGPSC_DIV4_MORT: ETRP frequency divided by 4.
rajathr 0:34ee385f4d2d 3003 * @arg TIM_ExtTRGPSC_DIV8_MORT: ETRP frequency divided by 8.
rajathr 0:34ee385f4d2d 3004 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
rajathr 0:34ee385f4d2d 3005 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3006 * @arg TIM_ExtTRGPolarity_Inverted_MORT: active low or falling edge active.
rajathr 0:34ee385f4d2d 3007 * @arg TIM_ExtTRGPolarity_NonInverted_MORT: active high or rising edge active.
rajathr 0:34ee385f4d2d 3008 * @param ExtTRGFilter: External Trigger Filter.
rajathr 0:34ee385f4d2d 3009 * This parameter must be a value between 0x00 and 0x0F
rajathr 0:34ee385f4d2d 3010 * @retval None
rajathr 0:34ee385f4d2d 3011 */
rajathr 0:34ee385f4d2d 3012 void TIM_ETRConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler,
rajathr 0:34ee385f4d2d 3013 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
rajathr 0:34ee385f4d2d 3014 {
rajathr 0:34ee385f4d2d 3015 uint16_t tmpsmcr = 0;
rajathr 0:34ee385f4d2d 3016
rajathr 0:34ee385f4d2d 3017 /* Check the parameters */
rajathr 0:34ee385f4d2d 3018 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 3019 assert_param(IS_TIM_EXT_PRESCALER_MORT(TIM_ExtTRGPrescaler));
rajathr 0:34ee385f4d2d 3020 assert_param(IS_TIM_EXT_POLARITY_MORT(TIM_ExtTRGPolarity));
rajathr 0:34ee385f4d2d 3021 assert_param(IS_TIM_EXT_FILTER_MORT(ExtTRGFilter));
rajathr 0:34ee385f4d2d 3022
rajathr 0:34ee385f4d2d 3023 tmpsmcr = TIMx->SMCR;
rajathr 0:34ee385f4d2d 3024
rajathr 0:34ee385f4d2d 3025 /* Reset the ETR Bits */
rajathr 0:34ee385f4d2d 3026 tmpsmcr &= SMCR_ETR_MASK_MORT;
rajathr 0:34ee385f4d2d 3027
rajathr 0:34ee385f4d2d 3028 /* Set the Prescaler, the Filter value and the Polarity */
rajathr 0:34ee385f4d2d 3029 tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
rajathr 0:34ee385f4d2d 3030
rajathr 0:34ee385f4d2d 3031 /* Write to TIMx SMCR */
rajathr 0:34ee385f4d2d 3032 TIMx->SMCR = tmpsmcr;
rajathr 0:34ee385f4d2d 3033 }
rajathr 0:34ee385f4d2d 3034 /**
rajathr 0:34ee385f4d2d 3035 * @}
rajathr 0:34ee385f4d2d 3036 */
rajathr 0:34ee385f4d2d 3037
rajathr 0:34ee385f4d2d 3038 /** @defgroup TIM_Group8 Specific interface management functions
rajathr 0:34ee385f4d2d 3039 * @brief Specific interface management functions
rajathr 0:34ee385f4d2d 3040 *
rajathr 0:34ee385f4d2d 3041 @verbatim
rajathr 0:34ee385f4d2d 3042 ===============================================================================
rajathr 0:34ee385f4d2d 3043 ##### Specific interface management functions #####
rajathr 0:34ee385f4d2d 3044 ===============================================================================
rajathr 0:34ee385f4d2d 3045
rajathr 0:34ee385f4d2d 3046 @endverbatim
rajathr 0:34ee385f4d2d 3047 * @{
rajathr 0:34ee385f4d2d 3048 */
rajathr 0:34ee385f4d2d 3049
rajathr 0:34ee385f4d2d 3050 /**
rajathr 0:34ee385f4d2d 3051 * @brief Configures the TIMx Encoder Interface.
rajathr 0:34ee385f4d2d 3052 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
rajathr 0:34ee385f4d2d 3053 * peripheral.
rajathr 0:34ee385f4d2d 3054 * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
rajathr 0:34ee385f4d2d 3055 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3056 * @arg TIM_EncoderMode_TI1_MORT: Counter counts on TI1FP1 edge depending on TI2FP2 level.
rajathr 0:34ee385f4d2d 3057 * @arg TIM_EncoderMode_TI2_MORT: Counter counts on TI2FP2 edge depending on TI1FP1 level.
rajathr 0:34ee385f4d2d 3058 * @arg TIM_EncoderMode_TI12_MORT: Counter counts on both TI1FP1 and TI2FP2 edges depending
rajathr 0:34ee385f4d2d 3059 * on the level of the other input.
rajathr 0:34ee385f4d2d 3060 * @param TIM_IC1Polarity: specifies the IC1 Polarity
rajathr 0:34ee385f4d2d 3061 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3062 * @arg TIM_ICPolarity_Falling_MORT: IC Falling edge.
rajathr 0:34ee385f4d2d 3063 * @arg TIM_ICPolarity_Rising_MORT: IC Rising edge.
rajathr 0:34ee385f4d2d 3064 * @param TIM_IC2Polarity: specifies the IC2 Polarity
rajathr 0:34ee385f4d2d 3065 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3066 * @arg TIM_ICPolarity_Falling_MORT: IC Falling edge.
rajathr 0:34ee385f4d2d 3067 * @arg TIM_ICPolarity_Rising_MORT: IC Rising edge.
rajathr 0:34ee385f4d2d 3068 * @retval None
rajathr 0:34ee385f4d2d 3069 */
rajathr 0:34ee385f4d2d 3070 void TIM_EncoderInterfaceConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_EncoderMode,
rajathr 0:34ee385f4d2d 3071 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
rajathr 0:34ee385f4d2d 3072 {
rajathr 0:34ee385f4d2d 3073 uint16_t tmpsmcr = 0;
rajathr 0:34ee385f4d2d 3074 uint16_t tmpccmr1 = 0;
rajathr 0:34ee385f4d2d 3075 uint16_t tmpccer = 0;
rajathr 0:34ee385f4d2d 3076
rajathr 0:34ee385f4d2d 3077 /* Check the parameters */
rajathr 0:34ee385f4d2d 3078 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 3079 assert_param(IS_TIM_ENCODER_MODE_MORT(TIM_EncoderMode));
rajathr 0:34ee385f4d2d 3080 assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
rajathr 0:34ee385f4d2d 3081 assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
rajathr 0:34ee385f4d2d 3082
rajathr 0:34ee385f4d2d 3083 /* Get the TIMx SMCR register value */
rajathr 0:34ee385f4d2d 3084 tmpsmcr = TIMx->SMCR;
rajathr 0:34ee385f4d2d 3085
rajathr 0:34ee385f4d2d 3086 /* Get the TIMx CCMR1 register value */
rajathr 0:34ee385f4d2d 3087 tmpccmr1 = TIMx->CCMR1;
rajathr 0:34ee385f4d2d 3088
rajathr 0:34ee385f4d2d 3089 /* Get the TIMx CCER register value */
rajathr 0:34ee385f4d2d 3090 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 3091
rajathr 0:34ee385f4d2d 3092 /* Set the encoder Mode */
rajathr 0:34ee385f4d2d 3093 tmpsmcr &= (uint16_t)~TIM_SMCR_SMS_MORT;
rajathr 0:34ee385f4d2d 3094 tmpsmcr |= TIM_EncoderMode;
rajathr 0:34ee385f4d2d 3095
rajathr 0:34ee385f4d2d 3096 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
rajathr 0:34ee385f4d2d 3097 tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S_MORT) & ((uint16_t)~TIM_CCMR1_CC2S_MORT);
rajathr 0:34ee385f4d2d 3098 tmpccmr1 |= TIM_CCMR1_CC1S_0_MORT | TIM_CCMR1_CC2S_0_MORT;
rajathr 0:34ee385f4d2d 3099
rajathr 0:34ee385f4d2d 3100 /* Set the TI1 and the TI2 Polarities */
rajathr 0:34ee385f4d2d 3101 tmpccer &= ((uint16_t)~TIM_CCER_CC1P_MORT) & ((uint16_t)~TIM_CCER_CC2P_MORT);
rajathr 0:34ee385f4d2d 3102 tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
rajathr 0:34ee385f4d2d 3103
rajathr 0:34ee385f4d2d 3104 /* Write to TIMx SMCR */
rajathr 0:34ee385f4d2d 3105 TIMx->SMCR = tmpsmcr;
rajathr 0:34ee385f4d2d 3106
rajathr 0:34ee385f4d2d 3107 /* Write to TIMx CCMR1 */
rajathr 0:34ee385f4d2d 3108 TIMx->CCMR1 = tmpccmr1;
rajathr 0:34ee385f4d2d 3109
rajathr 0:34ee385f4d2d 3110 /* Write to TIMx CCER */
rajathr 0:34ee385f4d2d 3111 TIMx->CCER = tmpccer;
rajathr 0:34ee385f4d2d 3112 }
rajathr 0:34ee385f4d2d 3113
rajathr 0:34ee385f4d2d 3114 /**
rajathr 0:34ee385f4d2d 3115 * @brief Enables or disables the TIMx's Hall sensor interface.
rajathr 0:34ee385f4d2d 3116 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
rajathr 0:34ee385f4d2d 3117 * peripheral.
rajathr 0:34ee385f4d2d 3118 * @param NewState: new state of the TIMx Hall sensor interface.
rajathr 0:34ee385f4d2d 3119 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 3120 * @retval None
rajathr 0:34ee385f4d2d 3121 */
rajathr 0:34ee385f4d2d 3122 void TIM_SelectHallSensor_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState)
rajathr 0:34ee385f4d2d 3123 {
rajathr 0:34ee385f4d2d 3124 /* Check the parameters */
rajathr 0:34ee385f4d2d 3125 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 3126 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 3127
rajathr 0:34ee385f4d2d 3128 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 3129 {
rajathr 0:34ee385f4d2d 3130 /* Set the TI1S Bit */
rajathr 0:34ee385f4d2d 3131 TIMx->CR2 |= TIM_CR2_TI1S_MORT;
rajathr 0:34ee385f4d2d 3132 }
rajathr 0:34ee385f4d2d 3133 else
rajathr 0:34ee385f4d2d 3134 {
rajathr 0:34ee385f4d2d 3135 /* Reset the TI1S Bit */
rajathr 0:34ee385f4d2d 3136 TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S_MORT;
rajathr 0:34ee385f4d2d 3137 }
rajathr 0:34ee385f4d2d 3138 }
rajathr 0:34ee385f4d2d 3139 /**
rajathr 0:34ee385f4d2d 3140 * @}
rajathr 0:34ee385f4d2d 3141 */
rajathr 0:34ee385f4d2d 3142
rajathr 0:34ee385f4d2d 3143 /** @defgroup TIM_Group9 Specific remapping management function
rajathr 0:34ee385f4d2d 3144 * @brief Specific remapping management function
rajathr 0:34ee385f4d2d 3145 *
rajathr 0:34ee385f4d2d 3146 @verbatim
rajathr 0:34ee385f4d2d 3147 ===============================================================================
rajathr 0:34ee385f4d2d 3148 ##### Specific remapping management function #####
rajathr 0:34ee385f4d2d 3149 ===============================================================================
rajathr 0:34ee385f4d2d 3150
rajathr 0:34ee385f4d2d 3151 @endverbatim
rajathr 0:34ee385f4d2d 3152 * @{
rajathr 0:34ee385f4d2d 3153 */
rajathr 0:34ee385f4d2d 3154
rajathr 0:34ee385f4d2d 3155 /**
rajathr 0:34ee385f4d2d 3156 * @brief Configures the TIM2_MORT, TIM5_MORT and TIM11_MORT Remapping input capabilities.
rajathr 0:34ee385f4d2d 3157 * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 3158 * @param TIM_Remap: specifies the TIM input remapping source.
rajathr 0:34ee385f4d2d 3159 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3160 * @arg TIM2_TIM8_TRGO: TIM2_MORT ITR1 input is connected to TIM8_MORT Trigger output(default)
rajathr 0:34ee385f4d2d 3161 * @arg TIM2_ETH_PTP_MORT: TIM2_MORT ITR1 input is connected to ETH PTP trigger output.
rajathr 0:34ee385f4d2d 3162 * @arg TIM2_USBFS_SOF_MORT: TIM2_MORT ITR1 input is connected to USB FS SOF.
rajathr 0:34ee385f4d2d 3163 * @arg TIM2_USBHS_SOF_MORT: TIM2_MORT ITR1 input is connected to USB HS SOF.
rajathr 0:34ee385f4d2d 3164 * @arg TIM5_GPIO: TIM5_MORT CH4 input is connected to dedicated Timer pin(default)
rajathr 0:34ee385f4d2d 3165 * @arg TIM5_LSI_MORT: TIM5_MORT CH4 input is connected to LSI clock.
rajathr 0:34ee385f4d2d 3166 * @arg TIM5_LSE_MORT: TIM5_MORT CH4 input is connected to LSE clock.
rajathr 0:34ee385f4d2d 3167 * @arg TIM5_RTC_MORT: TIM5_MORT CH4 input is connected to RTC Output event.
rajathr 0:34ee385f4d2d 3168 * @arg TIM11_GPIO_MORT: TIM11_MORT CH4 input is connected to dedicated Timer pin(default)
rajathr 0:34ee385f4d2d 3169 * @arg TIM11_HSE_MORT: TIM11_MORT CH4 input is connected to HSE_RTC clock
rajathr 0:34ee385f4d2d 3170 * (HSE divided by a programmable prescaler)
rajathr 0:34ee385f4d2d 3171 * @retval None
rajathr 0:34ee385f4d2d 3172 */
rajathr 0:34ee385f4d2d 3173 void TIM_RemapConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Remap)
rajathr 0:34ee385f4d2d 3174 {
rajathr 0:34ee385f4d2d 3175 /* Check the parameters */
rajathr 0:34ee385f4d2d 3176 assert_param(IS_TIM_LIST6_PERIPH_MORT(TIMx));
rajathr 0:34ee385f4d2d 3177 assert_param(IS_TIM_REMAP(TIM_Remap));
rajathr 0:34ee385f4d2d 3178
rajathr 0:34ee385f4d2d 3179 /* Set the Timer remapping configuration */
rajathr 0:34ee385f4d2d 3180 TIMx->OR = TIM_Remap;
rajathr 0:34ee385f4d2d 3181 }
rajathr 0:34ee385f4d2d 3182 /**
rajathr 0:34ee385f4d2d 3183 * @}
rajathr 0:34ee385f4d2d 3184 */
rajathr 0:34ee385f4d2d 3185
rajathr 0:34ee385f4d2d 3186 /**
rajathr 0:34ee385f4d2d 3187 * @brief Configure the TI1 as Input.
rajathr 0:34ee385f4d2d 3188 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
rajathr 0:34ee385f4d2d 3189 * to select the TIM peripheral.
rajathr 0:34ee385f4d2d 3190 * @param TIM_ICPolarity : The Input Polarity.
rajathr 0:34ee385f4d2d 3191 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3192 * @arg TIM_ICPolarity_Rising_MORT
rajathr 0:34ee385f4d2d 3193 * @arg TIM_ICPolarity_Falling_MORT
rajathr 0:34ee385f4d2d 3194 * @arg TIM_ICPolarity_BothEdge_MORT
rajathr 0:34ee385f4d2d 3195 * @param TIM_ICSelection: specifies the input to be used.
rajathr 0:34ee385f4d2d 3196 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3197 * @arg TIM_ICSelection_DirectTI_MORT: TIM Input 1 is selected to be connected to IC1.
rajathr 0:34ee385f4d2d 3198 * @arg TIM_ICSelection_IndirectTI_MORT: TIM Input 1 is selected to be connected to IC2.
rajathr 0:34ee385f4d2d 3199 * @arg TIM_ICSelection_TRC_MORT: TIM Input 1 is selected to be connected to TRC.
rajathr 0:34ee385f4d2d 3200 * @param TIM_ICFilter: Specifies the Input Capture Filter.
rajathr 0:34ee385f4d2d 3201 * This parameter must be a value between 0x00 and 0x0F.
rajathr 0:34ee385f4d2d 3202 * @retval None
rajathr 0:34ee385f4d2d 3203 */
rajathr 0:34ee385f4d2d 3204 static void TI1_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
rajathr 0:34ee385f4d2d 3205 uint16_t TIM_ICFilter)
rajathr 0:34ee385f4d2d 3206 {
rajathr 0:34ee385f4d2d 3207 uint16_t tmpccmr1 = 0, tmpccer = 0;
rajathr 0:34ee385f4d2d 3208
rajathr 0:34ee385f4d2d 3209 /* Disable the Channel 1: Reset the CC1E Bit */
rajathr 0:34ee385f4d2d 3210 TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E_MORT;
rajathr 0:34ee385f4d2d 3211 tmpccmr1 = TIMx->CCMR1;
rajathr 0:34ee385f4d2d 3212 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 3213
rajathr 0:34ee385f4d2d 3214 /* Select the Input and set the filter */
rajathr 0:34ee385f4d2d 3215 tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S_MORT) & ((uint16_t)~TIM_CCMR1_IC1F_MORT);
rajathr 0:34ee385f4d2d 3216 tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
rajathr 0:34ee385f4d2d 3217
rajathr 0:34ee385f4d2d 3218 /* Select the Polarity and set the CC1E Bit */
rajathr 0:34ee385f4d2d 3219 tmpccer &= (uint16_t)~(TIM_CCER_CC1P_MORT | TIM_CCER_CC1NP_MORT);
rajathr 0:34ee385f4d2d 3220 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E_MORT);
rajathr 0:34ee385f4d2d 3221
rajathr 0:34ee385f4d2d 3222 /* Write to TIMx CCMR1 and CCER registers */
rajathr 0:34ee385f4d2d 3223 TIMx->CCMR1 = tmpccmr1;
rajathr 0:34ee385f4d2d 3224 TIMx->CCER = tmpccer;
rajathr 0:34ee385f4d2d 3225 }
rajathr 0:34ee385f4d2d 3226
rajathr 0:34ee385f4d2d 3227 /**
rajathr 0:34ee385f4d2d 3228 * @brief Configure the TI2 as Input.
rajathr 0:34ee385f4d2d 3229 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
rajathr 0:34ee385f4d2d 3230 * peripheral.
rajathr 0:34ee385f4d2d 3231 * @param TIM_ICPolarity : The Input Polarity.
rajathr 0:34ee385f4d2d 3232 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3233 * @arg TIM_ICPolarity_Rising_MORT
rajathr 0:34ee385f4d2d 3234 * @arg TIM_ICPolarity_Falling_MORT
rajathr 0:34ee385f4d2d 3235 * @arg TIM_ICPolarity_BothEdge_MORT
rajathr 0:34ee385f4d2d 3236 * @param TIM_ICSelection: specifies the input to be used.
rajathr 0:34ee385f4d2d 3237 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3238 * @arg TIM_ICSelection_DirectTI_MORT: TIM Input 2 is selected to be connected to IC2.
rajathr 0:34ee385f4d2d 3239 * @arg TIM_ICSelection_IndirectTI_MORT: TIM Input 2 is selected to be connected to IC1.
rajathr 0:34ee385f4d2d 3240 * @arg TIM_ICSelection_TRC_MORT: TIM Input 2 is selected to be connected to TRC.
rajathr 0:34ee385f4d2d 3241 * @param TIM_ICFilter: Specifies the Input Capture Filter.
rajathr 0:34ee385f4d2d 3242 * This parameter must be a value between 0x00 and 0x0F.
rajathr 0:34ee385f4d2d 3243 * @retval None
rajathr 0:34ee385f4d2d 3244 */
rajathr 0:34ee385f4d2d 3245 static void TI2_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
rajathr 0:34ee385f4d2d 3246 uint16_t TIM_ICFilter)
rajathr 0:34ee385f4d2d 3247 {
rajathr 0:34ee385f4d2d 3248 uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
rajathr 0:34ee385f4d2d 3249
rajathr 0:34ee385f4d2d 3250 /* Disable the Channel 2: Reset the CC2E Bit */
rajathr 0:34ee385f4d2d 3251 TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E_MORT;
rajathr 0:34ee385f4d2d 3252 tmpccmr1 = TIMx->CCMR1;
rajathr 0:34ee385f4d2d 3253 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 3254 tmp = (uint16_t)(TIM_ICPolarity << 4);
rajathr 0:34ee385f4d2d 3255
rajathr 0:34ee385f4d2d 3256 /* Select the Input and set the filter */
rajathr 0:34ee385f4d2d 3257 tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S_MORT) & ((uint16_t)~TIM_CCMR1_IC2F_MORT);
rajathr 0:34ee385f4d2d 3258 tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
rajathr 0:34ee385f4d2d 3259 tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
rajathr 0:34ee385f4d2d 3260
rajathr 0:34ee385f4d2d 3261 /* Select the Polarity and set the CC2E Bit */
rajathr 0:34ee385f4d2d 3262 tmpccer &= (uint16_t)~(TIM_CCER_CC2P_MORT | TIM_CCER_CC2NP_MORT);
rajathr 0:34ee385f4d2d 3263 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E_MORT);
rajathr 0:34ee385f4d2d 3264
rajathr 0:34ee385f4d2d 3265 /* Write to TIMx CCMR1 and CCER registers */
rajathr 0:34ee385f4d2d 3266 TIMx->CCMR1 = tmpccmr1 ;
rajathr 0:34ee385f4d2d 3267 TIMx->CCER = tmpccer;
rajathr 0:34ee385f4d2d 3268 }
rajathr 0:34ee385f4d2d 3269
rajathr 0:34ee385f4d2d 3270 /**
rajathr 0:34ee385f4d2d 3271 * @brief Configure the TI3 as Input.
rajathr 0:34ee385f4d2d 3272 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 3273 * @param TIM_ICPolarity : The Input Polarity.
rajathr 0:34ee385f4d2d 3274 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3275 * @arg TIM_ICPolarity_Rising_MORT
rajathr 0:34ee385f4d2d 3276 * @arg TIM_ICPolarity_Falling_MORT
rajathr 0:34ee385f4d2d 3277 * @arg TIM_ICPolarity_BothEdge_MORT
rajathr 0:34ee385f4d2d 3278 * @param TIM_ICSelection: specifies the input to be used.
rajathr 0:34ee385f4d2d 3279 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3280 * @arg TIM_ICSelection_DirectTI_MORT: TIM Input 3 is selected to be connected to IC3.
rajathr 0:34ee385f4d2d 3281 * @arg TIM_ICSelection_IndirectTI_MORT: TIM Input 3 is selected to be connected to IC4.
rajathr 0:34ee385f4d2d 3282 * @arg TIM_ICSelection_TRC_MORT: TIM Input 3 is selected to be connected to TRC.
rajathr 0:34ee385f4d2d 3283 * @param TIM_ICFilter: Specifies the Input Capture Filter.
rajathr 0:34ee385f4d2d 3284 * This parameter must be a value between 0x00 and 0x0F.
rajathr 0:34ee385f4d2d 3285 * @retval None
rajathr 0:34ee385f4d2d 3286 */
rajathr 0:34ee385f4d2d 3287 static void TI3_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
rajathr 0:34ee385f4d2d 3288 uint16_t TIM_ICFilter)
rajathr 0:34ee385f4d2d 3289 {
rajathr 0:34ee385f4d2d 3290 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
rajathr 0:34ee385f4d2d 3291
rajathr 0:34ee385f4d2d 3292 /* Disable the Channel 3: Reset the CC3E Bit */
rajathr 0:34ee385f4d2d 3293 TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E_MORT;
rajathr 0:34ee385f4d2d 3294 tmpccmr2 = TIMx->CCMR2;
rajathr 0:34ee385f4d2d 3295 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 3296 tmp = (uint16_t)(TIM_ICPolarity << 8);
rajathr 0:34ee385f4d2d 3297
rajathr 0:34ee385f4d2d 3298 /* Select the Input and set the filter */
rajathr 0:34ee385f4d2d 3299 tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S_MORT) & ((uint16_t)~TIM_CCMR2_IC3F_MORT);
rajathr 0:34ee385f4d2d 3300 tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
rajathr 0:34ee385f4d2d 3301
rajathr 0:34ee385f4d2d 3302 /* Select the Polarity and set the CC3E Bit */
rajathr 0:34ee385f4d2d 3303 tmpccer &= (uint16_t)~(TIM_CCER_CC3P_MORT | TIM_CCER_CC3NP_MORT);
rajathr 0:34ee385f4d2d 3304 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E_MORT);
rajathr 0:34ee385f4d2d 3305
rajathr 0:34ee385f4d2d 3306 /* Write to TIMx CCMR2 and CCER registers */
rajathr 0:34ee385f4d2d 3307 TIMx->CCMR2 = tmpccmr2;
rajathr 0:34ee385f4d2d 3308 TIMx->CCER = tmpccer;
rajathr 0:34ee385f4d2d 3309 }
rajathr 0:34ee385f4d2d 3310
rajathr 0:34ee385f4d2d 3311 /**
rajathr 0:34ee385f4d2d 3312 * @brief Configure the TI4 as Input.
rajathr 0:34ee385f4d2d 3313 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
rajathr 0:34ee385f4d2d 3314 * @param TIM_ICPolarity : The Input Polarity.
rajathr 0:34ee385f4d2d 3315 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3316 * @arg TIM_ICPolarity_Rising_MORT
rajathr 0:34ee385f4d2d 3317 * @arg TIM_ICPolarity_Falling_MORT
rajathr 0:34ee385f4d2d 3318 * @arg TIM_ICPolarity_BothEdge_MORT
rajathr 0:34ee385f4d2d 3319 * @param TIM_ICSelection: specifies the input to be used.
rajathr 0:34ee385f4d2d 3320 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3321 * @arg TIM_ICSelection_DirectTI_MORT: TIM Input 4 is selected to be connected to IC4.
rajathr 0:34ee385f4d2d 3322 * @arg TIM_ICSelection_IndirectTI_MORT: TIM Input 4 is selected to be connected to IC3.
rajathr 0:34ee385f4d2d 3323 * @arg TIM_ICSelection_TRC_MORT: TIM Input 4 is selected to be connected to TRC.
rajathr 0:34ee385f4d2d 3324 * @param TIM_ICFilter: Specifies the Input Capture Filter.
rajathr 0:34ee385f4d2d 3325 * This parameter must be a value between 0x00 and 0x0F.
rajathr 0:34ee385f4d2d 3326 * @retval None
rajathr 0:34ee385f4d2d 3327 */
rajathr 0:34ee385f4d2d 3328 static void TI4_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
rajathr 0:34ee385f4d2d 3329 uint16_t TIM_ICFilter)
rajathr 0:34ee385f4d2d 3330 {
rajathr 0:34ee385f4d2d 3331 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
rajathr 0:34ee385f4d2d 3332
rajathr 0:34ee385f4d2d 3333 /* Disable the Channel 4: Reset the CC4E Bit */
rajathr 0:34ee385f4d2d 3334 TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E_MORT;
rajathr 0:34ee385f4d2d 3335 tmpccmr2 = TIMx->CCMR2;
rajathr 0:34ee385f4d2d 3336 tmpccer = TIMx->CCER;
rajathr 0:34ee385f4d2d 3337 tmp = (uint16_t)(TIM_ICPolarity << 12);
rajathr 0:34ee385f4d2d 3338
rajathr 0:34ee385f4d2d 3339 /* Select the Input and set the filter */
rajathr 0:34ee385f4d2d 3340 tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S_MORT) & ((uint16_t)~TIM_CCMR1_IC2F_MORT);
rajathr 0:34ee385f4d2d 3341 tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
rajathr 0:34ee385f4d2d 3342 tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
rajathr 0:34ee385f4d2d 3343
rajathr 0:34ee385f4d2d 3344 /* Select the Polarity and set the CC4E Bit */
rajathr 0:34ee385f4d2d 3345 tmpccer &= (uint16_t)~(TIM_CCER_CC4P_MORT | TIM_CCER_CC4NP_MORT);
rajathr 0:34ee385f4d2d 3346 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E_MORT);
rajathr 0:34ee385f4d2d 3347
rajathr 0:34ee385f4d2d 3348 /* Write to TIMx CCMR2 and CCER registers */
rajathr 0:34ee385f4d2d 3349 TIMx->CCMR2 = tmpccmr2;
rajathr 0:34ee385f4d2d 3350 TIMx->CCER = tmpccer ;
rajathr 0:34ee385f4d2d 3351 }
rajathr 0:34ee385f4d2d 3352
rajathr 0:34ee385f4d2d 3353 /**
rajathr 0:34ee385f4d2d 3354 * @}
rajathr 0:34ee385f4d2d 3355 */
rajathr 0:34ee385f4d2d 3356
rajathr 0:34ee385f4d2d 3357 /**
rajathr 0:34ee385f4d2d 3358 * @}
rajathr 0:34ee385f4d2d 3359 */
rajathr 0:34ee385f4d2d 3360
rajathr 0:34ee385f4d2d 3361 /**
rajathr 0:34ee385f4d2d 3362 * @}
rajathr 0:34ee385f4d2d 3363 */
rajathr 0:34ee385f4d2d 3364
rajathr 0:34ee385f4d2d 3365 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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