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Dependencies:   mbed

stm32f4xx_rcc_mort.c@0:34ee385f4d2d, 2021-10-23 (annotated)

Committer:
rajathr
Date:
Sat Oct 23 05:49:09 2021 +0000
Revision:
0:34ee385f4d2d
At 23rd Oct 21 - All Code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rajathr 0:34ee385f4d2d 1 /**
rajathr 0:34ee385f4d2d 2 ******************************************************************************
rajathr 0:34ee385f4d2d 3 * @file stm32f4xx_rcc.c
rajathr 0:34ee385f4d2d 4 * @author MCD Application Team
rajathr 0:34ee385f4d2d 5 * @version V1.8.0
rajathr 0:34ee385f4d2d 6 * @date 04-November-2016
rajathr 0:34ee385f4d2d 7 * @brief This file provides firmware functions to manage the following
rajathr 0:34ee385f4d2d 8 * functionalities of the Reset and clock control (RCC) peripheral:
rajathr 0:34ee385f4d2d 9 * + Internal/external clocks, PLL, CSS and MCO configuration
rajathr 0:34ee385f4d2d 10 * + System, AHB and APB busses clocks configuration
rajathr 0:34ee385f4d2d 11 * + Peripheral clocks configuration
rajathr 0:34ee385f4d2d 12 * + Interrupts and flags management
rajathr 0:34ee385f4d2d 13 *
rajathr 0:34ee385f4d2d 14 @verbatim
rajathr 0:34ee385f4d2d 15 ===============================================================================
rajathr 0:34ee385f4d2d 16 ##### RCC specific features #####
rajathr 0:34ee385f4d2d 17 ===============================================================================
rajathr 0:34ee385f4d2d 18 [..]
rajathr 0:34ee385f4d2d 19 After reset the device is running from Internal High Speed oscillator
rajathr 0:34ee385f4d2d 20 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
rajathr 0:34ee385f4d2d 21 and I-Cache are disabled, and all peripherals are off except internal
rajathr 0:34ee385f4d2d 22 SRAM, Flash and JTAG.
rajathr 0:34ee385f4d2d 23 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
rajathr 0:34ee385f4d2d 24 all peripherals mapped on these busses are running at HSI speed.
rajathr 0:34ee385f4d2d 25 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
rajathr 0:34ee385f4d2d 26 (+) All GPIOs are in input floating state, except the JTAG pins which
rajathr 0:34ee385f4d2d 27 are assigned to be used for debug purpose.
rajathr 0:34ee385f4d2d 28 [..]
rajathr 0:34ee385f4d2d 29 Once the device started from reset, the user application has to:
rajathr 0:34ee385f4d2d 30 (+) Configure the clock source to be used to drive the System clock
rajathr 0:34ee385f4d2d 31 (if the application needs higher frequency/performance)
rajathr 0:34ee385f4d2d 32 (+) Configure the System clock frequency and Flash settings
rajathr 0:34ee385f4d2d 33 (+) Configure the AHB and APB busses prescalers
rajathr 0:34ee385f4d2d 34 (+) Enable the clock for the peripheral(s) to be used
rajathr 0:34ee385f4d2d 35 (+) Configure the clock source(s) for peripherals which clocks are not
rajathr 0:34ee385f4d2d 36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
rajathr 0:34ee385f4d2d 37 @endverbatim
rajathr 0:34ee385f4d2d 38 ******************************************************************************
rajathr 0:34ee385f4d2d 39 * @attention
rajathr 0:34ee385f4d2d 40 *
rajathr 0:34ee385f4d2d 41 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
rajathr 0:34ee385f4d2d 42 *
rajathr 0:34ee385f4d2d 43 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
rajathr 0:34ee385f4d2d 44 * You may not use this file except in compliance with the License.
rajathr 0:34ee385f4d2d 45 * You may obtain a copy of the License at:
rajathr 0:34ee385f4d2d 46 *
rajathr 0:34ee385f4d2d 47 * http://www.st.com/software_license_agreement_liberty_v2
rajathr 0:34ee385f4d2d 48 *
rajathr 0:34ee385f4d2d 49 * Unless required by applicable law or agreed to in writing, software
rajathr 0:34ee385f4d2d 50 * distributed under the License is distributed on an "AS IS" BASIS,
rajathr 0:34ee385f4d2d 51 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
rajathr 0:34ee385f4d2d 52 * See the License for the specific language governing permissions and
rajathr 0:34ee385f4d2d 53 * limitations under the License.
rajathr 0:34ee385f4d2d 54 *
rajathr 0:34ee385f4d2d 55 ******************************************************************************
rajathr 0:34ee385f4d2d 56 */
rajathr 0:34ee385f4d2d 57
rajathr 0:34ee385f4d2d 58 /* Includes ------------------------------------------------------------------*/
rajathr 0:34ee385f4d2d 59 #include "stm32f4xx_rcc_mort.h"
rajathr 0:34ee385f4d2d 60
rajathr 0:34ee385f4d2d 61 /** @addtogroup STM32F4xx_StdPeriph_Driver
rajathr 0:34ee385f4d2d 62 * @{
rajathr 0:34ee385f4d2d 63 */
rajathr 0:34ee385f4d2d 64
rajathr 0:34ee385f4d2d 65 /** @defgroup RCC
rajathr 0:34ee385f4d2d 66 * @brief RCC driver modules
rajathr 0:34ee385f4d2d 67 * @{
rajathr 0:34ee385f4d2d 68 */
rajathr 0:34ee385f4d2d 69
rajathr 0:34ee385f4d2d 70 /* Private typedef -----------------------------------------------------------*/
rajathr 0:34ee385f4d2d 71 /* Private define ------------------------------------------------------------*/
rajathr 0:34ee385f4d2d 72 /* ------------ RCC registers bit address in the alias region ----------- */
rajathr 0:34ee385f4d2d 73 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
rajathr 0:34ee385f4d2d 74 /* --- CR Register ---*/
rajathr 0:34ee385f4d2d 75 /* Alias word address of HSION bit */
rajathr 0:34ee385f4d2d 76 #define CR_OFFSET (RCC_OFFSET + 0x00)
rajathr 0:34ee385f4d2d 77 #define HSION_BitNumber_MORT 0x00
rajathr 0:34ee385f4d2d 78 #define CR_HSION_BB_MORT (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
rajathr 0:34ee385f4d2d 79 /* Alias word address of CSSON bit */
rajathr 0:34ee385f4d2d 80 #define CSSON_BitNumber_MORT 0x13
rajathr 0:34ee385f4d2d 81 #define CR_CSSON_BB_MORT (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
rajathr 0:34ee385f4d2d 82 /* Alias word address of PLLON bit */
rajathr 0:34ee385f4d2d 83 #define PLLON_BitNumber_MORT 0x18
rajathr 0:34ee385f4d2d 84 #define CR_PLLON_BB_MORT (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
rajathr 0:34ee385f4d2d 85 /* Alias word address of PLLI2SON bit */
rajathr 0:34ee385f4d2d 86 #define PLLI2SON_BitNumber_MORT 0x1A
rajathr 0:34ee385f4d2d 87 #define CR_PLLI2SON_BB_MORT (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
rajathr 0:34ee385f4d2d 88
rajathr 0:34ee385f4d2d 89 /* Alias word address of PLLSAION bit */
rajathr 0:34ee385f4d2d 90 #define PLLSAION_BitNumber_MORT 0x1C
rajathr 0:34ee385f4d2d 91 #define CR_PLLSAION_BB_MORT (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
rajathr 0:34ee385f4d2d 92
rajathr 0:34ee385f4d2d 93 /* --- CFGR Register ---*/
rajathr 0:34ee385f4d2d 94 /* Alias word address of I2SSRC bit */
rajathr 0:34ee385f4d2d 95 #define CFGR_OFFSET (RCC_OFFSET + 0x08)
rajathr 0:34ee385f4d2d 96 #define I2SSRC_BitNumber_MORT 0x17
rajathr 0:34ee385f4d2d 97 #define CFGR_I2SSRC_BB_MORT (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
rajathr 0:34ee385f4d2d 98
rajathr 0:34ee385f4d2d 99 /* --- BDCR Register ---*/
rajathr 0:34ee385f4d2d 100 /* Alias word address of RTCEN bit */
rajathr 0:34ee385f4d2d 101 #define BDCR_OFFSET (RCC_OFFSET + 0x70)
rajathr 0:34ee385f4d2d 102 #define RTCEN_BitNumber_MORT 0x0F
rajathr 0:34ee385f4d2d 103 #define BDCR_RTCEN_BB_MORT (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
rajathr 0:34ee385f4d2d 104 /* Alias word address of BDRST bit */
rajathr 0:34ee385f4d2d 105 #define BDRST_BitNumber_MORT 0x10
rajathr 0:34ee385f4d2d 106 #define BDCR_BDRST_BB_MORT (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
rajathr 0:34ee385f4d2d 107
rajathr 0:34ee385f4d2d 108 /* --- CSR Register ---*/
rajathr 0:34ee385f4d2d 109 /* Alias word address of LSION bit */
rajathr 0:34ee385f4d2d 110 #define CSR_OFFSET (RCC_OFFSET + 0x74)
rajathr 0:34ee385f4d2d 111 #define LSION_BitNumber_MORT 0x00
rajathr 0:34ee385f4d2d 112 #define CSR_LSION_BB_MORT (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
rajathr 0:34ee385f4d2d 113
rajathr 0:34ee385f4d2d 114 /* --- DCKCFGR Register ---*/
rajathr 0:34ee385f4d2d 115 /* Alias word address of TIMPRE bit */
rajathr 0:34ee385f4d2d 116 #define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
rajathr 0:34ee385f4d2d 117 #define TIMPRE_BitNumber_MORT 0x18
rajathr 0:34ee385f4d2d 118 #define DCKCFGR_TIMPRE_BB_MORT (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
rajathr 0:34ee385f4d2d 119
rajathr 0:34ee385f4d2d 120 /* --- CFGR Register ---*/
rajathr 0:34ee385f4d2d 121 #define RCC_CFGR_OFFSET_MORT (RCC_OFFSET + 0x08)
rajathr 0:34ee385f4d2d 122 #if defined(STM32F410xx)
rajathr 0:34ee385f4d2d 123 /* Alias word address of MCO1EN bit */
rajathr 0:34ee385f4d2d 124 #define RCC_MCO1EN_BIT_NUMBER 0x8
rajathr 0:34ee385f4d2d 125 #define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
rajathr 0:34ee385f4d2d 126
rajathr 0:34ee385f4d2d 127 /* Alias word address of MCO2EN bit */
rajathr 0:34ee385f4d2d 128 #define RCC_MCO2EN_BIT_NUMBER 0x9
rajathr 0:34ee385f4d2d 129 #define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
rajathr 0:34ee385f4d2d 130 #endif /* STM32F410xx */
rajathr 0:34ee385f4d2d 131 /* ---------------------- RCC registers bit mask ------------------------ */
rajathr 0:34ee385f4d2d 132 /* CFGR register bit mask */
rajathr 0:34ee385f4d2d 133 #define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)
rajathr 0:34ee385f4d2d 134 #define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)
rajathr 0:34ee385f4d2d 135
rajathr 0:34ee385f4d2d 136 /* RCC Flag Mask */
rajathr 0:34ee385f4d2d 137 #define FLAG_MASK ((uint8_t)0x1F)
rajathr 0:34ee385f4d2d 138
rajathr 0:34ee385f4d2d 139 /* CR register byte 3 (Bits[23:16]) base address */
rajathr 0:34ee385f4d2d 140 #define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
rajathr 0:34ee385f4d2d 141
rajathr 0:34ee385f4d2d 142 /* CIR register byte 2 (Bits[15:8]) base address */
rajathr 0:34ee385f4d2d 143 #define CIR_BYTE2_ADDRESS_MORT ((uint32_t)(RCC_BASE + 0x0C + 0x01))
rajathr 0:34ee385f4d2d 144
rajathr 0:34ee385f4d2d 145 /* CIR register byte 3 (Bits[23:16]) base address */
rajathr 0:34ee385f4d2d 146 #define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
rajathr 0:34ee385f4d2d 147
rajathr 0:34ee385f4d2d 148 /* BDCR register base address */
rajathr 0:34ee385f4d2d 149 #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
rajathr 0:34ee385f4d2d 150
rajathr 0:34ee385f4d2d 151 /* Private macro -------------------------------------------------------------*/
rajathr 0:34ee385f4d2d 152 /* Private variables ---------------------------------------------------------*/
rajathr 0:34ee385f4d2d 153 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
rajathr 0:34ee385f4d2d 154
rajathr 0:34ee385f4d2d 155 /* Private function prototypes -----------------------------------------------*/
rajathr 0:34ee385f4d2d 156 /* Private functions ---------------------------------------------------------*/
rajathr 0:34ee385f4d2d 157
rajathr 0:34ee385f4d2d 158 /** @defgroup RCC_Private_Functions
rajathr 0:34ee385f4d2d 159 * @{
rajathr 0:34ee385f4d2d 160 */
rajathr 0:34ee385f4d2d 161
rajathr 0:34ee385f4d2d 162 /** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
rajathr 0:34ee385f4d2d 163 * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
rajathr 0:34ee385f4d2d 164 *
rajathr 0:34ee385f4d2d 165 @verbatim
rajathr 0:34ee385f4d2d 166 ===================================================================================
rajathr 0:34ee385f4d2d 167 ##### Internal and external clocks, PLL, CSS and MCO configuration functions #####
rajathr 0:34ee385f4d2d 168 ===================================================================================
rajathr 0:34ee385f4d2d 169 [..]
rajathr 0:34ee385f4d2d 170 This section provide functions allowing to configure the internal/external clocks,
rajathr 0:34ee385f4d2d 171 PLLs, CSS and MCO pins.
rajathr 0:34ee385f4d2d 172
rajathr 0:34ee385f4d2d 173 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
rajathr 0:34ee385f4d2d 174 the PLL as System clock source.
rajathr 0:34ee385f4d2d 175
rajathr 0:34ee385f4d2d 176 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
rajathr 0:34ee385f4d2d 177 clock source.
rajathr 0:34ee385f4d2d 178
rajathr 0:34ee385f4d2d 179 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
rajathr 0:34ee385f4d2d 180 through the PLL as System clock source. Can be used also as RTC clock source.
rajathr 0:34ee385f4d2d 181
rajathr 0:34ee385f4d2d 182 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
rajathr 0:34ee385f4d2d 183
rajathr 0:34ee385f4d2d 184 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
rajathr 0:34ee385f4d2d 185 (++) The first output is used to generate the high speed system clock (up to 168 MHz)
rajathr 0:34ee385f4d2d 186 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
rajathr 0:34ee385f4d2d 187 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
rajathr 0:34ee385f4d2d 188
rajathr 0:34ee385f4d2d 189 (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve
rajathr 0:34ee385f4d2d 190 high-quality audio performance on the I2S interface or SAI interface in case
rajathr 0:34ee385f4d2d 191 of STM32F429x/439x devices.
rajathr 0:34ee385f4d2d 192
rajathr 0:34ee385f4d2d 193 (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI
rajathr 0:34ee385f4d2d 194 interface and LCD TFT controller available only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
rajathr 0:34ee385f4d2d 195
rajathr 0:34ee385f4d2d 196 (#) CSS (Clock security system), once enable and if a HSE clock failure occurs
rajathr 0:34ee385f4d2d 197 (HSE used directly or through PLL as System clock source), the System clock
rajathr 0:34ee385f4d2d 198 is automatically switched to HSI and an interrupt is generated if enabled.
rajathr 0:34ee385f4d2d 199 The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
rajathr 0:34ee385f4d2d 200 exception vector.
rajathr 0:34ee385f4d2d 201
rajathr 0:34ee385f4d2d 202 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
rajathr 0:34ee385f4d2d 203 clock (through a configurable prescaler) on PA8 pin.
rajathr 0:34ee385f4d2d 204
rajathr 0:34ee385f4d2d 205 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
rajathr 0:34ee385f4d2d 206 clock (through a configurable prescaler) on PC9 pin.
rajathr 0:34ee385f4d2d 207 @endverbatim
rajathr 0:34ee385f4d2d 208 * @{
rajathr 0:34ee385f4d2d 209 */
rajathr 0:34ee385f4d2d 210
rajathr 0:34ee385f4d2d 211 /**
rajathr 0:34ee385f4d2d 212 * @brief Resets the RCC clock configuration to the default reset state.
rajathr 0:34ee385f4d2d 213 * @note The default reset state of the clock configuration is given below:
rajathr 0:34ee385f4d2d 214 * - HSI ON and used as system clock source
rajathr 0:34ee385f4d2d 215 * - HSE, PLL and PLLI2S OFF
rajathr 0:34ee385f4d2d 216 * - AHB, APB1 and APB2 prescaler set to 1.
rajathr 0:34ee385f4d2d 217 * - CSS, MCO1 and MCO2 OFF
rajathr 0:34ee385f4d2d 218 * - All interrupts disabled
rajathr 0:34ee385f4d2d 219 * @note This function doesn't modify the configuration of the
rajathr 0:34ee385f4d2d 220 * - Peripheral clocks
rajathr 0:34ee385f4d2d 221 * - LSI, LSE and RTC clocks
rajathr 0:34ee385f4d2d 222 * @param None
rajathr 0:34ee385f4d2d 223 * @retval None
rajathr 0:34ee385f4d2d 224 */
rajathr 0:34ee385f4d2d 225 void RCC_DeInit(void)
rajathr 0:34ee385f4d2d 226 {
rajathr 0:34ee385f4d2d 227 /* Set HSION bit */
rajathr 0:34ee385f4d2d 228 RCC->CR |= (uint32_t)0x00000001;
rajathr 0:34ee385f4d2d 229
rajathr 0:34ee385f4d2d 230 /* Reset CFGR register */
rajathr 0:34ee385f4d2d 231 RCC->CFGR = 0x00000000;
rajathr 0:34ee385f4d2d 232
rajathr 0:34ee385f4d2d 233 /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42xxx/43xxx/446xx/469xx/479xx devices) bits */
rajathr 0:34ee385f4d2d 234 RCC->CR &= (uint32_t)0xEAF6FFFF;
rajathr 0:34ee385f4d2d 235
rajathr 0:34ee385f4d2d 236 /* Reset PLLCFGR register */
rajathr 0:34ee385f4d2d 237 RCC->PLLCFGR = 0x24003010;
rajathr 0:34ee385f4d2d 238
rajathr 0:34ee385f4d2d 239 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F413_423xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 240 /* Reset PLLI2SCFGR register */
rajathr 0:34ee385f4d2d 241 RCC->PLLI2SCFGR = 0x20003000;
rajathr 0:34ee385f4d2d 242 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F413_423xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 243
rajathr 0:34ee385f4d2d 244 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 245 /* Reset PLLSAICFGR register, only available for STM32F42xxx/43xxx/446xx/469xx/479xx devices */
rajathr 0:34ee385f4d2d 246 RCC->PLLSAICFGR = 0x24003000;
rajathr 0:34ee385f4d2d 247 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 248
rajathr 0:34ee385f4d2d 249 /* Reset HSEBYP bit */
rajathr 0:34ee385f4d2d 250 RCC->CR &= (uint32_t)0xFFFBFFFF;
rajathr 0:34ee385f4d2d 251
rajathr 0:34ee385f4d2d 252 /* Disable all interrupts */
rajathr 0:34ee385f4d2d 253 RCC->CIR = 0x00000000;
rajathr 0:34ee385f4d2d 254
rajathr 0:34ee385f4d2d 255 /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx and STM32F413_423xx devices */
rajathr 0:34ee385f4d2d 256 RCC->DCKCFGR = 0x00000000;
rajathr 0:34ee385f4d2d 257
rajathr 0:34ee385f4d2d 258 #if defined(STM32F410xx) || defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 259 /* Disable LPTIM and FMPI2C clock prescalers selection, only available for STM32F410xx and STM32F413_423xx devices */
rajathr 0:34ee385f4d2d 260 RCC->DCKCFGR2 = 0x00000000;
rajathr 0:34ee385f4d2d 261 #endif /* STM32F410xx || STM32F413_423xx */
rajathr 0:34ee385f4d2d 262 }
rajathr 0:34ee385f4d2d 263
rajathr 0:34ee385f4d2d 264 /**
rajathr 0:34ee385f4d2d 265 * @brief Configures the External High Speed oscillator (HSE).
rajathr 0:34ee385f4d2d 266 * @note After enabling the HSE (RCC_HSE_ON_MORT or RCC_HSE_Bypass), the application
rajathr 0:34ee385f4d2d 267 * software should wait on HSERDY flag to be set indicating that HSE clock
rajathr 0:34ee385f4d2d 268 * is stable and can be used to clock the PLL and/or system clock.
rajathr 0:34ee385f4d2d 269 * @note HSE state can not be changed if it is used directly or through the
rajathr 0:34ee385f4d2d 270 * PLL as system clock. In this case, you have to select another source
rajathr 0:34ee385f4d2d 271 * of the system clock then change the HSE state (ex. disable it).
rajathr 0:34ee385f4d2d 272 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
rajathr 0:34ee385f4d2d 273 * @note This function reset the CSSON bit, so if the Clock security system(CSS)
rajathr 0:34ee385f4d2d 274 * was previously enabled you have to enable it again after calling this
rajathr 0:34ee385f4d2d 275 * function.
rajathr 0:34ee385f4d2d 276 * @param RCC_HSE: specifies the new state of the HSE.
rajathr 0:34ee385f4d2d 277 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 278 * @arg RCC_HSE_OFF_MORT: turn OFF the HSE oscillator, HSERDY flag goes low after
rajathr 0:34ee385f4d2d 279 * 6 HSE oscillator clock cycles.
rajathr 0:34ee385f4d2d 280 * @arg RCC_HSE_ON_MORT: turn ON the HSE oscillator
rajathr 0:34ee385f4d2d 281 * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
rajathr 0:34ee385f4d2d 282 * @retval None
rajathr 0:34ee385f4d2d 283 */
rajathr 0:34ee385f4d2d 284 void RCC_HSEConfig(uint8_t RCC_HSE)
rajathr 0:34ee385f4d2d 285 {
rajathr 0:34ee385f4d2d 286 /* Check the parameters */
rajathr 0:34ee385f4d2d 287 assert_param(IS_RCC_HSE_MORT(RCC_HSE));
rajathr 0:34ee385f4d2d 288
rajathr 0:34ee385f4d2d 289 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
rajathr 0:34ee385f4d2d 290 *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF_MORT;
rajathr 0:34ee385f4d2d 291
rajathr 0:34ee385f4d2d 292 /* Set the new HSE configuration -------------------------------------------*/
rajathr 0:34ee385f4d2d 293 *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
rajathr 0:34ee385f4d2d 294 }
rajathr 0:34ee385f4d2d 295
rajathr 0:34ee385f4d2d 296 /**
rajathr 0:34ee385f4d2d 297 * @brief Waits for HSE start-up.
rajathr 0:34ee385f4d2d 298 * @note This functions waits on HSERDY flag to be set and return SUCCESS if
rajathr 0:34ee385f4d2d 299 * this flag is set, otherwise returns ERROR if the timeout is reached
rajathr 0:34ee385f4d2d 300 * and this flag is not set. The timeout value is defined by the constant
rajathr 0:34ee385f4d2d 301 * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending
rajathr 0:34ee385f4d2d 302 * on the HSE crystal used in your application.
rajathr 0:34ee385f4d2d 303 * @param None
rajathr 0:34ee385f4d2d 304 * @retval An ErrorStatus enumeration value:
rajathr 0:34ee385f4d2d 305 * - SUCCESS: HSE oscillator is stable and ready to use
rajathr 0:34ee385f4d2d 306 * - ERROR: HSE oscillator not yet ready
rajathr 0:34ee385f4d2d 307 */
rajathr 0:34ee385f4d2d 308 ErrorStatus RCC_WaitForHSEStartUp(void)
rajathr 0:34ee385f4d2d 309 {
rajathr 0:34ee385f4d2d 310 __IO uint32_t startupcounter = 0;
rajathr 0:34ee385f4d2d 311 ErrorStatus status = ERROR;
rajathr 0:34ee385f4d2d 312 FlagStatus hsestatus = RESET;
rajathr 0:34ee385f4d2d 313 /* Wait till HSE is ready and if Time out is reached exit */
rajathr 0:34ee385f4d2d 314 do
rajathr 0:34ee385f4d2d 315 {
rajathr 0:34ee385f4d2d 316 hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
rajathr 0:34ee385f4d2d 317 startupcounter++;
rajathr 0:34ee385f4d2d 318 } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
rajathr 0:34ee385f4d2d 319
rajathr 0:34ee385f4d2d 320 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
rajathr 0:34ee385f4d2d 321 {
rajathr 0:34ee385f4d2d 322 status = SUCCESS;
rajathr 0:34ee385f4d2d 323 }
rajathr 0:34ee385f4d2d 324 else
rajathr 0:34ee385f4d2d 325 {
rajathr 0:34ee385f4d2d 326 status = ERROR;
rajathr 0:34ee385f4d2d 327 }
rajathr 0:34ee385f4d2d 328 return (status);
rajathr 0:34ee385f4d2d 329 }
rajathr 0:34ee385f4d2d 330
rajathr 0:34ee385f4d2d 331 /**
rajathr 0:34ee385f4d2d 332 * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
rajathr 0:34ee385f4d2d 333 * @note The calibration is used to compensate for the variations in voltage
rajathr 0:34ee385f4d2d 334 * and temperature that influence the frequency of the internal HSI RC.
rajathr 0:34ee385f4d2d 335 * @param HSICalibrationValue: specifies the calibration trimming value.
rajathr 0:34ee385f4d2d 336 * This parameter must be a number between 0 and 0x1F.
rajathr 0:34ee385f4d2d 337 * @retval None
rajathr 0:34ee385f4d2d 338 */
rajathr 0:34ee385f4d2d 339 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
rajathr 0:34ee385f4d2d 340 {
rajathr 0:34ee385f4d2d 341 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 342 /* Check the parameters */
rajathr 0:34ee385f4d2d 343 assert_param(IS_RCC_CALIBRATION_VALUE_MORT(HSICalibrationValue));
rajathr 0:34ee385f4d2d 344
rajathr 0:34ee385f4d2d 345 tmpreg = RCC->CR;
rajathr 0:34ee385f4d2d 346
rajathr 0:34ee385f4d2d 347 /* Clear HSITRIM[4:0] bits */
rajathr 0:34ee385f4d2d 348 tmpreg &= ~RCC_CR_HSITRIM_MORT;
rajathr 0:34ee385f4d2d 349
rajathr 0:34ee385f4d2d 350 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
rajathr 0:34ee385f4d2d 351 tmpreg |= (uint32_t)HSICalibrationValue << 3;
rajathr 0:34ee385f4d2d 352
rajathr 0:34ee385f4d2d 353 /* Store the new value */
rajathr 0:34ee385f4d2d 354 RCC->CR = tmpreg;
rajathr 0:34ee385f4d2d 355 }
rajathr 0:34ee385f4d2d 356
rajathr 0:34ee385f4d2d 357 /**
rajathr 0:34ee385f4d2d 358 * @brief Enables or disables the Internal High Speed oscillator (HSI).
rajathr 0:34ee385f4d2d 359 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
rajathr 0:34ee385f4d2d 360 * It is used (enabled by hardware) as system clock source after startup
rajathr 0:34ee385f4d2d 361 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
rajathr 0:34ee385f4d2d 362 * of the HSE used directly or indirectly as system clock (if the Clock
rajathr 0:34ee385f4d2d 363 * Security System CSS is enabled).
rajathr 0:34ee385f4d2d 364 * @note HSI can not be stopped if it is used as system clock source. In this case,
rajathr 0:34ee385f4d2d 365 * you have to select another source of the system clock then stop the HSI.
rajathr 0:34ee385f4d2d 366 * @note After enabling the HSI, the application software should wait on HSIRDY
rajathr 0:34ee385f4d2d 367 * flag to be set indicating that HSI clock is stable and can be used as
rajathr 0:34ee385f4d2d 368 * system clock source.
rajathr 0:34ee385f4d2d 369 * @param NewState: new state of the HSI.
rajathr 0:34ee385f4d2d 370 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 371 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
rajathr 0:34ee385f4d2d 372 * clock cycles.
rajathr 0:34ee385f4d2d 373 * @retval None
rajathr 0:34ee385f4d2d 374 */
rajathr 0:34ee385f4d2d 375 void RCC_HSICmd(FunctionalState NewState)
rajathr 0:34ee385f4d2d 376 {
rajathr 0:34ee385f4d2d 377 /* Check the parameters */
rajathr 0:34ee385f4d2d 378 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 379
rajathr 0:34ee385f4d2d 380 *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
rajathr 0:34ee385f4d2d 381 }
rajathr 0:34ee385f4d2d 382
rajathr 0:34ee385f4d2d 383 /**
rajathr 0:34ee385f4d2d 384 * @brief Configures the External Low Speed oscillator (LSE).
rajathr 0:34ee385f4d2d 385 * @note As the LSE is in the Backup domain and write access is denied to
rajathr 0:34ee385f4d2d 386 * this domain after reset, you have to enable write access using
rajathr 0:34ee385f4d2d 387 * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
rajathr 0:34ee385f4d2d 388 * (to be done once after reset).
rajathr 0:34ee385f4d2d 389 * @note After enabling the LSE (RCC_LSE_ON_MORT or RCC_LSE_Bypass), the application
rajathr 0:34ee385f4d2d 390 * software should wait on LSERDY flag to be set indicating that LSE clock
rajathr 0:34ee385f4d2d 391 * is stable and can be used to clock the RTC.
rajathr 0:34ee385f4d2d 392 * @param RCC_LSE: specifies the new state of the LSE.
rajathr 0:34ee385f4d2d 393 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 394 * @arg RCC_LSE_OFF_MORT: turn OFF the LSE oscillator, LSERDY flag goes low after
rajathr 0:34ee385f4d2d 395 * 6 LSE oscillator clock cycles.
rajathr 0:34ee385f4d2d 396 * @arg RCC_LSE_ON_MORT: turn ON the LSE oscillator
rajathr 0:34ee385f4d2d 397 * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
rajathr 0:34ee385f4d2d 398 * @retval None
rajathr 0:34ee385f4d2d 399 */
rajathr 0:34ee385f4d2d 400 void RCC_LSEConfig(uint8_t RCC_LSE)
rajathr 0:34ee385f4d2d 401 {
rajathr 0:34ee385f4d2d 402 /* Check the parameters */
rajathr 0:34ee385f4d2d 403 assert_param(IS_RCC_LSE_MORT(RCC_LSE));
rajathr 0:34ee385f4d2d 404
rajathr 0:34ee385f4d2d 405 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
rajathr 0:34ee385f4d2d 406 /* Reset LSEON bit */
rajathr 0:34ee385f4d2d 407 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF_MORT;
rajathr 0:34ee385f4d2d 408
rajathr 0:34ee385f4d2d 409 /* Reset LSEBYP bit */
rajathr 0:34ee385f4d2d 410 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF_MORT;
rajathr 0:34ee385f4d2d 411
rajathr 0:34ee385f4d2d 412 /* Configure LSE (RCC_LSE_OFF_MORT is already covered by the code section above) */
rajathr 0:34ee385f4d2d 413 switch (RCC_LSE)
rajathr 0:34ee385f4d2d 414 {
rajathr 0:34ee385f4d2d 415 case RCC_LSE_ON_MORT:
rajathr 0:34ee385f4d2d 416 /* Set LSEON bit */
rajathr 0:34ee385f4d2d 417 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON_MORT;
rajathr 0:34ee385f4d2d 418 break;
rajathr 0:34ee385f4d2d 419 case RCC_LSE_Bypass:
rajathr 0:34ee385f4d2d 420 /* Set LSEBYP and LSEON bits */
rajathr 0:34ee385f4d2d 421 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON_MORT;
rajathr 0:34ee385f4d2d 422 break;
rajathr 0:34ee385f4d2d 423 default:
rajathr 0:34ee385f4d2d 424 break;
rajathr 0:34ee385f4d2d 425 }
rajathr 0:34ee385f4d2d 426 }
rajathr 0:34ee385f4d2d 427
rajathr 0:34ee385f4d2d 428 /**
rajathr 0:34ee385f4d2d 429 * @brief Enables or disables the Internal Low Speed oscillator (LSI).
rajathr 0:34ee385f4d2d 430 * @note After enabling the LSI, the application software should wait on
rajathr 0:34ee385f4d2d 431 * LSIRDY flag to be set indicating that LSI clock is stable and can
rajathr 0:34ee385f4d2d 432 * be used to clock the IWDG and/or the RTC.
rajathr 0:34ee385f4d2d 433 * @note LSI can not be disabled if the IWDG is running.
rajathr 0:34ee385f4d2d 434 * @param NewState: new state of the LSI.
rajathr 0:34ee385f4d2d 435 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 436 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
rajathr 0:34ee385f4d2d 437 * clock cycles.
rajathr 0:34ee385f4d2d 438 * @retval None
rajathr 0:34ee385f4d2d 439 */
rajathr 0:34ee385f4d2d 440 void RCC_LSICmd(FunctionalState NewState)
rajathr 0:34ee385f4d2d 441 {
rajathr 0:34ee385f4d2d 442 /* Check the parameters */
rajathr 0:34ee385f4d2d 443 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 444
rajathr 0:34ee385f4d2d 445 *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
rajathr 0:34ee385f4d2d 446 }
rajathr 0:34ee385f4d2d 447
rajathr 0:34ee385f4d2d 448 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 449 /**
rajathr 0:34ee385f4d2d 450 * @brief Configures the main PLL clock source, multiplication and division factors.
rajathr 0:34ee385f4d2d 451 * @note This function must be used only when the main PLL is disabled.
rajathr 0:34ee385f4d2d 452 *
rajathr 0:34ee385f4d2d 453 * @param RCC_PLLSource: specifies the PLL entry clock source.
rajathr 0:34ee385f4d2d 454 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 455 * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
rajathr 0:34ee385f4d2d 456 * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
rajathr 0:34ee385f4d2d 457 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
rajathr 0:34ee385f4d2d 458 *
rajathr 0:34ee385f4d2d 459 * @param PLLM: specifies the division factor for PLL VCO input clock
rajathr 0:34ee385f4d2d 460 * This parameter must be a number between 0 and 63.
rajathr 0:34ee385f4d2d 461 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
rajathr 0:34ee385f4d2d 462 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
rajathr 0:34ee385f4d2d 463 * of 2 MHz to limit PLL jitter.
rajathr 0:34ee385f4d2d 464 *
rajathr 0:34ee385f4d2d 465 * @param PLLN: specifies the multiplication factor for PLL VCO output clock
rajathr 0:34ee385f4d2d 466 * This parameter must be a number between 50 and 432.
rajathr 0:34ee385f4d2d 467 * @note You have to set the PLLN parameter correctly to ensure that the VCO
rajathr 0:34ee385f4d2d 468 * output frequency is between 100 and 432 MHz.
rajathr 0:34ee385f4d2d 469 *
rajathr 0:34ee385f4d2d 470 * @param PLLP: specifies the division factor for main system clock (SYSCLK)
rajathr 0:34ee385f4d2d 471 * This parameter must be a number in the range {2, 4, 6, or 8}.
rajathr 0:34ee385f4d2d 472 * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
rajathr 0:34ee385f4d2d 473 * the System clock frequency.
rajathr 0:34ee385f4d2d 474 *
rajathr 0:34ee385f4d2d 475 * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
rajathr 0:34ee385f4d2d 476 * This parameter must be a number between 4 and 15.
rajathr 0:34ee385f4d2d 477 *
rajathr 0:34ee385f4d2d 478 * @param PLLR: specifies the division factor for I2S, SAI, SYSTEM, SPDIF in STM32F446xx devices
rajathr 0:34ee385f4d2d 479 * This parameter must be a number between 2 and 7.
rajathr 0:34ee385f4d2d 480 *
rajathr 0:34ee385f4d2d 481 * @note If the USB OTG FS is used in your application, you have to set the
rajathr 0:34ee385f4d2d 482 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
rajathr 0:34ee385f4d2d 483 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
rajathr 0:34ee385f4d2d 484 * correctly.
rajathr 0:34ee385f4d2d 485 *
rajathr 0:34ee385f4d2d 486 * @retval None
rajathr 0:34ee385f4d2d 487 */
rajathr 0:34ee385f4d2d 488 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR)
rajathr 0:34ee385f4d2d 489 {
rajathr 0:34ee385f4d2d 490 /* Check the parameters */
rajathr 0:34ee385f4d2d 491 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
rajathr 0:34ee385f4d2d 492 assert_param(IS_RCC_PLLM_VALUE_MORT(PLLM));
rajathr 0:34ee385f4d2d 493 assert_param(IS_RCC_PLLN_VALUE(PLLN));
rajathr 0:34ee385f4d2d 494 assert_param(IS_RCC_PLLP_VALUE_MORT(PLLP));
rajathr 0:34ee385f4d2d 495 assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
rajathr 0:34ee385f4d2d 496 assert_param(IS_RCC_PLLR_VALUE_MORT(PLLR));
rajathr 0:34ee385f4d2d 497
rajathr 0:34ee385f4d2d 498 RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
rajathr 0:34ee385f4d2d 499 (PLLQ << 24) | (PLLR << 28);
rajathr 0:34ee385f4d2d 500 }
rajathr 0:34ee385f4d2d 501 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 502
rajathr 0:34ee385f4d2d 503 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
rajathr 0:34ee385f4d2d 504 /**
rajathr 0:34ee385f4d2d 505 * @brief Configures the main PLL clock source, multiplication and division factors.
rajathr 0:34ee385f4d2d 506 * @note This function must be used only when the main PLL is disabled.
rajathr 0:34ee385f4d2d 507 *
rajathr 0:34ee385f4d2d 508 * @param RCC_PLLSource: specifies the PLL entry clock source.
rajathr 0:34ee385f4d2d 509 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 510 * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
rajathr 0:34ee385f4d2d 511 * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
rajathr 0:34ee385f4d2d 512 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
rajathr 0:34ee385f4d2d 513 *
rajathr 0:34ee385f4d2d 514 * @param PLLM: specifies the division factor for PLL VCO input clock
rajathr 0:34ee385f4d2d 515 * This parameter must be a number between 0 and 63.
rajathr 0:34ee385f4d2d 516 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
rajathr 0:34ee385f4d2d 517 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
rajathr 0:34ee385f4d2d 518 * of 2 MHz to limit PLL jitter.
rajathr 0:34ee385f4d2d 519 *
rajathr 0:34ee385f4d2d 520 * @param PLLN: specifies the multiplication factor for PLL VCO output clock
rajathr 0:34ee385f4d2d 521 * This parameter must be a number between 50 and 432.
rajathr 0:34ee385f4d2d 522 * @note You have to set the PLLN parameter correctly to ensure that the VCO
rajathr 0:34ee385f4d2d 523 * output frequency is between 100 and 432 MHz.
rajathr 0:34ee385f4d2d 524 *
rajathr 0:34ee385f4d2d 525 * @param PLLP: specifies the division factor for main system clock (SYSCLK)
rajathr 0:34ee385f4d2d 526 * This parameter must be a number in the range {2, 4, 6, or 8}.
rajathr 0:34ee385f4d2d 527 * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
rajathr 0:34ee385f4d2d 528 * the System clock frequency.
rajathr 0:34ee385f4d2d 529 *
rajathr 0:34ee385f4d2d 530 * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
rajathr 0:34ee385f4d2d 531 * This parameter must be a number between 4 and 15.
rajathr 0:34ee385f4d2d 532 * @note If the USB OTG FS is used in your application, you have to set the
rajathr 0:34ee385f4d2d 533 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
rajathr 0:34ee385f4d2d 534 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
rajathr 0:34ee385f4d2d 535 * correctly.
rajathr 0:34ee385f4d2d 536 *
rajathr 0:34ee385f4d2d 537 * @retval None
rajathr 0:34ee385f4d2d 538 */
rajathr 0:34ee385f4d2d 539 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
rajathr 0:34ee385f4d2d 540 {
rajathr 0:34ee385f4d2d 541 /* Check the parameters */
rajathr 0:34ee385f4d2d 542 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
rajathr 0:34ee385f4d2d 543 assert_param(IS_RCC_PLLM_VALUE_MORT(PLLM));
rajathr 0:34ee385f4d2d 544 assert_param(IS_RCC_PLLN_VALUE(PLLN));
rajathr 0:34ee385f4d2d 545 assert_param(IS_RCC_PLLP_VALUE_MORT(PLLP));
rajathr 0:34ee385f4d2d 546 assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
rajathr 0:34ee385f4d2d 547
rajathr 0:34ee385f4d2d 548 RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
rajathr 0:34ee385f4d2d 549 (PLLQ << 24);
rajathr 0:34ee385f4d2d 550 }
rajathr 0:34ee385f4d2d 551 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
rajathr 0:34ee385f4d2d 552
rajathr 0:34ee385f4d2d 553 /**
rajathr 0:34ee385f4d2d 554 * @brief Enables or disables the main PLL.
rajathr 0:34ee385f4d2d 555 * @note After enabling the main PLL, the application software should wait on
rajathr 0:34ee385f4d2d 556 * PLLRDY flag to be set indicating that PLL clock is stable and can
rajathr 0:34ee385f4d2d 557 * be used as system clock source.
rajathr 0:34ee385f4d2d 558 * @note The main PLL can not be disabled if it is used as system clock source
rajathr 0:34ee385f4d2d 559 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
rajathr 0:34ee385f4d2d 560 * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 561 * @retval None
rajathr 0:34ee385f4d2d 562 */
rajathr 0:34ee385f4d2d 563 void RCC_PLLCmd(FunctionalState NewState)
rajathr 0:34ee385f4d2d 564 {
rajathr 0:34ee385f4d2d 565 /* Check the parameters */
rajathr 0:34ee385f4d2d 566 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 567 *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
rajathr 0:34ee385f4d2d 568 }
rajathr 0:34ee385f4d2d 569
rajathr 0:34ee385f4d2d 570 #if defined(STM32F40_41xxx) || defined(STM32F401xx)
rajathr 0:34ee385f4d2d 571 /**
rajathr 0:34ee385f4d2d 572 * @brief Configures the PLLI2S clock multiplication and division factors.
rajathr 0:34ee385f4d2d 573 *
rajathr 0:34ee385f4d2d 574 * @note This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx
rajathr 0:34ee385f4d2d 575 * or STM32F401xx devices.
rajathr 0:34ee385f4d2d 576 *
rajathr 0:34ee385f4d2d 577 * @note This function must be used only when the PLLI2S is disabled.
rajathr 0:34ee385f4d2d 578 * @note PLLI2S clock source is common with the main PLL (configured in
rajathr 0:34ee385f4d2d 579 * RCC_PLLConfig function )
rajathr 0:34ee385f4d2d 580 *
rajathr 0:34ee385f4d2d 581 * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
rajathr 0:34ee385f4d2d 582 * This parameter must be a number between 50 and 432.
rajathr 0:34ee385f4d2d 583 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
rajathr 0:34ee385f4d2d 584 * output frequency is between 100 and 432 MHz.
rajathr 0:34ee385f4d2d 585 *
rajathr 0:34ee385f4d2d 586 * @param PLLI2SR: specifies the division factor for I2S clock
rajathr 0:34ee385f4d2d 587 * This parameter must be a number between 2 and 7.
rajathr 0:34ee385f4d2d 588 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
rajathr 0:34ee385f4d2d 589 * on the I2S clock frequency.
rajathr 0:34ee385f4d2d 590 *
rajathr 0:34ee385f4d2d 591 * @retval None
rajathr 0:34ee385f4d2d 592 */
rajathr 0:34ee385f4d2d 593 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
rajathr 0:34ee385f4d2d 594 {
rajathr 0:34ee385f4d2d 595 /* Check the parameters */
rajathr 0:34ee385f4d2d 596 assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
rajathr 0:34ee385f4d2d 597 assert_param(IS_RCC_PLLI2SR_VALUE_MORT(PLLI2SR));
rajathr 0:34ee385f4d2d 598
rajathr 0:34ee385f4d2d 599 RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
rajathr 0:34ee385f4d2d 600 }
rajathr 0:34ee385f4d2d 601 #endif /* STM32F40_41xxx || STM32F401xx */
rajathr 0:34ee385f4d2d 602
rajathr 0:34ee385f4d2d 603 #if defined(STM32F411xE)
rajathr 0:34ee385f4d2d 604 /**
rajathr 0:34ee385f4d2d 605 * @brief Configures the PLLI2S clock multiplication and division factors.
rajathr 0:34ee385f4d2d 606 *
rajathr 0:34ee385f4d2d 607 * @note This function can be used only for STM32F411xE devices.
rajathr 0:34ee385f4d2d 608 *
rajathr 0:34ee385f4d2d 609 * @note This function must be used only when the PLLI2S is disabled.
rajathr 0:34ee385f4d2d 610 * @note PLLI2S clock source is common with the main PLL (configured in
rajathr 0:34ee385f4d2d 611 * RCC_PLLConfig function )
rajathr 0:34ee385f4d2d 612 *
rajathr 0:34ee385f4d2d 613 * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock
rajathr 0:34ee385f4d2d 614 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
rajathr 0:34ee385f4d2d 615 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
rajathr 0:34ee385f4d2d 616 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
rajathr 0:34ee385f4d2d 617 * of 2 MHz to limit PLLI2S jitter.
rajathr 0:34ee385f4d2d 618 *
rajathr 0:34ee385f4d2d 619 * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
rajathr 0:34ee385f4d2d 620 * This parameter must be a number between 50 and 432.
rajathr 0:34ee385f4d2d 621 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
rajathr 0:34ee385f4d2d 622 * output frequency is between 100 and 432 MHz.
rajathr 0:34ee385f4d2d 623 *
rajathr 0:34ee385f4d2d 624 * @param PLLI2SR: specifies the division factor for I2S clock
rajathr 0:34ee385f4d2d 625 * This parameter must be a number between 2 and 7.
rajathr 0:34ee385f4d2d 626 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
rajathr 0:34ee385f4d2d 627 * on the I2S clock frequency.
rajathr 0:34ee385f4d2d 628 *
rajathr 0:34ee385f4d2d 629 * @retval None
rajathr 0:34ee385f4d2d 630 */
rajathr 0:34ee385f4d2d 631 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM)
rajathr 0:34ee385f4d2d 632 {
rajathr 0:34ee385f4d2d 633 /* Check the parameters */
rajathr 0:34ee385f4d2d 634 assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
rajathr 0:34ee385f4d2d 635 assert_param(IS_RCC_PLLI2SM_VALUE_MORT(PLLI2SM));
rajathr 0:34ee385f4d2d 636 assert_param(IS_RCC_PLLI2SR_VALUE_MORT(PLLI2SR));
rajathr 0:34ee385f4d2d 637
rajathr 0:34ee385f4d2d 638 RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28) | PLLI2SM;
rajathr 0:34ee385f4d2d 639 }
rajathr 0:34ee385f4d2d 640 #endif /* STM32F411xE */
rajathr 0:34ee385f4d2d 641
rajathr 0:34ee385f4d2d 642 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 643 /**
rajathr 0:34ee385f4d2d 644 * @brief Configures the PLLI2S clock multiplication and division factors.
rajathr 0:34ee385f4d2d 645 *
rajathr 0:34ee385f4d2d 646 * @note This function can be used only for STM32F42xxx/43xxx devices
rajathr 0:34ee385f4d2d 647 *
rajathr 0:34ee385f4d2d 648 * @note This function must be used only when the PLLI2S is disabled.
rajathr 0:34ee385f4d2d 649 * @note PLLI2S clock source is common with the main PLL (configured in
rajathr 0:34ee385f4d2d 650 * RCC_PLLConfig function )
rajathr 0:34ee385f4d2d 651 *
rajathr 0:34ee385f4d2d 652 * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
rajathr 0:34ee385f4d2d 653 * This parameter must be a number between 50 and 432.
rajathr 0:34ee385f4d2d 654 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
rajathr 0:34ee385f4d2d 655 * output frequency is between 100 and 432 MHz.
rajathr 0:34ee385f4d2d 656 *
rajathr 0:34ee385f4d2d 657 * @param PLLI2SQ: specifies the division factor for SAI1 clock
rajathr 0:34ee385f4d2d 658 * This parameter must be a number between 2 and 15.
rajathr 0:34ee385f4d2d 659 *
rajathr 0:34ee385f4d2d 660 * @param PLLI2SR: specifies the division factor for I2S clock
rajathr 0:34ee385f4d2d 661 * This parameter must be a number between 2 and 7.
rajathr 0:34ee385f4d2d 662 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
rajathr 0:34ee385f4d2d 663 * on the I2S clock frequency.
rajathr 0:34ee385f4d2d 664 *
rajathr 0:34ee385f4d2d 665 * @retval None
rajathr 0:34ee385f4d2d 666 */
rajathr 0:34ee385f4d2d 667 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR)
rajathr 0:34ee385f4d2d 668 {
rajathr 0:34ee385f4d2d 669 /* Check the parameters */
rajathr 0:34ee385f4d2d 670 assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
rajathr 0:34ee385f4d2d 671 assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ));
rajathr 0:34ee385f4d2d 672 assert_param(IS_RCC_PLLI2SR_VALUE_MORT(PLLI2SR));
rajathr 0:34ee385f4d2d 673
rajathr 0:34ee385f4d2d 674 RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28);
rajathr 0:34ee385f4d2d 675 }
rajathr 0:34ee385f4d2d 676 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 677
rajathr 0:34ee385f4d2d 678 #if defined(STM32F412xG ) || defined(STM32F413_423xx) || defined(STM32F446xx)
rajathr 0:34ee385f4d2d 679 /**
rajathr 0:34ee385f4d2d 680 * @brief Configures the PLLI2S clock multiplication and division factors.
rajathr 0:34ee385f4d2d 681 *
rajathr 0:34ee385f4d2d 682 * @note This function can be used only for STM32F446xx devices
rajathr 0:34ee385f4d2d 683 *
rajathr 0:34ee385f4d2d 684 * @note This function must be used only when the PLLI2S is disabled.
rajathr 0:34ee385f4d2d 685 * @note PLLI2S clock source is common with the main PLL (configured in
rajathr 0:34ee385f4d2d 686 * RCC_PLLConfig function )
rajathr 0:34ee385f4d2d 687 *
rajathr 0:34ee385f4d2d 688 * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock
rajathr 0:34ee385f4d2d 689 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
rajathr 0:34ee385f4d2d 690 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
rajathr 0:34ee385f4d2d 691 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
rajathr 0:34ee385f4d2d 692 * of 2 MHz to limit PLLI2S jitter.
rajathr 0:34ee385f4d2d 693 *
rajathr 0:34ee385f4d2d 694 * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
rajathr 0:34ee385f4d2d 695 * This parameter must be a number between 50 and 432.
rajathr 0:34ee385f4d2d 696 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
rajathr 0:34ee385f4d2d 697 * output frequency is between 100 and 432 MHz.
rajathr 0:34ee385f4d2d 698 *
rajathr 0:34ee385f4d2d 699 * @param PLLI2SP: specifies the division factor for PLL 48Mhz clock output
rajathr 0:34ee385f4d2d 700 * This parameter must be a number in the range {2, 4, 6, or 8}.
rajathr 0:34ee385f4d2d 701 *
rajathr 0:34ee385f4d2d 702 * @param PLLI2SQ: specifies the division factor for SAI1 clock
rajathr 0:34ee385f4d2d 703 * This parameter must be a number between 2 and 15.
rajathr 0:34ee385f4d2d 704 *
rajathr 0:34ee385f4d2d 705 * @param PLLI2SR: specifies the division factor for I2S clock
rajathr 0:34ee385f4d2d 706 * This parameter must be a number between 2 and 7.
rajathr 0:34ee385f4d2d 707 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
rajathr 0:34ee385f4d2d 708 * on the I2S clock frequency.
rajathr 0:34ee385f4d2d 709 * @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices.
rajathr 0:34ee385f4d2d 710 *
rajathr 0:34ee385f4d2d 711 * @retval None
rajathr 0:34ee385f4d2d 712 */
rajathr 0:34ee385f4d2d 713 void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR)
rajathr 0:34ee385f4d2d 714 {
rajathr 0:34ee385f4d2d 715 /* Check the parameters */
rajathr 0:34ee385f4d2d 716 assert_param(IS_RCC_PLLI2SM_VALUE_MORT(PLLI2SM));
rajathr 0:34ee385f4d2d 717 assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
rajathr 0:34ee385f4d2d 718 assert_param(IS_RCC_PLLI2SP_VALUE_MORT(PLLI2SP));
rajathr 0:34ee385f4d2d 719 assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ));
rajathr 0:34ee385f4d2d 720 assert_param(IS_RCC_PLLI2SR_VALUE_MORT(PLLI2SR));
rajathr 0:34ee385f4d2d 721
rajathr 0:34ee385f4d2d 722 RCC->PLLI2SCFGR = PLLI2SM | (PLLI2SN << 6) | (((PLLI2SP >> 1) -1) << 16) | (PLLI2SQ << 24) | (PLLI2SR << 28);
rajathr 0:34ee385f4d2d 723 }
rajathr 0:34ee385f4d2d 724 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
rajathr 0:34ee385f4d2d 725
rajathr 0:34ee385f4d2d 726 /**
rajathr 0:34ee385f4d2d 727 * @brief Enables or disables the PLLI2S.
rajathr 0:34ee385f4d2d 728 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
rajathr 0:34ee385f4d2d 729 * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 730 * @retval None
rajathr 0:34ee385f4d2d 731 */
rajathr 0:34ee385f4d2d 732 void RCC_PLLI2SCmd(FunctionalState NewState)
rajathr 0:34ee385f4d2d 733 {
rajathr 0:34ee385f4d2d 734 /* Check the parameters */
rajathr 0:34ee385f4d2d 735 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 736 *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
rajathr 0:34ee385f4d2d 737 }
rajathr 0:34ee385f4d2d 738
rajathr 0:34ee385f4d2d 739 #if defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 740 /**
rajathr 0:34ee385f4d2d 741 * @brief Configures the PLLSAI clock multiplication and division factors.
rajathr 0:34ee385f4d2d 742 *
rajathr 0:34ee385f4d2d 743 * @note This function can be used only for STM32F469_479xx devices
rajathr 0:34ee385f4d2d 744 *
rajathr 0:34ee385f4d2d 745 * @note This function must be used only when the PLLSAI is disabled.
rajathr 0:34ee385f4d2d 746 * @note PLLSAI clock source is common with the main PLL (configured in
rajathr 0:34ee385f4d2d 747 * RCC_PLLConfig function )
rajathr 0:34ee385f4d2d 748 *
rajathr 0:34ee385f4d2d 749 * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
rajathr 0:34ee385f4d2d 750 * This parameter must be a number between 50 and 432.
rajathr 0:34ee385f4d2d 751 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
rajathr 0:34ee385f4d2d 752 * output frequency is between 100 and 432 MHz.
rajathr 0:34ee385f4d2d 753 *
rajathr 0:34ee385f4d2d 754 * @param PLLSAIP: specifies the division factor for PLL 48Mhz clock output
rajathr 0:34ee385f4d2d 755 * This parameter must be a number in the range {2, 4, 6, or 8}..
rajathr 0:34ee385f4d2d 756 *
rajathr 0:34ee385f4d2d 757 * @param PLLSAIQ: specifies the division factor for SAI1 clock
rajathr 0:34ee385f4d2d 758 * This parameter must be a number between 2 and 15.
rajathr 0:34ee385f4d2d 759 *
rajathr 0:34ee385f4d2d 760 * @param PLLSAIR: specifies the division factor for LTDC clock
rajathr 0:34ee385f4d2d 761 * This parameter must be a number between 2 and 7.
rajathr 0:34ee385f4d2d 762 *
rajathr 0:34ee385f4d2d 763 * @retval None
rajathr 0:34ee385f4d2d 764 */
rajathr 0:34ee385f4d2d 765 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR)
rajathr 0:34ee385f4d2d 766 {
rajathr 0:34ee385f4d2d 767 /* Check the parameters */
rajathr 0:34ee385f4d2d 768 assert_param(IS_RCC_PLLSAIN_VALUE_MORT(PLLSAIN));
rajathr 0:34ee385f4d2d 769 assert_param(IS_RCC_PLLSAIP_VALUE_MORT(PLLSAIP));
rajathr 0:34ee385f4d2d 770 assert_param(IS_RCC_PLLSAIQ_VALUE_MORT(PLLSAIQ));
rajathr 0:34ee385f4d2d 771 assert_param(IS_RCC_PLLSAIR_VALUE_MORT(PLLSAIR));
rajathr 0:34ee385f4d2d 772
rajathr 0:34ee385f4d2d 773 RCC->PLLSAICFGR = (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24) | (PLLSAIR << 28);
rajathr 0:34ee385f4d2d 774 }
rajathr 0:34ee385f4d2d 775 #endif /* STM32F469_479xx */
rajathr 0:34ee385f4d2d 776
rajathr 0:34ee385f4d2d 777 #if defined(STM32F446xx)
rajathr 0:34ee385f4d2d 778 /**
rajathr 0:34ee385f4d2d 779 * @brief Configures the PLLSAI clock multiplication and division factors.
rajathr 0:34ee385f4d2d 780 *
rajathr 0:34ee385f4d2d 781 * @note This function can be used only for STM32F446xx devices
rajathr 0:34ee385f4d2d 782 *
rajathr 0:34ee385f4d2d 783 * @note This function must be used only when the PLLSAI is disabled.
rajathr 0:34ee385f4d2d 784 * @note PLLSAI clock source is common with the main PLL (configured in
rajathr 0:34ee385f4d2d 785 * RCC_PLLConfig function )
rajathr 0:34ee385f4d2d 786 *
rajathr 0:34ee385f4d2d 787 * @param PLLSAIM: specifies the division factor for PLLSAI VCO input clock
rajathr 0:34ee385f4d2d 788 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
rajathr 0:34ee385f4d2d 789 * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
rajathr 0:34ee385f4d2d 790 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
rajathr 0:34ee385f4d2d 791 * of 2 MHz to limit PLLSAI jitter.
rajathr 0:34ee385f4d2d 792 *
rajathr 0:34ee385f4d2d 793 * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
rajathr 0:34ee385f4d2d 794 * This parameter must be a number between 50 and 432.
rajathr 0:34ee385f4d2d 795 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
rajathr 0:34ee385f4d2d 796 * output frequency is between 100 and 432 MHz.
rajathr 0:34ee385f4d2d 797 *
rajathr 0:34ee385f4d2d 798 * @param PLLSAIP: specifies the division factor for PLL 48Mhz clock output
rajathr 0:34ee385f4d2d 799 * This parameter must be a number in the range {2, 4, 6, or 8}.
rajathr 0:34ee385f4d2d 800 *
rajathr 0:34ee385f4d2d 801 * @param PLLSAIQ: specifies the division factor for SAI1 clock
rajathr 0:34ee385f4d2d 802 * This parameter must be a number between 2 and 15.
rajathr 0:34ee385f4d2d 803 *
rajathr 0:34ee385f4d2d 804 * @retval None
rajathr 0:34ee385f4d2d 805 */
rajathr 0:34ee385f4d2d 806 void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ)
rajathr 0:34ee385f4d2d 807 {
rajathr 0:34ee385f4d2d 808 /* Check the parameters */
rajathr 0:34ee385f4d2d 809 assert_param(IS_RCC_PLLSAIM_VALUE_MORT(PLLSAIM));
rajathr 0:34ee385f4d2d 810 assert_param(IS_RCC_PLLSAIN_VALUE_MORT(PLLSAIN));
rajathr 0:34ee385f4d2d 811 assert_param(IS_RCC_PLLSAIP_VALUE_MORT(PLLSAIP));
rajathr 0:34ee385f4d2d 812 assert_param(IS_RCC_PLLSAIQ_VALUE_MORT(PLLSAIQ));
rajathr 0:34ee385f4d2d 813
rajathr 0:34ee385f4d2d 814 RCC->PLLSAICFGR = PLLSAIM | (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24);
rajathr 0:34ee385f4d2d 815 }
rajathr 0:34ee385f4d2d 816 #endif /* STM32F446xx */
rajathr 0:34ee385f4d2d 817
rajathr 0:34ee385f4d2d 818 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
rajathr 0:34ee385f4d2d 819 /**
rajathr 0:34ee385f4d2d 820 * @brief Configures the PLLSAI clock multiplication and division factors.
rajathr 0:34ee385f4d2d 821 *
rajathr 0:34ee385f4d2d 822 * @note This function can be used only for STM32F42xxx/43xxx devices
rajathr 0:34ee385f4d2d 823 *
rajathr 0:34ee385f4d2d 824 * @note This function must be used only when the PLLSAI is disabled.
rajathr 0:34ee385f4d2d 825 * @note PLLSAI clock source is common with the main PLL (configured in
rajathr 0:34ee385f4d2d 826 * RCC_PLLConfig function )
rajathr 0:34ee385f4d2d 827 *
rajathr 0:34ee385f4d2d 828 * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
rajathr 0:34ee385f4d2d 829 * This parameter must be a number between 50 and 432.
rajathr 0:34ee385f4d2d 830 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
rajathr 0:34ee385f4d2d 831 * output frequency is between 100 and 432 MHz.
rajathr 0:34ee385f4d2d 832 *
rajathr 0:34ee385f4d2d 833 * @param PLLSAIQ: specifies the division factor for SAI1 clock
rajathr 0:34ee385f4d2d 834 * This parameter must be a number between 2 and 15.
rajathr 0:34ee385f4d2d 835 *
rajathr 0:34ee385f4d2d 836 * @param PLLSAIR: specifies the division factor for LTDC clock
rajathr 0:34ee385f4d2d 837 * This parameter must be a number between 2 and 7.
rajathr 0:34ee385f4d2d 838 *
rajathr 0:34ee385f4d2d 839 * @retval None
rajathr 0:34ee385f4d2d 840 */
rajathr 0:34ee385f4d2d 841 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
rajathr 0:34ee385f4d2d 842 {
rajathr 0:34ee385f4d2d 843 /* Check the parameters */
rajathr 0:34ee385f4d2d 844 assert_param(IS_RCC_PLLSAIN_VALUE_MORT(PLLSAIN));
rajathr 0:34ee385f4d2d 845 assert_param(IS_RCC_PLLSAIR_VALUE_MORT(PLLSAIR));
rajathr 0:34ee385f4d2d 846 assert_param(IS_RCC_PLLSAIQ_VALUE_MORT(PLLSAIQ));
rajathr 0:34ee385f4d2d 847
rajathr 0:34ee385f4d2d 848 RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28);
rajathr 0:34ee385f4d2d 849 }
rajathr 0:34ee385f4d2d 850 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
rajathr 0:34ee385f4d2d 851
rajathr 0:34ee385f4d2d 852 /**
rajathr 0:34ee385f4d2d 853 * @brief Enables or disables the PLLSAI.
rajathr 0:34ee385f4d2d 854 *
rajathr 0:34ee385f4d2d 855 * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices
rajathr 0:34ee385f4d2d 856 *
rajathr 0:34ee385f4d2d 857 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
rajathr 0:34ee385f4d2d 858 * @param NewState: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 859 * @retval None
rajathr 0:34ee385f4d2d 860 */
rajathr 0:34ee385f4d2d 861 void RCC_PLLSAICmd(FunctionalState NewState)
rajathr 0:34ee385f4d2d 862 {
rajathr 0:34ee385f4d2d 863 /* Check the parameters */
rajathr 0:34ee385f4d2d 864 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 865 *(__IO uint32_t *) CR_PLLSAION_BB = (uint32_t)NewState;
rajathr 0:34ee385f4d2d 866 }
rajathr 0:34ee385f4d2d 867
rajathr 0:34ee385f4d2d 868 /**
rajathr 0:34ee385f4d2d 869 * @brief Enables or disables the Clock Security System.
rajathr 0:34ee385f4d2d 870 * @note If a failure is detected on the HSE oscillator clock, this oscillator
rajathr 0:34ee385f4d2d 871 * is automatically disabled and an interrupt is generated to inform the
rajathr 0:34ee385f4d2d 872 * software about the failure (Clock Security System Interrupt, CSSI),
rajathr 0:34ee385f4d2d 873 * allowing the MCU to perform rescue operations. The CSSI is linked to
rajathr 0:34ee385f4d2d 874 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
rajathr 0:34ee385f4d2d 875 * @param NewState: new state of the Clock Security System.
rajathr 0:34ee385f4d2d 876 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 877 * @retval None
rajathr 0:34ee385f4d2d 878 */
rajathr 0:34ee385f4d2d 879 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
rajathr 0:34ee385f4d2d 880 {
rajathr 0:34ee385f4d2d 881 /* Check the parameters */
rajathr 0:34ee385f4d2d 882 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 883 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
rajathr 0:34ee385f4d2d 884 }
rajathr 0:34ee385f4d2d 885
rajathr 0:34ee385f4d2d 886 /**
rajathr 0:34ee385f4d2d 887 * @brief Selects the clock source to output on MCO1 pin(PA8).
rajathr 0:34ee385f4d2d 888 * @note PA8 should be configured in alternate function mode.
rajathr 0:34ee385f4d2d 889 * @param RCC_MCO1Source: specifies the clock source to output.
rajathr 0:34ee385f4d2d 890 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 891 * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
rajathr 0:34ee385f4d2d 892 * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
rajathr 0:34ee385f4d2d 893 * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
rajathr 0:34ee385f4d2d 894 * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
rajathr 0:34ee385f4d2d 895 * @param RCC_MCO1Div: specifies the MCO1 prescaler.
rajathr 0:34ee385f4d2d 896 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 897 * @arg RCC_MCO1Div_1: no division applied to MCO1 clock
rajathr 0:34ee385f4d2d 898 * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock
rajathr 0:34ee385f4d2d 899 * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock
rajathr 0:34ee385f4d2d 900 * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock
rajathr 0:34ee385f4d2d 901 * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock
rajathr 0:34ee385f4d2d 902 * @retval None
rajathr 0:34ee385f4d2d 903 */
rajathr 0:34ee385f4d2d 904 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
rajathr 0:34ee385f4d2d 905 {
rajathr 0:34ee385f4d2d 906 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 907
rajathr 0:34ee385f4d2d 908 /* Check the parameters */
rajathr 0:34ee385f4d2d 909 assert_param(IS_RCC_MCO1SOURCE_MORT(RCC_MCO1Source));
rajathr 0:34ee385f4d2d 910 assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));
rajathr 0:34ee385f4d2d 911
rajathr 0:34ee385f4d2d 912 tmpreg = RCC->CFGR;
rajathr 0:34ee385f4d2d 913
rajathr 0:34ee385f4d2d 914 /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
rajathr 0:34ee385f4d2d 915 tmpreg &= CFGR_MCO1_RESET_MASK;
rajathr 0:34ee385f4d2d 916
rajathr 0:34ee385f4d2d 917 /* Select MCO1 clock source and prescaler */
rajathr 0:34ee385f4d2d 918 tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
rajathr 0:34ee385f4d2d 919
rajathr 0:34ee385f4d2d 920 /* Store the new value */
rajathr 0:34ee385f4d2d 921 RCC->CFGR = tmpreg;
rajathr 0:34ee385f4d2d 922
rajathr 0:34ee385f4d2d 923 #if defined(STM32F410xx)
rajathr 0:34ee385f4d2d 924 RCC_MCO1Cmd(ENABLE);
rajathr 0:34ee385f4d2d 925 #endif /* STM32F410xx */
rajathr 0:34ee385f4d2d 926 }
rajathr 0:34ee385f4d2d 927
rajathr 0:34ee385f4d2d 928 /**
rajathr 0:34ee385f4d2d 929 * @brief Selects the clock source to output on MCO2 pin(PC9).
rajathr 0:34ee385f4d2d 930 * @note PC9 should be configured in alternate function mode.
rajathr 0:34ee385f4d2d 931 * @param RCC_MCO2Source: specifies the clock source to output.
rajathr 0:34ee385f4d2d 932 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 933 * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
rajathr 0:34ee385f4d2d 934 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
rajathr 0:34ee385f4d2d 935 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410xx devices
rajathr 0:34ee385f4d2d 936 * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
rajathr 0:34ee385f4d2d 937 * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
rajathr 0:34ee385f4d2d 938 * @param RCC_MCO2Div: specifies the MCO2 prescaler.
rajathr 0:34ee385f4d2d 939 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 940 * @arg RCC_MCO2Div_1: no division applied to MCO2 clock
rajathr 0:34ee385f4d2d 941 * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock
rajathr 0:34ee385f4d2d 942 * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
rajathr 0:34ee385f4d2d 943 * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
rajathr 0:34ee385f4d2d 944 * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
rajathr 0:34ee385f4d2d 945 * @note For STM32F410xx devices to output I2SCLK clock on MCO2 you should have
rajathr 0:34ee385f4d2d 946 * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
rajathr 0:34ee385f4d2d 947 * @retval None
rajathr 0:34ee385f4d2d 948 */
rajathr 0:34ee385f4d2d 949 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
rajathr 0:34ee385f4d2d 950 {
rajathr 0:34ee385f4d2d 951 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 952
rajathr 0:34ee385f4d2d 953 /* Check the parameters */
rajathr 0:34ee385f4d2d 954 assert_param(IS_RCC_MCO2SOURCE_MORT(RCC_MCO2Source));
rajathr 0:34ee385f4d2d 955 assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
rajathr 0:34ee385f4d2d 956
rajathr 0:34ee385f4d2d 957 tmpreg = RCC->CFGR;
rajathr 0:34ee385f4d2d 958
rajathr 0:34ee385f4d2d 959 /* Clear MCO2 and MCO2PRE[2:0] bits */
rajathr 0:34ee385f4d2d 960 tmpreg &= CFGR_MCO2_RESET_MASK;
rajathr 0:34ee385f4d2d 961
rajathr 0:34ee385f4d2d 962 /* Select MCO2 clock source and prescaler */
rajathr 0:34ee385f4d2d 963 tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
rajathr 0:34ee385f4d2d 964
rajathr 0:34ee385f4d2d 965 /* Store the new value */
rajathr 0:34ee385f4d2d 966 RCC->CFGR = tmpreg;
rajathr 0:34ee385f4d2d 967
rajathr 0:34ee385f4d2d 968 #if defined(STM32F410xx)
rajathr 0:34ee385f4d2d 969 RCC_MCO2Cmd(ENABLE);
rajathr 0:34ee385f4d2d 970 #endif /* STM32F410xx */
rajathr 0:34ee385f4d2d 971 }
rajathr 0:34ee385f4d2d 972
rajathr 0:34ee385f4d2d 973 /**
rajathr 0:34ee385f4d2d 974 * @}
rajathr 0:34ee385f4d2d 975 */
rajathr 0:34ee385f4d2d 976
rajathr 0:34ee385f4d2d 977 /** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
rajathr 0:34ee385f4d2d 978 * @brief System, AHB and APB busses clocks configuration functions
rajathr 0:34ee385f4d2d 979 *
rajathr 0:34ee385f4d2d 980 @verbatim
rajathr 0:34ee385f4d2d 981 ===============================================================================
rajathr 0:34ee385f4d2d 982 ##### System, AHB and APB busses clocks configuration functions #####
rajathr 0:34ee385f4d2d 983 ===============================================================================
rajathr 0:34ee385f4d2d 984 [..]
rajathr 0:34ee385f4d2d 985 This section provide functions allowing to configure the System, AHB, APB1 and
rajathr 0:34ee385f4d2d 986 APB2 busses clocks.
rajathr 0:34ee385f4d2d 987
rajathr 0:34ee385f4d2d 988 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
rajathr 0:34ee385f4d2d 989 HSE and PLL.
rajathr 0:34ee385f4d2d 990 The AHB clock (HCLK) is derived from System clock through configurable
rajathr 0:34ee385f4d2d 991 prescaler and used to clock the CPU, memory and peripherals mapped
rajathr 0:34ee385f4d2d 992 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
rajathr 0:34ee385f4d2d 993 from AHB clock through configurable prescalers and used to clock
rajathr 0:34ee385f4d2d 994 the peripherals mapped on these busses. You can use
rajathr 0:34ee385f4d2d 995 "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
rajathr 0:34ee385f4d2d 996
rajathr 0:34ee385f4d2d 997 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
rajathr 0:34ee385f4d2d 998 (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
rajathr 0:34ee385f4d2d 999 from an external clock mapped on the I2S_CKIN pin.
rajathr 0:34ee385f4d2d 1000 You have to use RCC_I2SCLKConfig() function to configure this clock.
rajathr 0:34ee385f4d2d 1001 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
rajathr 0:34ee385f4d2d 1002 divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
rajathr 0:34ee385f4d2d 1003 functions to configure this clock.
rajathr 0:34ee385f4d2d 1004 (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
rajathr 0:34ee385f4d2d 1005 to work correctly, while the SDIO require a frequency equal or lower than
rajathr 0:34ee385f4d2d 1006 to 48. This clock is derived of the main PLL through PLLQ divider.
rajathr 0:34ee385f4d2d 1007 (+@) IWDG clock which is always the LSI clock.
rajathr 0:34ee385f4d2d 1008
rajathr 0:34ee385f4d2d 1009 (#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency
rajathr 0:34ee385f4d2d 1010 of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending
rajathr 0:34ee385f4d2d 1011 on the device voltage range, the maximum frequency should be adapted accordingly:
rajathr 0:34ee385f4d2d 1012 +-------------------------------------------------------------------------------------+
rajathr 0:34ee385f4d2d 1013 | Latency | HCLK clock frequency (MHz) |
rajathr 0:34ee385f4d2d 1014 | |---------------------------------------------------------------------|
rajathr 0:34ee385f4d2d 1015 | | voltage range | voltage range | voltage range | voltage range |
rajathr 0:34ee385f4d2d 1016 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
rajathr 0:34ee385f4d2d 1017 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1018 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
rajathr 0:34ee385f4d2d 1019 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1020 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
rajathr 0:34ee385f4d2d 1021 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1022 |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
rajathr 0:34ee385f4d2d 1023 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1024 |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
rajathr 0:34ee385f4d2d 1025 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1026 |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
rajathr 0:34ee385f4d2d 1027 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1028 |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
rajathr 0:34ee385f4d2d 1029 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1030 |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
rajathr 0:34ee385f4d2d 1031 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1032 |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
rajathr 0:34ee385f4d2d 1033 +---------------|----------------|----------------|-----------------|-----------------+
rajathr 0:34ee385f4d2d 1034 (#) For STM32F42xxx/43xxx/469xx/479xx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz,
rajathr 0:34ee385f4d2d 1035 PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum
rajathr 0:34ee385f4d2d 1036 frequency should be adapted accordingly:
rajathr 0:34ee385f4d2d 1037 +-------------------------------------------------------------------------------------+
rajathr 0:34ee385f4d2d 1038 | Latency | HCLK clock frequency (MHz) |
rajathr 0:34ee385f4d2d 1039 | |---------------------------------------------------------------------|
rajathr 0:34ee385f4d2d 1040 | | voltage range | voltage range | voltage range | voltage range |
rajathr 0:34ee385f4d2d 1041 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
rajathr 0:34ee385f4d2d 1042 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1043 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
rajathr 0:34ee385f4d2d 1044 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1045 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
rajathr 0:34ee385f4d2d 1046 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1047 |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
rajathr 0:34ee385f4d2d 1048 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1049 |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
rajathr 0:34ee385f4d2d 1050 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1051 |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
rajathr 0:34ee385f4d2d 1052 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1053 |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
rajathr 0:34ee385f4d2d 1054 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1055 |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
rajathr 0:34ee385f4d2d 1056 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1057 |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
rajathr 0:34ee385f4d2d 1058 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1059 |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168|
rajathr 0:34ee385f4d2d 1060 +-------------------------------------------------------------------------------------+
rajathr 0:34ee385f4d2d 1061
rajathr 0:34ee385f4d2d 1062 (#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
rajathr 0:34ee385f4d2d 1063 PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum
rajathr 0:34ee385f4d2d 1064 frequency should be adapted accordingly:
rajathr 0:34ee385f4d2d 1065 +-------------------------------------------------------------------------------------+
rajathr 0:34ee385f4d2d 1066 | Latency | HCLK clock frequency (MHz) |
rajathr 0:34ee385f4d2d 1067 | |---------------------------------------------------------------------|
rajathr 0:34ee385f4d2d 1068 | | voltage range | voltage range | voltage range | voltage range |
rajathr 0:34ee385f4d2d 1069 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
rajathr 0:34ee385f4d2d 1070 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1071 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
rajathr 0:34ee385f4d2d 1072 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1073 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
rajathr 0:34ee385f4d2d 1074 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1075 |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
rajathr 0:34ee385f4d2d 1076 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1077 |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 |
rajathr 0:34ee385f4d2d 1078 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1079 |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
rajathr 0:34ee385f4d2d 1080 +-------------------------------------------------------------------------------------+
rajathr 0:34ee385f4d2d 1081
rajathr 0:34ee385f4d2d 1082 (#) For STM32F410xx/STM32F411xE devices, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
rajathr 0:34ee385f4d2d 1083 PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum
rajathr 0:34ee385f4d2d 1084 frequency should be adapted accordingly:
rajathr 0:34ee385f4d2d 1085 +-------------------------------------------------------------------------------------+
rajathr 0:34ee385f4d2d 1086 | Latency | HCLK clock frequency (MHz) |
rajathr 0:34ee385f4d2d 1087 | |---------------------------------------------------------------------|
rajathr 0:34ee385f4d2d 1088 | | voltage range | voltage range | voltage range | voltage range |
rajathr 0:34ee385f4d2d 1089 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
rajathr 0:34ee385f4d2d 1090 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1091 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
rajathr 0:34ee385f4d2d 1092 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1093 |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
rajathr 0:34ee385f4d2d 1094 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1095 |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
rajathr 0:34ee385f4d2d 1096 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1097 |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
rajathr 0:34ee385f4d2d 1098 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1099 |4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 |
rajathr 0:34ee385f4d2d 1100 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1101 |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 |
rajathr 0:34ee385f4d2d 1102 |---------------|----------------|----------------|-----------------|-----------------|
rajathr 0:34ee385f4d2d 1103 |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 |
rajathr 0:34ee385f4d2d 1104 +-------------------------------------------------------------------------------------+
rajathr 0:34ee385f4d2d 1105
rajathr 0:34ee385f4d2d 1106 -@- On STM32F405xx/407xx and STM32F415xx/417xx devices:
rajathr 0:34ee385f4d2d 1107 (++) when VOS = '0', the maximum value of fHCLK = 144MHz.
rajathr 0:34ee385f4d2d 1108 (++) when VOS = '1', the maximum value of fHCLK = 168MHz.
rajathr 0:34ee385f4d2d 1109 [..]
rajathr 0:34ee385f4d2d 1110 On STM32F42xxx/43xxx/469xx/479xx devices:
rajathr 0:34ee385f4d2d 1111 (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz.
rajathr 0:34ee385f4d2d 1112 (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz.
rajathr 0:34ee385f4d2d 1113 (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz
rajathr 0:34ee385f4d2d 1114 [..]
rajathr 0:34ee385f4d2d 1115 On STM32F401x devices:
rajathr 0:34ee385f4d2d 1116 (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz.
rajathr 0:34ee385f4d2d 1117 (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz.
rajathr 0:34ee385f4d2d 1118 On STM32F410xx/STM32F411xE devices:
rajathr 0:34ee385f4d2d 1119 (++) when VOS[1:0] = '0x01' the maximum value of fHCLK is 64MHz.
rajathr 0:34ee385f4d2d 1120 (++) when VOS[1:0] = '0x10' the maximum value of fHCLK is 84MHz.
rajathr 0:34ee385f4d2d 1121 (++) when VOS[1:0] = '0x11' the maximum value of fHCLK is 100MHz.
rajathr 0:34ee385f4d2d 1122
rajathr 0:34ee385f4d2d 1123 You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
rajathr 0:34ee385f4d2d 1124
rajathr 0:34ee385f4d2d 1125 @endverbatim
rajathr 0:34ee385f4d2d 1126 * @{
rajathr 0:34ee385f4d2d 1127 */
rajathr 0:34ee385f4d2d 1128
rajathr 0:34ee385f4d2d 1129 /**
rajathr 0:34ee385f4d2d 1130 * @brief Configures the system clock (SYSCLK).
rajathr 0:34ee385f4d2d 1131 * @note The HSI is used (enabled by hardware) as system clock source after
rajathr 0:34ee385f4d2d 1132 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
rajathr 0:34ee385f4d2d 1133 * of failure of the HSE used directly or indirectly as system clock
rajathr 0:34ee385f4d2d 1134 * (if the Clock Security System CSS is enabled).
rajathr 0:34ee385f4d2d 1135 * @note A switch from one clock source to another occurs only if the target
rajathr 0:34ee385f4d2d 1136 * clock source is ready (clock stable after startup delay or PLL locked).
rajathr 0:34ee385f4d2d 1137 * If a clock source which is not yet ready is selected, the switch will
rajathr 0:34ee385f4d2d 1138 * occur when the clock source will be ready.
rajathr 0:34ee385f4d2d 1139 * You can use RCC_GetSYSCLKSource() function to know which clock is
rajathr 0:34ee385f4d2d 1140 * currently used as system clock source.
rajathr 0:34ee385f4d2d 1141 * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
rajathr 0:34ee385f4d2d 1142 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1143 * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
rajathr 0:34ee385f4d2d 1144 * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
rajathr 0:34ee385f4d2d 1145 * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source (RCC_SYSCLKSource_PLLPCLK for STM32F446xx devices)
rajathr 0:34ee385f4d2d 1146 * @arg RCC_SYSCLKSource_PLLRCLK: PLL R selected as system clock source only for STM32F412xG, STM32F413_423xx and STM32F446xx devices
rajathr 0:34ee385f4d2d 1147 * @retval None
rajathr 0:34ee385f4d2d 1148 */
rajathr 0:34ee385f4d2d 1149 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
rajathr 0:34ee385f4d2d 1150 {
rajathr 0:34ee385f4d2d 1151 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1152
rajathr 0:34ee385f4d2d 1153 /* Check the parameters */
rajathr 0:34ee385f4d2d 1154 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
rajathr 0:34ee385f4d2d 1155
rajathr 0:34ee385f4d2d 1156 tmpreg = RCC->CFGR;
rajathr 0:34ee385f4d2d 1157
rajathr 0:34ee385f4d2d 1158 /* Clear SW[1:0] bits */
rajathr 0:34ee385f4d2d 1159 tmpreg &= ~RCC_CFGR_SW_MORT;
rajathr 0:34ee385f4d2d 1160
rajathr 0:34ee385f4d2d 1161 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
rajathr 0:34ee385f4d2d 1162 tmpreg |= RCC_SYSCLKSource;
rajathr 0:34ee385f4d2d 1163
rajathr 0:34ee385f4d2d 1164 /* Store the new value */
rajathr 0:34ee385f4d2d 1165 RCC->CFGR = tmpreg;
rajathr 0:34ee385f4d2d 1166 }
rajathr 0:34ee385f4d2d 1167
rajathr 0:34ee385f4d2d 1168 /**
rajathr 0:34ee385f4d2d 1169 * @brief Returns the clock source used as system clock.
rajathr 0:34ee385f4d2d 1170 * @param None
rajathr 0:34ee385f4d2d 1171 * @retval The clock source used as system clock. The returned value can be one
rajathr 0:34ee385f4d2d 1172 * of the following:
rajathr 0:34ee385f4d2d 1173 * - 0x00: HSI used as system clock
rajathr 0:34ee385f4d2d 1174 * - 0x04: HSE used as system clock
rajathr 0:34ee385f4d2d 1175 * - 0x08: PLL used as system clock (PLL P for STM32F446xx devices)
rajathr 0:34ee385f4d2d 1176 * - 0x0C: PLL R used as system clock (only for STM32F412xG, STM32F413_423xx and STM32F446xx devices)
rajathr 0:34ee385f4d2d 1177 */
rajathr 0:34ee385f4d2d 1178 uint8_t RCC_GetSYSCLKSource(void)
rajathr 0:34ee385f4d2d 1179 {
rajathr 0:34ee385f4d2d 1180 return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS_MORT));
rajathr 0:34ee385f4d2d 1181 }
rajathr 0:34ee385f4d2d 1182
rajathr 0:34ee385f4d2d 1183 /**
rajathr 0:34ee385f4d2d 1184 * @brief Configures the AHB clock (HCLK).
rajathr 0:34ee385f4d2d 1185 * @note Depending on the device voltage range, the software has to set correctly
rajathr 0:34ee385f4d2d 1186 * these bits to ensure that HCLK not exceed the maximum allowed frequency
rajathr 0:34ee385f4d2d 1187 * (for more details refer to section above
rajathr 0:34ee385f4d2d 1188 * "CPU, AHB and APB busses clocks configuration functions")
rajathr 0:34ee385f4d2d 1189 * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
rajathr 0:34ee385f4d2d 1190 * the system clock (SYSCLK).
rajathr 0:34ee385f4d2d 1191 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1192 * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
rajathr 0:34ee385f4d2d 1193 * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
rajathr 0:34ee385f4d2d 1194 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
rajathr 0:34ee385f4d2d 1195 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
rajathr 0:34ee385f4d2d 1196 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
rajathr 0:34ee385f4d2d 1197 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
rajathr 0:34ee385f4d2d 1198 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
rajathr 0:34ee385f4d2d 1199 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
rajathr 0:34ee385f4d2d 1200 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
rajathr 0:34ee385f4d2d 1201 * @retval None
rajathr 0:34ee385f4d2d 1202 */
rajathr 0:34ee385f4d2d 1203 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
rajathr 0:34ee385f4d2d 1204 {
rajathr 0:34ee385f4d2d 1205 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1206
rajathr 0:34ee385f4d2d 1207 /* Check the parameters */
rajathr 0:34ee385f4d2d 1208 assert_param(IS_RCC_HCLK_MORT(RCC_SYSCLK));
rajathr 0:34ee385f4d2d 1209
rajathr 0:34ee385f4d2d 1210 tmpreg = RCC->CFGR;
rajathr 0:34ee385f4d2d 1211
rajathr 0:34ee385f4d2d 1212 /* Clear HPRE[3:0] bits */
rajathr 0:34ee385f4d2d 1213 tmpreg &= ~RCC_CFGR_HPRE_MORT;
rajathr 0:34ee385f4d2d 1214
rajathr 0:34ee385f4d2d 1215 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
rajathr 0:34ee385f4d2d 1216 tmpreg |= RCC_SYSCLK;
rajathr 0:34ee385f4d2d 1217
rajathr 0:34ee385f4d2d 1218 /* Store the new value */
rajathr 0:34ee385f4d2d 1219 RCC->CFGR = tmpreg;
rajathr 0:34ee385f4d2d 1220 }
rajathr 0:34ee385f4d2d 1221
rajathr 0:34ee385f4d2d 1222 /**
rajathr 0:34ee385f4d2d 1223 * @brief Configures the Low Speed APB clock (PCLK1).
rajathr 0:34ee385f4d2d 1224 * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
rajathr 0:34ee385f4d2d 1225 * the AHB clock (HCLK).
rajathr 0:34ee385f4d2d 1226 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1227 * @arg RCC_HCLK_Div1: APB1 clock = HCLK
rajathr 0:34ee385f4d2d 1228 * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
rajathr 0:34ee385f4d2d 1229 * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
rajathr 0:34ee385f4d2d 1230 * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
rajathr 0:34ee385f4d2d 1231 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
rajathr 0:34ee385f4d2d 1232 * @retval None
rajathr 0:34ee385f4d2d 1233 */
rajathr 0:34ee385f4d2d 1234 void RCC_PCLK1Config(uint32_t RCC_HCLK)
rajathr 0:34ee385f4d2d 1235 {
rajathr 0:34ee385f4d2d 1236 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1237
rajathr 0:34ee385f4d2d 1238 /* Check the parameters */
rajathr 0:34ee385f4d2d 1239 assert_param(IS_RCC_PCLK_MORT(RCC_HCLK));
rajathr 0:34ee385f4d2d 1240
rajathr 0:34ee385f4d2d 1241 tmpreg = RCC->CFGR;
rajathr 0:34ee385f4d2d 1242
rajathr 0:34ee385f4d2d 1243 /* Clear PPRE1[2:0] bits */
rajathr 0:34ee385f4d2d 1244 tmpreg &= ~RCC_CFGR_PPRE1_MORT;
rajathr 0:34ee385f4d2d 1245
rajathr 0:34ee385f4d2d 1246 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
rajathr 0:34ee385f4d2d 1247 tmpreg |= RCC_HCLK;
rajathr 0:34ee385f4d2d 1248
rajathr 0:34ee385f4d2d 1249 /* Store the new value */
rajathr 0:34ee385f4d2d 1250 RCC->CFGR = tmpreg;
rajathr 0:34ee385f4d2d 1251 }
rajathr 0:34ee385f4d2d 1252
rajathr 0:34ee385f4d2d 1253 /**
rajathr 0:34ee385f4d2d 1254 * @brief Configures the High Speed APB clock (PCLK2).
rajathr 0:34ee385f4d2d 1255 * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
rajathr 0:34ee385f4d2d 1256 * the AHB clock (HCLK).
rajathr 0:34ee385f4d2d 1257 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1258 * @arg RCC_HCLK_Div1: APB2 clock = HCLK
rajathr 0:34ee385f4d2d 1259 * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
rajathr 0:34ee385f4d2d 1260 * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
rajathr 0:34ee385f4d2d 1261 * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
rajathr 0:34ee385f4d2d 1262 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
rajathr 0:34ee385f4d2d 1263 * @retval None
rajathr 0:34ee385f4d2d 1264 */
rajathr 0:34ee385f4d2d 1265 void RCC_PCLK2Config(uint32_t RCC_HCLK)
rajathr 0:34ee385f4d2d 1266 {
rajathr 0:34ee385f4d2d 1267 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1268
rajathr 0:34ee385f4d2d 1269 /* Check the parameters */
rajathr 0:34ee385f4d2d 1270 assert_param(IS_RCC_PCLK_MORT(RCC_HCLK));
rajathr 0:34ee385f4d2d 1271
rajathr 0:34ee385f4d2d 1272 tmpreg = RCC->CFGR;
rajathr 0:34ee385f4d2d 1273
rajathr 0:34ee385f4d2d 1274 /* Clear PPRE2[2:0] bits */
rajathr 0:34ee385f4d2d 1275 tmpreg &= ~RCC_CFGR_PPRE2_MORT;
rajathr 0:34ee385f4d2d 1276
rajathr 0:34ee385f4d2d 1277 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
rajathr 0:34ee385f4d2d 1278 tmpreg |= RCC_HCLK << 3;
rajathr 0:34ee385f4d2d 1279
rajathr 0:34ee385f4d2d 1280 /* Store the new value */
rajathr 0:34ee385f4d2d 1281 RCC->CFGR = tmpreg;
rajathr 0:34ee385f4d2d 1282 }
rajathr 0:34ee385f4d2d 1283
rajathr 0:34ee385f4d2d 1284 /**
rajathr 0:34ee385f4d2d 1285 * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK,
rajathr 0:34ee385f4d2d 1286 * PCLK1 and PCLK2.
rajathr 0:34ee385f4d2d 1287 *
rajathr 0:34ee385f4d2d 1288 * @note The system frequency computed by this function is not the real
rajathr 0:34ee385f4d2d 1289 * frequency in the chip. It is calculated based on the predefined
rajathr 0:34ee385f4d2d 1290 * constant and the selected clock source:
rajathr 0:34ee385f4d2d 1291 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
rajathr 0:34ee385f4d2d 1292 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
rajathr 0:34ee385f4d2d 1293 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
rajathr 0:34ee385f4d2d 1294 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
rajathr 0:34ee385f4d2d 1295 * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
rajathr 0:34ee385f4d2d 1296 * 16 MHz) but the real value may vary depending on the variations
rajathr 0:34ee385f4d2d 1297 * in voltage and temperature.
rajathr 0:34ee385f4d2d 1298 * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
rajathr 0:34ee385f4d2d 1299 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
rajathr 0:34ee385f4d2d 1300 * frequency of the crystal used. Otherwise, this function may
rajathr 0:34ee385f4d2d 1301 * have wrong result.
rajathr 0:34ee385f4d2d 1302 *
rajathr 0:34ee385f4d2d 1303 * @note The result of this function could be not correct when using fractional
rajathr 0:34ee385f4d2d 1304 * value for HSE crystal.
rajathr 0:34ee385f4d2d 1305 *
rajathr 0:34ee385f4d2d 1306 * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
rajathr 0:34ee385f4d2d 1307 * the clocks frequencies.
rajathr 0:34ee385f4d2d 1308 *
rajathr 0:34ee385f4d2d 1309 * @note This function can be used by the user application to compute the
rajathr 0:34ee385f4d2d 1310 * baudrate for the communication peripherals or configure other parameters.
rajathr 0:34ee385f4d2d 1311 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
rajathr 0:34ee385f4d2d 1312 * must be called to update the structure's field. Otherwise, any
rajathr 0:34ee385f4d2d 1313 * configuration based on this function will be incorrect.
rajathr 0:34ee385f4d2d 1314 *
rajathr 0:34ee385f4d2d 1315 * @retval None
rajathr 0:34ee385f4d2d 1316 */
rajathr 0:34ee385f4d2d 1317 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
rajathr 0:34ee385f4d2d 1318 {
rajathr 0:34ee385f4d2d 1319 uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
rajathr 0:34ee385f4d2d 1320 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
rajathr 0:34ee385f4d2d 1321 uint32_t pllr = 2;
rajathr 0:34ee385f4d2d 1322 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
rajathr 0:34ee385f4d2d 1323
rajathr 0:34ee385f4d2d 1324 /* Get SYSCLK source -------------------------------------------------------*/
rajathr 0:34ee385f4d2d 1325 tmp = RCC->CFGR & RCC_CFGR_SWS_MORT;
rajathr 0:34ee385f4d2d 1326
rajathr 0:34ee385f4d2d 1327 switch (tmp)
rajathr 0:34ee385f4d2d 1328 {
rajathr 0:34ee385f4d2d 1329 case 0x00: /* HSI used as system clock source */
rajathr 0:34ee385f4d2d 1330 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
rajathr 0:34ee385f4d2d 1331 break;
rajathr 0:34ee385f4d2d 1332 case 0x04: /* HSE used as system clock source */
rajathr 0:34ee385f4d2d 1333 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
rajathr 0:34ee385f4d2d 1334 break;
rajathr 0:34ee385f4d2d 1335 case 0x08: /* PLL P used as system clock source */
rajathr 0:34ee385f4d2d 1336
rajathr 0:34ee385f4d2d 1337 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
rajathr 0:34ee385f4d2d 1338 SYSCLK = PLL_VCO / PLLP
rajathr 0:34ee385f4d2d 1339 */
rajathr 0:34ee385f4d2d 1340 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC_MORT) >> 22;
rajathr 0:34ee385f4d2d 1341 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM_MORT;
rajathr 0:34ee385f4d2d 1342
rajathr 0:34ee385f4d2d 1343 if (pllsource != 0)
rajathr 0:34ee385f4d2d 1344 {
rajathr 0:34ee385f4d2d 1345 /* HSE used as PLL clock source */
rajathr 0:34ee385f4d2d 1346 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN_MORT) >> 6);
rajathr 0:34ee385f4d2d 1347 }
rajathr 0:34ee385f4d2d 1348 else
rajathr 0:34ee385f4d2d 1349 {
rajathr 0:34ee385f4d2d 1350 /* HSI used as PLL clock source */
rajathr 0:34ee385f4d2d 1351 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN_MORT) >> 6);
rajathr 0:34ee385f4d2d 1352 }
rajathr 0:34ee385f4d2d 1353
rajathr 0:34ee385f4d2d 1354 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP_MORT) >>16) + 1 ) *2;
rajathr 0:34ee385f4d2d 1355 RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
rajathr 0:34ee385f4d2d 1356 break;
rajathr 0:34ee385f4d2d 1357
rajathr 0:34ee385f4d2d 1358 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
rajathr 0:34ee385f4d2d 1359 case 0x0C: /* PLL R used as system clock source */
rajathr 0:34ee385f4d2d 1360 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
rajathr 0:34ee385f4d2d 1361 SYSCLK = PLL_VCO / PLLR
rajathr 0:34ee385f4d2d 1362 */
rajathr 0:34ee385f4d2d 1363 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC_MORT) >> 22;
rajathr 0:34ee385f4d2d 1364 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM_MORT;
rajathr 0:34ee385f4d2d 1365
rajathr 0:34ee385f4d2d 1366 if (pllsource != 0)
rajathr 0:34ee385f4d2d 1367 {
rajathr 0:34ee385f4d2d 1368 /* HSE used as PLL clock source */
rajathr 0:34ee385f4d2d 1369 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN_MORT) >> 6);
rajathr 0:34ee385f4d2d 1370 }
rajathr 0:34ee385f4d2d 1371 else
rajathr 0:34ee385f4d2d 1372 {
rajathr 0:34ee385f4d2d 1373 /* HSI used as PLL clock source */
rajathr 0:34ee385f4d2d 1374 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN_MORT) >> 6);
rajathr 0:34ee385f4d2d 1375 }
rajathr 0:34ee385f4d2d 1376
rajathr 0:34ee385f4d2d 1377 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR_MORT) >>28) + 1 ) *2;
rajathr 0:34ee385f4d2d 1378 RCC_Clocks->SYSCLK_Frequency = pllvco/pllr;
rajathr 0:34ee385f4d2d 1379 break;
rajathr 0:34ee385f4d2d 1380 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
rajathr 0:34ee385f4d2d 1381
rajathr 0:34ee385f4d2d 1382 default:
rajathr 0:34ee385f4d2d 1383 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
rajathr 0:34ee385f4d2d 1384 break;
rajathr 0:34ee385f4d2d 1385 }
rajathr 0:34ee385f4d2d 1386 /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
rajathr 0:34ee385f4d2d 1387
rajathr 0:34ee385f4d2d 1388 /* Get HCLK prescaler */
rajathr 0:34ee385f4d2d 1389 tmp = RCC->CFGR & RCC_CFGR_HPRE_MORT;
rajathr 0:34ee385f4d2d 1390 tmp = tmp >> 4;
rajathr 0:34ee385f4d2d 1391 presc = APBAHBPrescTable[tmp];
rajathr 0:34ee385f4d2d 1392 /* HCLK clock frequency */
rajathr 0:34ee385f4d2d 1393 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
rajathr 0:34ee385f4d2d 1394
rajathr 0:34ee385f4d2d 1395 /* Get PCLK1 prescaler */
rajathr 0:34ee385f4d2d 1396 tmp = RCC->CFGR & RCC_CFGR_PPRE1_MORT;
rajathr 0:34ee385f4d2d 1397 tmp = tmp >> 10;
rajathr 0:34ee385f4d2d 1398 presc = APBAHBPrescTable[tmp];
rajathr 0:34ee385f4d2d 1399 /* PCLK1 clock frequency */
rajathr 0:34ee385f4d2d 1400 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
rajathr 0:34ee385f4d2d 1401
rajathr 0:34ee385f4d2d 1402 /* Get PCLK2 prescaler */
rajathr 0:34ee385f4d2d 1403 tmp = RCC->CFGR & RCC_CFGR_PPRE2_MORT;
rajathr 0:34ee385f4d2d 1404 tmp = tmp >> 13;
rajathr 0:34ee385f4d2d 1405 presc = APBAHBPrescTable[tmp];
rajathr 0:34ee385f4d2d 1406 /* PCLK2 clock frequency */
rajathr 0:34ee385f4d2d 1407 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
rajathr 0:34ee385f4d2d 1408 }
rajathr 0:34ee385f4d2d 1409
rajathr 0:34ee385f4d2d 1410 /**
rajathr 0:34ee385f4d2d 1411 * @}
rajathr 0:34ee385f4d2d 1412 */
rajathr 0:34ee385f4d2d 1413
rajathr 0:34ee385f4d2d 1414 /** @defgroup RCC_Group3 Peripheral clocks configuration functions
rajathr 0:34ee385f4d2d 1415 * @brief Peripheral clocks configuration functions
rajathr 0:34ee385f4d2d 1416 *
rajathr 0:34ee385f4d2d 1417 @verbatim
rajathr 0:34ee385f4d2d 1418 ===============================================================================
rajathr 0:34ee385f4d2d 1419 ##### Peripheral clocks configuration functions #####
rajathr 0:34ee385f4d2d 1420 ===============================================================================
rajathr 0:34ee385f4d2d 1421 [..] This section provide functions allowing to configure the Peripheral clocks.
rajathr 0:34ee385f4d2d 1422
rajathr 0:34ee385f4d2d 1423 (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided
rajathr 0:34ee385f4d2d 1424 by 2 to 31.
rajathr 0:34ee385f4d2d 1425
rajathr 0:34ee385f4d2d 1426 (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
rajathr 0:34ee385f4d2d 1427 except internal SRAM, Flash and JTAG. Before to start using a peripheral
rajathr 0:34ee385f4d2d 1428 you have to enable its interface clock. You can do this using
rajathr 0:34ee385f4d2d 1429 RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
rajathr 0:34ee385f4d2d 1430
rajathr 0:34ee385f4d2d 1431 (#) To reset the peripherals configuration (to the default state after device reset)
rajathr 0:34ee385f4d2d 1432 you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
rajathr 0:34ee385f4d2d 1433 RCC_APB1PeriphResetCmd() functions.
rajathr 0:34ee385f4d2d 1434
rajathr 0:34ee385f4d2d 1435 (#) To further reduce power consumption in SLEEP mode the peripheral clocks
rajathr 0:34ee385f4d2d 1436 can be disabled prior to executing the WFI or WFE instructions.
rajathr 0:34ee385f4d2d 1437 You can do this using RCC_AHBPeriphClockLPModeCmd(),
rajathr 0:34ee385f4d2d 1438 RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions.
rajathr 0:34ee385f4d2d 1439
rajathr 0:34ee385f4d2d 1440 @endverbatim
rajathr 0:34ee385f4d2d 1441 * @{
rajathr 0:34ee385f4d2d 1442 */
rajathr 0:34ee385f4d2d 1443
rajathr 0:34ee385f4d2d 1444 /**
rajathr 0:34ee385f4d2d 1445 * @brief Configures the RTC clock (RTCCLK).
rajathr 0:34ee385f4d2d 1446 * @note As the RTC clock configuration bits are in the Backup domain and write
rajathr 0:34ee385f4d2d 1447 * access is denied to this domain after reset, you have to enable write
rajathr 0:34ee385f4d2d 1448 * access using PWR_BackupAccessCmd(ENABLE) function before to configure
rajathr 0:34ee385f4d2d 1449 * the RTC clock source (to be done once after reset).
rajathr 0:34ee385f4d2d 1450 * @note Once the RTC clock is configured it can't be changed unless the
rajathr 0:34ee385f4d2d 1451 * Backup domain is reset using RCC_BackupResetCmd() function, or by
rajathr 0:34ee385f4d2d 1452 * a Power On Reset (POR).
rajathr 0:34ee385f4d2d 1453 *
rajathr 0:34ee385f4d2d 1454 * @param RCC_RTCCLKSource: specifies the RTC clock source.
rajathr 0:34ee385f4d2d 1455 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1456 * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
rajathr 0:34ee385f4d2d 1457 * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
rajathr 0:34ee385f4d2d 1458 * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected
rajathr 0:34ee385f4d2d 1459 * as RTC clock, where x:[2,31]
rajathr 0:34ee385f4d2d 1460 *
rajathr 0:34ee385f4d2d 1461 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
rajathr 0:34ee385f4d2d 1462 * work in STOP and STANDBY modes, and can be used as wakeup source.
rajathr 0:34ee385f4d2d 1463 * However, when the HSE clock is used as RTC clock source, the RTC
rajathr 0:34ee385f4d2d 1464 * cannot be used in STOP and STANDBY modes.
rajathr 0:34ee385f4d2d 1465 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
rajathr 0:34ee385f4d2d 1466 * RTC clock source).
rajathr 0:34ee385f4d2d 1467 *
rajathr 0:34ee385f4d2d 1468 * @retval None
rajathr 0:34ee385f4d2d 1469 */
rajathr 0:34ee385f4d2d 1470 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
rajathr 0:34ee385f4d2d 1471 {
rajathr 0:34ee385f4d2d 1472 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1473
rajathr 0:34ee385f4d2d 1474 /* Check the parameters */
rajathr 0:34ee385f4d2d 1475 assert_param(IS_RCC_RTCCLK_SOURCE_MORT(RCC_RTCCLKSource));
rajathr 0:34ee385f4d2d 1476
rajathr 0:34ee385f4d2d 1477 if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
rajathr 0:34ee385f4d2d 1478 { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
rajathr 0:34ee385f4d2d 1479 tmpreg = RCC->CFGR;
rajathr 0:34ee385f4d2d 1480
rajathr 0:34ee385f4d2d 1481 /* Clear RTCPRE[4:0] bits */
rajathr 0:34ee385f4d2d 1482 tmpreg &= ~RCC_CFGR_RTCPRE_MORT;
rajathr 0:34ee385f4d2d 1483
rajathr 0:34ee385f4d2d 1484 /* Configure HSE division factor for RTC clock */
rajathr 0:34ee385f4d2d 1485 tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
rajathr 0:34ee385f4d2d 1486
rajathr 0:34ee385f4d2d 1487 /* Store the new value */
rajathr 0:34ee385f4d2d 1488 RCC->CFGR = tmpreg;
rajathr 0:34ee385f4d2d 1489 }
rajathr 0:34ee385f4d2d 1490
rajathr 0:34ee385f4d2d 1491 /* Select the RTC clock source */
rajathr 0:34ee385f4d2d 1492 RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
rajathr 0:34ee385f4d2d 1493 }
rajathr 0:34ee385f4d2d 1494
rajathr 0:34ee385f4d2d 1495 /**
rajathr 0:34ee385f4d2d 1496 * @brief Enables or disables the RTC clock.
rajathr 0:34ee385f4d2d 1497 * @note This function must be used only after the RTC clock source was selected
rajathr 0:34ee385f4d2d 1498 * using the RCC_RTCCLKConfig function.
rajathr 0:34ee385f4d2d 1499 * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 1500 * @retval None
rajathr 0:34ee385f4d2d 1501 */
rajathr 0:34ee385f4d2d 1502 void RCC_RTCCLKCmd(FunctionalState NewState)
rajathr 0:34ee385f4d2d 1503 {
rajathr 0:34ee385f4d2d 1504 /* Check the parameters */
rajathr 0:34ee385f4d2d 1505 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 1506
rajathr 0:34ee385f4d2d 1507 *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
rajathr 0:34ee385f4d2d 1508 }
rajathr 0:34ee385f4d2d 1509
rajathr 0:34ee385f4d2d 1510 /**
rajathr 0:34ee385f4d2d 1511 * @brief Forces or releases the Backup domain reset.
rajathr 0:34ee385f4d2d 1512 * @note This function resets the RTC peripheral (including the backup registers)
rajathr 0:34ee385f4d2d 1513 * and the RTC clock source selection in RCC_CSR register.
rajathr 0:34ee385f4d2d 1514 * @note The BKPSRAM is not affected by this reset.
rajathr 0:34ee385f4d2d 1515 * @param NewState: new state of the Backup domain reset.
rajathr 0:34ee385f4d2d 1516 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 1517 * @retval None
rajathr 0:34ee385f4d2d 1518 */
rajathr 0:34ee385f4d2d 1519 void RCC_BackupResetCmd(FunctionalState NewState)
rajathr 0:34ee385f4d2d 1520 {
rajathr 0:34ee385f4d2d 1521 /* Check the parameters */
rajathr 0:34ee385f4d2d 1522 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 1523 *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
rajathr 0:34ee385f4d2d 1524 }
rajathr 0:34ee385f4d2d 1525
rajathr 0:34ee385f4d2d 1526 #if defined (STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
rajathr 0:34ee385f4d2d 1527 /**
rajathr 0:34ee385f4d2d 1528 * @brief Configures the I2S clock source (I2SCLK).
rajathr 0:34ee385f4d2d 1529 * @note This function must be called before enabling the I2S APB clock.
rajathr 0:34ee385f4d2d 1530 *
rajathr 0:34ee385f4d2d 1531 * @param RCC_I2SAPBx: specifies the APBx I2S clock source.
rajathr 0:34ee385f4d2d 1532 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1533 * @arg RCC_I2SBus_APB1: I2S peripheral instance is on APB1 Bus
rajathr 0:34ee385f4d2d 1534 * @arg RCC_I2SBus_APB2: I2S peripheral instance is on APB2 Bus
rajathr 0:34ee385f4d2d 1535 *
rajathr 0:34ee385f4d2d 1536 * @param RCC_I2SCLKSource: specifies the I2S clock source.
rajathr 0:34ee385f4d2d 1537 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1538 * @arg RCC_I2SCLKSource_PLLI2S: PLLI2S clock used as I2S clock source
rajathr 0:34ee385f4d2d 1539 * @arg RCC_I2SCLKSource_Ext: External clock mapped on the I2S_CKIN pin
rajathr 0:34ee385f4d2d 1540 * used as I2S clock source
rajathr 0:34ee385f4d2d 1541 * @arg RCC_I2SCLKSource_PLL: PLL clock used as I2S clock source
rajathr 0:34ee385f4d2d 1542 * @arg RCC_I2SCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as I2S clock source
rajathr 0:34ee385f4d2d 1543 * @retval None
rajathr 0:34ee385f4d2d 1544 */
rajathr 0:34ee385f4d2d 1545 void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource)
rajathr 0:34ee385f4d2d 1546 {
rajathr 0:34ee385f4d2d 1547 /* Check the parameters */
rajathr 0:34ee385f4d2d 1548 assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
rajathr 0:34ee385f4d2d 1549 assert_param(IS_RCC_I2S_APBx(RCC_I2SAPBx));
rajathr 0:34ee385f4d2d 1550
rajathr 0:34ee385f4d2d 1551 if(RCC_I2SAPBx == RCC_I2SBus_APB1)
rajathr 0:34ee385f4d2d 1552 {
rajathr 0:34ee385f4d2d 1553 /* Clear APB1 I2Sx clock source selection bits */
rajathr 0:34ee385f4d2d 1554 RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S1SRC_MORT;
rajathr 0:34ee385f4d2d 1555 /* Set new APB1 I2Sx clock source*/
rajathr 0:34ee385f4d2d 1556 RCC->DCKCFGR |= RCC_I2SCLKSource;
rajathr 0:34ee385f4d2d 1557 }
rajathr 0:34ee385f4d2d 1558 else
rajathr 0:34ee385f4d2d 1559 {
rajathr 0:34ee385f4d2d 1560 /* Clear APB2 I2Sx clock source selection bits */
rajathr 0:34ee385f4d2d 1561 RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S2SRC_MORT;
rajathr 0:34ee385f4d2d 1562 /* Set new APB2 I2Sx clock source */
rajathr 0:34ee385f4d2d 1563 RCC->DCKCFGR |= (RCC_I2SCLKSource << 2);
rajathr 0:34ee385f4d2d 1564 }
rajathr 0:34ee385f4d2d 1565 }
rajathr 0:34ee385f4d2d 1566 #if defined(STM32F446xx)
rajathr 0:34ee385f4d2d 1567 /**
rajathr 0:34ee385f4d2d 1568 * @brief Configures the SAIx clock source (SAIxCLK).
rajathr 0:34ee385f4d2d 1569 * @note This function must be called before enabling the SAIx APB clock.
rajathr 0:34ee385f4d2d 1570 *
rajathr 0:34ee385f4d2d 1571 * @param RCC_SAIInstance: specifies the SAIx clock source.
rajathr 0:34ee385f4d2d 1572 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1573 * @arg RCC_SAIInstance_SAI1: SAI1 clock source selection
rajathr 0:34ee385f4d2d 1574 * @arg RCC_SAIInstance_SAI2: SAI2 clock source selections
rajathr 0:34ee385f4d2d 1575 *
rajathr 0:34ee385f4d2d 1576 * @param RCC_SAICLKSource: specifies the SAI clock source.
rajathr 0:34ee385f4d2d 1577 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1578 * @arg RCC_SAICLKSource_PLLSAI: PLLSAI clock used as SAI clock source
rajathr 0:34ee385f4d2d 1579 * @arg RCC_SAICLKSource_PLLI2S: PLLI2S clock used as SAI clock source
rajathr 0:34ee385f4d2d 1580 * @arg RCC_SAICLKSource_PLL: PLL clock used as SAI clock source
rajathr 0:34ee385f4d2d 1581 * @arg RCC_SAICLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
rajathr 0:34ee385f4d2d 1582 * @retval None
rajathr 0:34ee385f4d2d 1583 */
rajathr 0:34ee385f4d2d 1584 void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource)
rajathr 0:34ee385f4d2d 1585 {
rajathr 0:34ee385f4d2d 1586 /* Check the parameters */
rajathr 0:34ee385f4d2d 1587 assert_param(IS_RCC_SAICLK_SOURCE(RCC_SAICLKSource));
rajathr 0:34ee385f4d2d 1588 assert_param(IS_RCC_SAI_INSTANCE(RCC_SAIInstance));
rajathr 0:34ee385f4d2d 1589
rajathr 0:34ee385f4d2d 1590 if(RCC_SAIInstance == RCC_SAIInstance_SAI1)
rajathr 0:34ee385f4d2d 1591 {
rajathr 0:34ee385f4d2d 1592 /* Clear SAI1 clock source selection bits */
rajathr 0:34ee385f4d2d 1593 RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI1SRC_MORT;
rajathr 0:34ee385f4d2d 1594 /* Set new SAI1 clock source */
rajathr 0:34ee385f4d2d 1595 RCC->DCKCFGR |= RCC_SAICLKSource;
rajathr 0:34ee385f4d2d 1596 }
rajathr 0:34ee385f4d2d 1597 else
rajathr 0:34ee385f4d2d 1598 {
rajathr 0:34ee385f4d2d 1599 /* Clear SAI2 clock source selection bits */
rajathr 0:34ee385f4d2d 1600 RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI2SRC_MORT;
rajathr 0:34ee385f4d2d 1601 /* Set new SAI2 clock source */
rajathr 0:34ee385f4d2d 1602 RCC->DCKCFGR |= (RCC_SAICLKSource << 2);
rajathr 0:34ee385f4d2d 1603 }
rajathr 0:34ee385f4d2d 1604 }
rajathr 0:34ee385f4d2d 1605 #endif /* STM32F446xx */
rajathr 0:34ee385f4d2d 1606
rajathr 0:34ee385f4d2d 1607 #if defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 1608 /**
rajathr 0:34ee385f4d2d 1609 * @brief Configures SAI1BlockA clock source selection.
rajathr 0:34ee385f4d2d 1610 * @note This function must be called before enabling PLLSAI, PLLI2S and
rajathr 0:34ee385f4d2d 1611 * the SAI clock.
rajathr 0:34ee385f4d2d 1612 * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source.
rajathr 0:34ee385f4d2d 1613 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1614 * @arg RCC_SAIACLKSource_PLLI2SR: PLLI2SR clock used as SAI clock source
rajathr 0:34ee385f4d2d 1615 * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S clock used as SAI clock source
rajathr 0:34ee385f4d2d 1616 * @arg RCC_SAIACLKSource_PLL: PLL clock used as SAI clock source
rajathr 0:34ee385f4d2d 1617 * @arg RCC_SAIACLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
rajathr 0:34ee385f4d2d 1618 * @retval None
rajathr 0:34ee385f4d2d 1619 */
rajathr 0:34ee385f4d2d 1620 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
rajathr 0:34ee385f4d2d 1621 {
rajathr 0:34ee385f4d2d 1622 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1623
rajathr 0:34ee385f4d2d 1624 /* Check the parameters */
rajathr 0:34ee385f4d2d 1625 assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource));
rajathr 0:34ee385f4d2d 1626
rajathr 0:34ee385f4d2d 1627 tmpreg = RCC->DCKCFGR;
rajathr 0:34ee385f4d2d 1628
rajathr 0:34ee385f4d2d 1629 /* Clear RCC_DCKCFGR_SAI1ASRC_MORT[1:0] bits */
rajathr 0:34ee385f4d2d 1630 tmpreg &= ~RCC_DCKCFGR_SAI1ASRC_MORT;
rajathr 0:34ee385f4d2d 1631
rajathr 0:34ee385f4d2d 1632 /* Set SAI Block A source selection value */
rajathr 0:34ee385f4d2d 1633 tmpreg |= RCC_SAIBlockACLKSource;
rajathr 0:34ee385f4d2d 1634
rajathr 0:34ee385f4d2d 1635 /* Store the new value */
rajathr 0:34ee385f4d2d 1636 RCC->DCKCFGR = tmpreg;
rajathr 0:34ee385f4d2d 1637 }
rajathr 0:34ee385f4d2d 1638
rajathr 0:34ee385f4d2d 1639 /**
rajathr 0:34ee385f4d2d 1640 * @brief Configures SAI1BlockB clock source selection.
rajathr 0:34ee385f4d2d 1641 * @note This function must be called before enabling PLLSAI, PLLI2S and
rajathr 0:34ee385f4d2d 1642 * the SAI clock.
rajathr 0:34ee385f4d2d 1643 * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source.
rajathr 0:34ee385f4d2d 1644 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1645 * @arg RCC_SAIBCLKSource_PLLI2SR: PLLI2SR clock used as SAI clock source
rajathr 0:34ee385f4d2d 1646 * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S clock used as SAI clock source
rajathr 0:34ee385f4d2d 1647 * @arg RCC_SAIBCLKSource_PLL: PLL clock used as SAI clock source
rajathr 0:34ee385f4d2d 1648 * @arg RCC_SAIBCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
rajathr 0:34ee385f4d2d 1649 * @retval None
rajathr 0:34ee385f4d2d 1650 */
rajathr 0:34ee385f4d2d 1651 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
rajathr 0:34ee385f4d2d 1652 {
rajathr 0:34ee385f4d2d 1653 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1654
rajathr 0:34ee385f4d2d 1655 /* Check the parameters */
rajathr 0:34ee385f4d2d 1656 assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource));
rajathr 0:34ee385f4d2d 1657
rajathr 0:34ee385f4d2d 1658 tmpreg = RCC->DCKCFGR;
rajathr 0:34ee385f4d2d 1659
rajathr 0:34ee385f4d2d 1660 /* Clear RCC_DCKCFGR_SAI1ASRC_MORT[1:0] bits */
rajathr 0:34ee385f4d2d 1661 tmpreg &= ~RCC_DCKCFGR_SAI1BSRC_MORT;
rajathr 0:34ee385f4d2d 1662
rajathr 0:34ee385f4d2d 1663 /* Set SAI Block B source selection value */
rajathr 0:34ee385f4d2d 1664 tmpreg |= RCC_SAIBlockBCLKSource;
rajathr 0:34ee385f4d2d 1665
rajathr 0:34ee385f4d2d 1666 /* Store the new value */
rajathr 0:34ee385f4d2d 1667 RCC->DCKCFGR = tmpreg;
rajathr 0:34ee385f4d2d 1668 }
rajathr 0:34ee385f4d2d 1669 #endif /* STM32F413_423xx */
rajathr 0:34ee385f4d2d 1670 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
rajathr 0:34ee385f4d2d 1671
rajathr 0:34ee385f4d2d 1672 #if defined(STM32F410xx)
rajathr 0:34ee385f4d2d 1673 /**
rajathr 0:34ee385f4d2d 1674 * @brief Configures the I2S clock source (I2SCLK).
rajathr 0:34ee385f4d2d 1675 * @note This function must be called before enabling the I2S clock.
rajathr 0:34ee385f4d2d 1676 *
rajathr 0:34ee385f4d2d 1677 * @param RCC_I2SCLKSource: specifies the I2S clock source.
rajathr 0:34ee385f4d2d 1678 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1679 * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
rajathr 0:34ee385f4d2d 1680 * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
rajathr 0:34ee385f4d2d 1681 * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
rajathr 0:34ee385f4d2d 1682 * @retval None
rajathr 0:34ee385f4d2d 1683 */
rajathr 0:34ee385f4d2d 1684 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
rajathr 0:34ee385f4d2d 1685 {
rajathr 0:34ee385f4d2d 1686 /* Check the parameters */
rajathr 0:34ee385f4d2d 1687 assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
rajathr 0:34ee385f4d2d 1688
rajathr 0:34ee385f4d2d 1689 /* Clear I2Sx clock source selection bits */
rajathr 0:34ee385f4d2d 1690 RCC->DCKCFGR &= ~RCC_DCKCFGR_I2SSRC;
rajathr 0:34ee385f4d2d 1691 /* Set new I2Sx clock source*/
rajathr 0:34ee385f4d2d 1692 RCC->DCKCFGR |= RCC_I2SCLKSource;
rajathr 0:34ee385f4d2d 1693 }
rajathr 0:34ee385f4d2d 1694 #endif /* STM32F410xx */
rajathr 0:34ee385f4d2d 1695
rajathr 0:34ee385f4d2d 1696 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 1697 /**
rajathr 0:34ee385f4d2d 1698 * @brief Configures the I2S clock source (I2SCLK).
rajathr 0:34ee385f4d2d 1699 * @note This function must be called before enabling the I2S APB clock.
rajathr 0:34ee385f4d2d 1700 * @param RCC_I2SCLKSource: specifies the I2S clock source.
rajathr 0:34ee385f4d2d 1701 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1702 * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
rajathr 0:34ee385f4d2d 1703 * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
rajathr 0:34ee385f4d2d 1704 * used as I2S clock source
rajathr 0:34ee385f4d2d 1705 * @retval None
rajathr 0:34ee385f4d2d 1706 */
rajathr 0:34ee385f4d2d 1707 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
rajathr 0:34ee385f4d2d 1708 {
rajathr 0:34ee385f4d2d 1709 /* Check the parameters */
rajathr 0:34ee385f4d2d 1710 assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
rajathr 0:34ee385f4d2d 1711
rajathr 0:34ee385f4d2d 1712 *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
rajathr 0:34ee385f4d2d 1713 }
rajathr 0:34ee385f4d2d 1714 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
rajathr 0:34ee385f4d2d 1715
rajathr 0:34ee385f4d2d 1716 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 1717 /**
rajathr 0:34ee385f4d2d 1718 * @brief Configures SAI1BlockA clock source selection.
rajathr 0:34ee385f4d2d 1719 *
rajathr 0:34ee385f4d2d 1720 * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.
rajathr 0:34ee385f4d2d 1721 *
rajathr 0:34ee385f4d2d 1722 * @note This function must be called before enabling PLLSAI, PLLI2S and
rajathr 0:34ee385f4d2d 1723 * the SAI clock.
rajathr 0:34ee385f4d2d 1724 * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source.
rajathr 0:34ee385f4d2d 1725 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1726 * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
rajathr 0:34ee385f4d2d 1727 * as SAI1 Block A clock
rajathr 0:34ee385f4d2d 1728 * @arg RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
rajathr 0:34ee385f4d2d 1729 * as SAI1 Block A clock
rajathr 0:34ee385f4d2d 1730 * @arg RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin
rajathr 0:34ee385f4d2d 1731 * used as SAI1 Block A clock
rajathr 0:34ee385f4d2d 1732 * @retval None
rajathr 0:34ee385f4d2d 1733 */
rajathr 0:34ee385f4d2d 1734 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
rajathr 0:34ee385f4d2d 1735 {
rajathr 0:34ee385f4d2d 1736 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1737
rajathr 0:34ee385f4d2d 1738 /* Check the parameters */
rajathr 0:34ee385f4d2d 1739 assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource));
rajathr 0:34ee385f4d2d 1740
rajathr 0:34ee385f4d2d 1741 tmpreg = RCC->DCKCFGR;
rajathr 0:34ee385f4d2d 1742
rajathr 0:34ee385f4d2d 1743 /* Clear RCC_DCKCFGR_SAI1ASRC_MORT[1:0] bits */
rajathr 0:34ee385f4d2d 1744 tmpreg &= ~RCC_DCKCFGR_SAI1ASRC_MORT;
rajathr 0:34ee385f4d2d 1745
rajathr 0:34ee385f4d2d 1746 /* Set SAI Block A source selection value */
rajathr 0:34ee385f4d2d 1747 tmpreg |= RCC_SAIBlockACLKSource;
rajathr 0:34ee385f4d2d 1748
rajathr 0:34ee385f4d2d 1749 /* Store the new value */
rajathr 0:34ee385f4d2d 1750 RCC->DCKCFGR = tmpreg;
rajathr 0:34ee385f4d2d 1751 }
rajathr 0:34ee385f4d2d 1752
rajathr 0:34ee385f4d2d 1753 /**
rajathr 0:34ee385f4d2d 1754 * @brief Configures SAI1BlockB clock source selection.
rajathr 0:34ee385f4d2d 1755 *
rajathr 0:34ee385f4d2d 1756 * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.
rajathr 0:34ee385f4d2d 1757 *
rajathr 0:34ee385f4d2d 1758 * @note This function must be called before enabling PLLSAI, PLLI2S and
rajathr 0:34ee385f4d2d 1759 * the SAI clock.
rajathr 0:34ee385f4d2d 1760 * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source.
rajathr 0:34ee385f4d2d 1761 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1762 * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
rajathr 0:34ee385f4d2d 1763 * as SAI1 Block B clock
rajathr 0:34ee385f4d2d 1764 * @arg RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
rajathr 0:34ee385f4d2d 1765 * as SAI1 Block B clock
rajathr 0:34ee385f4d2d 1766 * @arg RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin
rajathr 0:34ee385f4d2d 1767 * used as SAI1 Block B clock
rajathr 0:34ee385f4d2d 1768 * @retval None
rajathr 0:34ee385f4d2d 1769 */
rajathr 0:34ee385f4d2d 1770 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
rajathr 0:34ee385f4d2d 1771 {
rajathr 0:34ee385f4d2d 1772 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1773
rajathr 0:34ee385f4d2d 1774 /* Check the parameters */
rajathr 0:34ee385f4d2d 1775 assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource));
rajathr 0:34ee385f4d2d 1776
rajathr 0:34ee385f4d2d 1777 tmpreg = RCC->DCKCFGR;
rajathr 0:34ee385f4d2d 1778
rajathr 0:34ee385f4d2d 1779 /* Clear RCC_DCKCFGR_SAI1BSRC_MORT[1:0] bits */
rajathr 0:34ee385f4d2d 1780 tmpreg &= ~RCC_DCKCFGR_SAI1BSRC_MORT;
rajathr 0:34ee385f4d2d 1781
rajathr 0:34ee385f4d2d 1782 /* Set SAI Block B source selection value */
rajathr 0:34ee385f4d2d 1783 tmpreg |= RCC_SAIBlockBCLKSource;
rajathr 0:34ee385f4d2d 1784
rajathr 0:34ee385f4d2d 1785 /* Store the new value */
rajathr 0:34ee385f4d2d 1786 RCC->DCKCFGR = tmpreg;
rajathr 0:34ee385f4d2d 1787 }
rajathr 0:34ee385f4d2d 1788 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 1789
rajathr 0:34ee385f4d2d 1790 /**
rajathr 0:34ee385f4d2d 1791 * @brief Configures the SAI clock Divider coming from PLLI2S.
rajathr 0:34ee385f4d2d 1792 *
rajathr 0:34ee385f4d2d 1793 * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
rajathr 0:34ee385f4d2d 1794 *
rajathr 0:34ee385f4d2d 1795 * @note This function must be called before enabling the PLLI2S.
rajathr 0:34ee385f4d2d 1796 *
rajathr 0:34ee385f4d2d 1797 * @param RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock .
rajathr 0:34ee385f4d2d 1798 * This parameter must be a number between 1 and 32.
rajathr 0:34ee385f4d2d 1799 * SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ
rajathr 0:34ee385f4d2d 1800 *
rajathr 0:34ee385f4d2d 1801 * @retval None
rajathr 0:34ee385f4d2d 1802 */
rajathr 0:34ee385f4d2d 1803 void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)
rajathr 0:34ee385f4d2d 1804 {
rajathr 0:34ee385f4d2d 1805 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1806
rajathr 0:34ee385f4d2d 1807 /* Check the parameters */
rajathr 0:34ee385f4d2d 1808 assert_param(IS_RCC_PLLI2S_DIVQ_VALUE_MORT(RCC_PLLI2SDivQ));
rajathr 0:34ee385f4d2d 1809
rajathr 0:34ee385f4d2d 1810 tmpreg = RCC->DCKCFGR;
rajathr 0:34ee385f4d2d 1811
rajathr 0:34ee385f4d2d 1812 /* Clear PLLI2SDIVQ[4:0] bits */
rajathr 0:34ee385f4d2d 1813 tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ_MORT);
rajathr 0:34ee385f4d2d 1814
rajathr 0:34ee385f4d2d 1815 /* Set PLLI2SDIVQ values */
rajathr 0:34ee385f4d2d 1816 tmpreg |= (RCC_PLLI2SDivQ - 1);
rajathr 0:34ee385f4d2d 1817
rajathr 0:34ee385f4d2d 1818 /* Store the new value */
rajathr 0:34ee385f4d2d 1819 RCC->DCKCFGR = tmpreg;
rajathr 0:34ee385f4d2d 1820 }
rajathr 0:34ee385f4d2d 1821
rajathr 0:34ee385f4d2d 1822 /**
rajathr 0:34ee385f4d2d 1823 * @brief Configures the SAI clock Divider coming from PLLSAI.
rajathr 0:34ee385f4d2d 1824 *
rajathr 0:34ee385f4d2d 1825 * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
rajathr 0:34ee385f4d2d 1826 *
rajathr 0:34ee385f4d2d 1827 * @note This function must be called before enabling the PLLSAI.
rajathr 0:34ee385f4d2d 1828 *
rajathr 0:34ee385f4d2d 1829 * @param RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock .
rajathr 0:34ee385f4d2d 1830 * This parameter must be a number between 1 and 32.
rajathr 0:34ee385f4d2d 1831 * SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ
rajathr 0:34ee385f4d2d 1832 *
rajathr 0:34ee385f4d2d 1833 * @retval None
rajathr 0:34ee385f4d2d 1834 */
rajathr 0:34ee385f4d2d 1835 void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)
rajathr 0:34ee385f4d2d 1836 {
rajathr 0:34ee385f4d2d 1837 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1838
rajathr 0:34ee385f4d2d 1839 /* Check the parameters */
rajathr 0:34ee385f4d2d 1840 assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ));
rajathr 0:34ee385f4d2d 1841
rajathr 0:34ee385f4d2d 1842 tmpreg = RCC->DCKCFGR;
rajathr 0:34ee385f4d2d 1843
rajathr 0:34ee385f4d2d 1844 /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */
rajathr 0:34ee385f4d2d 1845 tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ_MORT);
rajathr 0:34ee385f4d2d 1846
rajathr 0:34ee385f4d2d 1847 /* Set PLLSAIDIVQ values */
rajathr 0:34ee385f4d2d 1848 tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8);
rajathr 0:34ee385f4d2d 1849
rajathr 0:34ee385f4d2d 1850 /* Store the new value */
rajathr 0:34ee385f4d2d 1851 RCC->DCKCFGR = tmpreg;
rajathr 0:34ee385f4d2d 1852 }
rajathr 0:34ee385f4d2d 1853
rajathr 0:34ee385f4d2d 1854 #if defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 1855 /**
rajathr 0:34ee385f4d2d 1856 * @brief Configures the SAI clock Divider coming from PLLI2S.
rajathr 0:34ee385f4d2d 1857 *
rajathr 0:34ee385f4d2d 1858 * @note This function can be used only for STM32F413_423xx
rajathr 0:34ee385f4d2d 1859 *
rajathr 0:34ee385f4d2d 1860 * @param RCC_PLLI2SDivR: specifies the PLLI2S division factor for SAI1 clock.
rajathr 0:34ee385f4d2d 1861 * This parameter must be a number between 1 and 32.
rajathr 0:34ee385f4d2d 1862 * SAI1 clock frequency = f(PLLI2SR) / RCC_PLLI2SDivR
rajathr 0:34ee385f4d2d 1863 * @retval None
rajathr 0:34ee385f4d2d 1864 */
rajathr 0:34ee385f4d2d 1865 void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR)
rajathr 0:34ee385f4d2d 1866 {
rajathr 0:34ee385f4d2d 1867 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1868
rajathr 0:34ee385f4d2d 1869 /* Check the parameters */
rajathr 0:34ee385f4d2d 1870 assert_param(IS_RCC_PLLI2S_DIVR_VALUE(RCC_PLLI2SDivR));
rajathr 0:34ee385f4d2d 1871
rajathr 0:34ee385f4d2d 1872 tmpreg = RCC->DCKCFGR;
rajathr 0:34ee385f4d2d 1873
rajathr 0:34ee385f4d2d 1874 /* Clear PLLI2SDIVR[4:0] bits */
rajathr 0:34ee385f4d2d 1875 tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVR);
rajathr 0:34ee385f4d2d 1876
rajathr 0:34ee385f4d2d 1877 /* Set PLLI2SDIVR values */
rajathr 0:34ee385f4d2d 1878 tmpreg |= (RCC_PLLI2SDivR-1);
rajathr 0:34ee385f4d2d 1879
rajathr 0:34ee385f4d2d 1880 /* Store the new value */
rajathr 0:34ee385f4d2d 1881 RCC->DCKCFGR = tmpreg;
rajathr 0:34ee385f4d2d 1882 }
rajathr 0:34ee385f4d2d 1883
rajathr 0:34ee385f4d2d 1884 /**
rajathr 0:34ee385f4d2d 1885 * @brief Configures the SAI clock Divider coming from PLL.
rajathr 0:34ee385f4d2d 1886 *
rajathr 0:34ee385f4d2d 1887 * @note This function can be used only for STM32F413_423xx
rajathr 0:34ee385f4d2d 1888 *
rajathr 0:34ee385f4d2d 1889 * @note This function must be called before enabling the PLLSAI.
rajathr 0:34ee385f4d2d 1890 *
rajathr 0:34ee385f4d2d 1891 * @param RCC_PLLDivR: specifies the PLL division factor for SAI1 clock.
rajathr 0:34ee385f4d2d 1892 * This parameter must be a number between 1 and 32.
rajathr 0:34ee385f4d2d 1893 * SAI1 clock frequency = f(PLLR) / RCC_PLLDivR
rajathr 0:34ee385f4d2d 1894 *
rajathr 0:34ee385f4d2d 1895 * @retval None
rajathr 0:34ee385f4d2d 1896 */
rajathr 0:34ee385f4d2d 1897 void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR)
rajathr 0:34ee385f4d2d 1898 {
rajathr 0:34ee385f4d2d 1899 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1900
rajathr 0:34ee385f4d2d 1901 /* Check the parameters */
rajathr 0:34ee385f4d2d 1902 assert_param(IS_RCC_PLL_DIVR_VALUE(RCC_PLLDivR));
rajathr 0:34ee385f4d2d 1903
rajathr 0:34ee385f4d2d 1904 tmpreg = RCC->DCKCFGR;
rajathr 0:34ee385f4d2d 1905
rajathr 0:34ee385f4d2d 1906 /* Clear PLLDIVR[12:8] */
rajathr 0:34ee385f4d2d 1907 tmpreg &= ~(RCC_DCKCFGR_PLLDIVR);
rajathr 0:34ee385f4d2d 1908
rajathr 0:34ee385f4d2d 1909 /* Set PLLDivR values */
rajathr 0:34ee385f4d2d 1910 tmpreg |= ((RCC_PLLDivR - 1 ) << 8);
rajathr 0:34ee385f4d2d 1911
rajathr 0:34ee385f4d2d 1912 /* Store the new value */
rajathr 0:34ee385f4d2d 1913 RCC->DCKCFGR = tmpreg;
rajathr 0:34ee385f4d2d 1914 }
rajathr 0:34ee385f4d2d 1915 #endif /* STM32F413_423xx */
rajathr 0:34ee385f4d2d 1916
rajathr 0:34ee385f4d2d 1917 /**
rajathr 0:34ee385f4d2d 1918 * @brief Configures the LTDC clock Divider coming from PLLSAI.
rajathr 0:34ee385f4d2d 1919 *
rajathr 0:34ee385f4d2d 1920 * @note The LTDC peripheral is only available with STM32F42xxx/43xxx/446xx/469xx/479xx Devices.
rajathr 0:34ee385f4d2d 1921 *
rajathr 0:34ee385f4d2d 1922 * @note This function must be called before enabling the PLLSAI.
rajathr 0:34ee385f4d2d 1923 *
rajathr 0:34ee385f4d2d 1924 * @param RCC_PLLSAIDivR: specifies the PLLSAI division factor for LTDC clock .
rajathr 0:34ee385f4d2d 1925 * LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR
rajathr 0:34ee385f4d2d 1926 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1927 * @arg RCC_PLLSAIDivR_Div2: LTDC clock = f(PLLSAI_R)/2
rajathr 0:34ee385f4d2d 1928 * @arg RCC_PLLSAIDivR_Div4: LTDC clock = f(PLLSAI_R)/4
rajathr 0:34ee385f4d2d 1929 * @arg RCC_PLLSAIDivR_Div8: LTDC clock = f(PLLSAI_R)/8
rajathr 0:34ee385f4d2d 1930 * @arg RCC_PLLSAIDivR_Div16: LTDC clock = f(PLLSAI_R)/16
rajathr 0:34ee385f4d2d 1931 *
rajathr 0:34ee385f4d2d 1932 * @retval None
rajathr 0:34ee385f4d2d 1933 */
rajathr 0:34ee385f4d2d 1934 void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
rajathr 0:34ee385f4d2d 1935 {
rajathr 0:34ee385f4d2d 1936 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1937
rajathr 0:34ee385f4d2d 1938 /* Check the parameters */
rajathr 0:34ee385f4d2d 1939 assert_param(IS_RCC_PLLSAI_DIVR_VALUE_MORT(RCC_PLLSAIDivR));
rajathr 0:34ee385f4d2d 1940
rajathr 0:34ee385f4d2d 1941 tmpreg = RCC->DCKCFGR;
rajathr 0:34ee385f4d2d 1942
rajathr 0:34ee385f4d2d 1943 /* Clear PLLSAIDIVR[2:0] bits */
rajathr 0:34ee385f4d2d 1944 tmpreg &= ~RCC_DCKCFGR_PLLSAIDIVR_MORT;
rajathr 0:34ee385f4d2d 1945
rajathr 0:34ee385f4d2d 1946 /* Set PLLSAIDIVR values */
rajathr 0:34ee385f4d2d 1947 tmpreg |= RCC_PLLSAIDivR;
rajathr 0:34ee385f4d2d 1948
rajathr 0:34ee385f4d2d 1949 /* Store the new value */
rajathr 0:34ee385f4d2d 1950 RCC->DCKCFGR = tmpreg;
rajathr 0:34ee385f4d2d 1951 }
rajathr 0:34ee385f4d2d 1952
rajathr 0:34ee385f4d2d 1953 #if defined(STM32F412xG) || defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 1954 /**
rajathr 0:34ee385f4d2d 1955 * @brief Configures the DFSDM clock source (DFSDMCLK).
rajathr 0:34ee385f4d2d 1956 * @note This function must be called before enabling the DFSDM APB clock.
rajathr 0:34ee385f4d2d 1957 * @param RCC_DFSDMCLKSource: specifies the DFSDM clock source.
rajathr 0:34ee385f4d2d 1958 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1959 * @arg RCC_DFSDMCLKSource_APB: APB clock used as DFSDM clock source.
rajathr 0:34ee385f4d2d 1960 * @arg RCC_DFSDMCLKSource_SYS: System clock used as DFSDM clock source.
rajathr 0:34ee385f4d2d 1961 *
rajathr 0:34ee385f4d2d 1962 * @retval None
rajathr 0:34ee385f4d2d 1963 */
rajathr 0:34ee385f4d2d 1964 void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDMCLKSource)
rajathr 0:34ee385f4d2d 1965 {
rajathr 0:34ee385f4d2d 1966 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1967
rajathr 0:34ee385f4d2d 1968 /* Check the parameters */
rajathr 0:34ee385f4d2d 1969 assert_param(IS_RCC_DFSDM1CLK_SOURCE(RCC_DFSDMCLKSource));
rajathr 0:34ee385f4d2d 1970
rajathr 0:34ee385f4d2d 1971 tmpreg = RCC->DCKCFGR;
rajathr 0:34ee385f4d2d 1972
rajathr 0:34ee385f4d2d 1973 /* Clear CKDFSDM-SEL bit */
rajathr 0:34ee385f4d2d 1974 tmpreg &= ~RCC_DCKCFGR_CKDFSDM1SEL;
rajathr 0:34ee385f4d2d 1975
rajathr 0:34ee385f4d2d 1976 /* Set CKDFSDM-SEL bit according to RCC_DFSDMCLKSource value */
rajathr 0:34ee385f4d2d 1977 tmpreg |= (RCC_DFSDMCLKSource << 31) ;
rajathr 0:34ee385f4d2d 1978
rajathr 0:34ee385f4d2d 1979 /* Store the new value */
rajathr 0:34ee385f4d2d 1980 RCC->DCKCFGR = tmpreg;
rajathr 0:34ee385f4d2d 1981 }
rajathr 0:34ee385f4d2d 1982
rajathr 0:34ee385f4d2d 1983 /**
rajathr 0:34ee385f4d2d 1984 * @brief Configures the DFSDM Audio clock source (DFSDMACLK).
rajathr 0:34ee385f4d2d 1985 * @note This function must be called before enabling the DFSDM APB clock.
rajathr 0:34ee385f4d2d 1986 * @param RCC_DFSDM1ACLKSource: specifies the DFSDM clock source.
rajathr 0:34ee385f4d2d 1987 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 1988 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source.
rajathr 0:34ee385f4d2d 1989 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source.
rajathr 0:34ee385f4d2d 1990 *
rajathr 0:34ee385f4d2d 1991 * @retval None
rajathr 0:34ee385f4d2d 1992 */
rajathr 0:34ee385f4d2d 1993 void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource)
rajathr 0:34ee385f4d2d 1994 {
rajathr 0:34ee385f4d2d 1995 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 1996
rajathr 0:34ee385f4d2d 1997 /* Check the parameters */
rajathr 0:34ee385f4d2d 1998 assert_param(IS_RCC_DFSDMACLK_SOURCE(RCC_DFSDM1ACLKSource));
rajathr 0:34ee385f4d2d 1999
rajathr 0:34ee385f4d2d 2000 tmpreg = RCC->DCKCFGR;
rajathr 0:34ee385f4d2d 2001
rajathr 0:34ee385f4d2d 2002 /* Clear CKDFSDMA SEL bit */
rajathr 0:34ee385f4d2d 2003 tmpreg &= ~RCC_DCKCFGR_CKDFSDM1ASEL;
rajathr 0:34ee385f4d2d 2004
rajathr 0:34ee385f4d2d 2005 /* Set CKDFSDM-SEL bt according to RCC_DFSDMCLKSource value */
rajathr 0:34ee385f4d2d 2006 tmpreg |= RCC_DFSDM1ACLKSource;
rajathr 0:34ee385f4d2d 2007
rajathr 0:34ee385f4d2d 2008 /* Store the new value */
rajathr 0:34ee385f4d2d 2009 RCC->DCKCFGR = tmpreg;
rajathr 0:34ee385f4d2d 2010 }
rajathr 0:34ee385f4d2d 2011
rajathr 0:34ee385f4d2d 2012 #if defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 2013 /**
rajathr 0:34ee385f4d2d 2014 * @brief Configures the DFSDM Audio clock source (DFSDMACLK).
rajathr 0:34ee385f4d2d 2015 * @note This function must be called before enabling the DFSDM APB clock.
rajathr 0:34ee385f4d2d 2016 * @param RCC_DFSDM2ACLKSource: specifies the DFSDM clock source.
rajathr 0:34ee385f4d2d 2017 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2018 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source.
rajathr 0:34ee385f4d2d 2019 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source.
rajathr 0:34ee385f4d2d 2020 *
rajathr 0:34ee385f4d2d 2021 * @retval None
rajathr 0:34ee385f4d2d 2022 */
rajathr 0:34ee385f4d2d 2023 void RCC_DFSDM2ACLKConfig(uint32_t RCC_DFSDMACLKSource)
rajathr 0:34ee385f4d2d 2024 {
rajathr 0:34ee385f4d2d 2025 uint32_t tmpreg = 0;
rajathr 0:34ee385f4d2d 2026
rajathr 0:34ee385f4d2d 2027 /* Check the parameters */
rajathr 0:34ee385f4d2d 2028 assert_param(IS_RCC_DFSDMCLK_SOURCE(RCC_DFSDMACLKSource));
rajathr 0:34ee385f4d2d 2029
rajathr 0:34ee385f4d2d 2030 tmpreg = RCC->DCKCFGR;
rajathr 0:34ee385f4d2d 2031
rajathr 0:34ee385f4d2d 2032 /* Clear CKDFSDMA SEL bit */
rajathr 0:34ee385f4d2d 2033 tmpreg &= ~RCC_DCKCFGR_CKDFSDM1ASEL;
rajathr 0:34ee385f4d2d 2034
rajathr 0:34ee385f4d2d 2035 /* Set CKDFSDM-SEL bt according to RCC_DFSDMCLKSource value */
rajathr 0:34ee385f4d2d 2036 tmpreg |= RCC_DFSDMACLKSource;
rajathr 0:34ee385f4d2d 2037
rajathr 0:34ee385f4d2d 2038 /* Store the new value */
rajathr 0:34ee385f4d2d 2039 RCC->DCKCFGR = tmpreg;
rajathr 0:34ee385f4d2d 2040 }
rajathr 0:34ee385f4d2d 2041 #endif /* STM32F413_423xx */
rajathr 0:34ee385f4d2d 2042 #endif /* STM32F412xG || STM32F413_423xx */
rajathr 0:34ee385f4d2d 2043
rajathr 0:34ee385f4d2d 2044 /**
rajathr 0:34ee385f4d2d 2045 * @brief Configures the Timers clocks prescalers selection.
rajathr 0:34ee385f4d2d 2046 *
rajathr 0:34ee385f4d2d 2047 * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
rajathr 0:34ee385f4d2d 2048 *
rajathr 0:34ee385f4d2d 2049 * @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection
rajathr 0:34ee385f4d2d 2050 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2051 * @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is
rajathr 0:34ee385f4d2d 2052 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
rajathr 0:34ee385f4d2d 2053 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
rajathr 0:34ee385f4d2d 2054 * division by 4 or more.
rajathr 0:34ee385f4d2d 2055 *
rajathr 0:34ee385f4d2d 2056 * @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is
rajathr 0:34ee385f4d2d 2057 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
rajathr 0:34ee385f4d2d 2058 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
rajathr 0:34ee385f4d2d 2059 * to division by 8 or more.
rajathr 0:34ee385f4d2d 2060 * @retval None
rajathr 0:34ee385f4d2d 2061 */
rajathr 0:34ee385f4d2d 2062 void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
rajathr 0:34ee385f4d2d 2063 {
rajathr 0:34ee385f4d2d 2064 /* Check the parameters */
rajathr 0:34ee385f4d2d 2065 assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler));
rajathr 0:34ee385f4d2d 2066
rajathr 0:34ee385f4d2d 2067 *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler;
rajathr 0:34ee385f4d2d 2068 }
rajathr 0:34ee385f4d2d 2069
rajathr 0:34ee385f4d2d 2070 /**
rajathr 0:34ee385f4d2d 2071 * @brief Enables or disables the AHB1 peripheral clock.
rajathr 0:34ee385f4d2d 2072 * @note After reset, the peripheral clock (used for registers read/write access)
rajathr 0:34ee385f4d2d 2073 * is disabled and the application software has to enable this clock before
rajathr 0:34ee385f4d2d 2074 * using it.
rajathr 0:34ee385f4d2d 2075 * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
rajathr 0:34ee385f4d2d 2076 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2077 * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
rajathr 0:34ee385f4d2d 2078 * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
rajathr 0:34ee385f4d2d 2079 * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
rajathr 0:34ee385f4d2d 2080 * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
rajathr 0:34ee385f4d2d 2081 * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
rajathr 0:34ee385f4d2d 2082 * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
rajathr 0:34ee385f4d2d 2083 * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
rajathr 0:34ee385f4d2d 2084 * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
rajathr 0:34ee385f4d2d 2085 * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
rajathr 0:34ee385f4d2d 2086 * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
rajathr 0:34ee385f4d2d 2087 * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
rajathr 0:34ee385f4d2d 2088 * @arg RCC_AHB1Periph_CRC: CRC clock
rajathr 0:34ee385f4d2d 2089 * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
rajathr 0:34ee385f4d2d 2090 * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
rajathr 0:34ee385f4d2d 2091 * @arg RCC_AHB1Periph_DMA1: DMA1_MORT clock
rajathr 0:34ee385f4d2d 2092 * @arg RCC_AHB1Periph_DMA2: DMA2_MORT clock
rajathr 0:34ee385f4d2d 2093 * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
rajathr 0:34ee385f4d2d 2094 * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
rajathr 0:34ee385f4d2d 2095 * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
rajathr 0:34ee385f4d2d 2096 * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
rajathr 0:34ee385f4d2d 2097 * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
rajathr 0:34ee385f4d2d 2098 * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
rajathr 0:34ee385f4d2d 2099 * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
rajathr 0:34ee385f4d2d 2100 * @param NewState: new state of the specified peripheral clock.
rajathr 0:34ee385f4d2d 2101 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2102 * @retval None
rajathr 0:34ee385f4d2d 2103 */
rajathr 0:34ee385f4d2d 2104 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2105 {
rajathr 0:34ee385f4d2d 2106 /* Check the parameters */
rajathr 0:34ee385f4d2d 2107 assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
rajathr 0:34ee385f4d2d 2108
rajathr 0:34ee385f4d2d 2109 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2110 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2111 {
rajathr 0:34ee385f4d2d 2112 RCC->AHB1ENR |= RCC_AHB1Periph;
rajathr 0:34ee385f4d2d 2113 }
rajathr 0:34ee385f4d2d 2114 else
rajathr 0:34ee385f4d2d 2115 {
rajathr 0:34ee385f4d2d 2116 RCC->AHB1ENR &= ~RCC_AHB1Periph;
rajathr 0:34ee385f4d2d 2117 }
rajathr 0:34ee385f4d2d 2118 }
rajathr 0:34ee385f4d2d 2119
rajathr 0:34ee385f4d2d 2120 /**
rajathr 0:34ee385f4d2d 2121 * @brief Enables or disables the AHB2 peripheral clock.
rajathr 0:34ee385f4d2d 2122 * @note After reset, the peripheral clock (used for registers read/write access)
rajathr 0:34ee385f4d2d 2123 * is disabled and the application software has to enable this clock before
rajathr 0:34ee385f4d2d 2124 * using it.
rajathr 0:34ee385f4d2d 2125 * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
rajathr 0:34ee385f4d2d 2126 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2127 * @arg RCC_AHB2Periph_DCMI: DCMI clock
rajathr 0:34ee385f4d2d 2128 * @arg RCC_AHB2Periph_CRYP: CRYP clock
rajathr 0:34ee385f4d2d 2129 * @arg RCC_AHB2Periph_HASH: HASH clock
rajathr 0:34ee385f4d2d 2130 * @arg RCC_AHB2Periph_RNG: RNG clock
rajathr 0:34ee385f4d2d 2131 * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
rajathr 0:34ee385f4d2d 2132 * @param NewState: new state of the specified peripheral clock.
rajathr 0:34ee385f4d2d 2133 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2134 * @retval None
rajathr 0:34ee385f4d2d 2135 */
rajathr 0:34ee385f4d2d 2136 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2137 {
rajathr 0:34ee385f4d2d 2138 /* Check the parameters */
rajathr 0:34ee385f4d2d 2139 assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
rajathr 0:34ee385f4d2d 2140 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2141
rajathr 0:34ee385f4d2d 2142 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2143 {
rajathr 0:34ee385f4d2d 2144 RCC->AHB2ENR |= RCC_AHB2Periph;
rajathr 0:34ee385f4d2d 2145 }
rajathr 0:34ee385f4d2d 2146 else
rajathr 0:34ee385f4d2d 2147 {
rajathr 0:34ee385f4d2d 2148 RCC->AHB2ENR &= ~RCC_AHB2Periph;
rajathr 0:34ee385f4d2d 2149 }
rajathr 0:34ee385f4d2d 2150 }
rajathr 0:34ee385f4d2d 2151
rajathr 0:34ee385f4d2d 2152 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 2153 /**
rajathr 0:34ee385f4d2d 2154 * @brief Enables or disables the AHB3 peripheral clock.
rajathr 0:34ee385f4d2d 2155 * @note After reset, the peripheral clock (used for registers read/write access)
rajathr 0:34ee385f4d2d 2156 * is disabled and the application software has to enable this clock before
rajathr 0:34ee385f4d2d 2157 * using it.
rajathr 0:34ee385f4d2d 2158 * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
rajathr 0:34ee385f4d2d 2159 * This parameter must be:
rajathr 0:34ee385f4d2d 2160 * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices)
rajathr 0:34ee385f4d2d 2161 * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices)
rajathr 0:34ee385f4d2d 2162 * @param NewState: new state of the specified peripheral clock.
rajathr 0:34ee385f4d2d 2163 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2164 * @retval None
rajathr 0:34ee385f4d2d 2165 */
rajathr 0:34ee385f4d2d 2166 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2167 {
rajathr 0:34ee385f4d2d 2168 /* Check the parameters */
rajathr 0:34ee385f4d2d 2169 assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
rajathr 0:34ee385f4d2d 2170 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2171
rajathr 0:34ee385f4d2d 2172 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2173 {
rajathr 0:34ee385f4d2d 2174 RCC->AHB3ENR |= RCC_AHB3Periph;
rajathr 0:34ee385f4d2d 2175 }
rajathr 0:34ee385f4d2d 2176 else
rajathr 0:34ee385f4d2d 2177 {
rajathr 0:34ee385f4d2d 2178 RCC->AHB3ENR &= ~RCC_AHB3Periph;
rajathr 0:34ee385f4d2d 2179 }
rajathr 0:34ee385f4d2d 2180 }
rajathr 0:34ee385f4d2d 2181 #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 2182
rajathr 0:34ee385f4d2d 2183 /**
rajathr 0:34ee385f4d2d 2184 * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
rajathr 0:34ee385f4d2d 2185 * @note After reset, the peripheral clock (used for registers read/write access)
rajathr 0:34ee385f4d2d 2186 * is disabled and the application software has to enable this clock before
rajathr 0:34ee385f4d2d 2187 * using it.
rajathr 0:34ee385f4d2d 2188 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
rajathr 0:34ee385f4d2d 2189 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2190 * @arg RCC_APB1Periph_TIM2: TIM2 clock
rajathr 0:34ee385f4d2d 2191 * @arg RCC_APB1Periph_TIM3: TIM3 clock
rajathr 0:34ee385f4d2d 2192 * @arg RCC_APB1Periph_TIM4: TIM4 clock
rajathr 0:34ee385f4d2d 2193 * @arg RCC_APB1Periph_TIM5: TIM5 clock
rajathr 0:34ee385f4d2d 2194 * @arg RCC_APB1Periph_TIM6: TIM6 clock
rajathr 0:34ee385f4d2d 2195 * @arg RCC_APB1Periph_TIM7: TIM7 clock
rajathr 0:34ee385f4d2d 2196 * @arg RCC_APB1Periph_TIM12: TIM12 clock
rajathr 0:34ee385f4d2d 2197 * @arg RCC_APB1Periph_TIM13: TIM13 clock
rajathr 0:34ee385f4d2d 2198 * @arg RCC_APB1Periph_TIM14: TIM14 clock
rajathr 0:34ee385f4d2d 2199 * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices)
rajathr 0:34ee385f4d2d 2200 * @arg RCC_APB1Periph_WWDG: WWDG clock
rajathr 0:34ee385f4d2d 2201 * @arg RCC_APB1Periph_SPI2: SPI2 clock
rajathr 0:34ee385f4d2d 2202 * @arg RCC_APB1Periph_SPI3: SPI3 clock
rajathr 0:34ee385f4d2d 2203 * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
rajathr 0:34ee385f4d2d 2204 * @arg RCC_APB1Periph_USART2: USART2 clock
rajathr 0:34ee385f4d2d 2205 * @arg RCC_APB1Periph_USART3: USART3 clock
rajathr 0:34ee385f4d2d 2206 * @arg RCC_APB1Periph_UART4: UART4 clock
rajathr 0:34ee385f4d2d 2207 * @arg RCC_APB1Periph_UART5: UART5 clock
rajathr 0:34ee385f4d2d 2208 * @arg RCC_APB1Periph_I2C1: I2C1 clock
rajathr 0:34ee385f4d2d 2209 * @arg RCC_APB1Periph_I2C2: I2C2 clock
rajathr 0:34ee385f4d2d 2210 * @arg RCC_APB1Periph_I2C3: I2C3 clock
rajathr 0:34ee385f4d2d 2211 * @arg RCC_APB1Periph_FMPI2C1:FMPI2C1 clock
rajathr 0:34ee385f4d2d 2212 * @arg RCC_APB1Periph_CAN1: CAN1 clock
rajathr 0:34ee385f4d2d 2213 * @arg RCC_APB1Periph_CAN2: CAN2 clock
rajathr 0:34ee385f4d2d 2214 * @arg RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices)
rajathr 0:34ee385f4d2d 2215 * @arg RCC_APB1Periph_PWR: PWR clock
rajathr 0:34ee385f4d2d 2216 * @arg RCC_APB1Periph_DAC: DAC clock
rajathr 0:34ee385f4d2d 2217 * @arg RCC_APB1Periph_UART7: UART7 clock
rajathr 0:34ee385f4d2d 2218 * @arg RCC_APB1Periph_UART8: UART8 clock
rajathr 0:34ee385f4d2d 2219 * @param NewState: new state of the specified peripheral clock.
rajathr 0:34ee385f4d2d 2220 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2221 * @retval None
rajathr 0:34ee385f4d2d 2222 */
rajathr 0:34ee385f4d2d 2223 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2224 {
rajathr 0:34ee385f4d2d 2225 /* Check the parameters */
rajathr 0:34ee385f4d2d 2226 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
rajathr 0:34ee385f4d2d 2227 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2228
rajathr 0:34ee385f4d2d 2229 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2230 {
rajathr 0:34ee385f4d2d 2231 RCC->APB1ENR |= RCC_APB1Periph;
rajathr 0:34ee385f4d2d 2232 }
rajathr 0:34ee385f4d2d 2233 else
rajathr 0:34ee385f4d2d 2234 {
rajathr 0:34ee385f4d2d 2235 RCC->APB1ENR &= ~RCC_APB1Periph;
rajathr 0:34ee385f4d2d 2236 }
rajathr 0:34ee385f4d2d 2237 }
rajathr 0:34ee385f4d2d 2238
rajathr 0:34ee385f4d2d 2239 /**
rajathr 0:34ee385f4d2d 2240 * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
rajathr 0:34ee385f4d2d 2241 * @note After reset, the peripheral clock (used for registers read/write access)
rajathr 0:34ee385f4d2d 2242 * is disabled and the application software has to enable this clock before
rajathr 0:34ee385f4d2d 2243 * using it.
rajathr 0:34ee385f4d2d 2244 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
rajathr 0:34ee385f4d2d 2245 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2246 * @arg RCC_APB2Periph_TIM1: TIM1 clock
rajathr 0:34ee385f4d2d 2247 * @arg RCC_APB2Periph_TIM8: TIM8 clock
rajathr 0:34ee385f4d2d 2248 * @arg RCC_APB2Periph_USART1: USART1 clock
rajathr 0:34ee385f4d2d 2249 * @arg RCC_APB2Periph_USART6: USART6 clock
rajathr 0:34ee385f4d2d 2250 * @arg RCC_APB2Periph_ADC1: ADC1 clock
rajathr 0:34ee385f4d2d 2251 * @arg RCC_APB2Periph_ADC2: ADC2 clock
rajathr 0:34ee385f4d2d 2252 * @arg RCC_APB2Periph_ADC3: ADC3 clock
rajathr 0:34ee385f4d2d 2253 * @arg RCC_APB2Periph_SDIO: SDIO clock
rajathr 0:34ee385f4d2d 2254 * @arg RCC_APB2Periph_SPI1: SPI1 clock
rajathr 0:34ee385f4d2d 2255 * @arg RCC_APB2Periph_SPI4: SPI4 clock
rajathr 0:34ee385f4d2d 2256 * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
rajathr 0:34ee385f4d2d 2257 * @arg RCC_APB2Periph_EXTIT: EXTIIT clock
rajathr 0:34ee385f4d2d 2258 * @arg RCC_APB2Periph_TIM9: TIM9 clock
rajathr 0:34ee385f4d2d 2259 * @arg RCC_APB2Periph_TIM10: TIM10 clock
rajathr 0:34ee385f4d2d 2260 * @arg RCC_APB2Periph_TIM11: TIM11 clock
rajathr 0:34ee385f4d2d 2261 * @arg RCC_APB2Periph_SPI5: SPI5 clock
rajathr 0:34ee385f4d2d 2262 * @arg RCC_APB2Periph_SPI6: SPI6 clock
rajathr 0:34ee385f4d2d 2263 * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices)
rajathr 0:34ee385f4d2d 2264 * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
rajathr 0:34ee385f4d2d 2265 * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
rajathr 0:34ee385f4d2d 2266 * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
rajathr 0:34ee385f4d2d 2267 * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices)
rajathr 0:34ee385f4d2d 2268 * @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices)
rajathr 0:34ee385f4d2d 2269 * @arg RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices)
rajathr 0:34ee385f4d2d 2270 * @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)
rajathr 0:34ee385f4d2d 2271 * @param NewState: new state of the specified peripheral clock.
rajathr 0:34ee385f4d2d 2272 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2273 * @retval None
rajathr 0:34ee385f4d2d 2274 */
rajathr 0:34ee385f4d2d 2275 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2276 {
rajathr 0:34ee385f4d2d 2277 /* Check the parameters */
rajathr 0:34ee385f4d2d 2278 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
rajathr 0:34ee385f4d2d 2279 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2280
rajathr 0:34ee385f4d2d 2281 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2282 {
rajathr 0:34ee385f4d2d 2283 RCC->APB2ENR |= RCC_APB2Periph;
rajathr 0:34ee385f4d2d 2284 }
rajathr 0:34ee385f4d2d 2285 else
rajathr 0:34ee385f4d2d 2286 {
rajathr 0:34ee385f4d2d 2287 RCC->APB2ENR &= ~RCC_APB2Periph;
rajathr 0:34ee385f4d2d 2288 }
rajathr 0:34ee385f4d2d 2289 }
rajathr 0:34ee385f4d2d 2290
rajathr 0:34ee385f4d2d 2291 /**
rajathr 0:34ee385f4d2d 2292 * @brief Forces or releases AHB1 peripheral reset.
rajathr 0:34ee385f4d2d 2293 * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset.
rajathr 0:34ee385f4d2d 2294 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2295 * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
rajathr 0:34ee385f4d2d 2296 * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
rajathr 0:34ee385f4d2d 2297 * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
rajathr 0:34ee385f4d2d 2298 * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
rajathr 0:34ee385f4d2d 2299 * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
rajathr 0:34ee385f4d2d 2300 * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
rajathr 0:34ee385f4d2d 2301 * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
rajathr 0:34ee385f4d2d 2302 * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
rajathr 0:34ee385f4d2d 2303 * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
rajathr 0:34ee385f4d2d 2304 * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
rajathr 0:34ee385f4d2d 2305 * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices)
rajathr 0:34ee385f4d2d 2306 * @arg RCC_AHB1Periph_CRC: CRC clock
rajathr 0:34ee385f4d2d 2307 * @arg RCC_AHB1Periph_DMA1: DMA1_MORT clock
rajathr 0:34ee385f4d2d 2308 * @arg RCC_AHB1Periph_DMA2: DMA2_MORT clock
rajathr 0:34ee385f4d2d 2309 * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
rajathr 0:34ee385f4d2d 2310 * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
rajathr 0:34ee385f4d2d 2311 * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
rajathr 0:34ee385f4d2d 2312 * @arg RCC_AHB1Periph_RNG: RNG clock for STM32F410xx devices
rajathr 0:34ee385f4d2d 2313 * @param NewState: new state of the specified peripheral reset.
rajathr 0:34ee385f4d2d 2314 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2315 * @retval None
rajathr 0:34ee385f4d2d 2316 */
rajathr 0:34ee385f4d2d 2317 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2318 {
rajathr 0:34ee385f4d2d 2319 /* Check the parameters */
rajathr 0:34ee385f4d2d 2320 assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
rajathr 0:34ee385f4d2d 2321 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2322
rajathr 0:34ee385f4d2d 2323 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2324 {
rajathr 0:34ee385f4d2d 2325 RCC->AHB1RSTR |= RCC_AHB1Periph;
rajathr 0:34ee385f4d2d 2326 }
rajathr 0:34ee385f4d2d 2327 else
rajathr 0:34ee385f4d2d 2328 {
rajathr 0:34ee385f4d2d 2329 RCC->AHB1RSTR &= ~RCC_AHB1Periph;
rajathr 0:34ee385f4d2d 2330 }
rajathr 0:34ee385f4d2d 2331 }
rajathr 0:34ee385f4d2d 2332
rajathr 0:34ee385f4d2d 2333 /**
rajathr 0:34ee385f4d2d 2334 * @brief Forces or releases AHB2 peripheral reset.
rajathr 0:34ee385f4d2d 2335 * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
rajathr 0:34ee385f4d2d 2336 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2337 * @arg RCC_AHB2Periph_DCMI: DCMI clock
rajathr 0:34ee385f4d2d 2338 * @arg RCC_AHB2Periph_CRYP: CRYP clock
rajathr 0:34ee385f4d2d 2339 * @arg RCC_AHB2Periph_HASH: HASH clock
rajathr 0:34ee385f4d2d 2340 * @arg RCC_AHB2Periph_RNG: RNG clock for STM32F40_41xxx/STM32F412xG/STM32F413_423xx/STM32F427_437xx/STM32F429_439xx/STM32F469_479xx devices
rajathr 0:34ee385f4d2d 2341 * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
rajathr 0:34ee385f4d2d 2342 * @param NewState: new state of the specified peripheral reset.
rajathr 0:34ee385f4d2d 2343 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2344 * @retval None
rajathr 0:34ee385f4d2d 2345 */
rajathr 0:34ee385f4d2d 2346 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2347 {
rajathr 0:34ee385f4d2d 2348 /* Check the parameters */
rajathr 0:34ee385f4d2d 2349 assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
rajathr 0:34ee385f4d2d 2350 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2351
rajathr 0:34ee385f4d2d 2352 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2353 {
rajathr 0:34ee385f4d2d 2354 RCC->AHB2RSTR |= RCC_AHB2Periph;
rajathr 0:34ee385f4d2d 2355 }
rajathr 0:34ee385f4d2d 2356 else
rajathr 0:34ee385f4d2d 2357 {
rajathr 0:34ee385f4d2d 2358 RCC->AHB2RSTR &= ~RCC_AHB2Periph;
rajathr 0:34ee385f4d2d 2359 }
rajathr 0:34ee385f4d2d 2360 }
rajathr 0:34ee385f4d2d 2361
rajathr 0:34ee385f4d2d 2362 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 2363 /**
rajathr 0:34ee385f4d2d 2364 * @brief Forces or releases AHB3 peripheral reset.
rajathr 0:34ee385f4d2d 2365 * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
rajathr 0:34ee385f4d2d 2366 * This parameter must be:
rajathr 0:34ee385f4d2d 2367 * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG, STM32F413_423xx and STM32F429x/439x devices)
rajathr 0:34ee385f4d2d 2368 * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices)
rajathr 0:34ee385f4d2d 2369 * @param NewState: new state of the specified peripheral reset.
rajathr 0:34ee385f4d2d 2370 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2371 * @retval None
rajathr 0:34ee385f4d2d 2372 */
rajathr 0:34ee385f4d2d 2373 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2374 {
rajathr 0:34ee385f4d2d 2375 /* Check the parameters */
rajathr 0:34ee385f4d2d 2376 assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
rajathr 0:34ee385f4d2d 2377 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2378
rajathr 0:34ee385f4d2d 2379 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2380 {
rajathr 0:34ee385f4d2d 2381 RCC->AHB3RSTR |= RCC_AHB3Periph;
rajathr 0:34ee385f4d2d 2382 }
rajathr 0:34ee385f4d2d 2383 else
rajathr 0:34ee385f4d2d 2384 {
rajathr 0:34ee385f4d2d 2385 RCC->AHB3RSTR &= ~RCC_AHB3Periph;
rajathr 0:34ee385f4d2d 2386 }
rajathr 0:34ee385f4d2d 2387 }
rajathr 0:34ee385f4d2d 2388 #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 2389
rajathr 0:34ee385f4d2d 2390 /**
rajathr 0:34ee385f4d2d 2391 * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
rajathr 0:34ee385f4d2d 2392 * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
rajathr 0:34ee385f4d2d 2393 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2394 * @arg RCC_APB1Periph_TIM2: TIM2 clock
rajathr 0:34ee385f4d2d 2395 * @arg RCC_APB1Periph_TIM3: TIM3 clock
rajathr 0:34ee385f4d2d 2396 * @arg RCC_APB1Periph_TIM4: TIM4 clock
rajathr 0:34ee385f4d2d 2397 * @arg RCC_APB1Periph_TIM5: TIM5 clock
rajathr 0:34ee385f4d2d 2398 * @arg RCC_APB1Periph_TIM6: TIM6 clock
rajathr 0:34ee385f4d2d 2399 * @arg RCC_APB1Periph_TIM7: TIM7 clock
rajathr 0:34ee385f4d2d 2400 * @arg RCC_APB1Periph_TIM12: TIM12 clock
rajathr 0:34ee385f4d2d 2401 * @arg RCC_APB1Periph_TIM13: TIM13 clock
rajathr 0:34ee385f4d2d 2402 * @arg RCC_APB1Periph_TIM14: TIM14 clock
rajathr 0:34ee385f4d2d 2403 * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices)
rajathr 0:34ee385f4d2d 2404 * @arg RCC_APB1Periph_WWDG: WWDG clock
rajathr 0:34ee385f4d2d 2405 * @arg RCC_APB1Periph_SPI2: SPI2 clock
rajathr 0:34ee385f4d2d 2406 * @arg RCC_APB1Periph_SPI3: SPI3 clock
rajathr 0:34ee385f4d2d 2407 * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
rajathr 0:34ee385f4d2d 2408 * @arg RCC_APB1Periph_USART2: USART2 clock
rajathr 0:34ee385f4d2d 2409 * @arg RCC_APB1Periph_USART3: USART3 clock
rajathr 0:34ee385f4d2d 2410 * @arg RCC_APB1Periph_UART4: UART4 clock
rajathr 0:34ee385f4d2d 2411 * @arg RCC_APB1Periph_UART5: UART5 clock
rajathr 0:34ee385f4d2d 2412 * @arg RCC_APB1Periph_I2C1: I2C1 clock
rajathr 0:34ee385f4d2d 2413 * @arg RCC_APB1Periph_I2C2: I2C2 clock
rajathr 0:34ee385f4d2d 2414 * @arg RCC_APB1Periph_I2C3: I2C3 clock
rajathr 0:34ee385f4d2d 2415 * @arg RCC_APB1Periph_FMPI2C1:FMPI2C1 clock
rajathr 0:34ee385f4d2d 2416 * @arg RCC_APB1Periph_CAN1: CAN1 clock
rajathr 0:34ee385f4d2d 2417 * @arg RCC_APB1Periph_CAN2: CAN2 clock
rajathr 0:34ee385f4d2d 2418 * @arg RCC_APB1Periph_CEC: CEC clock(STM32F446xx devices)
rajathr 0:34ee385f4d2d 2419 * @arg RCC_APB1Periph_PWR: PWR clock
rajathr 0:34ee385f4d2d 2420 * @arg RCC_APB1Periph_DAC: DAC clock
rajathr 0:34ee385f4d2d 2421 * @arg RCC_APB1Periph_UART7: UART7 clock
rajathr 0:34ee385f4d2d 2422 * @arg RCC_APB1Periph_UART8: UART8 clock
rajathr 0:34ee385f4d2d 2423 * @param NewState: new state of the specified peripheral reset.
rajathr 0:34ee385f4d2d 2424 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2425 * @retval None
rajathr 0:34ee385f4d2d 2426 */
rajathr 0:34ee385f4d2d 2427 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2428 {
rajathr 0:34ee385f4d2d 2429 /* Check the parameters */
rajathr 0:34ee385f4d2d 2430 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
rajathr 0:34ee385f4d2d 2431 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2432 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2433 {
rajathr 0:34ee385f4d2d 2434 RCC->APB1RSTR |= RCC_APB1Periph;
rajathr 0:34ee385f4d2d 2435 }
rajathr 0:34ee385f4d2d 2436 else
rajathr 0:34ee385f4d2d 2437 {
rajathr 0:34ee385f4d2d 2438 RCC->APB1RSTR &= ~RCC_APB1Periph;
rajathr 0:34ee385f4d2d 2439 }
rajathr 0:34ee385f4d2d 2440 }
rajathr 0:34ee385f4d2d 2441
rajathr 0:34ee385f4d2d 2442 /**
rajathr 0:34ee385f4d2d 2443 * @brief Forces or releases High Speed APB (APB2) peripheral reset.
rajathr 0:34ee385f4d2d 2444 * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
rajathr 0:34ee385f4d2d 2445 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2446 * @arg RCC_APB2Periph_TIM1: TIM1 clock
rajathr 0:34ee385f4d2d 2447 * @arg RCC_APB2Periph_TIM8: TIM8 clock
rajathr 0:34ee385f4d2d 2448 * @arg RCC_APB2Periph_USART1: USART1 clock
rajathr 0:34ee385f4d2d 2449 * @arg RCC_APB2Periph_USART6: USART6 clock
rajathr 0:34ee385f4d2d 2450 * @arg RCC_APB2Periph_ADC1: ADC1 clock
rajathr 0:34ee385f4d2d 2451 * @arg RCC_APB2Periph_ADC2: ADC2 clock
rajathr 0:34ee385f4d2d 2452 * @arg RCC_APB2Periph_ADC3: ADC3 clock
rajathr 0:34ee385f4d2d 2453 * @arg RCC_APB2Periph_SDIO: SDIO clock
rajathr 0:34ee385f4d2d 2454 * @arg RCC_APB2Periph_SPI1: SPI1 clock
rajathr 0:34ee385f4d2d 2455 * @arg RCC_APB2Periph_SPI4: SPI4 clock
rajathr 0:34ee385f4d2d 2456 * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
rajathr 0:34ee385f4d2d 2457 * @arg RCC_APB2Periph_TIM9: TIM9 clock
rajathr 0:34ee385f4d2d 2458 * @arg RCC_APB2Periph_TIM10: TIM10 clock
rajathr 0:34ee385f4d2d 2459 * @arg RCC_APB2Periph_TIM11: TIM11 clock
rajathr 0:34ee385f4d2d 2460 * @arg RCC_APB2Periph_SPI5: SPI5 clock
rajathr 0:34ee385f4d2d 2461 * @arg RCC_APB2Periph_SPI6: SPI6 clock
rajathr 0:34ee385f4d2d 2462 * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices)
rajathr 0:34ee385f4d2d 2463 * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
rajathr 0:34ee385f4d2d 2464 * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
rajathr 0:34ee385f4d2d 2465 * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
rajathr 0:34ee385f4d2d 2466 * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices)
rajathr 0:34ee385f4d2d 2467 * @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices)
rajathr 0:34ee385f4d2d 2468 * @arg RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices)
rajathr 0:34ee385f4d2d 2469 * @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)
rajathr 0:34ee385f4d2d 2470 * @param NewState: new state of the specified peripheral reset.
rajathr 0:34ee385f4d2d 2471 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2472 * @retval None
rajathr 0:34ee385f4d2d 2473 */
rajathr 0:34ee385f4d2d 2474 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2475 {
rajathr 0:34ee385f4d2d 2476 /* Check the parameters */
rajathr 0:34ee385f4d2d 2477 assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
rajathr 0:34ee385f4d2d 2478 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2479 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2480 {
rajathr 0:34ee385f4d2d 2481 RCC->APB2RSTR |= RCC_APB2Periph;
rajathr 0:34ee385f4d2d 2482 }
rajathr 0:34ee385f4d2d 2483 else
rajathr 0:34ee385f4d2d 2484 {
rajathr 0:34ee385f4d2d 2485 RCC->APB2RSTR &= ~RCC_APB2Periph;
rajathr 0:34ee385f4d2d 2486 }
rajathr 0:34ee385f4d2d 2487 }
rajathr 0:34ee385f4d2d 2488
rajathr 0:34ee385f4d2d 2489 /**
rajathr 0:34ee385f4d2d 2490 * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
rajathr 0:34ee385f4d2d 2491 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
rajathr 0:34ee385f4d2d 2492 * power consumption.
rajathr 0:34ee385f4d2d 2493 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
rajathr 0:34ee385f4d2d 2494 * @note By default, all peripheral clocks are enabled during SLEEP mode.
rajathr 0:34ee385f4d2d 2495 * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
rajathr 0:34ee385f4d2d 2496 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2497 * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
rajathr 0:34ee385f4d2d 2498 * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
rajathr 0:34ee385f4d2d 2499 * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
rajathr 0:34ee385f4d2d 2500 * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
rajathr 0:34ee385f4d2d 2501 * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
rajathr 0:34ee385f4d2d 2502 * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
rajathr 0:34ee385f4d2d 2503 * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
rajathr 0:34ee385f4d2d 2504 * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
rajathr 0:34ee385f4d2d 2505 * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
rajathr 0:34ee385f4d2d 2506 * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
rajathr 0:34ee385f4d2d 2507 * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
rajathr 0:34ee385f4d2d 2508 * @arg RCC_AHB1Periph_CRC: CRC clock
rajathr 0:34ee385f4d2d 2509 * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
rajathr 0:34ee385f4d2d 2510 * @arg RCC_AHB1Periph_DMA1: DMA1_MORT clock
rajathr 0:34ee385f4d2d 2511 * @arg RCC_AHB1Periph_DMA2: DMA2_MORT clock
rajathr 0:34ee385f4d2d 2512 * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
rajathr 0:34ee385f4d2d 2513 * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
rajathr 0:34ee385f4d2d 2514 * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
rajathr 0:34ee385f4d2d 2515 * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
rajathr 0:34ee385f4d2d 2516 * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
rajathr 0:34ee385f4d2d 2517 * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
rajathr 0:34ee385f4d2d 2518 * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
rajathr 0:34ee385f4d2d 2519 * @param NewState: new state of the specified peripheral clock.
rajathr 0:34ee385f4d2d 2520 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2521 * @retval None
rajathr 0:34ee385f4d2d 2522 */
rajathr 0:34ee385f4d2d 2523 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2524 {
rajathr 0:34ee385f4d2d 2525 /* Check the parameters */
rajathr 0:34ee385f4d2d 2526 assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
rajathr 0:34ee385f4d2d 2527 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2528 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2529 {
rajathr 0:34ee385f4d2d 2530 RCC->AHB1LPENR |= RCC_AHB1Periph;
rajathr 0:34ee385f4d2d 2531 }
rajathr 0:34ee385f4d2d 2532 else
rajathr 0:34ee385f4d2d 2533 {
rajathr 0:34ee385f4d2d 2534 RCC->AHB1LPENR &= ~RCC_AHB1Periph;
rajathr 0:34ee385f4d2d 2535 }
rajathr 0:34ee385f4d2d 2536 }
rajathr 0:34ee385f4d2d 2537
rajathr 0:34ee385f4d2d 2538 /**
rajathr 0:34ee385f4d2d 2539 * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
rajathr 0:34ee385f4d2d 2540 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
rajathr 0:34ee385f4d2d 2541 * power consumption.
rajathr 0:34ee385f4d2d 2542 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
rajathr 0:34ee385f4d2d 2543 * @note By default, all peripheral clocks are enabled during SLEEP mode.
rajathr 0:34ee385f4d2d 2544 * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
rajathr 0:34ee385f4d2d 2545 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2546 * @arg RCC_AHB2Periph_DCMI: DCMI clock
rajathr 0:34ee385f4d2d 2547 * @arg RCC_AHB2Periph_CRYP: CRYP clock
rajathr 0:34ee385f4d2d 2548 * @arg RCC_AHB2Periph_HASH: HASH clock
rajathr 0:34ee385f4d2d 2549 * @arg RCC_AHB2Periph_RNG: RNG clock
rajathr 0:34ee385f4d2d 2550 * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
rajathr 0:34ee385f4d2d 2551 * @param NewState: new state of the specified peripheral clock.
rajathr 0:34ee385f4d2d 2552 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2553 * @retval None
rajathr 0:34ee385f4d2d 2554 */
rajathr 0:34ee385f4d2d 2555 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2556 {
rajathr 0:34ee385f4d2d 2557 /* Check the parameters */
rajathr 0:34ee385f4d2d 2558 assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
rajathr 0:34ee385f4d2d 2559 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2560 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2561 {
rajathr 0:34ee385f4d2d 2562 RCC->AHB2LPENR |= RCC_AHB2Periph;
rajathr 0:34ee385f4d2d 2563 }
rajathr 0:34ee385f4d2d 2564 else
rajathr 0:34ee385f4d2d 2565 {
rajathr 0:34ee385f4d2d 2566 RCC->AHB2LPENR &= ~RCC_AHB2Periph;
rajathr 0:34ee385f4d2d 2567 }
rajathr 0:34ee385f4d2d 2568 }
rajathr 0:34ee385f4d2d 2569
rajathr 0:34ee385f4d2d 2570 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 2571 /**
rajathr 0:34ee385f4d2d 2572 * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
rajathr 0:34ee385f4d2d 2573 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
rajathr 0:34ee385f4d2d 2574 * power consumption.
rajathr 0:34ee385f4d2d 2575 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
rajathr 0:34ee385f4d2d 2576 * @note By default, all peripheral clocks are enabled during SLEEP mode.
rajathr 0:34ee385f4d2d 2577 * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
rajathr 0:34ee385f4d2d 2578 * This parameter must be:
rajathr 0:34ee385f4d2d 2579 * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices)
rajathr 0:34ee385f4d2d 2580 * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices)
rajathr 0:34ee385f4d2d 2581 * @param NewState: new state of the specified peripheral clock.
rajathr 0:34ee385f4d2d 2582 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2583 * @retval None
rajathr 0:34ee385f4d2d 2584 */
rajathr 0:34ee385f4d2d 2585 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2586 {
rajathr 0:34ee385f4d2d 2587 /* Check the parameters */
rajathr 0:34ee385f4d2d 2588 assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
rajathr 0:34ee385f4d2d 2589 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2590 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2591 {
rajathr 0:34ee385f4d2d 2592 RCC->AHB3LPENR |= RCC_AHB3Periph;
rajathr 0:34ee385f4d2d 2593 }
rajathr 0:34ee385f4d2d 2594 else
rajathr 0:34ee385f4d2d 2595 {
rajathr 0:34ee385f4d2d 2596 RCC->AHB3LPENR &= ~RCC_AHB3Periph;
rajathr 0:34ee385f4d2d 2597 }
rajathr 0:34ee385f4d2d 2598 }
rajathr 0:34ee385f4d2d 2599 #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 2600
rajathr 0:34ee385f4d2d 2601 /**
rajathr 0:34ee385f4d2d 2602 * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
rajathr 0:34ee385f4d2d 2603 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
rajathr 0:34ee385f4d2d 2604 * power consumption.
rajathr 0:34ee385f4d2d 2605 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
rajathr 0:34ee385f4d2d 2606 * @note By default, all peripheral clocks are enabled during SLEEP mode.
rajathr 0:34ee385f4d2d 2607 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
rajathr 0:34ee385f4d2d 2608 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2609 * @arg RCC_APB1Periph_TIM2: TIM2 clock
rajathr 0:34ee385f4d2d 2610 * @arg RCC_APB1Periph_TIM3: TIM3 clock
rajathr 0:34ee385f4d2d 2611 * @arg RCC_APB1Periph_TIM4: TIM4 clock
rajathr 0:34ee385f4d2d 2612 * @arg RCC_APB1Periph_TIM5: TIM5 clock
rajathr 0:34ee385f4d2d 2613 * @arg RCC_APB1Periph_TIM6: TIM6 clock
rajathr 0:34ee385f4d2d 2614 * @arg RCC_APB1Periph_TIM7: TIM7 clock
rajathr 0:34ee385f4d2d 2615 * @arg RCC_APB1Periph_TIM12: TIM12 clock
rajathr 0:34ee385f4d2d 2616 * @arg RCC_APB1Periph_TIM13: TIM13 clock
rajathr 0:34ee385f4d2d 2617 * @arg RCC_APB1Periph_TIM14: TIM14 clock
rajathr 0:34ee385f4d2d 2618 * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices)
rajathr 0:34ee385f4d2d 2619 * @arg RCC_APB1Periph_WWDG: WWDG clock
rajathr 0:34ee385f4d2d 2620 * @arg RCC_APB1Periph_SPI2: SPI2 clock
rajathr 0:34ee385f4d2d 2621 * @arg RCC_APB1Periph_SPI3: SPI3 clock
rajathr 0:34ee385f4d2d 2622 * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
rajathr 0:34ee385f4d2d 2623 * @arg RCC_APB1Periph_USART2: USART2 clock
rajathr 0:34ee385f4d2d 2624 * @arg RCC_APB1Periph_USART3: USART3 clock
rajathr 0:34ee385f4d2d 2625 * @arg RCC_APB1Periph_UART4: UART4 clock
rajathr 0:34ee385f4d2d 2626 * @arg RCC_APB1Periph_UART5: UART5 clock
rajathr 0:34ee385f4d2d 2627 * @arg RCC_APB1Periph_I2C1: I2C1 clock
rajathr 0:34ee385f4d2d 2628 * @arg RCC_APB1Periph_I2C2: I2C2 clock
rajathr 0:34ee385f4d2d 2629 * @arg RCC_APB1Periph_I2C3: I2C3 clock
rajathr 0:34ee385f4d2d 2630 * @arg RCC_APB1Periph_FMPI2C1: FMPI2C1 clock
rajathr 0:34ee385f4d2d 2631 * @arg RCC_APB1Periph_CAN1: CAN1 clock
rajathr 0:34ee385f4d2d 2632 * @arg RCC_APB1Periph_CAN2: CAN2 clock
rajathr 0:34ee385f4d2d 2633 * @arg RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices)
rajathr 0:34ee385f4d2d 2634 * @arg RCC_APB1Periph_PWR: PWR clock
rajathr 0:34ee385f4d2d 2635 * @arg RCC_APB1Periph_DAC: DAC clock
rajathr 0:34ee385f4d2d 2636 * @arg RCC_APB1Periph_UART7: UART7 clock
rajathr 0:34ee385f4d2d 2637 * @arg RCC_APB1Periph_UART8: UART8 clock
rajathr 0:34ee385f4d2d 2638 * @param NewState: new state of the specified peripheral clock.
rajathr 0:34ee385f4d2d 2639 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2640 * @retval None
rajathr 0:34ee385f4d2d 2641 */
rajathr 0:34ee385f4d2d 2642 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2643 {
rajathr 0:34ee385f4d2d 2644 /* Check the parameters */
rajathr 0:34ee385f4d2d 2645 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
rajathr 0:34ee385f4d2d 2646 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2647 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2648 {
rajathr 0:34ee385f4d2d 2649 RCC->APB1LPENR |= RCC_APB1Periph;
rajathr 0:34ee385f4d2d 2650 }
rajathr 0:34ee385f4d2d 2651 else
rajathr 0:34ee385f4d2d 2652 {
rajathr 0:34ee385f4d2d 2653 RCC->APB1LPENR &= ~RCC_APB1Periph;
rajathr 0:34ee385f4d2d 2654 }
rajathr 0:34ee385f4d2d 2655 }
rajathr 0:34ee385f4d2d 2656
rajathr 0:34ee385f4d2d 2657 /**
rajathr 0:34ee385f4d2d 2658 * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
rajathr 0:34ee385f4d2d 2659 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
rajathr 0:34ee385f4d2d 2660 * power consumption.
rajathr 0:34ee385f4d2d 2661 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
rajathr 0:34ee385f4d2d 2662 * @note By default, all peripheral clocks are enabled during SLEEP mode.
rajathr 0:34ee385f4d2d 2663 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
rajathr 0:34ee385f4d2d 2664 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2665 * @arg RCC_APB2Periph_TIM1: TIM1 clock
rajathr 0:34ee385f4d2d 2666 * @arg RCC_APB2Periph_TIM8: TIM8 clock
rajathr 0:34ee385f4d2d 2667 * @arg RCC_APB2Periph_USART1: USART1 clock
rajathr 0:34ee385f4d2d 2668 * @arg RCC_APB2Periph_USART6: USART6 clock
rajathr 0:34ee385f4d2d 2669 * @arg RCC_APB2Periph_ADC1: ADC1 clock
rajathr 0:34ee385f4d2d 2670 * @arg RCC_APB2Periph_ADC2: ADC2 clock
rajathr 0:34ee385f4d2d 2671 * @arg RCC_APB2Periph_ADC3: ADC3 clock
rajathr 0:34ee385f4d2d 2672 * @arg RCC_APB2Periph_SDIO: SDIO clock
rajathr 0:34ee385f4d2d 2673 * @arg RCC_APB2Periph_SPI1: SPI1 clock
rajathr 0:34ee385f4d2d 2674 * @arg RCC_APB2Periph_SPI4: SPI4 clock
rajathr 0:34ee385f4d2d 2675 * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
rajathr 0:34ee385f4d2d 2676 * @arg RCC_APB2Periph_EXTIT: EXTIIT clock
rajathr 0:34ee385f4d2d 2677 * @arg RCC_APB2Periph_TIM9: TIM9 clock
rajathr 0:34ee385f4d2d 2678 * @arg RCC_APB2Periph_TIM10: TIM10 clock
rajathr 0:34ee385f4d2d 2679 * @arg RCC_APB2Periph_TIM11: TIM11 clock
rajathr 0:34ee385f4d2d 2680 * @arg RCC_APB2Periph_SPI5: SPI5 clock
rajathr 0:34ee385f4d2d 2681 * @arg RCC_APB2Periph_SPI6: SPI6 clock
rajathr 0:34ee385f4d2d 2682 * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices)
rajathr 0:34ee385f4d2d 2683 * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
rajathr 0:34ee385f4d2d 2684 * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
rajathr 0:34ee385f4d2d 2685 * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
rajathr 0:34ee385f4d2d 2686 * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices)
rajathr 0:34ee385f4d2d 2687 * @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices)
rajathr 0:34ee385f4d2d 2688 * @arg RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices)
rajathr 0:34ee385f4d2d 2689 * @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)
rajathr 0:34ee385f4d2d 2690 * @param NewState: new state of the specified peripheral clock.
rajathr 0:34ee385f4d2d 2691 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2692 * @retval None
rajathr 0:34ee385f4d2d 2693 */
rajathr 0:34ee385f4d2d 2694 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2695 {
rajathr 0:34ee385f4d2d 2696 /* Check the parameters */
rajathr 0:34ee385f4d2d 2697 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
rajathr 0:34ee385f4d2d 2698 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2699 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2700 {
rajathr 0:34ee385f4d2d 2701 RCC->APB2LPENR |= RCC_APB2Periph;
rajathr 0:34ee385f4d2d 2702 }
rajathr 0:34ee385f4d2d 2703 else
rajathr 0:34ee385f4d2d 2704 {
rajathr 0:34ee385f4d2d 2705 RCC->APB2LPENR &= ~RCC_APB2Periph;
rajathr 0:34ee385f4d2d 2706 }
rajathr 0:34ee385f4d2d 2707 }
rajathr 0:34ee385f4d2d 2708
rajathr 0:34ee385f4d2d 2709 /**
rajathr 0:34ee385f4d2d 2710 * @brief Configures the External Low Speed oscillator mode (LSE mode).
rajathr 0:34ee385f4d2d 2711 * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices.
rajathr 0:34ee385f4d2d 2712 * @param Mode: specifies the LSE mode.
rajathr 0:34ee385f4d2d 2713 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2714 * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode.
rajathr 0:34ee385f4d2d 2715 * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode.
rajathr 0:34ee385f4d2d 2716 * @retval None
rajathr 0:34ee385f4d2d 2717 */
rajathr 0:34ee385f4d2d 2718 void RCC_LSEModeConfig(uint8_t RCC_Mode)
rajathr 0:34ee385f4d2d 2719 {
rajathr 0:34ee385f4d2d 2720 /* Check the parameters */
rajathr 0:34ee385f4d2d 2721 assert_param(IS_RCC_LSE_MODE(RCC_Mode));
rajathr 0:34ee385f4d2d 2722
rajathr 0:34ee385f4d2d 2723 if(RCC_Mode == RCC_LSE_HIGHDRIVE_MODE)
rajathr 0:34ee385f4d2d 2724 {
rajathr 0:34ee385f4d2d 2725 SET_BIT_MORT(RCC->BDCR, RCC_BDCR_LSEMOD_MORT);
rajathr 0:34ee385f4d2d 2726 }
rajathr 0:34ee385f4d2d 2727 else
rajathr 0:34ee385f4d2d 2728 {
rajathr 0:34ee385f4d2d 2729 CLEAR_BIT_MORT(RCC->BDCR, RCC_BDCR_LSEMOD_MORT);
rajathr 0:34ee385f4d2d 2730 }
rajathr 0:34ee385f4d2d 2731 }
rajathr 0:34ee385f4d2d 2732
rajathr 0:34ee385f4d2d 2733 #if defined(STM32F410xx) || defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 2734 /**
rajathr 0:34ee385f4d2d 2735 * @brief Configures the LPTIM1 clock Source.
rajathr 0:34ee385f4d2d 2736 * @note This feature is only available for STM32F410xx devices.
rajathr 0:34ee385f4d2d 2737 * @param RCC_ClockSource: specifies the LPTIM1 clock Source.
rajathr 0:34ee385f4d2d 2738 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2739 * @arg RCC_LPTIM1CLKSOURCE_PCLK: LPTIM1 clock from APB1 selected.
rajathr 0:34ee385f4d2d 2740 * @arg RCC_LPTIM1CLKSOURCE_HSI: LPTIM1 clock from HSI selected.
rajathr 0:34ee385f4d2d 2741 * @arg RCC_LPTIM1CLKSOURCE_LSI: LPTIM1 clock from LSI selected.
rajathr 0:34ee385f4d2d 2742 * @arg RCC_LPTIM1CLKSOURCE_LSE: LPTIM1 clock from LSE selected.
rajathr 0:34ee385f4d2d 2743 * @retval None
rajathr 0:34ee385f4d2d 2744 */
rajathr 0:34ee385f4d2d 2745 void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource)
rajathr 0:34ee385f4d2d 2746 {
rajathr 0:34ee385f4d2d 2747 /* Check the parameters */
rajathr 0:34ee385f4d2d 2748 assert_param(IS_RCC_LPTIM1_CLOCKSOURCE(RCC_ClockSource));
rajathr 0:34ee385f4d2d 2749
rajathr 0:34ee385f4d2d 2750 /* Clear LPTIM1 clock source selection source bits */
rajathr 0:34ee385f4d2d 2751 RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_LPTIM1SEL;
rajathr 0:34ee385f4d2d 2752 /* Set new LPTIM1 clock source */
rajathr 0:34ee385f4d2d 2753 RCC->DCKCFGR2 |= RCC_ClockSource;
rajathr 0:34ee385f4d2d 2754 }
rajathr 0:34ee385f4d2d 2755 #endif /* STM32F410xx || STM32F413_423xx */
rajathr 0:34ee385f4d2d 2756
rajathr 0:34ee385f4d2d 2757 #if defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 2758 /**
rajathr 0:34ee385f4d2d 2759 * @brief Configures the DSI clock Source.
rajathr 0:34ee385f4d2d 2760 * @note This feature is only available for STM32F469_479xx devices.
rajathr 0:34ee385f4d2d 2761 * @param RCC_ClockSource: specifies the DSI clock Source.
rajathr 0:34ee385f4d2d 2762 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2763 * @arg RCC_DSICLKSource_PHY: DSI-PHY used as DSI byte lane clock source (usual case).
rajathr 0:34ee385f4d2d 2764 * @arg RCC_DSICLKSource_PLLR: PLL_R used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode).
rajathr 0:34ee385f4d2d 2765 * @retval None
rajathr 0:34ee385f4d2d 2766 */
rajathr 0:34ee385f4d2d 2767 void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource)
rajathr 0:34ee385f4d2d 2768 {
rajathr 0:34ee385f4d2d 2769 /* Check the parameters */
rajathr 0:34ee385f4d2d 2770 assert_param(IS_RCC_DSI_CLOCKSOURCE(RCC_ClockSource));
rajathr 0:34ee385f4d2d 2771
rajathr 0:34ee385f4d2d 2772 if(RCC_ClockSource == RCC_DSICLKSource_PLLR)
rajathr 0:34ee385f4d2d 2773 {
rajathr 0:34ee385f4d2d 2774 SET_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL);
rajathr 0:34ee385f4d2d 2775 }
rajathr 0:34ee385f4d2d 2776 else
rajathr 0:34ee385f4d2d 2777 {
rajathr 0:34ee385f4d2d 2778 CLEAR_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL);
rajathr 0:34ee385f4d2d 2779 }
rajathr 0:34ee385f4d2d 2780 }
rajathr 0:34ee385f4d2d 2781 #endif /* STM32F469_479xx */
rajathr 0:34ee385f4d2d 2782
rajathr 0:34ee385f4d2d 2783 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 2784 /**
rajathr 0:34ee385f4d2d 2785 * @brief Configures the 48MHz clock Source.
rajathr 0:34ee385f4d2d 2786 * @note This feature is only available for STM32F446xx/STM32F469_479xx devices.
rajathr 0:34ee385f4d2d 2787 * @param RCC_ClockSource: specifies the 48MHz clock Source.
rajathr 0:34ee385f4d2d 2788 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2789 * @arg RCC_48MHZCLKSource_PLL: 48MHz from PLL selected.
rajathr 0:34ee385f4d2d 2790 * @arg RCC_48MHZCLKSource_PLLSAI: 48MHz from PLLSAI selected.
rajathr 0:34ee385f4d2d 2791 * @arg RCC_CK48CLKSOURCE_PLLI2SQ : 48MHz from PLLI2SQ
rajathr 0:34ee385f4d2d 2792 * @retval None
rajathr 0:34ee385f4d2d 2793 */
rajathr 0:34ee385f4d2d 2794 void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource)
rajathr 0:34ee385f4d2d 2795 {
rajathr 0:34ee385f4d2d 2796 /* Check the parameters */
rajathr 0:34ee385f4d2d 2797 assert_param(IS_RCC_48MHZ_CLOCKSOURCE(RCC_ClockSource));
rajathr 0:34ee385f4d2d 2798 #if defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 2799 if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
rajathr 0:34ee385f4d2d 2800 {
rajathr 0:34ee385f4d2d 2801 SET_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
rajathr 0:34ee385f4d2d 2802 }
rajathr 0:34ee385f4d2d 2803 else
rajathr 0:34ee385f4d2d 2804 {
rajathr 0:34ee385f4d2d 2805 CLEAR_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
rajathr 0:34ee385f4d2d 2806 }
rajathr 0:34ee385f4d2d 2807 #elif defined(STM32F446xx)
rajathr 0:34ee385f4d2d 2808 if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
rajathr 0:34ee385f4d2d 2809 {
rajathr 0:34ee385f4d2d 2810 SET_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL_MORT);
rajathr 0:34ee385f4d2d 2811 }
rajathr 0:34ee385f4d2d 2812 else
rajathr 0:34ee385f4d2d 2813 {
rajathr 0:34ee385f4d2d 2814 CLEAR_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL_MORT);
rajathr 0:34ee385f4d2d 2815 }
rajathr 0:34ee385f4d2d 2816 #elif defined(STM32F412xG) || defined(STM32F413_423xx)
rajathr 0:34ee385f4d2d 2817 if(RCC_ClockSource == RCC_CK48CLKSOURCE_PLLI2SQ)
rajathr 0:34ee385f4d2d 2818 {
rajathr 0:34ee385f4d2d 2819 SET_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL_MORT);
rajathr 0:34ee385f4d2d 2820 }
rajathr 0:34ee385f4d2d 2821 else
rajathr 0:34ee385f4d2d 2822 {
rajathr 0:34ee385f4d2d 2823 CLEAR_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL_MORT);
rajathr 0:34ee385f4d2d 2824 }
rajathr 0:34ee385f4d2d 2825 #else
rajathr 0:34ee385f4d2d 2826 #endif /* STM32F469_479xx */
rajathr 0:34ee385f4d2d 2827 }
rajathr 0:34ee385f4d2d 2828
rajathr 0:34ee385f4d2d 2829 /**
rajathr 0:34ee385f4d2d 2830 * @brief Configures the SDIO clock Source.
rajathr 0:34ee385f4d2d 2831 * @note This feature is only available for STM32F469_479xx/STM32F446xx devices.
rajathr 0:34ee385f4d2d 2832 * @param RCC_ClockSource: specifies the SDIO clock Source.
rajathr 0:34ee385f4d2d 2833 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2834 * @arg RCC_SDIOCLKSource_48MHZ: 48MHz clock selected.
rajathr 0:34ee385f4d2d 2835 * @arg RCC_SDIOCLKSource_SYSCLK: system clock selected.
rajathr 0:34ee385f4d2d 2836 * @retval None
rajathr 0:34ee385f4d2d 2837 */
rajathr 0:34ee385f4d2d 2838 void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource)
rajathr 0:34ee385f4d2d 2839 {
rajathr 0:34ee385f4d2d 2840 /* Check the parameters */
rajathr 0:34ee385f4d2d 2841 assert_param(IS_RCC_SDIO_CLOCKSOURCE(RCC_ClockSource));
rajathr 0:34ee385f4d2d 2842 #if defined(STM32F469_479xx)
rajathr 0:34ee385f4d2d 2843 if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
rajathr 0:34ee385f4d2d 2844 {
rajathr 0:34ee385f4d2d 2845 SET_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL);
rajathr 0:34ee385f4d2d 2846 }
rajathr 0:34ee385f4d2d 2847 else
rajathr 0:34ee385f4d2d 2848 {
rajathr 0:34ee385f4d2d 2849 CLEAR_BIT_MORT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL);
rajathr 0:34ee385f4d2d 2850 }
rajathr 0:34ee385f4d2d 2851 #elif defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
rajathr 0:34ee385f4d2d 2852 if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
rajathr 0:34ee385f4d2d 2853 {
rajathr 0:34ee385f4d2d 2854 SET_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL_MORT);
rajathr 0:34ee385f4d2d 2855 }
rajathr 0:34ee385f4d2d 2856 else
rajathr 0:34ee385f4d2d 2857 {
rajathr 0:34ee385f4d2d 2858 CLEAR_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL_MORT);
rajathr 0:34ee385f4d2d 2859 }
rajathr 0:34ee385f4d2d 2860 #else
rajathr 0:34ee385f4d2d 2861 #endif /* STM32F469_479xx */
rajathr 0:34ee385f4d2d 2862 }
rajathr 0:34ee385f4d2d 2863 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
rajathr 0:34ee385f4d2d 2864
rajathr 0:34ee385f4d2d 2865 #if defined(STM32F446xx)
rajathr 0:34ee385f4d2d 2866 /**
rajathr 0:34ee385f4d2d 2867 * @brief Enables or disables the AHB1 clock gating for the specified IPs.
rajathr 0:34ee385f4d2d 2868 * @note This feature is only available for STM32F446xx devices.
rajathr 0:34ee385f4d2d 2869 * @param RCC_AHB1ClockGating: specifies the AHB1 clock gating.
rajathr 0:34ee385f4d2d 2870 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 2871 * @arg RCC_AHB1ClockGating_APB1Bridge: AHB1 to APB1 clock
rajathr 0:34ee385f4d2d 2872 * @arg RCC_AHB1ClockGating_APB2Bridge: AHB1 to APB2 clock
rajathr 0:34ee385f4d2d 2873 * @arg RCC_AHB1ClockGating_CM4DBG: Cortex M4 ETM clock
rajathr 0:34ee385f4d2d 2874 * @arg RCC_AHB1ClockGating_SPARE: Spare clock
rajathr 0:34ee385f4d2d 2875 * @arg RCC_AHB1ClockGating_SRAM: SRAM controller clock
rajathr 0:34ee385f4d2d 2876 * @arg RCC_AHB1ClockGating_FLITF: Flash interface clock
rajathr 0:34ee385f4d2d 2877 * @arg RCC_AHB1ClockGating_RCC: RCC clock
rajathr 0:34ee385f4d2d 2878 * @param NewState: new state of the specified peripheral clock.
rajathr 0:34ee385f4d2d 2879 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2880 * @retval None
rajathr 0:34ee385f4d2d 2881 */
rajathr 0:34ee385f4d2d 2882 void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState)
rajathr 0:34ee385f4d2d 2883 {
rajathr 0:34ee385f4d2d 2884 /* Check the parameters */
rajathr 0:34ee385f4d2d 2885 assert_param(IS_RCC_AHB1_CLOCKGATING(RCC_AHB1ClockGating));
rajathr 0:34ee385f4d2d 2886
rajathr 0:34ee385f4d2d 2887 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2888 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 2889 {
rajathr 0:34ee385f4d2d 2890 RCC->CKGATENR &= ~RCC_AHB1ClockGating;
rajathr 0:34ee385f4d2d 2891 }
rajathr 0:34ee385f4d2d 2892 else
rajathr 0:34ee385f4d2d 2893 {
rajathr 0:34ee385f4d2d 2894 RCC->CKGATENR |= RCC_AHB1ClockGating;
rajathr 0:34ee385f4d2d 2895 }
rajathr 0:34ee385f4d2d 2896 }
rajathr 0:34ee385f4d2d 2897
rajathr 0:34ee385f4d2d 2898 /**
rajathr 0:34ee385f4d2d 2899 * @brief Configures the SPDIFRX clock Source.
rajathr 0:34ee385f4d2d 2900 * @note This feature is only available for STM32F446xx devices.
rajathr 0:34ee385f4d2d 2901 * @param RCC_ClockSource: specifies the SPDIFRX clock Source.
rajathr 0:34ee385f4d2d 2902 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2903 * @arg RCC_SPDIFRXCLKSource_PLLR: SPDIFRX clock from PLL_R selected.
rajathr 0:34ee385f4d2d 2904 * @arg RCC_SPDIFRXCLKSource_PLLI2SP: SPDIFRX clock from PLLI2S_P selected.
rajathr 0:34ee385f4d2d 2905 * @retval None
rajathr 0:34ee385f4d2d 2906 */
rajathr 0:34ee385f4d2d 2907 void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource)
rajathr 0:34ee385f4d2d 2908 {
rajathr 0:34ee385f4d2d 2909 /* Check the parameters */
rajathr 0:34ee385f4d2d 2910 assert_param(IS_RCC_SPDIFRX_CLOCKSOURCE(RCC_ClockSource));
rajathr 0:34ee385f4d2d 2911
rajathr 0:34ee385f4d2d 2912 if(RCC_ClockSource == RCC_SPDIFRXCLKSource_PLLI2SP)
rajathr 0:34ee385f4d2d 2913 {
rajathr 0:34ee385f4d2d 2914 SET_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL_MORT);
rajathr 0:34ee385f4d2d 2915 }
rajathr 0:34ee385f4d2d 2916 else
rajathr 0:34ee385f4d2d 2917 {
rajathr 0:34ee385f4d2d 2918 CLEAR_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL_MORT);
rajathr 0:34ee385f4d2d 2919 }
rajathr 0:34ee385f4d2d 2920 }
rajathr 0:34ee385f4d2d 2921
rajathr 0:34ee385f4d2d 2922 /**
rajathr 0:34ee385f4d2d 2923 * @brief Configures the CEC clock Source.
rajathr 0:34ee385f4d2d 2924 * @note This feature is only available for STM32F446xx devices.
rajathr 0:34ee385f4d2d 2925 * @param RCC_ClockSource: specifies the CEC clock Source.
rajathr 0:34ee385f4d2d 2926 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2927 * @arg RCC_CECCLKSource_HSIDiv488: CEC clock from HSI/488 selected.
rajathr 0:34ee385f4d2d 2928 * @arg RCC_CECCLKSource_LSE: CEC clock from LSE selected.
rajathr 0:34ee385f4d2d 2929 * @retval None
rajathr 0:34ee385f4d2d 2930 */
rajathr 0:34ee385f4d2d 2931 void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource)
rajathr 0:34ee385f4d2d 2932 {
rajathr 0:34ee385f4d2d 2933 /* Check the parameters */
rajathr 0:34ee385f4d2d 2934 assert_param(IS_RCC_CEC_CLOCKSOURCE(RCC_ClockSource));
rajathr 0:34ee385f4d2d 2935
rajathr 0:34ee385f4d2d 2936 if(RCC_ClockSource == RCC_CECCLKSource_LSE)
rajathr 0:34ee385f4d2d 2937 {
rajathr 0:34ee385f4d2d 2938 SET_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL_MORT);
rajathr 0:34ee385f4d2d 2939 }
rajathr 0:34ee385f4d2d 2940 else
rajathr 0:34ee385f4d2d 2941 {
rajathr 0:34ee385f4d2d 2942 CLEAR_BIT_MORT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL_MORT);
rajathr 0:34ee385f4d2d 2943 }
rajathr 0:34ee385f4d2d 2944 }
rajathr 0:34ee385f4d2d 2945 #endif /* STM32F446xx */
rajathr 0:34ee385f4d2d 2946
rajathr 0:34ee385f4d2d 2947 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
rajathr 0:34ee385f4d2d 2948 /**
rajathr 0:34ee385f4d2d 2949 * @brief Configures the FMPI2C1 clock Source.
rajathr 0:34ee385f4d2d 2950 * @note This feature is only available for STM32F446xx devices.
rajathr 0:34ee385f4d2d 2951 * @param RCC_ClockSource: specifies the FMPI2C1 clock Source.
rajathr 0:34ee385f4d2d 2952 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 2953 * @arg RCC_FMPI2C1CLKSource_APB1: FMPI2C1 clock from APB1 selected.
rajathr 0:34ee385f4d2d 2954 * @arg RCC_FMPI2C1CLKSource_SYSCLK: FMPI2C1 clock from Sytem clock selected.
rajathr 0:34ee385f4d2d 2955 * @arg RCC_FMPI2C1CLKSource_HSI: FMPI2C1 clock from HSI selected.
rajathr 0:34ee385f4d2d 2956 * @retval None
rajathr 0:34ee385f4d2d 2957 */
rajathr 0:34ee385f4d2d 2958 void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource)
rajathr 0:34ee385f4d2d 2959 {
rajathr 0:34ee385f4d2d 2960 /* Check the parameters */
rajathr 0:34ee385f4d2d 2961 assert_param(IS_RCC_FMPI2C1_CLOCKSOURCE(RCC_ClockSource));
rajathr 0:34ee385f4d2d 2962
rajathr 0:34ee385f4d2d 2963 /* Clear FMPI2C1 clock source selection source bits */
rajathr 0:34ee385f4d2d 2964 RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_FMPI2C1SEL_MORT;
rajathr 0:34ee385f4d2d 2965 /* Set new FMPI2C1 clock source */
rajathr 0:34ee385f4d2d 2966 RCC->DCKCFGR2 |= RCC_ClockSource;
rajathr 0:34ee385f4d2d 2967 }
rajathr 0:34ee385f4d2d 2968 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
rajathr 0:34ee385f4d2d 2969 /**
rajathr 0:34ee385f4d2d 2970 * @}
rajathr 0:34ee385f4d2d 2971 */
rajathr 0:34ee385f4d2d 2972
rajathr 0:34ee385f4d2d 2973 #if defined(STM32F410xx)
rajathr 0:34ee385f4d2d 2974 /**
rajathr 0:34ee385f4d2d 2975 * @brief Enables or disables the MCO1.
rajathr 0:34ee385f4d2d 2976 * @param NewState: new state of the MCO1.
rajathr 0:34ee385f4d2d 2977 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2978 * @retval None
rajathr 0:34ee385f4d2d 2979 */
rajathr 0:34ee385f4d2d 2980 void RCC_MCO1Cmd(FunctionalState NewState)
rajathr 0:34ee385f4d2d 2981 {
rajathr 0:34ee385f4d2d 2982 /* Check the parameters */
rajathr 0:34ee385f4d2d 2983 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2984
rajathr 0:34ee385f4d2d 2985 *(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = (uint32_t)NewState;
rajathr 0:34ee385f4d2d 2986 }
rajathr 0:34ee385f4d2d 2987
rajathr 0:34ee385f4d2d 2988 /**
rajathr 0:34ee385f4d2d 2989 * @brief Enables or disables the MCO2.
rajathr 0:34ee385f4d2d 2990 * @param NewState: new state of the MCO2.
rajathr 0:34ee385f4d2d 2991 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 2992 * @retval None
rajathr 0:34ee385f4d2d 2993 */
rajathr 0:34ee385f4d2d 2994 void RCC_MCO2Cmd(FunctionalState NewState)
rajathr 0:34ee385f4d2d 2995 {
rajathr 0:34ee385f4d2d 2996 /* Check the parameters */
rajathr 0:34ee385f4d2d 2997 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 2998
rajathr 0:34ee385f4d2d 2999 *(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = (uint32_t)NewState;
rajathr 0:34ee385f4d2d 3000 }
rajathr 0:34ee385f4d2d 3001 #endif /* STM32F410xx */
rajathr 0:34ee385f4d2d 3002
rajathr 0:34ee385f4d2d 3003 /** @defgroup RCC_Group4 Interrupts and flags management functions
rajathr 0:34ee385f4d2d 3004 * @brief Interrupts and flags management functions
rajathr 0:34ee385f4d2d 3005 *
rajathr 0:34ee385f4d2d 3006 @verbatim
rajathr 0:34ee385f4d2d 3007 ===============================================================================
rajathr 0:34ee385f4d2d 3008 ##### Interrupts and flags management functions #####
rajathr 0:34ee385f4d2d 3009 ===============================================================================
rajathr 0:34ee385f4d2d 3010
rajathr 0:34ee385f4d2d 3011 @endverbatim
rajathr 0:34ee385f4d2d 3012 * @{
rajathr 0:34ee385f4d2d 3013 */
rajathr 0:34ee385f4d2d 3014
rajathr 0:34ee385f4d2d 3015 /**
rajathr 0:34ee385f4d2d 3016 * @brief Enables or disables the specified RCC interrupts.
rajathr 0:34ee385f4d2d 3017 * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
rajathr 0:34ee385f4d2d 3018 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 3019 * @arg RCC_IT_LSIRDY: LSI ready interrupt
rajathr 0:34ee385f4d2d 3020 * @arg RCC_IT_LSERDY: LSE ready interrupt
rajathr 0:34ee385f4d2d 3021 * @arg RCC_IT_HSIRDY: HSI ready interrupt
rajathr 0:34ee385f4d2d 3022 * @arg RCC_IT_HSERDY: HSE ready interrupt
rajathr 0:34ee385f4d2d 3023 * @arg RCC_IT_PLLRDY: main PLL ready interrupt
rajathr 0:34ee385f4d2d 3024 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
rajathr 0:34ee385f4d2d 3025 * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
rajathr 0:34ee385f4d2d 3026 * @param NewState: new state of the specified RCC interrupts.
rajathr 0:34ee385f4d2d 3027 * This parameter can be: ENABLE or DISABLE.
rajathr 0:34ee385f4d2d 3028 * @retval None
rajathr 0:34ee385f4d2d 3029 */
rajathr 0:34ee385f4d2d 3030 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
rajathr 0:34ee385f4d2d 3031 {
rajathr 0:34ee385f4d2d 3032 /* Check the parameters */
rajathr 0:34ee385f4d2d 3033 assert_param(IS_RCC_IT(RCC_IT));
rajathr 0:34ee385f4d2d 3034 assert_param(IS_FUNCTIONAL_STATE(NewState));
rajathr 0:34ee385f4d2d 3035 if (NewState != DISABLE)
rajathr 0:34ee385f4d2d 3036 {
rajathr 0:34ee385f4d2d 3037 /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
rajathr 0:34ee385f4d2d 3038 *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
rajathr 0:34ee385f4d2d 3039 }
rajathr 0:34ee385f4d2d 3040 else
rajathr 0:34ee385f4d2d 3041 {
rajathr 0:34ee385f4d2d 3042 /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
rajathr 0:34ee385f4d2d 3043 *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
rajathr 0:34ee385f4d2d 3044 }
rajathr 0:34ee385f4d2d 3045 }
rajathr 0:34ee385f4d2d 3046
rajathr 0:34ee385f4d2d 3047 /**
rajathr 0:34ee385f4d2d 3048 * @brief Checks whether the specified RCC flag is set or not.
rajathr 0:34ee385f4d2d 3049 * @param RCC_FLAG: specifies the flag to check.
rajathr 0:34ee385f4d2d 3050 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3051 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
rajathr 0:34ee385f4d2d 3052 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
rajathr 0:34ee385f4d2d 3053 * @arg RCC_FLAG_PLLRDY: main PLL clock ready
rajathr 0:34ee385f4d2d 3054 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
rajathr 0:34ee385f4d2d 3055 * @arg RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
rajathr 0:34ee385f4d2d 3056 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
rajathr 0:34ee385f4d2d 3057 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
rajathr 0:34ee385f4d2d 3058 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
rajathr 0:34ee385f4d2d 3059 * @arg RCC_FLAG_PINRST: Pin reset
rajathr 0:34ee385f4d2d 3060 * @arg RCC_FLAG_PORRST: POR/PDR reset
rajathr 0:34ee385f4d2d 3061 * @arg RCC_FLAG_SFTRST: Software reset
rajathr 0:34ee385f4d2d 3062 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
rajathr 0:34ee385f4d2d 3063 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
rajathr 0:34ee385f4d2d 3064 * @arg RCC_FLAG_LPWRRST: Low Power reset
rajathr 0:34ee385f4d2d 3065 * @retval The new state of RCC_FLAG (SET or RESET).
rajathr 0:34ee385f4d2d 3066 */
rajathr 0:34ee385f4d2d 3067 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
rajathr 0:34ee385f4d2d 3068 {
rajathr 0:34ee385f4d2d 3069 uint32_t tmp = 0;
rajathr 0:34ee385f4d2d 3070 uint32_t statusreg = 0;
rajathr 0:34ee385f4d2d 3071 FlagStatus bitstatus = RESET;
rajathr 0:34ee385f4d2d 3072
rajathr 0:34ee385f4d2d 3073 /* Check the parameters */
rajathr 0:34ee385f4d2d 3074 assert_param(IS_RCC_FLAG(RCC_FLAG));
rajathr 0:34ee385f4d2d 3075
rajathr 0:34ee385f4d2d 3076 /* Get the RCC register index */
rajathr 0:34ee385f4d2d 3077 tmp = RCC_FLAG >> 5;
rajathr 0:34ee385f4d2d 3078 if (tmp == 1) /* The flag to check is in CR register */
rajathr 0:34ee385f4d2d 3079 {
rajathr 0:34ee385f4d2d 3080 statusreg = RCC->CR;
rajathr 0:34ee385f4d2d 3081 }
rajathr 0:34ee385f4d2d 3082 else if (tmp == 2) /* The flag to check is in BDCR register */
rajathr 0:34ee385f4d2d 3083 {
rajathr 0:34ee385f4d2d 3084 statusreg = RCC->BDCR;
rajathr 0:34ee385f4d2d 3085 }
rajathr 0:34ee385f4d2d 3086 else /* The flag to check is in CSR register */
rajathr 0:34ee385f4d2d 3087 {
rajathr 0:34ee385f4d2d 3088 statusreg = RCC->CSR;
rajathr 0:34ee385f4d2d 3089 }
rajathr 0:34ee385f4d2d 3090
rajathr 0:34ee385f4d2d 3091 /* Get the flag position */
rajathr 0:34ee385f4d2d 3092 tmp = RCC_FLAG & FLAG_MASK;
rajathr 0:34ee385f4d2d 3093 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
rajathr 0:34ee385f4d2d 3094 {
rajathr 0:34ee385f4d2d 3095 bitstatus = SET;
rajathr 0:34ee385f4d2d 3096 }
rajathr 0:34ee385f4d2d 3097 else
rajathr 0:34ee385f4d2d 3098 {
rajathr 0:34ee385f4d2d 3099 bitstatus = RESET;
rajathr 0:34ee385f4d2d 3100 }
rajathr 0:34ee385f4d2d 3101 /* Return the flag status */
rajathr 0:34ee385f4d2d 3102 return bitstatus;
rajathr 0:34ee385f4d2d 3103 }
rajathr 0:34ee385f4d2d 3104
rajathr 0:34ee385f4d2d 3105 /**
rajathr 0:34ee385f4d2d 3106 * @brief Clears the RCC reset flags.
rajathr 0:34ee385f4d2d 3107 * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
rajathr 0:34ee385f4d2d 3108 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
rajathr 0:34ee385f4d2d 3109 * @param None
rajathr 0:34ee385f4d2d 3110 * @retval None
rajathr 0:34ee385f4d2d 3111 */
rajathr 0:34ee385f4d2d 3112 void RCC_ClearFlag(void)
rajathr 0:34ee385f4d2d 3113 {
rajathr 0:34ee385f4d2d 3114 /* Set RMVF bit to clear the reset flags */
rajathr 0:34ee385f4d2d 3115 RCC->CSR |= RCC_CSR_RMVF_MORT;
rajathr 0:34ee385f4d2d 3116 }
rajathr 0:34ee385f4d2d 3117
rajathr 0:34ee385f4d2d 3118 /**
rajathr 0:34ee385f4d2d 3119 * @brief Checks whether the specified RCC interrupt has occurred or not.
rajathr 0:34ee385f4d2d 3120 * @param RCC_IT: specifies the RCC interrupt source to check.
rajathr 0:34ee385f4d2d 3121 * This parameter can be one of the following values:
rajathr 0:34ee385f4d2d 3122 * @arg RCC_IT_LSIRDY: LSI ready interrupt
rajathr 0:34ee385f4d2d 3123 * @arg RCC_IT_LSERDY: LSE ready interrupt
rajathr 0:34ee385f4d2d 3124 * @arg RCC_IT_HSIRDY: HSI ready interrupt
rajathr 0:34ee385f4d2d 3125 * @arg RCC_IT_HSERDY: HSE ready interrupt
rajathr 0:34ee385f4d2d 3126 * @arg RCC_IT_PLLRDY: main PLL ready interrupt
rajathr 0:34ee385f4d2d 3127 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
rajathr 0:34ee385f4d2d 3128 * @arg RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
rajathr 0:34ee385f4d2d 3129 * @arg RCC_IT_CSS: Clock Security System interrupt
rajathr 0:34ee385f4d2d 3130 * @retval The new state of RCC_IT (SET or RESET).
rajathr 0:34ee385f4d2d 3131 */
rajathr 0:34ee385f4d2d 3132 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
rajathr 0:34ee385f4d2d 3133 {
rajathr 0:34ee385f4d2d 3134 ITStatus bitstatus = RESET;
rajathr 0:34ee385f4d2d 3135
rajathr 0:34ee385f4d2d 3136 /* Check the parameters */
rajathr 0:34ee385f4d2d 3137 assert_param(IS_RCC_GET_IT(RCC_IT));
rajathr 0:34ee385f4d2d 3138
rajathr 0:34ee385f4d2d 3139 /* Check the status of the specified RCC interrupt */
rajathr 0:34ee385f4d2d 3140 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
rajathr 0:34ee385f4d2d 3141 {
rajathr 0:34ee385f4d2d 3142 bitstatus = SET;
rajathr 0:34ee385f4d2d 3143 }
rajathr 0:34ee385f4d2d 3144 else
rajathr 0:34ee385f4d2d 3145 {
rajathr 0:34ee385f4d2d 3146 bitstatus = RESET;
rajathr 0:34ee385f4d2d 3147 }
rajathr 0:34ee385f4d2d 3148 /* Return the RCC_IT status */
rajathr 0:34ee385f4d2d 3149 return bitstatus;
rajathr 0:34ee385f4d2d 3150 }
rajathr 0:34ee385f4d2d 3151
rajathr 0:34ee385f4d2d 3152 /**
rajathr 0:34ee385f4d2d 3153 * @brief Clears the RCC's interrupt pending bits.
rajathr 0:34ee385f4d2d 3154 * @param RCC_IT: specifies the interrupt pending bit to clear.
rajathr 0:34ee385f4d2d 3155 * This parameter can be any combination of the following values:
rajathr 0:34ee385f4d2d 3156 * @arg RCC_IT_LSIRDY: LSI ready interrupt
rajathr 0:34ee385f4d2d 3157 * @arg RCC_IT_LSERDY: LSE ready interrupt
rajathr 0:34ee385f4d2d 3158 * @arg RCC_IT_HSIRDY: HSI ready interrupt
rajathr 0:34ee385f4d2d 3159 * @arg RCC_IT_HSERDY: HSE ready interrupt
rajathr 0:34ee385f4d2d 3160 * @arg RCC_IT_PLLRDY: main PLL ready interrupt
rajathr 0:34ee385f4d2d 3161 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
rajathr 0:34ee385f4d2d 3162 * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
rajathr 0:34ee385f4d2d 3163 * @arg RCC_IT_CSS: Clock Security System interrupt
rajathr 0:34ee385f4d2d 3164 * @retval None
rajathr 0:34ee385f4d2d 3165 */
rajathr 0:34ee385f4d2d 3166 void RCC_ClearITPendingBit(uint8_t RCC_IT)
rajathr 0:34ee385f4d2d 3167 {
rajathr 0:34ee385f4d2d 3168 /* Check the parameters */
rajathr 0:34ee385f4d2d 3169 assert_param(IS_RCC_CLEAR_IT(RCC_IT));
rajathr 0:34ee385f4d2d 3170
rajathr 0:34ee385f4d2d 3171 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
rajathr 0:34ee385f4d2d 3172 pending bits */
rajathr 0:34ee385f4d2d 3173 *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
rajathr 0:34ee385f4d2d 3174 }
rajathr 0:34ee385f4d2d 3175
rajathr 0:34ee385f4d2d 3176 /**
rajathr 0:34ee385f4d2d 3177 * @}
rajathr 0:34ee385f4d2d 3178 */
rajathr 0:34ee385f4d2d 3179
rajathr 0:34ee385f4d2d 3180 /**
rajathr 0:34ee385f4d2d 3181 * @}
rajathr 0:34ee385f4d2d 3182 */
rajathr 0:34ee385f4d2d 3183
rajathr 0:34ee385f4d2d 3184 /**
rajathr 0:34ee385f4d2d 3185 * @}
rajathr 0:34ee385f4d2d 3186 */
rajathr 0:34ee385f4d2d 3187
rajathr 0:34ee385f4d2d 3188 /**
rajathr 0:34ee385f4d2d 3189 * @}
rajathr 0:34ee385f4d2d 3190 */
rajathr 0:34ee385f4d2d 3191
rajathr 0:34ee385f4d2d 3192 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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