Rajath Ravi
/
ravi_blinkycode
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stm32f4xx_adc_mort.h@0:34ee385f4d2d, 2021-10-23 (annotated)
- Committer:
- rajathr
- Date:
- Sat Oct 23 05:49:09 2021 +0000
- Revision:
- 0:34ee385f4d2d
At 23rd Oct 21 - All Code
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| rajathr | 0:34ee385f4d2d | 1 | /** |
| rajathr | 0:34ee385f4d2d | 2 | ****************************************************************************** |
| rajathr | 0:34ee385f4d2d | 3 | * @file stm32f4xx_adc_mort.h |
| rajathr | 0:34ee385f4d2d | 4 | * @author MCD Application Team |
| rajathr | 0:34ee385f4d2d | 5 | * @version V1.8.0 |
| rajathr | 0:34ee385f4d2d | 6 | * @date 04-November-2016 |
| rajathr | 0:34ee385f4d2d | 7 | * @brief This file contains all the functions prototypes for the ADC firmware |
| rajathr | 0:34ee385f4d2d | 8 | * library. |
| rajathr | 0:34ee385f4d2d | 9 | ****************************************************************************** |
| rajathr | 0:34ee385f4d2d | 10 | * @attention |
| rajathr | 0:34ee385f4d2d | 11 | * |
| rajathr | 0:34ee385f4d2d | 12 | * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> |
| rajathr | 0:34ee385f4d2d | 13 | * |
| rajathr | 0:34ee385f4d2d | 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); |
| rajathr | 0:34ee385f4d2d | 15 | * You may not use this file except in compliance with the License. |
| rajathr | 0:34ee385f4d2d | 16 | * You may obtain a copy of the License at: |
| rajathr | 0:34ee385f4d2d | 17 | * |
| rajathr | 0:34ee385f4d2d | 18 | * http://www.st.com/software_license_agreement_liberty_v2 |
| rajathr | 0:34ee385f4d2d | 19 | * |
| rajathr | 0:34ee385f4d2d | 20 | * Unless required by applicable law or agreed to in writing, software |
| rajathr | 0:34ee385f4d2d | 21 | * distributed under the License is distributed on an "AS IS" BASIS, |
| rajathr | 0:34ee385f4d2d | 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| rajathr | 0:34ee385f4d2d | 23 | * See the License for the specific language governing permissions and |
| rajathr | 0:34ee385f4d2d | 24 | * limitations under the License. |
| rajathr | 0:34ee385f4d2d | 25 | * |
| rajathr | 0:34ee385f4d2d | 26 | ****************************************************************************** |
| rajathr | 0:34ee385f4d2d | 27 | */ |
| rajathr | 0:34ee385f4d2d | 28 | |
| rajathr | 0:34ee385f4d2d | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| rajathr | 0:34ee385f4d2d | 30 | #ifndef __STM32F4xx_ADC_H_MORT |
| rajathr | 0:34ee385f4d2d | 31 | #define __STM32F4xx_ADC_H_MORT |
| rajathr | 0:34ee385f4d2d | 32 | |
| rajathr | 0:34ee385f4d2d | 33 | #ifdef __cplusplus |
| rajathr | 0:34ee385f4d2d | 34 | extern "C" { |
| rajathr | 0:34ee385f4d2d | 35 | #endif |
| rajathr | 0:34ee385f4d2d | 36 | |
| rajathr | 0:34ee385f4d2d | 37 | /* Includes ------------------------------------------------------------------*/ |
| rajathr | 0:34ee385f4d2d | 38 | #include "stm32f4xx_mort2.h" |
| rajathr | 0:34ee385f4d2d | 39 | |
| rajathr | 0:34ee385f4d2d | 40 | /** @addtogroup STM32F4xx_StdPeriph_Driver |
| rajathr | 0:34ee385f4d2d | 41 | * @{ |
| rajathr | 0:34ee385f4d2d | 42 | */ |
| rajathr | 0:34ee385f4d2d | 43 | |
| rajathr | 0:34ee385f4d2d | 44 | /** @addtogroup ADC |
| rajathr | 0:34ee385f4d2d | 45 | * @{ |
| rajathr | 0:34ee385f4d2d | 46 | */ |
| rajathr | 0:34ee385f4d2d | 47 | |
| rajathr | 0:34ee385f4d2d | 48 | /* Exported types ------------------------------------------------------------*/ |
| rajathr | 0:34ee385f4d2d | 49 | |
| rajathr | 0:34ee385f4d2d | 50 | /** |
| rajathr | 0:34ee385f4d2d | 51 | * @brief ADC Init structure definition |
| rajathr | 0:34ee385f4d2d | 52 | */ |
| rajathr | 0:34ee385f4d2d | 53 | typedef struct |
| rajathr | 0:34ee385f4d2d | 54 | { |
| rajathr | 0:34ee385f4d2d | 55 | uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. |
| rajathr | 0:34ee385f4d2d | 56 | This parameter can be a value of @ref ADC_resolution */ |
| rajathr | 0:34ee385f4d2d | 57 | FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion |
| rajathr | 0:34ee385f4d2d | 58 | is performed in Scan (multichannels) |
| rajathr | 0:34ee385f4d2d | 59 | or Single (one channel) mode. |
| rajathr | 0:34ee385f4d2d | 60 | This parameter can be set to ENABLE or DISABLE */ |
| rajathr | 0:34ee385f4d2d | 61 | FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion |
| rajathr | 0:34ee385f4d2d | 62 | is performed in Continuous or Single mode. |
| rajathr | 0:34ee385f4d2d | 63 | This parameter can be set to ENABLE or DISABLE. */ |
| rajathr | 0:34ee385f4d2d | 64 | uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and |
| rajathr | 0:34ee385f4d2d | 65 | enable the trigger of a regular group. |
| rajathr | 0:34ee385f4d2d | 66 | This parameter can be a value of |
| rajathr | 0:34ee385f4d2d | 67 | @ref ADC_external_trigger_edge_for_regular_channels_conversion */ |
| rajathr | 0:34ee385f4d2d | 68 | uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger |
| rajathr | 0:34ee385f4d2d | 69 | the start of conversion of a regular group. |
| rajathr | 0:34ee385f4d2d | 70 | This parameter can be a value of |
| rajathr | 0:34ee385f4d2d | 71 | @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */ |
| rajathr | 0:34ee385f4d2d | 72 | uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment |
| rajathr | 0:34ee385f4d2d | 73 | is left or right. This parameter can be |
| rajathr | 0:34ee385f4d2d | 74 | a value of @ref ADC_data_align */ |
| rajathr | 0:34ee385f4d2d | 75 | uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions |
| rajathr | 0:34ee385f4d2d | 76 | that will be done using the sequencer for |
| rajathr | 0:34ee385f4d2d | 77 | regular channel group. |
| rajathr | 0:34ee385f4d2d | 78 | This parameter must range from 1 to 16. */ |
| rajathr | 0:34ee385f4d2d | 79 | }ADC_InitTypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 80 | |
| rajathr | 0:34ee385f4d2d | 81 | /** |
| rajathr | 0:34ee385f4d2d | 82 | * @brief ADC Common Init structure definition |
| rajathr | 0:34ee385f4d2d | 83 | */ |
| rajathr | 0:34ee385f4d2d | 84 | typedef struct |
| rajathr | 0:34ee385f4d2d | 85 | { |
| rajathr | 0:34ee385f4d2d | 86 | uint32_t ADC_Mode; /*!< Configures the ADC to operate in |
| rajathr | 0:34ee385f4d2d | 87 | independent or multi mode. |
| rajathr | 0:34ee385f4d2d | 88 | This parameter can be a value of @ref ADC_Common_mode */ |
| rajathr | 0:34ee385f4d2d | 89 | uint32_t ADC_Prescaler; /*!< Select the frequency of the clock |
| rajathr | 0:34ee385f4d2d | 90 | to the ADC. The clock is common for all the ADCs. |
| rajathr | 0:34ee385f4d2d | 91 | This parameter can be a value of @ref ADC_Prescaler */ |
| rajathr | 0:34ee385f4d2d | 92 | uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access |
| rajathr | 0:34ee385f4d2d | 93 | mode for multi ADC mode. |
| rajathr | 0:34ee385f4d2d | 94 | This parameter can be a value of |
| rajathr | 0:34ee385f4d2d | 95 | @ref ADC_Direct_memory_access_mode_for_multi_mode */ |
| rajathr | 0:34ee385f4d2d | 96 | uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. |
| rajathr | 0:34ee385f4d2d | 97 | This parameter can be a value of |
| rajathr | 0:34ee385f4d2d | 98 | @ref ADC_delay_between_2_sampling_phases */ |
| rajathr | 0:34ee385f4d2d | 99 | |
| rajathr | 0:34ee385f4d2d | 100 | }ADC_CommonInitTypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 101 | |
| rajathr | 0:34ee385f4d2d | 102 | |
| rajathr | 0:34ee385f4d2d | 103 | /* Exported constants --------------------------------------------------------*/ |
| rajathr | 0:34ee385f4d2d | 104 | |
| rajathr | 0:34ee385f4d2d | 105 | /** @defgroup ADC_Exported_Constants |
| rajathr | 0:34ee385f4d2d | 106 | * @{ |
| rajathr | 0:34ee385f4d2d | 107 | */ |
| rajathr | 0:34ee385f4d2d | 108 | #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ |
| rajathr | 0:34ee385f4d2d | 109 | ((PERIPH) == ADC2) || \ |
| rajathr | 0:34ee385f4d2d | 110 | ((PERIPH) == ADC3)) |
| rajathr | 0:34ee385f4d2d | 111 | |
| rajathr | 0:34ee385f4d2d | 112 | /** @defgroup ADC_Common_mode |
| rajathr | 0:34ee385f4d2d | 113 | * @{ |
| rajathr | 0:34ee385f4d2d | 114 | */ |
| rajathr | 0:34ee385f4d2d | 115 | #define ADC_Mode_Independent ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 116 | #define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 117 | #define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 118 | #define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) |
| rajathr | 0:34ee385f4d2d | 119 | #define ADC_DualMode_RegSimult ((uint32_t)0x00000006) |
| rajathr | 0:34ee385f4d2d | 120 | #define ADC_DualMode_Interl ((uint32_t)0x00000007) |
| rajathr | 0:34ee385f4d2d | 121 | #define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) |
| rajathr | 0:34ee385f4d2d | 122 | #define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) |
| rajathr | 0:34ee385f4d2d | 123 | #define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) |
| rajathr | 0:34ee385f4d2d | 124 | #define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) |
| rajathr | 0:34ee385f4d2d | 125 | #define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) |
| rajathr | 0:34ee385f4d2d | 126 | #define ADC_TripleMode_Interl ((uint32_t)0x00000017) |
| rajathr | 0:34ee385f4d2d | 127 | #define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) |
| rajathr | 0:34ee385f4d2d | 128 | #define IS_ADC_MODE_MORT(MODE) (((MODE) == ADC_Mode_Independent) || \ |
| rajathr | 0:34ee385f4d2d | 129 | ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ |
| rajathr | 0:34ee385f4d2d | 130 | ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ |
| rajathr | 0:34ee385f4d2d | 131 | ((MODE) == ADC_DualMode_InjecSimult) || \ |
| rajathr | 0:34ee385f4d2d | 132 | ((MODE) == ADC_DualMode_RegSimult) || \ |
| rajathr | 0:34ee385f4d2d | 133 | ((MODE) == ADC_DualMode_Interl) || \ |
| rajathr | 0:34ee385f4d2d | 134 | ((MODE) == ADC_DualMode_AlterTrig) || \ |
| rajathr | 0:34ee385f4d2d | 135 | ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ |
| rajathr | 0:34ee385f4d2d | 136 | ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ |
| rajathr | 0:34ee385f4d2d | 137 | ((MODE) == ADC_TripleMode_InjecSimult) || \ |
| rajathr | 0:34ee385f4d2d | 138 | ((MODE) == ADC_TripleMode_RegSimult) || \ |
| rajathr | 0:34ee385f4d2d | 139 | ((MODE) == ADC_TripleMode_Interl) || \ |
| rajathr | 0:34ee385f4d2d | 140 | ((MODE) == ADC_TripleMode_AlterTrig)) |
| rajathr | 0:34ee385f4d2d | 141 | /** |
| rajathr | 0:34ee385f4d2d | 142 | * @} |
| rajathr | 0:34ee385f4d2d | 143 | */ |
| rajathr | 0:34ee385f4d2d | 144 | |
| rajathr | 0:34ee385f4d2d | 145 | |
| rajathr | 0:34ee385f4d2d | 146 | /** @defgroup ADC_Prescaler |
| rajathr | 0:34ee385f4d2d | 147 | * @{ |
| rajathr | 0:34ee385f4d2d | 148 | */ |
| rajathr | 0:34ee385f4d2d | 149 | #define ADC_Prescaler_Div2 ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 150 | #define ADC_Prescaler_Div4 ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 151 | #define ADC_Prescaler_Div6 ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 152 | #define ADC_Prescaler_Div8 ((uint32_t)0x00030000) |
| rajathr | 0:34ee385f4d2d | 153 | #define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \ |
| rajathr | 0:34ee385f4d2d | 154 | ((PRESCALER) == ADC_Prescaler_Div4) || \ |
| rajathr | 0:34ee385f4d2d | 155 | ((PRESCALER) == ADC_Prescaler_Div6) || \ |
| rajathr | 0:34ee385f4d2d | 156 | ((PRESCALER) == ADC_Prescaler_Div8)) |
| rajathr | 0:34ee385f4d2d | 157 | /** |
| rajathr | 0:34ee385f4d2d | 158 | * @} |
| rajathr | 0:34ee385f4d2d | 159 | */ |
| rajathr | 0:34ee385f4d2d | 160 | |
| rajathr | 0:34ee385f4d2d | 161 | |
| rajathr | 0:34ee385f4d2d | 162 | /** @defgroup ADC_Direct_memory_access_mode_for_multi_mode |
| rajathr | 0:34ee385f4d2d | 163 | * @{ |
| rajathr | 0:34ee385f4d2d | 164 | */ |
| rajathr | 0:34ee385f4d2d | 165 | #define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ |
| rajathr | 0:34ee385f4d2d | 166 | #define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ |
| rajathr | 0:34ee385f4d2d | 167 | #define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ |
| rajathr | 0:34ee385f4d2d | 168 | #define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ |
| rajathr | 0:34ee385f4d2d | 169 | #define IS_ADC_DMA_ACCESS_MODE_MORT(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ |
| rajathr | 0:34ee385f4d2d | 170 | ((MODE) == ADC_DMAAccessMode_1) || \ |
| rajathr | 0:34ee385f4d2d | 171 | ((MODE) == ADC_DMAAccessMode_2) || \ |
| rajathr | 0:34ee385f4d2d | 172 | ((MODE) == ADC_DMAAccessMode_3)) |
| rajathr | 0:34ee385f4d2d | 173 | |
| rajathr | 0:34ee385f4d2d | 174 | /** |
| rajathr | 0:34ee385f4d2d | 175 | * @} |
| rajathr | 0:34ee385f4d2d | 176 | */ |
| rajathr | 0:34ee385f4d2d | 177 | |
| rajathr | 0:34ee385f4d2d | 178 | |
| rajathr | 0:34ee385f4d2d | 179 | /** @defgroup ADC_delay_between_2_sampling_phases |
| rajathr | 0:34ee385f4d2d | 180 | * @{ |
| rajathr | 0:34ee385f4d2d | 181 | */ |
| rajathr | 0:34ee385f4d2d | 182 | #define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 183 | #define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 184 | #define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 185 | #define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) |
| rajathr | 0:34ee385f4d2d | 186 | #define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 187 | #define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) |
| rajathr | 0:34ee385f4d2d | 188 | #define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) |
| rajathr | 0:34ee385f4d2d | 189 | #define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) |
| rajathr | 0:34ee385f4d2d | 190 | #define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 191 | #define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) |
| rajathr | 0:34ee385f4d2d | 192 | #define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) |
| rajathr | 0:34ee385f4d2d | 193 | #define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) |
| rajathr | 0:34ee385f4d2d | 194 | #define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) |
| rajathr | 0:34ee385f4d2d | 195 | #define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) |
| rajathr | 0:34ee385f4d2d | 196 | #define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) |
| rajathr | 0:34ee385f4d2d | 197 | #define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) |
| rajathr | 0:34ee385f4d2d | 198 | #define IS_ADC_SAMPLING_DELAY_MORT(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 199 | ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 200 | ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 201 | ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 202 | ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 203 | ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 204 | ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 205 | ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 206 | ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 207 | ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 208 | ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 209 | ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 210 | ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 211 | ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 212 | ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 213 | ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) |
| rajathr | 0:34ee385f4d2d | 214 | |
| rajathr | 0:34ee385f4d2d | 215 | /** |
| rajathr | 0:34ee385f4d2d | 216 | * @} |
| rajathr | 0:34ee385f4d2d | 217 | */ |
| rajathr | 0:34ee385f4d2d | 218 | |
| rajathr | 0:34ee385f4d2d | 219 | |
| rajathr | 0:34ee385f4d2d | 220 | /** @defgroup ADC_resolution |
| rajathr | 0:34ee385f4d2d | 221 | * @{ |
| rajathr | 0:34ee385f4d2d | 222 | */ |
| rajathr | 0:34ee385f4d2d | 223 | #define ADC_Resolution_12b ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 224 | #define ADC_Resolution_10b ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 225 | #define ADC_Resolution_8b ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 226 | #define ADC_Resolution_6b ((uint32_t)0x03000000) |
| rajathr | 0:34ee385f4d2d | 227 | #define IS_ADC_RESOLUTION_MORT(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ |
| rajathr | 0:34ee385f4d2d | 228 | ((RESOLUTION) == ADC_Resolution_10b) || \ |
| rajathr | 0:34ee385f4d2d | 229 | ((RESOLUTION) == ADC_Resolution_8b) || \ |
| rajathr | 0:34ee385f4d2d | 230 | ((RESOLUTION) == ADC_Resolution_6b)) |
| rajathr | 0:34ee385f4d2d | 231 | |
| rajathr | 0:34ee385f4d2d | 232 | /** |
| rajathr | 0:34ee385f4d2d | 233 | * @} |
| rajathr | 0:34ee385f4d2d | 234 | */ |
| rajathr | 0:34ee385f4d2d | 235 | |
| rajathr | 0:34ee385f4d2d | 236 | |
| rajathr | 0:34ee385f4d2d | 237 | /** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion |
| rajathr | 0:34ee385f4d2d | 238 | * @{ |
| rajathr | 0:34ee385f4d2d | 239 | */ |
| rajathr | 0:34ee385f4d2d | 240 | #define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 241 | #define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 242 | #define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 243 | #define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) |
| rajathr | 0:34ee385f4d2d | 244 | #define IS_ADC_EXT_TRIG_EDGE_MORT(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ |
| rajathr | 0:34ee385f4d2d | 245 | ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ |
| rajathr | 0:34ee385f4d2d | 246 | ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ |
| rajathr | 0:34ee385f4d2d | 247 | ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) |
| rajathr | 0:34ee385f4d2d | 248 | /** |
| rajathr | 0:34ee385f4d2d | 249 | * @} |
| rajathr | 0:34ee385f4d2d | 250 | */ |
| rajathr | 0:34ee385f4d2d | 251 | |
| rajathr | 0:34ee385f4d2d | 252 | |
| rajathr | 0:34ee385f4d2d | 253 | /** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion |
| rajathr | 0:34ee385f4d2d | 254 | * @{ |
| rajathr | 0:34ee385f4d2d | 255 | */ |
| rajathr | 0:34ee385f4d2d | 256 | #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 257 | #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 258 | #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 259 | #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) |
| rajathr | 0:34ee385f4d2d | 260 | #define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 261 | #define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) |
| rajathr | 0:34ee385f4d2d | 262 | #define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) |
| rajathr | 0:34ee385f4d2d | 263 | #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) |
| rajathr | 0:34ee385f4d2d | 264 | #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 265 | #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) |
| rajathr | 0:34ee385f4d2d | 266 | #define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) |
| rajathr | 0:34ee385f4d2d | 267 | #define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) |
| rajathr | 0:34ee385f4d2d | 268 | #define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) |
| rajathr | 0:34ee385f4d2d | 269 | #define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) |
| rajathr | 0:34ee385f4d2d | 270 | #define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) |
| rajathr | 0:34ee385f4d2d | 271 | #define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) |
| rajathr | 0:34ee385f4d2d | 272 | #define IS_ADC_EXT_TRIG_MORT(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ |
| rajathr | 0:34ee385f4d2d | 273 | ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ |
| rajathr | 0:34ee385f4d2d | 274 | ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ |
| rajathr | 0:34ee385f4d2d | 275 | ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ |
| rajathr | 0:34ee385f4d2d | 276 | ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ |
| rajathr | 0:34ee385f4d2d | 277 | ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ |
| rajathr | 0:34ee385f4d2d | 278 | ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ |
| rajathr | 0:34ee385f4d2d | 279 | ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ |
| rajathr | 0:34ee385f4d2d | 280 | ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ |
| rajathr | 0:34ee385f4d2d | 281 | ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ |
| rajathr | 0:34ee385f4d2d | 282 | ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ |
| rajathr | 0:34ee385f4d2d | 283 | ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ |
| rajathr | 0:34ee385f4d2d | 284 | ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ |
| rajathr | 0:34ee385f4d2d | 285 | ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ |
| rajathr | 0:34ee385f4d2d | 286 | ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ |
| rajathr | 0:34ee385f4d2d | 287 | ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) |
| rajathr | 0:34ee385f4d2d | 288 | /** |
| rajathr | 0:34ee385f4d2d | 289 | * @} |
| rajathr | 0:34ee385f4d2d | 290 | */ |
| rajathr | 0:34ee385f4d2d | 291 | |
| rajathr | 0:34ee385f4d2d | 292 | |
| rajathr | 0:34ee385f4d2d | 293 | /** @defgroup ADC_data_align |
| rajathr | 0:34ee385f4d2d | 294 | * @{ |
| rajathr | 0:34ee385f4d2d | 295 | */ |
| rajathr | 0:34ee385f4d2d | 296 | #define ADC_DataAlign_Right ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 297 | #define ADC_DataAlign_Left ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 298 | #define IS_ADC_DATA_ALIGN_MORT(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ |
| rajathr | 0:34ee385f4d2d | 299 | ((ALIGN) == ADC_DataAlign_Left)) |
| rajathr | 0:34ee385f4d2d | 300 | /** |
| rajathr | 0:34ee385f4d2d | 301 | * @} |
| rajathr | 0:34ee385f4d2d | 302 | */ |
| rajathr | 0:34ee385f4d2d | 303 | |
| rajathr | 0:34ee385f4d2d | 304 | |
| rajathr | 0:34ee385f4d2d | 305 | /** @defgroup ADC_channels |
| rajathr | 0:34ee385f4d2d | 306 | * @{ |
| rajathr | 0:34ee385f4d2d | 307 | */ |
| rajathr | 0:34ee385f4d2d | 308 | #define ADC_Channel_0 ((uint8_t)0x00) |
| rajathr | 0:34ee385f4d2d | 309 | #define ADC_Channel_1 ((uint8_t)0x01) |
| rajathr | 0:34ee385f4d2d | 310 | #define ADC_Channel_2 ((uint8_t)0x02) |
| rajathr | 0:34ee385f4d2d | 311 | #define ADC_Channel_3 ((uint8_t)0x03) |
| rajathr | 0:34ee385f4d2d | 312 | #define ADC_Channel_4 ((uint8_t)0x04) |
| rajathr | 0:34ee385f4d2d | 313 | #define ADC_Channel_5 ((uint8_t)0x05) |
| rajathr | 0:34ee385f4d2d | 314 | #define ADC_Channel_6 ((uint8_t)0x06) |
| rajathr | 0:34ee385f4d2d | 315 | #define ADC_Channel_7 ((uint8_t)0x07) |
| rajathr | 0:34ee385f4d2d | 316 | #define ADC_Channel_8 ((uint8_t)0x08) |
| rajathr | 0:34ee385f4d2d | 317 | #define ADC_Channel_9 ((uint8_t)0x09) |
| rajathr | 0:34ee385f4d2d | 318 | #define ADC_Channel_10 ((uint8_t)0x0A) |
| rajathr | 0:34ee385f4d2d | 319 | #define ADC_Channel_11 ((uint8_t)0x0B) |
| rajathr | 0:34ee385f4d2d | 320 | #define ADC_Channel_12 ((uint8_t)0x0C) |
| rajathr | 0:34ee385f4d2d | 321 | #define ADC_Channel_13 ((uint8_t)0x0D) |
| rajathr | 0:34ee385f4d2d | 322 | #define ADC_Channel_14 ((uint8_t)0x0E) |
| rajathr | 0:34ee385f4d2d | 323 | #define ADC_Channel_15 ((uint8_t)0x0F) |
| rajathr | 0:34ee385f4d2d | 324 | #define ADC_Channel_16 ((uint8_t)0x10) |
| rajathr | 0:34ee385f4d2d | 325 | #define ADC_Channel_17 ((uint8_t)0x11) |
| rajathr | 0:34ee385f4d2d | 326 | #define ADC_Channel_18 ((uint8_t)0x12) |
| rajathr | 0:34ee385f4d2d | 327 | |
| rajathr | 0:34ee385f4d2d | 328 | #if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 329 | #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) |
| rajathr | 0:34ee385f4d2d | 330 | #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 331 | |
| rajathr | 0:34ee385f4d2d | 332 | #if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE) |
| rajathr | 0:34ee385f4d2d | 333 | #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18) |
| rajathr | 0:34ee385f4d2d | 334 | #endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE */ |
| rajathr | 0:34ee385f4d2d | 335 | |
| rajathr | 0:34ee385f4d2d | 336 | #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) |
| rajathr | 0:34ee385f4d2d | 337 | #define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) |
| rajathr | 0:34ee385f4d2d | 338 | |
| rajathr | 0:34ee385f4d2d | 339 | #define IS_ADC_CHANNEL_MORT(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \ |
| rajathr | 0:34ee385f4d2d | 340 | ((CHANNEL) == ADC_Channel_1) || \ |
| rajathr | 0:34ee385f4d2d | 341 | ((CHANNEL) == ADC_Channel_2) || \ |
| rajathr | 0:34ee385f4d2d | 342 | ((CHANNEL) == ADC_Channel_3) || \ |
| rajathr | 0:34ee385f4d2d | 343 | ((CHANNEL) == ADC_Channel_4) || \ |
| rajathr | 0:34ee385f4d2d | 344 | ((CHANNEL) == ADC_Channel_5) || \ |
| rajathr | 0:34ee385f4d2d | 345 | ((CHANNEL) == ADC_Channel_6) || \ |
| rajathr | 0:34ee385f4d2d | 346 | ((CHANNEL) == ADC_Channel_7) || \ |
| rajathr | 0:34ee385f4d2d | 347 | ((CHANNEL) == ADC_Channel_8) || \ |
| rajathr | 0:34ee385f4d2d | 348 | ((CHANNEL) == ADC_Channel_9) || \ |
| rajathr | 0:34ee385f4d2d | 349 | ((CHANNEL) == ADC_Channel_10) || \ |
| rajathr | 0:34ee385f4d2d | 350 | ((CHANNEL) == ADC_Channel_11) || \ |
| rajathr | 0:34ee385f4d2d | 351 | ((CHANNEL) == ADC_Channel_12) || \ |
| rajathr | 0:34ee385f4d2d | 352 | ((CHANNEL) == ADC_Channel_13) || \ |
| rajathr | 0:34ee385f4d2d | 353 | ((CHANNEL) == ADC_Channel_14) || \ |
| rajathr | 0:34ee385f4d2d | 354 | ((CHANNEL) == ADC_Channel_15) || \ |
| rajathr | 0:34ee385f4d2d | 355 | ((CHANNEL) == ADC_Channel_16) || \ |
| rajathr | 0:34ee385f4d2d | 356 | ((CHANNEL) == ADC_Channel_17) || \ |
| rajathr | 0:34ee385f4d2d | 357 | ((CHANNEL) == ADC_Channel_18)) |
| rajathr | 0:34ee385f4d2d | 358 | /** |
| rajathr | 0:34ee385f4d2d | 359 | * @} |
| rajathr | 0:34ee385f4d2d | 360 | */ |
| rajathr | 0:34ee385f4d2d | 361 | |
| rajathr | 0:34ee385f4d2d | 362 | |
| rajathr | 0:34ee385f4d2d | 363 | /** @defgroup ADC_sampling_times |
| rajathr | 0:34ee385f4d2d | 364 | * @{ |
| rajathr | 0:34ee385f4d2d | 365 | */ |
| rajathr | 0:34ee385f4d2d | 366 | #define ADC_SampleTime_3Cycles ((uint8_t)0x00) |
| rajathr | 0:34ee385f4d2d | 367 | #define ADC_SampleTime_15Cycles ((uint8_t)0x01) |
| rajathr | 0:34ee385f4d2d | 368 | #define ADC_SampleTime_28Cycles ((uint8_t)0x02) |
| rajathr | 0:34ee385f4d2d | 369 | #define ADC_SampleTime_56Cycles ((uint8_t)0x03) |
| rajathr | 0:34ee385f4d2d | 370 | #define ADC_SampleTime_84Cycles ((uint8_t)0x04) |
| rajathr | 0:34ee385f4d2d | 371 | #define ADC_SampleTime_112Cycles ((uint8_t)0x05) |
| rajathr | 0:34ee385f4d2d | 372 | #define ADC_SampleTime_144Cycles ((uint8_t)0x06) |
| rajathr | 0:34ee385f4d2d | 373 | #define ADC_SampleTime_480Cycles ((uint8_t)0x07) |
| rajathr | 0:34ee385f4d2d | 374 | #define IS_ADC_SAMPLE_TIME_MORT(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 375 | ((TIME) == ADC_SampleTime_15Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 376 | ((TIME) == ADC_SampleTime_28Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 377 | ((TIME) == ADC_SampleTime_56Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 378 | ((TIME) == ADC_SampleTime_84Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 379 | ((TIME) == ADC_SampleTime_112Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 380 | ((TIME) == ADC_SampleTime_144Cycles) || \ |
| rajathr | 0:34ee385f4d2d | 381 | ((TIME) == ADC_SampleTime_480Cycles)) |
| rajathr | 0:34ee385f4d2d | 382 | /** |
| rajathr | 0:34ee385f4d2d | 383 | * @} |
| rajathr | 0:34ee385f4d2d | 384 | */ |
| rajathr | 0:34ee385f4d2d | 385 | |
| rajathr | 0:34ee385f4d2d | 386 | |
| rajathr | 0:34ee385f4d2d | 387 | /** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion |
| rajathr | 0:34ee385f4d2d | 388 | * @{ |
| rajathr | 0:34ee385f4d2d | 389 | */ |
| rajathr | 0:34ee385f4d2d | 390 | #define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 391 | #define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 392 | #define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 393 | #define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) |
| rajathr | 0:34ee385f4d2d | 394 | #define IS_ADC_EXT_INJEC_TRIG_EDGE_MORT(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ |
| rajathr | 0:34ee385f4d2d | 395 | ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ |
| rajathr | 0:34ee385f4d2d | 396 | ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ |
| rajathr | 0:34ee385f4d2d | 397 | ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) |
| rajathr | 0:34ee385f4d2d | 398 | |
| rajathr | 0:34ee385f4d2d | 399 | /** |
| rajathr | 0:34ee385f4d2d | 400 | * @} |
| rajathr | 0:34ee385f4d2d | 401 | */ |
| rajathr | 0:34ee385f4d2d | 402 | |
| rajathr | 0:34ee385f4d2d | 403 | |
| rajathr | 0:34ee385f4d2d | 404 | /** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion |
| rajathr | 0:34ee385f4d2d | 405 | * @{ |
| rajathr | 0:34ee385f4d2d | 406 | */ |
| rajathr | 0:34ee385f4d2d | 407 | #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 408 | #define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 409 | #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 410 | #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) |
| rajathr | 0:34ee385f4d2d | 411 | #define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 412 | #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) |
| rajathr | 0:34ee385f4d2d | 413 | #define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) |
| rajathr | 0:34ee385f4d2d | 414 | #define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) |
| rajathr | 0:34ee385f4d2d | 415 | #define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 416 | #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) |
| rajathr | 0:34ee385f4d2d | 417 | #define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) |
| rajathr | 0:34ee385f4d2d | 418 | #define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) |
| rajathr | 0:34ee385f4d2d | 419 | #define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) |
| rajathr | 0:34ee385f4d2d | 420 | #define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) |
| rajathr | 0:34ee385f4d2d | 421 | #define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) |
| rajathr | 0:34ee385f4d2d | 422 | #define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) |
| rajathr | 0:34ee385f4d2d | 423 | #define IS_ADC_EXT_INJEC_TRIG_MORT(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ |
| rajathr | 0:34ee385f4d2d | 424 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ |
| rajathr | 0:34ee385f4d2d | 425 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ |
| rajathr | 0:34ee385f4d2d | 426 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ |
| rajathr | 0:34ee385f4d2d | 427 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ |
| rajathr | 0:34ee385f4d2d | 428 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ |
| rajathr | 0:34ee385f4d2d | 429 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ |
| rajathr | 0:34ee385f4d2d | 430 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ |
| rajathr | 0:34ee385f4d2d | 431 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ |
| rajathr | 0:34ee385f4d2d | 432 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ |
| rajathr | 0:34ee385f4d2d | 433 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ |
| rajathr | 0:34ee385f4d2d | 434 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ |
| rajathr | 0:34ee385f4d2d | 435 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ |
| rajathr | 0:34ee385f4d2d | 436 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ |
| rajathr | 0:34ee385f4d2d | 437 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ |
| rajathr | 0:34ee385f4d2d | 438 | ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) |
| rajathr | 0:34ee385f4d2d | 439 | /** |
| rajathr | 0:34ee385f4d2d | 440 | * @} |
| rajathr | 0:34ee385f4d2d | 441 | */ |
| rajathr | 0:34ee385f4d2d | 442 | |
| rajathr | 0:34ee385f4d2d | 443 | |
| rajathr | 0:34ee385f4d2d | 444 | /** @defgroup ADC_injected_channel_selection |
| rajathr | 0:34ee385f4d2d | 445 | * @{ |
| rajathr | 0:34ee385f4d2d | 446 | */ |
| rajathr | 0:34ee385f4d2d | 447 | #define ADC_InjectedChannel_1 ((uint8_t)0x14) |
| rajathr | 0:34ee385f4d2d | 448 | #define ADC_InjectedChannel_2 ((uint8_t)0x18) |
| rajathr | 0:34ee385f4d2d | 449 | #define ADC_InjectedChannel_3 ((uint8_t)0x1C) |
| rajathr | 0:34ee385f4d2d | 450 | #define ADC_InjectedChannel_4 ((uint8_t)0x20) |
| rajathr | 0:34ee385f4d2d | 451 | #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ |
| rajathr | 0:34ee385f4d2d | 452 | ((CHANNEL) == ADC_InjectedChannel_2) || \ |
| rajathr | 0:34ee385f4d2d | 453 | ((CHANNEL) == ADC_InjectedChannel_3) || \ |
| rajathr | 0:34ee385f4d2d | 454 | ((CHANNEL) == ADC_InjectedChannel_4)) |
| rajathr | 0:34ee385f4d2d | 455 | /** |
| rajathr | 0:34ee385f4d2d | 456 | * @} |
| rajathr | 0:34ee385f4d2d | 457 | */ |
| rajathr | 0:34ee385f4d2d | 458 | |
| rajathr | 0:34ee385f4d2d | 459 | |
| rajathr | 0:34ee385f4d2d | 460 | /** @defgroup ADC_analog_watchdog_selection |
| rajathr | 0:34ee385f4d2d | 461 | * @{ |
| rajathr | 0:34ee385f4d2d | 462 | */ |
| rajathr | 0:34ee385f4d2d | 463 | #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) |
| rajathr | 0:34ee385f4d2d | 464 | #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) |
| rajathr | 0:34ee385f4d2d | 465 | #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) |
| rajathr | 0:34ee385f4d2d | 466 | #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 467 | #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 468 | #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) |
| rajathr | 0:34ee385f4d2d | 469 | #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 470 | #define IS_ADC_ANALOG_WATCHDOG_MORT(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ |
| rajathr | 0:34ee385f4d2d | 471 | ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ |
| rajathr | 0:34ee385f4d2d | 472 | ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ |
| rajathr | 0:34ee385f4d2d | 473 | ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ |
| rajathr | 0:34ee385f4d2d | 474 | ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ |
| rajathr | 0:34ee385f4d2d | 475 | ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ |
| rajathr | 0:34ee385f4d2d | 476 | ((WATCHDOG) == ADC_AnalogWatchdog_None)) |
| rajathr | 0:34ee385f4d2d | 477 | /** |
| rajathr | 0:34ee385f4d2d | 478 | * @} |
| rajathr | 0:34ee385f4d2d | 479 | */ |
| rajathr | 0:34ee385f4d2d | 480 | |
| rajathr | 0:34ee385f4d2d | 481 | |
| rajathr | 0:34ee385f4d2d | 482 | /** @defgroup ADC_interrupts_definition |
| rajathr | 0:34ee385f4d2d | 483 | * @{ |
| rajathr | 0:34ee385f4d2d | 484 | */ |
| rajathr | 0:34ee385f4d2d | 485 | #define ADC_IT_EOC_MORT ((uint16_t)0x0205) |
| rajathr | 0:34ee385f4d2d | 486 | #define ADC_IT_AWD_MORT ((uint16_t)0x0106) |
| rajathr | 0:34ee385f4d2d | 487 | #define ADC_IT_JEOC_MORT ((uint16_t)0x0407) |
| rajathr | 0:34ee385f4d2d | 488 | #define ADC_IT_OVR_MORT ((uint16_t)0x201A) |
| rajathr | 0:34ee385f4d2d | 489 | #define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC_MORT) || ((IT) == ADC_IT_AWD_MORT) || \ |
| rajathr | 0:34ee385f4d2d | 490 | ((IT) == ADC_IT_JEOC_MORT)|| ((IT) == ADC_IT_OVR_MORT)) |
| rajathr | 0:34ee385f4d2d | 491 | /** |
| rajathr | 0:34ee385f4d2d | 492 | * @} |
| rajathr | 0:34ee385f4d2d | 493 | */ |
| rajathr | 0:34ee385f4d2d | 494 | |
| rajathr | 0:34ee385f4d2d | 495 | |
| rajathr | 0:34ee385f4d2d | 496 | /** @defgroup ADC_flags_definition |
| rajathr | 0:34ee385f4d2d | 497 | * @{ |
| rajathr | 0:34ee385f4d2d | 498 | */ |
| rajathr | 0:34ee385f4d2d | 499 | #define ADC_FLAG_AWD_MORT ((uint8_t)0x01) |
| rajathr | 0:34ee385f4d2d | 500 | #define ADC_FLAG_EOC_MORT ((uint8_t)0x02) |
| rajathr | 0:34ee385f4d2d | 501 | #define ADC_FLAG_JEOC_MORT ((uint8_t)0x04) |
| rajathr | 0:34ee385f4d2d | 502 | #define ADC_FLAG_JSTRT_MORT ((uint8_t)0x08) |
| rajathr | 0:34ee385f4d2d | 503 | #define ADC_FLAG_STRT_MORT ((uint8_t)0x10) |
| rajathr | 0:34ee385f4d2d | 504 | #define ADC_FLAG_OVR_MORT ((uint8_t)0x20) |
| rajathr | 0:34ee385f4d2d | 505 | |
| rajathr | 0:34ee385f4d2d | 506 | #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) |
| rajathr | 0:34ee385f4d2d | 507 | #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD_MORT) || \ |
| rajathr | 0:34ee385f4d2d | 508 | ((FLAG) == ADC_FLAG_EOC_MORT) || \ |
| rajathr | 0:34ee385f4d2d | 509 | ((FLAG) == ADC_FLAG_JEOC_MORT) || \ |
| rajathr | 0:34ee385f4d2d | 510 | ((FLAG)== ADC_FLAG_JSTRT_MORT) || \ |
| rajathr | 0:34ee385f4d2d | 511 | ((FLAG) == ADC_FLAG_STRT_MORT) || \ |
| rajathr | 0:34ee385f4d2d | 512 | ((FLAG)== ADC_FLAG_OVR_MORT)) |
| rajathr | 0:34ee385f4d2d | 513 | /** |
| rajathr | 0:34ee385f4d2d | 514 | * @} |
| rajathr | 0:34ee385f4d2d | 515 | */ |
| rajathr | 0:34ee385f4d2d | 516 | |
| rajathr | 0:34ee385f4d2d | 517 | |
| rajathr | 0:34ee385f4d2d | 518 | /** @defgroup ADC_thresholds |
| rajathr | 0:34ee385f4d2d | 519 | * @{ |
| rajathr | 0:34ee385f4d2d | 520 | */ |
| rajathr | 0:34ee385f4d2d | 521 | #define IS_ADC_THRESHOLD_MORT(THRESHOLD) ((THRESHOLD) <= 0xFFF) |
| rajathr | 0:34ee385f4d2d | 522 | /** |
| rajathr | 0:34ee385f4d2d | 523 | * @} |
| rajathr | 0:34ee385f4d2d | 524 | */ |
| rajathr | 0:34ee385f4d2d | 525 | |
| rajathr | 0:34ee385f4d2d | 526 | |
| rajathr | 0:34ee385f4d2d | 527 | /** @defgroup ADC_injected_offset |
| rajathr | 0:34ee385f4d2d | 528 | * @{ |
| rajathr | 0:34ee385f4d2d | 529 | */ |
| rajathr | 0:34ee385f4d2d | 530 | #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) |
| rajathr | 0:34ee385f4d2d | 531 | /** |
| rajathr | 0:34ee385f4d2d | 532 | * @} |
| rajathr | 0:34ee385f4d2d | 533 | */ |
| rajathr | 0:34ee385f4d2d | 534 | |
| rajathr | 0:34ee385f4d2d | 535 | |
| rajathr | 0:34ee385f4d2d | 536 | /** @defgroup ADC_injected_length |
| rajathr | 0:34ee385f4d2d | 537 | * @{ |
| rajathr | 0:34ee385f4d2d | 538 | */ |
| rajathr | 0:34ee385f4d2d | 539 | #define IS_ADC_INJECTED_LENGTH_MORT(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) |
| rajathr | 0:34ee385f4d2d | 540 | /** |
| rajathr | 0:34ee385f4d2d | 541 | * @} |
| rajathr | 0:34ee385f4d2d | 542 | */ |
| rajathr | 0:34ee385f4d2d | 543 | |
| rajathr | 0:34ee385f4d2d | 544 | |
| rajathr | 0:34ee385f4d2d | 545 | /** @defgroup ADC_injected_rank |
| rajathr | 0:34ee385f4d2d | 546 | * @{ |
| rajathr | 0:34ee385f4d2d | 547 | */ |
| rajathr | 0:34ee385f4d2d | 548 | #define IS_ADC_INJECTED_RANK_MORT(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) |
| rajathr | 0:34ee385f4d2d | 549 | /** |
| rajathr | 0:34ee385f4d2d | 550 | * @} |
| rajathr | 0:34ee385f4d2d | 551 | */ |
| rajathr | 0:34ee385f4d2d | 552 | |
| rajathr | 0:34ee385f4d2d | 553 | |
| rajathr | 0:34ee385f4d2d | 554 | /** @defgroup ADC_regular_length |
| rajathr | 0:34ee385f4d2d | 555 | * @{ |
| rajathr | 0:34ee385f4d2d | 556 | */ |
| rajathr | 0:34ee385f4d2d | 557 | #define IS_ADC_REGULAR_LENGTH_MORT(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) |
| rajathr | 0:34ee385f4d2d | 558 | /** |
| rajathr | 0:34ee385f4d2d | 559 | * @} |
| rajathr | 0:34ee385f4d2d | 560 | */ |
| rajathr | 0:34ee385f4d2d | 561 | |
| rajathr | 0:34ee385f4d2d | 562 | |
| rajathr | 0:34ee385f4d2d | 563 | /** @defgroup ADC_regular_rank |
| rajathr | 0:34ee385f4d2d | 564 | * @{ |
| rajathr | 0:34ee385f4d2d | 565 | */ |
| rajathr | 0:34ee385f4d2d | 566 | #define IS_ADC_REGULAR_RANK_MORT(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) |
| rajathr | 0:34ee385f4d2d | 567 | /** |
| rajathr | 0:34ee385f4d2d | 568 | * @} |
| rajathr | 0:34ee385f4d2d | 569 | */ |
| rajathr | 0:34ee385f4d2d | 570 | |
| rajathr | 0:34ee385f4d2d | 571 | |
| rajathr | 0:34ee385f4d2d | 572 | /** @defgroup ADC_regular_discontinuous_mode_number |
| rajathr | 0:34ee385f4d2d | 573 | * @{ |
| rajathr | 0:34ee385f4d2d | 574 | */ |
| rajathr | 0:34ee385f4d2d | 575 | #define IS_ADC_REGULAR_DISC_NUMBER_MORT(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) |
| rajathr | 0:34ee385f4d2d | 576 | /** |
| rajathr | 0:34ee385f4d2d | 577 | * @} |
| rajathr | 0:34ee385f4d2d | 578 | */ |
| rajathr | 0:34ee385f4d2d | 579 | |
| rajathr | 0:34ee385f4d2d | 580 | |
| rajathr | 0:34ee385f4d2d | 581 | /** |
| rajathr | 0:34ee385f4d2d | 582 | * @} |
| rajathr | 0:34ee385f4d2d | 583 | */ |
| rajathr | 0:34ee385f4d2d | 584 | |
| rajathr | 0:34ee385f4d2d | 585 | /* Exported macro ------------------------------------------------------------*/ |
| rajathr | 0:34ee385f4d2d | 586 | /* Exported functions --------------------------------------------------------*/ |
| rajathr | 0:34ee385f4d2d | 587 | |
| rajathr | 0:34ee385f4d2d | 588 | /* Function used to set the ADC configuration to the default reset state *****/ |
| rajathr | 0:34ee385f4d2d | 589 | void ADC_DeInit_mort(void); |
| rajathr | 0:34ee385f4d2d | 590 | |
| rajathr | 0:34ee385f4d2d | 591 | /* Initialization and Configuration functions *********************************/ |
| rajathr | 0:34ee385f4d2d | 592 | void ADC_Init_mort(ADC_TypeDef_mort* ADCx, ADC_InitTypeDef_mort* ADC_InitStruct); |
| rajathr | 0:34ee385f4d2d | 593 | void ADC_StructInit_mort(ADC_InitTypeDef_mort* ADC_InitStruct); |
| rajathr | 0:34ee385f4d2d | 594 | void ADC_CommonInit_mort(ADC_CommonInitTypeDef_mort* ADC_CommonInitStruct); |
| rajathr | 0:34ee385f4d2d | 595 | void ADC_CommonStructInit_mort(ADC_CommonInitTypeDef_mort* ADC_CommonInitStruct); |
| rajathr | 0:34ee385f4d2d | 596 | void ADC_Cmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); |
| rajathr | 0:34ee385f4d2d | 597 | |
| rajathr | 0:34ee385f4d2d | 598 | /* Analog Watchdog configuration functions ************************************/ |
| rajathr | 0:34ee385f4d2d | 599 | void ADC_AnalogWatchdogCmd_mort(ADC_TypeDef_mort* ADCx, uint32_t ADC_AnalogWatchdog); |
| rajathr | 0:34ee385f4d2d | 600 | void ADC_AnalogWatchdogThresholdsConfig_mort(ADC_TypeDef_mort* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); |
| rajathr | 0:34ee385f4d2d | 601 | void ADC_AnalogWatchdogSingleChannelConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_Channel); |
| rajathr | 0:34ee385f4d2d | 602 | |
| rajathr | 0:34ee385f4d2d | 603 | /* Temperature Sensor, Vrefint and VBAT management functions ******************/ |
| rajathr | 0:34ee385f4d2d | 604 | void ADC_TempSensorVrefintCmd_mort(FunctionalState NewState); |
| rajathr | 0:34ee385f4d2d | 605 | void ADC_VBATCmd_mort(FunctionalState NewState); |
| rajathr | 0:34ee385f4d2d | 606 | |
| rajathr | 0:34ee385f4d2d | 607 | /* Regular Channels Configuration functions ***********************************/ |
| rajathr | 0:34ee385f4d2d | 608 | void ADC_RegularChannelConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); |
| rajathr | 0:34ee385f4d2d | 609 | void ADC_SoftwareStartConv_mort(ADC_TypeDef_mort* ADCx); |
| rajathr | 0:34ee385f4d2d | 610 | FlagStatus ADC_GetSoftwareStartConvStatus_mort(ADC_TypeDef_mort* ADCx); |
| rajathr | 0:34ee385f4d2d | 611 | void ADC_EOCOnEachRegularChannelCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); |
| rajathr | 0:34ee385f4d2d | 612 | void ADC_ContinuousModeCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); |
| rajathr | 0:34ee385f4d2d | 613 | void ADC_DiscModeChannelCountConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t Number); |
| rajathr | 0:34ee385f4d2d | 614 | void ADC_DiscModeCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); |
| rajathr | 0:34ee385f4d2d | 615 | uint16_t ADC_GetConversionValue_mort(ADC_TypeDef_mort* ADCx); |
| rajathr | 0:34ee385f4d2d | 616 | uint32_t ADC_GetMultiModeConversionValue_mort(void); |
| rajathr | 0:34ee385f4d2d | 617 | |
| rajathr | 0:34ee385f4d2d | 618 | /* Regular Channels DMA Configuration functions *******************************/ |
| rajathr | 0:34ee385f4d2d | 619 | void ADC_DMACmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); |
| rajathr | 0:34ee385f4d2d | 620 | void ADC_DMARequestAfterLastTransferCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); |
| rajathr | 0:34ee385f4d2d | 621 | void ADC_MultiModeDMARequestAfterLastTransferCmd_mort(FunctionalState NewState); |
| rajathr | 0:34ee385f4d2d | 622 | |
| rajathr | 0:34ee385f4d2d | 623 | /* Injected channels Configuration functions **********************************/ |
| rajathr | 0:34ee385f4d2d | 624 | void ADC_InjectedChannelConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); |
| rajathr | 0:34ee385f4d2d | 625 | void ADC_InjectedSequencerLengthConfig_mort(ADC_TypeDef_mort* ADCx, uint8_t Length); |
| rajathr | 0:34ee385f4d2d | 626 | void ADC_SetInjectedOffset_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); |
| rajathr | 0:34ee385f4d2d | 627 | void ADC_ExternalTrigInjectedConvConfig_mort(ADC_TypeDef_mort* ADCx, uint32_t ADC_ExternalTrigInjecConv); |
| rajathr | 0:34ee385f4d2d | 628 | void ADC_ExternalTrigInjectedConvEdgeConfig_mort(ADC_TypeDef_mort* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); |
| rajathr | 0:34ee385f4d2d | 629 | void ADC_SoftwareStartInjectedConv_mort(ADC_TypeDef_mort* ADCx); |
| rajathr | 0:34ee385f4d2d | 630 | FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus_mort(ADC_TypeDef_mort* ADCx); |
| rajathr | 0:34ee385f4d2d | 631 | void ADC_AutoInjectedConvCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); |
| rajathr | 0:34ee385f4d2d | 632 | void ADC_InjectedDiscModeCmd_mort(ADC_TypeDef_mort* ADCx, FunctionalState NewState); |
| rajathr | 0:34ee385f4d2d | 633 | uint16_t ADC_GetInjectedConversionValue_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_InjectedChannel); |
| rajathr | 0:34ee385f4d2d | 634 | |
| rajathr | 0:34ee385f4d2d | 635 | /* Interrupts and flags management functions **********************************/ |
| rajathr | 0:34ee385f4d2d | 636 | void ADC_ITConfig_mort(ADC_TypeDef_mort* ADCx, uint16_t ADC_IT, FunctionalState NewState); |
| rajathr | 0:34ee385f4d2d | 637 | FlagStatus ADC_GetFlagStatus_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_FLAG); |
| rajathr | 0:34ee385f4d2d | 638 | void ADC_ClearFlag_mort(ADC_TypeDef_mort* ADCx, uint8_t ADC_FLAG); |
| rajathr | 0:34ee385f4d2d | 639 | ITStatus ADC_GetITStatus_mort(ADC_TypeDef_mort* ADCx, uint16_t ADC_IT); |
| rajathr | 0:34ee385f4d2d | 640 | void ADC_ClearITPendingBit_mort(ADC_TypeDef_mort* ADCx, uint16_t ADC_IT); |
| rajathr | 0:34ee385f4d2d | 641 | |
| rajathr | 0:34ee385f4d2d | 642 | #ifdef __cplusplus |
| rajathr | 0:34ee385f4d2d | 643 | } |
| rajathr | 0:34ee385f4d2d | 644 | #endif |
| rajathr | 0:34ee385f4d2d | 645 | |
| rajathr | 0:34ee385f4d2d | 646 | #endif /*__STM32F4xx_ADC_H_MORT */ |
| rajathr | 0:34ee385f4d2d | 647 | |
| rajathr | 0:34ee385f4d2d | 648 | /** |
| rajathr | 0:34ee385f4d2d | 649 | * @} |
| rajathr | 0:34ee385f4d2d | 650 | */ |
| rajathr | 0:34ee385f4d2d | 651 | |
| rajathr | 0:34ee385f4d2d | 652 | /** |
| rajathr | 0:34ee385f4d2d | 653 | * @} |
| rajathr | 0:34ee385f4d2d | 654 | */ |
| rajathr | 0:34ee385f4d2d | 655 | |
| rajathr | 0:34ee385f4d2d | 656 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| rajathr | 0:34ee385f4d2d | 657 | |
| rajathr | 0:34ee385f4d2d | 658 | |
| rajathr | 0:34ee385f4d2d | 659 | |
| rajathr | 0:34ee385f4d2d | 660 | |
| rajathr | 0:34ee385f4d2d | 661 |