パラメータを適応変化させる事により圧縮率を向上させた動的ライス・ゴロム符号を利用した可逆圧縮方式。圧縮ソフト、圧縮率のMATLABシミュレーションは詳細はInterface誌2011年8月号に掲載されるRX62Nマイコン連動特集にて掲載予定。

Dependencies:   mbed

Files at this revision

API Documentation at this revision

Comitter:
lynxeyed_atsu
Date:
Wed Mar 30 06:05:24 2011 +0000
Commit message:
alpha

Changed in this revision

FATFileSystem.lib Show annotated file Show diff for this revision Revisions of this file
I2S_Example/.DS_Store Show annotated file Show diff for this revision Revisions of this file
I2S_Example/LPC17xx.h Show annotated file Show diff for this revision Revisions of this file
I2S_Example/core_cm3.c Show annotated file Show diff for this revision Revisions of this file
I2S_Example/core_cm3.h Show annotated file Show diff for this revision Revisions of this file
I2S_Example/i2s_irq_test.c Show annotated file Show diff for this revision Revisions of this file
I2S_Example/i2s_irq_test.h Show annotated file Show diff for this revision Revisions of this file
I2S_Example/lpc17xx_clkpwr.c Show annotated file Show diff for this revision Revisions of this file
I2S_Example/lpc17xx_clkpwr.h Show annotated file Show diff for this revision Revisions of this file
I2S_Example/lpc17xx_i2s.c Show annotated file Show diff for this revision Revisions of this file
I2S_Example/lpc17xx_i2s.h Show annotated file Show diff for this revision Revisions of this file
I2S_Example/lpc17xx_libcfg.h Show annotated file Show diff for this revision Revisions of this file
I2S_Example/lpc17xx_libcfg_default.h Show annotated file Show diff for this revision Revisions of this file
I2S_Example/lpc17xx_pinsel.c Show annotated file Show diff for this revision Revisions of this file
I2S_Example/lpc17xx_pinsel.h Show annotated file Show diff for this revision Revisions of this file
I2S_Example/lpc17xx_uart.c Show annotated file Show diff for this revision Revisions of this file
I2S_Example/lpc17xx_uart.h Show annotated file Show diff for this revision Revisions of this file
I2S_Example/lpc_types.h Show annotated file Show diff for this revision Revisions of this file
I2S_Example/system_LPC17xx.c Show annotated file Show diff for this revision Revisions of this file
I2S_Example/system_LPC17xx.h Show annotated file Show diff for this revision Revisions of this file
Lossless_lib/_bitio.cpp Show annotated file Show diff for this revision Revisions of this file
Lossless_lib/_bitio.h Show annotated file Show diff for this revision Revisions of this file
MSCFileSystem.cpp Show annotated file Show diff for this revision Revisions of this file
MSCFileSystem.h Show annotated file Show diff for this revision Revisions of this file
SDHCFileSystem.cpp Show annotated file Show diff for this revision Revisions of this file
SDHCFileSystem.h Show annotated file Show diff for this revision Revisions of this file
TextLCD/TextLCD.cpp Show annotated file Show diff for this revision Revisions of this file
TextLCD/TextLCD.h Show annotated file Show diff for this revision Revisions of this file
USBHostLite/usbhost_cpu.h Show annotated file Show diff for this revision Revisions of this file
USBHostLite/usbhost_err.h Show annotated file Show diff for this revision Revisions of this file
USBHostLite/usbhost_inc.h Show annotated file Show diff for this revision Revisions of this file
USBHostLite/usbhost_lpc17xx.c Show annotated file Show diff for this revision Revisions of this file
USBHostLite/usbhost_lpc17xx.h Show annotated file Show diff for this revision Revisions of this file
USBHostLite/usbhost_ms.c Show annotated file Show diff for this revision Revisions of this file
USBHostLite/usbhost_ms.h Show annotated file Show diff for this revision Revisions of this file
aic23b_comm.h Show annotated file Show diff for this revision Revisions of this file
main.cpp Show annotated file Show diff for this revision Revisions of this file
mbed.bld Show annotated file Show diff for this revision Revisions of this file
diff -r 000000000000 -r d920d64db582 FATFileSystem.lib
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/FATFileSystem.lib	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,1 @@
+http://mbed.org/users/mbed_unsupported/code/fatfilesystem/
\ No newline at end of file
diff -r 000000000000 -r d920d64db582 I2S_Example/.DS_Store
Binary file I2S_Example/.DS_Store has changed
diff -r 000000000000 -r d920d64db582 I2S_Example/LPC17xx.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/LPC17xx.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,1079 @@
+/**************************************************************************//**
+ * @file     LPC17xx.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
+ *           NXP LPC17xx Device Series
+ * @version: V1.08
+ * @date:    21. December 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __LPC17xx_H__
+#define __LPC17xx_H__
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+/** @addtogroup LPC17xx_System
+ * @{
+ */
+
+/** @brief IRQ interrupt source definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
+  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */
+  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */
+  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */
+  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */
+  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */
+  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */
+  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */
+  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */
+
+/******  LPC17xx Specific Interrupt Numbers *******************************************************/
+  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
+  TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */
+  TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */
+  TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */
+  TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */
+  UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */
+  UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */
+  UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */
+  UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */
+  PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */
+  I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */
+  I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */
+  I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */
+  SPI_IRQn                      = 13,       /*!< SPI Interrupt                                    */
+  SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */
+  SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */
+  PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
+  RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */
+  EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */
+  EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */
+  EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */
+  EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */
+  ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */
+  BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */
+  USB_IRQn                      = 24,       /*!< USB Interrupt                                    */
+  CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */
+  DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */
+  I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */
+  ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */
+  RIT_IRQn                      = 29,       /*!< Repetitive Interrupt Timer Interrupt             */
+  MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */
+  QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */
+  PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */
+  USBActivity_IRQn                = 33,        /*!< USB Activity Interrupt                           */
+  CANActivity_IRQn                = 34,        /*!< CAN Activity Interrupt                           */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT             1         /*!< MPU present or not                               */
+#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+
+
+#include "core_cm3.h"                       /* Cortex-M3 processor and core peripherals           */
+#include "system_LPC17xx.h"                 /* System Header                                      */
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SC) ------------------------------------------*/
+/** @brief System Control (SC) register structure definition */
+typedef struct
+{
+  __IO uint32_t FLASHCFG;               /* Flash Accelerator Module           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t PLL0CON;                /* Clocking and Power Control         */
+  __IO uint32_t PLL0CFG;
+  __I  uint32_t PLL0STAT;
+  __O  uint32_t PLL0FEED;
+       uint32_t RESERVED1[4];
+  __IO uint32_t PLL1CON;
+  __IO uint32_t PLL1CFG;
+  __I  uint32_t PLL1STAT;
+  __O  uint32_t PLL1FEED;
+       uint32_t RESERVED2[4];
+  __IO uint32_t PCON;
+  __IO uint32_t PCONP;
+       uint32_t RESERVED3[15];
+  __IO uint32_t CCLKCFG;
+  __IO uint32_t USBCLKCFG;
+  __IO uint32_t CLKSRCSEL;
+  __IO uint32_t    CANSLEEPCLR;
+  __IO uint32_t    CANWAKEFLAGS;
+       uint32_t RESERVED4[10];
+  __IO uint32_t EXTINT;                 /* External Interrupts                */
+       uint32_t RESERVED5;
+  __IO uint32_t EXTMODE;
+  __IO uint32_t EXTPOLAR;
+       uint32_t RESERVED6[12];
+  __IO uint32_t RSID;                   /* Reset                              */
+       uint32_t RESERVED7[7];
+  __IO uint32_t SCS;                    /* Syscon Miscellaneous Registers     */
+  __IO uint32_t IRCTRIM;                /* Clock Dividers                     */
+  __IO uint32_t PCLKSEL0;
+  __IO uint32_t PCLKSEL1;
+       uint32_t RESERVED8[4];
+  __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */
+  __IO uint32_t DMAREQSEL;
+  __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */
+ } LPC_SC_TypeDef;
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+/** @brief Pin Connect Block (PINCON) register structure definition */
+typedef struct
+{
+  __IO uint32_t PINSEL0;
+  __IO uint32_t PINSEL1;
+  __IO uint32_t PINSEL2;
+  __IO uint32_t PINSEL3;
+  __IO uint32_t PINSEL4;
+  __IO uint32_t PINSEL5;
+  __IO uint32_t PINSEL6;
+  __IO uint32_t PINSEL7;
+  __IO uint32_t PINSEL8;
+  __IO uint32_t PINSEL9;
+  __IO uint32_t PINSEL10;
+       uint32_t RESERVED0[5];
+  __IO uint32_t PINMODE0;
+  __IO uint32_t PINMODE1;
+  __IO uint32_t PINMODE2;
+  __IO uint32_t PINMODE3;
+  __IO uint32_t PINMODE4;
+  __IO uint32_t PINMODE5;
+  __IO uint32_t PINMODE6;
+  __IO uint32_t PINMODE7;
+  __IO uint32_t PINMODE8;
+  __IO uint32_t PINMODE9;
+  __IO uint32_t PINMODE_OD0;
+  __IO uint32_t PINMODE_OD1;
+  __IO uint32_t PINMODE_OD2;
+  __IO uint32_t PINMODE_OD3;
+  __IO uint32_t PINMODE_OD4;
+  __IO uint32_t I2CPADCFG;
+} LPC_PINCON_TypeDef;
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+/** @brief General Purpose Input/Output (GPIO) register structure definition */
+typedef struct
+{
+  union {
+    __IO uint32_t FIODIR;
+    struct {
+      __IO uint16_t FIODIRL;
+      __IO uint16_t FIODIRH;
+    };
+    struct {
+      __IO uint8_t  FIODIR0;
+      __IO uint8_t  FIODIR1;
+      __IO uint8_t  FIODIR2;
+      __IO uint8_t  FIODIR3;
+    };
+  };
+  uint32_t RESERVED0[3];
+  union {
+    __IO uint32_t FIOMASK;
+    struct {
+      __IO uint16_t FIOMASKL;
+      __IO uint16_t FIOMASKH;
+    };
+    struct {
+      __IO uint8_t  FIOMASK0;
+      __IO uint8_t  FIOMASK1;
+      __IO uint8_t  FIOMASK2;
+      __IO uint8_t  FIOMASK3;
+    };
+  };
+  union {
+    __IO uint32_t FIOPIN;
+    struct {
+      __IO uint16_t FIOPINL;
+      __IO uint16_t FIOPINH;
+    };
+    struct {
+      __IO uint8_t  FIOPIN0;
+      __IO uint8_t  FIOPIN1;
+      __IO uint8_t  FIOPIN2;
+      __IO uint8_t  FIOPIN3;
+    };
+  };
+  union {
+    __IO uint32_t FIOSET;
+    struct {
+      __IO uint16_t FIOSETL;
+      __IO uint16_t FIOSETH;
+    };
+    struct {
+      __IO uint8_t  FIOSET0;
+      __IO uint8_t  FIOSET1;
+      __IO uint8_t  FIOSET2;
+      __IO uint8_t  FIOSET3;
+    };
+  };
+  union {
+    __O  uint32_t FIOCLR;
+    struct {
+      __O  uint16_t FIOCLRL;
+      __O  uint16_t FIOCLRH;
+    };
+    struct {
+      __O  uint8_t  FIOCLR0;
+      __O  uint8_t  FIOCLR1;
+      __O  uint8_t  FIOCLR2;
+      __O  uint8_t  FIOCLR3;
+    };
+  };
+} LPC_GPIO_TypeDef;
+
+/** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */
+typedef struct
+{
+  __I  uint32_t IntStatus;
+  __I  uint32_t IO0IntStatR;
+  __I  uint32_t IO0IntStatF;
+  __O  uint32_t IO0IntClr;
+  __IO uint32_t IO0IntEnR;
+  __IO uint32_t IO0IntEnF;
+       uint32_t RESERVED0[3];
+  __I  uint32_t IO2IntStatR;
+  __I  uint32_t IO2IntStatF;
+  __O  uint32_t IO2IntClr;
+  __IO uint32_t IO2IntEnR;
+  __IO uint32_t IO2IntEnF;
+} LPC_GPIOINT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+/** @brief Timer (TIM) register structure definition */
+typedef struct
+{
+  __IO uint32_t IR;
+  __IO uint32_t TCR;
+  __IO uint32_t TC;
+  __IO uint32_t PR;
+  __IO uint32_t PC;
+  __IO uint32_t MCR;
+  __IO uint32_t MR0;
+  __IO uint32_t MR1;
+  __IO uint32_t MR2;
+  __IO uint32_t MR3;
+  __IO uint32_t CCR;
+  __I  uint32_t CR0;
+  __I  uint32_t CR1;
+       uint32_t RESERVED0[2];
+  __IO uint32_t EMR;
+       uint32_t RESERVED1[12];
+  __IO uint32_t CTCR;
+} LPC_TIM_TypeDef;
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+/** @brief Pulse-Width Modulation (PWM) register structure definition */
+typedef struct
+{
+  __IO uint32_t IR;
+  __IO uint32_t TCR;
+  __IO uint32_t TC;
+  __IO uint32_t PR;
+  __IO uint32_t PC;
+  __IO uint32_t MCR;
+  __IO uint32_t MR0;
+  __IO uint32_t MR1;
+  __IO uint32_t MR2;
+  __IO uint32_t MR3;
+  __IO uint32_t CCR;
+  __I  uint32_t CR0;
+  __I  uint32_t CR1;
+  __I  uint32_t CR2;
+  __I  uint32_t CR3;
+       uint32_t RESERVED0;
+  __IO uint32_t MR4;
+  __IO uint32_t MR5;
+  __IO uint32_t MR6;
+  __IO uint32_t PCR;
+  __IO uint32_t LER;
+       uint32_t RESERVED1[7];
+  __IO uint32_t CTCR;
+} LPC_PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+/** @brief  Universal Asynchronous Receiver Transmitter (UART) register structure definition */
+typedef struct
+{
+  union {
+  __I  uint8_t  RBR;
+  __O  uint8_t  THR;
+  __IO uint8_t  DLL;
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;
+  __IO uint32_t IER;
+  };
+  union {
+  __I  uint32_t IIR;
+  __O  uint8_t  FCR;
+  };
+  __IO uint8_t  LCR;
+       uint8_t  RESERVED1[7];
+  __I  uint8_t  LSR;
+       uint8_t  RESERVED2[7];
+  __IO uint8_t  SCR;
+       uint8_t  RESERVED3[3];
+  __IO uint32_t ACR;
+  __IO uint8_t  ICR;
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  FDR;
+       uint8_t  RESERVED5[7];
+  __IO uint8_t  TER;
+       uint8_t  RESERVED6[39];
+  __I  uint8_t  FIFOLVL;
+} LPC_UART_TypeDef;
+
+/** @brief  Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */
+typedef struct
+{
+  union {
+  __I  uint8_t  RBR;
+  __O  uint8_t  THR;
+  __IO uint8_t  DLL;
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;
+  __IO uint32_t IER;
+  };
+  union {
+  __I  uint32_t IIR;
+  __O  uint8_t  FCR;
+  };
+  __IO uint8_t  LCR;
+       uint8_t  RESERVED1[7];
+  __I  uint8_t  LSR;
+       uint8_t  RESERVED2[7];
+  __IO uint8_t  SCR;
+       uint8_t  RESERVED3[3];
+  __IO uint32_t ACR;
+  __IO uint8_t  ICR;
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  FDR;
+       uint8_t  RESERVED5[7];
+  __IO uint8_t  TER;
+       uint8_t  RESERVED6[39];
+  __I  uint8_t  FIFOLVL;
+} LPC_UART0_TypeDef;
+
+/** @brief  Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition */
+typedef struct
+{
+  union {
+  __I  uint8_t  RBR;
+  __O  uint8_t  THR;
+  __IO uint8_t  DLL;
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;
+  __IO uint32_t IER;
+  };
+  union {
+  __I  uint32_t IIR;
+  __O  uint8_t  FCR;
+  };
+  __IO uint8_t  LCR;
+       uint8_t  RESERVED1[3];
+  __IO uint8_t  MCR;
+       uint8_t  RESERVED2[3];
+  __I  uint8_t  LSR;
+       uint8_t  RESERVED3[3];
+  __I  uint8_t  MSR;
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  SCR;
+       uint8_t  RESERVED5[3];
+  __IO uint32_t ACR;
+       uint32_t RESERVED6;
+  __IO uint32_t FDR;
+       uint32_t RESERVED7;
+  __IO uint8_t  TER;
+       uint8_t  RESERVED8[27];
+  __IO uint8_t  RS485CTRL;
+       uint8_t  RESERVED9[3];
+  __IO uint8_t  ADRMATCH;
+       uint8_t  RESERVED10[3];
+  __IO uint8_t  RS485DLY;
+       uint8_t  RESERVED11[3];
+  __I  uint8_t  FIFOLVL;
+} LPC_UART1_TypeDef;
+
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
+/** @brief  Serial Peripheral Interface (SPI) register structure definition */
+typedef struct
+{
+  __IO uint32_t SPCR;
+  __I  uint32_t SPSR;
+  __IO uint32_t SPDR;
+  __IO uint32_t SPCCR;
+       uint32_t RESERVED0[3];
+  __IO uint32_t SPINT;
+} LPC_SPI_TypeDef;
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+/** @brief  Synchronous Serial Communication (SSP) register structure definition */
+typedef struct
+{
+  __IO uint32_t CR0;
+  __IO uint32_t CR1;
+  __IO uint32_t DR;
+  __I  uint32_t SR;
+  __IO uint32_t CPSR;
+  __IO uint32_t IMSC;
+  __IO uint32_t RIS;
+  __IO uint32_t MIS;
+  __IO uint32_t ICR;
+  __IO uint32_t DMACR;
+} LPC_SSP_TypeDef;
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+/** @brief  Inter-Integrated Circuit (I2C) register structure definition */
+typedef struct
+{
+  __IO uint32_t I2CONSET;
+  __I  uint32_t I2STAT;
+  __IO uint32_t I2DAT;
+  __IO uint32_t I2ADR0;
+  __IO uint32_t I2SCLH;
+  __IO uint32_t I2SCLL;
+  __O  uint32_t I2CONCLR;
+  __IO uint32_t MMCTRL;
+  __IO uint32_t I2ADR1;
+  __IO uint32_t I2ADR2;
+  __IO uint32_t I2ADR3;
+  __I  uint32_t I2DATA_BUFFER;
+  __IO uint32_t I2MASK0;
+  __IO uint32_t I2MASK1;
+  __IO uint32_t I2MASK2;
+  __IO uint32_t I2MASK3;
+} LPC_I2C_TypeDef;
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+/** @brief  Inter IC Sound (I2S) register structure definition */
+typedef struct
+{
+  __IO uint32_t I2SDAO;
+  __IO uint32_t I2SDAI;
+  __O  uint32_t I2STXFIFO;
+  __I  uint32_t I2SRXFIFO;
+  __I  uint32_t I2SSTATE;
+  __IO uint32_t I2SDMA1;
+  __IO uint32_t I2SDMA2;
+  __IO uint32_t I2SIRQ;
+  __IO uint32_t I2STXRATE;
+  __IO uint32_t I2SRXRATE;
+  __IO uint32_t I2STXBITRATE;
+  __IO uint32_t I2SRXBITRATE;
+  __IO uint32_t I2STXMODE;
+  __IO uint32_t I2SRXMODE;
+} LPC_I2S_TypeDef;
+
+/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
+/** @brief  Repetitive Interrupt Timer (RIT) register structure definition */
+typedef struct
+{
+  __IO uint32_t RICOMPVAL;
+  __IO uint32_t RIMASK;
+  __IO uint8_t  RICTRL;
+       uint8_t  RESERVED0[3];
+  __IO uint32_t RICOUNTER;
+} LPC_RIT_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+/** @brief  Real-Time Clock (RTC) register structure definition */
+typedef struct
+{
+  __IO uint8_t  ILR;
+       uint8_t  RESERVED0[7];
+  __IO uint8_t  CCR;
+       uint8_t  RESERVED1[3];
+  __IO uint8_t  CIIR;
+       uint8_t  RESERVED2[3];
+  __IO uint8_t  AMR;
+       uint8_t  RESERVED3[3];
+  __I  uint32_t CTIME0;
+  __I  uint32_t CTIME1;
+  __I  uint32_t CTIME2;
+  __IO uint8_t  SEC;
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  MIN;
+       uint8_t  RESERVED5[3];
+  __IO uint8_t  HOUR;
+       uint8_t  RESERVED6[3];
+  __IO uint8_t  DOM;
+       uint8_t  RESERVED7[3];
+  __IO uint8_t  DOW;
+       uint8_t  RESERVED8[3];
+  __IO uint16_t DOY;
+       uint16_t RESERVED9;
+  __IO uint8_t  MONTH;
+       uint8_t  RESERVED10[3];
+  __IO uint16_t YEAR;
+       uint16_t RESERVED11;
+  __IO uint32_t CALIBRATION;
+  __IO uint32_t GPREG0;
+  __IO uint32_t GPREG1;
+  __IO uint32_t GPREG2;
+  __IO uint32_t GPREG3;
+  __IO uint32_t GPREG4;
+  __IO uint8_t  RTC_AUXEN;
+       uint8_t  RESERVED12[3];
+  __IO uint8_t  RTC_AUX;
+       uint8_t  RESERVED13[3];
+  __IO uint8_t  ALSEC;
+       uint8_t  RESERVED14[3];
+  __IO uint8_t  ALMIN;
+       uint8_t  RESERVED15[3];
+  __IO uint8_t  ALHOUR;
+       uint8_t  RESERVED16[3];
+  __IO uint8_t  ALDOM;
+       uint8_t  RESERVED17[3];
+  __IO uint8_t  ALDOW;
+       uint8_t  RESERVED18[3];
+  __IO uint16_t ALDOY;
+       uint16_t RESERVED19;
+  __IO uint8_t  ALMON;
+       uint8_t  RESERVED20[3];
+  __IO uint16_t ALYEAR;
+       uint16_t RESERVED21;
+} LPC_RTC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+/** @brief  Watchdog Timer (WDT) register structure definition */
+typedef struct
+{
+  __IO uint8_t  WDMOD;
+       uint8_t  RESERVED0[3];
+  __IO uint32_t WDTC;
+  __O  uint8_t  WDFEED;
+       uint8_t  RESERVED1[3];
+  __I  uint32_t WDTV;
+  __IO uint32_t WDCLKSEL;
+} LPC_WDT_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+/** @brief  Analog-to-Digital Converter (ADC) register structure definition */
+typedef struct
+{
+  __IO uint32_t ADCR;
+  __IO uint32_t ADGDR;
+       uint32_t RESERVED0;
+  __IO uint32_t ADINTEN;
+  __I  uint32_t ADDR0;
+  __I  uint32_t ADDR1;
+  __I  uint32_t ADDR2;
+  __I  uint32_t ADDR3;
+  __I  uint32_t ADDR4;
+  __I  uint32_t ADDR5;
+  __I  uint32_t ADDR6;
+  __I  uint32_t ADDR7;
+  __I  uint32_t ADSTAT;
+  __IO uint32_t ADTRM;
+} LPC_ADC_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+/** @brief  Digital-to-Analog Converter (DAC) register structure definition */
+typedef struct
+{
+  __IO uint32_t DACR;
+  __IO uint32_t DACCTRL;
+  __IO uint16_t DACCNTVAL;
+} LPC_DAC_TypeDef;
+
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
+/** @brief  Motor Control Pulse-Width Modulation (MCPWM) register structure definition */
+typedef struct
+{
+  __I  uint32_t MCCON;
+  __O  uint32_t MCCON_SET;
+  __O  uint32_t MCCON_CLR;
+  __I  uint32_t MCCAPCON;
+  __O  uint32_t MCCAPCON_SET;
+  __O  uint32_t MCCAPCON_CLR;
+  __IO uint32_t MCTIM0;
+  __IO uint32_t MCTIM1;
+  __IO uint32_t MCTIM2;
+  __IO uint32_t MCPER0;
+  __IO uint32_t MCPER1;
+  __IO uint32_t MCPER2;
+  __IO uint32_t MCPW0;
+  __IO uint32_t MCPW1;
+  __IO uint32_t MCPW2;
+  __IO uint32_t MCDEADTIME;
+  __IO uint32_t MCCCP;
+  __IO uint32_t MCCR0;
+  __IO uint32_t MCCR1;
+  __IO uint32_t MCCR2;
+  __I  uint32_t MCINTEN;
+  __O  uint32_t MCINTEN_SET;
+  __O  uint32_t MCINTEN_CLR;
+  __I  uint32_t MCCNTCON;
+  __O  uint32_t MCCNTCON_SET;
+  __O  uint32_t MCCNTCON_CLR;
+  __I  uint32_t MCINTFLAG;
+  __O  uint32_t MCINTFLAG_SET;
+  __O  uint32_t MCINTFLAG_CLR;
+  __O  uint32_t MCCAP_CLR;
+} LPC_MCPWM_TypeDef;
+
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
+/** @brief  Quadrature Encoder Interface (QEI) register structure definition */
+typedef struct
+{
+  __O  uint32_t QEICON;
+  __I  uint32_t QEISTAT;
+  __IO uint32_t QEICONF;
+  __I  uint32_t QEIPOS;
+  __IO uint32_t QEIMAXPOS;
+  __IO uint32_t CMPOS0;
+  __IO uint32_t CMPOS1;
+  __IO uint32_t CMPOS2;
+  __I  uint32_t INXCNT;
+  __IO uint32_t INXCMP;
+  __IO uint32_t QEILOAD;
+  __I  uint32_t QEITIME;
+  __I  uint32_t QEIVEL;
+  __I  uint32_t QEICAP;
+  __IO uint32_t VELCOMP;
+  __IO uint32_t FILTER;
+       uint32_t RESERVED0[998];
+  __O  uint32_t QEIIEC;
+  __O  uint32_t QEIIES;
+  __I  uint32_t QEIINTSTAT;
+  __I  uint32_t QEIIE;
+  __O  uint32_t QEICLR;
+  __O  uint32_t QEISET;
+} LPC_QEI_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+/** @brief  Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */
+typedef struct
+{
+  __IO uint32_t mask[512];              /* ID Masks                           */
+} LPC_CANAF_RAM_TypeDef;
+
+/** @brief  Controller Area Network Acceptance Filter(CANAF) register structure definition */
+typedef struct                          /* Acceptance Filter Registers        */
+{
+  __IO uint32_t AFMR;
+  __IO uint32_t SFF_sa;
+  __IO uint32_t SFF_GRP_sa;
+  __IO uint32_t EFF_sa;
+  __IO uint32_t EFF_GRP_sa;
+  __IO uint32_t ENDofTable;
+  __I  uint32_t LUTerrAd;
+  __I  uint32_t LUTerr;
+  __IO uint32_t FCANIE;
+  __IO uint32_t FCANIC0;
+  __IO uint32_t FCANIC1;
+} LPC_CANAF_TypeDef;
+
+/** @brief  Controller Area Network Central (CANCR) register structure definition */
+typedef struct                          /* Central Registers                  */
+{
+  __I  uint32_t CANTxSR;
+  __I  uint32_t CANRxSR;
+  __I  uint32_t CANMSR;
+} LPC_CANCR_TypeDef;
+
+/** @brief  Controller Area Network Controller (CAN) register structure definition */
+typedef struct                          /* Controller Registers               */
+{
+  __IO uint32_t MOD;
+  __O  uint32_t CMR;
+  __IO uint32_t GSR;
+  __I  uint32_t ICR;
+  __IO uint32_t IER;
+  __IO uint32_t BTR;
+  __IO uint32_t EWL;
+  __I  uint32_t SR;
+  __IO uint32_t RFS;
+  __IO uint32_t RID;
+  __IO uint32_t RDA;
+  __IO uint32_t RDB;
+  __IO uint32_t TFI1;
+  __IO uint32_t TID1;
+  __IO uint32_t TDA1;
+  __IO uint32_t TDB1;
+  __IO uint32_t TFI2;
+  __IO uint32_t TID2;
+  __IO uint32_t TDA2;
+  __IO uint32_t TDB2;
+  __IO uint32_t TFI3;
+  __IO uint32_t TID3;
+  __IO uint32_t TDA3;
+  __IO uint32_t TDB3;
+} LPC_CAN_TypeDef;
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+/** @brief  General Purpose Direct Memory Access (GPDMA) register structure definition */
+typedef struct                          /* Common Registers                   */
+{
+  __I  uint32_t DMACIntStat;
+  __I  uint32_t DMACIntTCStat;
+  __O  uint32_t DMACIntTCClear;
+  __I  uint32_t DMACIntErrStat;
+  __O  uint32_t DMACIntErrClr;
+  __I  uint32_t DMACRawIntTCStat;
+  __I  uint32_t DMACRawIntErrStat;
+  __I  uint32_t DMACEnbldChns;
+  __IO uint32_t DMACSoftBReq;
+  __IO uint32_t DMACSoftSReq;
+  __IO uint32_t DMACSoftLBReq;
+  __IO uint32_t DMACSoftLSReq;
+  __IO uint32_t DMACConfig;
+  __IO uint32_t DMACSync;
+} LPC_GPDMA_TypeDef;
+
+/** @brief  General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */
+typedef struct                          /* Channel Registers                  */
+{
+  __IO uint32_t DMACCSrcAddr;
+  __IO uint32_t DMACCDestAddr;
+  __IO uint32_t DMACCLLI;
+  __IO uint32_t DMACCControl;
+  __IO uint32_t DMACCConfig;
+} LPC_GPDMACH_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+/** @brief  Universal Serial Bus (USB) register structure definition */
+typedef struct
+{
+  __I  uint32_t HcRevision;             /* USB Host Registers                 */
+  __IO uint32_t HcControl;
+  __IO uint32_t HcCommandStatus;
+  __IO uint32_t HcInterruptStatus;
+  __IO uint32_t HcInterruptEnable;
+  __IO uint32_t HcInterruptDisable;
+  __IO uint32_t HcHCCA;
+  __I  uint32_t HcPeriodCurrentED;
+  __IO uint32_t HcControlHeadED;
+  __IO uint32_t HcControlCurrentED;
+  __IO uint32_t HcBulkHeadED;
+  __IO uint32_t HcBulkCurrentED;
+  __I  uint32_t HcDoneHead;
+  __IO uint32_t HcFmInterval;
+  __I  uint32_t HcFmRemaining;
+  __I  uint32_t HcFmNumber;
+  __IO uint32_t HcPeriodicStart;
+  __IO uint32_t HcLSTreshold;
+  __IO uint32_t HcRhDescriptorA;
+  __IO uint32_t HcRhDescriptorB;
+  __IO uint32_t HcRhStatus;
+  __IO uint32_t HcRhPortStatus1;
+  __IO uint32_t HcRhPortStatus2;
+       uint32_t RESERVED0[40];
+  __I  uint32_t Module_ID;
+
+  __I  uint32_t OTGIntSt;               /* USB On-The-Go Registers            */
+  __IO uint32_t OTGIntEn;
+  __O  uint32_t OTGIntSet;
+  __O  uint32_t OTGIntClr;
+  __IO uint32_t OTGStCtrl;
+  __IO uint32_t OTGTmr;
+       uint32_t RESERVED1[58];
+
+  __I  uint32_t USBDevIntSt;            /* USB Device Interrupt Registers     */
+  __IO uint32_t USBDevIntEn;
+  __O  uint32_t USBDevIntClr;
+  __O  uint32_t USBDevIntSet;
+
+  __O  uint32_t USBCmdCode;             /* USB Device SIE Command Registers   */
+  __I  uint32_t USBCmdData;
+
+  __I  uint32_t USBRxData;              /* USB Device Transfer Registers      */
+  __O  uint32_t USBTxData;
+  __I  uint32_t USBRxPLen;
+  __O  uint32_t USBTxPLen;
+  __IO uint32_t USBCtrl;
+  __O  uint32_t USBDevIntPri;
+
+  __I  uint32_t USBEpIntSt;             /* USB Device Endpoint Interrupt Regs */
+  __IO uint32_t USBEpIntEn;
+  __O  uint32_t USBEpIntClr;
+  __O  uint32_t USBEpIntSet;
+  __O  uint32_t USBEpIntPri;
+
+  __IO uint32_t USBReEp;                /* USB Device Endpoint Realization Reg*/
+  __O  uint32_t USBEpInd;
+  __IO uint32_t USBMaxPSize;
+
+  __I  uint32_t USBDMARSt;              /* USB Device DMA Registers           */
+  __O  uint32_t USBDMARClr;
+  __O  uint32_t USBDMARSet;
+       uint32_t RESERVED2[9];
+  __IO uint32_t USBUDCAH;
+  __I  uint32_t USBEpDMASt;
+  __O  uint32_t USBEpDMAEn;
+  __O  uint32_t USBEpDMADis;
+  __I  uint32_t USBDMAIntSt;
+  __IO uint32_t USBDMAIntEn;
+       uint32_t RESERVED3[2];
+  __I  uint32_t USBEoTIntSt;
+  __O  uint32_t USBEoTIntClr;
+  __O  uint32_t USBEoTIntSet;
+  __I  uint32_t USBNDDRIntSt;
+  __O  uint32_t USBNDDRIntClr;
+  __O  uint32_t USBNDDRIntSet;
+  __I  uint32_t USBSysErrIntSt;
+  __O  uint32_t USBSysErrIntClr;
+  __O  uint32_t USBSysErrIntSet;
+       uint32_t RESERVED4[15];
+
+  union {
+  __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */
+  __O  uint32_t I2C_TX;
+  };
+  __I  uint32_t I2C_STS;
+  __IO uint32_t I2C_CTL;
+  __IO uint32_t I2C_CLKHI;
+  __O  uint32_t I2C_CLKLO;
+       uint32_t RESERVED5[824];
+
+  union {
+  __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */
+  __IO uint32_t OTGClkCtrl;
+  };
+  union {
+  __I  uint32_t USBClkSt;
+  __I  uint32_t OTGClkSt;
+  };
+} LPC_USB_TypeDef;
+
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+/** @brief  Ethernet Media Access Controller (EMAC) register structure definition */
+typedef struct
+{
+  __IO uint32_t MAC1;                   /* MAC Registers                      */
+  __IO uint32_t MAC2;
+  __IO uint32_t IPGT;
+  __IO uint32_t IPGR;
+  __IO uint32_t CLRT;
+  __IO uint32_t MAXF;
+  __IO uint32_t SUPP;
+  __IO uint32_t TEST;
+  __IO uint32_t MCFG;
+  __IO uint32_t MCMD;
+  __IO uint32_t MADR;
+  __O  uint32_t MWTD;
+  __I  uint32_t MRDD;
+  __I  uint32_t MIND;
+       uint32_t RESERVED0[2];
+  __IO uint32_t SA0;
+  __IO uint32_t SA1;
+  __IO uint32_t SA2;
+       uint32_t RESERVED1[45];
+  __IO uint32_t Command;                /* Control Registers                  */
+  __I  uint32_t Status;
+  __IO uint32_t RxDescriptor;
+  __IO uint32_t RxStatus;
+  __IO uint32_t RxDescriptorNumber;
+  __I  uint32_t RxProduceIndex;
+  __IO uint32_t RxConsumeIndex;
+  __IO uint32_t TxDescriptor;
+  __IO uint32_t TxStatus;
+  __IO uint32_t TxDescriptorNumber;
+  __IO uint32_t TxProduceIndex;
+  __I  uint32_t TxConsumeIndex;
+       uint32_t RESERVED2[10];
+  __I  uint32_t TSV0;
+  __I  uint32_t TSV1;
+  __I  uint32_t RSV;
+       uint32_t RESERVED3[3];
+  __IO uint32_t FlowControlCounter;
+  __I  uint32_t FlowControlStatus;
+       uint32_t RESERVED4[34];
+  __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */
+  __IO uint32_t RxFilterWoLStatus;
+  __IO uint32_t RxFilterWoLClear;
+       uint32_t RESERVED5;
+  __IO uint32_t HashFilterL;
+  __IO uint32_t HashFilterH;
+       uint32_t RESERVED6[882];
+  __I  uint32_t IntStatus;              /* Module Control Registers           */
+  __IO uint32_t IntEnable;
+  __O  uint32_t IntClear;
+  __O  uint32_t IntSet;
+       uint32_t RESERVED7;
+  __IO uint32_t PowerDown;
+       uint32_t RESERVED8;
+  __IO uint32_t Module_ID;
+} LPC_EMAC_TypeDef;
+
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/* Base addresses                                                             */
+#define LPC_FLASH_BASE        (0x00000000UL)
+#define LPC_RAM_BASE          (0x10000000UL)
+#ifdef __LPC17XX_REV00
+#define LPC_AHBRAM0_BASE      (0x20000000UL)
+#define LPC_AHBRAM1_BASE      (0x20004000UL)
+#else
+#define LPC_AHBRAM0_BASE      (0x2007C000UL)
+#define LPC_AHBRAM1_BASE      (0x20080000UL)
+#endif
+#define LPC_GPIO_BASE         (0x2009C000UL)
+#define LPC_APB0_BASE         (0x40000000UL)
+#define LPC_APB1_BASE         (0x40080000UL)
+#define LPC_AHB_BASE          (0x50000000UL)
+#define LPC_CM3_BASE          (0xE0000000UL)
+
+/* APB0 peripherals                                                           */
+#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x00000)
+#define LPC_TIM0_BASE         (LPC_APB0_BASE + 0x04000)
+#define LPC_TIM1_BASE         (LPC_APB0_BASE + 0x08000)
+#define LPC_UART0_BASE        (LPC_APB0_BASE + 0x0C000)
+#define LPC_UART1_BASE        (LPC_APB0_BASE + 0x10000)
+#define LPC_PWM1_BASE         (LPC_APB0_BASE + 0x18000)
+#define LPC_I2C0_BASE         (LPC_APB0_BASE + 0x1C000)
+#define LPC_SPI_BASE          (LPC_APB0_BASE + 0x20000)
+#define LPC_RTC_BASE          (LPC_APB0_BASE + 0x24000)
+#define LPC_GPIOINT_BASE      (LPC_APB0_BASE + 0x28080)
+#define LPC_PINCON_BASE       (LPC_APB0_BASE + 0x2C000)
+#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x30000)
+#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x34000)
+#define LPC_CANAF_RAM_BASE    (LPC_APB0_BASE + 0x38000)
+#define LPC_CANAF_BASE        (LPC_APB0_BASE + 0x3C000)
+#define LPC_CANCR_BASE        (LPC_APB0_BASE + 0x40000)
+#define LPC_CAN1_BASE         (LPC_APB0_BASE + 0x44000)
+#define LPC_CAN2_BASE         (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C1_BASE         (LPC_APB0_BASE + 0x5C000)
+
+/* APB1 peripherals                                                           */
+#define LPC_SSP0_BASE         (LPC_APB1_BASE + 0x08000)
+#define LPC_DAC_BASE          (LPC_APB1_BASE + 0x0C000)
+#define LPC_TIM2_BASE         (LPC_APB1_BASE + 0x10000)
+#define LPC_TIM3_BASE         (LPC_APB1_BASE + 0x14000)
+#define LPC_UART2_BASE        (LPC_APB1_BASE + 0x18000)
+#define LPC_UART3_BASE        (LPC_APB1_BASE + 0x1C000)
+#define LPC_I2C2_BASE         (LPC_APB1_BASE + 0x20000)
+#define LPC_I2S_BASE          (LPC_APB1_BASE + 0x28000)
+#define LPC_RIT_BASE          (LPC_APB1_BASE + 0x30000)
+#define LPC_MCPWM_BASE        (LPC_APB1_BASE + 0x38000)
+#define LPC_QEI_BASE          (LPC_APB1_BASE + 0x3C000)
+#define LPC_SC_BASE           (LPC_APB1_BASE + 0x7C000)
+
+/* AHB peripherals                                                            */
+#define LPC_EMAC_BASE         (LPC_AHB_BASE  + 0x00000)
+#define LPC_GPDMA_BASE        (LPC_AHB_BASE  + 0x04000)
+#define LPC_GPDMACH0_BASE     (LPC_AHB_BASE  + 0x04100)
+#define LPC_GPDMACH1_BASE     (LPC_AHB_BASE  + 0x04120)
+#define LPC_GPDMACH2_BASE     (LPC_AHB_BASE  + 0x04140)
+#define LPC_GPDMACH3_BASE     (LPC_AHB_BASE  + 0x04160)
+#define LPC_GPDMACH4_BASE     (LPC_AHB_BASE  + 0x04180)
+#define LPC_GPDMACH5_BASE     (LPC_AHB_BASE  + 0x041A0)
+#define LPC_GPDMACH6_BASE     (LPC_AHB_BASE  + 0x041C0)
+#define LPC_GPDMACH7_BASE     (LPC_AHB_BASE  + 0x041E0)
+#define LPC_USB_BASE          (LPC_AHB_BASE  + 0x0C000)
+
+/* GPIOs                                                                      */
+#define LPC_GPIO0_BASE        (LPC_GPIO_BASE + 0x00000)
+#define LPC_GPIO1_BASE        (LPC_GPIO_BASE + 0x00020)
+#define LPC_GPIO2_BASE        (LPC_GPIO_BASE + 0x00040)
+#define LPC_GPIO3_BASE        (LPC_GPIO_BASE + 0x00060)
+#define LPC_GPIO4_BASE        (LPC_GPIO_BASE + 0x00080)
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+#define LPC_SC                ((LPC_SC_TypeDef        *) LPC_SC_BASE       )
+#define LPC_GPIO0             ((LPC_GPIO_TypeDef      *) LPC_GPIO0_BASE    )
+#define LPC_GPIO1             ((LPC_GPIO_TypeDef      *) LPC_GPIO1_BASE    )
+#define LPC_GPIO2             ((LPC_GPIO_TypeDef      *) LPC_GPIO2_BASE    )
+#define LPC_GPIO3             ((LPC_GPIO_TypeDef      *) LPC_GPIO3_BASE    )
+#define LPC_GPIO4             ((LPC_GPIO_TypeDef      *) LPC_GPIO4_BASE    )
+#define LPC_WDT               ((LPC_WDT_TypeDef       *) LPC_WDT_BASE      )
+#define LPC_TIM0              ((LPC_TIM_TypeDef       *) LPC_TIM0_BASE     )
+#define LPC_TIM1              ((LPC_TIM_TypeDef       *) LPC_TIM1_BASE     )
+#define LPC_TIM2              ((LPC_TIM_TypeDef       *) LPC_TIM2_BASE     )
+#define LPC_TIM3              ((LPC_TIM_TypeDef       *) LPC_TIM3_BASE     )
+#define LPC_RIT               ((LPC_RIT_TypeDef       *) LPC_RIT_BASE      )
+#define LPC_UART0             ((LPC_UART_TypeDef      *) LPC_UART0_BASE    )
+#define LPC_UART1             ((LPC_UART1_TypeDef     *) LPC_UART1_BASE    )
+#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
+#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
+#define LPC_PWM1              ((LPC_PWM_TypeDef       *) LPC_PWM1_BASE     )
+#define LPC_I2C0              ((LPC_I2C_TypeDef       *) LPC_I2C0_BASE     )
+#define LPC_I2C1              ((LPC_I2C_TypeDef       *) LPC_I2C1_BASE     )
+#define LPC_I2C2              ((LPC_I2C_TypeDef       *) LPC_I2C2_BASE     )
+#define LPC_I2S               ((LPC_I2S_TypeDef       *) LPC_I2S_BASE      )
+#define LPC_SPI               ((LPC_SPI_TypeDef       *) LPC_SPI_BASE      )
+#define LPC_RTC               ((LPC_RTC_TypeDef       *) LPC_RTC_BASE      )
+#define LPC_GPIOINT           ((LPC_GPIOINT_TypeDef   *) LPC_GPIOINT_BASE  )
+#define LPC_PINCON            ((LPC_PINCON_TypeDef    *) LPC_PINCON_BASE   )
+#define LPC_SSP0              ((LPC_SSP_TypeDef       *) LPC_SSP0_BASE     )
+#define LPC_SSP1              ((LPC_SSP_TypeDef       *) LPC_SSP1_BASE     )
+#define LPC_ADC               ((LPC_ADC_TypeDef       *) LPC_ADC_BASE      )
+#define LPC_DAC               ((LPC_DAC_TypeDef       *) LPC_DAC_BASE      )
+#define LPC_CANAF_RAM         ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF             ((LPC_CANAF_TypeDef     *) LPC_CANAF_BASE    )
+#define LPC_CANCR             ((LPC_CANCR_TypeDef     *) LPC_CANCR_BASE    )
+#define LPC_CAN1              ((LPC_CAN_TypeDef       *) LPC_CAN1_BASE     )
+#define LPC_CAN2              ((LPC_CAN_TypeDef       *) LPC_CAN2_BASE     )
+#define LPC_MCPWM             ((LPC_MCPWM_TypeDef     *) LPC_MCPWM_BASE    )
+#define LPC_QEI               ((LPC_QEI_TypeDef       *) LPC_QEI_BASE      )
+#define LPC_EMAC              ((LPC_EMAC_TypeDef      *) LPC_EMAC_BASE     )
+#define LPC_GPDMA             ((LPC_GPDMA_TypeDef     *) LPC_GPDMA_BASE    )
+#define DMAREQSEL             (*(__IO uint32_t *)  ( 0x4000C1C4))
+#define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )
+#define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )
+#define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )
+#define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )
+#define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )
+#define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )
+#define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )
+#define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )
+#define LPC_USB               ((LPC_USB_TypeDef       *) LPC_USB_BASE      )
+
+/**
+ * @}
+ */
+
+#endif  // __LPC17xx_H__
diff -r 000000000000 -r d920d64db582 I2S_Example/core_cm3.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/core_cm3.c	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,794 @@
+/**************************************************************************//**
+ * @file     core_cm3.c
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version  V1.30
+ * @date     30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <stdint.h>
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+__ASM uint32_t __get_PSP(void)
+{
+  mrs r0, psp
+  bx lr
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+  msr psp, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+__ASM uint32_t __get_MSP(void)
+{
+  mrs r0, msp
+  bx lr
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+  msr msp, r0
+  bx lr
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+__ASM uint32_t __REV16(uint16_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+__ASM int32_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief  Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+__ASM void __CLREX(void)
+{
+  clrex
+}
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+__ASM uint32_t  __get_BASEPRI(void)
+{
+  mrs r0, basepri
+  bx lr
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+  msr basepri, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+__ASM uint32_t __get_PRIMASK(void)
+{
+  mrs r0, primask
+  bx lr
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+  msr primask, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+__ASM uint32_t  __get_FAULTMASK(void)
+{
+  mrs r0, faultmask
+  bx lr
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+  msr faultmask, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Control Register value
+ *
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+__ASM uint32_t __get_CONTROL(void)
+{
+  mrs r0, control
+  bx lr
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+__ASM void __set_CONTROL(uint32_t control)
+{
+  msr control, r0
+  bx lr
+}
+
+#endif /* __ARMCC_VERSION  */
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#pragma diag_suppress=Pe940
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void)
+{
+  __ASM("mrs r0, psp");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM("msr psp, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+  __ASM("mrs r0, msp");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM("msr msp, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+  __ASM("rev16 r0, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+  __ASM("rbit r0, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit values)
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+  __ASM("ldrexb r0, [r0]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+  __ASM("ldrexh r0, [r0]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+  __ASM("ldrex r0, [r0]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+  __ASM("strexb r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+  __ASM("strexh r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+  __ASM("strex r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void) __attribute__( ( naked ) );
+uint32_t __get_PSP(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, psp\n\t"
+                  "MOV r0, %0 \n\t"
+                  "BX  lr     \n\t"  : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
+void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n\t"
+                  "BX  lr     \n\t" : : "r" (topOfProcStack) );
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void) __attribute__( ( naked ) );
+uint32_t __get_MSP(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, msp\n\t"
+                  "MOV r0, %0 \n\t"
+                  "BX  lr     \n\t"  : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
+void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n\t"
+                  "BX  lr     \n\t" : : "r" (topOfMainStack) );
+}
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+uint32_t __get_BASEPRI(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+uint32_t __get_PRIMASK(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+/**
+ * @brief  Return the Control Register value
+*
+*  @return Control value
+ *
+ * Return the content of the control register
+ */
+uint32_t __get_CONTROL(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/**
+ * @brief  Reverse byte order in integer value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in integer value
+ */
+uint32_t __REV(uint32_t value)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+int32_t __REVSH(int16_t value)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result=0;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit value
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+    uint8_t result=0;
+
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+    uint16_t result=0;
+
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+    uint32_t result=0;
+
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+   uint32_t result=0;
+
+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+   uint32_t result=0;
+
+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+   uint32_t result=0;
+
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
diff -r 000000000000 -r d920d64db582 I2S_Example/core_cm3.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/core_cm3.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,1834 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V1.30
+ * @date     30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CM3_CORE_H__
+#define __CM3_CORE_H__
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
+ *
+ * List of Lint messages which will be suppressed and not shown:
+ *   - Error 10: \n
+ *     register uint32_t __regBasePri         __asm("basepri"); \n
+ *     Error 10: Expecting ';'
+ * .
+ *   - Error 530: \n
+ *     return(__regBasePri); \n
+ *     Warning 530: Symbol '__regBasePri' (line 264) not initialized
+ * .
+ *   - Error 550: \n
+ *     __regBasePri = (basePri & 0x1ff); \n
+ *     Warning 550: Symbol '__regBasePri' (line 271) not accessed
+ * .
+ *   - Error 754: \n
+ *     uint32_t RESERVED0[24]; \n
+ *     Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
+ * .
+ *   - Error 750: \n
+ *     #define __CM3_CORE_H__ \n
+ *     Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
+ * .
+ *   - Error 528: \n
+ *     static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
+ *     Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
+ * .
+ *   - Error 751: \n
+ *     } InterruptType_Type; \n
+ *     Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
+ * .
+ * Note:  To re-enable a Message, insert a space before 'lint' *
+ *
+ */
+
+/*lint -save */
+/*lint -e10  */
+/*lint -e530 */
+/*lint -e550 */
+/*lint -e754 */
+/*lint -e750 */
+/*lint -e528 */
+/*lint -e751 */
+
+
+/** @addtogroup CMSIS_CM3_core_definitions CMSIS CM3 Core Definitions
+  This file defines all structures and symbols for CMSIS core:
+    - CMSIS version number
+    - Cortex-M core registers and bitfields
+    - Cortex-M core peripheral base address
+  @{
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (0x30)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
+
+#include <stdint.h>                           /* Include standard types */
+
+#if defined (__ICCARM__)
+  #include <intrinsics.h>                     /* IAR Intrinsics   */
+#endif
+
+
+#ifndef __NVIC_PRIO_BITS
+  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */
+#endif
+
+
+
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+
+#ifdef __cplusplus
+  #define     __I     volatile                /*!< defines 'read only' permissions      */
+#else
+  #define     __I     volatile const          /*!< defines 'read only' permissions      */
+#endif
+#define     __O     volatile                  /*!< defines 'write only' permissions     */
+#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
+ @{
+*/
+
+
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
+  memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
+  @{
+ */
+/** @brief  Nested Vectored Interrupt Controller (NVIC) register structure definition */
+typedef struct
+{
+  __IO uint32_t ISER[8];                      /*!< Offset: 0x000  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                      /*!< Offset: 0x080  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                      /*!< Offset: 0x100  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                      /*!< Offset: 0x180  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                      /*!< Offset: 0x200  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                      /*!< Offset: 0x300  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                         /*!< Offset: 0xE00  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+/*@}*/ /* end of group CMSIS_CM3_NVIC */
+
+
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
+  memory mapped structure for System Control Block (SCB)
+  @{
+ */
+/** @brief  System Control Block (SCB) register structure definition */
+typedef struct
+{
+  __I  uint32_t CPUID;                        /*!< Offset: 0x00  CPU ID Base Register                                  */
+  __IO uint32_t ICSR;                         /*!< Offset: 0x04  Interrupt Control State Register                      */
+  __IO uint32_t VTOR;                         /*!< Offset: 0x08  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                        /*!< Offset: 0x0C  Application Interrupt / Reset Control Register        */
+  __IO uint32_t SCR;                          /*!< Offset: 0x10  System Control Register                               */
+  __IO uint32_t CCR;                          /*!< Offset: 0x14  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                      /*!< Offset: 0x18  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                        /*!< Offset: 0x24  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                         /*!< Offset: 0x28  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                         /*!< Offset: 0x2C  Hard Fault Status Register                            */
+  __IO uint32_t DFSR;                         /*!< Offset: 0x30  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                        /*!< Offset: 0x34  Mem Manage Address Register                           */
+  __IO uint32_t BFAR;                         /*!< Offset: 0x38  Bus Fault Address Register                            */
+  __IO uint32_t AFSR;                         /*!< Offset: 0x3C  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                       /*!< Offset: 0x40  Processor Feature Register                            */
+  __I  uint32_t DFR;                          /*!< Offset: 0x48  Debug Feature Register                                */
+  __I  uint32_t ADR;                          /*!< Offset: 0x4C  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                      /*!< Offset: 0x50  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                      /*!< Offset: 0x60  ISA Feature Register                                  */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFul << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFul << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFul << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1ul << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1ul << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1ul << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1ul << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1ul << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1ul << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1ul << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFul << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1ul << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (0x1FFul << SCB_VTOR_TBLBASE_Pos)              /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1ul << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7ul << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1ul << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1ul << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1ul << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1ul << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1ul << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1ul << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1ul << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1ul << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1ul << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1ul << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1ul << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1ul << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1ul << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1ul << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1ul << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1ul << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1ul << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1ul << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1ul << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1ul << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1ul << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1ul << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1ul << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFul << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFul << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1ul << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1ul << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1ul << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1ul << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1ul << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1ul << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1ul << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1ul << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+/*@}*/ /* end of group CMSIS_CM3_SCB */
+
+
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
+  memory mapped structure for SysTick
+  @{
+ */
+/** @brief  System Tick Timer (SysTick) register structure definition */
+typedef struct
+{
+  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
+  __IO uint32_t RELOAD;                       /*!< Offset: 0x04  SysTick Reload Value Register       */
+  __IO uint32_t CURR;                          /*!< Offset: 0x08  SysTick Current Value Register      */
+  __IO uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+/*@}*/ /* end of group CMSIS_CM3_SysTick */
+
+
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
+  memory mapped structure for Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+/** @brief   Instrumentation Trace Macrocell (ITM) register structure definition */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                       /*!< Offset:       ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                      /*!< Offset:       ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                      /*!< Offset:       ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                               /*!< Offset: 0x00  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                          /*!< Offset:       ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                          /*!< Offset:       ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                          /*!< Offset:       ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __IO uint32_t IWR;                          /*!< Offset:       ITM Integration Write Register            */
+  __IO uint32_t IRR;                          /*!< Offset:       ITM Integration Read Register             */
+  __IO uint32_t IMCR;                         /*!< Offset:       ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __IO uint32_t LAR;                          /*!< Offset:       ITM Lock Access Register                  */
+  __IO uint32_t LSR;                          /*!< Offset:       ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                         /*!< Offset:       ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                         /*!< Offset:       ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                         /*!< Offset:       ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                         /*!< Offset:       ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                         /*!< Offset:       ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                         /*!< Offset:       ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                         /*!< Offset:       ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                         /*!< Offset:       ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                         /*!< Offset:       ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                         /*!< Offset:       ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                         /*!< Offset:       ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                         /*!< Offset:       ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFul << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1ul << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_ATBID_Msk                  (0x7Ful << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3ul << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1ul << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1ul << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1ul << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1ul << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1ul << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1ul << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1ul << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1ul << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1ul << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1ul << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1ul << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+/*@}*/ /* end of group CMSIS_CM3_ITM */
+
+
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
+  memory mapped structure for Interrupt Type
+  @{
+ */
+/** @brief   Instrumentation Trace Macrocell (ITM) register structure definition */
+typedef struct
+{
+       uint32_t RESERVED0;
+  __I  uint32_t ICTR;                         /*!< Offset: 0x04  Interrupt Control Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                        /*!< Offset: 0x08  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1;
+#endif
+} InterruptType_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define InterruptType_ICTR_INTLINESNUM_Pos  0                                             /*!< InterruptType ICTR: INTLINESNUM Position */
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define InterruptType_ACTLR_DISFOLD_Pos     2                                             /*!< InterruptType ACTLR: DISFOLD Position */
+#define InterruptType_ACTLR_DISFOLD_Msk    (1ul << InterruptType_ACTLR_DISFOLD_Pos)       /*!< InterruptType ACTLR: DISFOLD Mask */
+
+#define InterruptType_ACTLR_DISDEFWBUF_Pos  1                                             /*!< InterruptType ACTLR: DISDEFWBUF Position */
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos)    /*!< InterruptType ACTLR: DISDEFWBUF Mask */
+
+#define InterruptType_ACTLR_DISMCYCINT_Pos  0                                             /*!< InterruptType ACTLR: DISMCYCINT Position */
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos)    /*!< InterruptType ACTLR: DISMCYCINT Mask */
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
+  memory mapped structure for Memory Protection Unit (MPU)
+  @{
+ */
+/** @brief   Memory Protection Unit (MPU) register structure definition */
+typedef struct
+{
+  __I  uint32_t TYPE;                         /*!< Offset: 0x00  MPU Type Register                              */
+  __IO uint32_t CTRL;                         /*!< Offset: 0x04  MPU Control Register                           */
+  __IO uint32_t RNR;                          /*!< Offset: 0x08  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                         /*!< Offset: 0x0C  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                         /*!< Offset: 0x10  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                      /*!< Offset: 0x14  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                      /*!< Offset: 0x18  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                      /*!< Offset: 0x1C  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                      /*!< Offset: 0x20  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                      /*!< Offset: 0x24  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                      /*!< Offset: 0x28  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFul << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFul << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1ul << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1ul << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1ul << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1ul << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFul << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFul << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1ul << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFul << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
+#define MPU_RASR_XN_Msk                    (1ul << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
+#define MPU_RASR_AP_Msk                    (7ul << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
+#define MPU_RASR_TEX_Msk                   (7ul << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
+#define MPU_RASR_S_Msk                     (1ul << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
+#define MPU_RASR_C_Msk                     (1ul << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
+#define MPU_RASR_B_Msk                     (1ul << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFul << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1Ful << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENA_Msk                    (0x1Ful << MPU_RASR_ENA_Pos)                  /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@}*/ /* end of group CMSIS_CM3_MPU */
+#endif
+
+
+/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
+  memory mapped structure for Core Debug Register
+  @{
+ */
+/** @brief   Core Debug register structure definition */
+typedef struct
+{
+  __IO uint32_t DHCSR;                        /*!< Offset: 0x00  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                        /*!< Offset: 0x04  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                        /*!< Offset: 0x08  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                        /*!< Offset: 0x0C  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1ul << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1ul << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1ul << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1ul << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1ul << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1ul << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1ul << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1ul << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1ul << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1ul << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1ul << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1ul << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1ul << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1ul << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
+
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                  */
+#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address           */
+#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address */
+
+#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
+#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
+#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
+#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
+#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90)                      /*!< Memory Protection Unit            */
+  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
+#endif
+
+/*@}*/ /* end of group CMSIS_CM3_core_register */
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#define __enable_fault_irq                __enable_fiq
+#define __disable_fault_irq               __disable_fiq
+
+#define __NOP                             __nop
+#define __WFI                             __wfi
+#define __WFE                             __wfe
+#define __SEV                             __sev
+#define __ISB()                           __isb(0)
+#define __DSB()                           __dsb(0)
+#define __DMB()                           __dmb(0)
+#define __REV                             __rev
+#define __RBIT                            __rbit
+#define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))
+#define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))
+#define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))
+#define __STREXB(value, ptr)              __strex(value, ptr)
+#define __STREXH(value, ptr)              __strex(value, ptr)
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief  Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+extern void __CLREX(void);
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param   priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask faultMask value
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief  Return the Control Register value
+ *
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+#else  /* (__ARMCC_VERSION >= 400000)  */
+
+/**
+ * @brief  Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+#define __CLREX                           __clrex
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+static __INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & 1);
+}
+
+/**
+ * @brief  Return the Control Register value
+ *
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+#endif /* __ARMCC_VERSION  */
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
+#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
+
+static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }
+static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }
+
+#define __NOP                                     __no_operation            /*!< no operation intrinsic in IAR Compiler */
+static __INLINE  void __WFI()                     { __ASM ("wfi"); }
+static __INLINE  void __WFE()                     { __ASM ("wfe"); }
+static __INLINE  void __SEV()                     { __ASM ("sev"); }
+static __INLINE  void __CLREX()                   { __ASM ("clrex"); }
+
+/* intrinsic void __ISB(void)                                     */
+/* intrinsic void __DSB(void)                                     */
+/* intrinsic void __DMB(void)                                     */
+/* intrinsic void __set_PRIMASK();                                */
+/* intrinsic void __get_PRIMASK();                                */
+/* intrinsic void __set_FAULTMASK();                              */
+/* intrinsic void __get_FAULTMASK();                              */
+/* intrinsic uint32_t __REV(uint32_t value);                      */
+/* intrinsic uint32_t __REVSH(uint32_t value);                    */
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
+/* intrinsic unsigned long __LDREX(unsigned long *);              */
+
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit values)
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }
+static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }
+
+static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }
+static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }
+
+static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
+static __INLINE void __WFI()                      { __ASM volatile ("wfi"); }
+static __INLINE void __WFE()                      { __ASM volatile ("wfe"); }
+static __INLINE void __SEV()                      { __ASM volatile ("sev"); }
+static __INLINE void __ISB()                      { __ASM volatile ("isb"); }
+static __INLINE void __DSB()                      { __ASM volatile ("dsb"); }
+static __INLINE void __DMB()                      { __ASM volatile ("dmb"); }
+static __INLINE void __CLREX()                    { __ASM volatile ("clrex"); }
+
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+extern uint32_t  __get_PRIMASK(void);
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief  Return the Control Register value
+*
+*  @return Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+/**
+ * @brief  Reverse byte order in integer value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in integer value
+ */
+extern uint32_t __REV(uint32_t value);
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit value
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+
+/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
+  Core  Function Interface containing:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Reset Functions
+*/
+/*@{*/
+
+
+/* ##########################   NVIC functions  #################################### */
+
+/**
+ * @brief  Set the Priority Grouping in NVIC Interrupt Controller
+ *
+ * @param  PriorityGroup is priority grouping field
+ *
+ * Set the priority grouping field using the required unlock sequence.
+ * The parameter priority_grouping is assigned to the field
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                       |
+                (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+/**
+ * @brief  Get the Priority Grouping from NVIC Interrupt Controller
+ *
+ * @return priority grouping field
+ *
+ * Get the priority grouping from NVIC Interrupt Controller.
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+/**
+ * @brief  Enable Interrupt in NVIC Interrupt Controller
+ *
+ * @param  IRQn   The positive number of the external interrupt to enable
+ *
+ * Enable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+/**
+ * @brief  Disable the interrupt line for external interrupt specified
+ *
+ * @param  IRQn   The positive number of the external interrupt to disable
+ *
+ * Disable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+/**
+ * @brief  Read the interrupt pending bit for a device specific interrupt source
+ *
+ * @param  IRQn    The number of the device specifc interrupt
+ * @return         1 = interrupt pending, 0 = interrupt not pending
+ *
+ * Read the pending register in NVIC and return 1 if its status is pending,
+ * otherwise it returns 0
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+/**
+ * @brief  Set the pending bit for an external interrupt
+ *
+ * @param  IRQn    The number of the interrupt for set pending
+ *
+ * Set the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+/**
+ * @brief  Clear the pending bit for an external interrupt
+ *
+ * @param  IRQn    The number of the interrupt for clear pending
+ *
+ * Clear the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+/**
+ * @brief  Read the active bit for an external interrupt
+ *
+ * @param  IRQn    The number of the interrupt for read active bit
+ * @return         1 = interrupt active, 0 = interrupt not active
+ *
+ * Read the active register in NVIC and returns 1 if its status is active,
+ * otherwise it returns 0.
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+/**
+ * @brief  Set the priority for an interrupt
+ *
+ * @param  IRQn      The number of the interrupt for set priority
+ * @param  priority  The priority to set
+ *
+ * Set the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+/**
+ * @brief  Read the priority for an interrupt
+ *
+ * @param  IRQn      The number of the interrupt for get priority
+ * @return           The priority for the interrupt
+ *
+ * Read the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * The returned priority value is automatically aligned to the implemented
+ * priority bits of the microcontroller.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M3 system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/**
+ * @brief  Encode the priority for an interrupt
+ *
+ * @param  PriorityGroup    The used priority group
+ * @param  PreemptPriority  The preemptive priority value (starting from 0)
+ * @param  SubPriority      The sub priority value (starting from 0)
+ * @return                  The encoded priority for the interrupt
+ *
+ * Encode the priority for an interrupt with the given priority group,
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The returned priority value can be used for NVIC_SetPriority(...) function
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/**
+ * @brief  Decode the priority of an interrupt
+ *
+ * @param  Priority           The priority for the interrupt
+ * @param  PriorityGroup      The used priority group
+ * @param  pPreemptPriority   The preemptive priority value (starting from 0)
+ * @param  pSubPriority       The sub priority value (starting from 0)
+ *
+ * Decode an interrupt priority value with the given priority group to
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The priority value can be retrieved with NVIC_GetPriority(...) function
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+
+/* ##################################    SysTick function  ############################################ */
+
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
+
+/**
+ * @brief  Initialize and start the SysTick counter and its interrupt.
+ *
+ * @param   ticks   number of ticks between two interrupts
+ * @return  1 = failed, 0 = successful
+ *
+ * Initialise the system tick timer and its interrupt and start the
+ * system tick timer / counter in free running mode to generate
+ * periodical interrupts.
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->RELOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  SysTick->CURR   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+
+
+
+/* ##################################    Reset function  ############################################ */
+
+/**
+ * @brief  Initiate a system reset request.
+ *
+ * Initiate a system reset request to reset the MCU
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+
+/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
+  Core Debug Interface containing:
+  - Core Debug Receive / Transmit Functions
+  - Core Debug Defines
+  - Core Debug Variables
+*/
+/*@{*/
+
+extern volatile int ITM_RxBuffer;                    /*!< variable to receive characters                             */
+#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/**
+ * @brief  Outputs a character via the ITM channel 0
+ *
+ * @param  ch   character to output
+ * @return      character to output
+ *
+ * The function outputs a character via the ITM channel 0.
+ * The function returns when no debugger is connected that has booked the output.
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
+      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1ul << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/**
+ * @brief  Inputs a character via variable ITM_RxBuffer
+ *
+ * @return      received character, -1 = no character received
+ *
+ * The function inputs a character via variable ITM_RxBuffer.
+ * The function returns when no debugger is connected that has booked the output.
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ */
+static __INLINE int ITM_ReceiveChar (void) {
+  int ch = -1;                               /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+ * @brief  Check if a character via variable ITM_RxBuffer is available
+ *
+ * @return      1 = character available, 0 = no character available
+ *
+ * The function checks  variable ITM_RxBuffer whether a character is available or not.
+ * The function returns '1' if a character is available and '0' if no character is available.
+ */
+static __INLINE int ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/ /* end of group CMSIS_CM3_core_definitions */
+
+#endif /* __CM3_CORE_H__ */
+
+ /**
+  * @}
+  */
+
+/*lint -restore */
diff -r 000000000000 -r d920d64db582 I2S_Example/i2s_irq_test.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/i2s_irq_test.c	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,278 @@
+/***********************************************************************//**
+ * @file        i2s_irq_test.c
+ * @purpose        This example describes how to use I2S transfer in interrupt
+ *                   mode
+ * @version        2.0
+ * @date        21. May. 2010
+ * @author        NXP MCU SW Application Team
+ *---------------------------------------------------------------------
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **********************************************************************/
+#include "lpc17xx_i2s.h"
+#include "lpc17xx_libcfg.h"
+#include "lpc17xx_pinsel.h"
+//#include "lpc17xx_gpdma.h"
+//#include "debug_frmwrk.h"
+#include "lpc17xx_clkpwr.h"
+#include "i2s_irq_test.h"
+#include "mbed.h"
+
+
+
+/* Example group ----------------------------------------------------------- */
+/** @defgroup I2S_IRQ    I2S_IRQ
+ * @ingroup I2S_Examples
+ * @{
+ */
+
+
+/************************** PRIVATE VARIABLES ***********************/
+
+volatile uint8_t  I2STXDone = 0;
+volatile uint8_t  I2SRXDone = 0;
+
+volatile uint32_t *I2STXBuffer = (uint32_t*)(I2S_BUFFER_SRC);
+volatile uint32_t *I2SRXBuffer = (uint32_t *)(I2S_BUFFER_DST);
+
+volatile uint32_t I2SReadLength = 0;
+volatile uint32_t I2SWriteLength = 0;
+
+uint8_t tx_depth_irq = 0;
+uint8_t rx_depth_irq = 0;
+uint8_t dummy=0;
+
+
+/************************** PRIVATE FUNCTIONS *************************/
+void I2S_IRQHandler(void);
+void Buffer_Init(void);
+Bool Buffer_Verify(void);
+void print_menu(void);
+
+/*----------------- INTERRUPT SERVICE ROUTINES --------------------------*/
+/*********************************************************************//**
+ * @brief        I2S IRQ Handler
+ * @param[in]    None
+ * @return         None
+ **********************************************************************/
+/*void I2S_IRQHandler()
+{
+    uint32_t RXLevel = 0;
+
+    //Check RX interrupt
+    if(I2S_GetIRQStatus(LPC_I2S, I2S_RX_MODE))
+    {
+        RXLevel = I2S_GetLevel(LPC_I2S, I2S_RX_MODE);
+        if ( (RXLevel != RXFIFO_EMPTY) && !I2SRXDone )
+        {
+            while ( RXLevel > 0 )
+            {
+                if ( I2SReadLength == BUFFER_SIZE )
+                {
+                    //Stop RX
+                    I2S_Stop(LPC_I2S, I2S_RX_MODE);
+                    // Disable RX
+                    I2S_IRQCmd(LPC_I2S, I2S_RX_MODE, DISABLE);
+                    I2SRXDone = 1;
+                    break;
+                }
+                else
+                {
+                    I2SRXBuffer[I2SReadLength++] = LPC_I2S->I2SRXFIFO;
+                }
+                RXLevel--;
+            }
+        }
+    }
+    return;
+}
+*/
+/*-------------------------PRIVATE FUNCTIONS------------------------------*/
+/*********************************************************************//**
+ * @brief        Initialize buffer
+ * @param[in]    None
+ * @return         None
+ **********************************************************************/
+void Buffer_Init(void) {
+    uint32_t i;
+    for ( i = 0; i < BUFFER_SIZE; i++ )    /* clear buffer */
+    {
+    I2STXBuffer[i] = i |(i << 16);
+    I2SRXBuffer[i] = 0;
+    }
+
+}
+
+/*********************************************************************//**
+ * @brief        Verify buffer
+ * @param[in]    none
+ * @return         TRUE - if two buffers are similar
+ *                 FALSE - if two buffers are different
+ **********************************************************************/
+Bool Buffer_Verify(void) {
+    uint32_t i;
+    uint32_t *pTX = (uint32_t *) &I2STXBuffer[0];
+    uint32_t *pRX = (uint32_t *) &I2SRXBuffer[1];
+    /* Because first element of RX is dummy 0 value, so we just verify
+     * from 2nd element
+     */
+    for (i = 1; i < BUFFER_SIZE; i++) {
+        if (*pTX++ != *pRX++)  {
+            return FALSE;
+        }
+    }
+    return TRUE;
+}
+
+// for mbed
+void mbed_i2s_init(void){
+
+    //GPDMA_Channel_CFG_Type GPDMACfg;    // DMA
+    I2S_MODEConf_Type I2S_ClkConfig;
+    I2S_CFG_Type I2S_ConfigStruct;
+    //I2S_DMAConf_Type I2S_DMAStruct;     // DMA
+    PINSEL_CFG_Type PinCfg;
+
+    // uint32_t i;
+    /* Initialize debug via UART0
+     * 115200bps
+     * 8 data bit
+     * No parity
+     * 1 stop bit
+     * No flow control
+     */
+    // debug_frmwrk_init();
+    // print menu screen
+    // print_menu();
+
+
+    /* Initialize I2S peripheral ------------------------------------*/
+    /* Pin configuration:
+    * Assign:     - P0.4 as I2SRX_CLK  <- No use 
+    *             - P0.5 as I2SRX_WS   <- No use
+    *             - P0.6 as I2SRX_SDA  <- No use
+    *             - P0.7 as I2STX_CLK
+    *             - P0.8 as I2STX_WS
+    *             - P0.9 as I2STX_SDA
+    */
+    PinCfg.Funcnum = 1;
+    PinCfg.OpenDrain = 0;
+    PinCfg.Pinmode = 0;
+    PinCfg.Portnum = 0;
+    //PinCfg.Pinnum = 4;
+    //PINSEL_ConfigPin(&PinCfg);
+    //PinCfg.Pinnum = 5;
+    //PINSEL_ConfigPin(&PinCfg);
+    //PinCfg.Pinnum = 6;
+    //PINSEL_ConfigPin(&PinCfg);
+    PinCfg.Pinnum = 7;
+    PINSEL_ConfigPin(&PinCfg);
+    PinCfg.Pinnum = 8;
+    PINSEL_ConfigPin(&PinCfg);
+    PinCfg.Pinnum = 9;
+    PINSEL_ConfigPin(&PinCfg);
+
+    //Buffer_Init();
+    I2S_Init(LPC_I2S);  
+
+    /* setup:
+     *         - wordwidth: 16 bits
+     *         - stereo mode
+     *         - master mode for I2S_TX and slave for I2S_RX
+     *         - ws_halfperiod is 31
+     *         - not use mute mode
+     *         - use reset and stop mode
+     *         - select the fractional rate divider clock output as the source,
+     *         - disable 4-pin mode
+     *         - MCLK ouput is disable
+     *         - Frequency = 44.1 kHz
+     * Because we use mode I2STXMODE[3:0]= 0000, I2SDAO[5]=0 and
+     * I2SRX[3:0]=0000, I2SDAI[5] = 1. So we have I2SRX_CLK = I2STX_CLK
+     * --> I2SRXBITRATE = 1 (not divide TXCLK to produce RXCLK)
+     */
+    
+    /* Audio Config*/
+    I2S_ConfigStruct.wordwidth = I2S_WORDWIDTH_16;
+    I2S_ConfigStruct.mono = I2S_STEREO;
+    I2S_ConfigStruct.stop = I2S_STOP_ENABLE;
+    I2S_ConfigStruct.reset = I2S_RESET_ENABLE;
+    I2S_ConfigStruct.ws_sel = I2S_SLAVE_MODE;
+    I2S_ConfigStruct.mute = I2S_MUTE_DISABLE;
+    I2S_Config(LPC_I2S,I2S_TX_MODE,&I2S_ConfigStruct);
+    
+    //I2S_ConfigStruct.ws_sel = I2S_SLAVE_MODE;
+    //I2S_Config(LPC_I2S,I2S_RX_MODE,&I2S_ConfigStruct);
+    
+    /* Clock Mode Config*/
+    CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_I2S,CLKPWR_PCLKSEL_CCLK_DIV_4);
+    I2S_ClkConfig.clksel = I2S_CLKSEL_FRDCLK;
+    I2S_ClkConfig.fpin = I2S_4PIN_DISABLE;
+    I2S_ClkConfig.mcena = I2S_MCLK_DISABLE; 
+    I2S_ModeConfig(LPC_I2S,&I2S_ClkConfig,I2S_TX_MODE);
+    //I2S_ModeConfig(LPC_I2S,&I2S_ClkConfig,I2S_RX_MODE);
+
+
+    //I2S_FreqConfig(LPC_I2S, (uint16_t)44100, I2S_TX_MODE);    <- No use bacause I2S_TX is Slave mode
+    I2S_SetBitRate(LPC_I2S, 0, I2S_TX_MODE); //FOR SLAVE MODE TX
+    //I2S_SetBitRate(LPC_I2S, 0, I2S_RX_MODE);
+    
+    I2S_Stop(LPC_I2S, I2S_TX_MODE);
+    //I2S_Stop(LPC_I2S, I2S_RX_MODE);
+    
+
+
+    
+    NVIC_EnableIRQ(I2S_IRQn);
+    
+    /* RX FIFO depth is 1, TX FIFO depth is 8. */
+    I2S_IRQConfig(LPC_I2S,I2S_TX_MODE,8);
+    //I2S_IRQConfig(LPC_I2S,I2S_RX_MODE,1);
+    //I2S_IRQCmd(LPC_I2S,I2S_TX_MODE,ENABLE);
+    
+    
+    
+
+
+    I2S_Start(LPC_I2S);
+    
+}
+
+
+
+
+
+
+
+
+
+
+
+#ifdef  DEBUG
+/*******************************************************************************
+* @brief        Reports the name of the source file and the source line number
+*                 where the CHECK_PARAM error has occurred.
+* @param[in]    file Pointer to the source file name
+* @param[in]    line assert_param error line source number
+* @return        None
+*******************************************************************************/
+void check_failed(uint8_t *file, uint32_t line)
+{
+    /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+    /* Infinite loop */
+    while(1);
+}
+#endif
+
+/*
+ * @}
+ */
diff -r 000000000000 -r d920d64db582 I2S_Example/i2s_irq_test.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/i2s_irq_test.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,55 @@
+#ifndef I2S_IRQ_TEST_H_
+#define I2S_IRQ_TEST_H_
+
+
+#include "lpc_types.h"
+#include "lpc17xx_i2s.h"
+#include "lpc17xx_libcfg.h"
+#include "lpc17xx_pinsel.h"
+//#include "debug_frmwrk.h"
+#include "i2s_irq_test.h"
+
+
+/************************** PRIVATE DEFINITIONS *************************/
+/** Max buffer length */
+#define BUFFER_SIZE         0x400
+/** I2S Buffer Source Address is AHBRAM1_BASE that used for USB RAM purpose, but
+ * it is not used in this example, so this memory section can be used for general purpose
+ * memory
+ */
+#define I2S_BUFFER_SRC      LPC_AHBRAM1_BASE //0x20080000
+/** I2S Buffer Destination Address is (AHBRAM1_BASE + 0x100UL) that used for USB RAM purpose, but
+ * it is not used in this example, so this memory section can be used for general purpose
+ * memory
+ */
+#define I2S_BUFFER_DST      (I2S_BUFFER_SRC+0x1000UL) //0x20081000
+
+#define RXFIFO_EMPTY        0
+#define TXFIFO_FULL         8
+
+extern "C" void I2S_IRQHandler(void);
+
+
+
+extern void Buffer_Init(void);
+extern Bool Buffer_Verify(void);
+extern void print_menu(void);
+extern int c_entry(void);
+extern void mbed_i2s_init(void);
+
+
+extern volatile uint8_t  I2STXDone;
+extern volatile uint8_t  I2SRXDone;
+
+extern volatile uint32_t *I2STXBuffer;
+extern volatile uint32_t *I2SRXBuffer;
+
+extern volatile uint32_t I2SReadLength;
+extern volatile uint32_t I2SWriteLength;
+
+extern uint8_t tx_depth_irq;
+extern uint8_t rx_depth_irq;
+extern uint8_t dummy;
+
+
+#endif
\ No newline at end of file
diff -r 000000000000 -r d920d64db582 I2S_Example/lpc17xx_clkpwr.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/lpc17xx_clkpwr.c	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,338 @@
+/***********************************************************************//**
+ * @file        lpc17xx_clkpwr.c
+ * @brief        Contains all functions support for Clock and Power Control
+ *                 firmware library on LPC17xx
+ * @version        3.0
+ * @date        18. June. 2010
+ * @author        NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup CLKPWR
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_clkpwr.h"
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup CLKPWR_Public_Functions
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief         Set value of each Peripheral Clock Selection
+ * @param[in]    ClkType    Peripheral Clock Selection of each type,
+ *                 should be one of the following:
+ *                - CLKPWR_PCLKSEL_WDT           : WDT
+                - CLKPWR_PCLKSEL_TIMER0       : Timer 0
+                - CLKPWR_PCLKSEL_TIMER1       : Timer 1
+                - CLKPWR_PCLKSEL_UART0       : UART 0
+                - CLKPWR_PCLKSEL_UART1      : UART 1
+                - CLKPWR_PCLKSEL_PWM1       : PWM 1
+                - CLKPWR_PCLKSEL_I2C0       : I2C 0
+                - CLKPWR_PCLKSEL_SPI           : SPI
+                - CLKPWR_PCLKSEL_SSP1       : SSP 1
+                - CLKPWR_PCLKSEL_DAC           : DAC
+                - CLKPWR_PCLKSEL_ADC           : ADC
+                - CLKPWR_PCLKSEL_CAN1          : CAN 1
+                - CLKPWR_PCLKSEL_CAN2          : CAN 2
+                - CLKPWR_PCLKSEL_ACF           : ACF
+                - CLKPWR_PCLKSEL_QEI         : QEI
+                - CLKPWR_PCLKSEL_PCB           : PCB
+                - CLKPWR_PCLKSEL_I2C1       : I2C 1
+                - CLKPWR_PCLKSEL_SSP0       : SSP 0
+                - CLKPWR_PCLKSEL_TIMER2       : Timer 2
+                - CLKPWR_PCLKSEL_TIMER3       : Timer 3
+                - CLKPWR_PCLKSEL_UART2       : UART 2
+                - CLKPWR_PCLKSEL_UART3       : UART 3
+                - CLKPWR_PCLKSEL_I2C2       : I2C 2
+                - CLKPWR_PCLKSEL_I2S           : I2S
+                - CLKPWR_PCLKSEL_RIT           : RIT
+                - CLKPWR_PCLKSEL_SYSCON       : SYSCON
+                - CLKPWR_PCLKSEL_MC         : MC
+
+ * @param[in]    DivVal    Value of divider, should be:
+ *                 - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4
+ *                 - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1
+ *                - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2
+ *
+ * @return none
+ **********************************************************************/
+void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal)
+{
+    uint32_t bitpos;
+
+    bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32);
+
+    /* PCLKSEL0 selected */
+    if (ClkType < 32)
+    {
+        /* Clear two bit at bit position */
+        LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos)));
+
+        /* Set two selected bit */
+        LPC_SC->PCLKSEL0 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
+    }
+    /* PCLKSEL1 selected */
+    else
+    {
+        /* Clear two bit at bit position */
+        LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos));
+
+        /* Set two selected bit */
+        LPC_SC->PCLKSEL1 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
+    }
+}
+
+
+/*********************************************************************//**
+ * @brief        Get current value of each Peripheral Clock Selection
+ * @param[in]    ClkType    Peripheral Clock Selection of each type,
+ *                 should be one of the following:
+ *                - CLKPWR_PCLKSEL_WDT           : WDT
+                - CLKPWR_PCLKSEL_TIMER0       : Timer 0
+                - CLKPWR_PCLKSEL_TIMER1       : Timer 1
+                - CLKPWR_PCLKSEL_UART0       : UART 0
+                - CLKPWR_PCLKSEL_UART1      : UART 1
+                - CLKPWR_PCLKSEL_PWM1       : PWM 1
+                - CLKPWR_PCLKSEL_I2C0       : I2C 0
+                - CLKPWR_PCLKSEL_SPI           : SPI
+                - CLKPWR_PCLKSEL_SSP1       : SSP 1
+                - CLKPWR_PCLKSEL_DAC           : DAC
+                - CLKPWR_PCLKSEL_ADC           : ADC
+                - CLKPWR_PCLKSEL_CAN1          : CAN 1
+                - CLKPWR_PCLKSEL_CAN2          : CAN 2
+                - CLKPWR_PCLKSEL_ACF           : ACF
+                - CLKPWR_PCLKSEL_QEI         : QEI
+                - CLKPWR_PCLKSEL_PCB           : PCB
+                - CLKPWR_PCLKSEL_I2C1       : I2C 1
+                - CLKPWR_PCLKSEL_SSP0       : SSP 0
+                - CLKPWR_PCLKSEL_TIMER2       : Timer 2
+                - CLKPWR_PCLKSEL_TIMER3       : Timer 3
+                - CLKPWR_PCLKSEL_UART2       : UART 2
+                - CLKPWR_PCLKSEL_UART3       : UART 3
+                - CLKPWR_PCLKSEL_I2C2       : I2C 2
+                - CLKPWR_PCLKSEL_I2S           : I2S
+                - CLKPWR_PCLKSEL_RIT           : RIT
+                - CLKPWR_PCLKSEL_SYSCON       : SYSCON
+                - CLKPWR_PCLKSEL_MC         : MC
+
+ * @return        Value of Selected Peripheral Clock Selection
+ **********************************************************************/
+uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType)
+{
+    uint32_t bitpos, retval;
+
+    if (ClkType < 32)
+    {
+        bitpos = ClkType;
+        retval = LPC_SC->PCLKSEL0;
+    }
+    else
+    {
+        bitpos = ClkType - 32;
+        retval = LPC_SC->PCLKSEL1;
+    }
+
+    retval = CLKPWR_PCLKSEL_GET(bitpos, retval);
+    return retval;
+}
+
+
+
+/*********************************************************************//**
+ * @brief         Get current value of each Peripheral Clock
+ * @param[in]    ClkType    Peripheral Clock Selection of each type,
+ *                 should be one of the following:
+ *                - CLKPWR_PCLKSEL_WDT           : WDT
+                - CLKPWR_PCLKSEL_TIMER0       : Timer 0
+                - CLKPWR_PCLKSEL_TIMER1       : Timer 1
+                - CLKPWR_PCLKSEL_UART0       : UART 0
+                - CLKPWR_PCLKSEL_UART1      : UART 1
+                - CLKPWR_PCLKSEL_PWM1       : PWM 1
+                - CLKPWR_PCLKSEL_I2C0       : I2C 0
+                - CLKPWR_PCLKSEL_SPI           : SPI
+                - CLKPWR_PCLKSEL_SSP1       : SSP 1
+                - CLKPWR_PCLKSEL_DAC           : DAC
+                - CLKPWR_PCLKSEL_ADC           : ADC
+                - CLKPWR_PCLKSEL_CAN1          : CAN 1
+                - CLKPWR_PCLKSEL_CAN2          : CAN 2
+                - CLKPWR_PCLKSEL_ACF           : ACF
+                - CLKPWR_PCLKSEL_QEI         : QEI
+                - CLKPWR_PCLKSEL_PCB           : PCB
+                - CLKPWR_PCLKSEL_I2C1       : I2C 1
+                - CLKPWR_PCLKSEL_SSP0       : SSP 0
+                - CLKPWR_PCLKSEL_TIMER2       : Timer 2
+                - CLKPWR_PCLKSEL_TIMER3       : Timer 3
+                - CLKPWR_PCLKSEL_UART2       : UART 2
+                - CLKPWR_PCLKSEL_UART3       : UART 3
+                - CLKPWR_PCLKSEL_I2C2       : I2C 2
+                - CLKPWR_PCLKSEL_I2S           : I2S
+                - CLKPWR_PCLKSEL_RIT           : RIT
+                - CLKPWR_PCLKSEL_SYSCON       : SYSCON
+                - CLKPWR_PCLKSEL_MC         : MC
+
+ * @return        Value of Selected Peripheral Clock
+ **********************************************************************/
+uint32_t CLKPWR_GetPCLK (uint32_t ClkType)
+{
+    uint32_t retval, div;
+
+    retval = SystemCoreClock;
+    div = CLKPWR_GetPCLKSEL(ClkType);
+
+    switch (div)
+    {
+    case 0:
+        div = 4;
+        break;
+
+    case 1:
+        div = 1;
+        break;
+
+    case 2:
+        div = 2;
+        break;
+
+    case 3:
+        div = 8;
+        break;
+    }
+    retval /= div;
+
+    return retval;
+}
+
+
+
+/*********************************************************************//**
+ * @brief         Configure power supply for each peripheral according to NewState
+ * @param[in]    PPType    Type of peripheral used to enable power,
+ *                         should be one of the following:
+ *                 -  CLKPWR_PCONP_PCTIM0         : Timer 0
+                -  CLKPWR_PCONP_PCTIM1         : Timer 1
+                -  CLKPWR_PCONP_PCUART0      : UART 0
+                -  CLKPWR_PCONP_PCUART1       : UART 1
+                -  CLKPWR_PCONP_PCPWM1         : PWM 1
+                -  CLKPWR_PCONP_PCI2C0         : I2C 0
+                -  CLKPWR_PCONP_PCSPI       : SPI
+                -  CLKPWR_PCONP_PCRTC       : RTC
+                -  CLKPWR_PCONP_PCSSP1         : SSP 1
+                -  CLKPWR_PCONP_PCAD           : ADC
+                -  CLKPWR_PCONP_PCAN1       : CAN 1
+                -  CLKPWR_PCONP_PCAN2       : CAN 2
+                -  CLKPWR_PCONP_PCGPIO         : GPIO
+                -  CLKPWR_PCONP_PCRIT         : RIT
+                -  CLKPWR_PCONP_PCMC         : MC
+                -  CLKPWR_PCONP_PCQEI         : QEI
+                -  CLKPWR_PCONP_PCI2C1       : I2C 1
+                -  CLKPWR_PCONP_PCSSP0         : SSP 0
+                -  CLKPWR_PCONP_PCTIM2         : Timer 2
+                -  CLKPWR_PCONP_PCTIM3         : Timer 3
+                -  CLKPWR_PCONP_PCUART2      : UART 2
+                -  CLKPWR_PCONP_PCUART3       : UART 3
+                -  CLKPWR_PCONP_PCI2C2         : I2C 2
+                -  CLKPWR_PCONP_PCI2S       : I2S
+                -  CLKPWR_PCONP_PCGPDMA       : GPDMA
+                -  CLKPWR_PCONP_PCENET         : Ethernet
+                -  CLKPWR_PCONP_PCUSB       : USB
+ *
+ * @param[in]    NewState    New state of Peripheral Power, should be:
+ *                 - ENABLE    : Enable power for this peripheral
+ *                 - DISABLE    : Disable power for this peripheral
+ *
+ * @return none
+ **********************************************************************/
+void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
+{
+    if (NewState == ENABLE)
+    {
+        LPC_SC->PCONP |= PPType & CLKPWR_PCONP_BITMASK;
+    }
+    else if (NewState == DISABLE)
+    {
+        LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK;
+    }
+}
+
+
+/*********************************************************************//**
+ * @brief         Enter Sleep mode with co-operated instruction by the Cortex-M3.
+ * @param[in]    None
+ * @return        None
+ **********************************************************************/
+void CLKPWR_Sleep(void)
+{
+    LPC_SC->PCON = 0x00;
+    /* Sleep Mode*/
+    __WFI();
+}
+
+
+/*********************************************************************//**
+ * @brief         Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
+ * @param[in]    None
+ * @return        None
+ **********************************************************************/
+void CLKPWR_DeepSleep(void)
+{
+    /* Deep-Sleep Mode, set SLEEPDEEP bit */
+    SCB->SCR = 0x4;
+    LPC_SC->PCON = 0x8;
+    /* Deep Sleep Mode*/
+    __WFI();
+}
+
+
+/*********************************************************************//**
+ * @brief         Enter Power Down mode with co-operated instruction by the Cortex-M3.
+ * @param[in]    None
+ * @return        None
+ **********************************************************************/
+void CLKPWR_PowerDown(void)
+{
+    /* Deep-Sleep Mode, set SLEEPDEEP bit */
+    SCB->SCR = 0x4;
+    LPC_SC->PCON = 0x09;
+    /* Power Down Mode*/
+    __WFI();
+}
+
+
+/*********************************************************************//**
+ * @brief         Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
+ * @param[in]    None
+ * @return        None
+ **********************************************************************/
+void CLKPWR_DeepPowerDown(void)
+{
+    /* Deep-Sleep Mode, set SLEEPDEEP bit */
+    SCB->SCR = 0x4;
+    LPC_SC->PCON = 0x03;
+    /* Deep Power Down Mode*/
+    __WFI();
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff -r 000000000000 -r d920d64db582 I2S_Example/lpc17xx_clkpwr.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/lpc17xx_clkpwr.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,394 @@
+/***********************************************************************//**
+ * @file        lpc17xx_clkpwr.h
+ * @brief        Contains all macro definitions and function prototypes
+ *                 support for Clock and Power Control firmware library on LPC17xx
+ * @version        2.0
+ * @date        21. May. 2010
+ * @author        NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup CLKPWR CLKPWR
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_CLKPWR_H_
+#define LPC17XX_CLKPWR_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
+ * @{
+ */
+
+/**********************************************************************
+ * Peripheral Clock Selection Definitions
+ **********************************************************************/
+/** Peripheral clock divider bit position for WDT */
+#define    CLKPWR_PCLKSEL_WDT          ((uint32_t)(0))
+/** Peripheral clock divider bit position for TIMER0 */
+#define    CLKPWR_PCLKSEL_TIMER0          ((uint32_t)(2))
+/** Peripheral clock divider bit position for TIMER1 */
+#define    CLKPWR_PCLKSEL_TIMER1          ((uint32_t)(4))
+/** Peripheral clock divider bit position for UART0 */
+#define    CLKPWR_PCLKSEL_UART0          ((uint32_t)(6))
+/** Peripheral clock divider bit position for UART1 */
+#define    CLKPWR_PCLKSEL_UART1          ((uint32_t)(8))
+/** Peripheral clock divider bit position for PWM1 */
+#define    CLKPWR_PCLKSEL_PWM1          ((uint32_t)(12))
+/** Peripheral clock divider bit position for I2C0 */
+#define    CLKPWR_PCLKSEL_I2C0          ((uint32_t)(14))
+/** Peripheral clock divider bit position for SPI */
+#define    CLKPWR_PCLKSEL_SPI          ((uint32_t)(16))
+/** Peripheral clock divider bit position for SSP1 */
+#define    CLKPWR_PCLKSEL_SSP1          ((uint32_t)(20))
+/** Peripheral clock divider bit position for DAC */
+#define    CLKPWR_PCLKSEL_DAC          ((uint32_t)(22))
+/** Peripheral clock divider bit position for ADC */
+#define    CLKPWR_PCLKSEL_ADC          ((uint32_t)(24))
+/** Peripheral clock divider bit position for CAN1 */
+#define    CLKPWR_PCLKSEL_CAN1         ((uint32_t)(26))
+/** Peripheral clock divider bit position for CAN2 */
+#define    CLKPWR_PCLKSEL_CAN2         ((uint32_t)(28))
+/** Peripheral clock divider bit position for ACF */
+#define    CLKPWR_PCLKSEL_ACF          ((uint32_t)(30))
+/** Peripheral clock divider bit position for QEI */
+#define    CLKPWR_PCLKSEL_QEI          ((uint32_t)(32))
+/** Peripheral clock divider bit position for PCB */
+#define    CLKPWR_PCLKSEL_PCB          ((uint32_t)(36))
+/** Peripheral clock divider bit position for  I2C1 */
+#define    CLKPWR_PCLKSEL_I2C1          ((uint32_t)(38))
+/** Peripheral clock divider bit position for SSP0 */
+#define    CLKPWR_PCLKSEL_SSP0          ((uint32_t)(42))
+/** Peripheral clock divider bit position for TIMER2 */
+#define    CLKPWR_PCLKSEL_TIMER2          ((uint32_t)(44))
+/** Peripheral clock divider bit position for  TIMER3 */
+#define    CLKPWR_PCLKSEL_TIMER3          ((uint32_t)(46))
+/** Peripheral clock divider bit position for UART2 */
+#define    CLKPWR_PCLKSEL_UART2          ((uint32_t)(48))
+/** Peripheral clock divider bit position for UART3 */
+#define    CLKPWR_PCLKSEL_UART3          ((uint32_t)(50))
+/** Peripheral clock divider bit position for I2C2 */
+#define    CLKPWR_PCLKSEL_I2C2          ((uint32_t)(52))
+/** Peripheral clock divider bit position for I2S */
+#define    CLKPWR_PCLKSEL_I2S          ((uint32_t)(54))
+/** Peripheral clock divider bit position for RIT */
+#define    CLKPWR_PCLKSEL_RIT          ((uint32_t)(58))
+/** Peripheral clock divider bit position for SYSCON */
+#define    CLKPWR_PCLKSEL_SYSCON          ((uint32_t)(60))
+/** Peripheral clock divider bit position for MC */
+#define    CLKPWR_PCLKSEL_MC              ((uint32_t)(62))
+
+/** Macro for Peripheral Clock Selection register bit values
+ * Note: When CCLK_DIV_8, Peripheral&#65533;s clock is selected to
+ * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
+ * when &#65533;11&#65533;selects PCLK_xyz = CCLK/6 */
+/* Peripheral clock divider is set to 4 from CCLK */
+#define    CLKPWR_PCLKSEL_CCLK_DIV_4  ((uint32_t)(0))
+/** Peripheral clock divider is the same with CCLK */
+#define    CLKPWR_PCLKSEL_CCLK_DIV_1  ((uint32_t)(1))
+/** Peripheral clock divider is set to 2 from CCLK */
+#define    CLKPWR_PCLKSEL_CCLK_DIV_2  ((uint32_t)(2))
+
+
+/********************************************************************
+* Power Control for Peripherals Definitions
+**********************************************************************/
+/** Timer/Counter 0 power/clock control bit */
+#define     CLKPWR_PCONP_PCTIM0    ((uint32_t)(1<<1))
+/* Timer/Counter 1 power/clock control bit */
+#define     CLKPWR_PCONP_PCTIM1    ((uint32_t)(1<<2))
+/** UART0 power/clock control bit */
+#define     CLKPWR_PCONP_PCUART0      ((uint32_t)(1<<3))
+/** UART1 power/clock control bit */
+#define     CLKPWR_PCONP_PCUART1      ((uint32_t)(1<<4))
+/** PWM1 power/clock control bit */
+#define     CLKPWR_PCONP_PCPWM1    ((uint32_t)(1<<6))
+/** The I2C0 interface power/clock control bit */
+#define     CLKPWR_PCONP_PCI2C0    ((uint32_t)(1<<7))
+/** The SPI interface power/clock control bit */
+#define     CLKPWR_PCONP_PCSPI      ((uint32_t)(1<<8))
+/** The RTC power/clock control bit */
+#define     CLKPWR_PCONP_PCRTC      ((uint32_t)(1<<9))
+/** The SSP1 interface power/clock control bit */
+#define     CLKPWR_PCONP_PCSSP1    ((uint32_t)(1<<10))
+/** A/D converter 0 (ADC0) power/clock control bit */
+#define     CLKPWR_PCONP_PCAD      ((uint32_t)(1<<12))
+/** CAN Controller 1 power/clock control bit */
+#define     CLKPWR_PCONP_PCAN1      ((uint32_t)(1<<13))
+/** CAN Controller 2 power/clock control bit */
+#define     CLKPWR_PCONP_PCAN2     ((uint32_t)(1<<14))
+/** GPIO power/clock control bit */
+#define    CLKPWR_PCONP_PCGPIO     ((uint32_t)(1<<15))
+/** Repetitive Interrupt Timer power/clock control bit */
+#define    CLKPWR_PCONP_PCRIT         ((uint32_t)(1<<16))
+/** Motor Control PWM */
+#define CLKPWR_PCONP_PCMC         ((uint32_t)(1<<17))
+/** Quadrature Encoder Interface power/clock control bit */
+#define CLKPWR_PCONP_PCQEI         ((uint32_t)(1<<18))
+/** The I2C1 interface power/clock control bit */
+#define     CLKPWR_PCONP_PCI2C1      ((uint32_t)(1<<19))
+/** The SSP0 interface power/clock control bit */
+#define     CLKPWR_PCONP_PCSSP0    ((uint32_t)(1<<21))
+/** Timer 2 power/clock control bit */
+#define     CLKPWR_PCONP_PCTIM2    ((uint32_t)(1<<22))
+/** Timer 3 power/clock control bit */
+#define     CLKPWR_PCONP_PCTIM3    ((uint32_t)(1<<23))
+/** UART 2 power/clock control bit */
+#define     CLKPWR_PCONP_PCUART2      ((uint32_t)(1<<24))
+/** UART 3 power/clock control bit */
+#define     CLKPWR_PCONP_PCUART3      ((uint32_t)(1<<25))
+/** I2C interface 2 power/clock control bit */
+#define     CLKPWR_PCONP_PCI2C2    ((uint32_t)(1<<26))
+/** I2S interface power/clock control bit*/
+#define     CLKPWR_PCONP_PCI2S      ((uint32_t)(1<<27))
+/** GP DMA function power/clock control bit*/
+#define     CLKPWR_PCONP_PCGPDMA      ((uint32_t)(1<<29))
+/** Ethernet block power/clock control bit*/
+#define     CLKPWR_PCONP_PCENET    ((uint32_t)(1<<30))
+/** USB interface power/clock control bit*/
+#define     CLKPWR_PCONP_PCUSB      ((uint32_t)(1<<31))
+
+
+/**
+ * @}
+ */
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Clock Source Select Register
+ **********************************************************************/
+/** Internal RC oscillator */
+#define CLKPWR_CLKSRCSEL_CLKSRC_IRC            ((uint32_t)(0x00))
+/** Main oscillator */
+#define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC        ((uint32_t)(0x01))
+/** RTC oscillator */
+#define CLKPWR_CLKSRCSEL_CLKSRC_RTC            ((uint32_t)(0x02))
+/** Clock source selection bit mask */
+#define CLKPWR_CLKSRCSEL_BITMASK            ((uint32_t)(0x03))
+
+/*********************************************************************//**
+ * Macro defines for Clock Output Configuration Register
+ **********************************************************************/
+/* Clock Output Configuration register definition */
+/** Selects the CPU clock as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU        ((uint32_t)(0x00))
+/** Selects the main oscillator as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC    ((uint32_t)(0x01))
+/** Selects the Internal RC oscillator as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC        ((uint32_t)(0x02))
+/** Selects the USB clock as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB        ((uint32_t)(0x03))
+/** Selects the RTC oscillator as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC        ((uint32_t)(0x04))
+/** Integer value to divide the output clock by, minus one */
+#define CLKPWR_CLKOUTCFG_CLKOUTDIV(n)        ((uint32_t)((n&0x0F)<<4))
+/** CLKOUT enable control */
+#define CLKPWR_CLKOUTCFG_CLKOUT_EN            ((uint32_t)(1<<8))
+/** CLKOUT activity indication */
+#define CLKPWR_CLKOUTCFG_CLKOUT_ACT            ((uint32_t)(1<<9))
+/** Clock source selection bit mask */
+#define CLKPWR_CLKOUTCFG_BITMASK            ((uint32_t)(0x3FF))
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Control Register
+ **********************************************************************/
+/** PLL 0 control enable */
+#define CLKPWR_PLL0CON_ENABLE        ((uint32_t)(0x01))
+/** PLL 0 control connect */
+#define CLKPWR_PLL0CON_CONNECT        ((uint32_t)(0x02))
+/** PLL 0 control bit mask */
+#define CLKPWR_PLL0CON_BITMASK        ((uint32_t)(0x03))
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Configuration Register
+ **********************************************************************/
+/** PLL 0 Configuration MSEL field */
+#define CLKPWR_PLL0CFG_MSEL(n)        ((uint32_t)(n&0x7FFF))
+/** PLL 0 Configuration NSEL field */
+#define CLKPWR_PLL0CFG_NSEL(n)        ((uint32_t)((n<<16)&0xFF0000))
+/** PLL 0 Configuration bit mask */
+#define CLKPWR_PLL0CFG_BITMASK        ((uint32_t)(0xFF7FFF))
+
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Status Register
+ **********************************************************************/
+/** PLL 0 MSEL value */
+#define CLKPWR_PLL0STAT_MSEL(n)        ((uint32_t)(n&0x7FFF))
+/** PLL NSEL get value  */
+#define CLKPWR_PLL0STAT_NSEL(n)        ((uint32_t)((n>>16)&0xFF))
+/** PLL status enable bit */
+#define CLKPWR_PLL0STAT_PLLE        ((uint32_t)(1<<24))
+/** PLL status Connect bit */
+#define CLKPWR_PLL0STAT_PLLC        ((uint32_t)(1<<25))
+/** PLL status lock */
+#define CLKPWR_PLL0STAT_PLOCK        ((uint32_t)(1<<26))
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Feed Register
+ **********************************************************************/
+/** PLL0 Feed bit mask */
+#define CLKPWR_PLL0FEED_BITMASK            ((uint32_t)0xFF)
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Control Register
+ **********************************************************************/
+/** USB PLL control enable */
+#define CLKPWR_PLL1CON_ENABLE        ((uint32_t)(0x01))
+/** USB PLL control connect */
+#define CLKPWR_PLL1CON_CONNECT        ((uint32_t)(0x02))
+/** USB PLL control bit mask */
+#define CLKPWR_PLL1CON_BITMASK        ((uint32_t)(0x03))
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Configuration Register
+ **********************************************************************/
+/** USB PLL MSEL set value */
+#define CLKPWR_PLL1CFG_MSEL(n)        ((uint32_t)(n&0x1F))
+/** USB PLL PSEL set value */
+#define CLKPWR_PLL1CFG_PSEL(n)        ((uint32_t)((n&0x03)<<5))
+/** USB PLL configuration bit mask */
+#define CLKPWR_PLL1CFG_BITMASK        ((uint32_t)(0x7F))
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Status Register
+ **********************************************************************/
+/** USB PLL MSEL get value  */
+#define CLKPWR_PLL1STAT_MSEL(n)        ((uint32_t)(n&0x1F))
+/** USB PLL PSEL get value  */
+#define CLKPWR_PLL1STAT_PSEL(n)        ((uint32_t)((n>>5)&0x03))
+/** USB PLL status enable bit */
+#define CLKPWR_PLL1STAT_PLLE        ((uint32_t)(1<<8))
+/** USB PLL status Connect bit */
+#define CLKPWR_PLL1STAT_PLLC        ((uint32_t)(1<<9))
+/** USB PLL status lock */
+#define CLKPWR_PLL1STAT_PLOCK        ((uint32_t)(1<<10))
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Feed Register
+ **********************************************************************/
+/** PLL1 Feed bit mask */
+#define CLKPWR_PLL1FEED_BITMASK        ((uint32_t)0xFF)
+
+/*********************************************************************//**
+ * Macro defines for CPU Clock Configuration Register
+ **********************************************************************/
+/** CPU Clock configuration bit mask */
+#define CLKPWR_CCLKCFG_BITMASK        ((uint32_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro defines for USB Clock Configuration Register
+ **********************************************************************/
+/** USB Clock Configuration bit mask */
+#define CLKPWR_USBCLKCFG_BITMASK    ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro defines for IRC Trim Register
+ **********************************************************************/
+/** IRC Trim bit mask */
+#define CLKPWR_IRCTRIM_BITMASK        ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro defines for Peripheral Clock Selection Register 0 and 1
+ **********************************************************************/
+/** Peripheral Clock Selection 0 mask bit */
+#define CLKPWR_PCLKSEL0_BITMASK        ((uint32_t)(0xFFF3F3FF))
+/** Peripheral Clock Selection 1 mask bit */
+#define CLKPWR_PCLKSEL1_BITMASK        ((uint32_t)(0xFCF3F0F3))
+/** Macro to set peripheral clock of each type
+ * p: position of two bits that hold divider of peripheral clock
+ * n: value of divider of peripheral clock  to be set */
+#define CLKPWR_PCLKSEL_SET(p,n)        _SBF(p,n)
+/** Macro to mask peripheral clock of each type */
+#define CLKPWR_PCLKSEL_BITMASK(p)    _SBF(p,0x03)
+/** Macro to get peripheral clock of each type */
+#define CLKPWR_PCLKSEL_GET(p, n)    ((uint32_t)((n>>p)&0x03))
+
+/*********************************************************************//**
+ * Macro defines for Power Mode Control Register
+ **********************************************************************/
+/** Power mode control bit 0 */
+#define CLKPWR_PCON_PM0            ((uint32_t)(1<<0))
+/** Power mode control bit 1 */
+#define CLKPWR_PCON_PM1            ((uint32_t)(1<<1))
+/** Brown-Out Reduced Power Mode */
+#define CLKPWR_PCON_BODPDM        ((uint32_t)(1<<2))
+/** Brown-Out Global Disable */
+#define CLKPWR_PCON_BOGD        ((uint32_t)(1<<3))
+/** Brown Out Reset Disable */
+#define CLKPWR_PCON_BORD        ((uint32_t)(1<<4))
+/** Sleep Mode entry flag */
+#define CLKPWR_PCON_SMFLAG        ((uint32_t)(1<<8))
+/** Deep Sleep entry flag */
+#define CLKPWR_PCON_DSFLAG        ((uint32_t)(1<<9))
+/** Power-down entry flag */
+#define CLKPWR_PCON_PDFLAG        ((uint32_t)(1<<10))
+/** Deep Power-down entry flag */
+#define CLKPWR_PCON_DPDFLAG        ((uint32_t)(1<<11))
+
+/*********************************************************************//**
+ * Macro defines for Power Control for Peripheral Register
+ **********************************************************************/
+/** Power Control for Peripherals bit mask */
+#define CLKPWR_PCONP_BITMASK    0xEFEFF7DE
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
+ * @{
+ */
+
+void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
+uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
+uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
+void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
+void CLKPWR_Sleep(void);
+void CLKPWR_DeepSleep(void);
+void CLKPWR_PowerDown(void);
+void CLKPWR_DeepPowerDown(void);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_CLKPWR_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff -r 000000000000 -r d920d64db582 I2S_Example/lpc17xx_i2s.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/lpc17xx_i2s.c	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,650 @@
+/***********************************************************************//**
+ * @file        lpc17xx_i2s.c
+ * @brief        Contains all functions support for I2S firmware library on LPC17xx
+ * @version        3.0
+ * @date        18. June. 2010
+ * @author        NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup I2S
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+//#include "mbed.h"
+#include "lpc17xx_i2s.h"
+#include "lpc17xx_clkpwr.h"
+#include "mbed.h"
+
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _I2S
+
+/* Private Functions ---------------------------------------------------------- */
+
+static uint8_t i2s_GetWordWidth(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+static uint8_t i2s_GetChannel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+
+/********************************************************************//**
+ * @brief        Get I2S wordwidth value
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    TRMode is the I2S mode, should be:
+ *                 - I2S_TX_MODE = 0: transmit mode
+ *                 - I2S_RX_MODE = 1: receive mode
+ * @return         The wordwidth value, should be: 8,16 or 32
+ *********************************************************************/
+static uint8_t i2s_GetWordWidth(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) {
+    uint8_t value;
+
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+    CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+    if (TRMode == I2S_TX_MODE) {
+        value = (I2Sx->I2SDAO) & 0x03; /* get wordwidth bit */
+    } else {
+        value = (I2Sx->I2SDAI) & 0x03; /* get wordwidth bit */
+    }
+    switch (value) {
+    case I2S_WORDWIDTH_8:
+        return 8;
+    case I2S_WORDWIDTH_16:
+        return 16;
+    default:
+        return 32;
+    }
+}
+
+/********************************************************************//**
+ * @brief        Get I2S channel value
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    TRMode is the I2S mode, should be:
+ *                 - I2S_TX_MODE = 0: transmit mode
+ *                 - I2S_RX_MODE = 1: receive mode
+ * @return         The channel value, should be: 1(mono) or 2(stereo)
+ *********************************************************************/
+static uint8_t i2s_GetChannel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) {
+    uint8_t value;
+
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+    CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+    if (TRMode == I2S_TX_MODE) {
+        value = (I2Sx->I2SDAO) & 0x04; /* get bit[2] */
+    } else {
+        value = (I2Sx->I2SDAI) & 0x04; /* get bit[2] */
+    }
+        if(value == I2S_MONO) return 1;
+          return 2;
+}
+
+/* End of Private Functions --------------------------------------------------- */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup I2S_Public_Functions
+ * @{
+ */
+
+/********************************************************************//**
+ * @brief        Initialize I2S
+ *                     - Turn on power and clock
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @return         none
+ *********************************************************************/
+void I2S_Init(LPC_I2S_TypeDef *I2Sx) {
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+
+    // Turn on power and clock
+    CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCI2S, ENABLE);
+    LPC_I2S->I2SDAI = LPC_I2S->I2SDAO = 0x00;
+}
+
+/********************************************************************//**
+ * @brief        Configuration I2S, setting:
+ *                     - master/slave mode
+ *                     - wordwidth value
+ *                     - channel mode
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    TRMode transmit/receive mode, should be:
+ *                     - I2S_TX_MODE = 0: transmit mode
+ *                     - I2S_RX_MODE = 1: receive mode
+ * @param[in]    ConfigStruct pointer to I2S_CFG_Type structure
+ *              which will be initialized.
+ * @return         none
+ *********************************************************************/
+void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct)
+{
+    uint32_t bps, config;
+
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+
+    CHECK_PARAM(PARAM_I2S_WORDWIDTH(ConfigStruct->wordwidth));
+    CHECK_PARAM(PARAM_I2S_CHANNEL(ConfigStruct->mono));
+    CHECK_PARAM(PARAM_I2S_STOP(ConfigStruct->stop));
+    CHECK_PARAM(PARAM_I2S_RESET(ConfigStruct->reset));
+    CHECK_PARAM(PARAM_I2S_WS_SEL(ConfigStruct->ws_sel));
+    CHECK_PARAM(PARAM_I2S_MUTE(ConfigStruct->mute));
+
+    /* Setup clock */
+    bps = (ConfigStruct->wordwidth +1)*8;
+
+    /* Calculate audio config */
+    config = (bps - 1)<<6 | (ConfigStruct->ws_sel)<<5 | (ConfigStruct->reset)<<4 |
+        (ConfigStruct->stop)<<3 | (ConfigStruct->mono)<<2 | (ConfigStruct->wordwidth);
+
+    if(TRMode == I2S_RX_MODE){
+        LPC_I2S->I2SDAI = config;
+    }else{
+        LPC_I2S->I2SDAO = config;
+    }
+}
+
+/********************************************************************//**
+ * @brief        DeInitial both I2S transmit or receive
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @return         none
+ *********************************************************************/
+void I2S_DeInit(LPC_I2S_TypeDef *I2Sx) {
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+
+    // Turn off power and clock
+    CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCI2S, DISABLE);
+}
+
+/********************************************************************//**
+ * @brief        Get I2S Buffer Level
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    TRMode Transmit/receive mode, should be:
+ *                     - I2S_TX_MODE = 0: transmit mode
+ *                     - I2S_RX_MODE = 1: receive mode
+ * @return         current level of Transmit/Receive Buffer
+ *********************************************************************/
+uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode)
+{
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+    CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+    if(TRMode == I2S_TX_MODE)
+    {
+        return ((I2Sx->I2SSTATE >> 16) & 0xFF);
+    }
+    else
+    {
+        return ((I2Sx->I2SSTATE >> 8) & 0xFF);
+    }
+}
+
+/********************************************************************//**
+ * @brief        I2S Start: clear all STOP,RESET and MUTE bit, ready to operate
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @return         none
+ *********************************************************************/
+void I2S_Start(LPC_I2S_TypeDef *I2Sx)
+{
+    //Clear STOP,RESET and MUTE bit
+    I2Sx->I2SDAO &= ~I2S_DAI_RESET;
+    I2Sx->I2SDAI &= ~I2S_DAI_RESET;
+    I2Sx->I2SDAO &= ~I2S_DAI_STOP;
+    I2Sx->I2SDAI &= ~I2S_DAI_STOP;
+    I2Sx->I2SDAO &= ~I2S_DAI_MUTE;
+}
+
+/********************************************************************//**
+ * @brief        I2S Send data
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    BufferData pointer to uint32_t is the data will be send
+ * @return         none
+ *********************************************************************/
+void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData) {
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+
+    I2Sx->I2STXFIFO = BufferData;
+}
+
+/********************************************************************//**
+ * @brief        I2S Receive Data
+ * @param[in]    I2Sx pointer to LPC_I2S_TypeDef
+ * @return         received value
+ *********************************************************************/
+uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx) {
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+
+    return (I2Sx->I2SRXFIFO);
+
+}
+
+/********************************************************************//**
+ * @brief        I2S Pause
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    TRMode is transmit/receive mode, should be:
+ *                 - I2S_TX_MODE = 0: transmit mode
+ *                 - I2S_RX_MODE = 1: receive mode
+ * @return         none
+ *********************************************************************/
+void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) {
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+    CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+    if (TRMode == I2S_TX_MODE) //Transmit mode
+    {
+        I2Sx->I2SDAO |= I2S_DAO_STOP;
+    } else //Receive mode
+    {
+        I2Sx->I2SDAI |= I2S_DAI_STOP;
+    }
+}
+
+/********************************************************************//**
+ * @brief        I2S Mute
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    TRMode is transmit/receive mode, should be:
+ *                 - I2S_TX_MODE = 0: transmit mode
+ *                 - I2S_RX_MODE = 1: receive mode
+ * @return         none
+ *********************************************************************/
+void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) {
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+    CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+    if (TRMode == I2S_TX_MODE) //Transmit mode
+    {
+        I2Sx->I2SDAO |= I2S_DAO_MUTE;
+    } else //Receive mode
+    {
+        I2Sx->I2SDAI |= I2S_DAI_MUTE;
+    }
+}
+
+/********************************************************************//**
+ * @brief        I2S Stop
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    TRMode is transmit/receive mode, should be:
+ *                 - I2S_TX_MODE = 0: transmit mode
+ *                 - I2S_RX_MODE = 1: receive mode
+ * @return         none
+ *********************************************************************/
+void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) {
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+    CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+    if (TRMode == I2S_TX_MODE) //Transmit mode
+    {
+        I2Sx->I2SDAO &= ~I2S_DAO_MUTE;
+        I2Sx->I2SDAO |= I2S_DAO_STOP;
+        I2Sx->I2SDAO |= I2S_DAO_RESET;
+    } else //Receive mode
+    {
+        I2Sx->I2SDAI |= I2S_DAI_STOP;
+        I2Sx->I2SDAI |= I2S_DAI_RESET;
+    }
+}
+
+/********************************************************************//**
+ * @brief        Set frequency for I2S
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    Freq is the frequency for I2S will be set. It can range
+ *                 from 16-96 kHz(16, 22.05, 32, 44.1, 48, 96kHz)
+ * @param[in]    TRMode is transmit/receive mode, should be:
+ *                 - I2S_TX_MODE = 0: transmit mode
+ *                 - I2S_RX_MODE = 1: receive mode
+ * @return         Status: ERROR or SUCCESS
+ *********************************************************************/
+Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode) {
+
+    /* Calculate bit rate
+     * The formula is:
+     *      bit_rate = channel*wordwidth - 1
+     * 48kHz sample rate for 16 bit stereo date requires
+     * a bit rate of 48000*16*2=1536MHz (MCLK)
+     */
+    uint32_t i2sPclk;
+    uint64_t divider;
+    uint8_t bitrate, channel, wordwidth;
+    uint32_t x, y;
+    uint16_t dif;
+    uint16_t error;
+    uint8_t x_divide, y_divide=0;
+    uint16_t ErrorOptimal = 0xFFFF;
+
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+    CHECK_PARAM(PRAM_I2S_FREQ(Freq));
+    CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+    i2sPclk = CLKPWR_GetPCLK(CLKPWR_PCLKSEL_I2S);
+    printf("I2S_PCLK = %dHz\r\n",i2sPclk);
+    if(TRMode == I2S_TX_MODE)
+    {
+        channel = i2s_GetChannel(I2Sx,I2S_TX_MODE);
+        wordwidth = i2s_GetWordWidth(I2Sx,I2S_TX_MODE);
+    }
+    else
+    {
+        channel = i2s_GetChannel(I2Sx,I2S_RX_MODE);
+        wordwidth = i2s_GetWordWidth(I2Sx,I2S_RX_MODE);
+    }
+    bitrate = channel * wordwidth - 1;
+    if (TRMode == I2S_TX_MODE)// Transmitter
+    {
+        I2Sx->I2STXBITRATE = bitrate;
+    } else //Receiver
+    {
+        I2Sx->I2SRXBITRATE = bitrate;
+    }
+    printf("TX CHANNEL= %d\r\n",i2s_GetChannel(I2Sx,I2S_TX_MODE));
+    printf("TX WORDWIDTH= %dbits \r\n",i2s_GetWordWidth(I2Sx,I2S_TX_MODE));
+    printf("I2STXBITRATE= %d,bitrate= %d \r\n",I2Sx->I2STXBITRATE,bitrate);
+    /* Calculate X and Y divider
+     * The MCLK rate for the I2S transmitter is determined by the value
+     * in the I2STXRATE/I2SRXRATE register. The required I2STXRATE/I2SRXRATE
+     * setting depends on the desired audio sample rate desired, the format
+     * (stereo/mono) used, and the data size.
+     * The formula is:
+     *         I2S_MCLK = PCLK * (X/Y) / 2
+     * We have:
+     *         I2S_MCLK = Freq * bit_rate;
+     * So: (X/Y) = (Freq * bit_rate)/PCLK*2
+     * We use a loop function to chose the most suitable X,Y value
+     */
+
+    divider = ((uint64_t)(Freq *( bitrate+1)/* * 2*/)<<16) / i2sPclk;
+    for (y = 255; y > 0; y--) {
+        x = y * divider;
+        dif = x & 0xFFFF;
+        if(dif>0x8000) error = 0x10000-dif;
+        else error = dif;
+        if (error == 0)
+        {
+            y_divide = y;
+            break;
+        }
+        else if (error < ErrorOptimal)
+        {
+            ErrorOptimal = error;
+            y_divide = y;
+        }
+    }
+    //y_divide--;//for test
+    x_divide = (y_divide * Freq *( bitrate+1)* 2)/i2sPclk;
+    if (TRMode == I2S_TX_MODE)// Transmitter
+    {
+        I2Sx->I2STXRATE = y_divide | (x_divide << 8);
+    } else //Receiver
+    {
+        I2Sx->I2SRXRATE = y_divide | (x_divide << 8);
+    }
+    
+    printf("I2STXRATE=%d, x_divide=%d, y_divide=%d \r\n",I2Sx->I2STXRATE,x_divide,y_divide);
+    return SUCCESS;
+}
+
+/********************************************************************//**
+ * @brief        I2S set bitrate
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    bitrate value will be set, it can be calculate as follows:
+ *                     bitrate = channel * wordwidth - 1
+ *                 bitrate value should be in range: 0 .. 63
+ * @param[in]    TRMode is transmit/receive mode, should be:
+ *                 - I2S_TX_MODE = 0: transmit mode
+ *                 - I2S_RX_MODE = 1: receive mode
+ * @return         none
+ *********************************************************************/
+void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode)
+{
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+    CHECK_PARAM(PARAM_I2S_BITRATE(bitrate));
+    CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+    if(TRMode == I2S_TX_MODE)
+    {
+        I2Sx->I2STXBITRATE = bitrate;
+    }
+    else
+    {
+        I2Sx->I2SRXBITRATE = bitrate;
+    }
+}
+
+/********************************************************************//**
+ * @brief        Configuration operating mode for I2S
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    ModeConfig pointer to I2S_MODEConf_Type will be used to
+ *                 configure
+ * @param[in]    TRMode is transmit/receive mode, should be:
+ *                 - I2S_TX_MODE = 0: transmit mode
+ *                 - I2S_RX_MODE = 1: receive mode
+ * @return         none
+ *********************************************************************/
+void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig,
+        uint8_t TRMode)
+{
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+    CHECK_PARAM(PARAM_I2S_CLKSEL(ModeConfig->clksel));
+    CHECK_PARAM(PARAM_I2S_4PIN(ModeConfig->fpin));
+    CHECK_PARAM(PARAM_I2S_MCLK(ModeConfig->mcena));
+    CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+    if (TRMode == I2S_TX_MODE) {
+        I2Sx->I2STXMODE &= ~0x0F; //clear bit 3:0 in I2STXMODE register
+        if (ModeConfig->clksel == I2S_CLKSEL_MCLK) {
+            I2Sx->I2STXMODE |= 0x02;
+        }
+        if (ModeConfig->fpin == I2S_4PIN_ENABLE) {
+            I2Sx->I2STXMODE |= (1 << 2);
+        }
+        if (ModeConfig->mcena == I2S_MCLK_ENABLE) {
+            I2Sx->I2STXMODE |= (1 << 3);
+        }
+    } else {
+        I2Sx->I2SRXMODE &= ~0x0F; //clear bit 3:0 in I2STXMODE register
+        if (ModeConfig->clksel == I2S_CLKSEL_MCLK) {
+            I2Sx->I2SRXMODE |= 0x02;
+        }
+        if (ModeConfig->fpin == I2S_4PIN_ENABLE) {
+            I2Sx->I2SRXMODE |= (1 << 2);
+        }
+        if (ModeConfig->mcena == I2S_MCLK_ENABLE) {
+            I2Sx->I2SRXMODE |= (1 << 3);
+        }
+    }
+}
+
+/********************************************************************//**
+ * @brief        Configure DMA operation for I2S
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    DMAConfig pointer to I2S_DMAConf_Type will be used to configure
+ * @param[in]    TRMode is transmit/receive mode, should be:
+ *                 - I2S_TX_MODE = 0: transmit mode
+ *                 - I2S_RX_MODE = 1: receive mode
+ * @return         none
+ *********************************************************************/
+void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig,
+        uint8_t TRMode)
+{
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+    CHECK_PARAM(PARAM_I2S_DMA(DMAConfig->DMAIndex));
+    CHECK_PARAM(PARAM_I2S_DMA_DEPTH(DMAConfig->depth));
+    CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+    if (TRMode == I2S_RX_MODE) {
+        if (DMAConfig->DMAIndex == I2S_DMA_1) {
+            LPC_I2S->I2SDMA1 = (DMAConfig->depth) << 8;
+        } else {
+            LPC_I2S->I2SDMA2 = (DMAConfig->depth) << 8;
+        }
+    } else {
+        if (DMAConfig->DMAIndex == I2S_DMA_1) {
+            LPC_I2S->I2SDMA1 = (DMAConfig->depth) << 16;
+        } else {
+            LPC_I2S->I2SDMA2 = (DMAConfig->depth) << 16;
+        }
+    }
+}
+
+/********************************************************************//**
+ * @brief        Enable/Disable DMA operation for I2S
+ * @param[in]    I2Sx: I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    DMAIndex chose what DMA is used, should be:
+ *                 - I2S_DMA_1 = 0: DMA1
+ *                 - I2S_DMA_2 = 1: DMA2
+ * @param[in]    TRMode is transmit/receive mode, should be:
+ *                 - I2S_TX_MODE = 0: transmit mode
+ *                 - I2S_RX_MODE = 1: receive mode
+ * @param[in]    NewState is new state of DMA operation, should be:
+ *                 - ENABLE
+ *                 - DISABLE
+ * @return         none
+ *********************************************************************/
+void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex, uint8_t TRMode,
+        FunctionalState NewState)
+{
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+    CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+    CHECK_PARAM(PARAM_I2S_DMA(DMAIndex));
+    CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+    if (TRMode == I2S_RX_MODE) {
+        if (DMAIndex == I2S_DMA_1) {
+            if (NewState == ENABLE)
+                I2Sx->I2SDMA1 |= 0x01;
+            else
+                I2Sx->I2SDMA1 &= ~0x01;
+        } else {
+            if (NewState == ENABLE)
+                I2Sx->I2SDMA2 |= 0x01;
+            else
+                I2Sx->I2SDMA2 &= ~0x01;
+        }
+    } else {
+        if (DMAIndex == I2S_DMA_1) {
+            if (NewState == ENABLE)
+                I2Sx->I2SDMA1 |= 0x02;
+            else
+                I2Sx->I2SDMA1 &= ~0x02;
+        } else {
+            if (NewState == ENABLE)
+                I2Sx->I2SDMA2 |= 0x02;
+            else
+                I2Sx->I2SDMA2 &= ~0x02;
+        }
+    }
+}
+
+/********************************************************************//**
+ * @brief        Configure IRQ for I2S
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    TRMode is transmit/receive mode, should be:
+ *                 - I2S_TX_MODE = 0: transmit mode
+ *                 - I2S_RX_MODE = 1: receive mode
+ * @param[in]    level is the FIFO level that triggers IRQ request
+ * @return         none
+ *********************************************************************/
+void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level) {
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+    CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+    CHECK_PARAM(PARAM_I2S_IRQ_LEVEL(level));
+
+    if (TRMode == I2S_RX_MODE) {
+        I2Sx->I2SIRQ |= (level << 8);
+    } else {
+        I2Sx->I2SIRQ |= (level << 16);
+    }
+}
+
+/********************************************************************//**
+ * @brief        Enable/Disable IRQ for I2S
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    TRMode is transmit/receive mode, should be:
+ *                 - I2S_TX_MODE = 0: transmit mode
+ *                 - I2S_RX_MODE = 1: receive mode
+ * @param[in]    NewState is new state of DMA operation, should be:
+ *                 - ENABLE
+ *                 - DISABLE
+ * @return         none
+ *********************************************************************/
+void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, FunctionalState NewState) {
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+    CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+    if (TRMode == I2S_RX_MODE) {
+        if (NewState == ENABLE)
+            I2Sx->I2SIRQ |= 0x01;
+        else
+            I2Sx->I2SIRQ &= ~0x01;
+        //Enable DMA
+
+    } else {
+        if (NewState == ENABLE)
+            I2Sx->I2SIRQ |= 0x02;
+        else
+            I2Sx->I2SIRQ &= ~0x02;
+    }
+}
+
+/********************************************************************//**
+ * @brief        Get I2S interrupt status
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    TRMode is transmit/receive mode, should be:
+ *                 - I2S_TX_MODE = 0: transmit mode
+ *                 - I2S_RX_MODE = 1: receive mode
+ * @return         FunctionState    should be:
+ *                 - ENABLE: interrupt is enable
+ *                 - DISABLE: interrupt is disable
+ *********************************************************************/
+FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode)
+{
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+    if(TRMode == I2S_TX_MODE)
+        return (FunctionalState)((I2Sx->I2SIRQ >> 1)&0x01);
+    else
+        return (FunctionalState)((I2Sx->I2SIRQ)&0x01);
+}
+
+/********************************************************************//**
+ * @brief        Get I2S interrupt depth
+ * @param[in]    I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in]    TRMode is transmit/receive mode, should be:
+ *                 - I2S_TX_MODE = 0: transmit mode
+ *                 - I2S_RX_MODE = 1: receive mode
+ * @return         depth of FIFO level on which to create an irq request
+ *********************************************************************/
+uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode)
+{
+    CHECK_PARAM(PARAM_I2Sx(I2Sx));
+    if(TRMode == I2S_TX_MODE)
+        return (((I2Sx->I2SIRQ)>>16)&0xFF);
+    else
+        return (((I2Sx->I2SIRQ)>>8)&0xFF);
+}
+/**
+ * @}
+ */
+
+#endif /* _I2S */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff -r 000000000000 -r d920d64db582 I2S_Example/lpc17xx_i2s.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/lpc17xx_i2s.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,372 @@
+/***********************************************************************//**
+ * @file        lpc17xx_i2s.h
+ * @brief        Contains all macro definitions and function prototypes
+ *                 support for I2S firmware library on LPC17xx
+ * @version        3.0
+ * @date        18. June. 2010
+ * @author        NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup I2S I2S
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_I2S_H_
+#define LPC17XX_I2S_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup I2S_Public_Macros I2S Public Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ * I2S configuration parameter defines
+ **********************************************************************/
+/** I2S Wordwidth bit */
+#define I2S_WORDWIDTH_8        ((uint32_t)(0))
+#define I2S_WORDWIDTH_16    ((uint32_t)(1))
+#define I2S_WORDWIDTH_32    ((uint32_t)(3))
+/** I2S Channel bit */
+#define I2S_STEREO            ((uint32_t)(0))
+#define I2S_MONO            ((uint32_t)(1))
+/** I2S Master/Slave mode bit */
+#define I2S_MASTER_MODE        ((uint8_t)(0))
+#define I2S_SLAVE_MODE        ((uint8_t)(1))
+/** I2S Stop bit */
+#define I2S_STOP_ENABLE        ((uint8_t)(1))
+#define I2S_STOP_DISABLE    ((uint8_t)(0))
+/** I2S Reset bit */
+#define I2S_RESET_ENABLE    ((uint8_t)(1))
+#define I2S_RESET_DISABLE    ((uint8_t)(0))
+/** I2S Mute bit */
+#define I2S_MUTE_ENABLE        ((uint8_t)(1))
+#define I2S_MUTE_DISABLE    ((uint8_t)(0))
+/** I2S Transmit/Receive bit */
+#define I2S_TX_MODE            ((uint8_t)(0))
+#define I2S_RX_MODE            ((uint8_t)(1))
+/** I2S Clock Select bit */
+#define I2S_CLKSEL_FRDCLK    ((uint8_t)(0))
+#define I2S_CLKSEL_MCLK        ((uint8_t)(2))
+/** I2S 4-pin Mode bit */
+#define I2S_4PIN_ENABLE     ((uint8_t)(1))
+#define I2S_4PIN_DISABLE     ((uint8_t)(0))
+/** I2S MCLK Enable bit */
+#define I2S_MCLK_ENABLE        ((uint8_t)(1))
+#define I2S_MCLK_DISABLE    ((uint8_t)(0))
+/** I2S select DMA bit */
+#define I2S_DMA_1            ((uint8_t)(0))
+#define I2S_DMA_2            ((uint8_t)(1))
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup I2S_Private_Macros I2S Private Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ * Macro defines for DAO-Digital Audio Output register
+ **********************************************************************/
+/** I2S wordwide - the number of bytes in data*/
+#define I2S_DAO_WORDWIDTH_8        ((uint32_t)(0))        /** 8 bit    */
+#define I2S_DAO_WORDWIDTH_16    ((uint32_t)(1))        /** 16 bit    */
+#define I2S_DAO_WORDWIDTH_32    ((uint32_t)(3))        /** 32 bit    */
+/** I2S control mono or stereo format */
+#define I2S_DAO_MONO            ((uint32_t)(1<<2))
+/** I2S control stop mode */
+#define I2S_DAO_STOP            ((uint32_t)(1<<3))
+/** I2S control reset mode */
+#define I2S_DAO_RESET            ((uint32_t)(1<<4))
+/** I2S control master/slave mode */
+#define I2S_DAO_SLAVE            ((uint32_t)(1<<5))
+/** I2S word select half period minus one */
+#define I2S_DAO_WS_HALFPERIOD(n)    ((uint32_t)(n<<6))
+/** I2S control mute mode */
+#define I2S_DAO_MUTE            ((uint32_t)(1<<15))
+
+/*********************************************************************//**
+ * Macro defines for DAI-Digital Audio Input register
+**********************************************************************/
+/** I2S wordwide - the number of bytes in data*/
+#define I2S_DAI_WORDWIDTH_8        ((uint32_t)(0))        /** 8 bit    */
+#define I2S_DAI_WORDWIDTH_16    ((uint32_t)(1))        /** 16 bit    */
+#define I2S_DAI_WORDWIDTH_32    ((uint32_t)(3))        /** 32 bit    */
+/** I2S control mono or stereo format */
+#define I2S_DAI_MONO            ((uint32_t)(1<<2))
+/** I2S control stop mode */
+#define I2S_DAI_STOP            ((uint32_t)(1<<3))
+/** I2S control reset mode */
+#define I2S_DAI_RESET            ((uint32_t)(1<<4))
+/** I2S control master/slave mode */
+#define I2S_DAI_SLAVE            ((uint32_t)(1<<5))
+/** I2S word select half period minus one (9 bits)*/
+#define I2S_DAI_WS_HALFPERIOD(n)    ((uint32_t)((n&0x1FF)<<6))
+/** I2S control mute mode */
+#define I2S_DAI_MUTE            ((uint32_t)(1<<15))
+
+/*********************************************************************//**
+ * Macro defines for STAT register (Status Feedback register)
+**********************************************************************/
+/** I2S Status Receive or Transmit Interrupt */
+#define I2S_STATE_IRQ        ((uint32_t)(1))
+/** I2S Status Receive or Transmit DMA1 */
+#define I2S_STATE_DMA1        ((uint32_t)(1<<1))
+/** I2S Status Receive or Transmit DMA2 */
+#define I2S_STATE_DMA2        ((uint32_t)(1<<2))
+/** I2S Status Current level of the Receive FIFO (5 bits)*/
+#define I2S_STATE_RX_LEVEL(n)    ((uint32_t)((n&1F)<<8))
+/** I2S Status Current level of the Transmit FIFO (5 bits)*/
+#define I2S_STATE_TX_LEVEL(n)    ((uint32_t)((n&1F)<<16))
+
+/*********************************************************************//**
+ * Macro defines for DMA1 register (DMA1 Configuration register)
+**********************************************************************/
+/** I2S control DMA1 for I2S receive */
+#define I2S_DMA1_RX_ENABLE        ((uint32_t)(1))
+/** I2S control DMA1 for I2S transmit */
+#define I2S_DMA1_TX_ENABLE        ((uint32_t)(1<<1))
+/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
+#define I2S_DMA1_RX_DEPTH(n)    ((uint32_t)((n&0x1F)<<8))
+/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
+#define I2S_DMA1_TX_DEPTH(n)    ((uint32_t)((n&0x1F)<<16))
+
+/*********************************************************************//**
+ * Macro defines for DMA2 register (DMA2 Configuration register)
+**********************************************************************/
+/** I2S control DMA2 for I2S receive */
+#define I2S_DMA2_RX_ENABLE        ((uint32_t)(1))
+/** I2S control DMA1 for I2S transmit */
+#define I2S_DMA2_TX_ENABLE        ((uint32_t)(1<<1))
+/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
+#define I2S_DMA2_RX_DEPTH(n)    ((uint32_t)((n&0x1F)<<8))
+/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
+#define I2S_DMA2_TX_DEPTH(n)    ((uint32_t)((n&0x1F)<<16))
+
+/*********************************************************************//**
+* Macro defines for IRQ register (Interrupt Request Control register)
+**********************************************************************/
+/** I2S control I2S receive interrupt */
+#define I2S_IRQ_RX_ENABLE        ((uint32_t)(1))
+/** I2S control I2S transmit interrupt */
+#define I2S_IRQ_TX_ENABLE        ((uint32_t)(1<<1))
+/** I2S set the FIFO level on which to create an irq request */
+#define I2S_IRQ_RX_DEPTH(n)        ((uint32_t)((n&0x1F)<<8))
+/** I2S set the FIFO level on which to create an irq request */
+#define I2S_IRQ_TX_DEPTH(n)        ((uint32_t)((n&0x1F)<<16))
+
+/********************************************************************************//**
+ * Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
+*********************************************************************************/
+/** I2S Transmit MCLK rate denominator */
+#define I2S_TXRATE_Y_DIVIDER(n)    ((uint32_t)(n&0xFF))
+/** I2S Transmit MCLK rate denominator */
+#define I2S_TXRATE_X_DIVIDER(n)    ((uint32_t)((n&0xFF)<<8))
+/** I2S Receive MCLK rate denominator */
+#define I2S_RXRATE_Y_DIVIDER(n)    ((uint32_t)(n&0xFF))
+/** I2S Receive MCLK rate denominator */
+#define I2S_RXRATE_X_DIVIDER(n)    ((uint32_t)((n&0xFF)<<8))
+
+/*************************************************************************************//**
+ * Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
+**************************************************************************************/
+#define I2S_TXBITRATE(n)    ((uint32_t)(n&0x3F))
+#define I2S_RXBITRATE(n)    ((uint32_t)(n&0x3F))
+
+/**********************************************************************************//**
+ * Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
+************************************************************************************/
+/** I2S Transmit select clock source (2 bits)*/
+#define I2S_TXMODE_CLKSEL(n)    ((uint32_t)(n&0x03))
+/** I2S Transmit control 4-pin mode */
+#define I2S_TXMODE_4PIN_ENABLE    ((uint32_t)(1<<2))
+/** I2S Transmit control the TX_MCLK output */
+#define I2S_TXMODE_MCENA        ((uint32_t)(1<<3))
+/** I2S Receive select clock source */
+#define I2S_RXMODE_CLKSEL(n)    ((uint32_t)(n&0x03))
+/** I2S Receive control 4-pin mode */
+#define I2S_RXMODE_4PIN_ENABLE    ((uint32_t)(1<<2))
+/** I2S Receive control the TX_MCLK output */
+#define I2S_RXMODE_MCENA        ((uint32_t)(1<<3))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid I2S peripheral */
+#define PARAM_I2Sx(n)    (((uint32_t *)n)==((uint32_t *)LPC_I2S))
+/** Macro to check Data to send valid */
+#define PRAM_I2S_FREQ(freq)        ((freq>=16000)&&(freq <= 96000))
+/* Macro check I2S word width type */
+#define PARAM_I2S_WORDWIDTH(n)    ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\
+||(n==I2S_WORDWIDTH_32))
+/* Macro check I2S channel type */
+#define PARAM_I2S_CHANNEL(n)    ((n==I2S_STEREO)||(n==I2S_MONO))
+/* Macro check I2S master/slave mode */
+#define PARAM_I2S_WS_SEL(n)        ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE))
+/* Macro check I2S stop mode */
+#define PARAM_I2S_STOP(n)    ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE))
+/* Macro check I2S reset mode */
+#define PARAM_I2S_RESET(n)    ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE))
+/* Macro check I2S reset mode */
+#define PARAM_I2S_MUTE(n)    ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE))
+/* Macro check I2S transmit/receive mode */
+#define PARAM_I2S_TRX(n)         ((n==I2S_TX_MODE)||(n==I2S_RX_MODE))
+/* Macro check I2S clock select mode */
+#define PARAM_I2S_CLKSEL(n)        ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK))
+/* Macro check I2S 4-pin mode */
+#define PARAM_I2S_4PIN(n)    ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE))
+/* Macro check I2S MCLK mode */
+#define PARAM_I2S_MCLK(n)    ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE))
+/* Macro check I2S DMA mode */
+#define PARAM_I2S_DMA(n)        ((n==I2S_DMA_1)||(n==I2S_DMA_2))
+/* Macro check I2S DMA depth value */
+#define PARAM_I2S_DMA_DEPTH(n)    ((n>=0)||(n<=31))
+/* Macro check I2S irq level value */
+#define PARAM_I2S_IRQ_LEVEL(n)    ((n>=0)||(n<=31))
+/* Macro check I2S half-period value */
+#define PARAM_I2S_HALFPERIOD(n)    ((n>0)&&(n<512))
+/* Macro check I2S bit-rate value */
+#define PARAM_I2S_BITRATE(n)    ((n>=0)&&(n<=63))
+/**
+ * @}
+ */
+
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup I2S_Public_Types I2S Public Types
+ * @{
+ */
+
+/**
+ * @brief I2S configuration structure definition
+ */
+typedef struct {
+    uint8_t wordwidth;        /** the number of bytes in data as follow:
+                            -I2S_WORDWIDTH_8: 8 bit data
+                            -I2S_WORDWIDTH_16: 16 bit data
+                            -I2S_WORDWIDTH_32: 32 bit data */
+    uint8_t    mono;             /** Set mono/stereo mode, should be:
+                            - I2S_STEREO: stereo mode
+                            - I2S_MONO: mono mode */
+    uint8_t stop;            /** Disables accesses on FIFOs, should be:
+                            - I2S_STOP_ENABLE: enable stop mode
+                            - I2S_STOP_DISABLE: disable stop mode */
+    uint8_t reset;            /** Asynchronously reset tje transmit channel and FIFO, should be:
+                            - I2S_RESET_ENABLE: enable reset mode
+                            - I2S_RESET_DISABLE: disable reset mode */
+    uint8_t ws_sel;            /** Set Master/Slave mode, should be:
+                            - I2S_MASTER_MODE: I2S master mode
+                            - I2S_SLAVE_MODE: I2S slave mode */
+    uint8_t mute;            /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
+                            - I2S_MUTE_ENABLE: enable mute mode
+                            - I2S_MUTE_DISABLE: disable mute mode */
+    uint8_t Reserved0[2];
+} I2S_CFG_Type;
+
+/**
+ * @brief I2S DMA configuration structure definition
+ */
+typedef struct {
+    uint8_t DMAIndex;        /** Select DMA1 or DMA2, should be:
+                            - I2S_DMA_1: DMA1
+                            - I2S_DMA_2: DMA2 */
+    uint8_t depth;            /** FIFO level that triggers a DMA request */
+    uint8_t Reserved0[2];
+}I2S_DMAConf_Type;
+
+/**
+ * @brief I2S mode configuration structure definition
+ */
+typedef struct{
+    uint8_t clksel;            /** Clock source selection, should be:
+                            - I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output
+                            - I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */
+    uint8_t fpin;            /** Select four pin mode, should be:
+                            - I2S_4PIN_ENABLE: 4-pin enable
+                            - I2S_4PIN_DISABLE: 4-pin disable */
+    uint8_t mcena;            /** Select MCLK mode, should be:
+                            - I2S_MCLK_ENABLE: MCLK enable for output
+                            - I2S_MCLK_DISABLE: MCLK disable for output */
+    uint8_t Reserved;
+}I2S_MODEConf_Type;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup I2S_Public_Functions I2S Public Functions
+ * @{
+ */
+/* I2S Init/DeInit functions ---------*/
+void I2S_Init(LPC_I2S_TypeDef *I2Sx);
+void I2S_DeInit(LPC_I2S_TypeDef *I2Sx);
+
+/* I2S configuration functions --------*/
+void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);
+Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode);
+void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode);
+void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);
+uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+
+/* I2S operate functions -------------*/
+void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData);
+uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx);
+void I2S_Start(LPC_I2S_TypeDef *I2Sx);
+void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+
+/* I2S DMA functions ----------------*/
+void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);
+void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
+
+/* I2S IRQ functions ----------------*/
+void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState);
+void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level);
+FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
+uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC17XX_SSP_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff -r 000000000000 -r d920d64db582 I2S_Example/lpc17xx_libcfg.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/lpc17xx_libcfg.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,143 @@
+/***********************************************************************//**
+ * @file        lpc17xx_libcfg.h
+ * @purpose        Library configuration file
+ * @version        2.0
+ * @date        21. May. 2010
+ * @author        NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+#ifndef LPC17XX_LIBCFG_H_
+#define LPC17XX_LIBCFG_H_
+
+#include "lpc_types.h"
+
+
+/************************** DEBUG MODE DEFINITIONS *********************************/
+/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
+   the "CHECK_PARAM" macro in the FW library code */
+
+#define DEBUG
+
+
+/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
+
+/* Comment the line below to disable the specific peripheral inclusion */
+
+/* DEBUG_FRAMWORK ------------------------------ */
+#define _DBGFWK
+
+/* GPIO ------------------------------- */
+//#define _GPIO
+
+/* EXTI ------------------------------- */
+//#define _EXTI
+
+/* UART ------------------------------- */
+#define _UART
+#define _UART0
+//#define _UART1
+//#define _UART2
+//#define _UART3
+
+/* SPI ------------------------------- */
+//#define _SPI
+
+/* SSP ------------------------------- */
+//#define _SSP
+//#define _SSP0
+//#define _SSP1
+
+/* SYSTICK --------------------------- */
+//#define _SYSTICK
+
+/* I2C ------------------------------- */
+//#define _I2C
+//#define _I2C0
+//#define _I2C1
+//#define _I2C2
+
+/* TIMER ------------------------------- */
+//#define _TIM
+
+/* WDT ------------------------------- */
+//#define _WDT
+
+
+/* GPDMA ------------------------------- */
+//#define _GPDMA
+
+
+/* DAC ------------------------------- */
+//#define _DAC
+
+/* DAC ------------------------------- */
+//#define _ADC
+
+
+/* PWM ------------------------------- */
+//#define _PWM
+//#define _PWM1
+
+/* RTC ------------------------------- */
+//#define _RTC
+
+/* I2S ------------------------------- */
+#define _I2S
+
+/* USB device ------------------------------- */
+//#define _USBDEV
+//#define _USB_DMA
+
+/* QEI ------------------------------- */
+//#define _QEI
+
+/* MCPWM ------------------------------- */
+//#define _MCPWM
+
+/* CAN--------------------------------*/
+//#define _CAN
+
+/* RIT ------------------------------- */
+//#define _RIT
+
+/* EMAC ------------------------------ */
+//#define _EMAC
+
+/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
+
+#ifdef  DEBUG
+/*******************************************************************************
+* @brief        The CHECK_PARAM macro is used for function's parameters check.
+*                 It is used only if the library is compiled in DEBUG mode.
+* @param[in]    expr - If expr is false, it calls check_failed() function
+*                        which reports the name of the source file and the source
+*                        line number of the call that failed.
+*                    - If expr is true, it returns no value.
+* @return        None
+*******************************************************************************/
+#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
+#else
+#define CHECK_PARAM(expr)
+#endif /* DEBUG */
+
+
+
+/************************** GLOBAL/PUBLIC FUNCTION DECLARATION *********************************/
+
+#ifdef  DEBUG
+void check_failed(uint8_t *file, uint32_t line);
+#endif
+
+
+#endif /* LPC17XX_LIBCFG_H_ */
diff -r 000000000000 -r d920d64db582 I2S_Example/lpc17xx_libcfg_default.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/lpc17xx_libcfg_default.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,170 @@
+/***********************************************************************//**
+ * @file        lpc17xx_libcfg_default.h
+ * @brief        Default Library configuration header file
+ * @version        2.0
+ * @date        21. May. 2010
+ * @author        NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Library Configuration group ----------------------------------------------------------- */
+/** @defgroup LIBCFG_DEFAULT LIBCFG_DEFAULT
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_LIBCFG_DEFAULT_H_
+#define LPC17XX_LIBCFG_DEFAULT_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc_types.h"
+
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup LIBCFG_DEFAULT_Public_Macros LIBCFG_DEFAULT Public Macros
+ * @{
+ */
+
+/************************** DEBUG MODE DEFINITIONS *********************************/
+/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
+   the "CHECK_PARAM" macro in the FW library code */
+
+#define DEBUG
+
+
+/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
+/* Comment the line below to disable the specific peripheral inclusion */
+
+/* DEBUG_FRAMWORK ------------------------------ */
+#define _DBGFWK
+
+/* GPIO ------------------------------- */
+#define _GPIO
+
+/* EXTI ------------------------------- */
+#define _EXTI
+
+/* UART ------------------------------- */
+#define _UART
+#define _UART0
+#define _UART1
+#define _UART2
+#define _UART3
+
+/* SPI ------------------------------- */
+#define _SPI
+
+/* SYSTICK --------------------------- */
+#define _SYSTICK
+
+/* SSP ------------------------------- */
+#define _SSP
+#define _SSP0
+#define _SSP1
+
+
+/* I2C ------------------------------- */
+#define _I2C
+#define _I2C0
+#define _I2C1
+#define _I2C2
+
+/* TIMER ------------------------------- */
+#define _TIM
+
+/* WDT ------------------------------- */
+#define _WDT
+
+
+/* GPDMA ------------------------------- */
+#define _GPDMA
+
+
+/* DAC ------------------------------- */
+#define _DAC
+
+/* DAC ------------------------------- */
+#define _ADC
+
+
+/* PWM ------------------------------- */
+#define _PWM
+#define _PWM1
+
+/* RTC ------------------------------- */
+#define _RTC
+
+/* I2S ------------------------------- */
+#define _I2S
+
+/* USB device ------------------------------- */
+#define _USBDEV
+#define _USB_DMA
+
+/* QEI ------------------------------- */
+#define _QEI
+
+/* MCPWM ------------------------------- */
+#define _MCPWM
+
+/* CAN--------------------------------*/
+#define _CAN
+
+/* RIT ------------------------------- */
+#define _RIT
+
+/* EMAC ------------------------------ */
+#define _EMAC
+
+/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
+
+#ifdef  DEBUG
+/*******************************************************************************
+* @brief        The CHECK_PARAM macro is used for function's parameters check.
+*                 It is used only if the library is compiled in DEBUG mode.
+* @param[in]    expr - If expr is false, it calls check_failed() function
+*                        which reports the name of the source file and the source
+*                        line number of the call that failed.
+*                    - If expr is true, it returns no value.
+* @return        None
+*******************************************************************************/
+#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
+#else
+#define CHECK_PARAM(expr)
+#endif /* DEBUG */
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup LIBCFG_DEFAULT_Public_Functions LIBCFG_DEFAULT Public Functions
+ * @{
+ */
+
+#ifdef  DEBUG
+void check_failed(uint8_t *file, uint32_t line);
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* LPC17XX_LIBCFG_DEFAULT_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff -r 000000000000 -r d920d64db582 I2S_Example/lpc17xx_pinsel.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/lpc17xx_pinsel.c	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,306 @@
+/***********************************************************************//**
+ * @file        lpc17xx_pinsel.c
+ * @brief        Contains all functions support for Pin connect block firmware
+ *                 library on LPC17xx
+ * @version        2.0
+ * @date        21. May. 2010
+ * @author        NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup PINSEL
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_pinsel.h"
+
+/* Public Functions ----------------------------------------------------------- */
+
+static void set_PinFunc ( uint8_t portnum, uint8_t pinnum, uint8_t funcnum);
+static void set_ResistorMode ( uint8_t portnum, uint8_t pinnum, uint8_t modenum);
+static void set_OpenDrainMode( uint8_t portnum, uint8_t pinnum, uint8_t modenum);
+
+/*********************************************************************//**
+ * @brief         Setup the pin selection function
+ * @param[in]    portnum PORT number,
+ *                 should be one of the following:
+ *                 - PINSEL_PORT_0    : Port 0
+ *                 - PINSEL_PORT_1    : Port 1
+ *                 - PINSEL_PORT_2    : Port 2
+ *                 - PINSEL_PORT_3    : Port 3
+ *
+ * @param[in]    pinnum    Pin number,
+ *                 should be one of the following:
+                - PINSEL_PIN_0 : Pin 0
+                - PINSEL_PIN_1 : Pin 1
+                - PINSEL_PIN_2 : Pin 2
+                - PINSEL_PIN_3 : Pin 3
+                - PINSEL_PIN_4 : Pin 4
+                - PINSEL_PIN_5 : Pin 5
+                - PINSEL_PIN_6 : Pin 6
+                - PINSEL_PIN_7 : Pin 7
+                - PINSEL_PIN_8 : Pin 8
+                - PINSEL_PIN_9 : Pin 9
+                - PINSEL_PIN_10 : Pin 10
+                - PINSEL_PIN_11 : Pin 11
+                - PINSEL_PIN_12 : Pin 12
+                - PINSEL_PIN_13 : Pin 13
+                - PINSEL_PIN_14 : Pin 14
+                - PINSEL_PIN_15 : Pin 15
+                - PINSEL_PIN_16 : Pin 16
+                - PINSEL_PIN_17 : Pin 17
+                - PINSEL_PIN_18 : Pin 18
+                - PINSEL_PIN_19 : Pin 19
+                - PINSEL_PIN_20 : Pin 20
+                - PINSEL_PIN_21 : Pin 21
+                - PINSEL_PIN_22 : Pin 22
+                - PINSEL_PIN_23 : Pin 23
+                - PINSEL_PIN_24 : Pin 24
+                - PINSEL_PIN_25 : Pin 25
+                - PINSEL_PIN_26 : Pin 26
+                - PINSEL_PIN_27 : Pin 27
+                - PINSEL_PIN_28 : Pin 28
+                - PINSEL_PIN_29 : Pin 29
+                - PINSEL_PIN_30 : Pin 30
+                - PINSEL_PIN_31 : Pin 31
+
+ * @param[in]     funcnum Function number,
+ *                 should be one of the following:
+ *                - PINSEL_FUNC_0 : default function
+ *                - PINSEL_FUNC_1 : first alternate function
+ *                - PINSEL_FUNC_2 : second alternate function
+ *                - PINSEL_FUNC_3 : third alternate function
+ *
+ * @return         None
+ **********************************************************************/
+static void set_PinFunc ( uint8_t portnum, uint8_t pinnum, uint8_t funcnum)
+{
+    uint32_t pinnum_t = pinnum;
+    uint32_t pinselreg_idx = 2 * portnum;
+    uint32_t *pPinCon = (uint32_t *)&LPC_PINCON->PINSEL0;
+
+    if (pinnum_t >= 16) {
+        pinnum_t -= 16;
+        pinselreg_idx++;
+    }
+    *(uint32_t *)(pPinCon + pinselreg_idx) &= ~(0x03UL << (pinnum_t * 2));
+    *(uint32_t *)(pPinCon + pinselreg_idx) |= ((uint32_t)funcnum) << (pinnum_t * 2);
+}
+
+/*********************************************************************//**
+ * @brief         Setup resistor mode for each pin
+ * @param[in]    portnum PORT number,
+ *                 should be one of the following:
+ *                 - PINSEL_PORT_0    : Port 0
+ *                 - PINSEL_PORT_1    : Port 1
+ *                 - PINSEL_PORT_2    : Port 2
+ *                 - PINSEL_PORT_3    : Port 3
+ * @param[in]    pinnum    Pin number,
+ *                 should be one of the following:
+                - PINSEL_PIN_0 : Pin 0
+                - PINSEL_PIN_1 : Pin 1
+                - PINSEL_PIN_2 : Pin 2
+                - PINSEL_PIN_3 : Pin 3
+                - PINSEL_PIN_4 : Pin 4
+                - PINSEL_PIN_5 : Pin 5
+                - PINSEL_PIN_6 : Pin 6
+                - PINSEL_PIN_7 : Pin 7
+                - PINSEL_PIN_8 : Pin 8
+                - PINSEL_PIN_9 : Pin 9
+                - PINSEL_PIN_10 : Pin 10
+                - PINSEL_PIN_11 : Pin 11
+                - PINSEL_PIN_12 : Pin 12
+                - PINSEL_PIN_13 : Pin 13
+                - PINSEL_PIN_14 : Pin 14
+                - PINSEL_PIN_15 : Pin 15
+                - PINSEL_PIN_16 : Pin 16
+                - PINSEL_PIN_17 : Pin 17
+                - PINSEL_PIN_18 : Pin 18
+                - PINSEL_PIN_19 : Pin 19
+                - PINSEL_PIN_20 : Pin 20
+                - PINSEL_PIN_21 : Pin 21
+                - PINSEL_PIN_22 : Pin 22
+                - PINSEL_PIN_23 : Pin 23
+                - PINSEL_PIN_24 : Pin 24
+                - PINSEL_PIN_25 : Pin 25
+                - PINSEL_PIN_26 : Pin 26
+                - PINSEL_PIN_27 : Pin 27
+                - PINSEL_PIN_28 : Pin 28
+                - PINSEL_PIN_29 : Pin 29
+                - PINSEL_PIN_30 : Pin 30
+                - PINSEL_PIN_31 : Pin 31
+
+ * @param[in]     modenum: Mode number,
+ *                 should be one of the following:
+                - PINSEL_PINMODE_PULLUP    : Internal pull-up resistor
+                - PINSEL_PINMODE_TRISTATE : Tri-state
+                - PINSEL_PINMODE_PULLDOWN : Internal pull-down resistor
+
+ * @return         None
+ **********************************************************************/
+void set_ResistorMode ( uint8_t portnum, uint8_t pinnum, uint8_t modenum)
+{
+    uint32_t pinnum_t = pinnum;
+    uint32_t pinmodereg_idx = 2 * portnum;
+    uint32_t *pPinCon = (uint32_t *)&LPC_PINCON->PINMODE0;
+
+    if (pinnum_t >= 16) {
+        pinnum_t -= 16;
+        pinmodereg_idx++ ;
+    }
+
+    *(uint32_t *)(pPinCon + pinmodereg_idx) &= ~(0x03UL << (pinnum_t * 2));
+    *(uint32_t *)(pPinCon + pinmodereg_idx) |= ((uint32_t)modenum) << (pinnum_t * 2);
+}
+
+/*********************************************************************//**
+ * @brief         Setup Open drain mode for each pin
+ * @param[in]    portnum PORT number,
+ *                 should be one of the following:
+ *                 - PINSEL_PORT_0    : Port 0
+ *                 - PINSEL_PORT_1    : Port 1
+ *                 - PINSEL_PORT_2    : Port 2
+ *                 - PINSEL_PORT_3    : Port 3
+ *
+ * @param[in]    pinnum    Pin number,
+ *                 should be one of the following:
+                - PINSEL_PIN_0 : Pin 0
+                - PINSEL_PIN_1 : Pin 1
+                - PINSEL_PIN_2 : Pin 2
+                - PINSEL_PIN_3 : Pin 3
+                - PINSEL_PIN_4 : Pin 4
+                - PINSEL_PIN_5 : Pin 5
+                - PINSEL_PIN_6 : Pin 6
+                - PINSEL_PIN_7 : Pin 7
+                - PINSEL_PIN_8 : Pin 8
+                - PINSEL_PIN_9 : Pin 9
+                - PINSEL_PIN_10 : Pin 10
+                - PINSEL_PIN_11 : Pin 11
+                - PINSEL_PIN_12 : Pin 12
+                - PINSEL_PIN_13 : Pin 13
+                - PINSEL_PIN_14 : Pin 14
+                - PINSEL_PIN_15 : Pin 15
+                - PINSEL_PIN_16 : Pin 16
+                - PINSEL_PIN_17 : Pin 17
+                - PINSEL_PIN_18 : Pin 18
+                - PINSEL_PIN_19 : Pin 19
+                - PINSEL_PIN_20 : Pin 20
+                - PINSEL_PIN_21 : Pin 21
+                - PINSEL_PIN_22 : Pin 22
+                - PINSEL_PIN_23 : Pin 23
+                - PINSEL_PIN_24 : Pin 24
+                - PINSEL_PIN_25 : Pin 25
+                - PINSEL_PIN_26 : Pin 26
+                - PINSEL_PIN_27 : Pin 27
+                - PINSEL_PIN_28 : Pin 28
+                - PINSEL_PIN_29 : Pin 29
+                - PINSEL_PIN_30 : Pin 30
+                - PINSEL_PIN_31 : Pin 31
+
+ * @param[in]    modenum  Open drain mode number,
+ *                 should be one of the following:
+ *                 - PINSEL_PINMODE_NORMAL : Pin is in the normal (not open drain) mode
+ *                 - PINSEL_PINMODE_OPENDRAIN : Pin is in the open drain mode
+ *
+ * @return         None
+ **********************************************************************/
+void set_OpenDrainMode( uint8_t portnum, uint8_t pinnum, uint8_t modenum)
+{
+    uint32_t *pPinCon = (uint32_t *)&LPC_PINCON->PINMODE_OD0;
+
+    if (modenum == PINSEL_PINMODE_OPENDRAIN){
+        *(uint32_t *)(pPinCon + portnum) |= (0x01UL << pinnum);
+    } else {
+        *(uint32_t *)(pPinCon + portnum) &= ~(0x01UL << pinnum);
+    }
+}
+
+/* End of Public Functions ---------------------------------------------------- */
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup PINSEL_Public_Functions
+ * @{
+ */
+/*********************************************************************//**
+ * @brief         Configure trace function
+ * @param[in]     NewState State of the Trace function configuration,
+ *                 should be one of the following:
+ *                 - ENABLE : Enable Trace Function
+ *                 - DISABLE : Disable Trace Function
+ *
+ * @return         None
+ **********************************************************************/
+void PINSEL_ConfigTraceFunc(FunctionalState NewState)
+{
+    if (NewState == ENABLE) {
+        LPC_PINCON->PINSEL10 |= (0x01UL << 3);
+    } else if (NewState == DISABLE) {
+        LPC_PINCON->PINSEL10 &= ~(0x01UL << 3);
+    }
+}
+
+/*********************************************************************//**
+ * @brief         Setup I2C0 pins
+ * @param[in]    i2cPinMode I2C pin mode,
+ *                 should be one of the following:
+ *                 - PINSEL_I2C_Normal_Mode : The standard drive mode
+ *                 - PINSEL_I2C_Fast_Mode : Fast Mode Plus drive mode
+ *
+ * @param[in]    filterSlewRateEnable  should be:
+ *                 - ENABLE: Enable filter and slew rate.
+ *                 - DISABLE: Disable filter and slew rate.
+ *
+ * @return         None
+ **********************************************************************/
+void PINSEL_SetI2C0Pins(uint8_t i2cPinMode, FunctionalState filterSlewRateEnable)
+{
+    uint32_t regVal = 0;
+
+    if (i2cPinMode == PINSEL_I2C_Fast_Mode){
+        regVal = PINSEL_I2CPADCFG_SCLDRV0 | PINSEL_I2CPADCFG_SDADRV0;
+    }
+
+    if (filterSlewRateEnable == DISABLE){
+        regVal = PINSEL_I2CPADCFG_SCLI2C0 | PINSEL_I2CPADCFG_SDAI2C0;
+    }
+    LPC_PINCON->I2CPADCFG = regVal;
+}
+
+
+/*********************************************************************//**
+ * @brief         Configure Pin corresponding to specified parameters passed
+ *                 in the PinCfg
+ * @param[in]    PinCfg    Pointer to a PINSEL_CFG_Type structure
+ *                    that contains the configuration information for the
+ *                    specified pin.
+ * @return         None
+ **********************************************************************/
+void PINSEL_ConfigPin(PINSEL_CFG_Type *PinCfg)
+{
+    set_PinFunc(PinCfg->Portnum, PinCfg->Pinnum, PinCfg->Funcnum);
+    set_ResistorMode(PinCfg->Portnum, PinCfg->Pinnum, PinCfg->Pinmode);
+    set_OpenDrainMode(PinCfg->Portnum, PinCfg->Pinnum, PinCfg->OpenDrain);
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff -r 000000000000 -r d920d64db582 I2S_Example/lpc17xx_pinsel.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/lpc17xx_pinsel.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,191 @@
+/***********************************************************************//**
+ * @file        lpc17xx_pinsel.h
+ * @brief        Contains all macro definitions and function prototypes
+ *                 support for Pin connect block firmware library on LPC17xx
+ * @version        2.0
+ * @date        21. May. 2010
+ * @author        NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup PINSEL PINSEL
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_PINSEL_H_
+#define LPC17XX_PINSEL_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup PINSEL_Public_Macros PINSEL Public Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ *!< Macros define for PORT Selection
+ ***********************************************************************/
+#define PINSEL_PORT_0     ((0))    /**< PORT 0*/
+#define PINSEL_PORT_1     ((1))    /**< PORT 1*/
+#define PINSEL_PORT_2     ((2))    /**< PORT 2*/
+#define PINSEL_PORT_3     ((3))    /**< PORT 3*/
+#define PINSEL_PORT_4     ((4))    /**< PORT 4*/
+
+/***********************************************************************
+ * Macros define for Pin Function selection
+ **********************************************************************/
+#define PINSEL_FUNC_0    ((0))    /**< default function*/
+#define PINSEL_FUNC_1    ((1))    /**< first alternate function*/
+#define PINSEL_FUNC_2    ((2))    /**< second alternate function*/
+#define PINSEL_FUNC_3    ((3))    /**< third or reserved alternate function*/
+
+/***********************************************************************
+ * Macros define for Pin Number of Port
+ **********************************************************************/
+#define PINSEL_PIN_0     ((0))     /**< Pin 0 */
+#define PINSEL_PIN_1     ((1))     /**< Pin 1 */
+#define PINSEL_PIN_2     ((2))     /**< Pin 2 */
+#define PINSEL_PIN_3     ((3))     /**< Pin 3 */
+#define PINSEL_PIN_4     ((4))     /**< Pin 4 */
+#define PINSEL_PIN_5     ((5))     /**< Pin 5 */
+#define PINSEL_PIN_6     ((6))     /**< Pin 6 */
+#define PINSEL_PIN_7     ((7))     /**< Pin 7 */
+#define PINSEL_PIN_8     ((8))     /**< Pin 8 */
+#define PINSEL_PIN_9     ((9))     /**< Pin 9 */
+#define PINSEL_PIN_10     ((10))     /**< Pin 10 */
+#define PINSEL_PIN_11     ((11))     /**< Pin 11 */
+#define PINSEL_PIN_12     ((12))     /**< Pin 12 */
+#define PINSEL_PIN_13     ((13))     /**< Pin 13 */
+#define PINSEL_PIN_14     ((14))     /**< Pin 14 */
+#define PINSEL_PIN_15     ((15))     /**< Pin 15 */
+#define PINSEL_PIN_16     ((16))     /**< Pin 16 */
+#define PINSEL_PIN_17     ((17))     /**< Pin 17 */
+#define PINSEL_PIN_18     ((18))     /**< Pin 18 */
+#define PINSEL_PIN_19     ((19))     /**< Pin 19 */
+#define PINSEL_PIN_20     ((20))     /**< Pin 20 */
+#define PINSEL_PIN_21     ((21))     /**< Pin 21 */
+#define PINSEL_PIN_22     ((22))     /**< Pin 22 */
+#define PINSEL_PIN_23     ((23))     /**< Pin 23 */
+#define PINSEL_PIN_24     ((24))     /**< Pin 24 */
+#define PINSEL_PIN_25     ((25))     /**< Pin 25 */
+#define PINSEL_PIN_26     ((26))     /**< Pin 26 */
+#define PINSEL_PIN_27     ((27))     /**< Pin 27 */
+#define PINSEL_PIN_28     ((28))     /**< Pin 28 */
+#define PINSEL_PIN_29     ((29))     /**< Pin 29 */
+#define PINSEL_PIN_30     ((30))     /**< Pin 30 */
+#define PINSEL_PIN_31     ((31))     /**< Pin 31 */
+
+/***********************************************************************
+ * Macros define for Pin mode
+ **********************************************************************/
+#define PINSEL_PINMODE_PULLUP        ((0))    /**< Internal pull-up resistor*/
+#define PINSEL_PINMODE_TRISTATE     ((2))    /**< Tri-state */
+#define PINSEL_PINMODE_PULLDOWN     ((3))     /**< Internal pull-down resistor */
+
+/***********************************************************************
+ * Macros define for Pin mode (normal/open drain)
+ **********************************************************************/
+#define    PINSEL_PINMODE_NORMAL        ((0))    /**< Pin is in the normal (not open drain) mode.*/
+#define    PINSEL_PINMODE_OPENDRAIN    ((1))     /**< Pin is in the open drain mode */
+
+/***********************************************************************
+ * Macros define for I2C mode
+ ***********************************************************************/
+#define    PINSEL_I2C_Normal_Mode        ((0))    /**< The standard drive mode */
+#define    PINSEL_I2C_Fast_Mode        ((1))     /**<  Fast Mode Plus drive mode */
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup PINSEL_Private_Macros PINSEL Private Macros
+ * @{
+ */
+
+/* Pin selection define */
+/* I2C Pin Configuration register bit description */
+#define PINSEL_I2CPADCFG_SDADRV0     _BIT(0) /**< Drive mode control for the SDA0 pin, P0.27 */
+#define PINSEL_I2CPADCFG_SDAI2C0    _BIT(1) /**< I2C mode control for the SDA0 pin, P0.27 */
+#define PINSEL_I2CPADCFG_SCLDRV0    _BIT(2) /**< Drive mode control for the SCL0 pin, P0.28 */
+#define PINSEL_I2CPADCFG_SCLI2C0    _BIT(3) /**< I2C mode control for the SCL0 pin, P0.28 */
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup PINSEL_Public_Types PINSEL Public Types
+ * @{
+ */
+
+/** @brief Pin configuration structure */
+typedef struct
+{
+    uint8_t Portnum;    /**< Port Number, should be PINSEL_PORT_x,
+                        where x should be in range from 0 to 4 */
+    uint8_t Pinnum;        /**< Pin Number, should be PINSEL_PIN_x,
+                        where x should be in range from 0 to 31 */
+    uint8_t Funcnum;    /**< Function Number, should be PINSEL_FUNC_x,
+                        where x should be in range from 0 to 3 */
+    uint8_t Pinmode;    /**< Pin Mode, should be:
+                        - PINSEL_PINMODE_PULLUP: Internal pull-up resistor
+                        - PINSEL_PINMODE_TRISTATE: Tri-state
+                        - PINSEL_PINMODE_PULLDOWN: Internal pull-down resistor */
+    uint8_t OpenDrain;    /**< OpenDrain mode, should be:
+                        - PINSEL_PINMODE_NORMAL: Pin is in the normal (not open drain) mode
+                        - PINSEL_PINMODE_OPENDRAIN: Pin is in the open drain mode */
+} PINSEL_CFG_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup PINSEL_Public_Functions PINSEL Public Functions
+ * @{
+ */
+
+void PINSEL_ConfigPin(PINSEL_CFG_Type *PinCfg);
+void PINSEL_ConfigTraceFunc (FunctionalState NewState);
+void PINSEL_SetI2C0Pins(uint8_t i2cPinMode, FunctionalState filterSlewRateEnable);
+
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_PINSEL_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+
diff -r 000000000000 -r d920d64db582 I2S_Example/lpc17xx_uart.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/lpc17xx_uart.c	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,1366 @@
+/***********************************************************************//**
+ * @file        lpc17xx_uart.c
+ * @brief        Contains all functions support for UART firmware library on LPC17xx
+ * @version        3.0
+ * @date        18. June. 2010
+ * @author        NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup UART
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_uart.h"
+#include "lpc17xx_clkpwr.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _UART
+
+/* Private Functions ---------------------------------------------------------- */
+
+static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate);
+
+
+/*********************************************************************//**
+ * @brief        Determines best dividers to get a target clock rate
+ * @param[in]    UARTx    Pointer to selected UART peripheral, should be:
+ *                 - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @param[in]    baudrate Desired UART baud rate.
+ * @return         Error status, could be:
+ *                 - SUCCESS
+ *                 - ERROR
+ **********************************************************************/
+static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate)
+{
+    Status errorStatus = ERROR;
+
+    uint32_t uClk = 0;
+    uint32_t calcBaudrate = 0;
+    uint32_t temp = 0;
+
+    uint32_t mulFracDiv, dividerAddFracDiv;
+    uint32_t diviser = 0 ;
+    uint32_t mulFracDivOptimal = 1;
+    uint32_t dividerAddOptimal = 0;
+    uint32_t diviserOptimal = 0;
+
+    uint32_t relativeError = 0;
+    uint32_t relativeOptimalError = 100000;
+
+    /* get UART block clock */
+    if (UARTx == (LPC_UART_TypeDef *)LPC_UART0)
+    {
+        uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART0);
+    }
+    else if (UARTx == (LPC_UART_TypeDef *)LPC_UART1)
+    {
+        uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART1);
+    }
+    else if (UARTx == LPC_UART2)
+    {
+        uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART2);
+    }
+    else if (UARTx == LPC_UART3)
+    {
+        uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART3);
+    }
+
+
+    uClk = uClk >> 4; /* div by 16 */
+    /* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
+    * The formula is :
+    * BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
+    * It involves floating point calculations. That's the reason the formulae are adjusted with
+    * Multiply and divide method.*/
+    /* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
+    * 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
+    for (mulFracDiv = 1 ; mulFracDiv <= 15 ;mulFracDiv++)
+    {
+    for (dividerAddFracDiv = 0 ; dividerAddFracDiv <= 15 ;dividerAddFracDiv++)
+    {
+      temp = (mulFracDiv * uClk) / ((mulFracDiv + dividerAddFracDiv));
+
+      diviser = temp / baudrate;
+      if ((temp % baudrate) > (baudrate / 2))
+        diviser++;
+
+      if (diviser > 2 && diviser < 65536)
+      {
+        calcBaudrate = temp / diviser;
+
+        if (calcBaudrate <= baudrate)
+          relativeError = baudrate - calcBaudrate;
+        else
+          relativeError = calcBaudrate - baudrate;
+
+        if ((relativeError < relativeOptimalError))
+        {
+          mulFracDivOptimal = mulFracDiv ;
+          dividerAddOptimal = dividerAddFracDiv;
+          diviserOptimal = diviser;
+          relativeOptimalError = relativeError;
+          if (relativeError == 0)
+            break;
+        }
+      } /* End of if */
+    } /* end of inner for loop */
+    if (relativeError == 0)
+      break;
+    } /* end of outer for loop  */
+
+    if (relativeOptimalError < ((baudrate * UART_ACCEPTED_BAUDRATE_ERROR)/100))
+    {
+        if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+        {
+            ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN;
+            ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/DLM = UART_LOAD_DLM(diviserOptimal);
+            ((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/DLL = UART_LOAD_DLL(diviserOptimal);
+            /* Then reset DLAB bit */
+            ((LPC_UART1_TypeDef *)UARTx)->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
+            ((LPC_UART1_TypeDef *)UARTx)->FDR = (UART_FDR_MULVAL(mulFracDivOptimal) \
+                    | UART_FDR_DIVADDVAL(dividerAddOptimal)) & UART_FDR_BITMASK;
+        }
+        else
+        {
+            UARTx->LCR |= UART_LCR_DLAB_EN;
+            UARTx->/*DLIER.*/DLM = UART_LOAD_DLM(diviserOptimal);
+            UARTx->/*RBTHDLR.*/DLL = UART_LOAD_DLL(diviserOptimal);
+            /* Then reset DLAB bit */
+            UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
+            UARTx->FDR = (UART_FDR_MULVAL(mulFracDivOptimal) \
+                    | UART_FDR_DIVADDVAL(dividerAddOptimal)) & UART_FDR_BITMASK;
+        }
+        errorStatus = SUCCESS;
+    }
+
+    return errorStatus;
+}
+
+/* End of Private Functions ---------------------------------------------------- */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup UART_Public_Functions
+ * @{
+ */
+/* UART Init/DeInit functions -------------------------------------------------*/
+/********************************************************************//**
+ * @brief        Initializes the UARTx peripheral according to the specified
+ *               parameters in the UART_ConfigStruct.
+ * @param[in]    UARTx    UART peripheral selected, should be:
+ *               - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @param[in]    UART_ConfigStruct Pointer to a UART_CFG_Type structure
+*                    that contains the configuration information for the
+*                    specified UART peripheral.
+ * @return         None
+ *********************************************************************/
+void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct)
+{
+    uint32_t tmp;
+
+    // For debug mode
+    CHECK_PARAM(PARAM_UARTx(UARTx));
+    CHECK_PARAM(PARAM_UART_DATABIT(UART_ConfigStruct->Databits));
+    CHECK_PARAM(PARAM_UART_STOPBIT(UART_ConfigStruct->Stopbits));
+    CHECK_PARAM(PARAM_UART_PARITY(UART_ConfigStruct->Parity));
+
+#ifdef _UART0
+    if(UARTx == (LPC_UART_TypeDef *)LPC_UART0)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, ENABLE);
+    }
+#endif
+
+#ifdef _UART1
+    if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, ENABLE);
+    }
+#endif
+
+#ifdef _UART2
+    if(UARTx == LPC_UART2)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, ENABLE);
+    }
+#endif
+
+#ifdef _UART3
+    if(UARTx == LPC_UART3)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, ENABLE);
+    }
+#endif
+
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        /* FIFOs are empty */
+        ((LPC_UART1_TypeDef *)UARTx)->/*IIFCR.*/FCR = ( UART_FCR_FIFO_EN \
+                | UART_FCR_RX_RS | UART_FCR_TX_RS);
+        // Disable FIFO
+        ((LPC_UART1_TypeDef *)UARTx)->/*IIFCR.*/FCR = 0;
+
+        // Dummy reading
+        while (((LPC_UART1_TypeDef *)UARTx)->LSR & UART_LSR_RDR)
+        {
+            tmp = ((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/RBR;
+        }
+
+        ((LPC_UART1_TypeDef *)UARTx)->TER = UART_TER_TXEN;
+        // Wait for current transmit complete
+        while (!(((LPC_UART1_TypeDef *)UARTx)->LSR & UART_LSR_THRE));
+        // Disable Tx
+        ((LPC_UART1_TypeDef *)UARTx)->TER = 0;
+
+        // Disable interrupt
+        ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/IER = 0;
+        // Set LCR to default state
+        ((LPC_UART1_TypeDef *)UARTx)->LCR = 0;
+        // Set ACR to default state
+        ((LPC_UART1_TypeDef *)UARTx)->ACR = 0;
+        // Set Modem Control to default state
+        ((LPC_UART1_TypeDef *)UARTx)->MCR = 0;
+        // Set RS485 control to default state
+        ((LPC_UART1_TypeDef *)UARTx)->RS485CTRL = 0;
+        // Set RS485 delay timer to default state
+        ((LPC_UART1_TypeDef *)UARTx)->RS485DLY = 0;
+        // Set RS485 addr match to default state
+        ((LPC_UART1_TypeDef *)UARTx)->ADRMATCH = 0;
+        //Dummy Reading to Clear Status
+        tmp = ((LPC_UART1_TypeDef *)UARTx)->MSR;
+        tmp = ((LPC_UART1_TypeDef *)UARTx)->LSR;
+    }
+    else
+    {
+        /* FIFOs are empty */
+        UARTx->/*IIFCR.*/FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS);
+        // Disable FIFO
+        UARTx->/*IIFCR.*/FCR = 0;
+
+        // Dummy reading
+        while (UARTx->LSR & UART_LSR_RDR)
+        {
+            tmp = UARTx->/*RBTHDLR.*/RBR;
+        }
+
+        UARTx->TER = UART_TER_TXEN;
+        // Wait for current transmit complete
+        while (!(UARTx->LSR & UART_LSR_THRE));
+        // Disable Tx
+        UARTx->TER = 0;
+
+        // Disable interrupt
+        UARTx->/*DLIER.*/IER = 0;
+        // Set LCR to default state
+        UARTx->LCR = 0;
+        // Set ACR to default state
+        UARTx->ACR = 0;
+        // Dummy reading
+        tmp = UARTx->LSR;
+    }
+
+    if (UARTx == LPC_UART3)
+    {
+        // Set IrDA to default state
+        UARTx->ICR = 0;
+    }
+
+    // Set Line Control register ----------------------------
+
+    uart_set_divisors(UARTx, (UART_ConfigStruct->Baud_rate));
+
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        tmp = (((LPC_UART1_TypeDef *)UARTx)->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) \
+                & UART_LCR_BITMASK;
+    }
+    else
+    {
+        tmp = (UARTx->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK;
+    }
+
+    switch (UART_ConfigStruct->Databits){
+    case UART_DATABIT_5:
+        tmp |= UART_LCR_WLEN5;
+        break;
+    case UART_DATABIT_6:
+        tmp |= UART_LCR_WLEN6;
+        break;
+    case UART_DATABIT_7:
+        tmp |= UART_LCR_WLEN7;
+        break;
+    case UART_DATABIT_8:
+    default:
+        tmp |= UART_LCR_WLEN8;
+        break;
+    }
+
+    if (UART_ConfigStruct->Parity == UART_PARITY_NONE)
+    {
+        // Do nothing...
+    }
+    else
+    {
+        tmp |= UART_LCR_PARITY_EN;
+        switch (UART_ConfigStruct->Parity)
+        {
+        case UART_PARITY_ODD:
+            tmp |= UART_LCR_PARITY_ODD;
+            break;
+
+        case UART_PARITY_EVEN:
+            tmp |= UART_LCR_PARITY_EVEN;
+            break;
+
+        case UART_PARITY_SP_1:
+            tmp |= UART_LCR_PARITY_F_1;
+            break;
+
+        case UART_PARITY_SP_0:
+            tmp |= UART_LCR_PARITY_F_0;
+            break;
+        default:
+            break;
+        }
+    }
+
+    switch (UART_ConfigStruct->Stopbits){
+    case UART_STOPBIT_2:
+        tmp |= UART_LCR_STOPBIT_SEL;
+        break;
+    case UART_STOPBIT_1:
+    default:
+        // Do no thing
+        break;
+    }
+
+
+    // Write back to LCR, configure FIFO and Disable Tx
+    if (((LPC_UART1_TypeDef *)UARTx) ==  LPC_UART1)
+    {
+        ((LPC_UART1_TypeDef *)UARTx)->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
+    }
+    else
+    {
+        UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
+    }
+}
+
+/*********************************************************************//**
+ * @brief        De-initializes the UARTx peripheral registers to their
+ *                  default reset values.
+ * @param[in]    UARTx    UART peripheral selected, should be:
+ *               - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @return         None
+ **********************************************************************/
+void UART_DeInit(LPC_UART_TypeDef* UARTx)
+{
+    // For debug mode
+    CHECK_PARAM(PARAM_UARTx(UARTx));
+
+    UART_TxCmd(UARTx, DISABLE);
+
+#ifdef _UART0
+    if (UARTx == (LPC_UART_TypeDef *)LPC_UART0)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, DISABLE);
+    }
+#endif
+
+#ifdef _UART1
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, DISABLE);
+    }
+#endif
+
+#ifdef _UART2
+    if (UARTx == LPC_UART2)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, DISABLE);
+    }
+#endif
+
+#ifdef _UART3
+    if (UARTx == LPC_UART3)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, DISABLE);
+    }
+#endif
+}
+
+/*****************************************************************************//**
+* @brief        Fills each UART_InitStruct member with its default value:
+*                 - 9600 bps
+*                 - 8-bit data
+*                 - 1 Stopbit
+*                 - None Parity
+* @param[in]    UART_InitStruct Pointer to a UART_CFG_Type structure
+*                    which will be initialized.
+* @return        None
+*******************************************************************************/
+void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct)
+{
+    UART_InitStruct->Baud_rate = 9600;
+    UART_InitStruct->Databits = UART_DATABIT_8;
+    UART_InitStruct->Parity = UART_PARITY_NONE;
+    UART_InitStruct->Stopbits = UART_STOPBIT_1;
+}
+
+/* UART Send/Recieve functions -------------------------------------------------*/
+/*********************************************************************//**
+ * @brief        Transmit a single data through UART peripheral
+ * @param[in]    UARTx    UART peripheral selected, should be:
+ *               - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @param[in]    Data    Data to transmit (must be 8-bit long)
+ * @return         None
+ **********************************************************************/
+void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data)
+{
+    CHECK_PARAM(PARAM_UARTx(UARTx));
+
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        ((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/THR = Data & UART_THR_MASKBIT;
+    }
+    else
+    {
+        UARTx->/*RBTHDLR.*/THR = Data & UART_THR_MASKBIT;
+    }
+
+}
+
+
+/*********************************************************************//**
+ * @brief        Receive a single data from UART peripheral
+ * @param[in]    UARTx    UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @return         Data received
+ **********************************************************************/
+uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx)
+{
+    CHECK_PARAM(PARAM_UARTx(UARTx));
+
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        return (((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/RBR & UART_RBR_MASKBIT);
+    }
+    else
+    {
+        return (UARTx->/*RBTHDLR.*/RBR & UART_RBR_MASKBIT);
+    }
+}
+
+/*********************************************************************//**
+ * @brief        Send a block of data via UART peripheral
+ * @param[in]    UARTx    Selected UART peripheral used to send data, should be:
+ *               - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @param[in]    txbuf     Pointer to Transmit buffer
+ * @param[in]    buflen     Length of Transmit buffer
+ * @param[in]     flag     Flag used in  UART transfer, should be
+ *                         NONE_BLOCKING or BLOCKING
+ * @return         Number of bytes sent.
+ *
+ * Note: when using UART in BLOCKING mode, a time-out condition is used
+ * via defined symbol UART_BLOCKING_TIMEOUT.
+ **********************************************************************/
+uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf,
+        uint32_t buflen, TRANSFER_BLOCK_Type flag)
+{
+    uint32_t bToSend, bSent, timeOut, fifo_cnt;
+    uint8_t *pChar = txbuf;
+
+    bToSend = buflen;
+
+    // blocking mode
+    if (flag == BLOCKING) {
+        bSent = 0;
+        while (bToSend){
+            timeOut = UART_BLOCKING_TIMEOUT;
+            // Wait for THR empty with timeout
+            while (!(UARTx->LSR & UART_LSR_THRE)) {
+                if (timeOut == 0) break;
+                timeOut--;
+            }
+            // Time out!
+            if(timeOut == 0) break;
+            fifo_cnt = UART_TX_FIFO_SIZE;
+            while (fifo_cnt && bToSend){
+                UART_SendByte(UARTx, (*pChar++));
+                fifo_cnt--;
+                bToSend--;
+                bSent++;
+            }
+        }
+    }
+    // None blocking mode
+    else {
+        bSent = 0;
+        while (bToSend) {
+            if (!(UARTx->LSR & UART_LSR_THRE)){
+                break;
+            }
+            fifo_cnt = UART_TX_FIFO_SIZE;
+            while (fifo_cnt && bToSend) {
+                UART_SendByte(UARTx, (*pChar++));
+                bToSend--;
+                fifo_cnt--;
+                bSent++;
+            }
+        }
+    }
+    return bSent;
+}
+
+/*********************************************************************//**
+ * @brief        Receive a block of data via UART peripheral
+ * @param[in]    UARTx    Selected UART peripheral used to send data,
+ *                 should be:
+ *               - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @param[out]    rxbuf     Pointer to Received buffer
+ * @param[in]    buflen     Length of Received buffer
+ * @param[in]     flag     Flag mode, should be NONE_BLOCKING or BLOCKING
+
+ * @return         Number of bytes received
+ *
+ * Note: when using UART in BLOCKING mode, a time-out condition is used
+ * via defined symbol UART_BLOCKING_TIMEOUT.
+ **********************************************************************/
+uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \
+        uint32_t buflen, TRANSFER_BLOCK_Type flag)
+{
+    uint32_t bToRecv, bRecv, timeOut;
+    uint8_t *pChar = rxbuf;
+
+    bToRecv = buflen;
+
+    // Blocking mode
+    if (flag == BLOCKING) {
+        bRecv = 0;
+        while (bToRecv){
+            timeOut = UART_BLOCKING_TIMEOUT;
+            while (!(UARTx->LSR & UART_LSR_RDR)){
+                if (timeOut == 0) break;
+                timeOut--;
+            }
+            // Time out!
+            if(timeOut == 0) break;
+            // Get data from the buffer
+            (*pChar++) = UART_ReceiveByte(UARTx);
+            bToRecv--;
+            bRecv++;
+        }
+    }
+    // None blocking mode
+    else {
+        bRecv = 0;
+        while (bToRecv) {
+            if (!(UARTx->LSR & UART_LSR_RDR)) {
+                break;
+            } else {
+                (*pChar++) = UART_ReceiveByte(UARTx);
+                bRecv++;
+                bToRecv--;
+            }
+        }
+    }
+    return bRecv;
+}
+
+/*********************************************************************//**
+ * @brief        Force BREAK character on UART line, output pin UARTx TXD is
+                forced to logic 0.
+ * @param[in]    UARTx    UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @return         None
+ **********************************************************************/
+void UART_ForceBreak(LPC_UART_TypeDef* UARTx)
+{
+    CHECK_PARAM(PARAM_UARTx(UARTx));
+
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_BREAK_EN;
+    }
+    else
+    {
+        UARTx->LCR |= UART_LCR_BREAK_EN;
+    }
+}
+
+
+/********************************************************************//**
+ * @brief         Enable or disable specified UART interrupt.
+ * @param[in]    UARTx    UART peripheral selected, should be
+ *              - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @param[in]    UARTIntCfg    Specifies the interrupt flag,
+ *                 should be one of the following:
+                - UART_INTCFG_RBR     :  RBR Interrupt enable
+                - UART_INTCFG_THRE     :  THR Interrupt enable
+                - UART_INTCFG_RLS     :  RX line status interrupt enable
+                - UART1_INTCFG_MS    :  Modem status interrupt enable (UART1 only)
+                - UART1_INTCFG_CTS    :  CTS1 signal transition interrupt enable (UART1 only)
+                - UART_INTCFG_ABEO     :  Enables the end of auto-baud interrupt
+                - UART_INTCFG_ABTO     :  Enables the auto-baud time-out interrupt
+ * @param[in]    NewState New state of specified UART interrupt type,
+ *                 should be:
+ *                 - ENALBE: Enable this UART interrupt type.
+*                 - DISALBE: Disable this UART interrupt type.
+ * @return         None
+ *********************************************************************/
+void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState)
+{
+    uint32_t tmp = 0;
+
+    CHECK_PARAM(PARAM_UARTx(UARTx));
+    CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+    switch(UARTIntCfg){
+        case UART_INTCFG_RBR:
+            tmp = UART_IER_RBRINT_EN;
+            break;
+        case UART_INTCFG_THRE:
+            tmp = UART_IER_THREINT_EN;
+            break;
+        case UART_INTCFG_RLS:
+            tmp = UART_IER_RLSINT_EN;
+            break;
+        case UART1_INTCFG_MS:
+            tmp = UART1_IER_MSINT_EN;
+            break;
+        case UART1_INTCFG_CTS:
+            tmp = UART1_IER_CTSINT_EN;
+            break;
+        case UART_INTCFG_ABEO:
+            tmp = UART_IER_ABEOINT_EN;
+            break;
+        case UART_INTCFG_ABTO:
+            tmp = UART_IER_ABTOINT_EN;
+            break;
+    }
+
+    if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
+    {
+        CHECK_PARAM((PARAM_UART_INTCFG(UARTIntCfg)) || (PARAM_UART1_INTCFG(UARTIntCfg)));
+    }
+    else
+    {
+        CHECK_PARAM(PARAM_UART_INTCFG(UARTIntCfg));
+    }
+
+    if (NewState == ENABLE)
+    {
+        if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
+        {
+            ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/IER |= tmp;
+        }
+        else
+        {
+            UARTx->/*DLIER.*/IER |= tmp;
+        }
+    }
+    else
+    {
+        if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
+        {
+            ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/IER &= (~tmp) & UART1_IER_BITMASK;
+        }
+        else
+        {
+            UARTx->/*DLIER.*/IER &= (~tmp) & UART_IER_BITMASK;
+        }
+    }
+}
+
+
+/********************************************************************//**
+ * @brief         Get current value of Line Status register in UART peripheral.
+ * @param[in]    UARTx    UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @return        Current value of Line Status register in UART peripheral.
+ * Note:    The return value of this function must be ANDed with each member in
+ *             UART_LS_Type enumeration to determine current flag status
+ *             corresponding to each Line status type. Because some flags in
+ *             Line Status register will be cleared after reading, the next reading
+ *             Line Status register could not be correct. So this function used to
+ *             read Line status register in one time only, then the return value
+ *             used to check all flags.
+ *********************************************************************/
+uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx)
+{
+    CHECK_PARAM(PARAM_UARTx(UARTx));
+
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        return ((((LPC_UART1_TypeDef *)LPC_UART1)->LSR) & UART_LSR_BITMASK);
+    }
+    else
+    {
+        return ((UARTx->LSR) & UART_LSR_BITMASK);
+    }
+}
+
+/********************************************************************//**
+ * @brief         Get Interrupt Identification value
+ * @param[in]    UARTx    UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @return        Current value of UART UIIR register in UART peripheral.
+ *********************************************************************/
+uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx)
+{
+    CHECK_PARAM(PARAM_UARTx(UARTx));
+    return (UARTx->IIR & 0x03CF);
+}
+
+/*********************************************************************//**
+ * @brief        Check whether if UART is busy or not
+ * @param[in]    UARTx    UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @return        RESET if UART is not busy, otherwise return SET.
+ **********************************************************************/
+FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx)
+{
+    if (UARTx->LSR & UART_LSR_TEMT){
+        return RESET;
+    } else {
+        return SET;
+    }
+}
+
+
+/*********************************************************************//**
+ * @brief        Configure FIFO function on selected UART peripheral
+ * @param[in]    UARTx    UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @param[in]    FIFOCfg    Pointer to a UART_FIFO_CFG_Type Structure that
+ *                         contains specified information about FIFO configuration
+ * @return         none
+ **********************************************************************/
+void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg)
+{
+    uint8_t tmp = 0;
+
+    CHECK_PARAM(PARAM_UARTx(UARTx));
+    CHECK_PARAM(PARAM_UART_FIFO_LEVEL(FIFOCfg->FIFO_Level));
+    CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_DMAMode));
+    CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetRxBuf));
+    CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetTxBuf));
+
+    tmp |= UART_FCR_FIFO_EN;
+    switch (FIFOCfg->FIFO_Level){
+    case UART_FIFO_TRGLEV0:
+        tmp |= UART_FCR_TRG_LEV0;
+        break;
+    case UART_FIFO_TRGLEV1:
+        tmp |= UART_FCR_TRG_LEV1;
+        break;
+    case UART_FIFO_TRGLEV2:
+        tmp |= UART_FCR_TRG_LEV2;
+        break;
+    case UART_FIFO_TRGLEV3:
+    default:
+        tmp |= UART_FCR_TRG_LEV3;
+        break;
+    }
+
+    if (FIFOCfg->FIFO_ResetTxBuf == ENABLE)
+    {
+        tmp |= UART_FCR_TX_RS;
+    }
+    if (FIFOCfg->FIFO_ResetRxBuf == ENABLE)
+    {
+        tmp |= UART_FCR_RX_RS;
+    }
+    if (FIFOCfg->FIFO_DMAMode == ENABLE)
+    {
+        tmp |= UART_FCR_DMAMODE_SEL;
+    }
+
+
+    //write to FIFO control register
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        ((LPC_UART1_TypeDef *)UARTx)->/*IIFCR.*/FCR = tmp & UART_FCR_BITMASK;
+    }
+    else
+    {
+        UARTx->/*IIFCR.*/FCR = tmp & UART_FCR_BITMASK;
+    }
+}
+
+/*****************************************************************************//**
+* @brief        Fills each UART_FIFOInitStruct member with its default value:
+*                 - FIFO_DMAMode = DISABLE
+*                 - FIFO_Level = UART_FIFO_TRGLEV0
+*                 - FIFO_ResetRxBuf = ENABLE
+*                 - FIFO_ResetTxBuf = ENABLE
+*                 - FIFO_State = ENABLE
+
+* @param[in]    UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure
+*                    which will be initialized.
+* @return        None
+*******************************************************************************/
+void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct)
+{
+    UART_FIFOInitStruct->FIFO_DMAMode = DISABLE;
+    UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0;
+    UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE;
+    UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE;
+}
+
+
+/*********************************************************************//**
+ * @brief        Start/Stop Auto Baudrate activity
+ * @param[in]    UARTx    UART peripheral selected, should be
+ *               - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @param[in]    ABConfigStruct    A pointer to UART_AB_CFG_Type structure that
+ *                                 contains specified information about UART
+ *                                 auto baudrate configuration
+ * @param[in]    NewState New State of Auto baudrate activity, should be:
+ *                 - ENABLE: Start this activity
+ *                - DISABLE: Stop this activity
+ * Note:        Auto-baudrate mode enable bit will be cleared once this mode
+ *                 completed.
+ * @return         none
+ **********************************************************************/
+void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
+                FunctionalState NewState)
+{
+    uint32_t tmp;
+
+    CHECK_PARAM(PARAM_UARTx(UARTx));
+    CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+    tmp = 0;
+    if (NewState == ENABLE) {
+        if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1){
+            tmp |= UART_ACR_MODE;
+        }
+        if (ABConfigStruct->AutoRestart == ENABLE){
+            tmp |= UART_ACR_AUTO_RESTART;
+        }
+    }
+
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        if (NewState == ENABLE)
+        {
+            // Clear DLL and DLM value
+            ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN;
+            ((LPC_UART1_TypeDef *)UARTx)->DLL = 0;
+            ((LPC_UART1_TypeDef *)UARTx)->DLM = 0;
+            ((LPC_UART1_TypeDef *)UARTx)->LCR &= ~UART_LCR_DLAB_EN;
+            // FDR value must be reset to default value
+            ((LPC_UART1_TypeDef *)UARTx)->FDR = 0x10;
+            ((LPC_UART1_TypeDef *)UARTx)->ACR = UART_ACR_START | tmp;
+        }
+        else
+        {
+            ((LPC_UART1_TypeDef *)UARTx)->ACR = 0;
+        }
+    }
+    else
+    {
+        if (NewState == ENABLE)
+        {
+            // Clear DLL and DLM value
+            UARTx->LCR |= UART_LCR_DLAB_EN;
+            UARTx->DLL = 0;
+            UARTx->DLM = 0;
+            UARTx->LCR &= ~UART_LCR_DLAB_EN;
+            // FDR value must be reset to default value
+            UARTx->FDR = 0x10;
+            UARTx->ACR = UART_ACR_START | tmp;
+        }
+        else
+        {
+            UARTx->ACR = 0;
+        }
+    }
+}
+
+/*********************************************************************//**
+ * @brief        Clear Autobaud Interrupt Pending
+ * @param[in]    UARTx    UART peripheral selected, should be
+ *               - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @param[in]    ABIntType    type of auto-baud interrupt, should be:
+ *                 - UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt
+ *                 - UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt
+ * @return         none
+ **********************************************************************/
+void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType)
+{
+    CHECK_PARAM(PARAM_UARTx(UARTx));
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        UARTx->ACR |= ABIntType;
+    }
+    else
+        UARTx->ACR |= ABIntType;
+}
+
+/*********************************************************************//**
+ * @brief        Enable/Disable transmission on UART TxD pin
+ * @param[in]    UARTx    UART peripheral selected, should be:
+ *               - LPC_UART0: UART0 peripheral
+ *                 - LPC_UART1: UART1 peripheral
+ *                 - LPC_UART2: UART2 peripheral
+ *                 - LPC_UART3: UART3 peripheral
+ * @param[in]    NewState New State of Tx transmission function, should be:
+ *                 - ENABLE: Enable this function
+                - DISABLE: Disable this function
+ * @return none
+ **********************************************************************/
+void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState)
+{
+    CHECK_PARAM(PARAM_UARTx(UARTx));
+    CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+        {
+            ((LPC_UART1_TypeDef *)UARTx)->TER |= UART_TER_TXEN;
+        }
+        else
+        {
+            UARTx->TER |= UART_TER_TXEN;
+        }
+    }
+    else
+    {
+        if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+        {
+            ((LPC_UART1_TypeDef *)UARTx)->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
+        }
+        else
+        {
+            UARTx->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
+        }
+    }
+}
+
+/* UART IrDA functions ---------------------------------------------------*/
+
+#ifdef _UART3
+
+/*********************************************************************//**
+ * @brief        Enable or disable inverting serial input function of IrDA
+ *                 on UART peripheral.
+ * @param[in]    UARTx UART peripheral selected, should be LPC_UART3 (only)
+ * @param[in]    NewState New state of inverting serial input, should be:
+ *                 - ENABLE: Enable this function.
+ *                 - DISABLE: Disable this function.
+ * @return none
+ **********************************************************************/
+void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
+{
+    CHECK_PARAM(PARAM_UART_IrDA(UARTx));
+    CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        UARTx->ICR |= UART_ICR_IRDAINV;
+    }
+    else if (NewState == DISABLE)
+    {
+        UARTx->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK;
+    }
+}
+
+
+/*********************************************************************//**
+ * @brief        Enable or disable IrDA function on UART peripheral.
+ * @param[in]    UARTx UART peripheral selected, should be LPC_UART3 (only)
+ * @param[in]    NewState New state of IrDA function, should be:
+ *                 - ENABLE: Enable this function.
+ *                 - DISABLE: Disable this function.
+ * @return none
+ **********************************************************************/
+void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
+{
+    CHECK_PARAM(PARAM_UART_IrDA(UARTx));
+    CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+    if (NewState == ENABLE)
+    {
+        UARTx->ICR |= UART_ICR_IRDAEN;
+    }
+    else
+    {
+        UARTx->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK;
+    }
+}
+
+
+/*********************************************************************//**
+ * @brief        Configure Pulse divider for IrDA function on UART peripheral.
+ * @param[in]    UARTx UART peripheral selected, should be LPC_UART3 (only)
+ * @param[in]    PulseDiv Pulse Divider value from Peripheral clock,
+ *                 should be one of the following:
+                - UART_IrDA_PULSEDIV2     : Pulse width = 2 * Tpclk
+                - UART_IrDA_PULSEDIV4     : Pulse width = 4 * Tpclk
+                - UART_IrDA_PULSEDIV8     : Pulse width = 8 * Tpclk
+                - UART_IrDA_PULSEDIV16     : Pulse width = 16 * Tpclk
+                - UART_IrDA_PULSEDIV32     : Pulse width = 32 * Tpclk
+                - UART_IrDA_PULSEDIV64     : Pulse width = 64 * Tpclk
+                - UART_IrDA_PULSEDIV128 : Pulse width = 128 * Tpclk
+                - UART_IrDA_PULSEDIV256 : Pulse width = 256 * Tpclk
+
+ * @return none
+ **********************************************************************/
+void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv)
+{
+    uint32_t tmp, tmp1;
+    CHECK_PARAM(PARAM_UART_IrDA(UARTx));
+    CHECK_PARAM(PARAM_UART_IrDA_PULSEDIV(PulseDiv));
+
+    tmp1 = UART_ICR_PULSEDIV(PulseDiv);
+    tmp = UARTx->ICR & (~UART_ICR_PULSEDIV(7));
+    tmp |= tmp1 | UART_ICR_FIXPULSE_EN;
+    UARTx->ICR = tmp & UART_ICR_BITMASK;
+}
+
+#endif
+
+
+/* UART1 FullModem function ---------------------------------------------*/
+
+#ifdef _UART1
+
+/*********************************************************************//**
+ * @brief        Force pin DTR/RTS corresponding to given state (Full modem mode)
+ * @param[in]    UARTx    LPC_UART1 (only)
+ * @param[in]    Pin    Pin that NewState will be applied to, should be:
+ *                 - UART1_MODEM_PIN_DTR: DTR pin.
+ *                 - UART1_MODEM_PIN_RTS: RTS pin.
+ * @param[in]    NewState New State of DTR/RTS pin, should be:
+ *                 - INACTIVE: Force the pin to inactive signal.
+                - ACTIVE: Force the pin to active signal.
+ * @return none
+ **********************************************************************/
+void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \
+                            UART1_SignalState NewState)
+{
+    uint8_t tmp = 0;
+
+    CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
+    CHECK_PARAM(PARAM_UART1_MODEM_PIN(Pin));
+    CHECK_PARAM(PARAM_UART1_SIGNALSTATE(NewState));
+
+    switch (Pin){
+    case UART1_MODEM_PIN_DTR:
+        tmp = UART1_MCR_DTR_CTRL;
+        break;
+    case UART1_MODEM_PIN_RTS:
+        tmp = UART1_MCR_RTS_CTRL;
+        break;
+    default:
+        break;
+    }
+
+    if (NewState == ACTIVE){
+        UARTx->MCR |= tmp;
+    } else {
+        UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
+    }
+}
+
+
+/*********************************************************************//**
+ * @brief        Configure Full Modem mode for UART peripheral
+ * @param[in]    UARTx    LPC_UART1 (only)
+ * @param[in]    Mode Full Modem mode, should be:
+ *                 - UART1_MODEM_MODE_LOOPBACK: Loop back mode.
+ *                 - UART1_MODEM_MODE_AUTO_RTS: Auto-RTS mode.
+ *                 - UART1_MODEM_MODE_AUTO_CTS: Auto-CTS mode.
+ * @param[in]    NewState New State of this mode, should be:
+ *                 - ENABLE: Enable this mode.
+                - DISABLE: Disable this mode.
+ * @return none
+ **********************************************************************/
+void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \
+                            FunctionalState NewState)
+{
+    uint8_t tmp = 0;
+
+    CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
+    CHECK_PARAM(PARAM_UART1_MODEM_MODE(Mode));
+    CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+    switch(Mode){
+    case UART1_MODEM_MODE_LOOPBACK:
+        tmp = UART1_MCR_LOOPB_EN;
+        break;
+    case UART1_MODEM_MODE_AUTO_RTS:
+        tmp = UART1_MCR_AUTO_RTS_EN;
+        break;
+    case UART1_MODEM_MODE_AUTO_CTS:
+        tmp = UART1_MCR_AUTO_CTS_EN;
+        break;
+    default:
+        break;
+    }
+
+    if (NewState == ENABLE)
+    {
+        UARTx->MCR |= tmp;
+    }
+    else
+    {
+        UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
+    }
+}
+
+
+/*********************************************************************//**
+ * @brief        Get current status of modem status register
+ * @param[in]    UARTx    LPC_UART1 (only)
+ * @return         Current value of modem status register
+ * Note:    The return value of this function must be ANDed with each member
+ *             UART_MODEM_STAT_type enumeration to determine current flag status
+ *             corresponding to each modem flag status. Because some flags in
+ *             modem status register will be cleared after reading, the next reading
+ *             modem register could not be correct. So this function used to
+ *             read modem status register in one time only, then the return value
+ *             used to check all flags.
+ **********************************************************************/
+uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx)
+{
+    CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
+    return ((UARTx->MSR) & UART1_MSR_BITMASK);
+}
+
+
+/* UART RS485 functions --------------------------------------------------------------*/
+
+/*********************************************************************//**
+ * @brief        Configure UART peripheral in RS485 mode according to the specified
+*               parameters in the RS485ConfigStruct.
+ * @param[in]    UARTx    LPC_UART1 (only)
+ * @param[in]    RS485ConfigStruct Pointer to a UART1_RS485_CTRLCFG_Type structure
+*                    that contains the configuration information for specified UART
+*                    in RS485 mode.
+ * @return        None
+ **********************************************************************/
+void UART_RS485Config(LPC_UART1_TypeDef *UARTx, UART1_RS485_CTRLCFG_Type *RS485ConfigStruct)
+{
+    uint32_t tmp;
+
+    CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
+    CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoAddrDetect_State));
+    CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoDirCtrl_State));
+    CHECK_PARAM(PARAM_UART1_RS485_CFG_DELAYVALUE(RS485ConfigStruct->DelayValue));
+    CHECK_PARAM(PARAM_SETSTATE(RS485ConfigStruct->DirCtrlPol_Level));
+    CHECK_PARAM(PARAM_UART_RS485_DIRCTRL_PIN(RS485ConfigStruct->DirCtrlPin));
+    CHECK_PARAM(PARAM_UART1_RS485_CFG_MATCHADDRVALUE(RS485ConfigStruct->MatchAddrValue));
+    CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->NormalMultiDropMode_State));
+    CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->Rx_State));
+
+    tmp = 0;
+    // If Auto Direction Control is enabled -  This function is used in Master mode
+    if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE)
+    {
+        tmp |= UART1_RS485CTRL_DCTRL_EN;
+
+        // Set polar
+        if (RS485ConfigStruct->DirCtrlPol_Level == SET)
+        {
+            tmp |= UART1_RS485CTRL_OINV_1;
+        }
+
+        // Set pin according to
+        if (RS485ConfigStruct->DirCtrlPin == UART1_RS485_DIRCTRL_DTR)
+        {
+            tmp |= UART1_RS485CTRL_SEL_DTR;
+        }
+
+        // Fill delay time
+        UARTx->RS485DLY = RS485ConfigStruct->DelayValue & UART1_RS485DLY_BITMASK;
+    }
+
+    // MultiDrop mode is enable
+    if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE)
+    {
+        tmp |= UART1_RS485CTRL_NMM_EN;
+    }
+
+    // Auto Address Detect function
+    if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE)
+    {
+        tmp |= UART1_RS485CTRL_AADEN;
+        // Fill Match Address
+        UARTx->ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART1_RS485ADRMATCH_BITMASK;
+    }
+
+
+    // Receiver is disable
+    if (RS485ConfigStruct->Rx_State == DISABLE)
+    {
+        tmp |= UART1_RS485CTRL_RX_DIS;
+    }
+
+    // write back to RS485 control register
+    UARTx->RS485CTRL = tmp & UART1_RS485CTRL_BITMASK;
+
+    // Enable Parity function and leave parity in stick '0' parity as default
+    UARTx->LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN);
+}
+
+/*********************************************************************//**
+ * @brief        Enable/Disable receiver in RS485 module in UART1
+ * @param[in]    UARTx    LPC_UART1 (only)
+ * @param[in]    NewState    New State of command, should be:
+ *                             - ENABLE: Enable this function.
+ *                             - DISABLE: Disable this function.
+ * @return        None
+ **********************************************************************/
+void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState)
+{
+    if (NewState == ENABLE){
+        UARTx->RS485CTRL &= ~UART1_RS485CTRL_RX_DIS;
+    } else {
+        UARTx->RS485CTRL |= UART1_RS485CTRL_RX_DIS;
+    }
+}
+
+/*********************************************************************//**
+ * @brief        Send data on RS485 bus with specified parity stick value (9-bit mode).
+ * @param[in]    UARTx    LPC_UART1 (only)
+ * @param[in]    pDatFrm     Pointer to data frame.
+ * @param[in]    size        Size of data.
+ * @param[in]    ParityStick    Parity Stick value, should be 0 or 1.
+ * @return        None
+ **********************************************************************/
+uint32_t UART_RS485Send(LPC_UART1_TypeDef *UARTx, uint8_t *pDatFrm, \
+                    uint32_t size, uint8_t ParityStick)
+{
+    uint8_t tmp, save;
+    uint32_t cnt;
+
+    if (ParityStick){
+        save = tmp = UARTx->LCR & UART_LCR_BITMASK;
+        tmp &= ~(UART_LCR_PARITY_EVEN);
+        UARTx->LCR = tmp;
+        cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
+        while (!(UARTx->LSR & UART_LSR_TEMT));
+        UARTx->LCR = save;
+    } else {
+        cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
+        while (!(UARTx->LSR & UART_LSR_TEMT));
+    }
+    return cnt;
+}
+
+/*********************************************************************//**
+ * @brief        Send Slave address frames on RS485 bus.
+ * @param[in]    UARTx    LPC_UART1 (only)
+ * @param[in]    SlvAddr Slave Address.
+ * @return        None
+ **********************************************************************/
+void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr)
+{
+    UART_RS485Send(UARTx, &SlvAddr, 1, 1);
+}
+
+/*********************************************************************//**
+ * @brief        Send Data frames on RS485 bus.
+ * @param[in]    UARTx    LPC_UART1 (only)
+ * @param[in]    pData Pointer to data to be sent.
+ * @param[in]    size Size of data frame to be sent.
+ * @return        None
+ **********************************************************************/
+uint32_t UART_RS485SendData(LPC_UART1_TypeDef *UARTx, uint8_t *pData, uint32_t size)
+{
+    return (UART_RS485Send(UARTx, pData, size, 0));
+}
+
+#endif /* _UART1 */
+
+#endif /* _UART */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* --------------------------------- End Of File ------------------------------ */
+
diff -r 000000000000 -r d920d64db582 I2S_Example/lpc17xx_uart.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/lpc17xx_uart.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,644 @@
+/***********************************************************************//**
+ * @file        lpc17xx_uart.h
+ * @brief        Contains all macro definitions and function prototypes
+ *                 support for UART firmware library on LPC17xx
+ * @version        3.0
+ * @date        18. June. 2010
+ * @author        NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup UART UART
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC17XX_UART_H
+#define __LPC17XX_UART_H
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup UART_Public_Macros  UART Public Macros
+ * @{
+ */
+
+/** UART time-out definitions in case of using Read() and Write function
+ * with Blocking Flag mode
+ */
+#define UART_BLOCKING_TIMEOUT            (0xFFFFFFFFUL)
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+
+/* Accepted Error baud rate value (in percent unit) */
+#define UART_ACCEPTED_BAUDRATE_ERROR    (3)            /*!< Acceptable UART baudrate error */
+
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Receiver Buffer Register
+ **********************************************************************/
+#define UART_RBR_MASKBIT       ((uint8_t)0xFF)         /*!< UART Received Buffer mask bit (8 bits) */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Transmit Holding Register
+ **********************************************************************/
+#define UART_THR_MASKBIT       ((uint8_t)0xFF)         /*!< UART Transmit Holding mask bit (8 bits) */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch LSB register
+ **********************************************************************/
+#define UART_LOAD_DLL(div)    ((div) & 0xFF)    /**< Macro for loading least significant halfs of divisors */
+#define UART_DLL_MASKBIT    ((uint8_t)0xFF)    /*!< Divisor latch LSB bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch MSB register
+ **********************************************************************/
+#define UART_DLM_MASKBIT    ((uint8_t)0xFF)            /*!< Divisor latch MSB bit mask */
+#define UART_LOAD_DLM(div)  (((div) >> 8) & 0xFF)    /**< Macro for loading most significant halfs of divisors */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt enable register
+ **********************************************************************/
+#define UART_IER_RBRINT_EN        ((uint32_t)(1<<0))     /*!< RBR Interrupt enable*/
+#define UART_IER_THREINT_EN        ((uint32_t)(1<<1))     /*!< THR Interrupt enable*/
+#define UART_IER_RLSINT_EN        ((uint32_t)(1<<2))     /*!< RX line status interrupt enable*/
+#define UART1_IER_MSINT_EN        ((uint32_t)(1<<3))    /*!< Modem status interrupt enable */
+#define UART1_IER_CTSINT_EN        ((uint32_t)(1<<7))    /*!< CTS1 signal transition interrupt enable */
+#define UART_IER_ABEOINT_EN        ((uint32_t)(1<<8))     /*!< Enables the end of auto-baud interrupt */
+#define UART_IER_ABTOINT_EN        ((uint32_t)(1<<9))     /*!< Enables the auto-baud time-out interrupt */
+#define UART_IER_BITMASK        ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */
+#define UART1_IER_BITMASK        ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt identification register
+ **********************************************************************/
+#define UART_IIR_INTSTAT_PEND    ((uint32_t)(1<<0))    /*!<Interrupt Status - Active low */
+#define UART_IIR_INTID_RLS        ((uint32_t)(3<<1))     /*!<Interrupt identification: Receive line status*/
+#define UART_IIR_INTID_RDA        ((uint32_t)(2<<1))     /*!<Interrupt identification: Receive data available*/
+#define UART_IIR_INTID_CTI        ((uint32_t)(6<<1))     /*!<Interrupt identification: Character time-out indicator*/
+#define UART_IIR_INTID_THRE        ((uint32_t)(1<<1))     /*!<Interrupt identification: THRE interrupt*/
+#define UART1_IIR_INTID_MODEM    ((uint32_t)(0<<1))     /*!<Interrupt identification: Modem interrupt*/
+#define UART_IIR_INTID_MASK        ((uint32_t)(7<<1))    /*!<Interrupt identification: Interrupt ID mask */
+#define UART_IIR_FIFO_EN        ((uint32_t)(3<<6))     /*!<These bits are equivalent to UnFCR[0] */
+#define UART_IIR_ABEO_INT        ((uint32_t)(1<<8))     /*!< End of auto-baud interrupt */
+#define UART_IIR_ABTO_INT        ((uint32_t)(1<<9))     /*!< Auto-baud time-out interrupt */
+#define UART_IIR_BITMASK        ((uint32_t)(0x3CF))    /*!< UART interrupt identification register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART FIFO control register
+ **********************************************************************/
+#define UART_FCR_FIFO_EN        ((uint8_t)(1<<0))     /*!< UART FIFO enable */
+#define UART_FCR_RX_RS            ((uint8_t)(1<<1))     /*!< UART FIFO RX reset */
+#define UART_FCR_TX_RS            ((uint8_t)(1<<2))     /*!< UART FIFO TX reset */
+#define UART_FCR_DMAMODE_SEL     ((uint8_t)(1<<3))     /*!< UART DMA mode selection */
+#define UART_FCR_TRG_LEV0        ((uint8_t)(0))         /*!< UART FIFO trigger level 0: 1 character */
+#define UART_FCR_TRG_LEV1        ((uint8_t)(1<<6))     /*!< UART FIFO trigger level 1: 4 character */
+#define UART_FCR_TRG_LEV2        ((uint8_t)(2<<6))     /*!< UART FIFO trigger level 2: 8 character */
+#define UART_FCR_TRG_LEV3        ((uint8_t)(3<<6))     /*!< UART FIFO trigger level 3: 14 character */
+#define UART_FCR_BITMASK        ((uint8_t)(0xCF))    /*!< UART FIFO control bit mask */
+#define UART_TX_FIFO_SIZE        (16)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line control register
+ **********************************************************************/
+#define UART_LCR_WLEN5             ((uint8_t)(0))           /*!< UART 5 bit data mode */
+#define UART_LCR_WLEN6             ((uint8_t)(1<<0))       /*!< UART 6 bit data mode */
+#define UART_LCR_WLEN7             ((uint8_t)(2<<0))       /*!< UART 7 bit data mode */
+#define UART_LCR_WLEN8             ((uint8_t)(3<<0))       /*!< UART 8 bit data mode */
+#define UART_LCR_STOPBIT_SEL    ((uint8_t)(1<<2))       /*!< UART Two Stop Bits Select */
+#define UART_LCR_PARITY_EN        ((uint8_t)(1<<3))        /*!< UART Parity Enable */
+#define UART_LCR_PARITY_ODD        ((uint8_t)(0))             /*!< UART Odd Parity Select */
+#define UART_LCR_PARITY_EVEN    ((uint8_t)(1<<4))        /*!< UART Even Parity Select */
+#define UART_LCR_PARITY_F_1        ((uint8_t)(2<<4))        /*!< UART force 1 stick parity */
+#define UART_LCR_PARITY_F_0        ((uint8_t)(3<<4))        /*!< UART force 0 stick parity */
+#define UART_LCR_BREAK_EN        ((uint8_t)(1<<6))        /*!< UART Transmission Break enable */
+#define UART_LCR_DLAB_EN        ((uint8_t)(1<<7))        /*!< UART Divisor Latches Access bit enable */
+#define UART_LCR_BITMASK        ((uint8_t)(0xFF))        /*!< UART line control bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 Modem Control Register
+ **********************************************************************/
+#define UART1_MCR_DTR_CTRL        ((uint8_t)(1<<0))        /*!< Source for modem output pin DTR */
+#define UART1_MCR_RTS_CTRL        ((uint8_t)(1<<1))        /*!< Source for modem output pin RTS */
+#define UART1_MCR_LOOPB_EN        ((uint8_t)(1<<4))        /*!< Loop back mode select */
+#define UART1_MCR_AUTO_RTS_EN    ((uint8_t)(1<<6))        /*!< Enable Auto RTS flow-control */
+#define UART1_MCR_AUTO_CTS_EN    ((uint8_t)(1<<7))        /*!< Enable Auto CTS flow-control */
+#define UART1_MCR_BITMASK        ((uint8_t)(0x0F3))        /*!< UART1 bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line status register
+ **********************************************************************/
+#define UART_LSR_RDR        ((uint8_t)(1<<0))     /*!<Line status register: Receive data ready*/
+#define UART_LSR_OE            ((uint8_t)(1<<1))     /*!<Line status register: Overrun error*/
+#define UART_LSR_PE            ((uint8_t)(1<<2))     /*!<Line status register: Parity error*/
+#define UART_LSR_FE            ((uint8_t)(1<<3))     /*!<Line status register: Framing error*/
+#define UART_LSR_BI            ((uint8_t)(1<<4))     /*!<Line status register: Break interrupt*/
+#define UART_LSR_THRE        ((uint8_t)(1<<5))     /*!<Line status register: Transmit holding register empty*/
+#define UART_LSR_TEMT        ((uint8_t)(1<<6))     /*!<Line status register: Transmitter empty*/
+#define UART_LSR_RXFE        ((uint8_t)(1<<7))     /*!<Error in RX FIFO*/
+#define UART_LSR_BITMASK    ((uint8_t)(0xFF))     /*!<UART Line status bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Modem (UART1 only) status register
+ **********************************************************************/
+#define UART1_MSR_DELTA_CTS        ((uint8_t)(1<<0))    /*!< Set upon state change of input CTS */
+#define UART1_MSR_DELTA_DSR        ((uint8_t)(1<<1))    /*!< Set upon state change of input DSR */
+#define UART1_MSR_LO2HI_RI        ((uint8_t)(1<<2))    /*!< Set upon low to high transition of input RI */
+#define UART1_MSR_DELTA_DCD        ((uint8_t)(1<<3))    /*!< Set upon state change of input DCD */
+#define UART1_MSR_CTS            ((uint8_t)(1<<4))    /*!< Clear To Send State */
+#define UART1_MSR_DSR            ((uint8_t)(1<<5))    /*!< Data Set Ready State */
+#define UART1_MSR_RI            ((uint8_t)(1<<6))    /*!< Ring Indicator State */
+#define UART1_MSR_DCD            ((uint8_t)(1<<7))    /*!< Data Carrier Detect State */
+#define UART1_MSR_BITMASK        ((uint8_t)(0xFF))    /*!< MSR register bit-mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Scratch Pad Register
+ **********************************************************************/
+#define UART_SCR_BIMASK        ((uint8_t)(0xFF))    /*!< UART Scratch Pad bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Auto baudrate control register
+ **********************************************************************/
+#define UART_ACR_START                ((uint32_t)(1<<0))    /**< UART Auto-baud start */
+#define UART_ACR_MODE                ((uint32_t)(1<<1))    /**< UART Auto baudrate Mode 1 */
+#define UART_ACR_AUTO_RESTART        ((uint32_t)(1<<2))    /**< UART Auto baudrate restart */
+#define UART_ACR_ABEOINT_CLR        ((uint32_t)(1<<8))    /**< UART End of auto-baud interrupt clear */
+#define UART_ACR_ABTOINT_CLR        ((uint32_t)(1<<9))    /**< UART Auto-baud time-out interrupt clear */
+#define UART_ACR_BITMASK            ((uint32_t)(0x307))    /**< UART Auto Baudrate register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART IrDA control register
+ **********************************************************************/
+#define UART_ICR_IRDAEN            ((uint32_t)(1<<0))            /**< IrDA mode enable */
+#define UART_ICR_IRDAINV        ((uint32_t)(1<<1))            /**< IrDA serial input inverted */
+#define UART_ICR_FIXPULSE_EN    ((uint32_t)(1<<2))            /**< IrDA fixed pulse width mode */
+#define UART_ICR_PULSEDIV(n)    ((uint32_t)((n&0x07)<<3))    /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */
+#define UART_ICR_BITMASK        ((uint32_t)(0x3F))            /*!< UART IRDA bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Fractional divider register
+ **********************************************************************/
+#define UART_FDR_DIVADDVAL(n)    ((uint32_t)(n&0x0F))        /**< Baud-rate generation pre-scaler divisor */
+#define UART_FDR_MULVAL(n)        ((uint32_t)((n<<4)&0xF0))    /**< Baud-rate pre-scaler multiplier value */
+#define UART_FDR_BITMASK        ((uint32_t)(0xFF))            /**< UART Fractional Divider register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Tx Enable register
+ **********************************************************************/
+#define UART_TER_TXEN            ((uint8_t)(1<<7))         /*!< Transmit enable bit */
+#define UART_TER_BITMASK        ((uint8_t)(0x80))        /**< UART Transmit Enable Register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS485 Control register
+ **********************************************************************/
+#define UART1_RS485CTRL_NMM_EN        ((uint32_t)(1<<0))    /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM)
+                                                        is disabled */
+#define UART1_RS485CTRL_RX_DIS        ((uint32_t)(1<<1))    /*!< The receiver is disabled */
+#define UART1_RS485CTRL_AADEN        ((uint32_t)(1<<2))    /*!< Auto Address Detect (AAD) is enabled */
+#define UART1_RS485CTRL_SEL_DTR        ((uint32_t)(1<<3))    /*!< If direction control is enabled
+                                                        (bit DCTRL = 1), pin DTR is used for direction control */
+#define UART1_RS485CTRL_DCTRL_EN    ((uint32_t)(1<<4))    /*!< Enable Auto Direction Control */
+#define UART1_RS485CTRL_OINV_1        ((uint32_t)(1<<5))    /*!< This bit reverses the polarity of the direction
+                                                        control signal on the RTS (or DTR) pin. The direction control pin
+                                                        will be driven to logic "1" when the transmitter has data to be sent */
+#define UART1_RS485CTRL_BITMASK        ((uint32_t)(0x3F))    /**< RS485 control bit-mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS-485 Address Match register
+ **********************************************************************/
+#define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF))     /**< Bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS-485 Delay value register
+ **********************************************************************/
+/* Macro defines for UART1 RS-485 Delay value register */
+#define UART1_RS485DLY_BITMASK        ((uint8_t)(0xFF))     /** Bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART FIFO Level register
+ **********************************************************************/
+#define UART_FIFOLVL_RXFIFOLVL(n)    ((uint32_t)(n&0x0F))        /**< Reflects the current level of the UART receiver FIFO */
+#define UART_FIFOLVL_TXFIFOLVL(n)    ((uint32_t)((n>>8)&0x0F))    /**< Reflects the current level of the UART transmitter FIFO */
+#define UART_FIFOLVL_BITMASK        ((uint32_t)(0x0F0F))        /**< UART FIFO Level Register bit mask */
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+
+/** Macro to check the input UART_DATABIT parameters */
+#define PARAM_UART_DATABIT(databit)    ((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\
+|| (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8))
+
+/** Macro to check the input UART_STOPBIT parameters */
+#define PARAM_UART_STOPBIT(stopbit)    ((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2))
+
+/** Macro to check the input UART_PARITY parameters */
+#define PARAM_UART_PARITY(parity)    ((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \
+|| (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \
+|| (parity==UART_PARITY_SP_0))
+
+/** Macro to check the input UART_FIFO parameters */
+#define PARAM_UART_FIFO_LEVEL(fifo)    ((fifo==UART_FIFO_TRGLEV0) \
+|| (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \
+|| (fifo==UART_FIFO_TRGLEV3))
+
+/** Macro to check the input UART_INTCFG parameters */
+#define PARAM_UART_INTCFG(IntCfg)    ((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \
+|| (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \
+|| (IntCfg==UART_INTCFG_ABTO))
+
+/** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */
+#define PARAM_UART1_INTCFG(IntCfg)    ((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS))
+
+/** Macro to check the input UART_AUTOBAUD_MODE parameters */
+#define PARAM_UART_AUTOBAUD_MODE(ABmode)    ((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1))
+
+/** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */
+#define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat)    ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || \
+        (ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO))
+
+/** Macro to check the input UART_IrDA_PULSEDIV parameters */
+#define PARAM_UART_IrDA_PULSEDIV(PulseDiv)    ((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \
+|| (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \
+|| (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \
+|| (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256))
+
+/* Macro to check the input UART1_SignalState parameters */
+#define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE))
+
+/** Macro to check the input PARAM_UART1_MODEM_PIN parameters */
+#define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS))
+
+/** Macro to check the input PARAM_UART1_MODEM_MODE parameters */
+#define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \
+|| (x==UART1_MODEM_MODE_AUTO_CTS))
+
+/** Macro to check the direction control pin type */
+#define PARAM_UART_RS485_DIRCTRL_PIN(x)    ((x==UART1_RS485_DIRCTRL_RTS) || (x==UART1_RS485_DIRCTRL_DTR))
+
+/* Macro to determine if it is valid UART port number */
+#define PARAM_UARTx(x)    ((((uint32_t *)x)==((uint32_t *)LPC_UART0)) \
+|| (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \
+|| (((uint32_t *)x)==((uint32_t *)LPC_UART2)) \
+|| (((uint32_t *)x)==((uint32_t *)LPC_UART3)))
+#define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_UART3))
+#define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1))
+
+/** Macro to check the input value for UART1_RS485_CFG_MATCHADDRVALUE parameter */
+#define PARAM_UART1_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF))
+
+/** Macro to check the input value for UART1_RS485_CFG_DELAYVALUE parameter */
+#define PARAM_UART1_RS485_CFG_DELAYVALUE(x) ((x<0xFF))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup UART_Public_Types UART Public Types
+ * @{
+ */
+
+/**
+ * @brief UART Databit type definitions
+ */
+typedef enum {
+    UART_DATABIT_5        = 0,             /*!< UART 5 bit data mode */
+    UART_DATABIT_6,                         /*!< UART 6 bit data mode */
+    UART_DATABIT_7,                         /*!< UART 7 bit data mode */
+    UART_DATABIT_8                         /*!< UART 8 bit data mode */
+} UART_DATABIT_Type;
+
+/**
+ * @brief UART Stop bit type definitions
+ */
+typedef enum {
+    UART_STOPBIT_1        = (0),                       /*!< UART 1 Stop Bits Select */
+    UART_STOPBIT_2,                                     /*!< UART Two Stop Bits Select */
+} UART_STOPBIT_Type;
+
+/**
+ * @brief UART Parity type definitions
+ */
+typedef enum {
+    UART_PARITY_NONE     = 0,                    /*!< No parity */
+    UART_PARITY_ODD,                             /*!< Odd parity */
+    UART_PARITY_EVEN,                             /*!< Even parity */
+    UART_PARITY_SP_1,                             /*!< Forced "1" stick parity */
+    UART_PARITY_SP_0                             /*!< Forced "0" stick parity */
+} UART_PARITY_Type;
+
+/**
+ * @brief FIFO Level type definitions
+ */
+typedef enum {
+    UART_FIFO_TRGLEV0 = 0,    /*!< UART FIFO trigger level 0: 1 character */
+    UART_FIFO_TRGLEV1,         /*!< UART FIFO trigger level 1: 4 character */
+    UART_FIFO_TRGLEV2,        /*!< UART FIFO trigger level 2: 8 character */
+    UART_FIFO_TRGLEV3        /*!< UART FIFO trigger level 3: 14 character */
+} UART_FITO_LEVEL_Type;
+
+/********************************************************************//**
+* @brief UART Interrupt Type definitions
+**********************************************************************/
+typedef enum {
+    UART_INTCFG_RBR = 0,    /*!< RBR Interrupt enable*/
+    UART_INTCFG_THRE,        /*!< THR Interrupt enable*/
+    UART_INTCFG_RLS,        /*!< RX line status interrupt enable*/
+    UART1_INTCFG_MS,        /*!< Modem status interrupt enable (UART1 only) */
+    UART1_INTCFG_CTS,        /*!< CTS1 signal transition interrupt enable (UART1 only) */
+    UART_INTCFG_ABEO,        /*!< Enables the end of auto-baud interrupt */
+    UART_INTCFG_ABTO        /*!< Enables the auto-baud time-out interrupt */
+} UART_INT_Type;
+
+/**
+ * @brief UART Line Status Type definition
+ */
+typedef enum {
+    UART_LINESTAT_RDR    = UART_LSR_RDR,            /*!<Line status register: Receive data ready*/
+    UART_LINESTAT_OE    = UART_LSR_OE,            /*!<Line status register: Overrun error*/
+    UART_LINESTAT_PE    = UART_LSR_PE,            /*!<Line status register: Parity error*/
+    UART_LINESTAT_FE    = UART_LSR_FE,            /*!<Line status register: Framing error*/
+    UART_LINESTAT_BI    = UART_LSR_BI,            /*!<Line status register: Break interrupt*/
+    UART_LINESTAT_THRE    = UART_LSR_THRE,        /*!<Line status register: Transmit holding register empty*/
+    UART_LINESTAT_TEMT    = UART_LSR_TEMT,        /*!<Line status register: Transmitter empty*/
+    UART_LINESTAT_RXFE    = UART_LSR_RXFE            /*!<Error in RX FIFO*/
+} UART_LS_Type;
+
+/**
+ * @brief UART Auto-baudrate mode type definition
+ */
+typedef enum {
+    UART_AUTOBAUD_MODE0                = 0,            /**< UART Auto baudrate Mode 0 */
+    UART_AUTOBAUD_MODE1,                            /**< UART Auto baudrate Mode 1 */
+} UART_AB_MODE_Type;
+
+/**
+ * @brief Auto Baudrate mode configuration type definition
+ */
+typedef struct {
+    UART_AB_MODE_Type    ABMode;            /**< Autobaudrate mode */
+    FunctionalState        AutoRestart;    /**< Auto Restart state */
+} UART_AB_CFG_Type;
+
+/**
+ * @brief UART End of Auto-baudrate type definition
+ */
+typedef enum {
+    UART_AUTOBAUD_INTSTAT_ABEO        = UART_IIR_ABEO_INT,        /**< UART End of auto-baud interrupt  */
+    UART_AUTOBAUD_INTSTAT_ABTO        = UART_IIR_ABTO_INT            /**< UART Auto-baud time-out interrupt  */
+}UART_ABEO_Type;
+
+/**
+ * UART IrDA Control type Definition
+ */
+typedef enum {
+    UART_IrDA_PULSEDIV2        = 0,        /**< Pulse width = 2 * Tpclk
+                                        - Configures the pulse when FixPulseEn = 1 */
+    UART_IrDA_PULSEDIV4,                /**< Pulse width = 4 * Tpclk
+                                        - Configures the pulse when FixPulseEn = 1 */
+    UART_IrDA_PULSEDIV8,                /**< Pulse width = 8 * Tpclk
+                                        - Configures the pulse when FixPulseEn = 1 */
+    UART_IrDA_PULSEDIV16,                /**< Pulse width = 16 * Tpclk
+                                        - Configures the pulse when FixPulseEn = 1 */
+    UART_IrDA_PULSEDIV32,                /**< Pulse width = 32 * Tpclk
+                                        - Configures the pulse when FixPulseEn = 1 */
+    UART_IrDA_PULSEDIV64,                /**< Pulse width = 64 * Tpclk
+                                        - Configures the pulse when FixPulseEn = 1 */
+    UART_IrDA_PULSEDIV128,                /**< Pulse width = 128 * Tpclk
+                                        - Configures the pulse when FixPulseEn = 1 */
+    UART_IrDA_PULSEDIV256                /**< Pulse width = 256 * Tpclk
+                                        - Configures the pulse when FixPulseEn = 1 */
+} UART_IrDA_PULSE_Type;
+
+/********************************************************************//**
+* @brief UART1 Full modem -  Signal states definition
+**********************************************************************/
+typedef enum {
+    INACTIVE = 0,            /* In-active state */
+    ACTIVE = !INACTIVE         /* Active state */
+}UART1_SignalState;
+
+/**
+ * @brief UART modem status type definition
+ */
+typedef enum {
+    UART1_MODEM_STAT_DELTA_CTS    = UART1_MSR_DELTA_CTS,        /*!< Set upon state change of input CTS */
+    UART1_MODEM_STAT_DELTA_DSR    = UART1_MSR_DELTA_DSR,        /*!< Set upon state change of input DSR */
+    UART1_MODEM_STAT_LO2HI_RI    = UART1_MSR_LO2HI_RI,        /*!< Set upon low to high transition of input RI */
+    UART1_MODEM_STAT_DELTA_DCD    = UART1_MSR_DELTA_DCD,        /*!< Set upon state change of input DCD */
+    UART1_MODEM_STAT_CTS        = UART1_MSR_CTS,            /*!< Clear To Send State */
+    UART1_MODEM_STAT_DSR        = UART1_MSR_DSR,            /*!< Data Set Ready State */
+    UART1_MODEM_STAT_RI            = UART1_MSR_RI,                /*!< Ring Indicator State */
+    UART1_MODEM_STAT_DCD        = UART1_MSR_DCD                /*!< Data Carrier Detect State */
+} UART_MODEM_STAT_type;
+
+/**
+ * @brief Modem output pin type definition
+ */
+typedef enum {
+    UART1_MODEM_PIN_DTR            = 0,        /*!< Source for modem output pin DTR */
+    UART1_MODEM_PIN_RTS                        /*!< Source for modem output pin RTS */
+} UART_MODEM_PIN_Type;
+
+/**
+ * @brief UART Modem mode type definition
+ */
+typedef enum {
+    UART1_MODEM_MODE_LOOPBACK    = 0,        /*!< Loop back mode select */
+    UART1_MODEM_MODE_AUTO_RTS,                /*!< Enable Auto RTS flow-control */
+    UART1_MODEM_MODE_AUTO_CTS                 /*!< Enable Auto CTS flow-control */
+} UART_MODEM_MODE_Type;
+
+/**
+ * @brief UART Direction Control Pin type definition
+ */
+typedef enum {
+    UART1_RS485_DIRCTRL_RTS = 0,    /**< Pin RTS is used for direction control */
+    UART1_RS485_DIRCTRL_DTR            /**< Pin DTR is used for direction control */
+} UART_RS485_DIRCTRL_PIN_Type;
+
+/********************************************************************//**
+* @brief UART Configuration Structure definition
+**********************************************************************/
+typedef struct {
+  uint32_t Baud_rate;           /**< UART baud rate */
+  UART_PARITY_Type Parity;        /**< Parity selection, should be:
+                               - UART_PARITY_NONE: No parity
+                               - UART_PARITY_ODD: Odd parity
+                               - UART_PARITY_EVEN: Even parity
+                               - UART_PARITY_SP_1: Forced "1" stick parity
+                               - UART_PARITY_SP_0: Forced "0" stick parity
+                               */
+  UART_DATABIT_Type Databits;   /**< Number of data bits, should be:
+                               - UART_DATABIT_5: UART 5 bit data mode
+                               - UART_DATABIT_6: UART 6 bit data mode
+                               - UART_DATABIT_7: UART 7 bit data mode
+                               - UART_DATABIT_8: UART 8 bit data mode
+                               */
+  UART_STOPBIT_Type Stopbits;   /**< Number of stop bits, should be:
+                               - UART_STOPBIT_1: UART 1 Stop Bits Select
+                               - UART_STOPBIT_2: UART 2 Stop Bits Select
+                               */
+} UART_CFG_Type;
+
+/********************************************************************//**
+* @brief UART FIFO Configuration Structure definition
+**********************************************************************/
+
+typedef struct {
+    FunctionalState FIFO_ResetRxBuf;    /**< Reset Rx FIFO command state , should be:
+                                         - ENABLE: Reset Rx FIFO in UART
+                                         - DISABLE: Do not reset Rx FIFO  in UART
+                                         */
+    FunctionalState FIFO_ResetTxBuf;    /**< Reset Tx FIFO command state , should be:
+                                         - ENABLE: Reset Tx FIFO in UART
+                                         - DISABLE: Do not reset Tx FIFO  in UART
+                                         */
+    FunctionalState FIFO_DMAMode;        /**< DMA mode, should be:
+                                         - ENABLE: Enable DMA mode in UART
+                                         - DISABLE: Disable DMA mode in UART
+                                         */
+    UART_FITO_LEVEL_Type FIFO_Level;    /**< Rx FIFO trigger level, should be:
+                                        - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
+                                        - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
+                                        - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
+                                        - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
+                                        */
+} UART_FIFO_CFG_Type;
+
+/********************************************************************//**
+* @brief UART1 Full modem -  RS485 Control configuration type
+**********************************************************************/
+typedef struct {
+    FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
+                                                    - ENABLE: Enable this function.
+                                                    - DISABLE: Disable this function. */
+    FunctionalState Rx_State;                    /*!< Receiver State:
+                                                    - ENABLE: Enable Receiver.
+                                                    - DISABLE: Disable Receiver. */
+    FunctionalState AutoAddrDetect_State;        /*!< Auto Address Detect mode state:
+                                                - ENABLE: ENABLE this function.
+                                                - DISABLE: Disable this function. */
+    FunctionalState AutoDirCtrl_State;            /*!< Auto Direction Control State:
+                                                - ENABLE: Enable this function.
+                                                - DISABLE: Disable this function. */
+    UART_RS485_DIRCTRL_PIN_Type DirCtrlPin;        /*!< If direction control is enabled, state:
+                                                - UART1_RS485_DIRCTRL_RTS:
+                                                pin RTS is used for direction control.
+                                                - UART1_RS485_DIRCTRL_DTR:
+                                                pin DTR is used for direction control. */
+     SetState DirCtrlPol_Level;                    /*!< Polarity of the direction control signal on
+                                                the RTS (or DTR) pin:
+                                                - RESET: The direction control pin will be driven
+                                                to logic "0" when the transmitter has data to be sent.
+                                                - SET: The direction control pin will be driven
+                                                to logic "1" when the transmitter has data to be sent. */
+    uint8_t MatchAddrValue;                    /*!< address match value for RS-485/EIA-485 mode, 8-bit long */
+    uint8_t DelayValue;                        /*!< delay time is in periods of the baud clock, 8-bit long */
+} UART1_RS485_CTRLCFG_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup UART_Public_Functions UART Public Functions
+ * @{
+ */
+/* UART Init/DeInit functions --------------------------------------------------*/
+void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct);
+void UART_DeInit(LPC_UART_TypeDef* UARTx);
+void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
+
+/* UART Send/Receive functions -------------------------------------------------*/
+void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data);
+uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx);
+uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf,
+        uint32_t buflen, TRANSFER_BLOCK_Type flag);
+uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \
+        uint32_t buflen, TRANSFER_BLOCK_Type flag);
+
+/* UART FIFO functions ----------------------------------------------------------*/
+void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg);
+void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
+
+/* UART get information functions -----------------------------------------------*/
+uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx);
+uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx);
+
+/* UART operate functions -------------------------------------------------------*/
+void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \
+                FunctionalState NewState);
+void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState);
+FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx);
+void UART_ForceBreak(LPC_UART_TypeDef* UARTx);
+
+/* UART Auto-baud functions -----------------------------------------------------*/
+void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType);
+void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
+                FunctionalState NewState);
+
+/* UART1 FullModem functions ----------------------------------------------------*/
+void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \
+                            UART1_SignalState NewState);
+void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \
+                            FunctionalState NewState);
+uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx);
+
+/* UART RS485 functions ----------------------------------------------------------*/
+void UART_RS485Config(LPC_UART1_TypeDef *UARTx, \
+        UART1_RS485_CTRLCFG_Type *RS485ConfigStruct);
+void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState);
+void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr);
+uint32_t UART_RS485SendData(LPC_UART1_TypeDef *UARTx, uint8_t *pData, uint32_t size);
+
+/* UART IrDA functions-------------------------------------------------------------*/
+void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
+void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
+void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv);
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __LPC17XX_UART_H */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff -r 000000000000 -r d920d64db582 I2S_Example/lpc_types.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/lpc_types.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,207 @@
+/***********************************************************************//**
+ * @file        lpc_types.h
+ * @brief        Contains the NXP ABL typedefs for C standard types.
+ *                 It is intended to be used in ISO C conforming development
+ *                 environments and checks for this insofar as it is possible
+ *                 to do so.
+ * @version        1.0
+ * @date        27 Jul. 2008
+ * @author        wellsk
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Type group ----------------------------------------------------------- */
+/** @defgroup LPC_Types LPC_Types
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC_TYPES_H
+#define LPC_TYPES_H
+
+/* Includes ------------------------------------------------------------------- */
+#include <stdint.h>
+#include "mbed.h"
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Types LPC_Types Public Types
+ * @{
+ */
+
+/**
+ * @brief Boolean Type definition
+ */
+
+//typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
+#ifndef Bool
+#   define Bool int
+#endif
+#ifndef TRUE
+#   define TRUE 1
+#endif
+#ifndef FALSE
+#   define FALSE 0
+#endif
+
+/**
+ * @brief Flag Status and Interrupt Flag Status type definition
+ */
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
+#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
+
+/**
+ * @brief Functional State Definition
+ */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
+
+/**
+ * @ Status type definition
+ */
+typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
+
+
+/**
+ * Read/Write transfer type mode (Block or non-block)
+ */
+typedef enum
+{
+    NONE_BLOCKING = 0,        /**< None Blocking type */
+    BLOCKING,                /**< Blocking type */
+} TRANSFER_BLOCK_Type;
+
+
+/** Pointer to Function returning Void (any number of parameters) */
+typedef void (*PFV)();
+
+/** Pointer to Function returning int32_t (any number of parameters) */
+typedef int32_t(*PFI)();
+
+/**
+ * @}
+ */
+
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Macros  LPC_Types Public Macros
+ * @{
+ */
+
+/* _BIT(n) sets the bit at position "n"
+ * _BIT(n) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "(_BIT(3) | _BIT(7))".
+ */
+#undef _BIT
+/* Set bit macro */
+#define _BIT(n)    (1<<n)
+
+/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
+ * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
+ */
+#undef _SBF
+/* Set bit field macro */
+#define _SBF(f,v) (v<<f)
+
+/* _BITMASK constructs a symbol with 'field_width' least significant
+ * bits set.
+ * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
+ * The symbol is intended to be used to limit the bit field width
+ * thusly:
+ * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
+ * If "any_expression" results in a value that is larger than can be
+ * contained in 'x' bits, the bits above 'x - 1' are masked off.  When
+ * used with the _SBF example above, the example would be written:
+ * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
+ * This ensures that the value written to a_reg is no wider than
+ * 16 bits, and makes the code easier to read and understand.
+ */
+#undef _BITMASK
+/* Bitmask creation macro */
+#define _BITMASK(field_width) ( _BIT(field_width) - 1)
+
+/* NULL pointer */
+#ifndef NULL
+#define NULL ((void*) 0)
+#endif
+
+/* Number of elements in an array */
+#define NELEMENTS(array)  (sizeof (array) / sizeof (array[0]))
+
+/* Static data/function define */
+#define STATIC static
+/* External data/function define */
+#define EXTERN extern
+
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+
+/**
+ * @}
+ */
+
+
+/* Old Type Definition compatibility ------------------------------------------ */
+/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
+ * @{
+ */
+
+/** SMA type for character type */
+//typedef char CHAR;
+
+/** SMA type for 8 bit unsigned value */
+typedef uint8_t UNS_8;
+
+/** SMA type for 8 bit signed value */
+typedef int8_t INT_8;
+
+/** SMA type for 16 bit unsigned value */
+typedef    uint16_t UNS_16;
+
+/** SMA type for 16 bit signed value */
+typedef    int16_t INT_16;
+
+/** SMA type for 32 bit unsigned value */
+typedef    uint32_t UNS_32;
+
+/** SMA type for 32 bit signed value */
+typedef    int32_t INT_32;
+
+/** SMA type for 64 bit signed value */
+typedef int64_t INT_64;
+
+/** SMA type for 64 bit unsigned value */
+typedef uint64_t UNS_64;
+
+/** 32 bit boolean type */
+typedef Bool BOOL_32;
+
+/** 16 bit boolean type */
+typedef Bool BOOL_16;
+
+/** 8 bit boolean type */
+typedef Bool BOOL_8;
+
+/**
+ * @}
+ */
+
+
+#endif /* LPC_TYPES_H */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff -r 000000000000 -r d920d64db582 I2S_Example/system_LPC17xx.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/system_LPC17xx.c	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,532 @@
+/**************************************************************************//**
+ * @file     system_LPC17xx.c
+ * @brief    CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+ *           for the NXP LPC17xx Device Series
+ * @version  V1.03
+ * @date     07. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "LPC17xx.h"
+
+
+/** @addtogroup LPC17xx_System
+ * @{
+ */
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+//   <h> System Controls and Status Register (SCS)
+//     <o1.4>    OSCRANGE: Main Oscillator Range Select
+//                     <0=>  1 MHz to 20 MHz
+//                     <1=> 15 MHz to 24 MHz
+//     <e1.5>       OSCEN: Main Oscillator Enable
+//     </e>
+//   </h>
+//
+//   <h> Clock Source Select Register (CLKSRCSEL)
+//     <o2.0..1>   CLKSRC: PLL Clock Source Selection
+//                     <0=> Internal RC oscillator
+//                     <1=> Main oscillator
+//                     <2=> RTC oscillator
+//   </h>
+//
+//   <e3> PLL0 Configuration (Main PLL)
+//     <h> PLL0 Configuration Register (PLL0CFG)
+//                     <i> F_cco0 = (2 * M * F_in) / N
+//                     <i> F_in must be in the range of 32 kHz to 50 MHz
+//                     <i> F_cco0 must be in the range of 275 MHz to 550 MHz
+//       <o4.0..14>  MSEL: PLL Multiplier Selection
+//                     <6-32768><#-1>
+//                     <i> M Value
+//       <o4.16..23> NSEL: PLL Divider Selection
+//                     <1-256><#-1>
+//                     <i> N Value
+//     </h>
+//   </e>
+//
+//   <e5> PLL1 Configuration (USB PLL)
+//     <h> PLL1 Configuration Register (PLL1CFG)
+//                     <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
+//                     <i> F_cco1 = F_osc * M * 2 * P
+//                     <i> F_cco1 must be in the range of 156 MHz to 320 MHz
+//       <o6.0..4>   MSEL: PLL Multiplier Selection
+//                     <1-32><#-1>
+//                     <i> M Value (for USB maximum value is 4)
+//       <o6.5..6>   PSEL: PLL Divider Selection
+//                     <0=> 1
+//                     <1=> 2
+//                     <2=> 4
+//                     <3=> 8
+//                     <i> P Value
+//     </h>
+//   </e>
+//
+//   <h> CPU Clock Configuration Register (CCLKCFG)
+//     <o7.0..7>  CCLKSEL: Divide Value for CPU Clock from PLL0
+//                     <3-256><#-1>
+//   </h>
+//
+//   <h> USB Clock Configuration Register (USBCLKCFG)
+//     <o8.0..3>   USBSEL: Divide Value for USB Clock from PLL0
+//                     <0-15>
+//                     <i> Divide is USBSEL + 1
+//   </h>
+//
+//   <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
+//     <o9.0..1>    PCLK_WDT: Peripheral Clock Selection for WDT
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.2..3>    PCLK_TIMER0: Peripheral Clock Selection for TIMER0
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.4..5>    PCLK_TIMER1: Peripheral Clock Selection for TIMER1
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.6..7>    PCLK_UART0: Peripheral Clock Selection for UART0
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.8..9>    PCLK_UART1: Peripheral Clock Selection for UART1
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.12..13>  PCLK_PWM1: Peripheral Clock Selection for PWM1
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.14..15>  PCLK_I2C0: Peripheral Clock Selection for I2C0
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.16..17>  PCLK_SPI: Peripheral Clock Selection for SPI
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.20..21>  PCLK_SSP1: Peripheral Clock Selection for SSP1
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.22..23>  PCLK_DAC: Peripheral Clock Selection for DAC
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.24..25>  PCLK_ADC: Peripheral Clock Selection for ADC
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.26..27>  PCLK_CAN1: Peripheral Clock Selection for CAN1
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 6
+//     <o9.28..29>  PCLK_CAN2: Peripheral Clock Selection for CAN2
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 6
+//     <o9.30..31>  PCLK_ACF: Peripheral Clock Selection for ACF
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 6
+//   </h>
+//
+//   <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
+//     <o10.0..1>   PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.2..3>   PCLK_GPIO: Peripheral Clock Selection for GPIOs
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.4..5>   PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.6..7>   PCLK_I2C1: Peripheral Clock Selection for I2C1
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//   </h>
+//
+//   <h> Power Control for Peripherals Register (PCONP)
+//     <o11.1>      PCTIM0: Timer/Counter 0 power/clock enable
+//     <o11.2>      PCTIM1: Timer/Counter 1 power/clock enable
+//     <o11.3>      PCUART0: UART 0 power/clock enable
+//     <o11.4>      PCUART1: UART 1 power/clock enable
+//     <o11.6>      PCPWM1: PWM 1 power/clock enable
+//     <o11.7>      PCI2C0: I2C interface 0 power/clock enable
+//     <o11.8>      PCSPI: SPI interface power/clock enable
+//     <o11.9>      PCRTC: RTC power/clock enable
+//     <o11.10>     PCSSP1: SSP interface 1 power/clock enable
+//     <o11.12>     PCAD: A/D converter power/clock enable
+//     <o11.13>     PCCAN1: CAN controller 1 power/clock enable
+//     <o11.14>     PCCAN2: CAN controller 2 power/clock enable
+//     <o11.15>     PCGPIO: GPIOs power/clock enable
+//     <o11.16>     PCRIT: Repetitive interrupt timer power/clock enable
+//     <o11.17>     PCMC: Motor control PWM power/clock enable
+//     <o11.18>     PCQEI: Quadrature encoder interface power/clock enable
+//     <o11.19>     PCI2C1: I2C interface 1 power/clock enable
+//     <o11.21>     PCSSP0: SSP interface 0 power/clock enable
+//     <o11.22>     PCTIM2: Timer 2 power/clock enable
+//     <o11.23>     PCTIM3: Timer 3 power/clock enable
+//     <o11.24>     PCUART2: UART 2 power/clock enable
+//     <o11.25>     PCUART3: UART 3 power/clock enable
+//     <o11.26>     PCI2C2: I2C interface 2 power/clock enable
+//     <o11.27>     PCI2S: I2S interface power/clock enable
+//     <o11.29>     PCGPDMA: GP DMA function power/clock enable
+//     <o11.30>     PCENET: Ethernet block power/clock enable
+//     <o11.31>     PCUSB: USB interface power/clock enable
+//   </h>
+//
+//   <h> Clock Output Configuration Register (CLKOUTCFG)
+//     <o12.0..3>   CLKOUTSEL: Selects clock source for CLKOUT
+//                     <0=> CPU clock
+//                     <1=> Main oscillator
+//                     <2=> Internal RC oscillator
+//                     <3=> USB clock
+//                     <4=> RTC oscillator
+//     <o12.4..7>   CLKOUTDIV: Selects clock divider for CLKOUT
+//                     <1-16><#-1>
+//     <o12.8>      CLKOUT_EN: CLKOUT enable control
+//   </h>
+//
+// </e>
+*/
+
+
+
+/** @addtogroup LPC17xx_System_Defines  LPC17xx System Defines
+  @{
+ */
+
+#define CLOCK_SETUP           1
+#define SCS_Val               0x00000020
+#define CLKSRCSEL_Val         0x00000001
+#define PLL0_SETUP            1
+#define PLL0CFG_Val           0x00050063
+#define PLL1_SETUP            1
+#define PLL1CFG_Val           0x00000023
+#define CCLKCFG_Val           0x00000003
+#define USBCLKCFG_Val         0x00000000
+#define PCLKSEL0_Val          0x00000000
+#define PCLKSEL1_Val          0x00000000
+#define PCONP_Val             0x042887DE
+#define CLKOUTCFG_Val         0x00000000
+
+
+/*--------------------- Flash Accelerator Configuration ----------------------
+//
+// <e> Flash Accelerator Configuration
+//   <o1.0..11>  Reserved
+//   <o1.12..15> FLASHTIM: Flash Access Time
+//               <0=> 1 CPU clock (for CPU clock up to 20 MHz)
+//               <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
+//               <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
+//               <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
+//               <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
+//               <5=> 6 CPU clocks (for any CPU clock)
+// </e>
+*/
+#define FLASH_SETUP           1
+#define FLASHCFG_Val          0x0000303A
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+  Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask)                     (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SCS_Val),       ~0x00000030))
+   #error "SCS: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
+   #error "CLKSRCSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((PLL0CFG_Val),   ~0x00FF7FFF))
+   #error "PLL0CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F))
+   #error "PLL1CFG: Invalid values of reserved bits!"
+#endif
+
+#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
+   #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
+#endif
+
+#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
+   #error "USBCLKCFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL0_Val),   0x000C0C00))
+   #error "PCLKSEL0: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL1_Val),   0x03000300))
+   #error "PCLKSEL1: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCONP_Val),      0x10100821))
+   #error "PCONP: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
+   #error "CLKOUTCFG: Invalid values of reserved bits!"
+#endif
+
+/* Flash Accelerator Configuration -------------------------------------------*/
+#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
+   #error "FLASHCFG: Invalid values of reserved bits!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL        (12000000UL)        /* Oscillator frequency               */
+#define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
+#define RTC_CLK     (   32768UL)        /* RTC oscillator frequency           */
+#define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */
+
+
+/* F_cco0 = (2 * M * F_in) / N  */
+#define __M               (((PLL0CFG_Val      ) & 0x7FFF) + 1)
+#define __N               (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
+#define __FCCO(__F_IN)    ((2 * __M * __F_IN) / __N)
+#define __CCLK_DIV        (((CCLKCFG_Val      ) & 0x00FF) + 1)
+
+/* Determine core clock frequency according to settings */
+ #if (PLL0_SETUP)
+    #if   ((CLKSRCSEL_Val & 0x03) == 1)
+        #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
+    #elif ((CLKSRCSEL_Val & 0x03) == 2)
+        #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
+    #else
+        #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
+    #endif
+ #else
+    #if   ((CLKSRCSEL_Val & 0x03) == 1)
+        #define __CORE_CLK (OSC_CLK         / __CCLK_DIV)
+    #elif ((CLKSRCSEL_Val & 0x03) == 2)
+        #define __CORE_CLK (RTC_CLK         / __CCLK_DIV)
+    #else
+        #define __CORE_CLK (IRC_OSC         / __CCLK_DIV)
+    #endif
+ #endif
+
+ /**
+  * @}
+  */
+
+
+/** @addtogroup LPC17xx_System_Public_Variables  LPC17xx System Public Variables
+  @{
+ */
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+//uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup LPC17xx_System_Public_Functions  LPC17xx System Public Functions
+  @{
+ */
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+
+
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+ /*
+void SystemInit (void)
+{
+#if (CLOCK_SETUP)                       // Clock Setup                        
+  LPC_SC->SCS       = SCS_Val;
+  if (LPC_SC->SCS & (1 << 5)) {             // If Main Oscillator is enabled  
+    while ((LPC_SC->SCS & (1<<6)) == 0);// Wait for Oscillator to be ready    
+  }
+
+  LPC_SC->CCLKCFG   = CCLKCFG_Val;      // Setup Clock Divider                
+
+  LPC_SC->PCLKSEL0  = PCLKSEL0_Val;     // Peripheral Clock Selection         
+  LPC_SC->PCLKSEL1  = PCLKSEL1_Val;
+
+#if (PLL0_SETUP)
+  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    // Select Clock Source for PLL0       
+
+  LPC_SC->PLL0CFG   = PLL0CFG_Val;      // configure PLL0                     
+  LPC_SC->PLL0FEED  = 0xAA;
+  LPC_SC->PLL0FEED  = 0x55;
+
+  LPC_SC->PLL0CON   = 0x01;             // PLL0 Enable                        
+  LPC_SC->PLL0FEED  = 0xAA;
+  LPC_SC->PLL0FEED  = 0x55;
+  while (!(LPC_SC->PLL0STAT & (1<<26)));// Wait for PLOCK0                    
+
+  LPC_SC->PLL0CON   = 0x03;             // PLL0 Enable & Connect              
+  LPC_SC->PLL0FEED  = 0xAA;
+  LPC_SC->PLL0FEED  = 0x55;
+  while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));//Wait for PLLC0_STAT & PLLE0_STAT 
+#endif
+
+#if (PLL1_SETUP)
+  LPC_SC->PLL1CFG   = PLL1CFG_Val;
+  LPC_SC->PLL1FEED  = 0xAA;
+  LPC_SC->PLL1FEED  = 0x55;
+
+  LPC_SC->PLL1CON   = 0x01;             // PLL1 Enable                        
+  LPC_SC->PLL1FEED  = 0xAA;
+  LPC_SC->PLL1FEED  = 0x55;
+  while (!(LPC_SC->PLL1STAT & (1<<10)));// Wait for PLOCK1                    
+
+  LPC_SC->PLL1CON   = 0x03;             // PLL1 Enable & Connect              
+  LPC_SC->PLL1FEED  = 0xAA;
+  LPC_SC->PLL1FEED  = 0x55;
+  while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));// Wait for PLLC1_STAT & PLLE1_STAT 
+#else
+  LPC_SC->USBCLKCFG = USBCLKCFG_Val;    // Setup USB Clock Divider            
+#endif
+  LPC_SC->PCONP     = PCONP_Val;        // Power Control for Peripherals      
+
+  LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    // Clock Output Configuration         
+#endif
+
+#if (FLASH_SETUP == 1)                  // Flash Accelerator Setup            
+  LPC_SC->FLASHCFG  = FLASHCFG_Val;
+#endif
+
+//  Set Vector table offset value
+#if (__RAM_MODE__==1)
+  SCB->VTOR  = 0x10000000 & 0x3FFFFF80;
+#else
+  SCB->VTOR  = 0x00000000 & 0x3FFFFF80;
+#endif
+}
+
+*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff -r 000000000000 -r d920d64db582 I2S_Example/system_LPC17xx.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/I2S_Example/system_LPC17xx.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,72 @@
+/**************************************************************************//**
+ * @file     system_LPC17xx.h
+ * @brief    CMSIS Cortex-M3 Device Peripheral Access Layer Header File
+ *           for the NXP LPC17xx Device Series
+ * @version  V1.02
+ * @date     08. September 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC17xx_H
+#define __SYSTEM_LPC17xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/** @addtogroup LPC17xx_System
+ * @{
+ */
+
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* __SYSTEM_LPC17xx_H */
diff -r 000000000000 -r d920d64db582 Lossless_lib/_bitio.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Lossless_lib/_bitio.cpp	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,71 @@
+#include "mbed.h"
+#include "string"
+#include "_bitio.h"
+
+
+//FILE *infp, *outfp;
+int     getcount, putcount;
+int     bitbuf;
+
+
+void init_bit_o(void)
+{
+    putcount = 8; bitbuf = 0;
+}
+
+void init_bit_i(void)
+{
+    getcount = 0; bitbuf = 0;
+}
+
+
+Uint getbit(void)
+{
+    int flag;
+    if (--getcount >= 0)  return (bitbuf >> getcount) & 1U;
+    getcount = 7;
+    if((flag = fgetc(infp))==EOF)return OVERRUN;
+    else bitbuf = flag;
+    return (bitbuf >> 7) & 1U;
+}
+
+Uint getbits(int n)
+{
+    Uint x = 0;
+    if (n < 1 || 25 < n)  return 0;
+    while (n > getcount) {
+        n -= getcount;
+        x |= rightbits(getcount, bitbuf) << n;
+        bitbuf = fgetc(infp); 
+        getcount = 8;
+    }
+    getcount -= n;
+    return x | rightbits(n, bitbuf >> getcount);
+}
+
+
+void putbit(Uint bit)
+{
+    putcount--;
+    if (bit != 0)  bitbuf |= (1 << putcount);
+    if (putcount == 0) {
+        if (fputc(bitbuf, outfp) == EOF)  error("can't write\r\n");
+        bitbuf = 0; putcount = 8;
+    }
+}
+
+
+void putbits(int n, Uint x)
+{
+    if (n < 1 || 25 < n)  return;
+    while (n >= putcount) {
+        n -= putcount;
+        bitbuf |= rightbits(putcount, x >> n);
+        if (fputc(bitbuf, outfp) == EOF)  error("cant write\r\n");
+        bitbuf = 0U; 
+        putcount = 8;
+    }
+    putcount -= n;
+    bitbuf |= rightbits(n, x) << putcount;
+}
+
diff -r 000000000000 -r d920d64db582 Lossless_lib/_bitio.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Lossless_lib/_bitio.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,33 @@
+#ifndef    ___BITIO_H__
+#define    ___BITIO_H__
+/*
+#define TRUE     1
+#define FALSE    0
+*/
+#define rightbits(n, x) ((x) & ((1U << (n)) - 1U)) 
+
+#define OVERRUN 0xffff
+#define _lsb_k 0x0b //    _lsb_k:0x09 to 0x0b?    
+
+typedef unsigned int  Uint;
+typedef unsigned char Uchar;
+
+extern FILE *infp, *outfp;
+extern int  getcount, putcount;
+extern int  bitbuf;
+
+/* Rice Golomb en-decoding */
+extern void decode(void);
+extern void encode(long int n);
+
+
+void init_bit_o(void);
+void init_bit_i(void);
+Uint getbit(void);
+Uint getbits(int n);
+void putbit(Uint bit);
+void putbits(int n, Uint x);
+
+
+
+#endif
\ No newline at end of file
diff -r 000000000000 -r d920d64db582 MSCFileSystem.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/MSCFileSystem.cpp	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,113 @@
+/* USB Mass Storage device file system
+ * Copyrigh (c) 2010, Igor Skochinsky
+ * based on SDFileStorage
+ * Copyright (c) 2008-2009, sford
+ */
+ 
+/* Introduction
+ * ------------
+ * TODO: write one
+ * we're basically using NXP's USBHotLite sample code, just plugging in our own FAT library
+ */
+ 
+#include "MSCFileSystem.h"
+#include "usbhost_inc.h"
+
+MSCFileSystem::MSCFileSystem(const char* name) :
+  FATFileSystem(name)
+{
+}
+
+void print_inquiry(USB_INT08U *inqReply)
+{
+    // see USB Mass Storage Class &#8211; UFI Command Specification,
+    // 4.2 INQUIRY Command
+    printf("Inquiry reply:\n");
+    uint8_t tmp = inqReply[0]&0x1F;
+    printf("Peripheral device type: %02Xh\n", tmp);
+    if ( tmp == 0 )
+        printf("\t- Direct access (floppy)\n");
+    else if ( tmp == 0x1F )
+        printf("\t- none (no FDD connected)\n");
+    else
+        printf("\t- unknown type\n");
+    tmp = inqReply[1] >> 7;
+    printf("Removable Media Bit: %d\n", tmp);
+    tmp = inqReply[2] & 3;
+    printf("ANSI Version: %02Xh\n", tmp);
+    if ( tmp != 0 )
+        printf("\t- warning! must be 0\n");
+    tmp = (inqReply[2]>>3) & 3;
+    printf("ECMA Version: %02Xh\n", tmp);
+    if ( tmp != 0 )
+        printf("\t- warning! should be 0\n");
+    tmp = inqReply[2]>>6;
+    printf("ISO Version: %02Xh\n", tmp);
+    if ( tmp != 0 )
+        printf("\t- warning! should be 0\n");
+    tmp = inqReply[3] & 0xF;
+    printf("Response Data Format: %02Xh\n", tmp);
+    if ( tmp != 1 )
+        printf("\t- warning! should be 1\n");
+    tmp = inqReply[4];
+    printf("Additional length: %02Xh\n", tmp);
+    if ( tmp != 0x1F )
+        printf("\t- warning! should be 1Fh\n");
+    printf("Vendor Information: '%.8s'\n", &inqReply[8]);
+    printf("Product Identification: '%.16s'\n", &inqReply[16]);
+    printf("Product Revision: '%.4s'\n", &inqReply[32]);        
+}
+
+int MSCFileSystem::initialise_msc()
+{
+    USB_INT32S  rc;
+    USB_INT08U  inquiryResult[INQUIRY_LENGTH];
+    
+    //print_clock();
+    Host_Init();               /* Initialize the  host controller                                    */
+    rc = Host_EnumDev();       /* Enumerate the device connected                                            */
+    if (rc != OK)
+    {
+        fprintf(stderr, "Could not enumerate device: %d\n", rc);
+        return rc;
+    }
+        
+    
+    /* Initialize the mass storage and scsi interfaces */
+    rc = MS_Init( &_blkSize, &_numBlks, inquiryResult );
+    if (rc != OK)
+    {
+        fprintf(stderr, "Could not initialize mass storage interface: %d\n", rc);
+        return rc;
+    }
+    printf("Successfully initialized mass storage interface; %d blocks of size %d\n", _numBlks, _blkSize);
+    print_inquiry(inquiryResult);
+    // FATFileSystem supports only 512-byte blocks
+    return _blkSize == 512 ? OK : 1;
+}
+
+int MSCFileSystem::disk_initialize()
+{
+    if ( initialise_msc() != OK )
+        return 1;
+        
+    return 0;
+}
+
+int MSCFileSystem::disk_write(const char *buffer, int block_number)
+{
+    if ( OK == MS_BulkSend(block_number, 1, (USB_INT08U *)buffer) )
+        return 0;
+    return 1;
+}
+
+int MSCFileSystem::disk_read(char *buffer, int block_number)
+{
+    if ( OK == MS_BulkRecv(block_number, 1, (USB_INT08U *)buffer) )
+        return 0;
+    return 1;
+}
+
+int MSCFileSystem::disk_status() { return 0; }
+int MSCFileSystem::disk_sync() { return 0; }
+int MSCFileSystem::disk_sectors() { return _numBlks; }
diff -r 000000000000 -r d920d64db582 MSCFileSystem.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/MSCFileSystem.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,49 @@
+/* USB Mass Storage device file system
+ * Copyrigh (c) 2010, Igor Skochinsky
+ * based on SDFileStorage
+ * Copyright (c) 2008-2009, sford
+ */
+ 
+#ifndef MSCFILESYSTEM_H
+#define MSCFILESYSTEM_H
+
+#include "mbed.h"
+#include "FATFileSystem.h"
+
+/* Class: MSCFileSystem
+ *  Access the filesystem on an attached USB mass storage device (e.g. a memory stick)
+ *
+ * Example:
+ * > MSCFileSystem msc("msc");
+ * > 
+ * > int main() {
+ * >     FILE *fp = fopen("/msc/myfile.txt", "w");
+ * >     fprintf(fp, "Hello World!\n");
+ * >     fclose(fp);
+ * > }
+ */
+class MSCFileSystem : public FATFileSystem {
+public:
+
+    /* Constructor: MSCFileSystem
+     *  Create the File System for accessing a USB mass storage device
+     *
+     * Parameters:
+     *  name - The name used to access the filesystem
+     */
+    MSCFileSystem(const char* name);
+    virtual int disk_initialize();
+    virtual int disk_write(const char *buffer, int block_number);
+    virtual int disk_read(char *buffer, int block_number);    
+    virtual int disk_status();
+    virtual int disk_sync();
+    virtual int disk_sectors();
+
+protected:
+
+    int initialise_msc();
+    uint32_t _numBlks;
+    uint32_t _blkSize;
+};
+
+#endif
diff -r 000000000000 -r d920d64db582 SDHCFileSystem.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDHCFileSystem.cpp	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,495 @@
+/* mbed SDFileSystem Library, for providing file access to SD cards
+ * Copyright (c) 2008-2010, sford
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* Introduction
+ * ------------
+ * SD and MMC cards support a number of interfaces, but common to them all
+ * is one based on SPI. This is the one I'm implmenting because it means
+ * it is much more portable even though not so performant, and we already 
+ * have the mbed SPI Interface!
+ *
+ * The main reference I'm using is Chapter 7, "SPI Mode" of: 
+ *  http://www.sdcard.org/developers/tech/sdcard/pls/Simplified_Physical_Layer_Spec.pdf
+ *
+ * SPI Startup
+ * -----------
+ * The SD card powers up in SD mode. The SPI interface mode is selected by
+ * asserting CS low and sending the reset command (CMD0). The card will 
+ * respond with a (R1) response.
+ *
+ * CMD8 is optionally sent to determine the voltage range supported, and 
+ * indirectly determine whether it is a version 1.x SD/non-SD card or 
+ * version 2.x. I'll just ignore this for now.
+ *
+ * ACMD41 is repeatedly issued to initialise the card, until "in idle"
+ * (bit 0) of the R1 response goes to '0', indicating it is initialised.
+ *
+ * You should also indicate whether the host supports High Capicity cards,
+ * and check whether the card is high capacity - i'll also ignore this
+ *
+ * SPI Protocol
+ * ------------
+ * The SD SPI protocol is based on transactions made up of 8-bit words, with
+ * the host starting every bus transaction by asserting the CS signal low. The
+ * card always responds to commands, data blocks and errors.
+ * 
+ * The protocol supports a CRC, but by default it is off (except for the 
+ * first reset CMD0, where the CRC can just be pre-calculated, and CMD8)
+ * I'll leave the CRC off I think! 
+ * 
+ * Standard capacity cards have variable data block sizes, whereas High 
+ * Capacity cards fix the size of data block to 512 bytes. I'll therefore
+ * just always use the Standard Capacity cards with a block size of 512 bytes.
+ * This is set with CMD16.
+ *
+ * You can read and write single blocks (CMD17, CMD25) or multiple blocks 
+ * (CMD18, CMD25). For simplicity, I'll just use single block accesses. When
+ * the card gets a read command, it responds with a response token, and then 
+ * a data token or an error.
+ * 
+ * SPI Command Format
+ * ------------------
+ * Commands are 6-bytes long, containing the command, 32-bit argument, and CRC.
+ *
+ * +---------------+------------+------------+-----------+----------+--------------+
+ * | 01 | cmd[5:0] | arg[31:24] | arg[23:16] | arg[15:8] | arg[7:0] | crc[6:0] | 1 |
+ * +---------------+------------+------------+-----------+----------+--------------+
+ *
+ * As I'm not using CRC, I can fix that byte to what is needed for CMD0 (0x95)
+ *
+ * All Application Specific commands shall be preceded with APP_CMD (CMD55).
+ *
+ * SPI Response Format
+ * -------------------
+ * The main response format (R1) is a status byte (normally zero). Key flags:
+ *  idle - 1 if the card is in an idle state/initialising 
+ *  cmd  - 1 if an illegal command code was detected
+ *
+ *    +-------------------------------------------------+
+ * R1 | 0 | arg | addr | seq | crc | cmd | erase | idle |
+ *    +-------------------------------------------------+
+ *
+ * R1b is the same, except it is followed by a busy signal (zeros) until
+ * the first non-zero byte when it is ready again.
+ *
+ * Data Response Token
+ * -------------------
+ * Every data block written to the card is acknowledged by a byte 
+ * response token
+ *
+ * +----------------------+
+ * | xxx | 0 | status | 1 |
+ * +----------------------+
+ *              010 - OK!
+ *              101 - CRC Error
+ *              110 - Write Error
+ *
+ * Single Block Read and Write
+ * ---------------------------
+ *
+ * Block transfers have a byte header, followed by the data, followed
+ * by a 16-bit CRC. In our case, the data will always be 512 bytes.
+ *  
+ * +------+---------+---------+- -  - -+---------+-----------+----------+
+ * | 0xFE | data[0] | data[1] |        | data[n] | crc[15:8] | crc[7:0] | 
+ * +------+---------+---------+- -  - -+---------+-----------+----------+
+ */
+ 
+ /*
+ * Comment: Changes for SDHC support till 32GB 
+ * Name:    KB
+ * Date:    07/24/2010
+ * Release: 0.1
+ */
+ 
+#include "SDHCFileSystem.h"
+
+#define DEBUG
+#define SD_COMMAND_TIMEOUT 5000
+
+
+SDFileSystem::SDFileSystem(PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name) :
+  FATFileSystem(name), _spi(mosi, miso, sclk), _cs(cs) {
+      _cs = 1; 
+}
+
+#define R1_IDLE_STATE           (1 << 0)
+#define R1_ERASE_RESET          (1 << 1)
+#define R1_ILLEGAL_COMMAND      (1 << 2)
+#define R1_COM_CRC_ERROR        (1 << 3)
+#define R1_ERASE_SEQUENCE_ERROR (1 << 4)
+#define R1_ADDRESS_ERROR        (1 << 5)
+#define R1_PARAMETER_ERROR      (1 << 6)
+
+// Types
+//  - v1.x Standard Capacity
+//  - v2.x Standard Capacity
+//  - v2.x High Capacity
+//  - Not recognised as an SD Card
+
+#define SDCARD_FAIL 0
+#define SDCARD_V1   1
+#define SDCARD_V2   2
+#define SDCARD_V2HC 3
+
+int SDFileSystem::initialise_card() {
+    // Set to 100kHz for initialisation, and clock card with cs = 1
+    _spi.frequency(100000); 
+    _cs = 1;
+    for(int i=0; i<16; i++) {   
+        _spi.write(0xFF);
+    }
+
+    // send CMD0, should return with all zeros except IDLE STATE set (bit 0)
+    if(_cmd(0, 0) != R1_IDLE_STATE) { 
+        fprintf(stderr, "No disk, or could not put SD card in to SPI idle state\n");
+        return SDCARD_FAIL;
+    }
+
+    // send CMD8 to determine whther it is ver 2.x
+    int r = _cmd8();
+    if(r == R1_IDLE_STATE) {
+        return initialise_card_v2();
+    } else if(r == (R1_IDLE_STATE | R1_ILLEGAL_COMMAND)) {
+        return initialise_card_v1();
+    } else {
+        fprintf(stderr, "Not in idle state after sending CMD8 (not an SD card?)\n");
+        return SDCARD_FAIL;
+    }
+}
+
+int SDFileSystem::initialise_card_v1() {
+    for(int i=0; i<SD_COMMAND_TIMEOUT; i++) {
+        _cmd(55, 0); 
+        if(_cmd(41, 0) == 0) { 
+            cdv = 512;
+            #ifdef DEBUG 
+            printf("\n\rInit: SEDCARD_V1\n\r");
+            #endif
+            return SDCARD_V1;
+        }
+    }
+
+    fprintf(stderr, "Timeout waiting for v1.x card\n");
+    return SDCARD_FAIL;
+}
+
+int SDFileSystem::initialise_card_v2() {
+    
+    for(int i=0; i<SD_COMMAND_TIMEOUT; i++) {
+        wait_ms(50);
+        _cmd58();
+        _cmd(55, 0); 
+        if(_cmd(41, 0x40000000) == 0) { 
+            _cmd58();
+            #ifdef DEBUG
+            printf("\n\rInit: SDCARD_V2\n\r");
+            #endif
+            cdv = 1;
+            return SDCARD_V2;
+        }
+    }
+
+    fprintf(stderr, "Timeout waiting for v2.x card\n");
+    return SDCARD_FAIL;
+}
+
+int SDFileSystem::disk_initialize() {
+
+    int i = initialise_card();
+    #ifdef DEBUG 
+    printf("init card = %d\n", i);
+    #endif
+    _sectors = _sd_sectors();
+
+    // Set block length to 512 (CMD16)
+    if(_cmd(16, 512) != 0) {
+        fprintf(stderr, "Set 512-byte block timed out\n");
+        return 1;
+    }
+        
+    _spi.frequency(12000000); // Set to 1MHz for data transfer
+    return 0;
+}
+
+int SDFileSystem::disk_write(const char *buffer, int block_number) {
+    // set write address for single block (CMD24)
+    if(_cmd(24, block_number * cdv) != 0) {
+        return 1;
+    }
+
+    // send the data block
+    _write(buffer, 512);    
+    return 0;    
+}
+
+int SDFileSystem::disk_read(char *buffer, int block_number) {        
+    // set read address for single block (CMD17)
+    if(_cmd(17, block_number * cdv) != 0) {
+        return 1;
+    }
+    
+    // receive the data
+    _read(buffer, 512);
+    return 0;
+}
+
+int SDFileSystem::disk_status() { return 0; }
+int SDFileSystem::disk_sync() { return 0; }
+int SDFileSystem::disk_sectors() { return _sectors; }
+
+// PRIVATE FUNCTIONS
+
+int SDFileSystem::_cmd(int cmd, int arg) {
+    _cs = 0; 
+
+    // send a command
+    _spi.write(0x40 | cmd);
+    _spi.write(arg >> 24);
+    _spi.write(arg >> 16);
+    _spi.write(arg >> 8);
+    _spi.write(arg >> 0);
+    _spi.write(0x95);
+
+    // wait for the repsonse (response[7] == 0)
+    for(int i=0; i<SD_COMMAND_TIMEOUT; i++) {
+        int response = _spi.write(0xFF);
+        if(!(response & 0x80)) {
+            _cs = 1;
+            _spi.write(0xFF);
+            return response;
+        }
+    }
+    _cs = 1;
+    _spi.write(0xFF);
+    return -1; // timeout
+}
+int SDFileSystem::_cmdx(int cmd, int arg) {
+    _cs = 0; 
+
+    // send a command
+    _spi.write(0x40 | cmd);
+    _spi.write(arg >> 24);
+    _spi.write(arg >> 16);
+    _spi.write(arg >> 8);
+    _spi.write(arg >> 0);
+    _spi.write(0x95);
+
+    // wait for the repsonse (response[7] == 0)
+    for(int i=0; i<SD_COMMAND_TIMEOUT; i++) {
+        int response = _spi.write(0xFF);
+        if(!(response & 0x80)) {
+            return response;
+        }
+    }
+    _cs = 1;
+    _spi.write(0xFF);
+    return -1; // timeout
+}
+
+
+int SDFileSystem::_cmd58() {
+    _cs = 0; 
+    int arg = 0;
+    
+    // send a command
+    _spi.write(0x40 | 58);
+    _spi.write(arg >> 24);
+    _spi.write(arg >> 16);
+    _spi.write(arg >> 8);
+    _spi.write(arg >> 0);
+    _spi.write(0x95);
+
+    // wait for the repsonse (response[7] == 0)
+    for(int i=0; i<SD_COMMAND_TIMEOUT; i++) {
+        int response = _spi.write(0xFF);
+        if(!(response & 0x80)) {
+            int ocr = _spi.write(0xFF) << 24;
+            ocr |= _spi.write(0xFF) << 16;
+            ocr |= _spi.write(0xFF) << 8;
+            ocr |= _spi.write(0xFF) << 0;
+//            printf("OCR = 0x%08X\n", ocr);
+            _cs = 1;
+            _spi.write(0xFF);
+            return response;
+        }
+    }
+    _cs = 1;
+    _spi.write(0xFF);
+    return -1; // timeout
+}
+
+int SDFileSystem::_cmd8() {
+    _cs = 0; 
+    
+    // send a command
+    _spi.write(0x40 | 8); // CMD8
+    _spi.write(0x00);     // reserved
+    _spi.write(0x00);     // reserved
+    _spi.write(0x01);     // 3.3v
+    _spi.write(0xAA);     // check pattern
+    _spi.write(0x87);     // crc
+
+    // wait for the repsonse (response[7] == 0)
+    for(int i=0; i<SD_COMMAND_TIMEOUT * 1000; i++) {
+        char response[5];
+        response[0] = _spi.write(0xFF);
+        if(!(response[0] & 0x80)) {
+                for(int j=1; j<5; j++) {
+                    response[i] = _spi.write(0xFF);
+                }
+                _cs = 1;
+                _spi.write(0xFF);
+                return response[0];
+        }
+    }
+    _cs = 1;
+    _spi.write(0xFF);
+    return -1; // timeout
+}
+
+int SDFileSystem::_read(char *buffer, int length) {
+    _cs = 0;
+
+    // read until start byte (0xFF)
+    while(_spi.write(0xFF) != 0xFE);
+
+    // read data
+    for(int i=0; i<length; i++) {
+        buffer[i] = _spi.write(0xFF);
+    }
+    _spi.write(0xFF); // checksum
+    _spi.write(0xFF);
+
+    _cs = 1;    
+    _spi.write(0xFF);
+    return 0;
+}
+
+int SDFileSystem::_write(const char *buffer, int length) {
+    _cs = 0;
+    
+    // indicate start of block
+    _spi.write(0xFE);
+    
+    // write the data
+    for(int i=0; i<length; i++) {
+        _spi.write(buffer[i]);
+    }
+    
+    // write the checksum
+    _spi.write(0xFF); 
+    _spi.write(0xFF);
+
+    // check the repsonse token
+    if((_spi.write(0xFF) & 0x1F) != 0x05) {
+        _cs = 1;
+        _spi.write(0xFF);        
+        return 1;
+    }
+
+    // wait for write to finish
+    while(_spi.write(0xFF) == 0);
+
+    _cs = 1; 
+    _spi.write(0xFF);
+    return 0;
+}
+
+static int ext_bits(char *data, int msb, int lsb) {
+    int bits = 0;
+    int size = 1 + msb - lsb; 
+    for(int i=0; i<size; i++) {
+        int position = lsb + i;
+        int byte = 15 - (position >> 3);
+        int bit = position & 0x7;
+        int value = (data[byte] >> bit) & 1;
+        bits |= value << i;
+    }
+    return bits;
+}
+
+int SDFileSystem::_sd_sectors() {
+
+    int c_size, c_size_mult, read_bl_len;
+    int block_len, mult, blocknr, capacity;       
+    int blocks, hc_c_size;
+    uint64_t hc_capacity;
+     
+    // CMD9, Response R2 (R1 byte + 16-byte block read)
+    if(_cmdx(9, 0) != 0) {
+        fprintf(stderr, "Didn't get a response from the disk\n");
+        return 0;
+    }
+    
+    char csd[16];    
+    if(_read(csd, 16) != 0) {
+        fprintf(stderr, "Couldn't read csd response from disk\n");
+        return 0;
+    }
+
+    // csd_structure : csd[127:126]
+    // c_size        : csd[73:62]
+    // c_size_mult   : csd[49:47]
+    // read_bl_len   : csd[83:80] - the *maximum* read block length
+   
+    int csd_structure = ext_bits(csd, 127, 126);
+    
+    #ifdef DEBUG 
+    printf("\n\rCSD_STRUCT = %d\n", csd_structure);
+    #endif
+     
+    switch (csd_structure){
+     case 0:
+      cdv = 512;
+      c_size = ext_bits(csd, 73, 62);
+      c_size_mult = ext_bits(csd, 49, 47);
+      read_bl_len = ext_bits(csd, 83, 80);
+     
+      block_len = 1 << read_bl_len;
+      mult = 1 << (c_size_mult + 2);
+      blocknr = (c_size + 1) * mult;
+      capacity = blocknr * block_len;
+      blocks = capacity / 512;
+      #ifdef DEBUG 
+      printf("\n\rSDCard\n\rc_size: %.4X \n\rcapacity: %.ld \n\rsectors: %d\r\n", c_size, capacity, blocks);
+      #endif
+      break;
+    
+     case 1:
+      cdv = 1;
+      hc_c_size = ext_bits(csd, 63, 48);
+      int hc_read_bl_len = ext_bits(csd, 83, 80);
+      hc_capacity = hc_c_size+1;   
+      blocks = (hc_c_size+1)*1024;
+      #ifdef DEBUG 
+      printf("\n\rSDHC Card \n\rhc_c_size: %.4X \n\rcapacity: %.lld \n\rsectors: %d\r\n", hc_c_size, hc_capacity*512*1024, blocks);
+      #endif
+      break;
+   
+    default:    
+       fprintf(stderr, "This disk tastes funny! I only know about type 0 CSD structures\n");
+     return 0;
+     //break;
+    };
+ return blocks;
+}
diff -r 000000000000 -r d920d64db582 SDHCFileSystem.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDHCFileSystem.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,86 @@
+/* mbed SDFileSystem Library, for providing file access to SD cards
+ * Copyright (c) 2008-2010, sford
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef MBED_SDHCFILESYSTEM_H
+#define MBED_SDHCFILESYSTEM_H
+
+#include "mbed.h"
+#include "FATFileSystem.h"
+
+/* Double Words */
+typedef unsigned long long uint64_t;
+typedef long long sint64_t;
+
+/** Access the filesystem on an SD Card using SPI
+ *
+ * @code
+ * #include "mbed.h"
+ * #include "SDFileSystem.h"
+ *
+ * SDFileSystem sd(p5, p6, p7, p12, "sd"); // mosi, miso, sclk, cs
+ *  
+ * int main() {
+ *     FILE *fp = fopen("/sd/myfile.txt", "w");
+ *     fprintf(fp, "Hello World!\n");
+ *     fclose(fp);
+ * }
+ */
+class SDFileSystem : public FATFileSystem {
+public:
+
+    /** Create the File System for accessing an SD Card using SPI
+     *
+     * @param mosi SPI mosi pin connected to SD Card
+     * @param miso SPI miso pin conencted to SD Card
+     * @param sclk SPI sclk pin connected to SD Card
+     * @param cs   DigitalOut pin used as SD Card chip select
+     * @param name The name used to access the virtual filesystem
+     */
+    SDFileSystem(PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name);
+    virtual int disk_initialize();
+    virtual int disk_write(const char *buffer, int block_number);
+    virtual int disk_read(char *buffer, int block_number);    
+    virtual int disk_status();
+    virtual int disk_sync();
+    virtual int disk_sectors();
+
+protected:
+
+    int _cmd(int cmd, int arg);
+    int _cmdx(int cmd, int arg);
+    int _cmd8();
+    int _cmd58();
+    int initialise_card();
+    int initialise_card_v1();
+    int initialise_card_v2();
+    
+    int _read(char *buffer, int length);
+    int _write(const char *buffer, int length);
+    int _sd_sectors();
+    int _sectors;
+    
+    SPI _spi;
+    DigitalOut _cs; 
+    int cdv;    
+};
+
+#endif
diff -r 000000000000 -r d920d64db582 TextLCD/TextLCD.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/TextLCD/TextLCD.cpp	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,159 @@
+/* mbed TextLCD Library, for a 4-bit LCD based on HD44780
+ * Copyright (c) 2007-2010, sford
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "TextLCD.h"
+#include "mbed.h"
+
+TextLCD::TextLCD(PinName rs, PinName e, PinName d0, PinName d1,
+                 PinName d2, PinName d3, LCDType type) : _rs(rs),
+        _e(e), _d(d0, d1, d2, d3),
+        _type(type) {
+
+    _e  = 1;
+    _rs = 0;            // command mode
+
+    wait(0.015);        // Wait 15ms to ensure powered up
+
+    // send "Display Settings" 3 times (Only top nibble of 0x30 as we've got 4-bit bus)
+    for (int i=0; i<3; i++) {
+        writeByte(0x3);
+        wait(0.00164);  // this command takes 1.64ms, so wait for it
+    }
+    writeByte(0x2);     // 4-bit mode
+    wait(0.000040f);    // most instructions take 40us
+
+    writeCommand(0x28); // Function set 001 BW N F - -
+    writeCommand(0x0C);
+    writeCommand(0x6);  // Cursor Direction and Display Shift : 0000 01 CD S (CD 0-left, 1-right S(hift) 0-no, 1-yes
+    cls();
+}
+
+void TextLCD::character(int column, int row, int c) {
+    int a = address(column, row);
+    writeCommand(a);
+    writeData(c);
+}
+
+void TextLCD::cls() {
+    writeCommand(0x01); // cls, and set cursor to 0
+    wait(0.00164f);     // This command takes 1.64 ms
+    locate(0, 0);
+}
+
+void TextLCD::locate(int column, int row) {
+    _column = column;
+    _row = row;
+}
+
+int TextLCD::_putc(int value) {
+    if (value == '\n') {
+        _column = 0;
+        _row++;
+        if (_row >= rows()) {
+            _row = 0;
+        }
+    } else {
+        character(_column, _row, value);
+        _column++;
+        if (_column >= columns()) {
+            _column = 0;
+            _row++;
+            if (_row >= rows()) {
+                _row = 0;
+            }
+        }
+    }
+    return value;
+}
+
+int TextLCD::_getc() {
+    return -1;
+}
+
+void TextLCD::writeByte(int value) {
+    _d = value >> 4;
+    wait(0.000040f); // most instructions take 40us
+    _e = 0;
+    wait(0.000040f);
+    _e = 1;
+    _d = value >> 0;
+    wait(0.000040f);
+    _e = 0;
+    wait(0.000040f);  // most instructions take 40us
+    _e = 1;
+}
+
+void TextLCD::writeCommand(int command) {
+    _rs = 0;
+    writeByte(command);
+}
+
+void TextLCD::writeData(int data) {
+    _rs = 1;
+    writeByte(data);
+}
+
+int TextLCD::address(int column, int row) {
+    switch (_type) {
+        case LCD20x4:
+            switch (row) {
+                case 0:
+                    return 0x80 + column;
+                case 1:
+                    return 0xc0 + column;
+                case 2:
+                    return 0x94 + column;
+                case 3:
+                    return 0xd4 + column;
+            }
+        case LCD16x2B:
+            return 0x80 + (row * 40) + column;
+        case LCD16x2:
+        case LCD20x2:
+        default:
+            return 0x80 + (row * 0x40) + column;
+    }
+}
+
+int TextLCD::columns() {
+    switch (_type) {
+        case LCD20x4:
+        case LCD20x2:
+            return 20;
+        case LCD16x2:
+        case LCD16x2B:
+        default:
+            return 16;
+    }
+}
+
+int TextLCD::rows() {
+    switch (_type) {
+        case LCD20x4:
+            return 4;
+        case LCD16x2:
+        case LCD16x2B:
+        case LCD20x2:
+        default:
+            return 2;
+    }
+}
\ No newline at end of file
diff -r 000000000000 -r d920d64db582 TextLCD/TextLCD.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/TextLCD/TextLCD.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,111 @@
+/* mbed TextLCD Library, for a 4-bit LCD based on HD44780
+ * Copyright (c) 2007-2010, sford
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef MBED_TEXTLCD_H
+#define MBED_TEXTLCD_H
+
+#include "mbed.h"
+
+/** A TextLCD interface for driving 4-bit HD44780-based LCDs
+ *
+ * Currently supports 16x2, 20x2 and 20x4 panels
+ *
+ * @code
+ * #include "mbed.h"
+ * #include "TextLCD.h"
+ * 
+ * TextLCD lcd(p10, p12, p15, p16, p29, p30); // rs, e, d0-d3
+ * 
+ * int main() {
+ *     lcd.printf("Hello World!\n");
+ * }
+ * @endcode
+ */
+class TextLCD : public Stream {
+public:
+
+    /** LCD panel format */
+    enum LCDType {
+        LCD16x2     /**< 16x2 LCD panel (default) */
+        , LCD16x2B  /**< 16x2 LCD panel alternate addressing */
+        , LCD20x2   /**< 20x2 LCD panel */
+        , LCD20x4   /**< 20x4 LCD panel */
+    };
+
+    /** Create a TextLCD interface
+     *
+     * @param rs    Instruction/data control line
+     * @param e     Enable line (clock)
+     * @param d0-d3 Data lines
+     * @param type  Sets the panel size/addressing mode (default = LCD16x2)
+     */
+    TextLCD(PinName rs, PinName e, PinName d0, PinName d1, PinName d2, PinName d3, LCDType type = LCD16x2);
+
+#if DOXYGEN_ONLY
+    /** Write a character to the LCD
+     *
+     * @param c The character to write to the display
+     */
+    int putc(int c);
+
+    /** Write a formated string to the LCD
+     *
+     * @param format A printf-style format string, followed by the
+     *               variables to use in formating the string.
+     */
+    int printf(const char* format, ...);
+#endif
+
+    /** Locate to a screen column and row
+     *
+     * @param column  The horizontal position from the left, indexed from 0
+     * @param row     The vertical position from the top, indexed from 0
+     */
+    void locate(int column, int row);
+
+    /** Clear the screen and locate to 0,0 */
+    void cls();
+
+    int rows();
+    int columns();
+
+protected:
+
+    // Stream implementation functions
+    virtual int _putc(int value);
+    virtual int _getc();
+
+    int address(int column, int row);
+    void character(int column, int row, int c);
+    void writeByte(int value);
+    void writeCommand(int command);
+    void writeData(int data);
+
+    DigitalOut _rs, _e;
+    BusOut _d;
+    LCDType _type;
+
+    int _column;
+    int _row;
+};
+
+#endif
\ No newline at end of file
diff -r 000000000000 -r d920d64db582 USBHostLite/usbhost_cpu.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHostLite/usbhost_cpu.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,35 @@
+/*
+**************************************************************************************************************
+*                                                 NXP USB Host Stack
+*
+*                                     (c) Copyright 2008, NXP SemiConductors
+*                                     (c) Copyright 2008, OnChip  Technologies LLC
+*                                                 All Rights Reserved
+*
+*                                                  www.nxp.com
+*                                               www.onchiptech.com
+*
+* File           : usbhost_cpu.h
+* Programmer(s)  : Ravikanth.P
+* Version        :
+*
+**************************************************************************************************************
+*/
+
+#ifndef  USBHOST_CPU_H
+#define  USBHOST_CPU_H
+
+/*
+**************************************************************************************************************
+*                                           TYPE DEFINITIONS OF DATA TYPES
+**************************************************************************************************************
+*/
+
+typedef  unsigned int    USB_INT32U;
+typedef  signed   int    USB_INT32S;
+typedef  unsigned short  USB_INT16U;
+typedef  signed   short  USB_INT16S;
+typedef  unsigned char   USB_INT08U;
+typedef  signed   char   USB_INT08S;
+
+#endif
diff -r 000000000000 -r d920d64db582 USBHostLite/usbhost_err.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHostLite/usbhost_err.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,63 @@
+/*
+**************************************************************************************************************
+*                                                 NXP USB Host Stack
+*
+*                                     (c) Copyright 2008, NXP SemiConductors
+*                                     (c) Copyright 2008, OnChip  Technologies LLC
+*                                                 All Rights Reserved
+*
+*                                                  www.nxp.com
+*                                               www.onchiptech.com
+*
+* File           : usbhost_err.h
+* Programmer(s)  : Ravikanth.P
+* Version        :
+*
+**************************************************************************************************************
+*/
+
+#ifndef  USBHOST_ERR_H
+#define  USBHOST_ERR_H
+
+
+/*
+**************************************************************************************************************
+*                                        GENERAL DEFINITIONS
+**************************************************************************************************************
+*/
+
+#define  OK                        0
+#define  MATCH_FOUND               0
+
+/*
+**************************************************************************************************************
+*                                HOST CONTROLLER SPECIFIC ERROR CODES
+**************************************************************************************************************
+*/
+
+#define  ERR_TD_FAIL              -1
+
+/*
+**************************************************************************************************************
+*                                  MASS STORAGE SPECIFIC ERROR CODES
+**************************************************************************************************************
+*/
+
+#define  ERR_MS_CMD_FAILED       -10
+#define  ERR_BAD_CONFIGURATION   -11
+#define  ERR_NO_MS_INTERFACE     -12
+
+/*
+**************************************************************************************************************
+*                                      FAT SPECIFIC ERROR CODES
+**************************************************************************************************************
+*/
+
+#define  MATCH_NOT_FOUND         -20
+#define  ERR_FAT_NOT_SUPPORTED   -21
+#define  ERR_OPEN_LIMIT_REACHED  -22
+#define  ERR_INVALID_BOOT_SIG    -23
+#define  ERR_INVALID_BOOT_SEC    -24
+#define  ERR_ROOT_DIR_FULL       -25
+
+#endif
diff -r 000000000000 -r d920d64db582 USBHostLite/usbhost_inc.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHostLite/usbhost_inc.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,39 @@
+/*
+**************************************************************************************************************
+*                                                 NXP USB Host Stack
+*
+*                                     (c) Copyright 2008, NXP SemiConductors
+*                                     (c) Copyright 2008, OnChip  Technologies LLC
+*                                                 All Rights Reserved
+*
+*                                                  www.nxp.com
+*                                               www.onchiptech.com
+*
+* File           : usbhost_inc.h
+* Programmer(s)  : Ravikanth.P
+* Version        :
+*
+**************************************************************************************************************
+*/
+
+#ifndef  USBHOST_INC_H
+#define  USBHOST_INC_H
+
+/*
+**************************************************************************************************************
+*                                       INCLUDE HEADER FILES
+**************************************************************************************************************
+*/
+
+#include  "usbhost_cpu.h"
+#include  "usbhost_err.h"
+#include  "usbhost_lpc17xx.h"
+#include  "usbhost_ms.h"
+#include  "mbed.h"
+
+
+#ifdef TARGET_LPC2368
+#error "There is no USB host on the LPC2368!"
+#endif
+
+#endif
diff -r 000000000000 -r d920d64db582 USBHostLite/usbhost_lpc17xx.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHostLite/usbhost_lpc17xx.c	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,820 @@
+/*
+**************************************************************************************************************
+*                                                 NXP USB Host Stack
+*
+*                                     (c) Copyright 2008, NXP SemiConductors
+*                                     (c) Copyright 2008, OnChip  Technologies LLC
+*                                                 All Rights Reserved
+*
+*                                                  www.nxp.com
+*                                               www.onchiptech.com
+*
+* File           : usbhost_lpc17xx.c
+* Programmer(s)  : Ravikanth.P
+* Version        :
+*
+**************************************************************************************************************
+*/
+ 
+/*
+**************************************************************************************************************
+*                                            INCLUDE HEADER FILES
+**************************************************************************************************************
+*/
+
+#include  "usbhost_lpc17xx.h"
+
+/*
+**************************************************************************************************************
+*                                              GLOBAL VARIABLES
+**************************************************************************************************************
+*/
+int gUSBConnected;
+
+volatile  USB_INT32U   HOST_RhscIntr = 0;         /* Root Hub Status Change interrupt                       */
+volatile  USB_INT32U   HOST_WdhIntr  = 0;         /* Semaphore to wait until the TD is submitted            */
+volatile  USB_INT08U   HOST_TDControlStatus = 0;
+volatile  HCED        *EDCtrl;                    /* Control endpoint descriptor structure                  */
+volatile  HCED        *EDBulkIn;                  /* BulkIn endpoint descriptor  structure                  */
+volatile  HCED        *EDBulkOut;                 /* BulkOut endpoint descriptor structure                  */
+volatile  HCTD        *TDHead;                    /* Head transfer descriptor structure                     */
+volatile  HCTD        *TDTail;                    /* Tail transfer descriptor structure                     */
+volatile  HCCA        *Hcca;                      /* Host Controller Communications Area structure          */ 
+          USB_INT16U  *TDBufNonVol;               /* Identical to TDBuffer just to reduce compiler warnings */
+volatile  USB_INT08U  *TDBuffer;                  /* Current Buffer Pointer of transfer descriptor          */
+
+// USB host structures
+// AHB SRAM block 1
+#define HOSTBASEADDR 0x2007C000
+// reserve memory for the linker
+static USB_INT08U HostBuf[0x200] __attribute__((at(HOSTBASEADDR)));
+/*
+**************************************************************************************************************
+*                                         DELAY IN MILLI SECONDS
+*
+* Description: This function provides a delay in milli seconds
+*
+* Arguments  : delay    The delay required
+*
+* Returns    : None
+*
+**************************************************************************************************************
+*/
+
+void  Host_DelayMS (USB_INT32U  delay)
+{
+    volatile  USB_INT32U  i;
+
+
+    for (i = 0; i < delay; i++) {
+        Host_DelayUS(1000);
+    }
+}
+
+/*
+**************************************************************************************************************
+*                                         DELAY IN MICRO SECONDS
+*
+* Description: This function provides a delay in micro seconds
+*
+* Arguments  : delay    The delay required
+*
+* Returns    : None
+*
+**************************************************************************************************************
+*/
+
+void  Host_DelayUS (USB_INT32U  delay)
+{
+    volatile  USB_INT32U  i;
+
+
+    for (i = 0; i < (4 * delay); i++) {    /* This logic was tested. It gives app. 1 micro sec delay        */
+        ;
+    }
+}
+
+// bits of the USB/OTG clock control register
+#define HOST_CLK_EN     (1<<0)
+#define DEV_CLK_EN      (1<<1)
+#define PORTSEL_CLK_EN  (1<<3)
+#define AHB_CLK_EN      (1<<4)
+
+// bits of the USB/OTG clock status register
+#define HOST_CLK_ON     (1<<0)
+#define DEV_CLK_ON      (1<<1)
+#define PORTSEL_CLK_ON  (1<<3)
+#define AHB_CLK_ON      (1<<4)
+
+// we need host clock, OTG/portsel clock and AHB clock
+#define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
+
+/*
+**************************************************************************************************************
+*                                         INITIALIZE THE HOST CONTROLLER
+*
+* Description: This function initializes lpc17xx host controller
+*
+* Arguments  : None
+*
+* Returns    : 
+*
+**************************************************************************************************************
+*/
+void  Host_Init (void)
+{
+    PRINT_Log("In Host_Init\n");
+    NVIC_DisableIRQ(USB_IRQn);                           /* Disable the USB interrupt source           */
+    
+    // turn on power for USB
+    LPC_SC->PCONP       |= (1UL<<31);
+    // Enable USB host clock, port selection and AHB clock
+    LPC_USB->USBClkCtrl |= CLOCK_MASK;
+    // Wait for clocks to become available
+    while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK)
+        ;
+    
+    // it seems the bits[0:1] mean the following
+    // 0: U1=device, U2=host
+    // 1: U1=host, U2=host
+    // 2: reserved
+    // 3: U1=host, U2=device
+    // NB: this register is only available if OTG clock (aka "port select") is enabled!!
+    // since we don't care about port 2, set just bit 0 to 1 (U1=host)
+    LPC_USB->OTGStCtrl |= 1;
+    
+    // now that we've configured the ports, we can turn off the portsel clock
+    LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
+    
+    // power pins are not connected on mbed, so we can skip them
+    /* P1[18] = USB_UP_LED, 01 */
+    /* P1[19] = /USB_PPWR,     10 */
+    /* P1[22] = USB_PWRD, 10 */
+    /* P1[27] = /USB_OVRCR, 10 */
+    /*LPC_PINCON->PINSEL3 &= ~((3<<4) | (3<<6) | (3<<12) | (3<<22));  
+    LPC_PINCON->PINSEL3 |=  ((1<<4)|(2<<6) | (2<<12) | (2<<22));   // 0x00802080
+    */
+
+    // configure USB D+/D- pins
+    /* P0[29] = USB_D+, 01 */
+    /* P0[30] = USB_D-, 01 */
+    LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));  
+    LPC_PINCON->PINSEL1 |=  ((1<<26)|(1<<28));     // 0x14000000
+        
+    PRINT_Log("Initializing Host Stack\n");
+
+    Hcca       = (volatile  HCCA       *)(HostBuf+0x000);
+    TDHead     = (volatile  HCTD       *)(HostBuf+0x100);
+    TDTail     = (volatile  HCTD       *)(HostBuf+0x110);
+    EDCtrl     = (volatile  HCED       *)(HostBuf+0x120); 
+    EDBulkIn   = (volatile  HCED       *)(HostBuf+0x130);
+    EDBulkOut  = (volatile  HCED       *)(HostBuf+0x140);
+    TDBuffer   = (volatile  USB_INT08U *)(HostBuf+0x150);
+    
+    /* Initialize all the TDs, EDs and HCCA to 0  */
+    Host_EDInit(EDCtrl);
+    Host_EDInit(EDBulkIn);
+    Host_EDInit(EDBulkOut);
+    Host_TDInit(TDHead);
+    Host_TDInit(TDTail);
+    Host_HCCAInit(Hcca);
+    
+    Host_DelayMS(50);                                   /* Wait 50 ms before apply reset              */
+    LPC_USB->HcControl       = 0;                       /* HARDWARE RESET                             */
+    LPC_USB->HcControlHeadED = 0;                       /* Initialize Control list head to Zero       */
+    LPC_USB->HcBulkHeadED    = 0;                       /* Initialize Bulk list head to Zero          */
+    
+                                                        /* SOFTWARE RESET                             */
+    LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
+    LPC_USB->HcFmInterval    = DEFAULT_FMINTERVAL;      /* Write Fm Interval and Largest Data Packet Counter */
+
+                                                        /* Put HC in operational state                */
+    LPC_USB->HcControl  = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
+    LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC;            /* Set Global Power                           */
+    
+    LPC_USB->HcHCCA = (USB_INT32U)Hcca;
+    LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus;                   /* Clear Interrrupt Status                    */
+
+
+    LPC_USB->HcInterruptEnable  = OR_INTR_ENABLE_MIE |
+                         OR_INTR_ENABLE_WDH |
+                         OR_INTR_ENABLE_RHSC;
+
+    NVIC_SetPriority(USB_IRQn, 0);       /* highest priority */
+    /* Enable the USB Interrupt */
+    NVIC_EnableIRQ(USB_IRQn);
+    PRINT_Log("Host Initialized\n");
+}
+
+/*
+**************************************************************************************************************
+*                                         INTERRUPT SERVICE ROUTINE
+*
+* Description: This function services the interrupt caused by host controller
+*
+* Arguments  : None
+*
+* Returns    : None
+*
+**************************************************************************************************************
+*/
+
+void USB_IRQHandler (void) __irq
+{
+    USB_INT32U   int_status;
+    USB_INT32U   ie_status;
+
+    int_status    = LPC_USB->HcInterruptStatus;                          /* Read Interrupt Status                */
+    ie_status     = LPC_USB->HcInterruptEnable;                          /* Read Interrupt enable status         */
+ 
+    if (!(int_status & ie_status)) {
+        return;
+    } else {
+
+        int_status = int_status & ie_status;
+        if (int_status & OR_INTR_STATUS_RHSC) {                 /* Root hub status change interrupt     */
+            if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
+                if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
+                    /*
+                     * When DRWE is on, Connect Status Change
+                     * means a remote wakeup event.
+                    */
+                    HOST_RhscIntr = 1;// JUST SOMETHING FOR A BREAKPOINT
+                }
+                else {
+                    /*
+                     * When DRWE is off, Connect Status Change
+                     * is NOT a remote wakeup event
+                    */
+                    if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
+                        if (!gUSBConnected) {
+                            HOST_TDControlStatus = 0;
+                            HOST_WdhIntr = 0;
+                            HOST_RhscIntr = 1;
+                            gUSBConnected = 1;
+                        }
+                        else
+                            PRINT_Log("Spurious status change (connected)?\n");
+                    } else {
+                        if (gUSBConnected) {
+                            LPC_USB->HcInterruptEnable = 0; // why do we get multiple disc. rupts???
+                            HOST_RhscIntr = 0;
+                            gUSBConnected = 0;
+                        }
+                        else
+                            PRINT_Log("Spurious status change (disconnected)?\n");
+                    }
+                }
+                LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
+            }
+            if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
+                LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+            }
+        }
+        if (int_status & OR_INTR_STATUS_WDH) {                  /* Writeback Done Head interrupt        */
+            HOST_WdhIntr = 1;
+            HOST_TDControlStatus = (TDHead->Control >> 28) & 0xf;
+        }            
+        LPC_USB->HcInterruptStatus = int_status;                         /* Clear interrupt status register      */
+    }
+    return;
+}
+
+/*
+**************************************************************************************************************
+*                                     PROCESS TRANSFER DESCRIPTOR
+*
+* Description: This function processes the transfer descriptor
+*
+* Arguments  : ed            Endpoint descriptor that contains this transfer descriptor
+*              token         SETUP, IN, OUT
+*              buffer        Current Buffer Pointer of the transfer descriptor
+*              buffer_len    Length of the buffer
+*
+* Returns    : OK       if TD submission is successful
+*              ERROR    if TD submission fails
+*
+**************************************************************************************************************
+*/
+
+USB_INT32S  Host_ProcessTD (volatile  HCED       *ed,
+                            volatile  USB_INT32U  token,
+                            volatile  USB_INT08U *buffer,
+                                      USB_INT32U  buffer_len)
+{
+    volatile  USB_INT32U   td_toggle;
+
+
+    if (ed == EDCtrl) {
+        if (token == TD_SETUP) {
+            td_toggle = TD_TOGGLE_0;
+        } else {
+            td_toggle = TD_TOGGLE_1;
+        }
+    } else {
+        td_toggle = 0;
+    }
+    TDHead->Control = (TD_ROUNDING    |
+                      token           |
+                      TD_DELAY_INT(0) |                           
+                      td_toggle       |
+                      TD_CC);
+    TDTail->Control = 0;
+    TDHead->CurrBufPtr   = (USB_INT32U) buffer;
+    TDTail->CurrBufPtr   = 0;
+    TDHead->Next         = (USB_INT32U) TDTail;
+    TDTail->Next         = 0;
+    TDHead->BufEnd       = (USB_INT32U)(buffer + (buffer_len - 1));
+    TDTail->BufEnd       = 0;
+
+    ed->HeadTd  = (USB_INT32U)TDHead | ((ed->HeadTd) & 0x00000002);
+    ed->TailTd  = (USB_INT32U)TDTail;
+    ed->Next    = 0;
+
+    if (ed == EDCtrl) {
+        LPC_USB->HcControlHeadED = (USB_INT32U)ed;
+        LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_CLF;
+        LPC_USB->HcControl       = LPC_USB->HcControl       | OR_CONTROL_CLE;
+    } else {
+        LPC_USB->HcBulkHeadED    = (USB_INT32U)ed;
+        LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_BLF;
+        LPC_USB->HcControl       = LPC_USB->HcControl       | OR_CONTROL_BLE;
+    }    
+
+    Host_WDHWait();
+
+//    if (!(TDHead->Control & 0xF0000000)) {
+    if (!HOST_TDControlStatus) {
+        return (OK);
+    } else {      
+        return (ERR_TD_FAIL);
+    }
+}
+
+/*
+**************************************************************************************************************
+*                                       ENUMERATE THE DEVICE
+*
+* Description: This function is used to enumerate the device connected
+*
+* Arguments  : None
+*
+* Returns    : None
+*
+**************************************************************************************************************
+*/
+
+USB_INT32S  Host_EnumDev (void)
+{
+    USB_INT32S  rc;
+
+    PRINT_Log("Connect a Mass Storage device\n");
+    while (!HOST_RhscIntr)
+        __WFI();
+    Host_DelayMS(100);                             /* USB 2.0 spec says atleast 50ms delay beore port reset */
+    LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS; // Initiate port reset
+    while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS)
+        __WFI(); // Wait for port reset to complete...
+    LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC; // ...and clear port reset signal
+    Host_DelayMS(200);                                                 /* Wait for 100 MS after port reset  */
+
+    EDCtrl->Control = 8 << 16;                                         /* Put max pkt size = 8              */
+                                                                       /* Read first 8 bytes of device desc */
+    rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_DEVICE, 0, TDBuffer, 8);
+    if (rc != OK) {
+        PRINT_Err(rc);
+        return (rc);
+    }
+    EDCtrl->Control = TDBuffer[7] << 16;                               /* Get max pkt size of endpoint 0    */
+    rc = HOST_SET_ADDRESS(1);                                          /* Set the device address to 1       */
+    if (rc != OK) {
+        PRINT_Err(rc);
+        return (rc);
+    }
+    Host_DelayMS(2);
+    EDCtrl->Control = (EDCtrl->Control) | 1;                          /* Modify control pipe with address 1 */
+                                                                      /* Get the configuration descriptor   */
+    rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, 9);
+    if (rc != OK) {
+        PRINT_Err(rc);
+        return (rc);
+    }
+                                                                       /* Get the first configuration data  */
+    rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, ReadLE16U(&TDBuffer[2]));
+    if (rc != OK) {
+        PRINT_Err(rc);
+        return (rc);
+    }
+    rc = MS_ParseConfiguration();                                      /* Parse the configuration           */
+    if (rc != OK) {
+        PRINT_Err(rc);
+        return (rc);
+    }
+    rc = USBH_SET_CONFIGURATION(1);                                    /* Select device configuration 1     */
+    if (rc != OK) {
+        PRINT_Err(rc);
+    }
+    Host_DelayMS(100);                                               /* Some devices may require this delay */
+    return (rc);
+}
+
+/*
+**************************************************************************************************************
+*                                        RECEIVE THE CONTROL INFORMATION
+*
+* Description: This function is used to receive the control information
+*
+* Arguments  : bm_request_type
+*              b_request
+*              w_value
+*              w_index
+*              w_length
+*              buffer
+*
+* Returns    : OK       if Success
+*              ERROR    if Failed
+*
+**************************************************************************************************************
+*/
+   
+USB_INT32S  Host_CtrlRecv (         USB_INT08U   bm_request_type,
+                                    USB_INT08U   b_request,
+                                    USB_INT16U   w_value,
+                                    USB_INT16U   w_index,
+                                    USB_INT16U   w_length,
+                          volatile  USB_INT08U  *buffer)
+{
+    USB_INT32S  rc;
+
+
+    Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
+    rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
+    if (rc == OK) {
+        if (w_length) {
+            rc = Host_ProcessTD(EDCtrl, TD_IN, TDBuffer, w_length);
+        }
+        if (rc == OK) {
+            rc = Host_ProcessTD(EDCtrl, TD_OUT, NULL, 0);
+        }
+    }
+    return (rc);
+}
+
+/*
+**************************************************************************************************************
+*                                         SEND THE CONTROL INFORMATION
+*
+* Description: This function is used to send the control information
+*
+* Arguments  : None
+*
+* Returns    : OK                      if Success
+*              ERR_INVALID_BOOTSIG    if Failed
+*
+**************************************************************************************************************
+*/
+
+USB_INT32S  Host_CtrlSend (          USB_INT08U   bm_request_type,
+                                     USB_INT08U   b_request,
+                                     USB_INT16U   w_value,
+                                     USB_INT16U   w_index,
+                                     USB_INT16U   w_length,
+                           volatile  USB_INT08U  *buffer)
+{
+    USB_INT32S  rc;
+
+
+    Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
+
+    rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
+    if (rc == OK) {
+        if (w_length) {
+            rc = Host_ProcessTD(EDCtrl, TD_OUT, TDBuffer, w_length);
+        }
+        if (rc == OK) {
+            rc = Host_ProcessTD(EDCtrl, TD_IN, NULL, 0);
+        }
+    }
+    return (rc);
+}
+
+/*
+**************************************************************************************************************
+*                                          FILL SETUP PACKET
+*
+* Description: This function is used to fill the setup packet
+*
+* Arguments  : None
+*
+* Returns    : OK                      if Success
+*              ERR_INVALID_BOOTSIG    if Failed
+*
+**************************************************************************************************************
+*/
+
+void  Host_FillSetup (USB_INT08U   bm_request_type,
+                      USB_INT08U   b_request,
+                      USB_INT16U   w_value,
+                      USB_INT16U   w_index,
+                      USB_INT16U   w_length)
+{
+    int i;
+    for (i=0;i<w_length;i++)
+        TDBuffer[i] = 0;
+    
+    TDBuffer[0] = bm_request_type;
+    TDBuffer[1] = b_request;
+    WriteLE16U(&TDBuffer[2], w_value);
+    WriteLE16U(&TDBuffer[4], w_index);
+    WriteLE16U(&TDBuffer[6], w_length);
+}
+
+
+
+/*
+**************************************************************************************************************
+*                                         INITIALIZE THE TRANSFER DESCRIPTOR
+*
+* Description: This function initializes transfer descriptor
+*
+* Arguments  : Pointer to TD structure
+*
+* Returns    : None
+*
+**************************************************************************************************************
+*/
+
+void  Host_TDInit (volatile  HCTD *td)
+{
+
+    td->Control    = 0;
+    td->CurrBufPtr = 0;
+    td->Next       = 0;
+    td->BufEnd     = 0;
+}
+
+/*
+**************************************************************************************************************
+*                                         INITIALIZE THE ENDPOINT DESCRIPTOR
+*
+* Description: This function initializes endpoint descriptor
+*
+* Arguments  : Pointer to ED strcuture
+*
+* Returns    : None
+*
+**************************************************************************************************************
+*/
+
+void  Host_EDInit (volatile  HCED *ed)
+{
+
+    ed->Control = 0;
+    ed->TailTd  = 0;
+    ed->HeadTd  = 0;
+    ed->Next    = 0;
+}
+
+/*
+**************************************************************************************************************
+*                                 INITIALIZE HOST CONTROLLER COMMUNICATIONS AREA
+*
+* Description: This function initializes host controller communications area
+*
+* Arguments  : Pointer to HCCA
+*
+* Returns    : 
+*
+**************************************************************************************************************
+*/
+
+void  Host_HCCAInit (volatile  HCCA  *hcca)
+{
+    USB_INT32U  i;
+
+
+    for (i = 0; i < 32; i++) {
+
+        hcca->IntTable[i] = 0;
+        hcca->FrameNumber = 0;
+        hcca->DoneHead    = 0;
+    }
+
+}
+
+/*
+**************************************************************************************************************
+*                                         WAIT FOR WDH INTERRUPT
+*
+* Description: This function is infinite loop which breaks when ever a WDH interrupt rises
+*
+* Arguments  : None
+*
+* Returns    : None
+*
+**************************************************************************************************************
+*/
+
+void  Host_WDHWait (void)
+{
+  while (!HOST_WdhIntr)
+      __WFI();
+
+  HOST_WdhIntr = 0;
+}
+
+/*
+**************************************************************************************************************
+*                                         READ LE 32U
+*
+* Description: This function is used to read an unsigned integer from a character buffer in the platform
+*              containing little endian processor
+*
+* Arguments  : pmem    Pointer to the character buffer
+*
+* Returns    : val     Unsigned integer
+*
+**************************************************************************************************************
+*/
+
+USB_INT32U  ReadLE32U (volatile  USB_INT08U  *pmem)
+{
+    USB_INT32U val = *(USB_INT32U*)pmem;
+#ifdef __BIG_ENDIAN
+    return __REV(val);
+#else
+    return val;
+#endif    
+}
+
+/*
+**************************************************************************************************************
+*                                        WRITE LE 32U
+*
+* Description: This function is used to write an unsigned integer into a charecter buffer in the platform 
+*              containing little endian processor.
+*
+* Arguments  : pmem    Pointer to the charecter buffer
+*              val     Integer value to be placed in the charecter buffer
+*
+* Returns    : None
+*
+**************************************************************************************************************
+*/
+
+void  WriteLE32U (volatile  USB_INT08U  *pmem,
+                            USB_INT32U   val)
+{
+#ifdef __BIG_ENDIAN
+    *(USB_INT32U*)pmem = __REV(val);
+#else
+    *(USB_INT32U*)pmem = val;
+#endif
+}
+
+/*
+**************************************************************************************************************
+*                                          READ LE 16U
+*
+* Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
+*              containing little endian processor
+*
+* Arguments  : pmem    Pointer to the charecter buffer
+*
+* Returns    : val     Unsigned short integer
+*
+**************************************************************************************************************
+*/
+
+USB_INT16U  ReadLE16U (volatile  USB_INT08U  *pmem)
+{
+    USB_INT16U val = *(USB_INT16U*)pmem;
+#ifdef __BIG_ENDIAN
+    return __REV16(val);
+#else
+    return val;
+#endif    
+}
+
+/*
+**************************************************************************************************************
+*                                         WRITE LE 16U
+*
+* Description: This function is used to write an unsigned short integer into a charecter buffer in the
+*              platform containing little endian processor
+*
+* Arguments  : pmem    Pointer to the charecter buffer
+*              val     Value to be placed in the charecter buffer
+*
+* Returns    : None
+*
+**************************************************************************************************************
+*/
+
+void  WriteLE16U (volatile  USB_INT08U  *pmem,
+                            USB_INT16U   val)
+{
+#ifdef __BIG_ENDIAN
+    *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
+#else
+    *(USB_INT16U*)pmem = val;
+#endif
+}
+
+/*
+**************************************************************************************************************
+*                                         READ BE 32U
+*
+* Description: This function is used to read an unsigned integer from a charecter buffer in the platform
+*              containing big endian processor
+*
+* Arguments  : pmem    Pointer to the charecter buffer
+*
+* Returns    : val     Unsigned integer
+*
+**************************************************************************************************************
+*/
+
+USB_INT32U  ReadBE32U (volatile  USB_INT08U  *pmem)
+{
+    USB_INT32U val = *(USB_INT32U*)pmem;
+#ifdef __BIG_ENDIAN
+    return val;
+#else
+    return __REV(val);
+#endif
+}
+
+/*
+**************************************************************************************************************
+*                                         WRITE BE 32U
+*
+* Description: This function is used to write an unsigned integer into a charecter buffer in the platform
+*              containing big endian processor
+*
+* Arguments  : pmem    Pointer to the charecter buffer
+*              val     Value to be placed in the charecter buffer
+*
+* Returns    : None
+*
+**************************************************************************************************************
+*/
+
+void  WriteBE32U (volatile  USB_INT08U  *pmem,
+                            USB_INT32U   val)
+{
+#ifdef __BIG_ENDIAN
+    *(USB_INT32U*)pmem = val;
+#else
+    *(USB_INT32U*)pmem = __REV(val);
+#endif
+}
+
+/*
+**************************************************************************************************************
+*                                         READ BE 16U
+*
+* Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
+*              containing big endian processor
+*
+* Arguments  : pmem    Pointer to the charecter buffer
+*
+* Returns    : val     Unsigned short integer
+*
+**************************************************************************************************************
+*/
+
+USB_INT16U  ReadBE16U (volatile  USB_INT08U  *pmem)
+{
+    USB_INT16U val = *(USB_INT16U*)pmem;
+#ifdef __BIG_ENDIAN
+    return val;
+#else
+    return __REV16(val);
+#endif    
+}
+
+/*
+**************************************************************************************************************
+*                                         WRITE BE 16U
+*
+* Description: This function is used to write an unsigned short integer into the charecter buffer in the
+*              platform containing big endian processor
+*
+* Arguments  : pmem    Pointer to the charecter buffer
+*              val     Value to be placed in the charecter buffer
+*
+* Returns    : None
+*
+**************************************************************************************************************
+*/
+
+void  WriteBE16U (volatile  USB_INT08U  *pmem,
+                            USB_INT16U   val)
+{
+#ifdef __BIG_ENDIAN
+    *(USB_INT16U*)pmem = val;
+#else
+    *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
+#endif
+}
diff -r 000000000000 -r d920d64db582 USBHostLite/usbhost_lpc17xx.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHostLite/usbhost_lpc17xx.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,254 @@
+/*
+**************************************************************************************************************
+*                                                 NXP USB Host Stack
+*
+*                                     (c) Copyright 2008, NXP SemiConductors
+*                                     (c) Copyright 2008, OnChip  Technologies LLC
+*                                                 All Rights Reserved
+*
+*                                                  www.nxp.com
+*                                               www.onchiptech.com
+*
+* File           : usbhost_lpc17xx.h
+* Programmer(s)  : Ravikanth.P
+* Version        :
+*
+**************************************************************************************************************
+*/
+
+#ifndef USBHOST_LPC17xx_H
+#define USBHOST_LPC17xx_H
+
+/*
+**************************************************************************************************************
+*                                       INCLUDE HEADER FILES
+**************************************************************************************************************
+*/
+
+#include    "usbhost_inc.h"
+
+/*
+**************************************************************************************************************
+*                                        PRINT CONFIGURATION
+**************************************************************************************************************
+*/
+
+#define  PRINT_ENABLE         1
+
+#if PRINT_ENABLE
+#define  PRINT_Log(...)       printf(__VA_ARGS__)
+#define  PRINT_Err(rc)        printf("ERROR: In %s at Line %u - rc = %d\n", __FUNCTION__, __LINE__, rc)
+
+#else 
+#define  PRINT_Log(...)       do {} while(0)
+#define  PRINT_Err(rc)        do {} while(0)
+
+#endif
+
+/*
+**************************************************************************************************************
+*                                        GENERAL DEFINITIONS
+**************************************************************************************************************
+*/
+
+#define  DESC_LENGTH(x)  x[0]
+#define  DESC_TYPE(x)    x[1]
+
+
+#define  HOST_GET_DESCRIPTOR(descType, descIndex, data, length)                      \
+         Host_CtrlRecv(USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE, GET_DESCRIPTOR,    \
+         (descType << 8)|(descIndex), 0, length, data)
+
+#define  HOST_SET_ADDRESS(new_addr)                                                  \
+         Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE, SET_ADDRESS,       \
+         new_addr, 0, 0, NULL)
+
+#define  USBH_SET_CONFIGURATION(configNum)                                           \
+         Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE, SET_CONFIGURATION, \
+         configNum, 0, 0, NULL)
+
+#define  USBH_SET_INTERFACE(ifNum, altNum)                                           \
+         Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_INTERFACE, SET_INTERFACE,  \
+         altNum, ifNum, 0, NULL)
+
+/*
+**************************************************************************************************************
+*                                  OHCI OPERATIONAL REGISTER FIELD DEFINITIONS
+**************************************************************************************************************
+*/
+
+                                            /* ------------------ HcControl Register ---------------------  */
+#define  OR_CONTROL_CLE                 0x00000010
+#define  OR_CONTROL_BLE                 0x00000020
+#define  OR_CONTROL_HCFS                0x000000C0
+#define  OR_CONTROL_HC_OPER             0x00000080
+                                            /* ----------------- HcCommandStatus Register ----------------- */
+#define  OR_CMD_STATUS_HCR              0x00000001
+#define  OR_CMD_STATUS_CLF              0x00000002
+#define  OR_CMD_STATUS_BLF              0x00000004
+                                            /* --------------- HcInterruptStatus Register ----------------- */
+#define  OR_INTR_STATUS_WDH             0x00000002
+#define  OR_INTR_STATUS_RHSC            0x00000040
+                                            /* --------------- HcInterruptEnable Register ----------------- */
+#define  OR_INTR_ENABLE_WDH             0x00000002
+#define  OR_INTR_ENABLE_RHSC            0x00000040
+#define  OR_INTR_ENABLE_MIE             0x80000000
+                                            /* ---------------- HcRhDescriptorA Register ------------------ */
+#define  OR_RH_STATUS_LPSC              0x00010000
+#define  OR_RH_STATUS_DRWE              0x00008000
+                                            /* -------------- HcRhPortStatus[1:NDP] Register -------------- */
+#define  OR_RH_PORT_CCS                 0x00000001
+#define  OR_RH_PORT_PRS                 0x00000010
+#define  OR_RH_PORT_CSC                 0x00010000
+#define  OR_RH_PORT_PRSC                0x00100000
+
+
+/*
+**************************************************************************************************************
+*                                               FRAME INTERVAL
+**************************************************************************************************************
+*/
+
+#define  FI                     0x2EDF           /* 12000 bits per frame (-1)                               */
+#define  DEFAULT_FMINTERVAL     ((((6 * (FI - 210)) / 7) << 16) | FI)
+
+/*
+**************************************************************************************************************
+*                                       TRANSFER DESCRIPTOR CONTROL FIELDS
+**************************************************************************************************************
+*/
+
+#define  TD_ROUNDING        (USB_INT32U) (0x00040000)        /* Buffer Rounding                             */
+#define  TD_SETUP           (USB_INT32U)(0)                  /* Direction of Setup Packet                   */
+#define  TD_IN              (USB_INT32U)(0x00100000)         /* Direction In                                */
+#define  TD_OUT             (USB_INT32U)(0x00080000)         /* Direction Out                               */
+#define  TD_DELAY_INT(x)    (USB_INT32U)((x) << 21)          /* Delay Interrupt                             */
+#define  TD_TOGGLE_0        (USB_INT32U)(0x02000000)         /* Toggle 0                                    */
+#define  TD_TOGGLE_1        (USB_INT32U)(0x03000000)         /* Toggle 1                                    */
+#define  TD_CC              (USB_INT32U)(0xF0000000)         /* Completion Code                             */
+
+/*
+**************************************************************************************************************
+*                                       USB STANDARD REQUEST DEFINITIONS
+**************************************************************************************************************
+*/
+
+#define  USB_DESCRIPTOR_TYPE_DEVICE                     1
+#define  USB_DESCRIPTOR_TYPE_CONFIGURATION              2
+#define  USB_DESCRIPTOR_TYPE_INTERFACE                  4
+#define  USB_DESCRIPTOR_TYPE_ENDPOINT                   5
+                                                    /*  ----------- Control RequestType Fields  ----------- */
+#define  USB_DEVICE_TO_HOST         0x80
+#define  USB_HOST_TO_DEVICE         0x00
+#define  USB_REQUEST_TYPE_CLASS     0x20
+#define  USB_RECIPIENT_DEVICE       0x00
+#define  USB_RECIPIENT_INTERFACE    0x01
+                                                    /* -------------- USB Standard Requests  -------------- */
+#define  SET_ADDRESS                 5
+#define  GET_DESCRIPTOR              6
+#define  SET_CONFIGURATION           9
+#define  SET_INTERFACE              11
+
+/*
+**************************************************************************************************************
+*                                       TYPE DEFINITIONS
+**************************************************************************************************************
+*/
+
+typedef struct hcEd {                       /* ----------- HostController EndPoint Descriptor ------------- */
+    volatile  USB_INT32U  Control;              /* Endpoint descriptor control                              */
+    volatile  USB_INT32U  TailTd;               /* Physical address of tail in Transfer descriptor list     */
+    volatile  USB_INT32U  HeadTd;               /* Physcial address of head in Transfer descriptor list     */
+    volatile  USB_INT32U  Next;                 /* Physical address of next Endpoint descriptor             */
+} HCED;
+
+typedef struct hcTd {                       /* ------------ HostController Transfer Descriptor ------------ */
+    volatile  USB_INT32U  Control;              /* Transfer descriptor control                              */
+    volatile  USB_INT32U  CurrBufPtr;           /* Physical address of current buffer pointer               */
+    volatile  USB_INT32U  Next;                 /* Physical pointer to next Transfer Descriptor             */
+    volatile  USB_INT32U  BufEnd;               /* Physical address of end of buffer                        */
+} HCTD;
+
+typedef struct hcca {                       /* ----------- Host Controller Communication Area ------------  */
+    volatile  USB_INT32U  IntTable[32];         /* Interrupt Table                                          */
+    volatile  USB_INT32U  FrameNumber;          /* Frame Number                                             */
+    volatile  USB_INT32U  DoneHead;             /* Done Head                                                */
+    volatile  USB_INT08U  Reserved[116];        /* Reserved for future use                                  */
+    volatile  USB_INT08U  Unknown[4];           /* Unused                                                   */
+} HCCA;
+
+/*
+**************************************************************************************************************
+*                                     EXTERN DECLARATIONS
+**************************************************************************************************************
+*/
+
+extern  volatile  HCED        *EDBulkIn;        /* BulkIn endpoint descriptor  structure                    */
+extern  volatile  HCED        *EDBulkOut;       /* BulkOut endpoint descriptor structure                    */
+extern  volatile  HCTD        *TDHead;          /* Head transfer descriptor structure                       */
+extern  volatile  HCTD        *TDTail;          /* Tail transfer descriptor structure                       */
+extern  volatile  USB_INT08U  *TDBuffer;        /* Current Buffer Pointer of transfer descriptor            */
+
+/*
+**************************************************************************************************************
+*                                       FUNCTION PROTOTYPES
+**************************************************************************************************************
+*/
+
+void        Host_Init     (void);
+
+extern "C" void USB_IRQHandler(void)  __irq;
+
+USB_INT32S  Host_EnumDev  (void);
+
+USB_INT32S  Host_ProcessTD(volatile  HCED       *ed,
+                           volatile  USB_INT32U  token,
+                           volatile  USB_INT08U *buffer,
+                                     USB_INT32U  buffer_len);
+
+void        Host_DelayUS  (          USB_INT32U    delay);
+void        Host_DelayMS  (          USB_INT32U    delay);
+
+
+void        Host_TDInit   (volatile  HCTD *td);
+void        Host_EDInit   (volatile  HCED *ed);
+void        Host_HCCAInit (volatile  HCCA  *hcca);
+
+USB_INT32S  Host_CtrlRecv (          USB_INT08U   bm_request_type,
+                                     USB_INT08U   b_request,
+                                     USB_INT16U   w_value,
+                                     USB_INT16U   w_index,
+                                     USB_INT16U   w_length,
+                           volatile  USB_INT08U  *buffer);
+
+USB_INT32S  Host_CtrlSend (          USB_INT08U   bm_request_type,
+                                     USB_INT08U   b_request,
+                                     USB_INT16U   w_value,
+                                     USB_INT16U   w_index,
+                                     USB_INT16U   w_length,
+                           volatile  USB_INT08U  *buffer);
+
+void        Host_FillSetup(          USB_INT08U   bm_request_type,
+                                     USB_INT08U   b_request,
+                                     USB_INT16U   w_value,
+                                     USB_INT16U   w_index,
+                                     USB_INT16U   w_length);
+
+
+void        Host_WDHWait  (void);
+
+
+USB_INT32U  ReadLE32U     (volatile  USB_INT08U  *pmem);
+void        WriteLE32U    (volatile  USB_INT08U  *pmem,
+                                     USB_INT32U   val);
+USB_INT16U  ReadLE16U     (volatile  USB_INT08U  *pmem);
+void        WriteLE16U    (volatile  USB_INT08U  *pmem,
+                                     USB_INT16U   val);
+USB_INT32U  ReadBE32U     (volatile  USB_INT08U  *pmem);
+void        WriteBE32U    (volatile  USB_INT08U  *pmem,
+                                     USB_INT32U   val);
+USB_INT16U  ReadBE16U     (volatile  USB_INT08U  *pmem);
+void        WriteBE16U    (volatile  USB_INT08U  *pmem,
+                                     USB_INT16U   val);
+
+#endif
diff -r 000000000000 -r d920d64db582 USBHostLite/usbhost_ms.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHostLite/usbhost_ms.c	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,455 @@
+/*
+**************************************************************************************************************
+*                                                 NXP USB Host Stack
+*
+*                                     (c) Copyright 2008, NXP SemiConductors
+*                                     (c) Copyright 2008, OnChip  Technologies LLC
+*                                                 All Rights Reserved
+*
+*                                                  www.nxp.com
+*                                               www.onchiptech.com
+*
+* File           : usbhost_ms.c
+* Programmer(s)  : Ravikanth.P
+* Version        :
+*
+**************************************************************************************************************
+*/
+
+/*
+**************************************************************************************************************
+*                                       INCLUDE HEADER FILES
+**************************************************************************************************************
+*/
+
+#include  "usbhost_ms.h"
+
+/*
+**************************************************************************************************************
+*                                         GLOBAL VARIABLES
+**************************************************************************************************************
+*/
+
+USB_INT32U  MS_BlkSize;
+
+/*
+**************************************************************************************************************
+*                                      INITIALIZE MASS STORAGE INTERFACE
+*
+* Description: This function initializes the mass storage interface
+*
+* Arguments  : None
+*
+* Returns    : OK                      if Success
+*              ERR_INVALID_BOOTSIG    if Failed
+*
+**************************************************************************************************************
+*/
+
+USB_INT32S MS_Init (USB_INT32U *blkSize, USB_INT32U *numBlks, USB_INT08U *inquiryResult)
+{
+    USB_INT08U  retry;
+    USB_INT32S  rc;
+
+    MS_GetMaxLUN();                                                    /* Get maximum logical unit number   */
+    retry  = 80;
+    while(retry) {
+        rc = MS_TestUnitReady();                                       /* Test whether the unit is ready    */
+        if (rc == OK) {
+            break;
+        }
+        MS_GetSenseInfo();                                             /* Get sense information             */
+        retry--;
+    }
+    if (rc != OK) {
+        PRINT_Err(rc);
+        return (rc);
+    }
+    rc = MS_ReadCapacity(numBlks, blkSize);                         /* Read capacity of the disk         */
+    MS_BlkSize = *blkSize;                        // Set global
+    rc = MS_Inquire (inquiryResult);
+    return (rc);
+}
+/*
+**************************************************************************************************************
+*                                         PARSE THE CONFIGURATION
+*
+* Description: This function is used to parse the configuration
+*
+* Arguments  : None
+*
+* Returns    : OK                      if Success
+*              ERR_INVALID_BOOTSIG    if Failed
+*
+**************************************************************************************************************
+*/
+
+USB_INT32S  MS_ParseConfiguration (void)
+{
+    volatile  USB_INT08U  *desc_ptr;
+              USB_INT08U   ms_int_found;
+
+
+    desc_ptr     = TDBuffer;
+    ms_int_found = 0;
+
+    if (desc_ptr[1] != USB_DESCRIPTOR_TYPE_CONFIGURATION) {    
+        return (ERR_BAD_CONFIGURATION);
+    }
+    desc_ptr += desc_ptr[0];
+
+    while (desc_ptr != TDBuffer + ReadLE16U(&TDBuffer[2])) {
+
+        switch (desc_ptr[1]) {
+
+            case USB_DESCRIPTOR_TYPE_INTERFACE:                       /* If it is an interface descriptor   */
+                 if (desc_ptr[5] == MASS_STORAGE_CLASS &&             /* check if the class is mass storage */
+                     desc_ptr[6] == MASS_STORAGE_SUBCLASS_SCSI &&     /* check if the subclass is SCSI      */
+                     desc_ptr[7] == MASS_STORAGE_PROTOCOL_BO) {       /* check if the protocol is Bulk only */
+                     ms_int_found = 1;
+                     desc_ptr    += desc_ptr[0];                      /* Move to next descriptor start      */
+                 }
+                 break;
+
+            case USB_DESCRIPTOR_TYPE_ENDPOINT:                        /* If it is an endpoint descriptor    */
+                 if ((desc_ptr[3] & 0x03) == 0x02) {                  /* If it is Bulk endpoint             */
+                     if (desc_ptr[2] & 0x80) {                        /* If it is In endpoint               */
+                         EDBulkIn->Control =  1                             |      /* USB address           */
+                                              ((desc_ptr[2] & 0x7F) << 7)   |      /* Endpoint address      */
+                                              (2 << 11)                     |      /* direction             */
+                                              (ReadLE16U(&desc_ptr[4]) << 16);     /* MaxPkt Size           */
+                         desc_ptr += desc_ptr[0];                     /* Move to next descriptor start      */
+                     } else {                                         /* If it is Out endpoint              */
+                         EDBulkOut->Control = 1                             |      /* USB address           */
+                                              ((desc_ptr[2] & 0x7F) << 7)   |      /* Endpoint address      */
+                                              (1 << 11)                     |      /* direction             */
+                                              (ReadLE16U(&desc_ptr[4]) << 16);     /* MaxPkt Size           */
+                         desc_ptr += desc_ptr[0];                     /* Move to next descriptor start      */
+                     }
+                 } else {                                             /* If it is not bulk end point        */
+                     desc_ptr += desc_ptr[0];                         /* Move to next descriptor start      */
+                 }
+                 break;
+
+            default:                                 /* If the descriptor is neither interface nor endpoint */
+                 desc_ptr += desc_ptr[0];                             /* Move to next descriptor start      */
+                 break;
+        }
+    }
+    if (ms_int_found) {
+        PRINT_Log("Mass Storage device connected\n");
+        return (OK);
+    } else {
+        PRINT_Log("Not a Mass Storage device\n");
+        return (ERR_NO_MS_INTERFACE);
+    }
+}
+
+/*
+**************************************************************************************************************
+*                                         GET MAXIMUM LOGICAL UNIT
+*
+* Description: This function returns the maximum logical unit from the device
+*
+* Arguments  : None
+*
+* Returns    : OK                      if Success
+*              ERR_INVALID_BOOTSIG    if Failed
+*
+**************************************************************************************************************
+*/
+
+USB_INT32S  MS_GetMaxLUN (void)
+{
+    USB_INT32S  rc;
+
+
+    rc = Host_CtrlRecv(USB_DEVICE_TO_HOST | USB_REQUEST_TYPE_CLASS | USB_RECIPIENT_INTERFACE,
+                       MS_GET_MAX_LUN_REQ,
+                       0,
+                       0,
+                       1,
+                       TDBuffer);
+    return (rc); 
+}
+
+/*
+**************************************************************************************************************
+*                                          GET SENSE INFORMATION
+*
+* Description: This function is used to get sense information from the device
+*
+* Arguments  : None
+*
+* Returns    : OK       if Success
+*              ERROR    if Failed
+*
+**************************************************************************************************************
+*/
+
+USB_INT32S  MS_GetSenseInfo (void)
+{
+    USB_INT32S  rc;
+
+
+    Fill_MSCommand(0, 0, 0, MS_DATA_DIR_IN, SCSI_CMD_REQUEST_SENSE, 6);
+    rc = Host_ProcessTD(EDBulkOut, TD_OUT, TDBuffer, CBW_SIZE);
+    if (rc == OK) {
+        rc = Host_ProcessTD(EDBulkIn, TD_IN, TDBuffer, 18);
+        if (rc == OK) {
+            rc = Host_ProcessTD(EDBulkIn, TD_IN, TDBuffer, CSW_SIZE);
+            if (rc == OK) {
+                if (TDBuffer[12] != 0) {
+                    rc = ERR_MS_CMD_FAILED;
+                }
+            }
+        }
+    }
+    return (rc);
+}
+
+/*
+**************************************************************************************************************
+*                                           TEST UNIT READY
+*
+* Description: This function is used to test whether the unit is ready or not
+*
+* Arguments  : None
+*
+* Returns    : OK       if Success
+*              ERROR    if Failed
+*
+**************************************************************************************************************
+*/
+
+USB_INT32S  MS_TestUnitReady (void)
+{
+    USB_INT32S  rc;
+
+
+    Fill_MSCommand(0, 0, 0, MS_DATA_DIR_NONE, SCSI_CMD_TEST_UNIT_READY, 6);
+    rc = Host_ProcessTD(EDBulkOut, TD_OUT, TDBuffer, CBW_SIZE);
+    if (rc == OK) {
+        rc = Host_ProcessTD(EDBulkIn, TD_IN, TDBuffer, CSW_SIZE);
+        if (rc == OK) {        
+            if (TDBuffer[12] != 0) {
+                rc = ERR_MS_CMD_FAILED;
+            }
+        }
+    }
+    return (rc);
+}
+
+/*
+**************************************************************************************************************
+*                                            READ CAPACITY
+*
+* Description: This function is used to read the capacity of the mass storage device
+*
+* Arguments  : None
+*
+* Returns    : OK       if Success
+*              ERROR    if Failed
+*
+**************************************************************************************************************
+*/
+
+USB_INT32S MS_ReadCapacity (USB_INT32U *numBlks, USB_INT32U *blkSize)
+{
+    USB_INT32S  rc;
+
+
+    Fill_MSCommand(0, 0, 0, MS_DATA_DIR_IN, SCSI_CMD_READ_CAPACITY, 10);
+    rc = Host_ProcessTD(EDBulkOut, TD_OUT, TDBuffer, CBW_SIZE);
+    if (rc == OK) {
+        rc = Host_ProcessTD(EDBulkIn, TD_IN, TDBuffer, 8);
+        if (rc == OK) {
+            if (numBlks)
+                *numBlks = ReadBE32U(&TDBuffer[0]);
+            if (blkSize)
+                *blkSize = ReadBE32U(&TDBuffer[4]);
+            rc = Host_ProcessTD(EDBulkIn, TD_IN, TDBuffer, CSW_SIZE);
+            if (rc == OK) {
+                if (TDBuffer[12] != 0) {
+                    rc = ERR_MS_CMD_FAILED;
+                }
+            }
+        }
+    }
+    return (rc);
+}
+
+
+
+USB_INT32S MS_Inquire (USB_INT08U *response)
+{
+    USB_INT32S rc;
+    USB_INT32U i;
+
+    Fill_MSCommand(0, 0, 0, MS_DATA_DIR_IN, SCSI_CMD_INQUIRY, 6);
+    rc = Host_ProcessTD(EDBulkOut, TD_OUT, TDBuffer, CBW_SIZE);
+    if (rc == OK) {
+        rc = Host_ProcessTD(EDBulkIn, TD_IN, TDBuffer, INQUIRY_LENGTH);
+        if (rc == OK) {
+            if (response) {
+                for ( i = 0; i < INQUIRY_LENGTH; i++ )
+                    *response++ = *TDBuffer++;
+#if 0
+                MemCpy (response, TDBuffer, INQUIRY_LENGTH);
+                StrNullTrailingSpace (response->vendorID, SCSI_INQUIRY_VENDORCHARS);
+                StrNullTrailingSpace (response->productID, SCSI_INQUIRY_PRODUCTCHARS);
+                StrNullTrailingSpace (response->productRev, SCSI_INQUIRY_REVCHARS);
+#endif
+            }
+            rc = Host_ProcessTD(EDBulkIn, TD_IN, TDBuffer, CSW_SIZE);
+            if (rc == OK) {
+                if (TDBuffer[12] != 0) {    // bCSWStatus byte
+                    rc = ERR_MS_CMD_FAILED;
+                }
+            }
+        }
+    }
+    return (rc);
+}
+
+/*
+**************************************************************************************************************
+*                                         RECEIVE THE BULK DATA
+*
+* Description: This function is used to receive the bulk data
+*
+* Arguments  : None
+*
+* Returns    : OK                      if Success
+*              ERR_INVALID_BOOTSIG    if Failed
+*
+**************************************************************************************************************
+*/
+    
+USB_INT32S  MS_BulkRecv (          USB_INT32U   block_number,
+                                   USB_INT16U   num_blocks,
+                         volatile  USB_INT08U  *user_buffer)
+{
+    USB_INT32S  rc;
+    int i;
+    volatile USB_INT08U *c = user_buffer;
+    for (i=0;i<MS_BlkSize*num_blocks;i++)
+        *c++ = 0;
+
+
+    Fill_MSCommand(block_number, MS_BlkSize, num_blocks, MS_DATA_DIR_IN, SCSI_CMD_READ_10, 10);
+
+    rc = Host_ProcessTD(EDBulkOut, TD_OUT, TDBuffer, CBW_SIZE);
+    if (rc == OK) {
+        rc = Host_ProcessTD(EDBulkIn, TD_IN, user_buffer, MS_BlkSize * num_blocks);
+        if (rc == OK) {
+            rc = Host_ProcessTD(EDBulkIn, TD_IN, TDBuffer, CSW_SIZE);
+            if (rc == OK) {
+                if (TDBuffer[12] != 0) {
+                    rc = ERR_MS_CMD_FAILED;
+                }
+            }
+        }
+    }
+    return (rc);
+}
+
+/*
+**************************************************************************************************************
+*                                         SEND BULK DATA
+*
+* Description: This function is used to send the bulk data
+*
+* Arguments  : None
+*
+* Returns    : OK                      if Success
+*              ERR_INVALID_BOOTSIG    if Failed
+*
+**************************************************************************************************************
+*/
+
+USB_INT32S  MS_BulkSend (          USB_INT32U   block_number,
+                                   USB_INT16U   num_blocks,
+                         volatile  USB_INT08U  *user_buffer)
+{
+    USB_INT32S  rc;
+
+
+    Fill_MSCommand(block_number, MS_BlkSize, num_blocks, MS_DATA_DIR_OUT, SCSI_CMD_WRITE_10, 10);
+
+    rc = Host_ProcessTD(EDBulkOut, TD_OUT, TDBuffer, CBW_SIZE);
+    if (rc == OK) {
+        rc = Host_ProcessTD(EDBulkOut, TD_OUT, user_buffer, MS_BlkSize * num_blocks);
+        if (rc == OK) {
+            rc = Host_ProcessTD(EDBulkIn, TD_IN, TDBuffer, CSW_SIZE);
+            if (rc == OK) {
+                if (TDBuffer[12] != 0) {
+                    rc = ERR_MS_CMD_FAILED;
+                }
+            }
+        }
+    }
+    return (rc);
+}
+
+/*
+**************************************************************************************************************
+*                                         FILL MASS STORAGE COMMAND
+*
+* Description: This function is used to fill the mass storage command
+*
+* Arguments  : None
+*
+* Returns    : OK                      if Success
+*              ERR_INVALID_BOOTSIG    if Failed
+*
+**************************************************************************************************************
+*/
+
+void  Fill_MSCommand (USB_INT32U   block_number,
+                      USB_INT32U   block_size,
+                      USB_INT16U   num_blocks,
+                      MS_DATA_DIR  direction,
+                      USB_INT08U   scsi_cmd,
+                      USB_INT08U   scsi_cmd_len)
+{
+            USB_INT32U  data_len;
+    static  USB_INT32U  tag_cnt = 0;
+            USB_INT32U  cnt;
+
+
+    for (cnt = 0; cnt < CBW_SIZE; cnt++) {
+         TDBuffer[cnt] = 0;
+    }
+    switch(scsi_cmd) {
+
+        case SCSI_CMD_TEST_UNIT_READY:
+             data_len = 0;
+             break;
+        case SCSI_CMD_READ_CAPACITY:
+             data_len = 8;
+             break;
+        case SCSI_CMD_REQUEST_SENSE:
+             data_len = 18;
+             break;
+        case SCSI_CMD_INQUIRY:
+             data_len = 36;
+             break;
+        default:
+             data_len = block_size * num_blocks;
+             break;
+    }
+    WriteLE32U(TDBuffer, CBW_SIGNATURE);
+    WriteLE32U(&TDBuffer[4], tag_cnt);
+    WriteLE32U(&TDBuffer[8], data_len);
+    TDBuffer[12]     = (direction == MS_DATA_DIR_NONE) ? 0 : direction;
+    TDBuffer[14]     = scsi_cmd_len;                                   /* Length of the CBW                 */
+    TDBuffer[15]     = scsi_cmd;
+    if ((scsi_cmd     == SCSI_CMD_REQUEST_SENSE)
+     || (scsi_cmd     == SCSI_CMD_INQUIRY)) {
+        TDBuffer[19] = (USB_INT08U)data_len;
+    } else {
+        WriteBE32U(&TDBuffer[17], block_number);
+    }
+    WriteBE16U(&TDBuffer[22], num_blocks);
+}
diff -r 000000000000 -r d920d64db582 USBHostLite/usbhost_ms.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHostLite/usbhost_ms.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,101 @@
+/*
+**************************************************************************************************************
+*                                                 NXP USB Host Stack
+*
+*                                     (c) Copyright 2008, NXP SemiConductors
+*                                     (c) Copyright 2008, OnChip  Technologies LLC
+*                                                 All Rights Reserved
+*
+*                                                  www.nxp.com
+*                                               www.onchiptech.com
+*
+* File           : usbhost_ms.h
+* Programmer(s)  : Ravikanth.P
+* Version        :
+*
+**************************************************************************************************************
+*/
+
+#ifndef  USBHOST_MS_H
+#define  USBHOST_MS_H
+
+/*
+**************************************************************************************************************
+*                                       INCLUDE HEADER FILES
+**************************************************************************************************************
+*/
+
+#include  "usbhost_inc.h"
+
+/*
+**************************************************************************************************************
+*                               MASS STORAGE SPECIFIC DEFINITIONS
+**************************************************************************************************************
+*/
+
+#define    MS_GET_MAX_LUN_REQ            0xFE
+#define    MASS_STORAGE_CLASS            0x08
+#define    MASS_STORAGE_SUBCLASS_SCSI    0x06
+#define    MASS_STORAGE_PROTOCOL_BO      0x50
+
+#define    INQUIRY_LENGTH                36
+/*
+**************************************************************************************************************
+*                                  SCSI SPECIFIC DEFINITIONS
+**************************************************************************************************************
+*/
+
+#define  CBW_SIGNATURE               0x43425355
+#define  CSW_SIGNATURE               0x53425355
+#define  CBW_SIZE                      31
+#define  CSW_SIZE                      13
+#define  CSW_CMD_PASSED              0x00
+#define  SCSI_CMD_REQUEST_SENSE      0x03
+#define  SCSI_CMD_TEST_UNIT_READY    0x00
+#define  SCSI_CMD_INQUIRY            0x12
+#define  SCSI_CMD_READ_10            0x28
+#define  SCSI_CMD_READ_CAPACITY      0x25
+#define  SCSI_CMD_WRITE_10           0x2A
+
+/*
+**************************************************************************************************************
+*                                       TYPE DEFINITIONS
+**************************************************************************************************************
+*/
+
+typedef enum  ms_data_dir {
+
+    MS_DATA_DIR_IN     = 0x80,
+    MS_DATA_DIR_OUT    = 0x00,
+    MS_DATA_DIR_NONE   = 0x01
+
+} MS_DATA_DIR;
+
+/*
+**************************************************************************************************************
+*                                     FUNCTION PROTOTYPES
+**************************************************************************************************************
+*/
+
+USB_INT32S  MS_BulkRecv          (          USB_INT32U    block_number,
+                                            USB_INT16U    num_blocks,
+                                  volatile  USB_INT08U   *user_buffer);
+
+USB_INT32S  MS_BulkSend          (          USB_INT32U    block_number,
+                                            USB_INT16U    num_blocks,
+                                  volatile  USB_INT08U   *user_buffer);
+USB_INT32S  MS_ParseConfiguration(void);
+USB_INT32S  MS_TestUnitReady     (void);
+USB_INT32S  MS_ReadCapacity (USB_INT32U *numBlks, USB_INT32U *blkSize);
+USB_INT32S  MS_GetMaxLUN         (void);
+USB_INT32S  MS_GetSenseInfo      (void);
+USB_INT32S  MS_Init (USB_INT32U *blkSize, USB_INT32U *numBlks, USB_INT08U *inquiryResult);
+USB_INT32S  MS_Inquire (USB_INT08U *response);
+
+void        Fill_MSCommand       (          USB_INT32U    block_number,
+                                            USB_INT32U    block_size,
+                                            USB_INT16U    num_blocks,
+                                            MS_DATA_DIR   direction,
+                                            USB_INT08U    scsi_cmd,
+                                            USB_INT08U    scsi_cmd_len);
+#endif
diff -r 000000000000 -r d920d64db582 aic23b_comm.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/aic23b_comm.h	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,167 @@
+#include "mbed.h"
+
+//extern void aic23b_init(void);
+//extern int aic23b_send(int addr,char ctrl_address,char ctrl_data);
+
+// Register map of TLV320AIC23B. See "TLV320AIC23B Data Manual" section 3.1.3
+// I2C ADDRESS(MODE=0,CS=0)=0011010b 
+#define AIC23B_ADDRESS  (52)
+///////////////////////////////////////////////////////////////////////
+// Control Address Bits 
+#define LEFT_LINE_INPUT_CHANNEL_VOLUME_CONTROL      (0x00 << 1)
+#define RIGHT_LINE_INPUT_CHANNEL_VOLUME_CONTROL     (0x01 << 1)
+#define LEFT_CHANNEL_HEADPHONE_VOLUME_CONTROL       ((0x02 << 1)|1)
+#define RIGHT_CHANNEL_HEADPHONE_VOLUME_CONTROL      ((0x03 << 1)|1)
+#define ANALOG_AUDIO_PATH_CONTROL                   (0x04 << 1)
+#define DIGITAL_AUDIO_PATH_CONTROL                  (0x05 << 1)
+#define POWER_DOWN_CONTROL                          (0x06 << 1)
+#define DIGITAL_AUDIO_INTERFACE_FORMAT              (0x07 << 1)
+#define SAMPLE_RATE_CONTROL                         (0x08 << 1)
+#define DIGITAL_INTERFACE_ACTIVATION                (0x09 << 1)
+#define RESET_REFGISTER                             (0x0F << 1)
+///////////////////////////////////////////////////////////////////////
+// Control Data Bits
+// LEFT_LINE_INPUT_CHANNEL_VOLUME_CONTROL(Address:0x00)
+// (bit7)LIM:   Left line input mute 0=Normal 1=Muted
+// (bit6)X:     Reserved
+// (bit5)X:     Reserved
+// (bit4)LIV4:
+// (bit3)LIV3:
+// (bit2)LIV2:
+// (bit1)LIV1:
+// (bit0)LIV0:  Left line input volume control(10111=0dB default)
+#define LIM_MUTE_DISABLED   (0<<7)
+#define LIV_VOLUME_DEFAULT  (0x17<<0)
+// ----------------------------------------------------------------------
+// RIGHT_LINE_INPUT_CHANNEL_VOLUME_CONTROL(Address:0x01)
+// (bit7)RIM:   Right line input mute 0=Normal 1=Muted
+// (bit6)X:     Reserved
+// (bit5)X:     Reserved
+// (bit4)RIV4:
+// (bit3)RIV3:
+// (bit2)RIV2:
+// (bit1)RIV1:
+// (bit0)RIV0:  Right line input volume control(10111=0dB default)
+#define RIM_MUTE_DISABLED   (0<<7)
+#define RIV_VOLUME_DEFAULT  (0x17<<0)
+// ----------------------------------------------------------------------
+// LEFT_CHANNEL_HEADPHONE_VOLUME_CONTROL(Address:0x02)
+// (bit7)LZC:   Left-channel Zero-cross detect 0=Off 1=On
+// (bit6)LHV6:
+// (bit5)LHV5:
+// (bit4)LHV4:
+// (bit3)LHV3:
+// (bit2)LHV2:
+// (bit1)LHV1:
+// (bit0)LHV0:  Left headphone volume control(1111001=0dB default,0110000=-73dB Mute)
+#define LZC_ZERO_CROSS_DETECT_ON    (1<<7)
+#define LHV_VOLUME_DEFAULT          90//(0x79<<0)
+// ----------------------------------------------------------------------
+// RIGHT_CHANNEL_HEADPHONE_VOLUME_CONTROL(Address:0x03)
+// (bit7)RZC:   Right-channel Zero-cross detect 0=Off 1=On
+// (bit6)RHV6:
+// (bit5)RHV5:
+// (bit4)RHV4:
+// (bit3)RHV3:
+// (bit2)RHV2:
+// (bit1)RHV1:
+// (bit0)RHV0:  Right headphone volume control(1111001=0dB default,0110000=-73dB Mute)
+#define RZC_ZERO_CROSS_DETECT_ON    (1<<7)
+#define RHV_VOLUME_DEFAULT          90//(0x79<<0)
+// ----------------------------------------------------------------------
+// ANALOG_AUDIO_PATH_CONTROL(Address:0x04)
+// (bit7)STA1:   
+// (bit6)STA0:
+// (bit5)STE:   (See "TLV320AIC23B DATA MANUAL" pp.3-3)
+// (bit4)DAC:   DAC select              0=DAC off   1=DAC on
+// (bit3)BYP:   Bypass                  0=Disabled  1=Enabled
+// (bit2)INSEL: Input select for ADC    0=Line,     1=Microphone  
+// (bit1)MICM:  Microphone mute         0=Normal,   1=Muted
+// (bit0)MICB:  Microphone boost        0=dB,       1=20dB
+// ----------------------------------------------------------------------
+// DIGITAL_AUDIO_PATH_CONTROL(Address:0x05)
+// (bit7)X:         Reserved   
+// (bit6)X:         Reserved
+// (bit5)X:         Reserved
+// (bit4)X:         Reserved
+// (bit3)DACM:      DAC soft mute           0=Disabled  1=Enabled
+// (bit2)DEEMP1:    
+// (bit1)DEEMP0:    De-enphasis control     0=Normal,   1=Muted
+// (bit0)ADCHP:     ADC high-pass filter    0=dB,       1=20dB
+#define DAC_MUTE_DISABLED       (0<<3)
+#define DE_EMPHASIS_DISABLED    (0x0 << 0)
+#define DE_EMPHASIS_32_KHZ      (0x1 << 0)
+#define DE_EMPHASIS_44_1_KHZ    (0x2 << 0)
+#define DE_EMPHASIS_48_KHZ      (0x3 << 0)
+// ----------------------------------------------------------------------
+// POWER_DOWN_CONTROL(Address:0x06)
+// (bit7)OFF:   Device power        0=On,   1=Off  
+// (bit6)CLK:   Clock               0=On,   1=Off
+// (bit5)OSC:   Oscillator          0=On,   1=Off
+// (bit4)OUT:   Outputs             0=On,   1=Off
+// (bit3)DAC:   DAC                 0=On,   1=Off
+// (bit2)ADC:   ADC                 0=On,   1=Off
+// (bit1)MIC:   Microphone input    0=On,   1=Off
+// (bit0)LINE:  Line input          0=On,   1=Off
+#define DEVICE_POWER_ON     (0<<7)
+#define CLOCK_ON            (0<<6)
+#define OSCILLATOR_ON       (0<<5)
+#define OUTPUTS_ON          (0<<4)
+#define DAC_ON              (0<<3)
+#define ADC_ON              (0<<2)
+#define MICROPHONE_INPUT_ON (0<<1)
+#define LINE_INPUT_ON       (0<<0)
+// ----------------------------------------------------------------------
+// DIGITAL_AUDUIO_INTERFACE_FORMAT(Address:0x07)
+// (bit7)X:         Reserved
+// (bit6)MS:        Master/Slave mode       0=Slave,    1=Master
+// (bit5)LRSWAP:    DAC left/right swap     0=Disabled, 1=Enabled
+// (bit4)LRP:       0=R-ch ON,LRCLKIN high, 1=R-ch ON,LRCLKIN low
+// (bit3)IWL1:
+// (bit2)IWL0:      Input bit length        00=16bit,   01=20bit,   10=24bit,   11=32bit
+// (bit1)FOR1:
+// (bit0)FOR0:      Data format             11=DSP,     10=I2S,     01=MSB first left algn.,   00=MSB right algn.
+#define MASTER_MODE                 (1<<6)
+#define INPUT_DATA_16_BIT_LENGTH    (0x00<<2)
+#define INPUT_DATA_20_BIT_LENGTH    (0x01<<2)
+#define INPUT_DATA_24_BIT_LENGTH    (0x02<<2)
+#define INPUT_DATA_32_BIT_LENGTH    (0x03<<2)
+#define DSP_FORMAT                  (0x03<<0)
+#define I2S_FORMAT                  (0x02<<0)
+#define MSB_FIRST_LEFT_ALIGN        (0x01<<0)
+#define MSB_FIRST_RIGHT_ALIGN       (0x00<<0)
+// ----------------------------------------------------------------------
+// SAMPLE_RATE_CONTROL(Address:0x08)
+// (bit7)CLKOUT:    Clock output divider    0=MCLK, 1=MCLK/2
+// (bit6)CLKIN:     Clock input divider     0=MCLK, 1=MCLK/2
+// (bit5)SR3:
+// (bit4)SR2:
+// (bit3)SR1:
+// (bit2)SR0:       (See "TLV320AIC23B DATA MANUAL" section 3.3.2.1 and 3.3.2.2)
+// (bit1)BOSR:
+// (bit0)USB/Normal:    Clock mode select   0=Normal,   1=USB
+#define SR_USB_44_1_KHZ_MODE         (0x08<<2)
+#define BOSR_USB_44_1_KHZ_MODE       (0x01<<1)
+#define USE_USB_CLOCK_44_1_KHZ_MODE  (0x01<<0)
+// ----------------------------------------------------------------------
+// DIGITAL_INTERFACE_ACTIVATION(Address:0x09)
+// (bit7)RES:
+// (bit6)RES:
+// (bit5)X:         Reserved
+// (bit4)X:         Reserved
+// (bit3)X:         Reserved
+// (bit2)X:         Reserved
+// (bit1)X:         Reserved
+// (bit0)ACT:       Activate interface      0=Inactive, 1=Active
+#define DIGITAL_INTERFACE_ACTIVE   (0x01<<0)
+// ----------------------------------------------------------------------
+// RESET_REGISTER(Address:0x0F)
+// (bit7)RES:
+// (bit6)RES:
+// (bit5)RES:
+// (bit4)RES:
+// (bit3)RES:
+// (bit2)RES:
+// (bit1)RES:
+// (bit0)RES:       Write 00000000 to this register triggers reset
+#define RESET  (0x00<<0)
diff -r 000000000000 -r d920d64db582 main.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,320 @@
+#include "mbed.h"
+#include "MSCFileSystem.h"
+#include "SDHCFileSystem.h"
+#include "TextLCD.h"
+#include "i2s_irq_test.h"
+#include "lpc17xx_i2s.h"
+#include "lpc17xx_clkpwr.h"
+#include "aic23b_comm.h"
+#include "string"
+#include "_bitio.h"
+
+#define _RGM_ADAPTIVE   1   /* 1:Adaptive 0:Constant */
+
+#define k_bits	0x07        //    k_bits:0x09 to 0x0b?    
+#define min_of_k 0x07 
+#define max_of_k 0x0b		/*for dynamic Rice-Golomb codings */
+
+DigitalOut led1(LED1); 
+DigitalOut led2(LED2);
+DigitalOut led3(LED3); 
+DigitalOut led4(LED4); 
+Serial pc(USBTX, USBRX); // tx, rx       
+I2C AIC23B(p9,p10);     //sda,scl
+
+TextLCD lcd(p24, p26, p27, p28, p29, p30);
+SDFileSystem sd(p11, p12, p13, p14, "sd");//p5,6,7,8
+//MSCFileSystem msc("msc"); // Mount flash drive under the name "msc"
+FILE    *infp,*outfp,*playlist;
+
+Ticker  tick;
+Ticker  fl_leds;
+
+#define AudioBufRow	256                         /* length of proc_r */  
+volatile short int AudioBuf[2][AudioBufRow];    /* Audio Data Buffer:AudioBuf[empty_c][proc_r] */
+volatile BYTE empty_c=0;			            /* Column of AudioBuf */
+volatile BYTE proc_r=0;				            /* Row of AudioBuf */			
+bool dac_semp;						            /* Write AudioBuf Complete? true:Yes, false:No */
+
+
+int aic23b_send(int addr,char ctrl_address,char ctrl_data){
+    int flag;
+    char cmd[2];
+    cmd[0]=ctrl_address;
+    cmd[1]=ctrl_data;
+    flag = AIC23B.write(addr, cmd, 2);
+    pc.printf("ADDR=0x%x, CTRL_ADD=0x%x, CTRL_DATA=0x%x, RESP=0x%x\r\n",(addr&0x7f),cmd[0],cmd[1],flag);
+    return (flag);
+}
+
+int aic23b_init(void){
+    int flag=0;
+    printf("*************************\r\nReset TLV320AIC23B\r\n*************************\r\n");
+    AIC23B.frequency(150000);   
+    flag = aic23b_send(AIC23B_ADDRESS,RESET_REFGISTER,RESET);
+    wait(0.1);
+    flag += aic23b_send(AIC23B_ADDRESS,POWER_DOWN_CONTROL,0);
+    wait(0.1);
+    flag += aic23b_send(AIC23B_ADDRESS,POWER_DOWN_CONTROL,1);
+    wait(0.1);
+    flag += aic23b_send(AIC23B_ADDRESS,DIGITAL_AUDIO_INTERFACE_FORMAT,(MASTER_MODE|INPUT_DATA_16_BIT_LENGTH|I2S_FORMAT));
+    wait(0.1);
+    flag += aic23b_send(AIC23B_ADDRESS,SAMPLE_RATE_CONTROL,(SR_USB_44_1_KHZ_MODE| BOSR_USB_44_1_KHZ_MODE| USE_USB_CLOCK_44_1_KHZ_MODE));
+    wait(0.1);
+    flag += aic23b_send(AIC23B_ADDRESS,ANALOG_AUDIO_PATH_CONTROL,0x10);
+    wait(0.1);
+    flag += aic23b_send(AIC23B_ADDRESS,DIGITAL_AUDIO_PATH_CONTROL,0);
+    wait(0.1);
+    flag += aic23b_send(AIC23B_ADDRESS,DIGITAL_INTERFACE_ACTIVATION,DIGITAL_INTERFACE_ACTIVE);
+    wait(0.1);
+    flag += aic23b_send(AIC23B_ADDRESS,LEFT_CHANNEL_HEADPHONE_VOLUME_CONTROL,LHV_VOLUME_DEFAULT);
+    wait(0.1);
+    flag += aic23b_send(AIC23B_ADDRESS,RIGHT_CHANNEL_HEADPHONE_VOLUME_CONTROL,RHV_VOLUME_DEFAULT);
+ 
+    if(!flag) {
+        printf("*************************\r\nReset OK\r\n*************************\r\n");
+        return 0;
+    }
+    else{ 
+        printf("*************************\r\nReset FAILED\r\n*************************\r\n");
+        return -1;
+    }
+}
+
+void pl_led_flash(void)
+{
+    if(led1){
+        led1 = 0;
+        led2 = 1;
+        return;
+    }
+
+    if(led2){
+        led2 = 0;
+        led3 = 1;
+        return;
+    }
+    
+    if(led3){
+        led3 = 0;
+        led4 = 1;
+        return;
+    }    
+    
+    if(led4){
+        led4 = 0;
+        led1 = 1;
+        return;
+    }       
+
+
+}
+
+void dac_out(void)
+{
+    volatile static short i,j;		// AudioBuf[j][i]
+    volatile uint32_t   DBufLR;     // Buffer Data to send I2S_TX 
+    uint16_t BufLPCnt;
+    for(BufLPCnt=0 ; BufLPCnt < 9 ; BufLPCnt++ )
+    {
+    	if(i >= AudioBufRow-1)
+    	{
+    		if(dac_semp)					/* colunm (empty_c) is full? true:Yes */
+    		{
+    			i=0;
+    			empty_c =(empty_c==1)?0:1;	/* empty_c:empty column of buffer AudioBuf, Because I2S_TX used these data */
+    			j=(empty_c==1)?0:1;			/* Change column which buffer is filled with data by function decode() */
+    			dac_semp = false;			/* false: empty_c is ready to get data from function decode() */
+    			
+    		}else{							/* Buffer is NOT ready to read? */
+    			return;						/* NO:return */
+    		}
+    	}
+    	//Send I2S_TX
+    	if(I2S_GetLevel(LPC_I2S, I2S_TX_MODE)==TXFIFO_FULL)break;
+    	DBufLR = (0xffff0000 & (AudioBuf[j][i++]<<16))|(0x0000ffff & AudioBuf[j][i++]);
+        I2S_Send(LPC_I2S,DBufLR);
+    } 
+}
+
+void encode(long int n){
+    int zero_shift = 0;
+    
+    if(n < 0){
+        putbit(0);                    // sign (put 0:if n as negative)
+        n = -n;                        // n = abs(n)
+        //printf("\t 0");
+    }
+    else{ 
+        putbit(1);                    // sign (put 1:if n as positive)
+        //printf("\t 1");
+    }
+    zero_shift = (n >> (_lsb_k));
+    //printf("\t shift= %d",zero_shift);
+    while(zero_shift > 0){
+
+        zero_shift--;
+        putbit(0);
+    }    // put n/(2^_lsb_k) 0's
+    
+    putbit(1);                        // terminating "1"
+    putbits(_lsb_k,rightbits(_lsb_k,n));
+    //printf("\t finish= %d \r\n",(n & ((1U<<_lsb_k)-1)));
+}
+
+
+
+void decode(void)
+{
+	volatile short		i=0,j=0;
+
+	volatile long int	diff=0,diff2=0;				/* differential of previous data buffer  */
+	volatile unsigned  int	buff_sign,zero_shift;	/* sign buffer,register for unary codings */
+	volatile long int	decode_buff;				
+	
+	volatile unsigned char	k1= k_bits;				/* Coding Parameter (init:k_bits) */
+	volatile unsigned char	k2= k_bits;
+	
+	init_bit_o();
+	init_bit_i();								/* init bit control function */
+	while(1){
+		
+		if(i!=empty_c)
+		{
+			if(j>=AudioBufRow-1)
+			{
+				i=empty_c;			/* Choose empty buffer*/
+				j=0;
+			}
+		}
+		
+		if (j<AudioBufRow-1) 
+		{
+			/* decode */
+			if((buff_sign = getbit()) == OVERRUN)break; /*get sign*/
+
+			zero_shift = 0;
+	    	while(getbit()==0)
+				zero_shift++;							/* decode unary code */
+			
+			decode_buff = (signed int)(zero_shift*(1U<<k1));	/*decode Rice-Golomb code*/
+			decode_buff += getbits(k1);
+			
+			if(!buff_sign)decode_buff =- decode_buff;	/*add sign */
+			diff =(diff + decode_buff);					/* get audio data */		
+        
+			AudioBuf[i][j]=(short int)(diff);			/* write AudioBuf */
+			j++;
+			
+			
+#if _RGM_ADAPTIVE
+			/* calc k */
+			if(zero_shift > 2)k1=k1+1;
+			if(zero_shift == 0)k1=k1-1;
+			if(k1 < min_of_k)k1 = min_of_k;
+			if(k1 > max_of_k)k1 = max_of_k; 
+#endif	
+			
+			if((buff_sign = getbit()) == OVERRUN)break; /* get sign */
+			
+			zero_shift = 0;
+			while(getbit()==0)
+				zero_shift++;									/* decode unary code */
+		
+			decode_buff = (signed int)(zero_shift*(1U<<k2));	/* decode Rice-Golomb code */
+			decode_buff += getbits(k2);			
+			
+			if(!buff_sign)decode_buff =- decode_buff;	/* add sign */
+			diff2 =(diff2 + decode_buff);				/* get Audio data */		
+        
+			AudioBuf[i][j]=(short int)(diff2);					/* Write Buffer */
+			j++;
+
+#if _RGM_ADAPTIVE			
+			/* calc k */
+			if(zero_shift > 2)k2=k2+1;
+			if(zero_shift == 0)k2=k2-1;
+			if(k2 < min_of_k)k2 = min_of_k;
+			if(k2 > max_of_k)k2 = max_of_k;
+#endif 
+		
+		}
+		if(j>=AudioBufRow-1){				/* AudioBuf is filled with data? */
+			dac_semp = true;
+		}
+	}
+}
+
+  
+int main() {
+
+    char s[256];
+    char* p;
+    
+    lcd.cls();
+    lcd.locate(0,0);
+    lcd.printf("I2S Codec:");
+    mbed_i2s_init();    //DAC:44100Hz sampling ,16bit ,Stereo ,MCLK Disable, TLV320AIC23B=Master
+    if(aic23b_init()==0){
+        lcd.locate(12,0);
+        lcd.printf("OK");
+    }else{
+        lcd.locate(12,0);
+        lcd.printf("NG");
+    }
+    Buffer_Init();
+    pc.printf("CCLKCFG= %d \r\n",LPC_SC->CCLKCFG);
+    pc.printf("I2S Send start.\r\n");
+    led1=1;
+    lcd.locate(0,1);
+    lcd.printf("> Please Wait..."); 
+ 
+    if ( NULL == (playlist = fopen( "/sd/play.txt", "r" )) ) {
+        printf( "\r\nError: The Playlist file cannot be accessed\r\n" );
+        return -1;
+    }
+
+
+    while(1){
+        if((fgets( s, 256, playlist ))==NULL){
+            fseek(playlist, 0L, SEEK_SET);
+            fgets( s, 256, playlist );
+        } 
+        p=strchr(s,'\n');
+        if(p!=NULL){
+            *p='\0';
+        
+        }                   //remove CR code for Macintosh text-file 
+        p=strchr(s,'\r');
+        if(p!=NULL){
+            *p='\0';
+        
+        }                   //remove LF code for Linux & Windows text-file  
+        printf("\r\n open file:%s \r\n",s); // cut '\n' symbol
+        lcd.locate(0,1);
+        lcd.printf(">               ");
+        s[15]='\0';                           
+        lcd.locate(1,1);
+        lcd.printf("%s",s);
+        if ( NULL == (infp = fopen( s, "r" )) ) {
+            printf( "\r\nError: The message file cannot be accessed\r\n" );
+            return -1;
+        }
+            
+        fseek(infp, 0L, SEEK_SET);
+        tick.attach_us(&dac_out, 181); //set 44.1kHz/8(word FIFO) sampling data
+        fl_leds.attach(&pl_led_flash,1);
+        
+        
+        decode();
+    
+        fclose( infp );
+        infp = NULL;    
+        tick.detach();
+        fl_leds.detach();
+                lcd.locate(0,1);
+        lcd.printf("> Please Wait...");    
+    }
+}
+
+ 
\ No newline at end of file
diff -r 000000000000 -r d920d64db582 mbed.bld
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed.bld	Wed Mar 30 06:05:24 2011 +0000
@@ -0,0 +1,1 @@
+http://mbed.org/users/mbed_official/code/mbed/builds/e2ac27c8e93e