xeye_ atsu / Mbed 2 deprecated I2S_AIC23B_RiceGolomb

パラメータを適応変化させる事により圧縮率を向上させた動的ライス・ゴロム符号を利用した可逆圧縮方式。圧縮ソフト、圧縮率のMATLABシミュレーションは詳細はInterface誌2011年8月号に掲載されるRX62Nマイコン連動特集にて掲載予定。

Dependencies:   mbed

I2S_Example/lpc17xx_i2s.h@0:d920d64db582, 2011-03-30 (annotated)

Committer:
lynxeyed_atsu
Date:
Wed Mar 30 06:05:24 2011 +0000
Revision:
0:d920d64db582
alpha

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lynxeyed_atsu 0:d920d64db582 1 /***********************************************************************//**
lynxeyed_atsu 0:d920d64db582 2 * @file lpc17xx_i2s.h
lynxeyed_atsu 0:d920d64db582 3 * @brief Contains all macro definitions and function prototypes
lynxeyed_atsu 0:d920d64db582 4 * support for I2S firmware library on LPC17xx
lynxeyed_atsu 0:d920d64db582 5 * @version 3.0
lynxeyed_atsu 0:d920d64db582 6 * @date 18. June. 2010
lynxeyed_atsu 0:d920d64db582 7 * @author NXP MCU SW Application Team
lynxeyed_atsu 0:d920d64db582 8 **************************************************************************
lynxeyed_atsu 0:d920d64db582 9 * Software that is described herein is for illustrative purposes only
lynxeyed_atsu 0:d920d64db582 10 * which provides customers with programming information regarding the
lynxeyed_atsu 0:d920d64db582 11 * products. This software is supplied "AS IS" without any warranties.
lynxeyed_atsu 0:d920d64db582 12 * NXP Semiconductors assumes no responsibility or liability for the
lynxeyed_atsu 0:d920d64db582 13 * use of the software, conveys no license or title under any patent,
lynxeyed_atsu 0:d920d64db582 14 * copyright, or mask work right to the product. NXP Semiconductors
lynxeyed_atsu 0:d920d64db582 15 * reserves the right to make changes in the software without
lynxeyed_atsu 0:d920d64db582 16 * notification. NXP Semiconductors also make no representation or
lynxeyed_atsu 0:d920d64db582 17 * warranty that such application will be suitable for the specified
lynxeyed_atsu 0:d920d64db582 18 * use without further testing or modification.
lynxeyed_atsu 0:d920d64db582 19 **************************************************************************/
lynxeyed_atsu 0:d920d64db582 20
lynxeyed_atsu 0:d920d64db582 21 /* Peripheral group ----------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 22 /** @defgroup I2S I2S
lynxeyed_atsu 0:d920d64db582 23 * @ingroup LPC1700CMSIS_FwLib_Drivers
lynxeyed_atsu 0:d920d64db582 24 * @{
lynxeyed_atsu 0:d920d64db582 25 */
lynxeyed_atsu 0:d920d64db582 26
lynxeyed_atsu 0:d920d64db582 27 #ifndef LPC17XX_I2S_H_
lynxeyed_atsu 0:d920d64db582 28 #define LPC17XX_I2S_H_
lynxeyed_atsu 0:d920d64db582 29
lynxeyed_atsu 0:d920d64db582 30 /* Includes ------------------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 31 #include "LPC17xx.h"
lynxeyed_atsu 0:d920d64db582 32 #include "lpc_types.h"
lynxeyed_atsu 0:d920d64db582 33
lynxeyed_atsu 0:d920d64db582 34
lynxeyed_atsu 0:d920d64db582 35 #ifdef __cplusplus
lynxeyed_atsu 0:d920d64db582 36 extern "C"
lynxeyed_atsu 0:d920d64db582 37 {
lynxeyed_atsu 0:d920d64db582 38 #endif
lynxeyed_atsu 0:d920d64db582 39
lynxeyed_atsu 0:d920d64db582 40 /* Public Macros -------------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 41 /** @defgroup I2S_Public_Macros I2S Public Macros
lynxeyed_atsu 0:d920d64db582 42 * @{
lynxeyed_atsu 0:d920d64db582 43 */
lynxeyed_atsu 0:d920d64db582 44
lynxeyed_atsu 0:d920d64db582 45 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 46 * I2S configuration parameter defines
lynxeyed_atsu 0:d920d64db582 47 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 48 /** I2S Wordwidth bit */
lynxeyed_atsu 0:d920d64db582 49 #define I2S_WORDWIDTH_8 ((uint32_t)(0))
lynxeyed_atsu 0:d920d64db582 50 #define I2S_WORDWIDTH_16 ((uint32_t)(1))
lynxeyed_atsu 0:d920d64db582 51 #define I2S_WORDWIDTH_32 ((uint32_t)(3))
lynxeyed_atsu 0:d920d64db582 52 /** I2S Channel bit */
lynxeyed_atsu 0:d920d64db582 53 #define I2S_STEREO ((uint32_t)(0))
lynxeyed_atsu 0:d920d64db582 54 #define I2S_MONO ((uint32_t)(1))
lynxeyed_atsu 0:d920d64db582 55 /** I2S Master/Slave mode bit */
lynxeyed_atsu 0:d920d64db582 56 #define I2S_MASTER_MODE ((uint8_t)(0))
lynxeyed_atsu 0:d920d64db582 57 #define I2S_SLAVE_MODE ((uint8_t)(1))
lynxeyed_atsu 0:d920d64db582 58 /** I2S Stop bit */
lynxeyed_atsu 0:d920d64db582 59 #define I2S_STOP_ENABLE ((uint8_t)(1))
lynxeyed_atsu 0:d920d64db582 60 #define I2S_STOP_DISABLE ((uint8_t)(0))
lynxeyed_atsu 0:d920d64db582 61 /** I2S Reset bit */
lynxeyed_atsu 0:d920d64db582 62 #define I2S_RESET_ENABLE ((uint8_t)(1))
lynxeyed_atsu 0:d920d64db582 63 #define I2S_RESET_DISABLE ((uint8_t)(0))
lynxeyed_atsu 0:d920d64db582 64 /** I2S Mute bit */
lynxeyed_atsu 0:d920d64db582 65 #define I2S_MUTE_ENABLE ((uint8_t)(1))
lynxeyed_atsu 0:d920d64db582 66 #define I2S_MUTE_DISABLE ((uint8_t)(0))
lynxeyed_atsu 0:d920d64db582 67 /** I2S Transmit/Receive bit */
lynxeyed_atsu 0:d920d64db582 68 #define I2S_TX_MODE ((uint8_t)(0))
lynxeyed_atsu 0:d920d64db582 69 #define I2S_RX_MODE ((uint8_t)(1))
lynxeyed_atsu 0:d920d64db582 70 /** I2S Clock Select bit */
lynxeyed_atsu 0:d920d64db582 71 #define I2S_CLKSEL_FRDCLK ((uint8_t)(0))
lynxeyed_atsu 0:d920d64db582 72 #define I2S_CLKSEL_MCLK ((uint8_t)(2))
lynxeyed_atsu 0:d920d64db582 73 /** I2S 4-pin Mode bit */
lynxeyed_atsu 0:d920d64db582 74 #define I2S_4PIN_ENABLE ((uint8_t)(1))
lynxeyed_atsu 0:d920d64db582 75 #define I2S_4PIN_DISABLE ((uint8_t)(0))
lynxeyed_atsu 0:d920d64db582 76 /** I2S MCLK Enable bit */
lynxeyed_atsu 0:d920d64db582 77 #define I2S_MCLK_ENABLE ((uint8_t)(1))
lynxeyed_atsu 0:d920d64db582 78 #define I2S_MCLK_DISABLE ((uint8_t)(0))
lynxeyed_atsu 0:d920d64db582 79 /** I2S select DMA bit */
lynxeyed_atsu 0:d920d64db582 80 #define I2S_DMA_1 ((uint8_t)(0))
lynxeyed_atsu 0:d920d64db582 81 #define I2S_DMA_2 ((uint8_t)(1))
lynxeyed_atsu 0:d920d64db582 82
lynxeyed_atsu 0:d920d64db582 83 /**
lynxeyed_atsu 0:d920d64db582 84 * @}
lynxeyed_atsu 0:d920d64db582 85 */
lynxeyed_atsu 0:d920d64db582 86
lynxeyed_atsu 0:d920d64db582 87 /* Private Macros ------------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 88 /** @defgroup I2S_Private_Macros I2S Private Macros
lynxeyed_atsu 0:d920d64db582 89 * @{
lynxeyed_atsu 0:d920d64db582 90 */
lynxeyed_atsu 0:d920d64db582 91
lynxeyed_atsu 0:d920d64db582 92 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 93 * Macro defines for DAO-Digital Audio Output register
lynxeyed_atsu 0:d920d64db582 94 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 95 /** I2S wordwide - the number of bytes in data*/
lynxeyed_atsu 0:d920d64db582 96 #define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
lynxeyed_atsu 0:d920d64db582 97 #define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
lynxeyed_atsu 0:d920d64db582 98 #define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
lynxeyed_atsu 0:d920d64db582 99 /** I2S control mono or stereo format */
lynxeyed_atsu 0:d920d64db582 100 #define I2S_DAO_MONO ((uint32_t)(1<<2))
lynxeyed_atsu 0:d920d64db582 101 /** I2S control stop mode */
lynxeyed_atsu 0:d920d64db582 102 #define I2S_DAO_STOP ((uint32_t)(1<<3))
lynxeyed_atsu 0:d920d64db582 103 /** I2S control reset mode */
lynxeyed_atsu 0:d920d64db582 104 #define I2S_DAO_RESET ((uint32_t)(1<<4))
lynxeyed_atsu 0:d920d64db582 105 /** I2S control master/slave mode */
lynxeyed_atsu 0:d920d64db582 106 #define I2S_DAO_SLAVE ((uint32_t)(1<<5))
lynxeyed_atsu 0:d920d64db582 107 /** I2S word select half period minus one */
lynxeyed_atsu 0:d920d64db582 108 #define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6))
lynxeyed_atsu 0:d920d64db582 109 /** I2S control mute mode */
lynxeyed_atsu 0:d920d64db582 110 #define I2S_DAO_MUTE ((uint32_t)(1<<15))
lynxeyed_atsu 0:d920d64db582 111
lynxeyed_atsu 0:d920d64db582 112 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 113 * Macro defines for DAI-Digital Audio Input register
lynxeyed_atsu 0:d920d64db582 114 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 115 /** I2S wordwide - the number of bytes in data*/
lynxeyed_atsu 0:d920d64db582 116 #define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
lynxeyed_atsu 0:d920d64db582 117 #define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
lynxeyed_atsu 0:d920d64db582 118 #define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
lynxeyed_atsu 0:d920d64db582 119 /** I2S control mono or stereo format */
lynxeyed_atsu 0:d920d64db582 120 #define I2S_DAI_MONO ((uint32_t)(1<<2))
lynxeyed_atsu 0:d920d64db582 121 /** I2S control stop mode */
lynxeyed_atsu 0:d920d64db582 122 #define I2S_DAI_STOP ((uint32_t)(1<<3))
lynxeyed_atsu 0:d920d64db582 123 /** I2S control reset mode */
lynxeyed_atsu 0:d920d64db582 124 #define I2S_DAI_RESET ((uint32_t)(1<<4))
lynxeyed_atsu 0:d920d64db582 125 /** I2S control master/slave mode */
lynxeyed_atsu 0:d920d64db582 126 #define I2S_DAI_SLAVE ((uint32_t)(1<<5))
lynxeyed_atsu 0:d920d64db582 127 /** I2S word select half period minus one (9 bits)*/
lynxeyed_atsu 0:d920d64db582 128 #define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6))
lynxeyed_atsu 0:d920d64db582 129 /** I2S control mute mode */
lynxeyed_atsu 0:d920d64db582 130 #define I2S_DAI_MUTE ((uint32_t)(1<<15))
lynxeyed_atsu 0:d920d64db582 131
lynxeyed_atsu 0:d920d64db582 132 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 133 * Macro defines for STAT register (Status Feedback register)
lynxeyed_atsu 0:d920d64db582 134 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 135 /** I2S Status Receive or Transmit Interrupt */
lynxeyed_atsu 0:d920d64db582 136 #define I2S_STATE_IRQ ((uint32_t)(1))
lynxeyed_atsu 0:d920d64db582 137 /** I2S Status Receive or Transmit DMA1 */
lynxeyed_atsu 0:d920d64db582 138 #define I2S_STATE_DMA1 ((uint32_t)(1<<1))
lynxeyed_atsu 0:d920d64db582 139 /** I2S Status Receive or Transmit DMA2 */
lynxeyed_atsu 0:d920d64db582 140 #define I2S_STATE_DMA2 ((uint32_t)(1<<2))
lynxeyed_atsu 0:d920d64db582 141 /** I2S Status Current level of the Receive FIFO (5 bits)*/
lynxeyed_atsu 0:d920d64db582 142 #define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8))
lynxeyed_atsu 0:d920d64db582 143 /** I2S Status Current level of the Transmit FIFO (5 bits)*/
lynxeyed_atsu 0:d920d64db582 144 #define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16))
lynxeyed_atsu 0:d920d64db582 145
lynxeyed_atsu 0:d920d64db582 146 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 147 * Macro defines for DMA1 register (DMA1 Configuration register)
lynxeyed_atsu 0:d920d64db582 148 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 149 /** I2S control DMA1 for I2S receive */
lynxeyed_atsu 0:d920d64db582 150 #define I2S_DMA1_RX_ENABLE ((uint32_t)(1))
lynxeyed_atsu 0:d920d64db582 151 /** I2S control DMA1 for I2S transmit */
lynxeyed_atsu 0:d920d64db582 152 #define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1))
lynxeyed_atsu 0:d920d64db582 153 /** I2S set FIFO level that trigger a receive DMA request on DMA1 */
lynxeyed_atsu 0:d920d64db582 154 #define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
lynxeyed_atsu 0:d920d64db582 155 /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
lynxeyed_atsu 0:d920d64db582 156 #define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
lynxeyed_atsu 0:d920d64db582 157
lynxeyed_atsu 0:d920d64db582 158 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 159 * Macro defines for DMA2 register (DMA2 Configuration register)
lynxeyed_atsu 0:d920d64db582 160 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 161 /** I2S control DMA2 for I2S receive */
lynxeyed_atsu 0:d920d64db582 162 #define I2S_DMA2_RX_ENABLE ((uint32_t)(1))
lynxeyed_atsu 0:d920d64db582 163 /** I2S control DMA1 for I2S transmit */
lynxeyed_atsu 0:d920d64db582 164 #define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1))
lynxeyed_atsu 0:d920d64db582 165 /** I2S set FIFO level that trigger a receive DMA request on DMA1 */
lynxeyed_atsu 0:d920d64db582 166 #define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
lynxeyed_atsu 0:d920d64db582 167 /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
lynxeyed_atsu 0:d920d64db582 168 #define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
lynxeyed_atsu 0:d920d64db582 169
lynxeyed_atsu 0:d920d64db582 170 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 171 * Macro defines for IRQ register (Interrupt Request Control register)
lynxeyed_atsu 0:d920d64db582 172 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 173 /** I2S control I2S receive interrupt */
lynxeyed_atsu 0:d920d64db582 174 #define I2S_IRQ_RX_ENABLE ((uint32_t)(1))
lynxeyed_atsu 0:d920d64db582 175 /** I2S control I2S transmit interrupt */
lynxeyed_atsu 0:d920d64db582 176 #define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1))
lynxeyed_atsu 0:d920d64db582 177 /** I2S set the FIFO level on which to create an irq request */
lynxeyed_atsu 0:d920d64db582 178 #define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
lynxeyed_atsu 0:d920d64db582 179 /** I2S set the FIFO level on which to create an irq request */
lynxeyed_atsu 0:d920d64db582 180 #define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
lynxeyed_atsu 0:d920d64db582 181
lynxeyed_atsu 0:d920d64db582 182 /********************************************************************************//**
lynxeyed_atsu 0:d920d64db582 183 * Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
lynxeyed_atsu 0:d920d64db582 184 *********************************************************************************/
lynxeyed_atsu 0:d920d64db582 185 /** I2S Transmit MCLK rate denominator */
lynxeyed_atsu 0:d920d64db582 186 #define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
lynxeyed_atsu 0:d920d64db582 187 /** I2S Transmit MCLK rate denominator */
lynxeyed_atsu 0:d920d64db582 188 #define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
lynxeyed_atsu 0:d920d64db582 189 /** I2S Receive MCLK rate denominator */
lynxeyed_atsu 0:d920d64db582 190 #define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
lynxeyed_atsu 0:d920d64db582 191 /** I2S Receive MCLK rate denominator */
lynxeyed_atsu 0:d920d64db582 192 #define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
lynxeyed_atsu 0:d920d64db582 193
lynxeyed_atsu 0:d920d64db582 194 /*************************************************************************************//**
lynxeyed_atsu 0:d920d64db582 195 * Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
lynxeyed_atsu 0:d920d64db582 196 **************************************************************************************/
lynxeyed_atsu 0:d920d64db582 197 #define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F))
lynxeyed_atsu 0:d920d64db582 198 #define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F))
lynxeyed_atsu 0:d920d64db582 199
lynxeyed_atsu 0:d920d64db582 200 /**********************************************************************************//**
lynxeyed_atsu 0:d920d64db582 201 * Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
lynxeyed_atsu 0:d920d64db582 202 ************************************************************************************/
lynxeyed_atsu 0:d920d64db582 203 /** I2S Transmit select clock source (2 bits)*/
lynxeyed_atsu 0:d920d64db582 204 #define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
lynxeyed_atsu 0:d920d64db582 205 /** I2S Transmit control 4-pin mode */
lynxeyed_atsu 0:d920d64db582 206 #define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
lynxeyed_atsu 0:d920d64db582 207 /** I2S Transmit control the TX_MCLK output */
lynxeyed_atsu 0:d920d64db582 208 #define I2S_TXMODE_MCENA ((uint32_t)(1<<3))
lynxeyed_atsu 0:d920d64db582 209 /** I2S Receive select clock source */
lynxeyed_atsu 0:d920d64db582 210 #define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
lynxeyed_atsu 0:d920d64db582 211 /** I2S Receive control 4-pin mode */
lynxeyed_atsu 0:d920d64db582 212 #define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
lynxeyed_atsu 0:d920d64db582 213 /** I2S Receive control the TX_MCLK output */
lynxeyed_atsu 0:d920d64db582 214 #define I2S_RXMODE_MCENA ((uint32_t)(1<<3))
lynxeyed_atsu 0:d920d64db582 215
lynxeyed_atsu 0:d920d64db582 216
lynxeyed_atsu 0:d920d64db582 217 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
lynxeyed_atsu 0:d920d64db582 218 /** Macro to determine if it is valid I2S peripheral */
lynxeyed_atsu 0:d920d64db582 219 #define PARAM_I2Sx(n) (((uint32_t *)n)==((uint32_t *)LPC_I2S))
lynxeyed_atsu 0:d920d64db582 220 /** Macro to check Data to send valid */
lynxeyed_atsu 0:d920d64db582 221 #define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000))
lynxeyed_atsu 0:d920d64db582 222 /* Macro check I2S word width type */
lynxeyed_atsu 0:d920d64db582 223 #define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\
lynxeyed_atsu 0:d920d64db582 224 ||(n==I2S_WORDWIDTH_32))
lynxeyed_atsu 0:d920d64db582 225 /* Macro check I2S channel type */
lynxeyed_atsu 0:d920d64db582 226 #define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO))
lynxeyed_atsu 0:d920d64db582 227 /* Macro check I2S master/slave mode */
lynxeyed_atsu 0:d920d64db582 228 #define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE))
lynxeyed_atsu 0:d920d64db582 229 /* Macro check I2S stop mode */
lynxeyed_atsu 0:d920d64db582 230 #define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE))
lynxeyed_atsu 0:d920d64db582 231 /* Macro check I2S reset mode */
lynxeyed_atsu 0:d920d64db582 232 #define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE))
lynxeyed_atsu 0:d920d64db582 233 /* Macro check I2S reset mode */
lynxeyed_atsu 0:d920d64db582 234 #define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE))
lynxeyed_atsu 0:d920d64db582 235 /* Macro check I2S transmit/receive mode */
lynxeyed_atsu 0:d920d64db582 236 #define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE))
lynxeyed_atsu 0:d920d64db582 237 /* Macro check I2S clock select mode */
lynxeyed_atsu 0:d920d64db582 238 #define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK))
lynxeyed_atsu 0:d920d64db582 239 /* Macro check I2S 4-pin mode */
lynxeyed_atsu 0:d920d64db582 240 #define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE))
lynxeyed_atsu 0:d920d64db582 241 /* Macro check I2S MCLK mode */
lynxeyed_atsu 0:d920d64db582 242 #define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE))
lynxeyed_atsu 0:d920d64db582 243 /* Macro check I2S DMA mode */
lynxeyed_atsu 0:d920d64db582 244 #define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2))
lynxeyed_atsu 0:d920d64db582 245 /* Macro check I2S DMA depth value */
lynxeyed_atsu 0:d920d64db582 246 #define PARAM_I2S_DMA_DEPTH(n) ((n>=0)||(n<=31))
lynxeyed_atsu 0:d920d64db582 247 /* Macro check I2S irq level value */
lynxeyed_atsu 0:d920d64db582 248 #define PARAM_I2S_IRQ_LEVEL(n) ((n>=0)||(n<=31))
lynxeyed_atsu 0:d920d64db582 249 /* Macro check I2S half-period value */
lynxeyed_atsu 0:d920d64db582 250 #define PARAM_I2S_HALFPERIOD(n) ((n>0)&&(n<512))
lynxeyed_atsu 0:d920d64db582 251 /* Macro check I2S bit-rate value */
lynxeyed_atsu 0:d920d64db582 252 #define PARAM_I2S_BITRATE(n) ((n>=0)&&(n<=63))
lynxeyed_atsu 0:d920d64db582 253 /**
lynxeyed_atsu 0:d920d64db582 254 * @}
lynxeyed_atsu 0:d920d64db582 255 */
lynxeyed_atsu 0:d920d64db582 256
lynxeyed_atsu 0:d920d64db582 257
lynxeyed_atsu 0:d920d64db582 258
lynxeyed_atsu 0:d920d64db582 259 /* Public Types --------------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 260 /** @defgroup I2S_Public_Types I2S Public Types
lynxeyed_atsu 0:d920d64db582 261 * @{
lynxeyed_atsu 0:d920d64db582 262 */
lynxeyed_atsu 0:d920d64db582 263
lynxeyed_atsu 0:d920d64db582 264 /**
lynxeyed_atsu 0:d920d64db582 265 * @brief I2S configuration structure definition
lynxeyed_atsu 0:d920d64db582 266 */
lynxeyed_atsu 0:d920d64db582 267 typedef struct {
lynxeyed_atsu 0:d920d64db582 268 uint8_t wordwidth; /** the number of bytes in data as follow:
lynxeyed_atsu 0:d920d64db582 269 -I2S_WORDWIDTH_8: 8 bit data
lynxeyed_atsu 0:d920d64db582 270 -I2S_WORDWIDTH_16: 16 bit data
lynxeyed_atsu 0:d920d64db582 271 -I2S_WORDWIDTH_32: 32 bit data */
lynxeyed_atsu 0:d920d64db582 272 uint8_t mono; /** Set mono/stereo mode, should be:
lynxeyed_atsu 0:d920d64db582 273 - I2S_STEREO: stereo mode
lynxeyed_atsu 0:d920d64db582 274 - I2S_MONO: mono mode */
lynxeyed_atsu 0:d920d64db582 275 uint8_t stop; /** Disables accesses on FIFOs, should be:
lynxeyed_atsu 0:d920d64db582 276 - I2S_STOP_ENABLE: enable stop mode
lynxeyed_atsu 0:d920d64db582 277 - I2S_STOP_DISABLE: disable stop mode */
lynxeyed_atsu 0:d920d64db582 278 uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be:
lynxeyed_atsu 0:d920d64db582 279 - I2S_RESET_ENABLE: enable reset mode
lynxeyed_atsu 0:d920d64db582 280 - I2S_RESET_DISABLE: disable reset mode */
lynxeyed_atsu 0:d920d64db582 281 uint8_t ws_sel; /** Set Master/Slave mode, should be:
lynxeyed_atsu 0:d920d64db582 282 - I2S_MASTER_MODE: I2S master mode
lynxeyed_atsu 0:d920d64db582 283 - I2S_SLAVE_MODE: I2S slave mode */
lynxeyed_atsu 0:d920d64db582 284 uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
lynxeyed_atsu 0:d920d64db582 285 - I2S_MUTE_ENABLE: enable mute mode
lynxeyed_atsu 0:d920d64db582 286 - I2S_MUTE_DISABLE: disable mute mode */
lynxeyed_atsu 0:d920d64db582 287 uint8_t Reserved0[2];
lynxeyed_atsu 0:d920d64db582 288 } I2S_CFG_Type;
lynxeyed_atsu 0:d920d64db582 289
lynxeyed_atsu 0:d920d64db582 290 /**
lynxeyed_atsu 0:d920d64db582 291 * @brief I2S DMA configuration structure definition
lynxeyed_atsu 0:d920d64db582 292 */
lynxeyed_atsu 0:d920d64db582 293 typedef struct {
lynxeyed_atsu 0:d920d64db582 294 uint8_t DMAIndex; /** Select DMA1 or DMA2, should be:
lynxeyed_atsu 0:d920d64db582 295 - I2S_DMA_1: DMA1
lynxeyed_atsu 0:d920d64db582 296 - I2S_DMA_2: DMA2 */
lynxeyed_atsu 0:d920d64db582 297 uint8_t depth; /** FIFO level that triggers a DMA request */
lynxeyed_atsu 0:d920d64db582 298 uint8_t Reserved0[2];
lynxeyed_atsu 0:d920d64db582 299 }I2S_DMAConf_Type;
lynxeyed_atsu 0:d920d64db582 300
lynxeyed_atsu 0:d920d64db582 301 /**
lynxeyed_atsu 0:d920d64db582 302 * @brief I2S mode configuration structure definition
lynxeyed_atsu 0:d920d64db582 303 */
lynxeyed_atsu 0:d920d64db582 304 typedef struct{
lynxeyed_atsu 0:d920d64db582 305 uint8_t clksel; /** Clock source selection, should be:
lynxeyed_atsu 0:d920d64db582 306 - I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output
lynxeyed_atsu 0:d920d64db582 307 - I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */
lynxeyed_atsu 0:d920d64db582 308 uint8_t fpin; /** Select four pin mode, should be:
lynxeyed_atsu 0:d920d64db582 309 - I2S_4PIN_ENABLE: 4-pin enable
lynxeyed_atsu 0:d920d64db582 310 - I2S_4PIN_DISABLE: 4-pin disable */
lynxeyed_atsu 0:d920d64db582 311 uint8_t mcena; /** Select MCLK mode, should be:
lynxeyed_atsu 0:d920d64db582 312 - I2S_MCLK_ENABLE: MCLK enable for output
lynxeyed_atsu 0:d920d64db582 313 - I2S_MCLK_DISABLE: MCLK disable for output */
lynxeyed_atsu 0:d920d64db582 314 uint8_t Reserved;
lynxeyed_atsu 0:d920d64db582 315 }I2S_MODEConf_Type;
lynxeyed_atsu 0:d920d64db582 316
lynxeyed_atsu 0:d920d64db582 317
lynxeyed_atsu 0:d920d64db582 318 /**
lynxeyed_atsu 0:d920d64db582 319 * @}
lynxeyed_atsu 0:d920d64db582 320 */
lynxeyed_atsu 0:d920d64db582 321
lynxeyed_atsu 0:d920d64db582 322
lynxeyed_atsu 0:d920d64db582 323 /* Public Functions ----------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 324 /** @defgroup I2S_Public_Functions I2S Public Functions
lynxeyed_atsu 0:d920d64db582 325 * @{
lynxeyed_atsu 0:d920d64db582 326 */
lynxeyed_atsu 0:d920d64db582 327 /* I2S Init/DeInit functions ---------*/
lynxeyed_atsu 0:d920d64db582 328 void I2S_Init(LPC_I2S_TypeDef *I2Sx);
lynxeyed_atsu 0:d920d64db582 329 void I2S_DeInit(LPC_I2S_TypeDef *I2Sx);
lynxeyed_atsu 0:d920d64db582 330
lynxeyed_atsu 0:d920d64db582 331 /* I2S configuration functions --------*/
lynxeyed_atsu 0:d920d64db582 332 void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);
lynxeyed_atsu 0:d920d64db582 333 Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode);
lynxeyed_atsu 0:d920d64db582 334 void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode);
lynxeyed_atsu 0:d920d64db582 335 void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);
lynxeyed_atsu 0:d920d64db582 336 uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
lynxeyed_atsu 0:d920d64db582 337
lynxeyed_atsu 0:d920d64db582 338 /* I2S operate functions -------------*/
lynxeyed_atsu 0:d920d64db582 339 void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData);
lynxeyed_atsu 0:d920d64db582 340 uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx);
lynxeyed_atsu 0:d920d64db582 341 void I2S_Start(LPC_I2S_TypeDef *I2Sx);
lynxeyed_atsu 0:d920d64db582 342 void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
lynxeyed_atsu 0:d920d64db582 343 void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
lynxeyed_atsu 0:d920d64db582 344 void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
lynxeyed_atsu 0:d920d64db582 345
lynxeyed_atsu 0:d920d64db582 346 /* I2S DMA functions ----------------*/
lynxeyed_atsu 0:d920d64db582 347 void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);
lynxeyed_atsu 0:d920d64db582 348 void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
lynxeyed_atsu 0:d920d64db582 349
lynxeyed_atsu 0:d920d64db582 350 /* I2S IRQ functions ----------------*/
lynxeyed_atsu 0:d920d64db582 351 void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState);
lynxeyed_atsu 0:d920d64db582 352 void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level);
lynxeyed_atsu 0:d920d64db582 353 FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
lynxeyed_atsu 0:d920d64db582 354 uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
lynxeyed_atsu 0:d920d64db582 355
lynxeyed_atsu 0:d920d64db582 356 /**
lynxeyed_atsu 0:d920d64db582 357 * @}
lynxeyed_atsu 0:d920d64db582 358 */
lynxeyed_atsu 0:d920d64db582 359
lynxeyed_atsu 0:d920d64db582 360
lynxeyed_atsu 0:d920d64db582 361 #ifdef __cplusplus
lynxeyed_atsu 0:d920d64db582 362 }
lynxeyed_atsu 0:d920d64db582 363 #endif
lynxeyed_atsu 0:d920d64db582 364
lynxeyed_atsu 0:d920d64db582 365
lynxeyed_atsu 0:d920d64db582 366 #endif /* LPC17XX_SSP_H_ */
lynxeyed_atsu 0:d920d64db582 367
lynxeyed_atsu 0:d920d64db582 368 /**
lynxeyed_atsu 0:d920d64db582 369 * @}
lynxeyed_atsu 0:d920d64db582 370 */
lynxeyed_atsu 0:d920d64db582 371
lynxeyed_atsu 0:d920d64db582 372 /* --------------------------------- End Of File ------------------------------ */