xeye_ atsu / Mbed 2 deprecated I2S_AIC23B_RiceGolomb

パラメータを適応変化させる事により圧縮率を向上させた動的ライス・ゴロム符号を利用した可逆圧縮方式。圧縮ソフト、圧縮率のMATLABシミュレーションは詳細はInterface誌2011年8月号に掲載されるRX62Nマイコン連動特集にて掲載予定。

Dependencies:   mbed

I2S_Example/system_LPC17xx.c@0:d920d64db582, 2011-03-30 (annotated)

Committer:
lynxeyed_atsu
Date:
Wed Mar 30 06:05:24 2011 +0000
Revision:
0:d920d64db582
alpha

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lynxeyed_atsu 0:d920d64db582 1 /**************************************************************************//**
lynxeyed_atsu 0:d920d64db582 2 * @file system_LPC17xx.c
lynxeyed_atsu 0:d920d64db582 3 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
lynxeyed_atsu 0:d920d64db582 4 * for the NXP LPC17xx Device Series
lynxeyed_atsu 0:d920d64db582 5 * @version V1.03
lynxeyed_atsu 0:d920d64db582 6 * @date 07. October 2009
lynxeyed_atsu 0:d920d64db582 7 *
lynxeyed_atsu 0:d920d64db582 8 * @note
lynxeyed_atsu 0:d920d64db582 9 * Copyright (C) 2009 ARM Limited. All rights reserved.
lynxeyed_atsu 0:d920d64db582 10 *
lynxeyed_atsu 0:d920d64db582 11 * @par
lynxeyed_atsu 0:d920d64db582 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
lynxeyed_atsu 0:d920d64db582 13 * processor based microcontrollers. This file can be freely distributed
lynxeyed_atsu 0:d920d64db582 14 * within development tools that are supporting such ARM based processors.
lynxeyed_atsu 0:d920d64db582 15 *
lynxeyed_atsu 0:d920d64db582 16 * @par
lynxeyed_atsu 0:d920d64db582 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
lynxeyed_atsu 0:d920d64db582 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
lynxeyed_atsu 0:d920d64db582 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
lynxeyed_atsu 0:d920d64db582 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
lynxeyed_atsu 0:d920d64db582 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
lynxeyed_atsu 0:d920d64db582 22 *
lynxeyed_atsu 0:d920d64db582 23 ******************************************************************************/
lynxeyed_atsu 0:d920d64db582 24
lynxeyed_atsu 0:d920d64db582 25
lynxeyed_atsu 0:d920d64db582 26 #include <stdint.h>
lynxeyed_atsu 0:d920d64db582 27 #include "LPC17xx.h"
lynxeyed_atsu 0:d920d64db582 28
lynxeyed_atsu 0:d920d64db582 29
lynxeyed_atsu 0:d920d64db582 30 /** @addtogroup LPC17xx_System
lynxeyed_atsu 0:d920d64db582 31 * @{
lynxeyed_atsu 0:d920d64db582 32 */
lynxeyed_atsu 0:d920d64db582 33
lynxeyed_atsu 0:d920d64db582 34 /*
lynxeyed_atsu 0:d920d64db582 35 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
lynxeyed_atsu 0:d920d64db582 36 */
lynxeyed_atsu 0:d920d64db582 37
lynxeyed_atsu 0:d920d64db582 38 /*--------------------- Clock Configuration ----------------------------------
lynxeyed_atsu 0:d920d64db582 39 //
lynxeyed_atsu 0:d920d64db582 40 // <e> Clock Configuration
lynxeyed_atsu 0:d920d64db582 41 // <h> System Controls and Status Register (SCS)
lynxeyed_atsu 0:d920d64db582 42 // <o1.4> OSCRANGE: Main Oscillator Range Select
lynxeyed_atsu 0:d920d64db582 43 // <0=> 1 MHz to 20 MHz
lynxeyed_atsu 0:d920d64db582 44 // <1=> 15 MHz to 24 MHz
lynxeyed_atsu 0:d920d64db582 45 // <e1.5> OSCEN: Main Oscillator Enable
lynxeyed_atsu 0:d920d64db582 46 // </e>
lynxeyed_atsu 0:d920d64db582 47 // </h>
lynxeyed_atsu 0:d920d64db582 48 //
lynxeyed_atsu 0:d920d64db582 49 // <h> Clock Source Select Register (CLKSRCSEL)
lynxeyed_atsu 0:d920d64db582 50 // <o2.0..1> CLKSRC: PLL Clock Source Selection
lynxeyed_atsu 0:d920d64db582 51 // <0=> Internal RC oscillator
lynxeyed_atsu 0:d920d64db582 52 // <1=> Main oscillator
lynxeyed_atsu 0:d920d64db582 53 // <2=> RTC oscillator
lynxeyed_atsu 0:d920d64db582 54 // </h>
lynxeyed_atsu 0:d920d64db582 55 //
lynxeyed_atsu 0:d920d64db582 56 // <e3> PLL0 Configuration (Main PLL)
lynxeyed_atsu 0:d920d64db582 57 // <h> PLL0 Configuration Register (PLL0CFG)
lynxeyed_atsu 0:d920d64db582 58 // <i> F_cco0 = (2 * M * F_in) / N
lynxeyed_atsu 0:d920d64db582 59 // <i> F_in must be in the range of 32 kHz to 50 MHz
lynxeyed_atsu 0:d920d64db582 60 // <i> F_cco0 must be in the range of 275 MHz to 550 MHz
lynxeyed_atsu 0:d920d64db582 61 // <o4.0..14> MSEL: PLL Multiplier Selection
lynxeyed_atsu 0:d920d64db582 62 // <6-32768><#-1>
lynxeyed_atsu 0:d920d64db582 63 // <i> M Value
lynxeyed_atsu 0:d920d64db582 64 // <o4.16..23> NSEL: PLL Divider Selection
lynxeyed_atsu 0:d920d64db582 65 // <1-256><#-1>
lynxeyed_atsu 0:d920d64db582 66 // <i> N Value
lynxeyed_atsu 0:d920d64db582 67 // </h>
lynxeyed_atsu 0:d920d64db582 68 // </e>
lynxeyed_atsu 0:d920d64db582 69 //
lynxeyed_atsu 0:d920d64db582 70 // <e5> PLL1 Configuration (USB PLL)
lynxeyed_atsu 0:d920d64db582 71 // <h> PLL1 Configuration Register (PLL1CFG)
lynxeyed_atsu 0:d920d64db582 72 // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
lynxeyed_atsu 0:d920d64db582 73 // <i> F_cco1 = F_osc * M * 2 * P
lynxeyed_atsu 0:d920d64db582 74 // <i> F_cco1 must be in the range of 156 MHz to 320 MHz
lynxeyed_atsu 0:d920d64db582 75 // <o6.0..4> MSEL: PLL Multiplier Selection
lynxeyed_atsu 0:d920d64db582 76 // <1-32><#-1>
lynxeyed_atsu 0:d920d64db582 77 // <i> M Value (for USB maximum value is 4)
lynxeyed_atsu 0:d920d64db582 78 // <o6.5..6> PSEL: PLL Divider Selection
lynxeyed_atsu 0:d920d64db582 79 // <0=> 1
lynxeyed_atsu 0:d920d64db582 80 // <1=> 2
lynxeyed_atsu 0:d920d64db582 81 // <2=> 4
lynxeyed_atsu 0:d920d64db582 82 // <3=> 8
lynxeyed_atsu 0:d920d64db582 83 // <i> P Value
lynxeyed_atsu 0:d920d64db582 84 // </h>
lynxeyed_atsu 0:d920d64db582 85 // </e>
lynxeyed_atsu 0:d920d64db582 86 //
lynxeyed_atsu 0:d920d64db582 87 // <h> CPU Clock Configuration Register (CCLKCFG)
lynxeyed_atsu 0:d920d64db582 88 // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
lynxeyed_atsu 0:d920d64db582 89 // <3-256><#-1>
lynxeyed_atsu 0:d920d64db582 90 // </h>
lynxeyed_atsu 0:d920d64db582 91 //
lynxeyed_atsu 0:d920d64db582 92 // <h> USB Clock Configuration Register (USBCLKCFG)
lynxeyed_atsu 0:d920d64db582 93 // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
lynxeyed_atsu 0:d920d64db582 94 // <0-15>
lynxeyed_atsu 0:d920d64db582 95 // <i> Divide is USBSEL + 1
lynxeyed_atsu 0:d920d64db582 96 // </h>
lynxeyed_atsu 0:d920d64db582 97 //
lynxeyed_atsu 0:d920d64db582 98 // <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
lynxeyed_atsu 0:d920d64db582 99 // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
lynxeyed_atsu 0:d920d64db582 100 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 101 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 102 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 103 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 104 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
lynxeyed_atsu 0:d920d64db582 105 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 106 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 107 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 108 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 109 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
lynxeyed_atsu 0:d920d64db582 110 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 111 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 112 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 113 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 114 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
lynxeyed_atsu 0:d920d64db582 115 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 116 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 117 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 118 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 119 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
lynxeyed_atsu 0:d920d64db582 120 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 121 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 122 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 123 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 124 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
lynxeyed_atsu 0:d920d64db582 125 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 126 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 127 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 128 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 129 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
lynxeyed_atsu 0:d920d64db582 130 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 131 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 132 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 133 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 134 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
lynxeyed_atsu 0:d920d64db582 135 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 136 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 137 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 138 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 139 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
lynxeyed_atsu 0:d920d64db582 140 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 141 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 142 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 143 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 144 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
lynxeyed_atsu 0:d920d64db582 145 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 146 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 147 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 148 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 149 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
lynxeyed_atsu 0:d920d64db582 150 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 151 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 152 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 153 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 154 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
lynxeyed_atsu 0:d920d64db582 155 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 156 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 157 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 158 // <3=> Pclk = Hclk / 6
lynxeyed_atsu 0:d920d64db582 159 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
lynxeyed_atsu 0:d920d64db582 160 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 161 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 162 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 163 // <3=> Pclk = Hclk / 6
lynxeyed_atsu 0:d920d64db582 164 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
lynxeyed_atsu 0:d920d64db582 165 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 166 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 167 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 168 // <3=> Pclk = Hclk / 6
lynxeyed_atsu 0:d920d64db582 169 // </h>
lynxeyed_atsu 0:d920d64db582 170 //
lynxeyed_atsu 0:d920d64db582 171 // <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
lynxeyed_atsu 0:d920d64db582 172 // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
lynxeyed_atsu 0:d920d64db582 173 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 174 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 175 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 176 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 177 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
lynxeyed_atsu 0:d920d64db582 178 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 179 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 180 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 181 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 182 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
lynxeyed_atsu 0:d920d64db582 183 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 184 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 185 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 186 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 187 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
lynxeyed_atsu 0:d920d64db582 188 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 189 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 190 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 191 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 192 // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
lynxeyed_atsu 0:d920d64db582 193 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 194 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 195 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 196 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 197 // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
lynxeyed_atsu 0:d920d64db582 198 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 199 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 200 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 201 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 202 // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
lynxeyed_atsu 0:d920d64db582 203 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 204 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 205 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 206 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 207 // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
lynxeyed_atsu 0:d920d64db582 208 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 209 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 210 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 211 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 212 // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
lynxeyed_atsu 0:d920d64db582 213 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 214 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 215 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 216 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 217 // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
lynxeyed_atsu 0:d920d64db582 218 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 219 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 220 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 221 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 222 // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
lynxeyed_atsu 0:d920d64db582 223 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 224 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 225 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 226 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 227 // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
lynxeyed_atsu 0:d920d64db582 228 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 229 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 230 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 231 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 232 // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
lynxeyed_atsu 0:d920d64db582 233 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 234 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 235 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 236 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 237 // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
lynxeyed_atsu 0:d920d64db582 238 // <0=> Pclk = Cclk / 4
lynxeyed_atsu 0:d920d64db582 239 // <1=> Pclk = Cclk
lynxeyed_atsu 0:d920d64db582 240 // <2=> Pclk = Cclk / 2
lynxeyed_atsu 0:d920d64db582 241 // <3=> Pclk = Hclk / 8
lynxeyed_atsu 0:d920d64db582 242 // </h>
lynxeyed_atsu 0:d920d64db582 243 //
lynxeyed_atsu 0:d920d64db582 244 // <h> Power Control for Peripherals Register (PCONP)
lynxeyed_atsu 0:d920d64db582 245 // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
lynxeyed_atsu 0:d920d64db582 246 // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
lynxeyed_atsu 0:d920d64db582 247 // <o11.3> PCUART0: UART 0 power/clock enable
lynxeyed_atsu 0:d920d64db582 248 // <o11.4> PCUART1: UART 1 power/clock enable
lynxeyed_atsu 0:d920d64db582 249 // <o11.6> PCPWM1: PWM 1 power/clock enable
lynxeyed_atsu 0:d920d64db582 250 // <o11.7> PCI2C0: I2C interface 0 power/clock enable
lynxeyed_atsu 0:d920d64db582 251 // <o11.8> PCSPI: SPI interface power/clock enable
lynxeyed_atsu 0:d920d64db582 252 // <o11.9> PCRTC: RTC power/clock enable
lynxeyed_atsu 0:d920d64db582 253 // <o11.10> PCSSP1: SSP interface 1 power/clock enable
lynxeyed_atsu 0:d920d64db582 254 // <o11.12> PCAD: A/D converter power/clock enable
lynxeyed_atsu 0:d920d64db582 255 // <o11.13> PCCAN1: CAN controller 1 power/clock enable
lynxeyed_atsu 0:d920d64db582 256 // <o11.14> PCCAN2: CAN controller 2 power/clock enable
lynxeyed_atsu 0:d920d64db582 257 // <o11.15> PCGPIO: GPIOs power/clock enable
lynxeyed_atsu 0:d920d64db582 258 // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
lynxeyed_atsu 0:d920d64db582 259 // <o11.17> PCMC: Motor control PWM power/clock enable
lynxeyed_atsu 0:d920d64db582 260 // <o11.18> PCQEI: Quadrature encoder interface power/clock enable
lynxeyed_atsu 0:d920d64db582 261 // <o11.19> PCI2C1: I2C interface 1 power/clock enable
lynxeyed_atsu 0:d920d64db582 262 // <o11.21> PCSSP0: SSP interface 0 power/clock enable
lynxeyed_atsu 0:d920d64db582 263 // <o11.22> PCTIM2: Timer 2 power/clock enable
lynxeyed_atsu 0:d920d64db582 264 // <o11.23> PCTIM3: Timer 3 power/clock enable
lynxeyed_atsu 0:d920d64db582 265 // <o11.24> PCUART2: UART 2 power/clock enable
lynxeyed_atsu 0:d920d64db582 266 // <o11.25> PCUART3: UART 3 power/clock enable
lynxeyed_atsu 0:d920d64db582 267 // <o11.26> PCI2C2: I2C interface 2 power/clock enable
lynxeyed_atsu 0:d920d64db582 268 // <o11.27> PCI2S: I2S interface power/clock enable
lynxeyed_atsu 0:d920d64db582 269 // <o11.29> PCGPDMA: GP DMA function power/clock enable
lynxeyed_atsu 0:d920d64db582 270 // <o11.30> PCENET: Ethernet block power/clock enable
lynxeyed_atsu 0:d920d64db582 271 // <o11.31> PCUSB: USB interface power/clock enable
lynxeyed_atsu 0:d920d64db582 272 // </h>
lynxeyed_atsu 0:d920d64db582 273 //
lynxeyed_atsu 0:d920d64db582 274 // <h> Clock Output Configuration Register (CLKOUTCFG)
lynxeyed_atsu 0:d920d64db582 275 // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
lynxeyed_atsu 0:d920d64db582 276 // <0=> CPU clock
lynxeyed_atsu 0:d920d64db582 277 // <1=> Main oscillator
lynxeyed_atsu 0:d920d64db582 278 // <2=> Internal RC oscillator
lynxeyed_atsu 0:d920d64db582 279 // <3=> USB clock
lynxeyed_atsu 0:d920d64db582 280 // <4=> RTC oscillator
lynxeyed_atsu 0:d920d64db582 281 // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
lynxeyed_atsu 0:d920d64db582 282 // <1-16><#-1>
lynxeyed_atsu 0:d920d64db582 283 // <o12.8> CLKOUT_EN: CLKOUT enable control
lynxeyed_atsu 0:d920d64db582 284 // </h>
lynxeyed_atsu 0:d920d64db582 285 //
lynxeyed_atsu 0:d920d64db582 286 // </e>
lynxeyed_atsu 0:d920d64db582 287 */
lynxeyed_atsu 0:d920d64db582 288
lynxeyed_atsu 0:d920d64db582 289
lynxeyed_atsu 0:d920d64db582 290
lynxeyed_atsu 0:d920d64db582 291 /** @addtogroup LPC17xx_System_Defines LPC17xx System Defines
lynxeyed_atsu 0:d920d64db582 292 @{
lynxeyed_atsu 0:d920d64db582 293 */
lynxeyed_atsu 0:d920d64db582 294
lynxeyed_atsu 0:d920d64db582 295 #define CLOCK_SETUP 1
lynxeyed_atsu 0:d920d64db582 296 #define SCS_Val 0x00000020
lynxeyed_atsu 0:d920d64db582 297 #define CLKSRCSEL_Val 0x00000001
lynxeyed_atsu 0:d920d64db582 298 #define PLL0_SETUP 1
lynxeyed_atsu 0:d920d64db582 299 #define PLL0CFG_Val 0x00050063
lynxeyed_atsu 0:d920d64db582 300 #define PLL1_SETUP 1
lynxeyed_atsu 0:d920d64db582 301 #define PLL1CFG_Val 0x00000023
lynxeyed_atsu 0:d920d64db582 302 #define CCLKCFG_Val 0x00000003
lynxeyed_atsu 0:d920d64db582 303 #define USBCLKCFG_Val 0x00000000
lynxeyed_atsu 0:d920d64db582 304 #define PCLKSEL0_Val 0x00000000
lynxeyed_atsu 0:d920d64db582 305 #define PCLKSEL1_Val 0x00000000
lynxeyed_atsu 0:d920d64db582 306 #define PCONP_Val 0x042887DE
lynxeyed_atsu 0:d920d64db582 307 #define CLKOUTCFG_Val 0x00000000
lynxeyed_atsu 0:d920d64db582 308
lynxeyed_atsu 0:d920d64db582 309
lynxeyed_atsu 0:d920d64db582 310 /*--------------------- Flash Accelerator Configuration ----------------------
lynxeyed_atsu 0:d920d64db582 311 //
lynxeyed_atsu 0:d920d64db582 312 // <e> Flash Accelerator Configuration
lynxeyed_atsu 0:d920d64db582 313 // <o1.0..11> Reserved
lynxeyed_atsu 0:d920d64db582 314 // <o1.12..15> FLASHTIM: Flash Access Time
lynxeyed_atsu 0:d920d64db582 315 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
lynxeyed_atsu 0:d920d64db582 316 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
lynxeyed_atsu 0:d920d64db582 317 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
lynxeyed_atsu 0:d920d64db582 318 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
lynxeyed_atsu 0:d920d64db582 319 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
lynxeyed_atsu 0:d920d64db582 320 // <5=> 6 CPU clocks (for any CPU clock)
lynxeyed_atsu 0:d920d64db582 321 // </e>
lynxeyed_atsu 0:d920d64db582 322 */
lynxeyed_atsu 0:d920d64db582 323 #define FLASH_SETUP 1
lynxeyed_atsu 0:d920d64db582 324 #define FLASHCFG_Val 0x0000303A
lynxeyed_atsu 0:d920d64db582 325
lynxeyed_atsu 0:d920d64db582 326 /*
lynxeyed_atsu 0:d920d64db582 327 //-------- <<< end of configuration section >>> ------------------------------
lynxeyed_atsu 0:d920d64db582 328 */
lynxeyed_atsu 0:d920d64db582 329
lynxeyed_atsu 0:d920d64db582 330 /*----------------------------------------------------------------------------
lynxeyed_atsu 0:d920d64db582 331 Check the register settings
lynxeyed_atsu 0:d920d64db582 332 *----------------------------------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 333 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
lynxeyed_atsu 0:d920d64db582 334 #define CHECK_RSVD(val, mask) (val & mask)
lynxeyed_atsu 0:d920d64db582 335
lynxeyed_atsu 0:d920d64db582 336 /* Clock Configuration -------------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 337 #if (CHECK_RSVD((SCS_Val), ~0x00000030))
lynxeyed_atsu 0:d920d64db582 338 #error "SCS: Invalid values of reserved bits!"
lynxeyed_atsu 0:d920d64db582 339 #endif
lynxeyed_atsu 0:d920d64db582 340
lynxeyed_atsu 0:d920d64db582 341 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
lynxeyed_atsu 0:d920d64db582 342 #error "CLKSRCSEL: Value out of range!"
lynxeyed_atsu 0:d920d64db582 343 #endif
lynxeyed_atsu 0:d920d64db582 344
lynxeyed_atsu 0:d920d64db582 345 #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
lynxeyed_atsu 0:d920d64db582 346 #error "PLL0CFG: Invalid values of reserved bits!"
lynxeyed_atsu 0:d920d64db582 347 #endif
lynxeyed_atsu 0:d920d64db582 348
lynxeyed_atsu 0:d920d64db582 349 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
lynxeyed_atsu 0:d920d64db582 350 #error "PLL1CFG: Invalid values of reserved bits!"
lynxeyed_atsu 0:d920d64db582 351 #endif
lynxeyed_atsu 0:d920d64db582 352
lynxeyed_atsu 0:d920d64db582 353 #if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
lynxeyed_atsu 0:d920d64db582 354 #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
lynxeyed_atsu 0:d920d64db582 355 #endif
lynxeyed_atsu 0:d920d64db582 356
lynxeyed_atsu 0:d920d64db582 357 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
lynxeyed_atsu 0:d920d64db582 358 #error "USBCLKCFG: Invalid values of reserved bits!"
lynxeyed_atsu 0:d920d64db582 359 #endif
lynxeyed_atsu 0:d920d64db582 360
lynxeyed_atsu 0:d920d64db582 361 #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
lynxeyed_atsu 0:d920d64db582 362 #error "PCLKSEL0: Invalid values of reserved bits!"
lynxeyed_atsu 0:d920d64db582 363 #endif
lynxeyed_atsu 0:d920d64db582 364
lynxeyed_atsu 0:d920d64db582 365 #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
lynxeyed_atsu 0:d920d64db582 366 #error "PCLKSEL1: Invalid values of reserved bits!"
lynxeyed_atsu 0:d920d64db582 367 #endif
lynxeyed_atsu 0:d920d64db582 368
lynxeyed_atsu 0:d920d64db582 369 #if (CHECK_RSVD((PCONP_Val), 0x10100821))
lynxeyed_atsu 0:d920d64db582 370 #error "PCONP: Invalid values of reserved bits!"
lynxeyed_atsu 0:d920d64db582 371 #endif
lynxeyed_atsu 0:d920d64db582 372
lynxeyed_atsu 0:d920d64db582 373 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
lynxeyed_atsu 0:d920d64db582 374 #error "CLKOUTCFG: Invalid values of reserved bits!"
lynxeyed_atsu 0:d920d64db582 375 #endif
lynxeyed_atsu 0:d920d64db582 376
lynxeyed_atsu 0:d920d64db582 377 /* Flash Accelerator Configuration -------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 378 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
lynxeyed_atsu 0:d920d64db582 379 #error "FLASHCFG: Invalid values of reserved bits!"
lynxeyed_atsu 0:d920d64db582 380 #endif
lynxeyed_atsu 0:d920d64db582 381
lynxeyed_atsu 0:d920d64db582 382
lynxeyed_atsu 0:d920d64db582 383 /*----------------------------------------------------------------------------
lynxeyed_atsu 0:d920d64db582 384 DEFINES
lynxeyed_atsu 0:d920d64db582 385 *----------------------------------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 386
lynxeyed_atsu 0:d920d64db582 387 /*----------------------------------------------------------------------------
lynxeyed_atsu 0:d920d64db582 388 Define clocks
lynxeyed_atsu 0:d920d64db582 389 *----------------------------------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 390 #define XTAL (12000000UL) /* Oscillator frequency */
lynxeyed_atsu 0:d920d64db582 391 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
lynxeyed_atsu 0:d920d64db582 392 #define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
lynxeyed_atsu 0:d920d64db582 393 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
lynxeyed_atsu 0:d920d64db582 394
lynxeyed_atsu 0:d920d64db582 395
lynxeyed_atsu 0:d920d64db582 396 /* F_cco0 = (2 * M * F_in) / N */
lynxeyed_atsu 0:d920d64db582 397 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
lynxeyed_atsu 0:d920d64db582 398 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
lynxeyed_atsu 0:d920d64db582 399 #define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
lynxeyed_atsu 0:d920d64db582 400 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
lynxeyed_atsu 0:d920d64db582 401
lynxeyed_atsu 0:d920d64db582 402 /* Determine core clock frequency according to settings */
lynxeyed_atsu 0:d920d64db582 403 #if (PLL0_SETUP)
lynxeyed_atsu 0:d920d64db582 404 #if ((CLKSRCSEL_Val & 0x03) == 1)
lynxeyed_atsu 0:d920d64db582 405 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
lynxeyed_atsu 0:d920d64db582 406 #elif ((CLKSRCSEL_Val & 0x03) == 2)
lynxeyed_atsu 0:d920d64db582 407 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
lynxeyed_atsu 0:d920d64db582 408 #else
lynxeyed_atsu 0:d920d64db582 409 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
lynxeyed_atsu 0:d920d64db582 410 #endif
lynxeyed_atsu 0:d920d64db582 411 #else
lynxeyed_atsu 0:d920d64db582 412 #if ((CLKSRCSEL_Val & 0x03) == 1)
lynxeyed_atsu 0:d920d64db582 413 #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
lynxeyed_atsu 0:d920d64db582 414 #elif ((CLKSRCSEL_Val & 0x03) == 2)
lynxeyed_atsu 0:d920d64db582 415 #define __CORE_CLK (RTC_CLK / __CCLK_DIV)
lynxeyed_atsu 0:d920d64db582 416 #else
lynxeyed_atsu 0:d920d64db582 417 #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
lynxeyed_atsu 0:d920d64db582 418 #endif
lynxeyed_atsu 0:d920d64db582 419 #endif
lynxeyed_atsu 0:d920d64db582 420
lynxeyed_atsu 0:d920d64db582 421 /**
lynxeyed_atsu 0:d920d64db582 422 * @}
lynxeyed_atsu 0:d920d64db582 423 */
lynxeyed_atsu 0:d920d64db582 424
lynxeyed_atsu 0:d920d64db582 425
lynxeyed_atsu 0:d920d64db582 426 /** @addtogroup LPC17xx_System_Public_Variables LPC17xx System Public Variables
lynxeyed_atsu 0:d920d64db582 427 @{
lynxeyed_atsu 0:d920d64db582 428 */
lynxeyed_atsu 0:d920d64db582 429 /*----------------------------------------------------------------------------
lynxeyed_atsu 0:d920d64db582 430 Clock Variable definitions
lynxeyed_atsu 0:d920d64db582 431 *----------------------------------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 432 //uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
lynxeyed_atsu 0:d920d64db582 433
lynxeyed_atsu 0:d920d64db582 434 /**
lynxeyed_atsu 0:d920d64db582 435 * @}
lynxeyed_atsu 0:d920d64db582 436 */
lynxeyed_atsu 0:d920d64db582 437
lynxeyed_atsu 0:d920d64db582 438
lynxeyed_atsu 0:d920d64db582 439 /** @addtogroup LPC17xx_System_Public_Functions LPC17xx System Public Functions
lynxeyed_atsu 0:d920d64db582 440 @{
lynxeyed_atsu 0:d920d64db582 441 */
lynxeyed_atsu 0:d920d64db582 442
lynxeyed_atsu 0:d920d64db582 443 /*----------------------------------------------------------------------------
lynxeyed_atsu 0:d920d64db582 444 Clock functions
lynxeyed_atsu 0:d920d64db582 445 *----------------------------------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 446
lynxeyed_atsu 0:d920d64db582 447
lynxeyed_atsu 0:d920d64db582 448
lynxeyed_atsu 0:d920d64db582 449
lynxeyed_atsu 0:d920d64db582 450 /**
lynxeyed_atsu 0:d920d64db582 451 * Initialize the system
lynxeyed_atsu 0:d920d64db582 452 *
lynxeyed_atsu 0:d920d64db582 453 * @param none
lynxeyed_atsu 0:d920d64db582 454 * @return none
lynxeyed_atsu 0:d920d64db582 455 *
lynxeyed_atsu 0:d920d64db582 456 * @brief Setup the microcontroller system.
lynxeyed_atsu 0:d920d64db582 457 * Initialize the System.
lynxeyed_atsu 0:d920d64db582 458 */
lynxeyed_atsu 0:d920d64db582 459 /*
lynxeyed_atsu 0:d920d64db582 460 void SystemInit (void)
lynxeyed_atsu 0:d920d64db582 461 {
lynxeyed_atsu 0:d920d64db582 462 #if (CLOCK_SETUP) // Clock Setup
lynxeyed_atsu 0:d920d64db582 463 LPC_SC->SCS = SCS_Val;
lynxeyed_atsu 0:d920d64db582 464 if (LPC_SC->SCS & (1 << 5)) { // If Main Oscillator is enabled
lynxeyed_atsu 0:d920d64db582 465 while ((LPC_SC->SCS & (1<<6)) == 0);// Wait for Oscillator to be ready
lynxeyed_atsu 0:d920d64db582 466 }
lynxeyed_atsu 0:d920d64db582 467
lynxeyed_atsu 0:d920d64db582 468 LPC_SC->CCLKCFG = CCLKCFG_Val; // Setup Clock Divider
lynxeyed_atsu 0:d920d64db582 469
lynxeyed_atsu 0:d920d64db582 470 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; // Peripheral Clock Selection
lynxeyed_atsu 0:d920d64db582 471 LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
lynxeyed_atsu 0:d920d64db582 472
lynxeyed_atsu 0:d920d64db582 473 #if (PLL0_SETUP)
lynxeyed_atsu 0:d920d64db582 474 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; // Select Clock Source for PLL0
lynxeyed_atsu 0:d920d64db582 475
lynxeyed_atsu 0:d920d64db582 476 LPC_SC->PLL0CFG = PLL0CFG_Val; // configure PLL0
lynxeyed_atsu 0:d920d64db582 477 LPC_SC->PLL0FEED = 0xAA;
lynxeyed_atsu 0:d920d64db582 478 LPC_SC->PLL0FEED = 0x55;
lynxeyed_atsu 0:d920d64db582 479
lynxeyed_atsu 0:d920d64db582 480 LPC_SC->PLL0CON = 0x01; // PLL0 Enable
lynxeyed_atsu 0:d920d64db582 481 LPC_SC->PLL0FEED = 0xAA;
lynxeyed_atsu 0:d920d64db582 482 LPC_SC->PLL0FEED = 0x55;
lynxeyed_atsu 0:d920d64db582 483 while (!(LPC_SC->PLL0STAT & (1<<26)));// Wait for PLOCK0
lynxeyed_atsu 0:d920d64db582 484
lynxeyed_atsu 0:d920d64db582 485 LPC_SC->PLL0CON = 0x03; // PLL0 Enable & Connect
lynxeyed_atsu 0:d920d64db582 486 LPC_SC->PLL0FEED = 0xAA;
lynxeyed_atsu 0:d920d64db582 487 LPC_SC->PLL0FEED = 0x55;
lynxeyed_atsu 0:d920d64db582 488 while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));//Wait for PLLC0_STAT & PLLE0_STAT
lynxeyed_atsu 0:d920d64db582 489 #endif
lynxeyed_atsu 0:d920d64db582 490
lynxeyed_atsu 0:d920d64db582 491 #if (PLL1_SETUP)
lynxeyed_atsu 0:d920d64db582 492 LPC_SC->PLL1CFG = PLL1CFG_Val;
lynxeyed_atsu 0:d920d64db582 493 LPC_SC->PLL1FEED = 0xAA;
lynxeyed_atsu 0:d920d64db582 494 LPC_SC->PLL1FEED = 0x55;
lynxeyed_atsu 0:d920d64db582 495
lynxeyed_atsu 0:d920d64db582 496 LPC_SC->PLL1CON = 0x01; // PLL1 Enable
lynxeyed_atsu 0:d920d64db582 497 LPC_SC->PLL1FEED = 0xAA;
lynxeyed_atsu 0:d920d64db582 498 LPC_SC->PLL1FEED = 0x55;
lynxeyed_atsu 0:d920d64db582 499 while (!(LPC_SC->PLL1STAT & (1<<10)));// Wait for PLOCK1
lynxeyed_atsu 0:d920d64db582 500
lynxeyed_atsu 0:d920d64db582 501 LPC_SC->PLL1CON = 0x03; // PLL1 Enable & Connect
lynxeyed_atsu 0:d920d64db582 502 LPC_SC->PLL1FEED = 0xAA;
lynxeyed_atsu 0:d920d64db582 503 LPC_SC->PLL1FEED = 0x55;
lynxeyed_atsu 0:d920d64db582 504 while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));// Wait for PLLC1_STAT & PLLE1_STAT
lynxeyed_atsu 0:d920d64db582 505 #else
lynxeyed_atsu 0:d920d64db582 506 LPC_SC->USBCLKCFG = USBCLKCFG_Val; // Setup USB Clock Divider
lynxeyed_atsu 0:d920d64db582 507 #endif
lynxeyed_atsu 0:d920d64db582 508 LPC_SC->PCONP = PCONP_Val; // Power Control for Peripherals
lynxeyed_atsu 0:d920d64db582 509
lynxeyed_atsu 0:d920d64db582 510 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; // Clock Output Configuration
lynxeyed_atsu 0:d920d64db582 511 #endif
lynxeyed_atsu 0:d920d64db582 512
lynxeyed_atsu 0:d920d64db582 513 #if (FLASH_SETUP == 1) // Flash Accelerator Setup
lynxeyed_atsu 0:d920d64db582 514 LPC_SC->FLASHCFG = FLASHCFG_Val;
lynxeyed_atsu 0:d920d64db582 515 #endif
lynxeyed_atsu 0:d920d64db582 516
lynxeyed_atsu 0:d920d64db582 517 // Set Vector table offset value
lynxeyed_atsu 0:d920d64db582 518 #if (__RAM_MODE__==1)
lynxeyed_atsu 0:d920d64db582 519 SCB->VTOR = 0x10000000 & 0x3FFFFF80;
lynxeyed_atsu 0:d920d64db582 520 #else
lynxeyed_atsu 0:d920d64db582 521 SCB->VTOR = 0x00000000 & 0x3FFFFF80;
lynxeyed_atsu 0:d920d64db582 522 #endif
lynxeyed_atsu 0:d920d64db582 523 }
lynxeyed_atsu 0:d920d64db582 524
lynxeyed_atsu 0:d920d64db582 525 */
lynxeyed_atsu 0:d920d64db582 526 /**
lynxeyed_atsu 0:d920d64db582 527 * @}
lynxeyed_atsu 0:d920d64db582 528 */
lynxeyed_atsu 0:d920d64db582 529
lynxeyed_atsu 0:d920d64db582 530 /**
lynxeyed_atsu 0:d920d64db582 531 * @}
lynxeyed_atsu 0:d920d64db582 532 */