xeye_ atsu / Mbed 2 deprecated I2S_AIC23B_RiceGolomb

パラメータを適応変化させる事により圧縮率を向上させた動的ライス・ゴロム符号を利用した可逆圧縮方式。圧縮ソフト、圧縮率のMATLABシミュレーションは詳細はInterface誌2011年8月号に掲載されるRX62Nマイコン連動特集にて掲載予定。

Dependencies:   mbed

I2S_Example/lpc17xx_clkpwr.c@0:d920d64db582, 2011-03-30 (annotated)

Committer:
lynxeyed_atsu
Date:
Wed Mar 30 06:05:24 2011 +0000
Revision:
0:d920d64db582
alpha

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lynxeyed_atsu 0:d920d64db582 1 /***********************************************************************//**
lynxeyed_atsu 0:d920d64db582 2 * @file lpc17xx_clkpwr.c
lynxeyed_atsu 0:d920d64db582 3 * @brief Contains all functions support for Clock and Power Control
lynxeyed_atsu 0:d920d64db582 4 * firmware library on LPC17xx
lynxeyed_atsu 0:d920d64db582 5 * @version 3.0
lynxeyed_atsu 0:d920d64db582 6 * @date 18. June. 2010
lynxeyed_atsu 0:d920d64db582 7 * @author NXP MCU SW Application Team
lynxeyed_atsu 0:d920d64db582 8 **************************************************************************
lynxeyed_atsu 0:d920d64db582 9 * Software that is described herein is for illustrative purposes only
lynxeyed_atsu 0:d920d64db582 10 * which provides customers with programming information regarding the
lynxeyed_atsu 0:d920d64db582 11 * products. This software is supplied "AS IS" without any warranties.
lynxeyed_atsu 0:d920d64db582 12 * NXP Semiconductors assumes no responsibility or liability for the
lynxeyed_atsu 0:d920d64db582 13 * use of the software, conveys no license or title under any patent,
lynxeyed_atsu 0:d920d64db582 14 * copyright, or mask work right to the product. NXP Semiconductors
lynxeyed_atsu 0:d920d64db582 15 * reserves the right to make changes in the software without
lynxeyed_atsu 0:d920d64db582 16 * notification. NXP Semiconductors also make no representation or
lynxeyed_atsu 0:d920d64db582 17 * warranty that such application will be suitable for the specified
lynxeyed_atsu 0:d920d64db582 18 * use without further testing or modification.
lynxeyed_atsu 0:d920d64db582 19 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 20
lynxeyed_atsu 0:d920d64db582 21 /* Peripheral group ----------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 22 /** @addtogroup CLKPWR
lynxeyed_atsu 0:d920d64db582 23 * @{
lynxeyed_atsu 0:d920d64db582 24 */
lynxeyed_atsu 0:d920d64db582 25
lynxeyed_atsu 0:d920d64db582 26 /* Includes ------------------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 27 #include "lpc17xx_clkpwr.h"
lynxeyed_atsu 0:d920d64db582 28
lynxeyed_atsu 0:d920d64db582 29
lynxeyed_atsu 0:d920d64db582 30 /* Public Functions ----------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 31 /** @addtogroup CLKPWR_Public_Functions
lynxeyed_atsu 0:d920d64db582 32 * @{
lynxeyed_atsu 0:d920d64db582 33 */
lynxeyed_atsu 0:d920d64db582 34
lynxeyed_atsu 0:d920d64db582 35 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 36 * @brief Set value of each Peripheral Clock Selection
lynxeyed_atsu 0:d920d64db582 37 * @param[in] ClkType Peripheral Clock Selection of each type,
lynxeyed_atsu 0:d920d64db582 38 * should be one of the following:
lynxeyed_atsu 0:d920d64db582 39 * - CLKPWR_PCLKSEL_WDT : WDT
lynxeyed_atsu 0:d920d64db582 40 - CLKPWR_PCLKSEL_TIMER0 : Timer 0
lynxeyed_atsu 0:d920d64db582 41 - CLKPWR_PCLKSEL_TIMER1 : Timer 1
lynxeyed_atsu 0:d920d64db582 42 - CLKPWR_PCLKSEL_UART0 : UART 0
lynxeyed_atsu 0:d920d64db582 43 - CLKPWR_PCLKSEL_UART1 : UART 1
lynxeyed_atsu 0:d920d64db582 44 - CLKPWR_PCLKSEL_PWM1 : PWM 1
lynxeyed_atsu 0:d920d64db582 45 - CLKPWR_PCLKSEL_I2C0 : I2C 0
lynxeyed_atsu 0:d920d64db582 46 - CLKPWR_PCLKSEL_SPI : SPI
lynxeyed_atsu 0:d920d64db582 47 - CLKPWR_PCLKSEL_SSP1 : SSP 1
lynxeyed_atsu 0:d920d64db582 48 - CLKPWR_PCLKSEL_DAC : DAC
lynxeyed_atsu 0:d920d64db582 49 - CLKPWR_PCLKSEL_ADC : ADC
lynxeyed_atsu 0:d920d64db582 50 - CLKPWR_PCLKSEL_CAN1 : CAN 1
lynxeyed_atsu 0:d920d64db582 51 - CLKPWR_PCLKSEL_CAN2 : CAN 2
lynxeyed_atsu 0:d920d64db582 52 - CLKPWR_PCLKSEL_ACF : ACF
lynxeyed_atsu 0:d920d64db582 53 - CLKPWR_PCLKSEL_QEI : QEI
lynxeyed_atsu 0:d920d64db582 54 - CLKPWR_PCLKSEL_PCB : PCB
lynxeyed_atsu 0:d920d64db582 55 - CLKPWR_PCLKSEL_I2C1 : I2C 1
lynxeyed_atsu 0:d920d64db582 56 - CLKPWR_PCLKSEL_SSP0 : SSP 0
lynxeyed_atsu 0:d920d64db582 57 - CLKPWR_PCLKSEL_TIMER2 : Timer 2
lynxeyed_atsu 0:d920d64db582 58 - CLKPWR_PCLKSEL_TIMER3 : Timer 3
lynxeyed_atsu 0:d920d64db582 59 - CLKPWR_PCLKSEL_UART2 : UART 2
lynxeyed_atsu 0:d920d64db582 60 - CLKPWR_PCLKSEL_UART3 : UART 3
lynxeyed_atsu 0:d920d64db582 61 - CLKPWR_PCLKSEL_I2C2 : I2C 2
lynxeyed_atsu 0:d920d64db582 62 - CLKPWR_PCLKSEL_I2S : I2S
lynxeyed_atsu 0:d920d64db582 63 - CLKPWR_PCLKSEL_RIT : RIT
lynxeyed_atsu 0:d920d64db582 64 - CLKPWR_PCLKSEL_SYSCON : SYSCON
lynxeyed_atsu 0:d920d64db582 65 - CLKPWR_PCLKSEL_MC : MC
lynxeyed_atsu 0:d920d64db582 66
lynxeyed_atsu 0:d920d64db582 67 * @param[in] DivVal Value of divider, should be:
lynxeyed_atsu 0:d920d64db582 68 * - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4
lynxeyed_atsu 0:d920d64db582 69 * - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1
lynxeyed_atsu 0:d920d64db582 70 * - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2
lynxeyed_atsu 0:d920d64db582 71 *
lynxeyed_atsu 0:d920d64db582 72 * @return none
lynxeyed_atsu 0:d920d64db582 73 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 74 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal)
lynxeyed_atsu 0:d920d64db582 75 {
lynxeyed_atsu 0:d920d64db582 76 uint32_t bitpos;
lynxeyed_atsu 0:d920d64db582 77
lynxeyed_atsu 0:d920d64db582 78 bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32);
lynxeyed_atsu 0:d920d64db582 79
lynxeyed_atsu 0:d920d64db582 80 /* PCLKSEL0 selected */
lynxeyed_atsu 0:d920d64db582 81 if (ClkType < 32)
lynxeyed_atsu 0:d920d64db582 82 {
lynxeyed_atsu 0:d920d64db582 83 /* Clear two bit at bit position */
lynxeyed_atsu 0:d920d64db582 84 LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos)));
lynxeyed_atsu 0:d920d64db582 85
lynxeyed_atsu 0:d920d64db582 86 /* Set two selected bit */
lynxeyed_atsu 0:d920d64db582 87 LPC_SC->PCLKSEL0 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
lynxeyed_atsu 0:d920d64db582 88 }
lynxeyed_atsu 0:d920d64db582 89 /* PCLKSEL1 selected */
lynxeyed_atsu 0:d920d64db582 90 else
lynxeyed_atsu 0:d920d64db582 91 {
lynxeyed_atsu 0:d920d64db582 92 /* Clear two bit at bit position */
lynxeyed_atsu 0:d920d64db582 93 LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos));
lynxeyed_atsu 0:d920d64db582 94
lynxeyed_atsu 0:d920d64db582 95 /* Set two selected bit */
lynxeyed_atsu 0:d920d64db582 96 LPC_SC->PCLKSEL1 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
lynxeyed_atsu 0:d920d64db582 97 }
lynxeyed_atsu 0:d920d64db582 98 }
lynxeyed_atsu 0:d920d64db582 99
lynxeyed_atsu 0:d920d64db582 100
lynxeyed_atsu 0:d920d64db582 101 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 102 * @brief Get current value of each Peripheral Clock Selection
lynxeyed_atsu 0:d920d64db582 103 * @param[in] ClkType Peripheral Clock Selection of each type,
lynxeyed_atsu 0:d920d64db582 104 * should be one of the following:
lynxeyed_atsu 0:d920d64db582 105 * - CLKPWR_PCLKSEL_WDT : WDT
lynxeyed_atsu 0:d920d64db582 106 - CLKPWR_PCLKSEL_TIMER0 : Timer 0
lynxeyed_atsu 0:d920d64db582 107 - CLKPWR_PCLKSEL_TIMER1 : Timer 1
lynxeyed_atsu 0:d920d64db582 108 - CLKPWR_PCLKSEL_UART0 : UART 0
lynxeyed_atsu 0:d920d64db582 109 - CLKPWR_PCLKSEL_UART1 : UART 1
lynxeyed_atsu 0:d920d64db582 110 - CLKPWR_PCLKSEL_PWM1 : PWM 1
lynxeyed_atsu 0:d920d64db582 111 - CLKPWR_PCLKSEL_I2C0 : I2C 0
lynxeyed_atsu 0:d920d64db582 112 - CLKPWR_PCLKSEL_SPI : SPI
lynxeyed_atsu 0:d920d64db582 113 - CLKPWR_PCLKSEL_SSP1 : SSP 1
lynxeyed_atsu 0:d920d64db582 114 - CLKPWR_PCLKSEL_DAC : DAC
lynxeyed_atsu 0:d920d64db582 115 - CLKPWR_PCLKSEL_ADC : ADC
lynxeyed_atsu 0:d920d64db582 116 - CLKPWR_PCLKSEL_CAN1 : CAN 1
lynxeyed_atsu 0:d920d64db582 117 - CLKPWR_PCLKSEL_CAN2 : CAN 2
lynxeyed_atsu 0:d920d64db582 118 - CLKPWR_PCLKSEL_ACF : ACF
lynxeyed_atsu 0:d920d64db582 119 - CLKPWR_PCLKSEL_QEI : QEI
lynxeyed_atsu 0:d920d64db582 120 - CLKPWR_PCLKSEL_PCB : PCB
lynxeyed_atsu 0:d920d64db582 121 - CLKPWR_PCLKSEL_I2C1 : I2C 1
lynxeyed_atsu 0:d920d64db582 122 - CLKPWR_PCLKSEL_SSP0 : SSP 0
lynxeyed_atsu 0:d920d64db582 123 - CLKPWR_PCLKSEL_TIMER2 : Timer 2
lynxeyed_atsu 0:d920d64db582 124 - CLKPWR_PCLKSEL_TIMER3 : Timer 3
lynxeyed_atsu 0:d920d64db582 125 - CLKPWR_PCLKSEL_UART2 : UART 2
lynxeyed_atsu 0:d920d64db582 126 - CLKPWR_PCLKSEL_UART3 : UART 3
lynxeyed_atsu 0:d920d64db582 127 - CLKPWR_PCLKSEL_I2C2 : I2C 2
lynxeyed_atsu 0:d920d64db582 128 - CLKPWR_PCLKSEL_I2S : I2S
lynxeyed_atsu 0:d920d64db582 129 - CLKPWR_PCLKSEL_RIT : RIT
lynxeyed_atsu 0:d920d64db582 130 - CLKPWR_PCLKSEL_SYSCON : SYSCON
lynxeyed_atsu 0:d920d64db582 131 - CLKPWR_PCLKSEL_MC : MC
lynxeyed_atsu 0:d920d64db582 132
lynxeyed_atsu 0:d920d64db582 133 * @return Value of Selected Peripheral Clock Selection
lynxeyed_atsu 0:d920d64db582 134 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 135 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType)
lynxeyed_atsu 0:d920d64db582 136 {
lynxeyed_atsu 0:d920d64db582 137 uint32_t bitpos, retval;
lynxeyed_atsu 0:d920d64db582 138
lynxeyed_atsu 0:d920d64db582 139 if (ClkType < 32)
lynxeyed_atsu 0:d920d64db582 140 {
lynxeyed_atsu 0:d920d64db582 141 bitpos = ClkType;
lynxeyed_atsu 0:d920d64db582 142 retval = LPC_SC->PCLKSEL0;
lynxeyed_atsu 0:d920d64db582 143 }
lynxeyed_atsu 0:d920d64db582 144 else
lynxeyed_atsu 0:d920d64db582 145 {
lynxeyed_atsu 0:d920d64db582 146 bitpos = ClkType - 32;
lynxeyed_atsu 0:d920d64db582 147 retval = LPC_SC->PCLKSEL1;
lynxeyed_atsu 0:d920d64db582 148 }
lynxeyed_atsu 0:d920d64db582 149
lynxeyed_atsu 0:d920d64db582 150 retval = CLKPWR_PCLKSEL_GET(bitpos, retval);
lynxeyed_atsu 0:d920d64db582 151 return retval;
lynxeyed_atsu 0:d920d64db582 152 }
lynxeyed_atsu 0:d920d64db582 153
lynxeyed_atsu 0:d920d64db582 154
lynxeyed_atsu 0:d920d64db582 155
lynxeyed_atsu 0:d920d64db582 156 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 157 * @brief Get current value of each Peripheral Clock
lynxeyed_atsu 0:d920d64db582 158 * @param[in] ClkType Peripheral Clock Selection of each type,
lynxeyed_atsu 0:d920d64db582 159 * should be one of the following:
lynxeyed_atsu 0:d920d64db582 160 * - CLKPWR_PCLKSEL_WDT : WDT
lynxeyed_atsu 0:d920d64db582 161 - CLKPWR_PCLKSEL_TIMER0 : Timer 0
lynxeyed_atsu 0:d920d64db582 162 - CLKPWR_PCLKSEL_TIMER1 : Timer 1
lynxeyed_atsu 0:d920d64db582 163 - CLKPWR_PCLKSEL_UART0 : UART 0
lynxeyed_atsu 0:d920d64db582 164 - CLKPWR_PCLKSEL_UART1 : UART 1
lynxeyed_atsu 0:d920d64db582 165 - CLKPWR_PCLKSEL_PWM1 : PWM 1
lynxeyed_atsu 0:d920d64db582 166 - CLKPWR_PCLKSEL_I2C0 : I2C 0
lynxeyed_atsu 0:d920d64db582 167 - CLKPWR_PCLKSEL_SPI : SPI
lynxeyed_atsu 0:d920d64db582 168 - CLKPWR_PCLKSEL_SSP1 : SSP 1
lynxeyed_atsu 0:d920d64db582 169 - CLKPWR_PCLKSEL_DAC : DAC
lynxeyed_atsu 0:d920d64db582 170 - CLKPWR_PCLKSEL_ADC : ADC
lynxeyed_atsu 0:d920d64db582 171 - CLKPWR_PCLKSEL_CAN1 : CAN 1
lynxeyed_atsu 0:d920d64db582 172 - CLKPWR_PCLKSEL_CAN2 : CAN 2
lynxeyed_atsu 0:d920d64db582 173 - CLKPWR_PCLKSEL_ACF : ACF
lynxeyed_atsu 0:d920d64db582 174 - CLKPWR_PCLKSEL_QEI : QEI
lynxeyed_atsu 0:d920d64db582 175 - CLKPWR_PCLKSEL_PCB : PCB
lynxeyed_atsu 0:d920d64db582 176 - CLKPWR_PCLKSEL_I2C1 : I2C 1
lynxeyed_atsu 0:d920d64db582 177 - CLKPWR_PCLKSEL_SSP0 : SSP 0
lynxeyed_atsu 0:d920d64db582 178 - CLKPWR_PCLKSEL_TIMER2 : Timer 2
lynxeyed_atsu 0:d920d64db582 179 - CLKPWR_PCLKSEL_TIMER3 : Timer 3
lynxeyed_atsu 0:d920d64db582 180 - CLKPWR_PCLKSEL_UART2 : UART 2
lynxeyed_atsu 0:d920d64db582 181 - CLKPWR_PCLKSEL_UART3 : UART 3
lynxeyed_atsu 0:d920d64db582 182 - CLKPWR_PCLKSEL_I2C2 : I2C 2
lynxeyed_atsu 0:d920d64db582 183 - CLKPWR_PCLKSEL_I2S : I2S
lynxeyed_atsu 0:d920d64db582 184 - CLKPWR_PCLKSEL_RIT : RIT
lynxeyed_atsu 0:d920d64db582 185 - CLKPWR_PCLKSEL_SYSCON : SYSCON
lynxeyed_atsu 0:d920d64db582 186 - CLKPWR_PCLKSEL_MC : MC
lynxeyed_atsu 0:d920d64db582 187
lynxeyed_atsu 0:d920d64db582 188 * @return Value of Selected Peripheral Clock
lynxeyed_atsu 0:d920d64db582 189 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 190 uint32_t CLKPWR_GetPCLK (uint32_t ClkType)
lynxeyed_atsu 0:d920d64db582 191 {
lynxeyed_atsu 0:d920d64db582 192 uint32_t retval, div;
lynxeyed_atsu 0:d920d64db582 193
lynxeyed_atsu 0:d920d64db582 194 retval = SystemCoreClock;
lynxeyed_atsu 0:d920d64db582 195 div = CLKPWR_GetPCLKSEL(ClkType);
lynxeyed_atsu 0:d920d64db582 196
lynxeyed_atsu 0:d920d64db582 197 switch (div)
lynxeyed_atsu 0:d920d64db582 198 {
lynxeyed_atsu 0:d920d64db582 199 case 0:
lynxeyed_atsu 0:d920d64db582 200 div = 4;
lynxeyed_atsu 0:d920d64db582 201 break;
lynxeyed_atsu 0:d920d64db582 202
lynxeyed_atsu 0:d920d64db582 203 case 1:
lynxeyed_atsu 0:d920d64db582 204 div = 1;
lynxeyed_atsu 0:d920d64db582 205 break;
lynxeyed_atsu 0:d920d64db582 206
lynxeyed_atsu 0:d920d64db582 207 case 2:
lynxeyed_atsu 0:d920d64db582 208 div = 2;
lynxeyed_atsu 0:d920d64db582 209 break;
lynxeyed_atsu 0:d920d64db582 210
lynxeyed_atsu 0:d920d64db582 211 case 3:
lynxeyed_atsu 0:d920d64db582 212 div = 8;
lynxeyed_atsu 0:d920d64db582 213 break;
lynxeyed_atsu 0:d920d64db582 214 }
lynxeyed_atsu 0:d920d64db582 215 retval /= div;
lynxeyed_atsu 0:d920d64db582 216
lynxeyed_atsu 0:d920d64db582 217 return retval;
lynxeyed_atsu 0:d920d64db582 218 }
lynxeyed_atsu 0:d920d64db582 219
lynxeyed_atsu 0:d920d64db582 220
lynxeyed_atsu 0:d920d64db582 221
lynxeyed_atsu 0:d920d64db582 222 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 223 * @brief Configure power supply for each peripheral according to NewState
lynxeyed_atsu 0:d920d64db582 224 * @param[in] PPType Type of peripheral used to enable power,
lynxeyed_atsu 0:d920d64db582 225 * should be one of the following:
lynxeyed_atsu 0:d920d64db582 226 * - CLKPWR_PCONP_PCTIM0 : Timer 0
lynxeyed_atsu 0:d920d64db582 227 - CLKPWR_PCONP_PCTIM1 : Timer 1
lynxeyed_atsu 0:d920d64db582 228 - CLKPWR_PCONP_PCUART0 : UART 0
lynxeyed_atsu 0:d920d64db582 229 - CLKPWR_PCONP_PCUART1 : UART 1
lynxeyed_atsu 0:d920d64db582 230 - CLKPWR_PCONP_PCPWM1 : PWM 1
lynxeyed_atsu 0:d920d64db582 231 - CLKPWR_PCONP_PCI2C0 : I2C 0
lynxeyed_atsu 0:d920d64db582 232 - CLKPWR_PCONP_PCSPI : SPI
lynxeyed_atsu 0:d920d64db582 233 - CLKPWR_PCONP_PCRTC : RTC
lynxeyed_atsu 0:d920d64db582 234 - CLKPWR_PCONP_PCSSP1 : SSP 1
lynxeyed_atsu 0:d920d64db582 235 - CLKPWR_PCONP_PCAD : ADC
lynxeyed_atsu 0:d920d64db582 236 - CLKPWR_PCONP_PCAN1 : CAN 1
lynxeyed_atsu 0:d920d64db582 237 - CLKPWR_PCONP_PCAN2 : CAN 2
lynxeyed_atsu 0:d920d64db582 238 - CLKPWR_PCONP_PCGPIO : GPIO
lynxeyed_atsu 0:d920d64db582 239 - CLKPWR_PCONP_PCRIT : RIT
lynxeyed_atsu 0:d920d64db582 240 - CLKPWR_PCONP_PCMC : MC
lynxeyed_atsu 0:d920d64db582 241 - CLKPWR_PCONP_PCQEI : QEI
lynxeyed_atsu 0:d920d64db582 242 - CLKPWR_PCONP_PCI2C1 : I2C 1
lynxeyed_atsu 0:d920d64db582 243 - CLKPWR_PCONP_PCSSP0 : SSP 0
lynxeyed_atsu 0:d920d64db582 244 - CLKPWR_PCONP_PCTIM2 : Timer 2
lynxeyed_atsu 0:d920d64db582 245 - CLKPWR_PCONP_PCTIM3 : Timer 3
lynxeyed_atsu 0:d920d64db582 246 - CLKPWR_PCONP_PCUART2 : UART 2
lynxeyed_atsu 0:d920d64db582 247 - CLKPWR_PCONP_PCUART3 : UART 3
lynxeyed_atsu 0:d920d64db582 248 - CLKPWR_PCONP_PCI2C2 : I2C 2
lynxeyed_atsu 0:d920d64db582 249 - CLKPWR_PCONP_PCI2S : I2S
lynxeyed_atsu 0:d920d64db582 250 - CLKPWR_PCONP_PCGPDMA : GPDMA
lynxeyed_atsu 0:d920d64db582 251 - CLKPWR_PCONP_PCENET : Ethernet
lynxeyed_atsu 0:d920d64db582 252 - CLKPWR_PCONP_PCUSB : USB
lynxeyed_atsu 0:d920d64db582 253 *
lynxeyed_atsu 0:d920d64db582 254 * @param[in] NewState New state of Peripheral Power, should be:
lynxeyed_atsu 0:d920d64db582 255 * - ENABLE : Enable power for this peripheral
lynxeyed_atsu 0:d920d64db582 256 * - DISABLE : Disable power for this peripheral
lynxeyed_atsu 0:d920d64db582 257 *
lynxeyed_atsu 0:d920d64db582 258 * @return none
lynxeyed_atsu 0:d920d64db582 259 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 260 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
lynxeyed_atsu 0:d920d64db582 261 {
lynxeyed_atsu 0:d920d64db582 262 if (NewState == ENABLE)
lynxeyed_atsu 0:d920d64db582 263 {
lynxeyed_atsu 0:d920d64db582 264 LPC_SC->PCONP |= PPType & CLKPWR_PCONP_BITMASK;
lynxeyed_atsu 0:d920d64db582 265 }
lynxeyed_atsu 0:d920d64db582 266 else if (NewState == DISABLE)
lynxeyed_atsu 0:d920d64db582 267 {
lynxeyed_atsu 0:d920d64db582 268 LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK;
lynxeyed_atsu 0:d920d64db582 269 }
lynxeyed_atsu 0:d920d64db582 270 }
lynxeyed_atsu 0:d920d64db582 271
lynxeyed_atsu 0:d920d64db582 272
lynxeyed_atsu 0:d920d64db582 273 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 274 * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
lynxeyed_atsu 0:d920d64db582 275 * @param[in] None
lynxeyed_atsu 0:d920d64db582 276 * @return None
lynxeyed_atsu 0:d920d64db582 277 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 278 void CLKPWR_Sleep(void)
lynxeyed_atsu 0:d920d64db582 279 {
lynxeyed_atsu 0:d920d64db582 280 LPC_SC->PCON = 0x00;
lynxeyed_atsu 0:d920d64db582 281 /* Sleep Mode*/
lynxeyed_atsu 0:d920d64db582 282 __WFI();
lynxeyed_atsu 0:d920d64db582 283 }
lynxeyed_atsu 0:d920d64db582 284
lynxeyed_atsu 0:d920d64db582 285
lynxeyed_atsu 0:d920d64db582 286 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 287 * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
lynxeyed_atsu 0:d920d64db582 288 * @param[in] None
lynxeyed_atsu 0:d920d64db582 289 * @return None
lynxeyed_atsu 0:d920d64db582 290 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 291 void CLKPWR_DeepSleep(void)
lynxeyed_atsu 0:d920d64db582 292 {
lynxeyed_atsu 0:d920d64db582 293 /* Deep-Sleep Mode, set SLEEPDEEP bit */
lynxeyed_atsu 0:d920d64db582 294 SCB->SCR = 0x4;
lynxeyed_atsu 0:d920d64db582 295 LPC_SC->PCON = 0x8;
lynxeyed_atsu 0:d920d64db582 296 /* Deep Sleep Mode*/
lynxeyed_atsu 0:d920d64db582 297 __WFI();
lynxeyed_atsu 0:d920d64db582 298 }
lynxeyed_atsu 0:d920d64db582 299
lynxeyed_atsu 0:d920d64db582 300
lynxeyed_atsu 0:d920d64db582 301 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 302 * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
lynxeyed_atsu 0:d920d64db582 303 * @param[in] None
lynxeyed_atsu 0:d920d64db582 304 * @return None
lynxeyed_atsu 0:d920d64db582 305 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 306 void CLKPWR_PowerDown(void)
lynxeyed_atsu 0:d920d64db582 307 {
lynxeyed_atsu 0:d920d64db582 308 /* Deep-Sleep Mode, set SLEEPDEEP bit */
lynxeyed_atsu 0:d920d64db582 309 SCB->SCR = 0x4;
lynxeyed_atsu 0:d920d64db582 310 LPC_SC->PCON = 0x09;
lynxeyed_atsu 0:d920d64db582 311 /* Power Down Mode*/
lynxeyed_atsu 0:d920d64db582 312 __WFI();
lynxeyed_atsu 0:d920d64db582 313 }
lynxeyed_atsu 0:d920d64db582 314
lynxeyed_atsu 0:d920d64db582 315
lynxeyed_atsu 0:d920d64db582 316 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 317 * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
lynxeyed_atsu 0:d920d64db582 318 * @param[in] None
lynxeyed_atsu 0:d920d64db582 319 * @return None
lynxeyed_atsu 0:d920d64db582 320 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 321 void CLKPWR_DeepPowerDown(void)
lynxeyed_atsu 0:d920d64db582 322 {
lynxeyed_atsu 0:d920d64db582 323 /* Deep-Sleep Mode, set SLEEPDEEP bit */
lynxeyed_atsu 0:d920d64db582 324 SCB->SCR = 0x4;
lynxeyed_atsu 0:d920d64db582 325 LPC_SC->PCON = 0x03;
lynxeyed_atsu 0:d920d64db582 326 /* Deep Power Down Mode*/
lynxeyed_atsu 0:d920d64db582 327 __WFI();
lynxeyed_atsu 0:d920d64db582 328 }
lynxeyed_atsu 0:d920d64db582 329
lynxeyed_atsu 0:d920d64db582 330 /**
lynxeyed_atsu 0:d920d64db582 331 * @}
lynxeyed_atsu 0:d920d64db582 332 */
lynxeyed_atsu 0:d920d64db582 333
lynxeyed_atsu 0:d920d64db582 334 /**
lynxeyed_atsu 0:d920d64db582 335 * @}
lynxeyed_atsu 0:d920d64db582 336 */
lynxeyed_atsu 0:d920d64db582 337
lynxeyed_atsu 0:d920d64db582 338 /* --------------------------------- End Of File ------------------------------ */