xeye_ atsu / Mbed 2 deprecated I2S_AIC23B_RiceGolomb

パラメータを適応変化させる事により圧縮率を向上させた動的ライス・ゴロム符号を利用した可逆圧縮方式。圧縮ソフト、圧縮率のMATLABシミュレーションは詳細はInterface誌2011年8月号に掲載されるRX62Nマイコン連動特集にて掲載予定。

Dependencies:   mbed

aic23b_comm.h@0:d920d64db582, 2011-03-30 (annotated)

Committer:
lynxeyed_atsu
Date:
Wed Mar 30 06:05:24 2011 +0000
Revision:
0:d920d64db582
alpha

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lynxeyed_atsu 0:d920d64db582 1 #include "mbed.h"
lynxeyed_atsu 0:d920d64db582 2
lynxeyed_atsu 0:d920d64db582 3 //extern void aic23b_init(void);
lynxeyed_atsu 0:d920d64db582 4 //extern int aic23b_send(int addr,char ctrl_address,char ctrl_data);
lynxeyed_atsu 0:d920d64db582 5
lynxeyed_atsu 0:d920d64db582 6 // Register map of TLV320AIC23B. See "TLV320AIC23B Data Manual" section 3.1.3
lynxeyed_atsu 0:d920d64db582 7 // I2C ADDRESS(MODE=0,CS=0)=0011010b
lynxeyed_atsu 0:d920d64db582 8 #define AIC23B_ADDRESS (52)
lynxeyed_atsu 0:d920d64db582 9 ///////////////////////////////////////////////////////////////////////
lynxeyed_atsu 0:d920d64db582 10 // Control Address Bits
lynxeyed_atsu 0:d920d64db582 11 #define LEFT_LINE_INPUT_CHANNEL_VOLUME_CONTROL (0x00 << 1)
lynxeyed_atsu 0:d920d64db582 12 #define RIGHT_LINE_INPUT_CHANNEL_VOLUME_CONTROL (0x01 << 1)
lynxeyed_atsu 0:d920d64db582 13 #define LEFT_CHANNEL_HEADPHONE_VOLUME_CONTROL ((0x02 << 1)|1)
lynxeyed_atsu 0:d920d64db582 14 #define RIGHT_CHANNEL_HEADPHONE_VOLUME_CONTROL ((0x03 << 1)|1)
lynxeyed_atsu 0:d920d64db582 15 #define ANALOG_AUDIO_PATH_CONTROL (0x04 << 1)
lynxeyed_atsu 0:d920d64db582 16 #define DIGITAL_AUDIO_PATH_CONTROL (0x05 << 1)
lynxeyed_atsu 0:d920d64db582 17 #define POWER_DOWN_CONTROL (0x06 << 1)
lynxeyed_atsu 0:d920d64db582 18 #define DIGITAL_AUDIO_INTERFACE_FORMAT (0x07 << 1)
lynxeyed_atsu 0:d920d64db582 19 #define SAMPLE_RATE_CONTROL (0x08 << 1)
lynxeyed_atsu 0:d920d64db582 20 #define DIGITAL_INTERFACE_ACTIVATION (0x09 << 1)
lynxeyed_atsu 0:d920d64db582 21 #define RESET_REFGISTER (0x0F << 1)
lynxeyed_atsu 0:d920d64db582 22 ///////////////////////////////////////////////////////////////////////
lynxeyed_atsu 0:d920d64db582 23 // Control Data Bits
lynxeyed_atsu 0:d920d64db582 24 // LEFT_LINE_INPUT_CHANNEL_VOLUME_CONTROL(Address:0x00)
lynxeyed_atsu 0:d920d64db582 25 // (bit7)LIM: Left line input mute 0=Normal 1=Muted
lynxeyed_atsu 0:d920d64db582 26 // (bit6)X: Reserved
lynxeyed_atsu 0:d920d64db582 27 // (bit5)X: Reserved
lynxeyed_atsu 0:d920d64db582 28 // (bit4)LIV4:
lynxeyed_atsu 0:d920d64db582 29 // (bit3)LIV3:
lynxeyed_atsu 0:d920d64db582 30 // (bit2)LIV2:
lynxeyed_atsu 0:d920d64db582 31 // (bit1)LIV1:
lynxeyed_atsu 0:d920d64db582 32 // (bit0)LIV0: Left line input volume control(10111=0dB default)
lynxeyed_atsu 0:d920d64db582 33 #define LIM_MUTE_DISABLED (0<<7)
lynxeyed_atsu 0:d920d64db582 34 #define LIV_VOLUME_DEFAULT (0x17<<0)
lynxeyed_atsu 0:d920d64db582 35 // ----------------------------------------------------------------------
lynxeyed_atsu 0:d920d64db582 36 // RIGHT_LINE_INPUT_CHANNEL_VOLUME_CONTROL(Address:0x01)
lynxeyed_atsu 0:d920d64db582 37 // (bit7)RIM: Right line input mute 0=Normal 1=Muted
lynxeyed_atsu 0:d920d64db582 38 // (bit6)X: Reserved
lynxeyed_atsu 0:d920d64db582 39 // (bit5)X: Reserved
lynxeyed_atsu 0:d920d64db582 40 // (bit4)RIV4:
lynxeyed_atsu 0:d920d64db582 41 // (bit3)RIV3:
lynxeyed_atsu 0:d920d64db582 42 // (bit2)RIV2:
lynxeyed_atsu 0:d920d64db582 43 // (bit1)RIV1:
lynxeyed_atsu 0:d920d64db582 44 // (bit0)RIV0: Right line input volume control(10111=0dB default)
lynxeyed_atsu 0:d920d64db582 45 #define RIM_MUTE_DISABLED (0<<7)
lynxeyed_atsu 0:d920d64db582 46 #define RIV_VOLUME_DEFAULT (0x17<<0)
lynxeyed_atsu 0:d920d64db582 47 // ----------------------------------------------------------------------
lynxeyed_atsu 0:d920d64db582 48 // LEFT_CHANNEL_HEADPHONE_VOLUME_CONTROL(Address:0x02)
lynxeyed_atsu 0:d920d64db582 49 // (bit7)LZC: Left-channel Zero-cross detect 0=Off 1=On
lynxeyed_atsu 0:d920d64db582 50 // (bit6)LHV6:
lynxeyed_atsu 0:d920d64db582 51 // (bit5)LHV5:
lynxeyed_atsu 0:d920d64db582 52 // (bit4)LHV4:
lynxeyed_atsu 0:d920d64db582 53 // (bit3)LHV3:
lynxeyed_atsu 0:d920d64db582 54 // (bit2)LHV2:
lynxeyed_atsu 0:d920d64db582 55 // (bit1)LHV1:
lynxeyed_atsu 0:d920d64db582 56 // (bit0)LHV0: Left headphone volume control(1111001=0dB default,0110000=-73dB Mute)
lynxeyed_atsu 0:d920d64db582 57 #define LZC_ZERO_CROSS_DETECT_ON (1<<7)
lynxeyed_atsu 0:d920d64db582 58 #define LHV_VOLUME_DEFAULT 90//(0x79<<0)
lynxeyed_atsu 0:d920d64db582 59 // ----------------------------------------------------------------------
lynxeyed_atsu 0:d920d64db582 60 // RIGHT_CHANNEL_HEADPHONE_VOLUME_CONTROL(Address:0x03)
lynxeyed_atsu 0:d920d64db582 61 // (bit7)RZC: Right-channel Zero-cross detect 0=Off 1=On
lynxeyed_atsu 0:d920d64db582 62 // (bit6)RHV6:
lynxeyed_atsu 0:d920d64db582 63 // (bit5)RHV5:
lynxeyed_atsu 0:d920d64db582 64 // (bit4)RHV4:
lynxeyed_atsu 0:d920d64db582 65 // (bit3)RHV3:
lynxeyed_atsu 0:d920d64db582 66 // (bit2)RHV2:
lynxeyed_atsu 0:d920d64db582 67 // (bit1)RHV1:
lynxeyed_atsu 0:d920d64db582 68 // (bit0)RHV0: Right headphone volume control(1111001=0dB default,0110000=-73dB Mute)
lynxeyed_atsu 0:d920d64db582 69 #define RZC_ZERO_CROSS_DETECT_ON (1<<7)
lynxeyed_atsu 0:d920d64db582 70 #define RHV_VOLUME_DEFAULT 90//(0x79<<0)
lynxeyed_atsu 0:d920d64db582 71 // ----------------------------------------------------------------------
lynxeyed_atsu 0:d920d64db582 72 // ANALOG_AUDIO_PATH_CONTROL(Address:0x04)
lynxeyed_atsu 0:d920d64db582 73 // (bit7)STA1:
lynxeyed_atsu 0:d920d64db582 74 // (bit6)STA0:
lynxeyed_atsu 0:d920d64db582 75 // (bit5)STE: (See "TLV320AIC23B DATA MANUAL" pp.3-3)
lynxeyed_atsu 0:d920d64db582 76 // (bit4)DAC: DAC select 0=DAC off 1=DAC on
lynxeyed_atsu 0:d920d64db582 77 // (bit3)BYP: Bypass 0=Disabled 1=Enabled
lynxeyed_atsu 0:d920d64db582 78 // (bit2)INSEL: Input select for ADC 0=Line, 1=Microphone
lynxeyed_atsu 0:d920d64db582 79 // (bit1)MICM: Microphone mute 0=Normal, 1=Muted
lynxeyed_atsu 0:d920d64db582 80 // (bit0)MICB: Microphone boost 0=dB, 1=20dB
lynxeyed_atsu 0:d920d64db582 81 // ----------------------------------------------------------------------
lynxeyed_atsu 0:d920d64db582 82 // DIGITAL_AUDIO_PATH_CONTROL(Address:0x05)
lynxeyed_atsu 0:d920d64db582 83 // (bit7)X: Reserved
lynxeyed_atsu 0:d920d64db582 84 // (bit6)X: Reserved
lynxeyed_atsu 0:d920d64db582 85 // (bit5)X: Reserved
lynxeyed_atsu 0:d920d64db582 86 // (bit4)X: Reserved
lynxeyed_atsu 0:d920d64db582 87 // (bit3)DACM: DAC soft mute 0=Disabled 1=Enabled
lynxeyed_atsu 0:d920d64db582 88 // (bit2)DEEMP1:
lynxeyed_atsu 0:d920d64db582 89 // (bit1)DEEMP0: De-enphasis control 0=Normal, 1=Muted
lynxeyed_atsu 0:d920d64db582 90 // (bit0)ADCHP: ADC high-pass filter 0=dB, 1=20dB
lynxeyed_atsu 0:d920d64db582 91 #define DAC_MUTE_DISABLED (0<<3)
lynxeyed_atsu 0:d920d64db582 92 #define DE_EMPHASIS_DISABLED (0x0 << 0)
lynxeyed_atsu 0:d920d64db582 93 #define DE_EMPHASIS_32_KHZ (0x1 << 0)
lynxeyed_atsu 0:d920d64db582 94 #define DE_EMPHASIS_44_1_KHZ (0x2 << 0)
lynxeyed_atsu 0:d920d64db582 95 #define DE_EMPHASIS_48_KHZ (0x3 << 0)
lynxeyed_atsu 0:d920d64db582 96 // ----------------------------------------------------------------------
lynxeyed_atsu 0:d920d64db582 97 // POWER_DOWN_CONTROL(Address:0x06)
lynxeyed_atsu 0:d920d64db582 98 // (bit7)OFF: Device power 0=On, 1=Off
lynxeyed_atsu 0:d920d64db582 99 // (bit6)CLK: Clock 0=On, 1=Off
lynxeyed_atsu 0:d920d64db582 100 // (bit5)OSC: Oscillator 0=On, 1=Off
lynxeyed_atsu 0:d920d64db582 101 // (bit4)OUT: Outputs 0=On, 1=Off
lynxeyed_atsu 0:d920d64db582 102 // (bit3)DAC: DAC 0=On, 1=Off
lynxeyed_atsu 0:d920d64db582 103 // (bit2)ADC: ADC 0=On, 1=Off
lynxeyed_atsu 0:d920d64db582 104 // (bit1)MIC: Microphone input 0=On, 1=Off
lynxeyed_atsu 0:d920d64db582 105 // (bit0)LINE: Line input 0=On, 1=Off
lynxeyed_atsu 0:d920d64db582 106 #define DEVICE_POWER_ON (0<<7)
lynxeyed_atsu 0:d920d64db582 107 #define CLOCK_ON (0<<6)
lynxeyed_atsu 0:d920d64db582 108 #define OSCILLATOR_ON (0<<5)
lynxeyed_atsu 0:d920d64db582 109 #define OUTPUTS_ON (0<<4)
lynxeyed_atsu 0:d920d64db582 110 #define DAC_ON (0<<3)
lynxeyed_atsu 0:d920d64db582 111 #define ADC_ON (0<<2)
lynxeyed_atsu 0:d920d64db582 112 #define MICROPHONE_INPUT_ON (0<<1)
lynxeyed_atsu 0:d920d64db582 113 #define LINE_INPUT_ON (0<<0)
lynxeyed_atsu 0:d920d64db582 114 // ----------------------------------------------------------------------
lynxeyed_atsu 0:d920d64db582 115 // DIGITAL_AUDUIO_INTERFACE_FORMAT(Address:0x07)
lynxeyed_atsu 0:d920d64db582 116 // (bit7)X: Reserved
lynxeyed_atsu 0:d920d64db582 117 // (bit6)MS: Master/Slave mode 0=Slave, 1=Master
lynxeyed_atsu 0:d920d64db582 118 // (bit5)LRSWAP: DAC left/right swap 0=Disabled, 1=Enabled
lynxeyed_atsu 0:d920d64db582 119 // (bit4)LRP: 0=R-ch ON,LRCLKIN high, 1=R-ch ON,LRCLKIN low
lynxeyed_atsu 0:d920d64db582 120 // (bit3)IWL1:
lynxeyed_atsu 0:d920d64db582 121 // (bit2)IWL0: Input bit length 00=16bit, 01=20bit, 10=24bit, 11=32bit
lynxeyed_atsu 0:d920d64db582 122 // (bit1)FOR1:
lynxeyed_atsu 0:d920d64db582 123 // (bit0)FOR0: Data format 11=DSP, 10=I2S, 01=MSB first left algn., 00=MSB right algn.
lynxeyed_atsu 0:d920d64db582 124 #define MASTER_MODE (1<<6)
lynxeyed_atsu 0:d920d64db582 125 #define INPUT_DATA_16_BIT_LENGTH (0x00<<2)
lynxeyed_atsu 0:d920d64db582 126 #define INPUT_DATA_20_BIT_LENGTH (0x01<<2)
lynxeyed_atsu 0:d920d64db582 127 #define INPUT_DATA_24_BIT_LENGTH (0x02<<2)
lynxeyed_atsu 0:d920d64db582 128 #define INPUT_DATA_32_BIT_LENGTH (0x03<<2)
lynxeyed_atsu 0:d920d64db582 129 #define DSP_FORMAT (0x03<<0)
lynxeyed_atsu 0:d920d64db582 130 #define I2S_FORMAT (0x02<<0)
lynxeyed_atsu 0:d920d64db582 131 #define MSB_FIRST_LEFT_ALIGN (0x01<<0)
lynxeyed_atsu 0:d920d64db582 132 #define MSB_FIRST_RIGHT_ALIGN (0x00<<0)
lynxeyed_atsu 0:d920d64db582 133 // ----------------------------------------------------------------------
lynxeyed_atsu 0:d920d64db582 134 // SAMPLE_RATE_CONTROL(Address:0x08)
lynxeyed_atsu 0:d920d64db582 135 // (bit7)CLKOUT: Clock output divider 0=MCLK, 1=MCLK/2
lynxeyed_atsu 0:d920d64db582 136 // (bit6)CLKIN: Clock input divider 0=MCLK, 1=MCLK/2
lynxeyed_atsu 0:d920d64db582 137 // (bit5)SR3:
lynxeyed_atsu 0:d920d64db582 138 // (bit4)SR2:
lynxeyed_atsu 0:d920d64db582 139 // (bit3)SR1:
lynxeyed_atsu 0:d920d64db582 140 // (bit2)SR0: (See "TLV320AIC23B DATA MANUAL" section 3.3.2.1 and 3.3.2.2)
lynxeyed_atsu 0:d920d64db582 141 // (bit1)BOSR:
lynxeyed_atsu 0:d920d64db582 142 // (bit0)USB/Normal: Clock mode select 0=Normal, 1=USB
lynxeyed_atsu 0:d920d64db582 143 #define SR_USB_44_1_KHZ_MODE (0x08<<2)
lynxeyed_atsu 0:d920d64db582 144 #define BOSR_USB_44_1_KHZ_MODE (0x01<<1)
lynxeyed_atsu 0:d920d64db582 145 #define USE_USB_CLOCK_44_1_KHZ_MODE (0x01<<0)
lynxeyed_atsu 0:d920d64db582 146 // ----------------------------------------------------------------------
lynxeyed_atsu 0:d920d64db582 147 // DIGITAL_INTERFACE_ACTIVATION(Address:0x09)
lynxeyed_atsu 0:d920d64db582 148 // (bit7)RES:
lynxeyed_atsu 0:d920d64db582 149 // (bit6)RES:
lynxeyed_atsu 0:d920d64db582 150 // (bit5)X: Reserved
lynxeyed_atsu 0:d920d64db582 151 // (bit4)X: Reserved
lynxeyed_atsu 0:d920d64db582 152 // (bit3)X: Reserved
lynxeyed_atsu 0:d920d64db582 153 // (bit2)X: Reserved
lynxeyed_atsu 0:d920d64db582 154 // (bit1)X: Reserved
lynxeyed_atsu 0:d920d64db582 155 // (bit0)ACT: Activate interface 0=Inactive, 1=Active
lynxeyed_atsu 0:d920d64db582 156 #define DIGITAL_INTERFACE_ACTIVE (0x01<<0)
lynxeyed_atsu 0:d920d64db582 157 // ----------------------------------------------------------------------
lynxeyed_atsu 0:d920d64db582 158 // RESET_REGISTER(Address:0x0F)
lynxeyed_atsu 0:d920d64db582 159 // (bit7)RES:
lynxeyed_atsu 0:d920d64db582 160 // (bit6)RES:
lynxeyed_atsu 0:d920d64db582 161 // (bit5)RES:
lynxeyed_atsu 0:d920d64db582 162 // (bit4)RES:
lynxeyed_atsu 0:d920d64db582 163 // (bit3)RES:
lynxeyed_atsu 0:d920d64db582 164 // (bit2)RES:
lynxeyed_atsu 0:d920d64db582 165 // (bit1)RES:
lynxeyed_atsu 0:d920d64db582 166 // (bit0)RES: Write 00000000 to this register triggers reset
lynxeyed_atsu 0:d920d64db582 167 #define RESET (0x00<<0)