xeye_ atsu / Mbed 2 deprecated I2S_AIC23B_RiceGolomb

パラメータを適応変化させる事により圧縮率を向上させた動的ライス・ゴロム符号を利用した可逆圧縮方式。圧縮ソフト、圧縮率のMATLABシミュレーションは詳細はInterface誌2011年8月号に掲載されるRX62Nマイコン連動特集にて掲載予定。

Dependencies:   mbed

I2S_Example/lpc17xx_uart.c@0:d920d64db582, 2011-03-30 (annotated)

Committer:
lynxeyed_atsu
Date:
Wed Mar 30 06:05:24 2011 +0000
Revision:
0:d920d64db582
alpha

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lynxeyed_atsu 0:d920d64db582 1 /***********************************************************************//**
lynxeyed_atsu 0:d920d64db582 2 * @file lpc17xx_uart.c
lynxeyed_atsu 0:d920d64db582 3 * @brief Contains all functions support for UART firmware library on LPC17xx
lynxeyed_atsu 0:d920d64db582 4 * @version 3.0
lynxeyed_atsu 0:d920d64db582 5 * @date 18. June. 2010
lynxeyed_atsu 0:d920d64db582 6 * @author NXP MCU SW Application Team
lynxeyed_atsu 0:d920d64db582 7 **************************************************************************
lynxeyed_atsu 0:d920d64db582 8 * Software that is described herein is for illustrative purposes only
lynxeyed_atsu 0:d920d64db582 9 * which provides customers with programming information regarding the
lynxeyed_atsu 0:d920d64db582 10 * products. This software is supplied "AS IS" without any warranties.
lynxeyed_atsu 0:d920d64db582 11 * NXP Semiconductors assumes no responsibility or liability for the
lynxeyed_atsu 0:d920d64db582 12 * use of the software, conveys no license or title under any patent,
lynxeyed_atsu 0:d920d64db582 13 * copyright, or mask work right to the product. NXP Semiconductors
lynxeyed_atsu 0:d920d64db582 14 * reserves the right to make changes in the software without
lynxeyed_atsu 0:d920d64db582 15 * notification. NXP Semiconductors also make no representation or
lynxeyed_atsu 0:d920d64db582 16 * warranty that such application will be suitable for the specified
lynxeyed_atsu 0:d920d64db582 17 * use without further testing or modification.
lynxeyed_atsu 0:d920d64db582 18 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 19
lynxeyed_atsu 0:d920d64db582 20 /* Peripheral group ----------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 21 /** @addtogroup UART
lynxeyed_atsu 0:d920d64db582 22 * @{
lynxeyed_atsu 0:d920d64db582 23 */
lynxeyed_atsu 0:d920d64db582 24
lynxeyed_atsu 0:d920d64db582 25 /* Includes ------------------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 26 #include "lpc17xx_uart.h"
lynxeyed_atsu 0:d920d64db582 27 #include "lpc17xx_clkpwr.h"
lynxeyed_atsu 0:d920d64db582 28
lynxeyed_atsu 0:d920d64db582 29 /* If this source file built with example, the LPC17xx FW library configuration
lynxeyed_atsu 0:d920d64db582 30 * file in each example directory ("lpc17xx_libcfg.h") must be included,
lynxeyed_atsu 0:d920d64db582 31 * otherwise the default FW library configuration file must be included instead
lynxeyed_atsu 0:d920d64db582 32 */
lynxeyed_atsu 0:d920d64db582 33 #ifdef __BUILD_WITH_EXAMPLE__
lynxeyed_atsu 0:d920d64db582 34 #include "lpc17xx_libcfg.h"
lynxeyed_atsu 0:d920d64db582 35 #else
lynxeyed_atsu 0:d920d64db582 36 #include "lpc17xx_libcfg_default.h"
lynxeyed_atsu 0:d920d64db582 37 #endif /* __BUILD_WITH_EXAMPLE__ */
lynxeyed_atsu 0:d920d64db582 38
lynxeyed_atsu 0:d920d64db582 39
lynxeyed_atsu 0:d920d64db582 40 #ifdef _UART
lynxeyed_atsu 0:d920d64db582 41
lynxeyed_atsu 0:d920d64db582 42 /* Private Functions ---------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 43
lynxeyed_atsu 0:d920d64db582 44 static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate);
lynxeyed_atsu 0:d920d64db582 45
lynxeyed_atsu 0:d920d64db582 46
lynxeyed_atsu 0:d920d64db582 47 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 48 * @brief Determines best dividers to get a target clock rate
lynxeyed_atsu 0:d920d64db582 49 * @param[in] UARTx Pointer to selected UART peripheral, should be:
lynxeyed_atsu 0:d920d64db582 50 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 51 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 52 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 53 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 54 * @param[in] baudrate Desired UART baud rate.
lynxeyed_atsu 0:d920d64db582 55 * @return Error status, could be:
lynxeyed_atsu 0:d920d64db582 56 * - SUCCESS
lynxeyed_atsu 0:d920d64db582 57 * - ERROR
lynxeyed_atsu 0:d920d64db582 58 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 59 static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate)
lynxeyed_atsu 0:d920d64db582 60 {
lynxeyed_atsu 0:d920d64db582 61 Status errorStatus = ERROR;
lynxeyed_atsu 0:d920d64db582 62
lynxeyed_atsu 0:d920d64db582 63 uint32_t uClk = 0;
lynxeyed_atsu 0:d920d64db582 64 uint32_t calcBaudrate = 0;
lynxeyed_atsu 0:d920d64db582 65 uint32_t temp = 0;
lynxeyed_atsu 0:d920d64db582 66
lynxeyed_atsu 0:d920d64db582 67 uint32_t mulFracDiv, dividerAddFracDiv;
lynxeyed_atsu 0:d920d64db582 68 uint32_t diviser = 0 ;
lynxeyed_atsu 0:d920d64db582 69 uint32_t mulFracDivOptimal = 1;
lynxeyed_atsu 0:d920d64db582 70 uint32_t dividerAddOptimal = 0;
lynxeyed_atsu 0:d920d64db582 71 uint32_t diviserOptimal = 0;
lynxeyed_atsu 0:d920d64db582 72
lynxeyed_atsu 0:d920d64db582 73 uint32_t relativeError = 0;
lynxeyed_atsu 0:d920d64db582 74 uint32_t relativeOptimalError = 100000;
lynxeyed_atsu 0:d920d64db582 75
lynxeyed_atsu 0:d920d64db582 76 /* get UART block clock */
lynxeyed_atsu 0:d920d64db582 77 if (UARTx == (LPC_UART_TypeDef *)LPC_UART0)
lynxeyed_atsu 0:d920d64db582 78 {
lynxeyed_atsu 0:d920d64db582 79 uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART0);
lynxeyed_atsu 0:d920d64db582 80 }
lynxeyed_atsu 0:d920d64db582 81 else if (UARTx == (LPC_UART_TypeDef *)LPC_UART1)
lynxeyed_atsu 0:d920d64db582 82 {
lynxeyed_atsu 0:d920d64db582 83 uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART1);
lynxeyed_atsu 0:d920d64db582 84 }
lynxeyed_atsu 0:d920d64db582 85 else if (UARTx == LPC_UART2)
lynxeyed_atsu 0:d920d64db582 86 {
lynxeyed_atsu 0:d920d64db582 87 uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART2);
lynxeyed_atsu 0:d920d64db582 88 }
lynxeyed_atsu 0:d920d64db582 89 else if (UARTx == LPC_UART3)
lynxeyed_atsu 0:d920d64db582 90 {
lynxeyed_atsu 0:d920d64db582 91 uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART3);
lynxeyed_atsu 0:d920d64db582 92 }
lynxeyed_atsu 0:d920d64db582 93
lynxeyed_atsu 0:d920d64db582 94
lynxeyed_atsu 0:d920d64db582 95 uClk = uClk >> 4; /* div by 16 */
lynxeyed_atsu 0:d920d64db582 96 /* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
lynxeyed_atsu 0:d920d64db582 97 * The formula is :
lynxeyed_atsu 0:d920d64db582 98 * BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
lynxeyed_atsu 0:d920d64db582 99 * It involves floating point calculations. That's the reason the formulae are adjusted with
lynxeyed_atsu 0:d920d64db582 100 * Multiply and divide method.*/
lynxeyed_atsu 0:d920d64db582 101 /* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
lynxeyed_atsu 0:d920d64db582 102 * 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
lynxeyed_atsu 0:d920d64db582 103 for (mulFracDiv = 1 ; mulFracDiv <= 15 ;mulFracDiv++)
lynxeyed_atsu 0:d920d64db582 104 {
lynxeyed_atsu 0:d920d64db582 105 for (dividerAddFracDiv = 0 ; dividerAddFracDiv <= 15 ;dividerAddFracDiv++)
lynxeyed_atsu 0:d920d64db582 106 {
lynxeyed_atsu 0:d920d64db582 107 temp = (mulFracDiv * uClk) / ((mulFracDiv + dividerAddFracDiv));
lynxeyed_atsu 0:d920d64db582 108
lynxeyed_atsu 0:d920d64db582 109 diviser = temp / baudrate;
lynxeyed_atsu 0:d920d64db582 110 if ((temp % baudrate) > (baudrate / 2))
lynxeyed_atsu 0:d920d64db582 111 diviser++;
lynxeyed_atsu 0:d920d64db582 112
lynxeyed_atsu 0:d920d64db582 113 if (diviser > 2 && diviser < 65536)
lynxeyed_atsu 0:d920d64db582 114 {
lynxeyed_atsu 0:d920d64db582 115 calcBaudrate = temp / diviser;
lynxeyed_atsu 0:d920d64db582 116
lynxeyed_atsu 0:d920d64db582 117 if (calcBaudrate <= baudrate)
lynxeyed_atsu 0:d920d64db582 118 relativeError = baudrate - calcBaudrate;
lynxeyed_atsu 0:d920d64db582 119 else
lynxeyed_atsu 0:d920d64db582 120 relativeError = calcBaudrate - baudrate;
lynxeyed_atsu 0:d920d64db582 121
lynxeyed_atsu 0:d920d64db582 122 if ((relativeError < relativeOptimalError))
lynxeyed_atsu 0:d920d64db582 123 {
lynxeyed_atsu 0:d920d64db582 124 mulFracDivOptimal = mulFracDiv ;
lynxeyed_atsu 0:d920d64db582 125 dividerAddOptimal = dividerAddFracDiv;
lynxeyed_atsu 0:d920d64db582 126 diviserOptimal = diviser;
lynxeyed_atsu 0:d920d64db582 127 relativeOptimalError = relativeError;
lynxeyed_atsu 0:d920d64db582 128 if (relativeError == 0)
lynxeyed_atsu 0:d920d64db582 129 break;
lynxeyed_atsu 0:d920d64db582 130 }
lynxeyed_atsu 0:d920d64db582 131 } /* End of if */
lynxeyed_atsu 0:d920d64db582 132 } /* end of inner for loop */
lynxeyed_atsu 0:d920d64db582 133 if (relativeError == 0)
lynxeyed_atsu 0:d920d64db582 134 break;
lynxeyed_atsu 0:d920d64db582 135 } /* end of outer for loop */
lynxeyed_atsu 0:d920d64db582 136
lynxeyed_atsu 0:d920d64db582 137 if (relativeOptimalError < ((baudrate * UART_ACCEPTED_BAUDRATE_ERROR)/100))
lynxeyed_atsu 0:d920d64db582 138 {
lynxeyed_atsu 0:d920d64db582 139 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 140 {
lynxeyed_atsu 0:d920d64db582 141 ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN;
lynxeyed_atsu 0:d920d64db582 142 ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/DLM = UART_LOAD_DLM(diviserOptimal);
lynxeyed_atsu 0:d920d64db582 143 ((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/DLL = UART_LOAD_DLL(diviserOptimal);
lynxeyed_atsu 0:d920d64db582 144 /* Then reset DLAB bit */
lynxeyed_atsu 0:d920d64db582 145 ((LPC_UART1_TypeDef *)UARTx)->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
lynxeyed_atsu 0:d920d64db582 146 ((LPC_UART1_TypeDef *)UARTx)->FDR = (UART_FDR_MULVAL(mulFracDivOptimal) \
lynxeyed_atsu 0:d920d64db582 147 | UART_FDR_DIVADDVAL(dividerAddOptimal)) & UART_FDR_BITMASK;
lynxeyed_atsu 0:d920d64db582 148 }
lynxeyed_atsu 0:d920d64db582 149 else
lynxeyed_atsu 0:d920d64db582 150 {
lynxeyed_atsu 0:d920d64db582 151 UARTx->LCR |= UART_LCR_DLAB_EN;
lynxeyed_atsu 0:d920d64db582 152 UARTx->/*DLIER.*/DLM = UART_LOAD_DLM(diviserOptimal);
lynxeyed_atsu 0:d920d64db582 153 UARTx->/*RBTHDLR.*/DLL = UART_LOAD_DLL(diviserOptimal);
lynxeyed_atsu 0:d920d64db582 154 /* Then reset DLAB bit */
lynxeyed_atsu 0:d920d64db582 155 UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
lynxeyed_atsu 0:d920d64db582 156 UARTx->FDR = (UART_FDR_MULVAL(mulFracDivOptimal) \
lynxeyed_atsu 0:d920d64db582 157 | UART_FDR_DIVADDVAL(dividerAddOptimal)) & UART_FDR_BITMASK;
lynxeyed_atsu 0:d920d64db582 158 }
lynxeyed_atsu 0:d920d64db582 159 errorStatus = SUCCESS;
lynxeyed_atsu 0:d920d64db582 160 }
lynxeyed_atsu 0:d920d64db582 161
lynxeyed_atsu 0:d920d64db582 162 return errorStatus;
lynxeyed_atsu 0:d920d64db582 163 }
lynxeyed_atsu 0:d920d64db582 164
lynxeyed_atsu 0:d920d64db582 165 /* End of Private Functions ---------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 166
lynxeyed_atsu 0:d920d64db582 167
lynxeyed_atsu 0:d920d64db582 168 /* Public Functions ----------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 169 /** @addtogroup UART_Public_Functions
lynxeyed_atsu 0:d920d64db582 170 * @{
lynxeyed_atsu 0:d920d64db582 171 */
lynxeyed_atsu 0:d920d64db582 172 /* UART Init/DeInit functions -------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 173 /********************************************************************//**
lynxeyed_atsu 0:d920d64db582 174 * @brief Initializes the UARTx peripheral according to the specified
lynxeyed_atsu 0:d920d64db582 175 * parameters in the UART_ConfigStruct.
lynxeyed_atsu 0:d920d64db582 176 * @param[in] UARTx UART peripheral selected, should be:
lynxeyed_atsu 0:d920d64db582 177 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 178 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 179 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 180 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 181 * @param[in] UART_ConfigStruct Pointer to a UART_CFG_Type structure
lynxeyed_atsu 0:d920d64db582 182 * that contains the configuration information for the
lynxeyed_atsu 0:d920d64db582 183 * specified UART peripheral.
lynxeyed_atsu 0:d920d64db582 184 * @return None
lynxeyed_atsu 0:d920d64db582 185 *********************************************************************/
lynxeyed_atsu 0:d920d64db582 186 void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct)
lynxeyed_atsu 0:d920d64db582 187 {
lynxeyed_atsu 0:d920d64db582 188 uint32_t tmp;
lynxeyed_atsu 0:d920d64db582 189
lynxeyed_atsu 0:d920d64db582 190 // For debug mode
lynxeyed_atsu 0:d920d64db582 191 CHECK_PARAM(PARAM_UARTx(UARTx));
lynxeyed_atsu 0:d920d64db582 192 CHECK_PARAM(PARAM_UART_DATABIT(UART_ConfigStruct->Databits));
lynxeyed_atsu 0:d920d64db582 193 CHECK_PARAM(PARAM_UART_STOPBIT(UART_ConfigStruct->Stopbits));
lynxeyed_atsu 0:d920d64db582 194 CHECK_PARAM(PARAM_UART_PARITY(UART_ConfigStruct->Parity));
lynxeyed_atsu 0:d920d64db582 195
lynxeyed_atsu 0:d920d64db582 196 #ifdef _UART0
lynxeyed_atsu 0:d920d64db582 197 if(UARTx == (LPC_UART_TypeDef *)LPC_UART0)
lynxeyed_atsu 0:d920d64db582 198 {
lynxeyed_atsu 0:d920d64db582 199 /* Set up clock and power for UART module */
lynxeyed_atsu 0:d920d64db582 200 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, ENABLE);
lynxeyed_atsu 0:d920d64db582 201 }
lynxeyed_atsu 0:d920d64db582 202 #endif
lynxeyed_atsu 0:d920d64db582 203
lynxeyed_atsu 0:d920d64db582 204 #ifdef _UART1
lynxeyed_atsu 0:d920d64db582 205 if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 206 {
lynxeyed_atsu 0:d920d64db582 207 /* Set up clock and power for UART module */
lynxeyed_atsu 0:d920d64db582 208 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, ENABLE);
lynxeyed_atsu 0:d920d64db582 209 }
lynxeyed_atsu 0:d920d64db582 210 #endif
lynxeyed_atsu 0:d920d64db582 211
lynxeyed_atsu 0:d920d64db582 212 #ifdef _UART2
lynxeyed_atsu 0:d920d64db582 213 if(UARTx == LPC_UART2)
lynxeyed_atsu 0:d920d64db582 214 {
lynxeyed_atsu 0:d920d64db582 215 /* Set up clock and power for UART module */
lynxeyed_atsu 0:d920d64db582 216 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, ENABLE);
lynxeyed_atsu 0:d920d64db582 217 }
lynxeyed_atsu 0:d920d64db582 218 #endif
lynxeyed_atsu 0:d920d64db582 219
lynxeyed_atsu 0:d920d64db582 220 #ifdef _UART3
lynxeyed_atsu 0:d920d64db582 221 if(UARTx == LPC_UART3)
lynxeyed_atsu 0:d920d64db582 222 {
lynxeyed_atsu 0:d920d64db582 223 /* Set up clock and power for UART module */
lynxeyed_atsu 0:d920d64db582 224 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, ENABLE);
lynxeyed_atsu 0:d920d64db582 225 }
lynxeyed_atsu 0:d920d64db582 226 #endif
lynxeyed_atsu 0:d920d64db582 227
lynxeyed_atsu 0:d920d64db582 228 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 229 {
lynxeyed_atsu 0:d920d64db582 230 /* FIFOs are empty */
lynxeyed_atsu 0:d920d64db582 231 ((LPC_UART1_TypeDef *)UARTx)->/*IIFCR.*/FCR = ( UART_FCR_FIFO_EN \
lynxeyed_atsu 0:d920d64db582 232 | UART_FCR_RX_RS | UART_FCR_TX_RS);
lynxeyed_atsu 0:d920d64db582 233 // Disable FIFO
lynxeyed_atsu 0:d920d64db582 234 ((LPC_UART1_TypeDef *)UARTx)->/*IIFCR.*/FCR = 0;
lynxeyed_atsu 0:d920d64db582 235
lynxeyed_atsu 0:d920d64db582 236 // Dummy reading
lynxeyed_atsu 0:d920d64db582 237 while (((LPC_UART1_TypeDef *)UARTx)->LSR & UART_LSR_RDR)
lynxeyed_atsu 0:d920d64db582 238 {
lynxeyed_atsu 0:d920d64db582 239 tmp = ((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/RBR;
lynxeyed_atsu 0:d920d64db582 240 }
lynxeyed_atsu 0:d920d64db582 241
lynxeyed_atsu 0:d920d64db582 242 ((LPC_UART1_TypeDef *)UARTx)->TER = UART_TER_TXEN;
lynxeyed_atsu 0:d920d64db582 243 // Wait for current transmit complete
lynxeyed_atsu 0:d920d64db582 244 while (!(((LPC_UART1_TypeDef *)UARTx)->LSR & UART_LSR_THRE));
lynxeyed_atsu 0:d920d64db582 245 // Disable Tx
lynxeyed_atsu 0:d920d64db582 246 ((LPC_UART1_TypeDef *)UARTx)->TER = 0;
lynxeyed_atsu 0:d920d64db582 247
lynxeyed_atsu 0:d920d64db582 248 // Disable interrupt
lynxeyed_atsu 0:d920d64db582 249 ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/IER = 0;
lynxeyed_atsu 0:d920d64db582 250 // Set LCR to default state
lynxeyed_atsu 0:d920d64db582 251 ((LPC_UART1_TypeDef *)UARTx)->LCR = 0;
lynxeyed_atsu 0:d920d64db582 252 // Set ACR to default state
lynxeyed_atsu 0:d920d64db582 253 ((LPC_UART1_TypeDef *)UARTx)->ACR = 0;
lynxeyed_atsu 0:d920d64db582 254 // Set Modem Control to default state
lynxeyed_atsu 0:d920d64db582 255 ((LPC_UART1_TypeDef *)UARTx)->MCR = 0;
lynxeyed_atsu 0:d920d64db582 256 // Set RS485 control to default state
lynxeyed_atsu 0:d920d64db582 257 ((LPC_UART1_TypeDef *)UARTx)->RS485CTRL = 0;
lynxeyed_atsu 0:d920d64db582 258 // Set RS485 delay timer to default state
lynxeyed_atsu 0:d920d64db582 259 ((LPC_UART1_TypeDef *)UARTx)->RS485DLY = 0;
lynxeyed_atsu 0:d920d64db582 260 // Set RS485 addr match to default state
lynxeyed_atsu 0:d920d64db582 261 ((LPC_UART1_TypeDef *)UARTx)->ADRMATCH = 0;
lynxeyed_atsu 0:d920d64db582 262 //Dummy Reading to Clear Status
lynxeyed_atsu 0:d920d64db582 263 tmp = ((LPC_UART1_TypeDef *)UARTx)->MSR;
lynxeyed_atsu 0:d920d64db582 264 tmp = ((LPC_UART1_TypeDef *)UARTx)->LSR;
lynxeyed_atsu 0:d920d64db582 265 }
lynxeyed_atsu 0:d920d64db582 266 else
lynxeyed_atsu 0:d920d64db582 267 {
lynxeyed_atsu 0:d920d64db582 268 /* FIFOs are empty */
lynxeyed_atsu 0:d920d64db582 269 UARTx->/*IIFCR.*/FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS);
lynxeyed_atsu 0:d920d64db582 270 // Disable FIFO
lynxeyed_atsu 0:d920d64db582 271 UARTx->/*IIFCR.*/FCR = 0;
lynxeyed_atsu 0:d920d64db582 272
lynxeyed_atsu 0:d920d64db582 273 // Dummy reading
lynxeyed_atsu 0:d920d64db582 274 while (UARTx->LSR & UART_LSR_RDR)
lynxeyed_atsu 0:d920d64db582 275 {
lynxeyed_atsu 0:d920d64db582 276 tmp = UARTx->/*RBTHDLR.*/RBR;
lynxeyed_atsu 0:d920d64db582 277 }
lynxeyed_atsu 0:d920d64db582 278
lynxeyed_atsu 0:d920d64db582 279 UARTx->TER = UART_TER_TXEN;
lynxeyed_atsu 0:d920d64db582 280 // Wait for current transmit complete
lynxeyed_atsu 0:d920d64db582 281 while (!(UARTx->LSR & UART_LSR_THRE));
lynxeyed_atsu 0:d920d64db582 282 // Disable Tx
lynxeyed_atsu 0:d920d64db582 283 UARTx->TER = 0;
lynxeyed_atsu 0:d920d64db582 284
lynxeyed_atsu 0:d920d64db582 285 // Disable interrupt
lynxeyed_atsu 0:d920d64db582 286 UARTx->/*DLIER.*/IER = 0;
lynxeyed_atsu 0:d920d64db582 287 // Set LCR to default state
lynxeyed_atsu 0:d920d64db582 288 UARTx->LCR = 0;
lynxeyed_atsu 0:d920d64db582 289 // Set ACR to default state
lynxeyed_atsu 0:d920d64db582 290 UARTx->ACR = 0;
lynxeyed_atsu 0:d920d64db582 291 // Dummy reading
lynxeyed_atsu 0:d920d64db582 292 tmp = UARTx->LSR;
lynxeyed_atsu 0:d920d64db582 293 }
lynxeyed_atsu 0:d920d64db582 294
lynxeyed_atsu 0:d920d64db582 295 if (UARTx == LPC_UART3)
lynxeyed_atsu 0:d920d64db582 296 {
lynxeyed_atsu 0:d920d64db582 297 // Set IrDA to default state
lynxeyed_atsu 0:d920d64db582 298 UARTx->ICR = 0;
lynxeyed_atsu 0:d920d64db582 299 }
lynxeyed_atsu 0:d920d64db582 300
lynxeyed_atsu 0:d920d64db582 301 // Set Line Control register ----------------------------
lynxeyed_atsu 0:d920d64db582 302
lynxeyed_atsu 0:d920d64db582 303 uart_set_divisors(UARTx, (UART_ConfigStruct->Baud_rate));
lynxeyed_atsu 0:d920d64db582 304
lynxeyed_atsu 0:d920d64db582 305 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 306 {
lynxeyed_atsu 0:d920d64db582 307 tmp = (((LPC_UART1_TypeDef *)UARTx)->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) \
lynxeyed_atsu 0:d920d64db582 308 & UART_LCR_BITMASK;
lynxeyed_atsu 0:d920d64db582 309 }
lynxeyed_atsu 0:d920d64db582 310 else
lynxeyed_atsu 0:d920d64db582 311 {
lynxeyed_atsu 0:d920d64db582 312 tmp = (UARTx->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK;
lynxeyed_atsu 0:d920d64db582 313 }
lynxeyed_atsu 0:d920d64db582 314
lynxeyed_atsu 0:d920d64db582 315 switch (UART_ConfigStruct->Databits){
lynxeyed_atsu 0:d920d64db582 316 case UART_DATABIT_5:
lynxeyed_atsu 0:d920d64db582 317 tmp |= UART_LCR_WLEN5;
lynxeyed_atsu 0:d920d64db582 318 break;
lynxeyed_atsu 0:d920d64db582 319 case UART_DATABIT_6:
lynxeyed_atsu 0:d920d64db582 320 tmp |= UART_LCR_WLEN6;
lynxeyed_atsu 0:d920d64db582 321 break;
lynxeyed_atsu 0:d920d64db582 322 case UART_DATABIT_7:
lynxeyed_atsu 0:d920d64db582 323 tmp |= UART_LCR_WLEN7;
lynxeyed_atsu 0:d920d64db582 324 break;
lynxeyed_atsu 0:d920d64db582 325 case UART_DATABIT_8:
lynxeyed_atsu 0:d920d64db582 326 default:
lynxeyed_atsu 0:d920d64db582 327 tmp |= UART_LCR_WLEN8;
lynxeyed_atsu 0:d920d64db582 328 break;
lynxeyed_atsu 0:d920d64db582 329 }
lynxeyed_atsu 0:d920d64db582 330
lynxeyed_atsu 0:d920d64db582 331 if (UART_ConfigStruct->Parity == UART_PARITY_NONE)
lynxeyed_atsu 0:d920d64db582 332 {
lynxeyed_atsu 0:d920d64db582 333 // Do nothing...
lynxeyed_atsu 0:d920d64db582 334 }
lynxeyed_atsu 0:d920d64db582 335 else
lynxeyed_atsu 0:d920d64db582 336 {
lynxeyed_atsu 0:d920d64db582 337 tmp |= UART_LCR_PARITY_EN;
lynxeyed_atsu 0:d920d64db582 338 switch (UART_ConfigStruct->Parity)
lynxeyed_atsu 0:d920d64db582 339 {
lynxeyed_atsu 0:d920d64db582 340 case UART_PARITY_ODD:
lynxeyed_atsu 0:d920d64db582 341 tmp |= UART_LCR_PARITY_ODD;
lynxeyed_atsu 0:d920d64db582 342 break;
lynxeyed_atsu 0:d920d64db582 343
lynxeyed_atsu 0:d920d64db582 344 case UART_PARITY_EVEN:
lynxeyed_atsu 0:d920d64db582 345 tmp |= UART_LCR_PARITY_EVEN;
lynxeyed_atsu 0:d920d64db582 346 break;
lynxeyed_atsu 0:d920d64db582 347
lynxeyed_atsu 0:d920d64db582 348 case UART_PARITY_SP_1:
lynxeyed_atsu 0:d920d64db582 349 tmp |= UART_LCR_PARITY_F_1;
lynxeyed_atsu 0:d920d64db582 350 break;
lynxeyed_atsu 0:d920d64db582 351
lynxeyed_atsu 0:d920d64db582 352 case UART_PARITY_SP_0:
lynxeyed_atsu 0:d920d64db582 353 tmp |= UART_LCR_PARITY_F_0;
lynxeyed_atsu 0:d920d64db582 354 break;
lynxeyed_atsu 0:d920d64db582 355 default:
lynxeyed_atsu 0:d920d64db582 356 break;
lynxeyed_atsu 0:d920d64db582 357 }
lynxeyed_atsu 0:d920d64db582 358 }
lynxeyed_atsu 0:d920d64db582 359
lynxeyed_atsu 0:d920d64db582 360 switch (UART_ConfigStruct->Stopbits){
lynxeyed_atsu 0:d920d64db582 361 case UART_STOPBIT_2:
lynxeyed_atsu 0:d920d64db582 362 tmp |= UART_LCR_STOPBIT_SEL;
lynxeyed_atsu 0:d920d64db582 363 break;
lynxeyed_atsu 0:d920d64db582 364 case UART_STOPBIT_1:
lynxeyed_atsu 0:d920d64db582 365 default:
lynxeyed_atsu 0:d920d64db582 366 // Do no thing
lynxeyed_atsu 0:d920d64db582 367 break;
lynxeyed_atsu 0:d920d64db582 368 }
lynxeyed_atsu 0:d920d64db582 369
lynxeyed_atsu 0:d920d64db582 370
lynxeyed_atsu 0:d920d64db582 371 // Write back to LCR, configure FIFO and Disable Tx
lynxeyed_atsu 0:d920d64db582 372 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 373 {
lynxeyed_atsu 0:d920d64db582 374 ((LPC_UART1_TypeDef *)UARTx)->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
lynxeyed_atsu 0:d920d64db582 375 }
lynxeyed_atsu 0:d920d64db582 376 else
lynxeyed_atsu 0:d920d64db582 377 {
lynxeyed_atsu 0:d920d64db582 378 UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
lynxeyed_atsu 0:d920d64db582 379 }
lynxeyed_atsu 0:d920d64db582 380 }
lynxeyed_atsu 0:d920d64db582 381
lynxeyed_atsu 0:d920d64db582 382 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 383 * @brief De-initializes the UARTx peripheral registers to their
lynxeyed_atsu 0:d920d64db582 384 * default reset values.
lynxeyed_atsu 0:d920d64db582 385 * @param[in] UARTx UART peripheral selected, should be:
lynxeyed_atsu 0:d920d64db582 386 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 387 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 388 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 389 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 390 * @return None
lynxeyed_atsu 0:d920d64db582 391 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 392 void UART_DeInit(LPC_UART_TypeDef* UARTx)
lynxeyed_atsu 0:d920d64db582 393 {
lynxeyed_atsu 0:d920d64db582 394 // For debug mode
lynxeyed_atsu 0:d920d64db582 395 CHECK_PARAM(PARAM_UARTx(UARTx));
lynxeyed_atsu 0:d920d64db582 396
lynxeyed_atsu 0:d920d64db582 397 UART_TxCmd(UARTx, DISABLE);
lynxeyed_atsu 0:d920d64db582 398
lynxeyed_atsu 0:d920d64db582 399 #ifdef _UART0
lynxeyed_atsu 0:d920d64db582 400 if (UARTx == (LPC_UART_TypeDef *)LPC_UART0)
lynxeyed_atsu 0:d920d64db582 401 {
lynxeyed_atsu 0:d920d64db582 402 /* Set up clock and power for UART module */
lynxeyed_atsu 0:d920d64db582 403 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, DISABLE);
lynxeyed_atsu 0:d920d64db582 404 }
lynxeyed_atsu 0:d920d64db582 405 #endif
lynxeyed_atsu 0:d920d64db582 406
lynxeyed_atsu 0:d920d64db582 407 #ifdef _UART1
lynxeyed_atsu 0:d920d64db582 408 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 409 {
lynxeyed_atsu 0:d920d64db582 410 /* Set up clock and power for UART module */
lynxeyed_atsu 0:d920d64db582 411 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, DISABLE);
lynxeyed_atsu 0:d920d64db582 412 }
lynxeyed_atsu 0:d920d64db582 413 #endif
lynxeyed_atsu 0:d920d64db582 414
lynxeyed_atsu 0:d920d64db582 415 #ifdef _UART2
lynxeyed_atsu 0:d920d64db582 416 if (UARTx == LPC_UART2)
lynxeyed_atsu 0:d920d64db582 417 {
lynxeyed_atsu 0:d920d64db582 418 /* Set up clock and power for UART module */
lynxeyed_atsu 0:d920d64db582 419 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, DISABLE);
lynxeyed_atsu 0:d920d64db582 420 }
lynxeyed_atsu 0:d920d64db582 421 #endif
lynxeyed_atsu 0:d920d64db582 422
lynxeyed_atsu 0:d920d64db582 423 #ifdef _UART3
lynxeyed_atsu 0:d920d64db582 424 if (UARTx == LPC_UART3)
lynxeyed_atsu 0:d920d64db582 425 {
lynxeyed_atsu 0:d920d64db582 426 /* Set up clock and power for UART module */
lynxeyed_atsu 0:d920d64db582 427 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, DISABLE);
lynxeyed_atsu 0:d920d64db582 428 }
lynxeyed_atsu 0:d920d64db582 429 #endif
lynxeyed_atsu 0:d920d64db582 430 }
lynxeyed_atsu 0:d920d64db582 431
lynxeyed_atsu 0:d920d64db582 432 /*****************************************************************************//**
lynxeyed_atsu 0:d920d64db582 433 * @brief Fills each UART_InitStruct member with its default value:
lynxeyed_atsu 0:d920d64db582 434 * - 9600 bps
lynxeyed_atsu 0:d920d64db582 435 * - 8-bit data
lynxeyed_atsu 0:d920d64db582 436 * - 1 Stopbit
lynxeyed_atsu 0:d920d64db582 437 * - None Parity
lynxeyed_atsu 0:d920d64db582 438 * @param[in] UART_InitStruct Pointer to a UART_CFG_Type structure
lynxeyed_atsu 0:d920d64db582 439 * which will be initialized.
lynxeyed_atsu 0:d920d64db582 440 * @return None
lynxeyed_atsu 0:d920d64db582 441 *******************************************************************************/
lynxeyed_atsu 0:d920d64db582 442 void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct)
lynxeyed_atsu 0:d920d64db582 443 {
lynxeyed_atsu 0:d920d64db582 444 UART_InitStruct->Baud_rate = 9600;
lynxeyed_atsu 0:d920d64db582 445 UART_InitStruct->Databits = UART_DATABIT_8;
lynxeyed_atsu 0:d920d64db582 446 UART_InitStruct->Parity = UART_PARITY_NONE;
lynxeyed_atsu 0:d920d64db582 447 UART_InitStruct->Stopbits = UART_STOPBIT_1;
lynxeyed_atsu 0:d920d64db582 448 }
lynxeyed_atsu 0:d920d64db582 449
lynxeyed_atsu 0:d920d64db582 450 /* UART Send/Recieve functions -------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 451 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 452 * @brief Transmit a single data through UART peripheral
lynxeyed_atsu 0:d920d64db582 453 * @param[in] UARTx UART peripheral selected, should be:
lynxeyed_atsu 0:d920d64db582 454 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 455 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 456 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 457 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 458 * @param[in] Data Data to transmit (must be 8-bit long)
lynxeyed_atsu 0:d920d64db582 459 * @return None
lynxeyed_atsu 0:d920d64db582 460 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 461 void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data)
lynxeyed_atsu 0:d920d64db582 462 {
lynxeyed_atsu 0:d920d64db582 463 CHECK_PARAM(PARAM_UARTx(UARTx));
lynxeyed_atsu 0:d920d64db582 464
lynxeyed_atsu 0:d920d64db582 465 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 466 {
lynxeyed_atsu 0:d920d64db582 467 ((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/THR = Data & UART_THR_MASKBIT;
lynxeyed_atsu 0:d920d64db582 468 }
lynxeyed_atsu 0:d920d64db582 469 else
lynxeyed_atsu 0:d920d64db582 470 {
lynxeyed_atsu 0:d920d64db582 471 UARTx->/*RBTHDLR.*/THR = Data & UART_THR_MASKBIT;
lynxeyed_atsu 0:d920d64db582 472 }
lynxeyed_atsu 0:d920d64db582 473
lynxeyed_atsu 0:d920d64db582 474 }
lynxeyed_atsu 0:d920d64db582 475
lynxeyed_atsu 0:d920d64db582 476
lynxeyed_atsu 0:d920d64db582 477 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 478 * @brief Receive a single data from UART peripheral
lynxeyed_atsu 0:d920d64db582 479 * @param[in] UARTx UART peripheral selected, should be:
lynxeyed_atsu 0:d920d64db582 480 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 481 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 482 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 483 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 484 * @return Data received
lynxeyed_atsu 0:d920d64db582 485 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 486 uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx)
lynxeyed_atsu 0:d920d64db582 487 {
lynxeyed_atsu 0:d920d64db582 488 CHECK_PARAM(PARAM_UARTx(UARTx));
lynxeyed_atsu 0:d920d64db582 489
lynxeyed_atsu 0:d920d64db582 490 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 491 {
lynxeyed_atsu 0:d920d64db582 492 return (((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/RBR & UART_RBR_MASKBIT);
lynxeyed_atsu 0:d920d64db582 493 }
lynxeyed_atsu 0:d920d64db582 494 else
lynxeyed_atsu 0:d920d64db582 495 {
lynxeyed_atsu 0:d920d64db582 496 return (UARTx->/*RBTHDLR.*/RBR & UART_RBR_MASKBIT);
lynxeyed_atsu 0:d920d64db582 497 }
lynxeyed_atsu 0:d920d64db582 498 }
lynxeyed_atsu 0:d920d64db582 499
lynxeyed_atsu 0:d920d64db582 500 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 501 * @brief Send a block of data via UART peripheral
lynxeyed_atsu 0:d920d64db582 502 * @param[in] UARTx Selected UART peripheral used to send data, should be:
lynxeyed_atsu 0:d920d64db582 503 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 504 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 505 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 506 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 507 * @param[in] txbuf Pointer to Transmit buffer
lynxeyed_atsu 0:d920d64db582 508 * @param[in] buflen Length of Transmit buffer
lynxeyed_atsu 0:d920d64db582 509 * @param[in] flag Flag used in UART transfer, should be
lynxeyed_atsu 0:d920d64db582 510 * NONE_BLOCKING or BLOCKING
lynxeyed_atsu 0:d920d64db582 511 * @return Number of bytes sent.
lynxeyed_atsu 0:d920d64db582 512 *
lynxeyed_atsu 0:d920d64db582 513 * Note: when using UART in BLOCKING mode, a time-out condition is used
lynxeyed_atsu 0:d920d64db582 514 * via defined symbol UART_BLOCKING_TIMEOUT.
lynxeyed_atsu 0:d920d64db582 515 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 516 uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf,
lynxeyed_atsu 0:d920d64db582 517 uint32_t buflen, TRANSFER_BLOCK_Type flag)
lynxeyed_atsu 0:d920d64db582 518 {
lynxeyed_atsu 0:d920d64db582 519 uint32_t bToSend, bSent, timeOut, fifo_cnt;
lynxeyed_atsu 0:d920d64db582 520 uint8_t *pChar = txbuf;
lynxeyed_atsu 0:d920d64db582 521
lynxeyed_atsu 0:d920d64db582 522 bToSend = buflen;
lynxeyed_atsu 0:d920d64db582 523
lynxeyed_atsu 0:d920d64db582 524 // blocking mode
lynxeyed_atsu 0:d920d64db582 525 if (flag == BLOCKING) {
lynxeyed_atsu 0:d920d64db582 526 bSent = 0;
lynxeyed_atsu 0:d920d64db582 527 while (bToSend){
lynxeyed_atsu 0:d920d64db582 528 timeOut = UART_BLOCKING_TIMEOUT;
lynxeyed_atsu 0:d920d64db582 529 // Wait for THR empty with timeout
lynxeyed_atsu 0:d920d64db582 530 while (!(UARTx->LSR & UART_LSR_THRE)) {
lynxeyed_atsu 0:d920d64db582 531 if (timeOut == 0) break;
lynxeyed_atsu 0:d920d64db582 532 timeOut--;
lynxeyed_atsu 0:d920d64db582 533 }
lynxeyed_atsu 0:d920d64db582 534 // Time out!
lynxeyed_atsu 0:d920d64db582 535 if(timeOut == 0) break;
lynxeyed_atsu 0:d920d64db582 536 fifo_cnt = UART_TX_FIFO_SIZE;
lynxeyed_atsu 0:d920d64db582 537 while (fifo_cnt && bToSend){
lynxeyed_atsu 0:d920d64db582 538 UART_SendByte(UARTx, (*pChar++));
lynxeyed_atsu 0:d920d64db582 539 fifo_cnt--;
lynxeyed_atsu 0:d920d64db582 540 bToSend--;
lynxeyed_atsu 0:d920d64db582 541 bSent++;
lynxeyed_atsu 0:d920d64db582 542 }
lynxeyed_atsu 0:d920d64db582 543 }
lynxeyed_atsu 0:d920d64db582 544 }
lynxeyed_atsu 0:d920d64db582 545 // None blocking mode
lynxeyed_atsu 0:d920d64db582 546 else {
lynxeyed_atsu 0:d920d64db582 547 bSent = 0;
lynxeyed_atsu 0:d920d64db582 548 while (bToSend) {
lynxeyed_atsu 0:d920d64db582 549 if (!(UARTx->LSR & UART_LSR_THRE)){
lynxeyed_atsu 0:d920d64db582 550 break;
lynxeyed_atsu 0:d920d64db582 551 }
lynxeyed_atsu 0:d920d64db582 552 fifo_cnt = UART_TX_FIFO_SIZE;
lynxeyed_atsu 0:d920d64db582 553 while (fifo_cnt && bToSend) {
lynxeyed_atsu 0:d920d64db582 554 UART_SendByte(UARTx, (*pChar++));
lynxeyed_atsu 0:d920d64db582 555 bToSend--;
lynxeyed_atsu 0:d920d64db582 556 fifo_cnt--;
lynxeyed_atsu 0:d920d64db582 557 bSent++;
lynxeyed_atsu 0:d920d64db582 558 }
lynxeyed_atsu 0:d920d64db582 559 }
lynxeyed_atsu 0:d920d64db582 560 }
lynxeyed_atsu 0:d920d64db582 561 return bSent;
lynxeyed_atsu 0:d920d64db582 562 }
lynxeyed_atsu 0:d920d64db582 563
lynxeyed_atsu 0:d920d64db582 564 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 565 * @brief Receive a block of data via UART peripheral
lynxeyed_atsu 0:d920d64db582 566 * @param[in] UARTx Selected UART peripheral used to send data,
lynxeyed_atsu 0:d920d64db582 567 * should be:
lynxeyed_atsu 0:d920d64db582 568 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 569 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 570 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 571 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 572 * @param[out] rxbuf Pointer to Received buffer
lynxeyed_atsu 0:d920d64db582 573 * @param[in] buflen Length of Received buffer
lynxeyed_atsu 0:d920d64db582 574 * @param[in] flag Flag mode, should be NONE_BLOCKING or BLOCKING
lynxeyed_atsu 0:d920d64db582 575
lynxeyed_atsu 0:d920d64db582 576 * @return Number of bytes received
lynxeyed_atsu 0:d920d64db582 577 *
lynxeyed_atsu 0:d920d64db582 578 * Note: when using UART in BLOCKING mode, a time-out condition is used
lynxeyed_atsu 0:d920d64db582 579 * via defined symbol UART_BLOCKING_TIMEOUT.
lynxeyed_atsu 0:d920d64db582 580 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 581 uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \
lynxeyed_atsu 0:d920d64db582 582 uint32_t buflen, TRANSFER_BLOCK_Type flag)
lynxeyed_atsu 0:d920d64db582 583 {
lynxeyed_atsu 0:d920d64db582 584 uint32_t bToRecv, bRecv, timeOut;
lynxeyed_atsu 0:d920d64db582 585 uint8_t *pChar = rxbuf;
lynxeyed_atsu 0:d920d64db582 586
lynxeyed_atsu 0:d920d64db582 587 bToRecv = buflen;
lynxeyed_atsu 0:d920d64db582 588
lynxeyed_atsu 0:d920d64db582 589 // Blocking mode
lynxeyed_atsu 0:d920d64db582 590 if (flag == BLOCKING) {
lynxeyed_atsu 0:d920d64db582 591 bRecv = 0;
lynxeyed_atsu 0:d920d64db582 592 while (bToRecv){
lynxeyed_atsu 0:d920d64db582 593 timeOut = UART_BLOCKING_TIMEOUT;
lynxeyed_atsu 0:d920d64db582 594 while (!(UARTx->LSR & UART_LSR_RDR)){
lynxeyed_atsu 0:d920d64db582 595 if (timeOut == 0) break;
lynxeyed_atsu 0:d920d64db582 596 timeOut--;
lynxeyed_atsu 0:d920d64db582 597 }
lynxeyed_atsu 0:d920d64db582 598 // Time out!
lynxeyed_atsu 0:d920d64db582 599 if(timeOut == 0) break;
lynxeyed_atsu 0:d920d64db582 600 // Get data from the buffer
lynxeyed_atsu 0:d920d64db582 601 (*pChar++) = UART_ReceiveByte(UARTx);
lynxeyed_atsu 0:d920d64db582 602 bToRecv--;
lynxeyed_atsu 0:d920d64db582 603 bRecv++;
lynxeyed_atsu 0:d920d64db582 604 }
lynxeyed_atsu 0:d920d64db582 605 }
lynxeyed_atsu 0:d920d64db582 606 // None blocking mode
lynxeyed_atsu 0:d920d64db582 607 else {
lynxeyed_atsu 0:d920d64db582 608 bRecv = 0;
lynxeyed_atsu 0:d920d64db582 609 while (bToRecv) {
lynxeyed_atsu 0:d920d64db582 610 if (!(UARTx->LSR & UART_LSR_RDR)) {
lynxeyed_atsu 0:d920d64db582 611 break;
lynxeyed_atsu 0:d920d64db582 612 } else {
lynxeyed_atsu 0:d920d64db582 613 (*pChar++) = UART_ReceiveByte(UARTx);
lynxeyed_atsu 0:d920d64db582 614 bRecv++;
lynxeyed_atsu 0:d920d64db582 615 bToRecv--;
lynxeyed_atsu 0:d920d64db582 616 }
lynxeyed_atsu 0:d920d64db582 617 }
lynxeyed_atsu 0:d920d64db582 618 }
lynxeyed_atsu 0:d920d64db582 619 return bRecv;
lynxeyed_atsu 0:d920d64db582 620 }
lynxeyed_atsu 0:d920d64db582 621
lynxeyed_atsu 0:d920d64db582 622 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 623 * @brief Force BREAK character on UART line, output pin UARTx TXD is
lynxeyed_atsu 0:d920d64db582 624 forced to logic 0.
lynxeyed_atsu 0:d920d64db582 625 * @param[in] UARTx UART peripheral selected, should be:
lynxeyed_atsu 0:d920d64db582 626 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 627 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 628 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 629 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 630 * @return None
lynxeyed_atsu 0:d920d64db582 631 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 632 void UART_ForceBreak(LPC_UART_TypeDef* UARTx)
lynxeyed_atsu 0:d920d64db582 633 {
lynxeyed_atsu 0:d920d64db582 634 CHECK_PARAM(PARAM_UARTx(UARTx));
lynxeyed_atsu 0:d920d64db582 635
lynxeyed_atsu 0:d920d64db582 636 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 637 {
lynxeyed_atsu 0:d920d64db582 638 ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_BREAK_EN;
lynxeyed_atsu 0:d920d64db582 639 }
lynxeyed_atsu 0:d920d64db582 640 else
lynxeyed_atsu 0:d920d64db582 641 {
lynxeyed_atsu 0:d920d64db582 642 UARTx->LCR |= UART_LCR_BREAK_EN;
lynxeyed_atsu 0:d920d64db582 643 }
lynxeyed_atsu 0:d920d64db582 644 }
lynxeyed_atsu 0:d920d64db582 645
lynxeyed_atsu 0:d920d64db582 646
lynxeyed_atsu 0:d920d64db582 647 /********************************************************************//**
lynxeyed_atsu 0:d920d64db582 648 * @brief Enable or disable specified UART interrupt.
lynxeyed_atsu 0:d920d64db582 649 * @param[in] UARTx UART peripheral selected, should be
lynxeyed_atsu 0:d920d64db582 650 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 651 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 652 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 653 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 654 * @param[in] UARTIntCfg Specifies the interrupt flag,
lynxeyed_atsu 0:d920d64db582 655 * should be one of the following:
lynxeyed_atsu 0:d920d64db582 656 - UART_INTCFG_RBR : RBR Interrupt enable
lynxeyed_atsu 0:d920d64db582 657 - UART_INTCFG_THRE : THR Interrupt enable
lynxeyed_atsu 0:d920d64db582 658 - UART_INTCFG_RLS : RX line status interrupt enable
lynxeyed_atsu 0:d920d64db582 659 - UART1_INTCFG_MS : Modem status interrupt enable (UART1 only)
lynxeyed_atsu 0:d920d64db582 660 - UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only)
lynxeyed_atsu 0:d920d64db582 661 - UART_INTCFG_ABEO : Enables the end of auto-baud interrupt
lynxeyed_atsu 0:d920d64db582 662 - UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt
lynxeyed_atsu 0:d920d64db582 663 * @param[in] NewState New state of specified UART interrupt type,
lynxeyed_atsu 0:d920d64db582 664 * should be:
lynxeyed_atsu 0:d920d64db582 665 * - ENALBE: Enable this UART interrupt type.
lynxeyed_atsu 0:d920d64db582 666 * - DISALBE: Disable this UART interrupt type.
lynxeyed_atsu 0:d920d64db582 667 * @return None
lynxeyed_atsu 0:d920d64db582 668 *********************************************************************/
lynxeyed_atsu 0:d920d64db582 669 void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState)
lynxeyed_atsu 0:d920d64db582 670 {
lynxeyed_atsu 0:d920d64db582 671 uint32_t tmp = 0;
lynxeyed_atsu 0:d920d64db582 672
lynxeyed_atsu 0:d920d64db582 673 CHECK_PARAM(PARAM_UARTx(UARTx));
lynxeyed_atsu 0:d920d64db582 674 CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
lynxeyed_atsu 0:d920d64db582 675
lynxeyed_atsu 0:d920d64db582 676 switch(UARTIntCfg){
lynxeyed_atsu 0:d920d64db582 677 case UART_INTCFG_RBR:
lynxeyed_atsu 0:d920d64db582 678 tmp = UART_IER_RBRINT_EN;
lynxeyed_atsu 0:d920d64db582 679 break;
lynxeyed_atsu 0:d920d64db582 680 case UART_INTCFG_THRE:
lynxeyed_atsu 0:d920d64db582 681 tmp = UART_IER_THREINT_EN;
lynxeyed_atsu 0:d920d64db582 682 break;
lynxeyed_atsu 0:d920d64db582 683 case UART_INTCFG_RLS:
lynxeyed_atsu 0:d920d64db582 684 tmp = UART_IER_RLSINT_EN;
lynxeyed_atsu 0:d920d64db582 685 break;
lynxeyed_atsu 0:d920d64db582 686 case UART1_INTCFG_MS:
lynxeyed_atsu 0:d920d64db582 687 tmp = UART1_IER_MSINT_EN;
lynxeyed_atsu 0:d920d64db582 688 break;
lynxeyed_atsu 0:d920d64db582 689 case UART1_INTCFG_CTS:
lynxeyed_atsu 0:d920d64db582 690 tmp = UART1_IER_CTSINT_EN;
lynxeyed_atsu 0:d920d64db582 691 break;
lynxeyed_atsu 0:d920d64db582 692 case UART_INTCFG_ABEO:
lynxeyed_atsu 0:d920d64db582 693 tmp = UART_IER_ABEOINT_EN;
lynxeyed_atsu 0:d920d64db582 694 break;
lynxeyed_atsu 0:d920d64db582 695 case UART_INTCFG_ABTO:
lynxeyed_atsu 0:d920d64db582 696 tmp = UART_IER_ABTOINT_EN;
lynxeyed_atsu 0:d920d64db582 697 break;
lynxeyed_atsu 0:d920d64db582 698 }
lynxeyed_atsu 0:d920d64db582 699
lynxeyed_atsu 0:d920d64db582 700 if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 701 {
lynxeyed_atsu 0:d920d64db582 702 CHECK_PARAM((PARAM_UART_INTCFG(UARTIntCfg)) || (PARAM_UART1_INTCFG(UARTIntCfg)));
lynxeyed_atsu 0:d920d64db582 703 }
lynxeyed_atsu 0:d920d64db582 704 else
lynxeyed_atsu 0:d920d64db582 705 {
lynxeyed_atsu 0:d920d64db582 706 CHECK_PARAM(PARAM_UART_INTCFG(UARTIntCfg));
lynxeyed_atsu 0:d920d64db582 707 }
lynxeyed_atsu 0:d920d64db582 708
lynxeyed_atsu 0:d920d64db582 709 if (NewState == ENABLE)
lynxeyed_atsu 0:d920d64db582 710 {
lynxeyed_atsu 0:d920d64db582 711 if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 712 {
lynxeyed_atsu 0:d920d64db582 713 ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/IER |= tmp;
lynxeyed_atsu 0:d920d64db582 714 }
lynxeyed_atsu 0:d920d64db582 715 else
lynxeyed_atsu 0:d920d64db582 716 {
lynxeyed_atsu 0:d920d64db582 717 UARTx->/*DLIER.*/IER |= tmp;
lynxeyed_atsu 0:d920d64db582 718 }
lynxeyed_atsu 0:d920d64db582 719 }
lynxeyed_atsu 0:d920d64db582 720 else
lynxeyed_atsu 0:d920d64db582 721 {
lynxeyed_atsu 0:d920d64db582 722 if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 723 {
lynxeyed_atsu 0:d920d64db582 724 ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/IER &= (~tmp) & UART1_IER_BITMASK;
lynxeyed_atsu 0:d920d64db582 725 }
lynxeyed_atsu 0:d920d64db582 726 else
lynxeyed_atsu 0:d920d64db582 727 {
lynxeyed_atsu 0:d920d64db582 728 UARTx->/*DLIER.*/IER &= (~tmp) & UART_IER_BITMASK;
lynxeyed_atsu 0:d920d64db582 729 }
lynxeyed_atsu 0:d920d64db582 730 }
lynxeyed_atsu 0:d920d64db582 731 }
lynxeyed_atsu 0:d920d64db582 732
lynxeyed_atsu 0:d920d64db582 733
lynxeyed_atsu 0:d920d64db582 734 /********************************************************************//**
lynxeyed_atsu 0:d920d64db582 735 * @brief Get current value of Line Status register in UART peripheral.
lynxeyed_atsu 0:d920d64db582 736 * @param[in] UARTx UART peripheral selected, should be:
lynxeyed_atsu 0:d920d64db582 737 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 738 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 739 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 740 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 741 * @return Current value of Line Status register in UART peripheral.
lynxeyed_atsu 0:d920d64db582 742 * Note: The return value of this function must be ANDed with each member in
lynxeyed_atsu 0:d920d64db582 743 * UART_LS_Type enumeration to determine current flag status
lynxeyed_atsu 0:d920d64db582 744 * corresponding to each Line status type. Because some flags in
lynxeyed_atsu 0:d920d64db582 745 * Line Status register will be cleared after reading, the next reading
lynxeyed_atsu 0:d920d64db582 746 * Line Status register could not be correct. So this function used to
lynxeyed_atsu 0:d920d64db582 747 * read Line status register in one time only, then the return value
lynxeyed_atsu 0:d920d64db582 748 * used to check all flags.
lynxeyed_atsu 0:d920d64db582 749 *********************************************************************/
lynxeyed_atsu 0:d920d64db582 750 uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx)
lynxeyed_atsu 0:d920d64db582 751 {
lynxeyed_atsu 0:d920d64db582 752 CHECK_PARAM(PARAM_UARTx(UARTx));
lynxeyed_atsu 0:d920d64db582 753
lynxeyed_atsu 0:d920d64db582 754 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 755 {
lynxeyed_atsu 0:d920d64db582 756 return ((((LPC_UART1_TypeDef *)LPC_UART1)->LSR) & UART_LSR_BITMASK);
lynxeyed_atsu 0:d920d64db582 757 }
lynxeyed_atsu 0:d920d64db582 758 else
lynxeyed_atsu 0:d920d64db582 759 {
lynxeyed_atsu 0:d920d64db582 760 return ((UARTx->LSR) & UART_LSR_BITMASK);
lynxeyed_atsu 0:d920d64db582 761 }
lynxeyed_atsu 0:d920d64db582 762 }
lynxeyed_atsu 0:d920d64db582 763
lynxeyed_atsu 0:d920d64db582 764 /********************************************************************//**
lynxeyed_atsu 0:d920d64db582 765 * @brief Get Interrupt Identification value
lynxeyed_atsu 0:d920d64db582 766 * @param[in] UARTx UART peripheral selected, should be:
lynxeyed_atsu 0:d920d64db582 767 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 768 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 769 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 770 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 771 * @return Current value of UART UIIR register in UART peripheral.
lynxeyed_atsu 0:d920d64db582 772 *********************************************************************/
lynxeyed_atsu 0:d920d64db582 773 uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx)
lynxeyed_atsu 0:d920d64db582 774 {
lynxeyed_atsu 0:d920d64db582 775 CHECK_PARAM(PARAM_UARTx(UARTx));
lynxeyed_atsu 0:d920d64db582 776 return (UARTx->IIR & 0x03CF);
lynxeyed_atsu 0:d920d64db582 777 }
lynxeyed_atsu 0:d920d64db582 778
lynxeyed_atsu 0:d920d64db582 779 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 780 * @brief Check whether if UART is busy or not
lynxeyed_atsu 0:d920d64db582 781 * @param[in] UARTx UART peripheral selected, should be:
lynxeyed_atsu 0:d920d64db582 782 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 783 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 784 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 785 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 786 * @return RESET if UART is not busy, otherwise return SET.
lynxeyed_atsu 0:d920d64db582 787 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 788 FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx)
lynxeyed_atsu 0:d920d64db582 789 {
lynxeyed_atsu 0:d920d64db582 790 if (UARTx->LSR & UART_LSR_TEMT){
lynxeyed_atsu 0:d920d64db582 791 return RESET;
lynxeyed_atsu 0:d920d64db582 792 } else {
lynxeyed_atsu 0:d920d64db582 793 return SET;
lynxeyed_atsu 0:d920d64db582 794 }
lynxeyed_atsu 0:d920d64db582 795 }
lynxeyed_atsu 0:d920d64db582 796
lynxeyed_atsu 0:d920d64db582 797
lynxeyed_atsu 0:d920d64db582 798 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 799 * @brief Configure FIFO function on selected UART peripheral
lynxeyed_atsu 0:d920d64db582 800 * @param[in] UARTx UART peripheral selected, should be:
lynxeyed_atsu 0:d920d64db582 801 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 802 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 803 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 804 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 805 * @param[in] FIFOCfg Pointer to a UART_FIFO_CFG_Type Structure that
lynxeyed_atsu 0:d920d64db582 806 * contains specified information about FIFO configuration
lynxeyed_atsu 0:d920d64db582 807 * @return none
lynxeyed_atsu 0:d920d64db582 808 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 809 void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg)
lynxeyed_atsu 0:d920d64db582 810 {
lynxeyed_atsu 0:d920d64db582 811 uint8_t tmp = 0;
lynxeyed_atsu 0:d920d64db582 812
lynxeyed_atsu 0:d920d64db582 813 CHECK_PARAM(PARAM_UARTx(UARTx));
lynxeyed_atsu 0:d920d64db582 814 CHECK_PARAM(PARAM_UART_FIFO_LEVEL(FIFOCfg->FIFO_Level));
lynxeyed_atsu 0:d920d64db582 815 CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_DMAMode));
lynxeyed_atsu 0:d920d64db582 816 CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetRxBuf));
lynxeyed_atsu 0:d920d64db582 817 CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetTxBuf));
lynxeyed_atsu 0:d920d64db582 818
lynxeyed_atsu 0:d920d64db582 819 tmp |= UART_FCR_FIFO_EN;
lynxeyed_atsu 0:d920d64db582 820 switch (FIFOCfg->FIFO_Level){
lynxeyed_atsu 0:d920d64db582 821 case UART_FIFO_TRGLEV0:
lynxeyed_atsu 0:d920d64db582 822 tmp |= UART_FCR_TRG_LEV0;
lynxeyed_atsu 0:d920d64db582 823 break;
lynxeyed_atsu 0:d920d64db582 824 case UART_FIFO_TRGLEV1:
lynxeyed_atsu 0:d920d64db582 825 tmp |= UART_FCR_TRG_LEV1;
lynxeyed_atsu 0:d920d64db582 826 break;
lynxeyed_atsu 0:d920d64db582 827 case UART_FIFO_TRGLEV2:
lynxeyed_atsu 0:d920d64db582 828 tmp |= UART_FCR_TRG_LEV2;
lynxeyed_atsu 0:d920d64db582 829 break;
lynxeyed_atsu 0:d920d64db582 830 case UART_FIFO_TRGLEV3:
lynxeyed_atsu 0:d920d64db582 831 default:
lynxeyed_atsu 0:d920d64db582 832 tmp |= UART_FCR_TRG_LEV3;
lynxeyed_atsu 0:d920d64db582 833 break;
lynxeyed_atsu 0:d920d64db582 834 }
lynxeyed_atsu 0:d920d64db582 835
lynxeyed_atsu 0:d920d64db582 836 if (FIFOCfg->FIFO_ResetTxBuf == ENABLE)
lynxeyed_atsu 0:d920d64db582 837 {
lynxeyed_atsu 0:d920d64db582 838 tmp |= UART_FCR_TX_RS;
lynxeyed_atsu 0:d920d64db582 839 }
lynxeyed_atsu 0:d920d64db582 840 if (FIFOCfg->FIFO_ResetRxBuf == ENABLE)
lynxeyed_atsu 0:d920d64db582 841 {
lynxeyed_atsu 0:d920d64db582 842 tmp |= UART_FCR_RX_RS;
lynxeyed_atsu 0:d920d64db582 843 }
lynxeyed_atsu 0:d920d64db582 844 if (FIFOCfg->FIFO_DMAMode == ENABLE)
lynxeyed_atsu 0:d920d64db582 845 {
lynxeyed_atsu 0:d920d64db582 846 tmp |= UART_FCR_DMAMODE_SEL;
lynxeyed_atsu 0:d920d64db582 847 }
lynxeyed_atsu 0:d920d64db582 848
lynxeyed_atsu 0:d920d64db582 849
lynxeyed_atsu 0:d920d64db582 850 //write to FIFO control register
lynxeyed_atsu 0:d920d64db582 851 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 852 {
lynxeyed_atsu 0:d920d64db582 853 ((LPC_UART1_TypeDef *)UARTx)->/*IIFCR.*/FCR = tmp & UART_FCR_BITMASK;
lynxeyed_atsu 0:d920d64db582 854 }
lynxeyed_atsu 0:d920d64db582 855 else
lynxeyed_atsu 0:d920d64db582 856 {
lynxeyed_atsu 0:d920d64db582 857 UARTx->/*IIFCR.*/FCR = tmp & UART_FCR_BITMASK;
lynxeyed_atsu 0:d920d64db582 858 }
lynxeyed_atsu 0:d920d64db582 859 }
lynxeyed_atsu 0:d920d64db582 860
lynxeyed_atsu 0:d920d64db582 861 /*****************************************************************************//**
lynxeyed_atsu 0:d920d64db582 862 * @brief Fills each UART_FIFOInitStruct member with its default value:
lynxeyed_atsu 0:d920d64db582 863 * - FIFO_DMAMode = DISABLE
lynxeyed_atsu 0:d920d64db582 864 * - FIFO_Level = UART_FIFO_TRGLEV0
lynxeyed_atsu 0:d920d64db582 865 * - FIFO_ResetRxBuf = ENABLE
lynxeyed_atsu 0:d920d64db582 866 * - FIFO_ResetTxBuf = ENABLE
lynxeyed_atsu 0:d920d64db582 867 * - FIFO_State = ENABLE
lynxeyed_atsu 0:d920d64db582 868
lynxeyed_atsu 0:d920d64db582 869 * @param[in] UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure
lynxeyed_atsu 0:d920d64db582 870 * which will be initialized.
lynxeyed_atsu 0:d920d64db582 871 * @return None
lynxeyed_atsu 0:d920d64db582 872 *******************************************************************************/
lynxeyed_atsu 0:d920d64db582 873 void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct)
lynxeyed_atsu 0:d920d64db582 874 {
lynxeyed_atsu 0:d920d64db582 875 UART_FIFOInitStruct->FIFO_DMAMode = DISABLE;
lynxeyed_atsu 0:d920d64db582 876 UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0;
lynxeyed_atsu 0:d920d64db582 877 UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE;
lynxeyed_atsu 0:d920d64db582 878 UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE;
lynxeyed_atsu 0:d920d64db582 879 }
lynxeyed_atsu 0:d920d64db582 880
lynxeyed_atsu 0:d920d64db582 881
lynxeyed_atsu 0:d920d64db582 882 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 883 * @brief Start/Stop Auto Baudrate activity
lynxeyed_atsu 0:d920d64db582 884 * @param[in] UARTx UART peripheral selected, should be
lynxeyed_atsu 0:d920d64db582 885 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 886 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 887 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 888 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 889 * @param[in] ABConfigStruct A pointer to UART_AB_CFG_Type structure that
lynxeyed_atsu 0:d920d64db582 890 * contains specified information about UART
lynxeyed_atsu 0:d920d64db582 891 * auto baudrate configuration
lynxeyed_atsu 0:d920d64db582 892 * @param[in] NewState New State of Auto baudrate activity, should be:
lynxeyed_atsu 0:d920d64db582 893 * - ENABLE: Start this activity
lynxeyed_atsu 0:d920d64db582 894 * - DISABLE: Stop this activity
lynxeyed_atsu 0:d920d64db582 895 * Note: Auto-baudrate mode enable bit will be cleared once this mode
lynxeyed_atsu 0:d920d64db582 896 * completed.
lynxeyed_atsu 0:d920d64db582 897 * @return none
lynxeyed_atsu 0:d920d64db582 898 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 899 void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
lynxeyed_atsu 0:d920d64db582 900 FunctionalState NewState)
lynxeyed_atsu 0:d920d64db582 901 {
lynxeyed_atsu 0:d920d64db582 902 uint32_t tmp;
lynxeyed_atsu 0:d920d64db582 903
lynxeyed_atsu 0:d920d64db582 904 CHECK_PARAM(PARAM_UARTx(UARTx));
lynxeyed_atsu 0:d920d64db582 905 CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
lynxeyed_atsu 0:d920d64db582 906
lynxeyed_atsu 0:d920d64db582 907 tmp = 0;
lynxeyed_atsu 0:d920d64db582 908 if (NewState == ENABLE) {
lynxeyed_atsu 0:d920d64db582 909 if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1){
lynxeyed_atsu 0:d920d64db582 910 tmp |= UART_ACR_MODE;
lynxeyed_atsu 0:d920d64db582 911 }
lynxeyed_atsu 0:d920d64db582 912 if (ABConfigStruct->AutoRestart == ENABLE){
lynxeyed_atsu 0:d920d64db582 913 tmp |= UART_ACR_AUTO_RESTART;
lynxeyed_atsu 0:d920d64db582 914 }
lynxeyed_atsu 0:d920d64db582 915 }
lynxeyed_atsu 0:d920d64db582 916
lynxeyed_atsu 0:d920d64db582 917 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 918 {
lynxeyed_atsu 0:d920d64db582 919 if (NewState == ENABLE)
lynxeyed_atsu 0:d920d64db582 920 {
lynxeyed_atsu 0:d920d64db582 921 // Clear DLL and DLM value
lynxeyed_atsu 0:d920d64db582 922 ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN;
lynxeyed_atsu 0:d920d64db582 923 ((LPC_UART1_TypeDef *)UARTx)->DLL = 0;
lynxeyed_atsu 0:d920d64db582 924 ((LPC_UART1_TypeDef *)UARTx)->DLM = 0;
lynxeyed_atsu 0:d920d64db582 925 ((LPC_UART1_TypeDef *)UARTx)->LCR &= ~UART_LCR_DLAB_EN;
lynxeyed_atsu 0:d920d64db582 926 // FDR value must be reset to default value
lynxeyed_atsu 0:d920d64db582 927 ((LPC_UART1_TypeDef *)UARTx)->FDR = 0x10;
lynxeyed_atsu 0:d920d64db582 928 ((LPC_UART1_TypeDef *)UARTx)->ACR = UART_ACR_START | tmp;
lynxeyed_atsu 0:d920d64db582 929 }
lynxeyed_atsu 0:d920d64db582 930 else
lynxeyed_atsu 0:d920d64db582 931 {
lynxeyed_atsu 0:d920d64db582 932 ((LPC_UART1_TypeDef *)UARTx)->ACR = 0;
lynxeyed_atsu 0:d920d64db582 933 }
lynxeyed_atsu 0:d920d64db582 934 }
lynxeyed_atsu 0:d920d64db582 935 else
lynxeyed_atsu 0:d920d64db582 936 {
lynxeyed_atsu 0:d920d64db582 937 if (NewState == ENABLE)
lynxeyed_atsu 0:d920d64db582 938 {
lynxeyed_atsu 0:d920d64db582 939 // Clear DLL and DLM value
lynxeyed_atsu 0:d920d64db582 940 UARTx->LCR |= UART_LCR_DLAB_EN;
lynxeyed_atsu 0:d920d64db582 941 UARTx->DLL = 0;
lynxeyed_atsu 0:d920d64db582 942 UARTx->DLM = 0;
lynxeyed_atsu 0:d920d64db582 943 UARTx->LCR &= ~UART_LCR_DLAB_EN;
lynxeyed_atsu 0:d920d64db582 944 // FDR value must be reset to default value
lynxeyed_atsu 0:d920d64db582 945 UARTx->FDR = 0x10;
lynxeyed_atsu 0:d920d64db582 946 UARTx->ACR = UART_ACR_START | tmp;
lynxeyed_atsu 0:d920d64db582 947 }
lynxeyed_atsu 0:d920d64db582 948 else
lynxeyed_atsu 0:d920d64db582 949 {
lynxeyed_atsu 0:d920d64db582 950 UARTx->ACR = 0;
lynxeyed_atsu 0:d920d64db582 951 }
lynxeyed_atsu 0:d920d64db582 952 }
lynxeyed_atsu 0:d920d64db582 953 }
lynxeyed_atsu 0:d920d64db582 954
lynxeyed_atsu 0:d920d64db582 955 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 956 * @brief Clear Autobaud Interrupt Pending
lynxeyed_atsu 0:d920d64db582 957 * @param[in] UARTx UART peripheral selected, should be
lynxeyed_atsu 0:d920d64db582 958 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 959 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 960 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 961 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 962 * @param[in] ABIntType type of auto-baud interrupt, should be:
lynxeyed_atsu 0:d920d64db582 963 * - UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt
lynxeyed_atsu 0:d920d64db582 964 * - UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt
lynxeyed_atsu 0:d920d64db582 965 * @return none
lynxeyed_atsu 0:d920d64db582 966 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 967 void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType)
lynxeyed_atsu 0:d920d64db582 968 {
lynxeyed_atsu 0:d920d64db582 969 CHECK_PARAM(PARAM_UARTx(UARTx));
lynxeyed_atsu 0:d920d64db582 970 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 971 {
lynxeyed_atsu 0:d920d64db582 972 UARTx->ACR |= ABIntType;
lynxeyed_atsu 0:d920d64db582 973 }
lynxeyed_atsu 0:d920d64db582 974 else
lynxeyed_atsu 0:d920d64db582 975 UARTx->ACR |= ABIntType;
lynxeyed_atsu 0:d920d64db582 976 }
lynxeyed_atsu 0:d920d64db582 977
lynxeyed_atsu 0:d920d64db582 978 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 979 * @brief Enable/Disable transmission on UART TxD pin
lynxeyed_atsu 0:d920d64db582 980 * @param[in] UARTx UART peripheral selected, should be:
lynxeyed_atsu 0:d920d64db582 981 * - LPC_UART0: UART0 peripheral
lynxeyed_atsu 0:d920d64db582 982 * - LPC_UART1: UART1 peripheral
lynxeyed_atsu 0:d920d64db582 983 * - LPC_UART2: UART2 peripheral
lynxeyed_atsu 0:d920d64db582 984 * - LPC_UART3: UART3 peripheral
lynxeyed_atsu 0:d920d64db582 985 * @param[in] NewState New State of Tx transmission function, should be:
lynxeyed_atsu 0:d920d64db582 986 * - ENABLE: Enable this function
lynxeyed_atsu 0:d920d64db582 987 - DISABLE: Disable this function
lynxeyed_atsu 0:d920d64db582 988 * @return none
lynxeyed_atsu 0:d920d64db582 989 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 990 void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState)
lynxeyed_atsu 0:d920d64db582 991 {
lynxeyed_atsu 0:d920d64db582 992 CHECK_PARAM(PARAM_UARTx(UARTx));
lynxeyed_atsu 0:d920d64db582 993 CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
lynxeyed_atsu 0:d920d64db582 994
lynxeyed_atsu 0:d920d64db582 995 if (NewState == ENABLE)
lynxeyed_atsu 0:d920d64db582 996 {
lynxeyed_atsu 0:d920d64db582 997 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 998 {
lynxeyed_atsu 0:d920d64db582 999 ((LPC_UART1_TypeDef *)UARTx)->TER |= UART_TER_TXEN;
lynxeyed_atsu 0:d920d64db582 1000 }
lynxeyed_atsu 0:d920d64db582 1001 else
lynxeyed_atsu 0:d920d64db582 1002 {
lynxeyed_atsu 0:d920d64db582 1003 UARTx->TER |= UART_TER_TXEN;
lynxeyed_atsu 0:d920d64db582 1004 }
lynxeyed_atsu 0:d920d64db582 1005 }
lynxeyed_atsu 0:d920d64db582 1006 else
lynxeyed_atsu 0:d920d64db582 1007 {
lynxeyed_atsu 0:d920d64db582 1008 if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
lynxeyed_atsu 0:d920d64db582 1009 {
lynxeyed_atsu 0:d920d64db582 1010 ((LPC_UART1_TypeDef *)UARTx)->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
lynxeyed_atsu 0:d920d64db582 1011 }
lynxeyed_atsu 0:d920d64db582 1012 else
lynxeyed_atsu 0:d920d64db582 1013 {
lynxeyed_atsu 0:d920d64db582 1014 UARTx->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
lynxeyed_atsu 0:d920d64db582 1015 }
lynxeyed_atsu 0:d920d64db582 1016 }
lynxeyed_atsu 0:d920d64db582 1017 }
lynxeyed_atsu 0:d920d64db582 1018
lynxeyed_atsu 0:d920d64db582 1019 /* UART IrDA functions ---------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 1020
lynxeyed_atsu 0:d920d64db582 1021 #ifdef _UART3
lynxeyed_atsu 0:d920d64db582 1022
lynxeyed_atsu 0:d920d64db582 1023 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 1024 * @brief Enable or disable inverting serial input function of IrDA
lynxeyed_atsu 0:d920d64db582 1025 * on UART peripheral.
lynxeyed_atsu 0:d920d64db582 1026 * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only)
lynxeyed_atsu 0:d920d64db582 1027 * @param[in] NewState New state of inverting serial input, should be:
lynxeyed_atsu 0:d920d64db582 1028 * - ENABLE: Enable this function.
lynxeyed_atsu 0:d920d64db582 1029 * - DISABLE: Disable this function.
lynxeyed_atsu 0:d920d64db582 1030 * @return none
lynxeyed_atsu 0:d920d64db582 1031 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 1032 void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
lynxeyed_atsu 0:d920d64db582 1033 {
lynxeyed_atsu 0:d920d64db582 1034 CHECK_PARAM(PARAM_UART_IrDA(UARTx));
lynxeyed_atsu 0:d920d64db582 1035 CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
lynxeyed_atsu 0:d920d64db582 1036
lynxeyed_atsu 0:d920d64db582 1037 if (NewState == ENABLE)
lynxeyed_atsu 0:d920d64db582 1038 {
lynxeyed_atsu 0:d920d64db582 1039 UARTx->ICR |= UART_ICR_IRDAINV;
lynxeyed_atsu 0:d920d64db582 1040 }
lynxeyed_atsu 0:d920d64db582 1041 else if (NewState == DISABLE)
lynxeyed_atsu 0:d920d64db582 1042 {
lynxeyed_atsu 0:d920d64db582 1043 UARTx->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK;
lynxeyed_atsu 0:d920d64db582 1044 }
lynxeyed_atsu 0:d920d64db582 1045 }
lynxeyed_atsu 0:d920d64db582 1046
lynxeyed_atsu 0:d920d64db582 1047
lynxeyed_atsu 0:d920d64db582 1048 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 1049 * @brief Enable or disable IrDA function on UART peripheral.
lynxeyed_atsu 0:d920d64db582 1050 * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only)
lynxeyed_atsu 0:d920d64db582 1051 * @param[in] NewState New state of IrDA function, should be:
lynxeyed_atsu 0:d920d64db582 1052 * - ENABLE: Enable this function.
lynxeyed_atsu 0:d920d64db582 1053 * - DISABLE: Disable this function.
lynxeyed_atsu 0:d920d64db582 1054 * @return none
lynxeyed_atsu 0:d920d64db582 1055 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 1056 void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
lynxeyed_atsu 0:d920d64db582 1057 {
lynxeyed_atsu 0:d920d64db582 1058 CHECK_PARAM(PARAM_UART_IrDA(UARTx));
lynxeyed_atsu 0:d920d64db582 1059 CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
lynxeyed_atsu 0:d920d64db582 1060
lynxeyed_atsu 0:d920d64db582 1061 if (NewState == ENABLE)
lynxeyed_atsu 0:d920d64db582 1062 {
lynxeyed_atsu 0:d920d64db582 1063 UARTx->ICR |= UART_ICR_IRDAEN;
lynxeyed_atsu 0:d920d64db582 1064 }
lynxeyed_atsu 0:d920d64db582 1065 else
lynxeyed_atsu 0:d920d64db582 1066 {
lynxeyed_atsu 0:d920d64db582 1067 UARTx->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK;
lynxeyed_atsu 0:d920d64db582 1068 }
lynxeyed_atsu 0:d920d64db582 1069 }
lynxeyed_atsu 0:d920d64db582 1070
lynxeyed_atsu 0:d920d64db582 1071
lynxeyed_atsu 0:d920d64db582 1072 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 1073 * @brief Configure Pulse divider for IrDA function on UART peripheral.
lynxeyed_atsu 0:d920d64db582 1074 * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only)
lynxeyed_atsu 0:d920d64db582 1075 * @param[in] PulseDiv Pulse Divider value from Peripheral clock,
lynxeyed_atsu 0:d920d64db582 1076 * should be one of the following:
lynxeyed_atsu 0:d920d64db582 1077 - UART_IrDA_PULSEDIV2 : Pulse width = 2 * Tpclk
lynxeyed_atsu 0:d920d64db582 1078 - UART_IrDA_PULSEDIV4 : Pulse width = 4 * Tpclk
lynxeyed_atsu 0:d920d64db582 1079 - UART_IrDA_PULSEDIV8 : Pulse width = 8 * Tpclk
lynxeyed_atsu 0:d920d64db582 1080 - UART_IrDA_PULSEDIV16 : Pulse width = 16 * Tpclk
lynxeyed_atsu 0:d920d64db582 1081 - UART_IrDA_PULSEDIV32 : Pulse width = 32 * Tpclk
lynxeyed_atsu 0:d920d64db582 1082 - UART_IrDA_PULSEDIV64 : Pulse width = 64 * Tpclk
lynxeyed_atsu 0:d920d64db582 1083 - UART_IrDA_PULSEDIV128 : Pulse width = 128 * Tpclk
lynxeyed_atsu 0:d920d64db582 1084 - UART_IrDA_PULSEDIV256 : Pulse width = 256 * Tpclk
lynxeyed_atsu 0:d920d64db582 1085
lynxeyed_atsu 0:d920d64db582 1086 * @return none
lynxeyed_atsu 0:d920d64db582 1087 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 1088 void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv)
lynxeyed_atsu 0:d920d64db582 1089 {
lynxeyed_atsu 0:d920d64db582 1090 uint32_t tmp, tmp1;
lynxeyed_atsu 0:d920d64db582 1091 CHECK_PARAM(PARAM_UART_IrDA(UARTx));
lynxeyed_atsu 0:d920d64db582 1092 CHECK_PARAM(PARAM_UART_IrDA_PULSEDIV(PulseDiv));
lynxeyed_atsu 0:d920d64db582 1093
lynxeyed_atsu 0:d920d64db582 1094 tmp1 = UART_ICR_PULSEDIV(PulseDiv);
lynxeyed_atsu 0:d920d64db582 1095 tmp = UARTx->ICR & (~UART_ICR_PULSEDIV(7));
lynxeyed_atsu 0:d920d64db582 1096 tmp |= tmp1 | UART_ICR_FIXPULSE_EN;
lynxeyed_atsu 0:d920d64db582 1097 UARTx->ICR = tmp & UART_ICR_BITMASK;
lynxeyed_atsu 0:d920d64db582 1098 }
lynxeyed_atsu 0:d920d64db582 1099
lynxeyed_atsu 0:d920d64db582 1100 #endif
lynxeyed_atsu 0:d920d64db582 1101
lynxeyed_atsu 0:d920d64db582 1102
lynxeyed_atsu 0:d920d64db582 1103 /* UART1 FullModem function ---------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 1104
lynxeyed_atsu 0:d920d64db582 1105 #ifdef _UART1
lynxeyed_atsu 0:d920d64db582 1106
lynxeyed_atsu 0:d920d64db582 1107 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 1108 * @brief Force pin DTR/RTS corresponding to given state (Full modem mode)
lynxeyed_atsu 0:d920d64db582 1109 * @param[in] UARTx LPC_UART1 (only)
lynxeyed_atsu 0:d920d64db582 1110 * @param[in] Pin Pin that NewState will be applied to, should be:
lynxeyed_atsu 0:d920d64db582 1111 * - UART1_MODEM_PIN_DTR: DTR pin.
lynxeyed_atsu 0:d920d64db582 1112 * - UART1_MODEM_PIN_RTS: RTS pin.
lynxeyed_atsu 0:d920d64db582 1113 * @param[in] NewState New State of DTR/RTS pin, should be:
lynxeyed_atsu 0:d920d64db582 1114 * - INACTIVE: Force the pin to inactive signal.
lynxeyed_atsu 0:d920d64db582 1115 - ACTIVE: Force the pin to active signal.
lynxeyed_atsu 0:d920d64db582 1116 * @return none
lynxeyed_atsu 0:d920d64db582 1117 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 1118 void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \
lynxeyed_atsu 0:d920d64db582 1119 UART1_SignalState NewState)
lynxeyed_atsu 0:d920d64db582 1120 {
lynxeyed_atsu 0:d920d64db582 1121 uint8_t tmp = 0;
lynxeyed_atsu 0:d920d64db582 1122
lynxeyed_atsu 0:d920d64db582 1123 CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
lynxeyed_atsu 0:d920d64db582 1124 CHECK_PARAM(PARAM_UART1_MODEM_PIN(Pin));
lynxeyed_atsu 0:d920d64db582 1125 CHECK_PARAM(PARAM_UART1_SIGNALSTATE(NewState));
lynxeyed_atsu 0:d920d64db582 1126
lynxeyed_atsu 0:d920d64db582 1127 switch (Pin){
lynxeyed_atsu 0:d920d64db582 1128 case UART1_MODEM_PIN_DTR:
lynxeyed_atsu 0:d920d64db582 1129 tmp = UART1_MCR_DTR_CTRL;
lynxeyed_atsu 0:d920d64db582 1130 break;
lynxeyed_atsu 0:d920d64db582 1131 case UART1_MODEM_PIN_RTS:
lynxeyed_atsu 0:d920d64db582 1132 tmp = UART1_MCR_RTS_CTRL;
lynxeyed_atsu 0:d920d64db582 1133 break;
lynxeyed_atsu 0:d920d64db582 1134 default:
lynxeyed_atsu 0:d920d64db582 1135 break;
lynxeyed_atsu 0:d920d64db582 1136 }
lynxeyed_atsu 0:d920d64db582 1137
lynxeyed_atsu 0:d920d64db582 1138 if (NewState == ACTIVE){
lynxeyed_atsu 0:d920d64db582 1139 UARTx->MCR |= tmp;
lynxeyed_atsu 0:d920d64db582 1140 } else {
lynxeyed_atsu 0:d920d64db582 1141 UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
lynxeyed_atsu 0:d920d64db582 1142 }
lynxeyed_atsu 0:d920d64db582 1143 }
lynxeyed_atsu 0:d920d64db582 1144
lynxeyed_atsu 0:d920d64db582 1145
lynxeyed_atsu 0:d920d64db582 1146 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 1147 * @brief Configure Full Modem mode for UART peripheral
lynxeyed_atsu 0:d920d64db582 1148 * @param[in] UARTx LPC_UART1 (only)
lynxeyed_atsu 0:d920d64db582 1149 * @param[in] Mode Full Modem mode, should be:
lynxeyed_atsu 0:d920d64db582 1150 * - UART1_MODEM_MODE_LOOPBACK: Loop back mode.
lynxeyed_atsu 0:d920d64db582 1151 * - UART1_MODEM_MODE_AUTO_RTS: Auto-RTS mode.
lynxeyed_atsu 0:d920d64db582 1152 * - UART1_MODEM_MODE_AUTO_CTS: Auto-CTS mode.
lynxeyed_atsu 0:d920d64db582 1153 * @param[in] NewState New State of this mode, should be:
lynxeyed_atsu 0:d920d64db582 1154 * - ENABLE: Enable this mode.
lynxeyed_atsu 0:d920d64db582 1155 - DISABLE: Disable this mode.
lynxeyed_atsu 0:d920d64db582 1156 * @return none
lynxeyed_atsu 0:d920d64db582 1157 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 1158 void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \
lynxeyed_atsu 0:d920d64db582 1159 FunctionalState NewState)
lynxeyed_atsu 0:d920d64db582 1160 {
lynxeyed_atsu 0:d920d64db582 1161 uint8_t tmp = 0;
lynxeyed_atsu 0:d920d64db582 1162
lynxeyed_atsu 0:d920d64db582 1163 CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
lynxeyed_atsu 0:d920d64db582 1164 CHECK_PARAM(PARAM_UART1_MODEM_MODE(Mode));
lynxeyed_atsu 0:d920d64db582 1165 CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
lynxeyed_atsu 0:d920d64db582 1166
lynxeyed_atsu 0:d920d64db582 1167 switch(Mode){
lynxeyed_atsu 0:d920d64db582 1168 case UART1_MODEM_MODE_LOOPBACK:
lynxeyed_atsu 0:d920d64db582 1169 tmp = UART1_MCR_LOOPB_EN;
lynxeyed_atsu 0:d920d64db582 1170 break;
lynxeyed_atsu 0:d920d64db582 1171 case UART1_MODEM_MODE_AUTO_RTS:
lynxeyed_atsu 0:d920d64db582 1172 tmp = UART1_MCR_AUTO_RTS_EN;
lynxeyed_atsu 0:d920d64db582 1173 break;
lynxeyed_atsu 0:d920d64db582 1174 case UART1_MODEM_MODE_AUTO_CTS:
lynxeyed_atsu 0:d920d64db582 1175 tmp = UART1_MCR_AUTO_CTS_EN;
lynxeyed_atsu 0:d920d64db582 1176 break;
lynxeyed_atsu 0:d920d64db582 1177 default:
lynxeyed_atsu 0:d920d64db582 1178 break;
lynxeyed_atsu 0:d920d64db582 1179 }
lynxeyed_atsu 0:d920d64db582 1180
lynxeyed_atsu 0:d920d64db582 1181 if (NewState == ENABLE)
lynxeyed_atsu 0:d920d64db582 1182 {
lynxeyed_atsu 0:d920d64db582 1183 UARTx->MCR |= tmp;
lynxeyed_atsu 0:d920d64db582 1184 }
lynxeyed_atsu 0:d920d64db582 1185 else
lynxeyed_atsu 0:d920d64db582 1186 {
lynxeyed_atsu 0:d920d64db582 1187 UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
lynxeyed_atsu 0:d920d64db582 1188 }
lynxeyed_atsu 0:d920d64db582 1189 }
lynxeyed_atsu 0:d920d64db582 1190
lynxeyed_atsu 0:d920d64db582 1191
lynxeyed_atsu 0:d920d64db582 1192 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 1193 * @brief Get current status of modem status register
lynxeyed_atsu 0:d920d64db582 1194 * @param[in] UARTx LPC_UART1 (only)
lynxeyed_atsu 0:d920d64db582 1195 * @return Current value of modem status register
lynxeyed_atsu 0:d920d64db582 1196 * Note: The return value of this function must be ANDed with each member
lynxeyed_atsu 0:d920d64db582 1197 * UART_MODEM_STAT_type enumeration to determine current flag status
lynxeyed_atsu 0:d920d64db582 1198 * corresponding to each modem flag status. Because some flags in
lynxeyed_atsu 0:d920d64db582 1199 * modem status register will be cleared after reading, the next reading
lynxeyed_atsu 0:d920d64db582 1200 * modem register could not be correct. So this function used to
lynxeyed_atsu 0:d920d64db582 1201 * read modem status register in one time only, then the return value
lynxeyed_atsu 0:d920d64db582 1202 * used to check all flags.
lynxeyed_atsu 0:d920d64db582 1203 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 1204 uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx)
lynxeyed_atsu 0:d920d64db582 1205 {
lynxeyed_atsu 0:d920d64db582 1206 CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
lynxeyed_atsu 0:d920d64db582 1207 return ((UARTx->MSR) & UART1_MSR_BITMASK);
lynxeyed_atsu 0:d920d64db582 1208 }
lynxeyed_atsu 0:d920d64db582 1209
lynxeyed_atsu 0:d920d64db582 1210
lynxeyed_atsu 0:d920d64db582 1211 /* UART RS485 functions --------------------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 1212
lynxeyed_atsu 0:d920d64db582 1213 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 1214 * @brief Configure UART peripheral in RS485 mode according to the specified
lynxeyed_atsu 0:d920d64db582 1215 * parameters in the RS485ConfigStruct.
lynxeyed_atsu 0:d920d64db582 1216 * @param[in] UARTx LPC_UART1 (only)
lynxeyed_atsu 0:d920d64db582 1217 * @param[in] RS485ConfigStruct Pointer to a UART1_RS485_CTRLCFG_Type structure
lynxeyed_atsu 0:d920d64db582 1218 * that contains the configuration information for specified UART
lynxeyed_atsu 0:d920d64db582 1219 * in RS485 mode.
lynxeyed_atsu 0:d920d64db582 1220 * @return None
lynxeyed_atsu 0:d920d64db582 1221 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 1222 void UART_RS485Config(LPC_UART1_TypeDef *UARTx, UART1_RS485_CTRLCFG_Type *RS485ConfigStruct)
lynxeyed_atsu 0:d920d64db582 1223 {
lynxeyed_atsu 0:d920d64db582 1224 uint32_t tmp;
lynxeyed_atsu 0:d920d64db582 1225
lynxeyed_atsu 0:d920d64db582 1226 CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
lynxeyed_atsu 0:d920d64db582 1227 CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoAddrDetect_State));
lynxeyed_atsu 0:d920d64db582 1228 CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoDirCtrl_State));
lynxeyed_atsu 0:d920d64db582 1229 CHECK_PARAM(PARAM_UART1_RS485_CFG_DELAYVALUE(RS485ConfigStruct->DelayValue));
lynxeyed_atsu 0:d920d64db582 1230 CHECK_PARAM(PARAM_SETSTATE(RS485ConfigStruct->DirCtrlPol_Level));
lynxeyed_atsu 0:d920d64db582 1231 CHECK_PARAM(PARAM_UART_RS485_DIRCTRL_PIN(RS485ConfigStruct->DirCtrlPin));
lynxeyed_atsu 0:d920d64db582 1232 CHECK_PARAM(PARAM_UART1_RS485_CFG_MATCHADDRVALUE(RS485ConfigStruct->MatchAddrValue));
lynxeyed_atsu 0:d920d64db582 1233 CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->NormalMultiDropMode_State));
lynxeyed_atsu 0:d920d64db582 1234 CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->Rx_State));
lynxeyed_atsu 0:d920d64db582 1235
lynxeyed_atsu 0:d920d64db582 1236 tmp = 0;
lynxeyed_atsu 0:d920d64db582 1237 // If Auto Direction Control is enabled - This function is used in Master mode
lynxeyed_atsu 0:d920d64db582 1238 if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE)
lynxeyed_atsu 0:d920d64db582 1239 {
lynxeyed_atsu 0:d920d64db582 1240 tmp |= UART1_RS485CTRL_DCTRL_EN;
lynxeyed_atsu 0:d920d64db582 1241
lynxeyed_atsu 0:d920d64db582 1242 // Set polar
lynxeyed_atsu 0:d920d64db582 1243 if (RS485ConfigStruct->DirCtrlPol_Level == SET)
lynxeyed_atsu 0:d920d64db582 1244 {
lynxeyed_atsu 0:d920d64db582 1245 tmp |= UART1_RS485CTRL_OINV_1;
lynxeyed_atsu 0:d920d64db582 1246 }
lynxeyed_atsu 0:d920d64db582 1247
lynxeyed_atsu 0:d920d64db582 1248 // Set pin according to
lynxeyed_atsu 0:d920d64db582 1249 if (RS485ConfigStruct->DirCtrlPin == UART1_RS485_DIRCTRL_DTR)
lynxeyed_atsu 0:d920d64db582 1250 {
lynxeyed_atsu 0:d920d64db582 1251 tmp |= UART1_RS485CTRL_SEL_DTR;
lynxeyed_atsu 0:d920d64db582 1252 }
lynxeyed_atsu 0:d920d64db582 1253
lynxeyed_atsu 0:d920d64db582 1254 // Fill delay time
lynxeyed_atsu 0:d920d64db582 1255 UARTx->RS485DLY = RS485ConfigStruct->DelayValue & UART1_RS485DLY_BITMASK;
lynxeyed_atsu 0:d920d64db582 1256 }
lynxeyed_atsu 0:d920d64db582 1257
lynxeyed_atsu 0:d920d64db582 1258 // MultiDrop mode is enable
lynxeyed_atsu 0:d920d64db582 1259 if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE)
lynxeyed_atsu 0:d920d64db582 1260 {
lynxeyed_atsu 0:d920d64db582 1261 tmp |= UART1_RS485CTRL_NMM_EN;
lynxeyed_atsu 0:d920d64db582 1262 }
lynxeyed_atsu 0:d920d64db582 1263
lynxeyed_atsu 0:d920d64db582 1264 // Auto Address Detect function
lynxeyed_atsu 0:d920d64db582 1265 if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE)
lynxeyed_atsu 0:d920d64db582 1266 {
lynxeyed_atsu 0:d920d64db582 1267 tmp |= UART1_RS485CTRL_AADEN;
lynxeyed_atsu 0:d920d64db582 1268 // Fill Match Address
lynxeyed_atsu 0:d920d64db582 1269 UARTx->ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART1_RS485ADRMATCH_BITMASK;
lynxeyed_atsu 0:d920d64db582 1270 }
lynxeyed_atsu 0:d920d64db582 1271
lynxeyed_atsu 0:d920d64db582 1272
lynxeyed_atsu 0:d920d64db582 1273 // Receiver is disable
lynxeyed_atsu 0:d920d64db582 1274 if (RS485ConfigStruct->Rx_State == DISABLE)
lynxeyed_atsu 0:d920d64db582 1275 {
lynxeyed_atsu 0:d920d64db582 1276 tmp |= UART1_RS485CTRL_RX_DIS;
lynxeyed_atsu 0:d920d64db582 1277 }
lynxeyed_atsu 0:d920d64db582 1278
lynxeyed_atsu 0:d920d64db582 1279 // write back to RS485 control register
lynxeyed_atsu 0:d920d64db582 1280 UARTx->RS485CTRL = tmp & UART1_RS485CTRL_BITMASK;
lynxeyed_atsu 0:d920d64db582 1281
lynxeyed_atsu 0:d920d64db582 1282 // Enable Parity function and leave parity in stick '0' parity as default
lynxeyed_atsu 0:d920d64db582 1283 UARTx->LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN);
lynxeyed_atsu 0:d920d64db582 1284 }
lynxeyed_atsu 0:d920d64db582 1285
lynxeyed_atsu 0:d920d64db582 1286 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 1287 * @brief Enable/Disable receiver in RS485 module in UART1
lynxeyed_atsu 0:d920d64db582 1288 * @param[in] UARTx LPC_UART1 (only)
lynxeyed_atsu 0:d920d64db582 1289 * @param[in] NewState New State of command, should be:
lynxeyed_atsu 0:d920d64db582 1290 * - ENABLE: Enable this function.
lynxeyed_atsu 0:d920d64db582 1291 * - DISABLE: Disable this function.
lynxeyed_atsu 0:d920d64db582 1292 * @return None
lynxeyed_atsu 0:d920d64db582 1293 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 1294 void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState)
lynxeyed_atsu 0:d920d64db582 1295 {
lynxeyed_atsu 0:d920d64db582 1296 if (NewState == ENABLE){
lynxeyed_atsu 0:d920d64db582 1297 UARTx->RS485CTRL &= ~UART1_RS485CTRL_RX_DIS;
lynxeyed_atsu 0:d920d64db582 1298 } else {
lynxeyed_atsu 0:d920d64db582 1299 UARTx->RS485CTRL |= UART1_RS485CTRL_RX_DIS;
lynxeyed_atsu 0:d920d64db582 1300 }
lynxeyed_atsu 0:d920d64db582 1301 }
lynxeyed_atsu 0:d920d64db582 1302
lynxeyed_atsu 0:d920d64db582 1303 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 1304 * @brief Send data on RS485 bus with specified parity stick value (9-bit mode).
lynxeyed_atsu 0:d920d64db582 1305 * @param[in] UARTx LPC_UART1 (only)
lynxeyed_atsu 0:d920d64db582 1306 * @param[in] pDatFrm Pointer to data frame.
lynxeyed_atsu 0:d920d64db582 1307 * @param[in] size Size of data.
lynxeyed_atsu 0:d920d64db582 1308 * @param[in] ParityStick Parity Stick value, should be 0 or 1.
lynxeyed_atsu 0:d920d64db582 1309 * @return None
lynxeyed_atsu 0:d920d64db582 1310 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 1311 uint32_t UART_RS485Send(LPC_UART1_TypeDef *UARTx, uint8_t *pDatFrm, \
lynxeyed_atsu 0:d920d64db582 1312 uint32_t size, uint8_t ParityStick)
lynxeyed_atsu 0:d920d64db582 1313 {
lynxeyed_atsu 0:d920d64db582 1314 uint8_t tmp, save;
lynxeyed_atsu 0:d920d64db582 1315 uint32_t cnt;
lynxeyed_atsu 0:d920d64db582 1316
lynxeyed_atsu 0:d920d64db582 1317 if (ParityStick){
lynxeyed_atsu 0:d920d64db582 1318 save = tmp = UARTx->LCR & UART_LCR_BITMASK;
lynxeyed_atsu 0:d920d64db582 1319 tmp &= ~(UART_LCR_PARITY_EVEN);
lynxeyed_atsu 0:d920d64db582 1320 UARTx->LCR = tmp;
lynxeyed_atsu 0:d920d64db582 1321 cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
lynxeyed_atsu 0:d920d64db582 1322 while (!(UARTx->LSR & UART_LSR_TEMT));
lynxeyed_atsu 0:d920d64db582 1323 UARTx->LCR = save;
lynxeyed_atsu 0:d920d64db582 1324 } else {
lynxeyed_atsu 0:d920d64db582 1325 cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
lynxeyed_atsu 0:d920d64db582 1326 while (!(UARTx->LSR & UART_LSR_TEMT));
lynxeyed_atsu 0:d920d64db582 1327 }
lynxeyed_atsu 0:d920d64db582 1328 return cnt;
lynxeyed_atsu 0:d920d64db582 1329 }
lynxeyed_atsu 0:d920d64db582 1330
lynxeyed_atsu 0:d920d64db582 1331 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 1332 * @brief Send Slave address frames on RS485 bus.
lynxeyed_atsu 0:d920d64db582 1333 * @param[in] UARTx LPC_UART1 (only)
lynxeyed_atsu 0:d920d64db582 1334 * @param[in] SlvAddr Slave Address.
lynxeyed_atsu 0:d920d64db582 1335 * @return None
lynxeyed_atsu 0:d920d64db582 1336 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 1337 void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr)
lynxeyed_atsu 0:d920d64db582 1338 {
lynxeyed_atsu 0:d920d64db582 1339 UART_RS485Send(UARTx, &SlvAddr, 1, 1);
lynxeyed_atsu 0:d920d64db582 1340 }
lynxeyed_atsu 0:d920d64db582 1341
lynxeyed_atsu 0:d920d64db582 1342 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 1343 * @brief Send Data frames on RS485 bus.
lynxeyed_atsu 0:d920d64db582 1344 * @param[in] UARTx LPC_UART1 (only)
lynxeyed_atsu 0:d920d64db582 1345 * @param[in] pData Pointer to data to be sent.
lynxeyed_atsu 0:d920d64db582 1346 * @param[in] size Size of data frame to be sent.
lynxeyed_atsu 0:d920d64db582 1347 * @return None
lynxeyed_atsu 0:d920d64db582 1348 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 1349 uint32_t UART_RS485SendData(LPC_UART1_TypeDef *UARTx, uint8_t *pData, uint32_t size)
lynxeyed_atsu 0:d920d64db582 1350 {
lynxeyed_atsu 0:d920d64db582 1351 return (UART_RS485Send(UARTx, pData, size, 0));
lynxeyed_atsu 0:d920d64db582 1352 }
lynxeyed_atsu 0:d920d64db582 1353
lynxeyed_atsu 0:d920d64db582 1354 #endif /* _UART1 */
lynxeyed_atsu 0:d920d64db582 1355
lynxeyed_atsu 0:d920d64db582 1356 #endif /* _UART */
lynxeyed_atsu 0:d920d64db582 1357
lynxeyed_atsu 0:d920d64db582 1358 /**
lynxeyed_atsu 0:d920d64db582 1359 * @}
lynxeyed_atsu 0:d920d64db582 1360 */
lynxeyed_atsu 0:d920d64db582 1361
lynxeyed_atsu 0:d920d64db582 1362 /**
lynxeyed_atsu 0:d920d64db582 1363 * @}
lynxeyed_atsu 0:d920d64db582 1364 */
lynxeyed_atsu 0:d920d64db582 1365 /* --------------------------------- End Of File ------------------------------ */
lynxeyed_atsu 0:d920d64db582 1366