I2S_AIC23B_RiceGolomb - パラメータを適応変化させる事により圧縮率を向上させた動的ライス・ゴロム符号を利用した可逆圧縮方式。…

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xeye_ atsu / Mbed 2 deprecated I2S_AIC23B_RiceGolomb

パラメータを適応変化させる事により圧縮率を向上させた動的ライス・ゴロム符号を利用した可逆圧縮方式。圧縮ソフト、圧縮率のMATLABシミュレーションは詳細はInterface誌2011年8月号に掲載されるRX62Nマイコン連動特集にて掲載予定。

Dependencies: mbed

I2S_Example/core_cm3.h@0:d920d64db582, 2011-03-30 (annotated)

Committer:: lynxeyed_atsu
Date:: Wed Mar 30 06:05:24 2011 +0000
Revision:: 0:d920d64db582

alpha

Who changed what in which revision?

User	Revision	Line number	New contents of line
lynxeyed_atsu	0:d920d64db582	1	/************************************************************************//
lynxeyed_atsu	0:d920d64db582	2	* @file core_cm3.h
lynxeyed_atsu	0:d920d64db582	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
lynxeyed_atsu	0:d920d64db582	4	* @version V1.30
lynxeyed_atsu	0:d920d64db582	5	* @date 30. October 2009
lynxeyed_atsu	0:d920d64db582	6	*
lynxeyed_atsu	0:d920d64db582	7	* @note
lynxeyed_atsu	0:d920d64db582	8	* Copyright (C) 2009 ARM Limited. All rights reserved.
lynxeyed_atsu	0:d920d64db582	9	*
lynxeyed_atsu	0:d920d64db582	10	* @par
lynxeyed_atsu	0:d920d64db582	11	* ARM Limited (ARM) is supplying this software for use with Cortex-M
lynxeyed_atsu	0:d920d64db582	12	* processor based microcontrollers. This file can be freely distributed
lynxeyed_atsu	0:d920d64db582	13	* within development tools that are supporting such ARM based processors.
lynxeyed_atsu	0:d920d64db582	14	*
lynxeyed_atsu	0:d920d64db582	15	* @par
lynxeyed_atsu	0:d920d64db582	16	* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
lynxeyed_atsu	0:d920d64db582	17	* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
lynxeyed_atsu	0:d920d64db582	18	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
lynxeyed_atsu	0:d920d64db582	19	* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
lynxeyed_atsu	0:d920d64db582	20	* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
lynxeyed_atsu	0:d920d64db582	21	*
lynxeyed_atsu	0:d920d64db582	22	******************************************************************************/
lynxeyed_atsu	0:d920d64db582	23
lynxeyed_atsu	0:d920d64db582	24	#ifndef __CM3_CORE_H__
lynxeyed_atsu	0:d920d64db582	25	#define __CM3_CORE_H__
lynxeyed_atsu	0:d920d64db582	26
lynxeyed_atsu	0:d920d64db582	27	/** @addtogroup CMSIS
lynxeyed_atsu	0:d920d64db582	28	* @{
lynxeyed_atsu	0:d920d64db582	29	*/
lynxeyed_atsu	0:d920d64db582	30
lynxeyed_atsu	0:d920d64db582	31	/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
lynxeyed_atsu	0:d920d64db582	32	*
lynxeyed_atsu	0:d920d64db582	33	* List of Lint messages which will be suppressed and not shown:
lynxeyed_atsu	0:d920d64db582	34	* - Error 10: \n
lynxeyed_atsu	0:d920d64db582	35	* register uint32_t __regBasePri __asm("basepri"); \n
lynxeyed_atsu	0:d920d64db582	36	* Error 10: Expecting ';'
lynxeyed_atsu	0:d920d64db582	37	* .
lynxeyed_atsu	0:d920d64db582	38	* - Error 530: \n
lynxeyed_atsu	0:d920d64db582	39	* return(__regBasePri); \n
lynxeyed_atsu	0:d920d64db582	40	* Warning 530: Symbol '__regBasePri' (line 264) not initialized
lynxeyed_atsu	0:d920d64db582	41	* .
lynxeyed_atsu	0:d920d64db582	42	* - Error 550: \n
lynxeyed_atsu	0:d920d64db582	43	* __regBasePri = (basePri & 0x1ff); \n
lynxeyed_atsu	0:d920d64db582	44	* Warning 550: Symbol '__regBasePri' (line 271) not accessed
lynxeyed_atsu	0:d920d64db582	45	* .
lynxeyed_atsu	0:d920d64db582	46	* - Error 754: \n
lynxeyed_atsu	0:d920d64db582	47	* uint32_t RESERVED0[24]; \n
lynxeyed_atsu	0:d920d64db582	48	* Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
lynxeyed_atsu	0:d920d64db582	49	* .
lynxeyed_atsu	0:d920d64db582	50	* - Error 750: \n
lynxeyed_atsu	0:d920d64db582	51	* #define __CM3_CORE_H__ \n
lynxeyed_atsu	0:d920d64db582	52	* Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
lynxeyed_atsu	0:d920d64db582	53	* .
lynxeyed_atsu	0:d920d64db582	54	* - Error 528: \n
lynxeyed_atsu	0:d920d64db582	55	* static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
lynxeyed_atsu	0:d920d64db582	56	* Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
lynxeyed_atsu	0:d920d64db582	57	* .
lynxeyed_atsu	0:d920d64db582	58	* - Error 751: \n
lynxeyed_atsu	0:d920d64db582	59	* } InterruptType_Type; \n
lynxeyed_atsu	0:d920d64db582	60	* Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
lynxeyed_atsu	0:d920d64db582	61	* .
lynxeyed_atsu	0:d920d64db582	62	* Note: To re-enable a Message, insert a space before 'lint' *
lynxeyed_atsu	0:d920d64db582	63	*
lynxeyed_atsu	0:d920d64db582	64	*/
lynxeyed_atsu	0:d920d64db582	65
lynxeyed_atsu	0:d920d64db582	66	/lint -save /
lynxeyed_atsu	0:d920d64db582	67	/lint -e10 /
lynxeyed_atsu	0:d920d64db582	68	/lint -e530 /
lynxeyed_atsu	0:d920d64db582	69	/lint -e550 /
lynxeyed_atsu	0:d920d64db582	70	/lint -e754 /
lynxeyed_atsu	0:d920d64db582	71	/lint -e750 /
lynxeyed_atsu	0:d920d64db582	72	/lint -e528 /
lynxeyed_atsu	0:d920d64db582	73	/lint -e751 /
lynxeyed_atsu	0:d920d64db582	74
lynxeyed_atsu	0:d920d64db582	75
lynxeyed_atsu	0:d920d64db582	76	/** @addtogroup CMSIS_CM3_core_definitions CMSIS CM3 Core Definitions
lynxeyed_atsu	0:d920d64db582	77	This file defines all structures and symbols for CMSIS core:
lynxeyed_atsu	0:d920d64db582	78	- CMSIS version number
lynxeyed_atsu	0:d920d64db582	79	- Cortex-M core registers and bitfields
lynxeyed_atsu	0:d920d64db582	80	- Cortex-M core peripheral base address
lynxeyed_atsu	0:d920d64db582	81	@{
lynxeyed_atsu	0:d920d64db582	82	*/
lynxeyed_atsu	0:d920d64db582	83
lynxeyed_atsu	0:d920d64db582	84	#ifdef __cplusplus
lynxeyed_atsu	0:d920d64db582	85	extern "C" {
lynxeyed_atsu	0:d920d64db582	86	#endif
lynxeyed_atsu	0:d920d64db582	87
lynxeyed_atsu	0:d920d64db582	88	#define __CM3_CMSIS_VERSION_MAIN (0x01) /!< [31:16] CMSIS HAL main version /
lynxeyed_atsu	0:d920d64db582	89	#define __CM3_CMSIS_VERSION_SUB (0x30) /!< [15:0] CMSIS HAL sub version /
lynxeyed_atsu	0:d920d64db582	90	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| __CM3_CMSIS_VERSION_SUB) /!< CMSIS HAL version number /
lynxeyed_atsu	0:d920d64db582	91
lynxeyed_atsu	0:d920d64db582	92	#define __CORTEX_M (0x03) /!< Cortex core /
lynxeyed_atsu	0:d920d64db582	93
lynxeyed_atsu	0:d920d64db582	94	#include <stdint.h> /* Include standard types */
lynxeyed_atsu	0:d920d64db582	95
lynxeyed_atsu	0:d920d64db582	96	#if defined (__ICCARM__)
lynxeyed_atsu	0:d920d64db582	97	#include <intrinsics.h> /* IAR Intrinsics */
lynxeyed_atsu	0:d920d64db582	98	#endif
lynxeyed_atsu	0:d920d64db582	99
lynxeyed_atsu	0:d920d64db582	100
lynxeyed_atsu	0:d920d64db582	101	#ifndef __NVIC_PRIO_BITS
lynxeyed_atsu	0:d920d64db582	102	#define __NVIC_PRIO_BITS 4 /!< standard definition for NVIC Priority Bits /
lynxeyed_atsu	0:d920d64db582	103	#endif
lynxeyed_atsu	0:d920d64db582	104
lynxeyed_atsu	0:d920d64db582	105
lynxeyed_atsu	0:d920d64db582	106
lynxeyed_atsu	0:d920d64db582	107
lynxeyed_atsu	0:d920d64db582	108	/**
lynxeyed_atsu	0:d920d64db582	109	* IO definitions
lynxeyed_atsu	0:d920d64db582	110	*
lynxeyed_atsu	0:d920d64db582	111	* define access restrictions to peripheral registers
lynxeyed_atsu	0:d920d64db582	112	*/
lynxeyed_atsu	0:d920d64db582	113
lynxeyed_atsu	0:d920d64db582	114	#ifdef __cplusplus
lynxeyed_atsu	0:d920d64db582	115	#define __I volatile /!< defines 'read only' permissions /
lynxeyed_atsu	0:d920d64db582	116	#else
lynxeyed_atsu	0:d920d64db582	117	#define __I volatile const /!< defines 'read only' permissions /
lynxeyed_atsu	0:d920d64db582	118	#endif
lynxeyed_atsu	0:d920d64db582	119	#define __O volatile /!< defines 'write only' permissions /
lynxeyed_atsu	0:d920d64db582	120	#define __IO volatile /!< defines 'read / write' permissions /
lynxeyed_atsu	0:d920d64db582	121
lynxeyed_atsu	0:d920d64db582	122
lynxeyed_atsu	0:d920d64db582	123
lynxeyed_atsu	0:d920d64db582	124	/*******************************************************************************
lynxeyed_atsu	0:d920d64db582	125	* Register Abstraction
lynxeyed_atsu	0:d920d64db582	126	******************************************************************************/
lynxeyed_atsu	0:d920d64db582	127	/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
lynxeyed_atsu	0:d920d64db582	128	@{
lynxeyed_atsu	0:d920d64db582	129	*/
lynxeyed_atsu	0:d920d64db582	130
lynxeyed_atsu	0:d920d64db582	131
lynxeyed_atsu	0:d920d64db582	132	/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
lynxeyed_atsu	0:d920d64db582	133	memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
lynxeyed_atsu	0:d920d64db582	134	@{
lynxeyed_atsu	0:d920d64db582	135	*/
lynxeyed_atsu	0:d920d64db582	136	/** @brief Nested Vectored Interrupt Controller (NVIC) register structure definition */
lynxeyed_atsu	0:d920d64db582	137	typedef struct
lynxeyed_atsu	0:d920d64db582	138	{
lynxeyed_atsu	0:d920d64db582	139	__IO uint32_t ISER[8]; /!< Offset: 0x000 Interrupt Set Enable Register /
lynxeyed_atsu	0:d920d64db582	140	uint32_t RESERVED0[24];
lynxeyed_atsu	0:d920d64db582	141	__IO uint32_t ICER[8]; /!< Offset: 0x080 Interrupt Clear Enable Register /
lynxeyed_atsu	0:d920d64db582	142	uint32_t RSERVED1[24];
lynxeyed_atsu	0:d920d64db582	143	__IO uint32_t ISPR[8]; /!< Offset: 0x100 Interrupt Set Pending Register /
lynxeyed_atsu	0:d920d64db582	144	uint32_t RESERVED2[24];
lynxeyed_atsu	0:d920d64db582	145	__IO uint32_t ICPR[8]; /!< Offset: 0x180 Interrupt Clear Pending Register /
lynxeyed_atsu	0:d920d64db582	146	uint32_t RESERVED3[24];
lynxeyed_atsu	0:d920d64db582	147	__IO uint32_t IABR[8]; /!< Offset: 0x200 Interrupt Active bit Register /
lynxeyed_atsu	0:d920d64db582	148	uint32_t RESERVED4[56];
lynxeyed_atsu	0:d920d64db582	149	__IO uint8_t IP[240]; /!< Offset: 0x300 Interrupt Priority Register (8Bit wide) /
lynxeyed_atsu	0:d920d64db582	150	uint32_t RESERVED5[644];
lynxeyed_atsu	0:d920d64db582	151	__O uint32_t STIR; /!< Offset: 0xE00 Software Trigger Interrupt Register /
lynxeyed_atsu	0:d920d64db582	152	} NVIC_Type;
lynxeyed_atsu	0:d920d64db582	153	/@}/ /* end of group CMSIS_CM3_NVIC */
lynxeyed_atsu	0:d920d64db582	154
lynxeyed_atsu	0:d920d64db582	155
lynxeyed_atsu	0:d920d64db582	156	/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
lynxeyed_atsu	0:d920d64db582	157	memory mapped structure for System Control Block (SCB)
lynxeyed_atsu	0:d920d64db582	158	@{
lynxeyed_atsu	0:d920d64db582	159	*/
lynxeyed_atsu	0:d920d64db582	160	/** @brief System Control Block (SCB) register structure definition */
lynxeyed_atsu	0:d920d64db582	161	typedef struct
lynxeyed_atsu	0:d920d64db582	162	{
lynxeyed_atsu	0:d920d64db582	163	__I uint32_t CPUID; /!< Offset: 0x00 CPU ID Base Register /
lynxeyed_atsu	0:d920d64db582	164	__IO uint32_t ICSR; /!< Offset: 0x04 Interrupt Control State Register /
lynxeyed_atsu	0:d920d64db582	165	__IO uint32_t VTOR; /!< Offset: 0x08 Vector Table Offset Register /
lynxeyed_atsu	0:d920d64db582	166	__IO uint32_t AIRCR; /!< Offset: 0x0C Application Interrupt / Reset Control Register /
lynxeyed_atsu	0:d920d64db582	167	__IO uint32_t SCR; /!< Offset: 0x10 System Control Register /
lynxeyed_atsu	0:d920d64db582	168	__IO uint32_t CCR; /!< Offset: 0x14 Configuration Control Register /
lynxeyed_atsu	0:d920d64db582	169	__IO uint8_t SHP[12]; /!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) /
lynxeyed_atsu	0:d920d64db582	170	__IO uint32_t SHCSR; /!< Offset: 0x24 System Handler Control and State Register /
lynxeyed_atsu	0:d920d64db582	171	__IO uint32_t CFSR; /!< Offset: 0x28 Configurable Fault Status Register /
lynxeyed_atsu	0:d920d64db582	172	__IO uint32_t HFSR; /!< Offset: 0x2C Hard Fault Status Register /
lynxeyed_atsu	0:d920d64db582	173	__IO uint32_t DFSR; /!< Offset: 0x30 Debug Fault Status Register /
lynxeyed_atsu	0:d920d64db582	174	__IO uint32_t MMFAR; /!< Offset: 0x34 Mem Manage Address Register /
lynxeyed_atsu	0:d920d64db582	175	__IO uint32_t BFAR; /!< Offset: 0x38 Bus Fault Address Register /
lynxeyed_atsu	0:d920d64db582	176	__IO uint32_t AFSR; /!< Offset: 0x3C Auxiliary Fault Status Register /
lynxeyed_atsu	0:d920d64db582	177	__I uint32_t PFR[2]; /!< Offset: 0x40 Processor Feature Register /
lynxeyed_atsu	0:d920d64db582	178	__I uint32_t DFR; /!< Offset: 0x48 Debug Feature Register /
lynxeyed_atsu	0:d920d64db582	179	__I uint32_t ADR; /!< Offset: 0x4C Auxiliary Feature Register /
lynxeyed_atsu	0:d920d64db582	180	__I uint32_t MMFR[4]; /!< Offset: 0x50 Memory Model Feature Register /
lynxeyed_atsu	0:d920d64db582	181	__I uint32_t ISAR[5]; /!< Offset: 0x60 ISA Feature Register /
lynxeyed_atsu	0:d920d64db582	182	} SCB_Type;
lynxeyed_atsu	0:d920d64db582	183
lynxeyed_atsu	0:d920d64db582	184	/* SCB CPUID Register Definitions */
lynxeyed_atsu	0:d920d64db582	185	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
lynxeyed_atsu	0:d920d64db582	186	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
lynxeyed_atsu	0:d920d64db582	187
lynxeyed_atsu	0:d920d64db582	188	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
lynxeyed_atsu	0:d920d64db582	189	#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
lynxeyed_atsu	0:d920d64db582	190
lynxeyed_atsu	0:d920d64db582	191	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
lynxeyed_atsu	0:d920d64db582	192	#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
lynxeyed_atsu	0:d920d64db582	193
lynxeyed_atsu	0:d920d64db582	194	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
lynxeyed_atsu	0:d920d64db582	195	#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
lynxeyed_atsu	0:d920d64db582	196
lynxeyed_atsu	0:d920d64db582	197	/* SCB Interrupt Control State Register Definitions */
lynxeyed_atsu	0:d920d64db582	198	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
lynxeyed_atsu	0:d920d64db582	199	#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
lynxeyed_atsu	0:d920d64db582	200
lynxeyed_atsu	0:d920d64db582	201	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
lynxeyed_atsu	0:d920d64db582	202	#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
lynxeyed_atsu	0:d920d64db582	203
lynxeyed_atsu	0:d920d64db582	204	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
lynxeyed_atsu	0:d920d64db582	205	#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
lynxeyed_atsu	0:d920d64db582	206
lynxeyed_atsu	0:d920d64db582	207	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
lynxeyed_atsu	0:d920d64db582	208	#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
lynxeyed_atsu	0:d920d64db582	209
lynxeyed_atsu	0:d920d64db582	210	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
lynxeyed_atsu	0:d920d64db582	211	#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
lynxeyed_atsu	0:d920d64db582	212
lynxeyed_atsu	0:d920d64db582	213	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
lynxeyed_atsu	0:d920d64db582	214	#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
lynxeyed_atsu	0:d920d64db582	215
lynxeyed_atsu	0:d920d64db582	216	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
lynxeyed_atsu	0:d920d64db582	217	#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
lynxeyed_atsu	0:d920d64db582	218
lynxeyed_atsu	0:d920d64db582	219	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
lynxeyed_atsu	0:d920d64db582	220	#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
lynxeyed_atsu	0:d920d64db582	221
lynxeyed_atsu	0:d920d64db582	222	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
lynxeyed_atsu	0:d920d64db582	223	#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
lynxeyed_atsu	0:d920d64db582	224
lynxeyed_atsu	0:d920d64db582	225	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
lynxeyed_atsu	0:d920d64db582	226	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
lynxeyed_atsu	0:d920d64db582	227
lynxeyed_atsu	0:d920d64db582	228	/* SCB Interrupt Control State Register Definitions */
lynxeyed_atsu	0:d920d64db582	229	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
lynxeyed_atsu	0:d920d64db582	230	#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
lynxeyed_atsu	0:d920d64db582	231
lynxeyed_atsu	0:d920d64db582	232	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
lynxeyed_atsu	0:d920d64db582	233	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
lynxeyed_atsu	0:d920d64db582	234
lynxeyed_atsu	0:d920d64db582	235	/* SCB Application Interrupt and Reset Control Register Definitions */
lynxeyed_atsu	0:d920d64db582	236	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
lynxeyed_atsu	0:d920d64db582	237	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
lynxeyed_atsu	0:d920d64db582	238
lynxeyed_atsu	0:d920d64db582	239	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
lynxeyed_atsu	0:d920d64db582	240	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
lynxeyed_atsu	0:d920d64db582	241
lynxeyed_atsu	0:d920d64db582	242	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
lynxeyed_atsu	0:d920d64db582	243	#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
lynxeyed_atsu	0:d920d64db582	244
lynxeyed_atsu	0:d920d64db582	245	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
lynxeyed_atsu	0:d920d64db582	246	#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
lynxeyed_atsu	0:d920d64db582	247
lynxeyed_atsu	0:d920d64db582	248	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
lynxeyed_atsu	0:d920d64db582	249	#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
lynxeyed_atsu	0:d920d64db582	250
lynxeyed_atsu	0:d920d64db582	251	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
lynxeyed_atsu	0:d920d64db582	252	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
lynxeyed_atsu	0:d920d64db582	253
lynxeyed_atsu	0:d920d64db582	254	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
lynxeyed_atsu	0:d920d64db582	255	#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
lynxeyed_atsu	0:d920d64db582	256
lynxeyed_atsu	0:d920d64db582	257	/* SCB System Control Register Definitions */
lynxeyed_atsu	0:d920d64db582	258	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
lynxeyed_atsu	0:d920d64db582	259	#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
lynxeyed_atsu	0:d920d64db582	260
lynxeyed_atsu	0:d920d64db582	261	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
lynxeyed_atsu	0:d920d64db582	262	#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
lynxeyed_atsu	0:d920d64db582	263
lynxeyed_atsu	0:d920d64db582	264	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
lynxeyed_atsu	0:d920d64db582	265	#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
lynxeyed_atsu	0:d920d64db582	266
lynxeyed_atsu	0:d920d64db582	267	/* SCB Configuration Control Register Definitions */
lynxeyed_atsu	0:d920d64db582	268	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
lynxeyed_atsu	0:d920d64db582	269	#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
lynxeyed_atsu	0:d920d64db582	270
lynxeyed_atsu	0:d920d64db582	271	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
lynxeyed_atsu	0:d920d64db582	272	#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
lynxeyed_atsu	0:d920d64db582	273
lynxeyed_atsu	0:d920d64db582	274	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
lynxeyed_atsu	0:d920d64db582	275	#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
lynxeyed_atsu	0:d920d64db582	276
lynxeyed_atsu	0:d920d64db582	277	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
lynxeyed_atsu	0:d920d64db582	278	#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
lynxeyed_atsu	0:d920d64db582	279
lynxeyed_atsu	0:d920d64db582	280	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
lynxeyed_atsu	0:d920d64db582	281	#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
lynxeyed_atsu	0:d920d64db582	282
lynxeyed_atsu	0:d920d64db582	283	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
lynxeyed_atsu	0:d920d64db582	284	#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
lynxeyed_atsu	0:d920d64db582	285
lynxeyed_atsu	0:d920d64db582	286	/* SCB System Handler Control and State Register Definitions */
lynxeyed_atsu	0:d920d64db582	287	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
lynxeyed_atsu	0:d920d64db582	288	#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
lynxeyed_atsu	0:d920d64db582	289
lynxeyed_atsu	0:d920d64db582	290	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
lynxeyed_atsu	0:d920d64db582	291	#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
lynxeyed_atsu	0:d920d64db582	292
lynxeyed_atsu	0:d920d64db582	293	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
lynxeyed_atsu	0:d920d64db582	294	#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
lynxeyed_atsu	0:d920d64db582	295
lynxeyed_atsu	0:d920d64db582	296	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
lynxeyed_atsu	0:d920d64db582	297	#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
lynxeyed_atsu	0:d920d64db582	298
lynxeyed_atsu	0:d920d64db582	299	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
lynxeyed_atsu	0:d920d64db582	300	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
lynxeyed_atsu	0:d920d64db582	301
lynxeyed_atsu	0:d920d64db582	302	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
lynxeyed_atsu	0:d920d64db582	303	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
lynxeyed_atsu	0:d920d64db582	304
lynxeyed_atsu	0:d920d64db582	305	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
lynxeyed_atsu	0:d920d64db582	306	#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
lynxeyed_atsu	0:d920d64db582	307
lynxeyed_atsu	0:d920d64db582	308	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
lynxeyed_atsu	0:d920d64db582	309	#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
lynxeyed_atsu	0:d920d64db582	310
lynxeyed_atsu	0:d920d64db582	311	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
lynxeyed_atsu	0:d920d64db582	312	#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
lynxeyed_atsu	0:d920d64db582	313
lynxeyed_atsu	0:d920d64db582	314	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
lynxeyed_atsu	0:d920d64db582	315	#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
lynxeyed_atsu	0:d920d64db582	316
lynxeyed_atsu	0:d920d64db582	317	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
lynxeyed_atsu	0:d920d64db582	318	#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
lynxeyed_atsu	0:d920d64db582	319
lynxeyed_atsu	0:d920d64db582	320	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
lynxeyed_atsu	0:d920d64db582	321	#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
lynxeyed_atsu	0:d920d64db582	322
lynxeyed_atsu	0:d920d64db582	323	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
lynxeyed_atsu	0:d920d64db582	324	#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
lynxeyed_atsu	0:d920d64db582	325
lynxeyed_atsu	0:d920d64db582	326	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
lynxeyed_atsu	0:d920d64db582	327	#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
lynxeyed_atsu	0:d920d64db582	328
lynxeyed_atsu	0:d920d64db582	329	/* SCB Configurable Fault Status Registers Definitions */
lynxeyed_atsu	0:d920d64db582	330	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
lynxeyed_atsu	0:d920d64db582	331	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
lynxeyed_atsu	0:d920d64db582	332
lynxeyed_atsu	0:d920d64db582	333	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
lynxeyed_atsu	0:d920d64db582	334	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
lynxeyed_atsu	0:d920d64db582	335
lynxeyed_atsu	0:d920d64db582	336	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
lynxeyed_atsu	0:d920d64db582	337	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
lynxeyed_atsu	0:d920d64db582	338
lynxeyed_atsu	0:d920d64db582	339	/* SCB Hard Fault Status Registers Definitions */
lynxeyed_atsu	0:d920d64db582	340	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
lynxeyed_atsu	0:d920d64db582	341	#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
lynxeyed_atsu	0:d920d64db582	342
lynxeyed_atsu	0:d920d64db582	343	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
lynxeyed_atsu	0:d920d64db582	344	#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
lynxeyed_atsu	0:d920d64db582	345
lynxeyed_atsu	0:d920d64db582	346	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
lynxeyed_atsu	0:d920d64db582	347	#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
lynxeyed_atsu	0:d920d64db582	348
lynxeyed_atsu	0:d920d64db582	349	/* SCB Debug Fault Status Register Definitions */
lynxeyed_atsu	0:d920d64db582	350	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
lynxeyed_atsu	0:d920d64db582	351	#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
lynxeyed_atsu	0:d920d64db582	352
lynxeyed_atsu	0:d920d64db582	353	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
lynxeyed_atsu	0:d920d64db582	354	#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
lynxeyed_atsu	0:d920d64db582	355
lynxeyed_atsu	0:d920d64db582	356	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
lynxeyed_atsu	0:d920d64db582	357	#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
lynxeyed_atsu	0:d920d64db582	358
lynxeyed_atsu	0:d920d64db582	359	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
lynxeyed_atsu	0:d920d64db582	360	#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
lynxeyed_atsu	0:d920d64db582	361
lynxeyed_atsu	0:d920d64db582	362	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
lynxeyed_atsu	0:d920d64db582	363	#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
lynxeyed_atsu	0:d920d64db582	364	/@}/ /* end of group CMSIS_CM3_SCB */
lynxeyed_atsu	0:d920d64db582	365
lynxeyed_atsu	0:d920d64db582	366
lynxeyed_atsu	0:d920d64db582	367	/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
lynxeyed_atsu	0:d920d64db582	368	memory mapped structure for SysTick
lynxeyed_atsu	0:d920d64db582	369	@{
lynxeyed_atsu	0:d920d64db582	370	*/
lynxeyed_atsu	0:d920d64db582	371	/** @brief System Tick Timer (SysTick) register structure definition */
lynxeyed_atsu	0:d920d64db582	372	typedef struct
lynxeyed_atsu	0:d920d64db582	373	{
lynxeyed_atsu	0:d920d64db582	374	__IO uint32_t CTRL; /!< Offset: 0x00 SysTick Control and Status Register /
lynxeyed_atsu	0:d920d64db582	375	__IO uint32_t RELOAD; /!< Offset: 0x04 SysTick Reload Value Register /
lynxeyed_atsu	0:d920d64db582	376	__IO uint32_t CURR; /!< Offset: 0x08 SysTick Current Value Register /
lynxeyed_atsu	0:d920d64db582	377	__IO uint32_t CALIB; /!< Offset: 0x0C SysTick Calibration Register /
lynxeyed_atsu	0:d920d64db582	378	} SysTick_Type;
lynxeyed_atsu	0:d920d64db582	379
lynxeyed_atsu	0:d920d64db582	380	/* SysTick Control / Status Register Definitions */
lynxeyed_atsu	0:d920d64db582	381	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
lynxeyed_atsu	0:d920d64db582	382	#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
lynxeyed_atsu	0:d920d64db582	383
lynxeyed_atsu	0:d920d64db582	384	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
lynxeyed_atsu	0:d920d64db582	385	#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
lynxeyed_atsu	0:d920d64db582	386
lynxeyed_atsu	0:d920d64db582	387	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
lynxeyed_atsu	0:d920d64db582	388	#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
lynxeyed_atsu	0:d920d64db582	389
lynxeyed_atsu	0:d920d64db582	390	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
lynxeyed_atsu	0:d920d64db582	391	#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
lynxeyed_atsu	0:d920d64db582	392
lynxeyed_atsu	0:d920d64db582	393	/* SysTick Reload Register Definitions */
lynxeyed_atsu	0:d920d64db582	394	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
lynxeyed_atsu	0:d920d64db582	395	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
lynxeyed_atsu	0:d920d64db582	396
lynxeyed_atsu	0:d920d64db582	397	/* SysTick Current Register Definitions */
lynxeyed_atsu	0:d920d64db582	398	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
lynxeyed_atsu	0:d920d64db582	399	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
lynxeyed_atsu	0:d920d64db582	400
lynxeyed_atsu	0:d920d64db582	401	/* SysTick Calibration Register Definitions */
lynxeyed_atsu	0:d920d64db582	402	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
lynxeyed_atsu	0:d920d64db582	403	#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
lynxeyed_atsu	0:d920d64db582	404
lynxeyed_atsu	0:d920d64db582	405	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
lynxeyed_atsu	0:d920d64db582	406	#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
lynxeyed_atsu	0:d920d64db582	407
lynxeyed_atsu	0:d920d64db582	408	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
lynxeyed_atsu	0:d920d64db582	409	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
lynxeyed_atsu	0:d920d64db582	410	/@}/ /* end of group CMSIS_CM3_SysTick */
lynxeyed_atsu	0:d920d64db582	411
lynxeyed_atsu	0:d920d64db582	412
lynxeyed_atsu	0:d920d64db582	413	/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
lynxeyed_atsu	0:d920d64db582	414	memory mapped structure for Instrumentation Trace Macrocell (ITM)
lynxeyed_atsu	0:d920d64db582	415	@{
lynxeyed_atsu	0:d920d64db582	416	*/
lynxeyed_atsu	0:d920d64db582	417	/** @brief Instrumentation Trace Macrocell (ITM) register structure definition */
lynxeyed_atsu	0:d920d64db582	418	typedef struct
lynxeyed_atsu	0:d920d64db582	419	{
lynxeyed_atsu	0:d920d64db582	420	__O union
lynxeyed_atsu	0:d920d64db582	421	{
lynxeyed_atsu	0:d920d64db582	422	__O uint8_t u8; /!< Offset: ITM Stimulus Port 8-bit /
lynxeyed_atsu	0:d920d64db582	423	__O uint16_t u16; /!< Offset: ITM Stimulus Port 16-bit /
lynxeyed_atsu	0:d920d64db582	424	__O uint32_t u32; /!< Offset: ITM Stimulus Port 32-bit /
lynxeyed_atsu	0:d920d64db582	425	} PORT [32]; /!< Offset: 0x00 ITM Stimulus Port Registers /
lynxeyed_atsu	0:d920d64db582	426	uint32_t RESERVED0[864];
lynxeyed_atsu	0:d920d64db582	427	__IO uint32_t TER; /!< Offset: ITM Trace Enable Register /
lynxeyed_atsu	0:d920d64db582	428	uint32_t RESERVED1[15];
lynxeyed_atsu	0:d920d64db582	429	__IO uint32_t TPR; /!< Offset: ITM Trace Privilege Register /
lynxeyed_atsu	0:d920d64db582	430	uint32_t RESERVED2[15];
lynxeyed_atsu	0:d920d64db582	431	__IO uint32_t TCR; /!< Offset: ITM Trace Control Register /
lynxeyed_atsu	0:d920d64db582	432	uint32_t RESERVED3[29];
lynxeyed_atsu	0:d920d64db582	433	__IO uint32_t IWR; /!< Offset: ITM Integration Write Register /
lynxeyed_atsu	0:d920d64db582	434	__IO uint32_t IRR; /!< Offset: ITM Integration Read Register /
lynxeyed_atsu	0:d920d64db582	435	__IO uint32_t IMCR; /!< Offset: ITM Integration Mode Control Register /
lynxeyed_atsu	0:d920d64db582	436	uint32_t RESERVED4[43];
lynxeyed_atsu	0:d920d64db582	437	__IO uint32_t LAR; /!< Offset: ITM Lock Access Register /
lynxeyed_atsu	0:d920d64db582	438	__IO uint32_t LSR; /!< Offset: ITM Lock Status Register /
lynxeyed_atsu	0:d920d64db582	439	uint32_t RESERVED5[6];
lynxeyed_atsu	0:d920d64db582	440	__I uint32_t PID4; /!< Offset: ITM Peripheral Identification Register #4 /
lynxeyed_atsu	0:d920d64db582	441	__I uint32_t PID5; /!< Offset: ITM Peripheral Identification Register #5 /
lynxeyed_atsu	0:d920d64db582	442	__I uint32_t PID6; /!< Offset: ITM Peripheral Identification Register #6 /
lynxeyed_atsu	0:d920d64db582	443	__I uint32_t PID7; /!< Offset: ITM Peripheral Identification Register #7 /
lynxeyed_atsu	0:d920d64db582	444	__I uint32_t PID0; /!< Offset: ITM Peripheral Identification Register #0 /
lynxeyed_atsu	0:d920d64db582	445	__I uint32_t PID1; /!< Offset: ITM Peripheral Identification Register #1 /
lynxeyed_atsu	0:d920d64db582	446	__I uint32_t PID2; /!< Offset: ITM Peripheral Identification Register #2 /
lynxeyed_atsu	0:d920d64db582	447	__I uint32_t PID3; /!< Offset: ITM Peripheral Identification Register #3 /
lynxeyed_atsu	0:d920d64db582	448	__I uint32_t CID0; /!< Offset: ITM Component Identification Register #0 /
lynxeyed_atsu	0:d920d64db582	449	__I uint32_t CID1; /!< Offset: ITM Component Identification Register #1 /
lynxeyed_atsu	0:d920d64db582	450	__I uint32_t CID2; /!< Offset: ITM Component Identification Register #2 /
lynxeyed_atsu	0:d920d64db582	451	__I uint32_t CID3; /!< Offset: ITM Component Identification Register #3 /
lynxeyed_atsu	0:d920d64db582	452	} ITM_Type;
lynxeyed_atsu	0:d920d64db582	453
lynxeyed_atsu	0:d920d64db582	454	/* ITM Trace Privilege Register Definitions */
lynxeyed_atsu	0:d920d64db582	455	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
lynxeyed_atsu	0:d920d64db582	456	#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
lynxeyed_atsu	0:d920d64db582	457
lynxeyed_atsu	0:d920d64db582	458	/* ITM Trace Control Register Definitions */
lynxeyed_atsu	0:d920d64db582	459	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
lynxeyed_atsu	0:d920d64db582	460	#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
lynxeyed_atsu	0:d920d64db582	461
lynxeyed_atsu	0:d920d64db582	462	#define ITM_TCR_ATBID_Pos 16 /!< ITM TCR: ATBID Position /
lynxeyed_atsu	0:d920d64db582	463	#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /!< ITM TCR: ATBID Mask /
lynxeyed_atsu	0:d920d64db582	464
lynxeyed_atsu	0:d920d64db582	465	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
lynxeyed_atsu	0:d920d64db582	466	#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
lynxeyed_atsu	0:d920d64db582	467
lynxeyed_atsu	0:d920d64db582	468	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
lynxeyed_atsu	0:d920d64db582	469	#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
lynxeyed_atsu	0:d920d64db582	470
lynxeyed_atsu	0:d920d64db582	471	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
lynxeyed_atsu	0:d920d64db582	472	#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
lynxeyed_atsu	0:d920d64db582	473
lynxeyed_atsu	0:d920d64db582	474	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
lynxeyed_atsu	0:d920d64db582	475	#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
lynxeyed_atsu	0:d920d64db582	476
lynxeyed_atsu	0:d920d64db582	477	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
lynxeyed_atsu	0:d920d64db582	478	#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
lynxeyed_atsu	0:d920d64db582	479
lynxeyed_atsu	0:d920d64db582	480	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
lynxeyed_atsu	0:d920d64db582	481	#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
lynxeyed_atsu	0:d920d64db582	482
lynxeyed_atsu	0:d920d64db582	483	/* ITM Integration Write Register Definitions */
lynxeyed_atsu	0:d920d64db582	484	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
lynxeyed_atsu	0:d920d64db582	485	#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
lynxeyed_atsu	0:d920d64db582	486
lynxeyed_atsu	0:d920d64db582	487	/* ITM Integration Read Register Definitions */
lynxeyed_atsu	0:d920d64db582	488	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
lynxeyed_atsu	0:d920d64db582	489	#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
lynxeyed_atsu	0:d920d64db582	490
lynxeyed_atsu	0:d920d64db582	491	/* ITM Integration Mode Control Register Definitions */
lynxeyed_atsu	0:d920d64db582	492	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
lynxeyed_atsu	0:d920d64db582	493	#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
lynxeyed_atsu	0:d920d64db582	494
lynxeyed_atsu	0:d920d64db582	495	/* ITM Lock Status Register Definitions */
lynxeyed_atsu	0:d920d64db582	496	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
lynxeyed_atsu	0:d920d64db582	497	#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
lynxeyed_atsu	0:d920d64db582	498
lynxeyed_atsu	0:d920d64db582	499	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
lynxeyed_atsu	0:d920d64db582	500	#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
lynxeyed_atsu	0:d920d64db582	501
lynxeyed_atsu	0:d920d64db582	502	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
lynxeyed_atsu	0:d920d64db582	503	#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
lynxeyed_atsu	0:d920d64db582	504	/@}/ /* end of group CMSIS_CM3_ITM */
lynxeyed_atsu	0:d920d64db582	505
lynxeyed_atsu	0:d920d64db582	506
lynxeyed_atsu	0:d920d64db582	507	/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
lynxeyed_atsu	0:d920d64db582	508	memory mapped structure for Interrupt Type
lynxeyed_atsu	0:d920d64db582	509	@{
lynxeyed_atsu	0:d920d64db582	510	*/
lynxeyed_atsu	0:d920d64db582	511	/** @brief Instrumentation Trace Macrocell (ITM) register structure definition */
lynxeyed_atsu	0:d920d64db582	512	typedef struct
lynxeyed_atsu	0:d920d64db582	513	{
lynxeyed_atsu	0:d920d64db582	514	uint32_t RESERVED0;
lynxeyed_atsu	0:d920d64db582	515	__I uint32_t ICTR; /!< Offset: 0x04 Interrupt Control Type Register /
lynxeyed_atsu	0:d920d64db582	516	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
lynxeyed_atsu	0:d920d64db582	517	__IO uint32_t ACTLR; /!< Offset: 0x08 Auxiliary Control Register /
lynxeyed_atsu	0:d920d64db582	518	#else
lynxeyed_atsu	0:d920d64db582	519	uint32_t RESERVED1;
lynxeyed_atsu	0:d920d64db582	520	#endif
lynxeyed_atsu	0:d920d64db582	521	} InterruptType_Type;
lynxeyed_atsu	0:d920d64db582	522
lynxeyed_atsu	0:d920d64db582	523	/* Interrupt Controller Type Register Definitions */
lynxeyed_atsu	0:d920d64db582	524	#define InterruptType_ICTR_INTLINESNUM_Pos 0 /!< InterruptType ICTR: INTLINESNUM Position /
lynxeyed_atsu	0:d920d64db582	525	#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /!< InterruptType ICTR: INTLINESNUM Mask /
lynxeyed_atsu	0:d920d64db582	526
lynxeyed_atsu	0:d920d64db582	527	/* Auxiliary Control Register Definitions */
lynxeyed_atsu	0:d920d64db582	528	#define InterruptType_ACTLR_DISFOLD_Pos 2 /!< InterruptType ACTLR: DISFOLD Position /
lynxeyed_atsu	0:d920d64db582	529	#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /!< InterruptType ACTLR: DISFOLD Mask /
lynxeyed_atsu	0:d920d64db582	530
lynxeyed_atsu	0:d920d64db582	531	#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /!< InterruptType ACTLR: DISDEFWBUF Position /
lynxeyed_atsu	0:d920d64db582	532	#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /!< InterruptType ACTLR: DISDEFWBUF Mask /
lynxeyed_atsu	0:d920d64db582	533
lynxeyed_atsu	0:d920d64db582	534	#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /!< InterruptType ACTLR: DISMCYCINT Position /
lynxeyed_atsu	0:d920d64db582	535	#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /!< InterruptType ACTLR: DISMCYCINT Mask /
lynxeyed_atsu	0:d920d64db582	536	/@}/ /* end of group CMSIS_CM3_InterruptType */
lynxeyed_atsu	0:d920d64db582	537
lynxeyed_atsu	0:d920d64db582	538
lynxeyed_atsu	0:d920d64db582	539	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
lynxeyed_atsu	0:d920d64db582	540	/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
lynxeyed_atsu	0:d920d64db582	541	memory mapped structure for Memory Protection Unit (MPU)
lynxeyed_atsu	0:d920d64db582	542	@{
lynxeyed_atsu	0:d920d64db582	543	*/
lynxeyed_atsu	0:d920d64db582	544	/** @brief Memory Protection Unit (MPU) register structure definition */
lynxeyed_atsu	0:d920d64db582	545	typedef struct
lynxeyed_atsu	0:d920d64db582	546	{
lynxeyed_atsu	0:d920d64db582	547	__I uint32_t TYPE; /!< Offset: 0x00 MPU Type Register /
lynxeyed_atsu	0:d920d64db582	548	__IO uint32_t CTRL; /!< Offset: 0x04 MPU Control Register /
lynxeyed_atsu	0:d920d64db582	549	__IO uint32_t RNR; /!< Offset: 0x08 MPU Region RNRber Register /
lynxeyed_atsu	0:d920d64db582	550	__IO uint32_t RBAR; /!< Offset: 0x0C MPU Region Base Address Register /
lynxeyed_atsu	0:d920d64db582	551	__IO uint32_t RASR; /!< Offset: 0x10 MPU Region Attribute and Size Register /
lynxeyed_atsu	0:d920d64db582	552	__IO uint32_t RBAR_A1; /!< Offset: 0x14 MPU Alias 1 Region Base Address Register /
lynxeyed_atsu	0:d920d64db582	553	__IO uint32_t RASR_A1; /!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register /
lynxeyed_atsu	0:d920d64db582	554	__IO uint32_t RBAR_A2; /!< Offset: 0x1C MPU Alias 2 Region Base Address Register /
lynxeyed_atsu	0:d920d64db582	555	__IO uint32_t RASR_A2; /!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register /
lynxeyed_atsu	0:d920d64db582	556	__IO uint32_t RBAR_A3; /!< Offset: 0x24 MPU Alias 3 Region Base Address Register /
lynxeyed_atsu	0:d920d64db582	557	__IO uint32_t RASR_A3; /!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register /
lynxeyed_atsu	0:d920d64db582	558	} MPU_Type;
lynxeyed_atsu	0:d920d64db582	559
lynxeyed_atsu	0:d920d64db582	560	/* MPU Type Register */
lynxeyed_atsu	0:d920d64db582	561	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
lynxeyed_atsu	0:d920d64db582	562	#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
lynxeyed_atsu	0:d920d64db582	563
lynxeyed_atsu	0:d920d64db582	564	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
lynxeyed_atsu	0:d920d64db582	565	#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
lynxeyed_atsu	0:d920d64db582	566
lynxeyed_atsu	0:d920d64db582	567	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
lynxeyed_atsu	0:d920d64db582	568	#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
lynxeyed_atsu	0:d920d64db582	569
lynxeyed_atsu	0:d920d64db582	570	/* MPU Control Register */
lynxeyed_atsu	0:d920d64db582	571	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
lynxeyed_atsu	0:d920d64db582	572	#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
lynxeyed_atsu	0:d920d64db582	573
lynxeyed_atsu	0:d920d64db582	574	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
lynxeyed_atsu	0:d920d64db582	575	#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
lynxeyed_atsu	0:d920d64db582	576
lynxeyed_atsu	0:d920d64db582	577	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
lynxeyed_atsu	0:d920d64db582	578	#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
lynxeyed_atsu	0:d920d64db582	579
lynxeyed_atsu	0:d920d64db582	580	/* MPU Region Number Register */
lynxeyed_atsu	0:d920d64db582	581	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
lynxeyed_atsu	0:d920d64db582	582	#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
lynxeyed_atsu	0:d920d64db582	583
lynxeyed_atsu	0:d920d64db582	584	/* MPU Region Base Address Register */
lynxeyed_atsu	0:d920d64db582	585	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
lynxeyed_atsu	0:d920d64db582	586	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
lynxeyed_atsu	0:d920d64db582	587
lynxeyed_atsu	0:d920d64db582	588	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
lynxeyed_atsu	0:d920d64db582	589	#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
lynxeyed_atsu	0:d920d64db582	590
lynxeyed_atsu	0:d920d64db582	591	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
lynxeyed_atsu	0:d920d64db582	592	#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
lynxeyed_atsu	0:d920d64db582	593
lynxeyed_atsu	0:d920d64db582	594	/* MPU Region Attribute and Size Register */
lynxeyed_atsu	0:d920d64db582	595	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: XN Position /
lynxeyed_atsu	0:d920d64db582	596	#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /!< MPU RASR: XN Mask /
lynxeyed_atsu	0:d920d64db582	597
lynxeyed_atsu	0:d920d64db582	598	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: AP Position /
lynxeyed_atsu	0:d920d64db582	599	#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /!< MPU RASR: AP Mask /
lynxeyed_atsu	0:d920d64db582	600
lynxeyed_atsu	0:d920d64db582	601	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: TEX Position /
lynxeyed_atsu	0:d920d64db582	602	#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /!< MPU RASR: TEX Mask /
lynxeyed_atsu	0:d920d64db582	603
lynxeyed_atsu	0:d920d64db582	604	#define MPU_RASR_S_Pos 18 /!< MPU RASR: Shareable bit Position /
lynxeyed_atsu	0:d920d64db582	605	#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /!< MPU RASR: Shareable bit Mask /
lynxeyed_atsu	0:d920d64db582	606
lynxeyed_atsu	0:d920d64db582	607	#define MPU_RASR_C_Pos 17 /!< MPU RASR: Cacheable bit Position /
lynxeyed_atsu	0:d920d64db582	608	#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /!< MPU RASR: Cacheable bit Mask /
lynxeyed_atsu	0:d920d64db582	609
lynxeyed_atsu	0:d920d64db582	610	#define MPU_RASR_B_Pos 16 /!< MPU RASR: Bufferable bit Position /
lynxeyed_atsu	0:d920d64db582	611	#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /!< MPU RASR: Bufferable bit Mask /
lynxeyed_atsu	0:d920d64db582	612
lynxeyed_atsu	0:d920d64db582	613	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
lynxeyed_atsu	0:d920d64db582	614	#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
lynxeyed_atsu	0:d920d64db582	615
lynxeyed_atsu	0:d920d64db582	616	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
lynxeyed_atsu	0:d920d64db582	617	#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
lynxeyed_atsu	0:d920d64db582	618
lynxeyed_atsu	0:d920d64db582	619	#define MPU_RASR_ENA_Pos 0 /!< MPU RASR: Region enable bit Position /
lynxeyed_atsu	0:d920d64db582	620	#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /!< MPU RASR: Region enable bit Disable Mask /
lynxeyed_atsu	0:d920d64db582	621
lynxeyed_atsu	0:d920d64db582	622	/@}/ /* end of group CMSIS_CM3_MPU */
lynxeyed_atsu	0:d920d64db582	623	#endif
lynxeyed_atsu	0:d920d64db582	624
lynxeyed_atsu	0:d920d64db582	625
lynxeyed_atsu	0:d920d64db582	626	/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
lynxeyed_atsu	0:d920d64db582	627	memory mapped structure for Core Debug Register
lynxeyed_atsu	0:d920d64db582	628	@{
lynxeyed_atsu	0:d920d64db582	629	*/
lynxeyed_atsu	0:d920d64db582	630	/** @brief Core Debug register structure definition */
lynxeyed_atsu	0:d920d64db582	631	typedef struct
lynxeyed_atsu	0:d920d64db582	632	{
lynxeyed_atsu	0:d920d64db582	633	__IO uint32_t DHCSR; /!< Offset: 0x00 Debug Halting Control and Status Register /
lynxeyed_atsu	0:d920d64db582	634	__O uint32_t DCRSR; /!< Offset: 0x04 Debug Core Register Selector Register /
lynxeyed_atsu	0:d920d64db582	635	__IO uint32_t DCRDR; /!< Offset: 0x08 Debug Core Register Data Register /
lynxeyed_atsu	0:d920d64db582	636	__IO uint32_t DEMCR; /!< Offset: 0x0C Debug Exception and Monitor Control Register /
lynxeyed_atsu	0:d920d64db582	637	} CoreDebug_Type;
lynxeyed_atsu	0:d920d64db582	638
lynxeyed_atsu	0:d920d64db582	639	/* Debug Halting Control and Status Register */
lynxeyed_atsu	0:d920d64db582	640	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
lynxeyed_atsu	0:d920d64db582	641	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
lynxeyed_atsu	0:d920d64db582	642
lynxeyed_atsu	0:d920d64db582	643	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
lynxeyed_atsu	0:d920d64db582	644	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
lynxeyed_atsu	0:d920d64db582	645
lynxeyed_atsu	0:d920d64db582	646	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
lynxeyed_atsu	0:d920d64db582	647	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
lynxeyed_atsu	0:d920d64db582	648
lynxeyed_atsu	0:d920d64db582	649	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
lynxeyed_atsu	0:d920d64db582	650	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
lynxeyed_atsu	0:d920d64db582	651
lynxeyed_atsu	0:d920d64db582	652	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
lynxeyed_atsu	0:d920d64db582	653	#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
lynxeyed_atsu	0:d920d64db582	654
lynxeyed_atsu	0:d920d64db582	655	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
lynxeyed_atsu	0:d920d64db582	656	#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
lynxeyed_atsu	0:d920d64db582	657
lynxeyed_atsu	0:d920d64db582	658	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
lynxeyed_atsu	0:d920d64db582	659	#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
lynxeyed_atsu	0:d920d64db582	660
lynxeyed_atsu	0:d920d64db582	661	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
lynxeyed_atsu	0:d920d64db582	662	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
lynxeyed_atsu	0:d920d64db582	663
lynxeyed_atsu	0:d920d64db582	664	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
lynxeyed_atsu	0:d920d64db582	665	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
lynxeyed_atsu	0:d920d64db582	666
lynxeyed_atsu	0:d920d64db582	667	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
lynxeyed_atsu	0:d920d64db582	668	#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
lynxeyed_atsu	0:d920d64db582	669
lynxeyed_atsu	0:d920d64db582	670	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
lynxeyed_atsu	0:d920d64db582	671	#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
lynxeyed_atsu	0:d920d64db582	672
lynxeyed_atsu	0:d920d64db582	673	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
lynxeyed_atsu	0:d920d64db582	674	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
lynxeyed_atsu	0:d920d64db582	675
lynxeyed_atsu	0:d920d64db582	676	/* Debug Core Register Selector Register */
lynxeyed_atsu	0:d920d64db582	677	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
lynxeyed_atsu	0:d920d64db582	678	#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
lynxeyed_atsu	0:d920d64db582	679
lynxeyed_atsu	0:d920d64db582	680	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
lynxeyed_atsu	0:d920d64db582	681	#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
lynxeyed_atsu	0:d920d64db582	682
lynxeyed_atsu	0:d920d64db582	683	/* Debug Exception and Monitor Control Register */
lynxeyed_atsu	0:d920d64db582	684	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
lynxeyed_atsu	0:d920d64db582	685	#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
lynxeyed_atsu	0:d920d64db582	686
lynxeyed_atsu	0:d920d64db582	687	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
lynxeyed_atsu	0:d920d64db582	688	#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
lynxeyed_atsu	0:d920d64db582	689
lynxeyed_atsu	0:d920d64db582	690	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
lynxeyed_atsu	0:d920d64db582	691	#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
lynxeyed_atsu	0:d920d64db582	692
lynxeyed_atsu	0:d920d64db582	693	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
lynxeyed_atsu	0:d920d64db582	694	#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
lynxeyed_atsu	0:d920d64db582	695
lynxeyed_atsu	0:d920d64db582	696	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
lynxeyed_atsu	0:d920d64db582	697	#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
lynxeyed_atsu	0:d920d64db582	698
lynxeyed_atsu	0:d920d64db582	699	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
lynxeyed_atsu	0:d920d64db582	700	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
lynxeyed_atsu	0:d920d64db582	701
lynxeyed_atsu	0:d920d64db582	702	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
lynxeyed_atsu	0:d920d64db582	703	#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
lynxeyed_atsu	0:d920d64db582	704
lynxeyed_atsu	0:d920d64db582	705	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
lynxeyed_atsu	0:d920d64db582	706	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
lynxeyed_atsu	0:d920d64db582	707
lynxeyed_atsu	0:d920d64db582	708	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
lynxeyed_atsu	0:d920d64db582	709	#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
lynxeyed_atsu	0:d920d64db582	710
lynxeyed_atsu	0:d920d64db582	711	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
lynxeyed_atsu	0:d920d64db582	712	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
lynxeyed_atsu	0:d920d64db582	713
lynxeyed_atsu	0:d920d64db582	714	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
lynxeyed_atsu	0:d920d64db582	715	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
lynxeyed_atsu	0:d920d64db582	716
lynxeyed_atsu	0:d920d64db582	717	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
lynxeyed_atsu	0:d920d64db582	718	#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
lynxeyed_atsu	0:d920d64db582	719
lynxeyed_atsu	0:d920d64db582	720	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
lynxeyed_atsu	0:d920d64db582	721	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
lynxeyed_atsu	0:d920d64db582	722	/@}/ /* end of group CMSIS_CM3_CoreDebug */
lynxeyed_atsu	0:d920d64db582	723
lynxeyed_atsu	0:d920d64db582	724
lynxeyed_atsu	0:d920d64db582	725	/* Memory mapping of Cortex-M3 Hardware */
lynxeyed_atsu	0:d920d64db582	726	#define SCS_BASE (0xE000E000) /!< System Control Space Base Address /
lynxeyed_atsu	0:d920d64db582	727	#define ITM_BASE (0xE0000000) /!< ITM Base Address /
lynxeyed_atsu	0:d920d64db582	728	#define CoreDebug_BASE (0xE000EDF0) /!< Core Debug Base Address /
lynxeyed_atsu	0:d920d64db582	729	#define SysTick_BASE (SCS_BASE + 0x0010) /!< SysTick Base Address /
lynxeyed_atsu	0:d920d64db582	730	#define NVIC_BASE (SCS_BASE + 0x0100) /!< NVIC Base Address /
lynxeyed_atsu	0:d920d64db582	731	#define SCB_BASE (SCS_BASE + 0x0D00) /!< System Control Block Base Address /
lynxeyed_atsu	0:d920d64db582	732
lynxeyed_atsu	0:d920d64db582	733	#define InterruptType ((InterruptType_Type ) SCS_BASE) /!< Interrupt Type Register */
lynxeyed_atsu	0:d920d64db582	734	#define SCB ((SCB_Type ) SCB_BASE) /!< SCB configuration struct */
lynxeyed_atsu	0:d920d64db582	735	#define SysTick ((SysTick_Type ) SysTick_BASE) /!< SysTick configuration struct */
lynxeyed_atsu	0:d920d64db582	736	#define NVIC ((NVIC_Type ) NVIC_BASE) /!< NVIC configuration struct */
lynxeyed_atsu	0:d920d64db582	737	#define ITM ((ITM_Type ) ITM_BASE) /!< ITM configuration struct */
lynxeyed_atsu	0:d920d64db582	738	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
lynxeyed_atsu	0:d920d64db582	739
lynxeyed_atsu	0:d920d64db582	740	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
lynxeyed_atsu	0:d920d64db582	741	#define MPU_BASE (SCS_BASE + 0x0D90) /!< Memory Protection Unit /
lynxeyed_atsu	0:d920d64db582	742	#define MPU ((MPU_Type) MPU_BASE) /!< Memory Protection Unit */
lynxeyed_atsu	0:d920d64db582	743	#endif
lynxeyed_atsu	0:d920d64db582	744
lynxeyed_atsu	0:d920d64db582	745	/@}/ /* end of group CMSIS_CM3_core_register */
lynxeyed_atsu	0:d920d64db582	746
lynxeyed_atsu	0:d920d64db582	747
lynxeyed_atsu	0:d920d64db582	748	/*******************************************************************************
lynxeyed_atsu	0:d920d64db582	749	* Hardware Abstraction Layer
lynxeyed_atsu	0:d920d64db582	750	******************************************************************************/
lynxeyed_atsu	0:d920d64db582	751
lynxeyed_atsu	0:d920d64db582	752	#if defined ( __CC_ARM )
lynxeyed_atsu	0:d920d64db582	753	#define __ASM __asm /!< asm keyword for ARM Compiler /
lynxeyed_atsu	0:d920d64db582	754	#define __INLINE __inline /!< inline keyword for ARM Compiler /
lynxeyed_atsu	0:d920d64db582	755
lynxeyed_atsu	0:d920d64db582	756	#elif defined ( __ICCARM__ )
lynxeyed_atsu	0:d920d64db582	757	#define __ASM __asm /!< asm keyword for IAR Compiler /
lynxeyed_atsu	0:d920d64db582	758	#define __INLINE inline /!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! /
lynxeyed_atsu	0:d920d64db582	759
lynxeyed_atsu	0:d920d64db582	760	#elif defined ( __GNUC__ )
lynxeyed_atsu	0:d920d64db582	761	#define __ASM __asm /!< asm keyword for GNU Compiler /
lynxeyed_atsu	0:d920d64db582	762	#define __INLINE inline /!< inline keyword for GNU Compiler /
lynxeyed_atsu	0:d920d64db582	763
lynxeyed_atsu	0:d920d64db582	764	#elif defined ( __TASKING__ )
lynxeyed_atsu	0:d920d64db582	765	#define __ASM __asm /!< asm keyword for TASKING Compiler /
lynxeyed_atsu	0:d920d64db582	766	#define __INLINE inline /!< inline keyword for TASKING Compiler /
lynxeyed_atsu	0:d920d64db582	767
lynxeyed_atsu	0:d920d64db582	768	#endif
lynxeyed_atsu	0:d920d64db582	769
lynxeyed_atsu	0:d920d64db582	770
lynxeyed_atsu	0:d920d64db582	771	/* ################### Compiler specific Intrinsics ########################### */
lynxeyed_atsu	0:d920d64db582	772
lynxeyed_atsu	0:d920d64db582	773	#if defined ( __CC_ARM ) /------------------RealView Compiler -----------------/
lynxeyed_atsu	0:d920d64db582	774	/* ARM armcc specific functions */
lynxeyed_atsu	0:d920d64db582	775
lynxeyed_atsu	0:d920d64db582	776	#define __enable_fault_irq __enable_fiq
lynxeyed_atsu	0:d920d64db582	777	#define __disable_fault_irq __disable_fiq
lynxeyed_atsu	0:d920d64db582	778
lynxeyed_atsu	0:d920d64db582	779	#define __NOP __nop
lynxeyed_atsu	0:d920d64db582	780	#define __WFI __wfi
lynxeyed_atsu	0:d920d64db582	781	#define __WFE __wfe
lynxeyed_atsu	0:d920d64db582	782	#define __SEV __sev
lynxeyed_atsu	0:d920d64db582	783	#define __ISB() __isb(0)
lynxeyed_atsu	0:d920d64db582	784	#define __DSB() __dsb(0)
lynxeyed_atsu	0:d920d64db582	785	#define __DMB() __dmb(0)
lynxeyed_atsu	0:d920d64db582	786	#define __REV __rev
lynxeyed_atsu	0:d920d64db582	787	#define __RBIT __rbit
lynxeyed_atsu	0:d920d64db582	788	#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
lynxeyed_atsu	0:d920d64db582	789	#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
lynxeyed_atsu	0:d920d64db582	790	#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
lynxeyed_atsu	0:d920d64db582	791	#define __STREXB(value, ptr) __strex(value, ptr)
lynxeyed_atsu	0:d920d64db582	792	#define __STREXH(value, ptr) __strex(value, ptr)
lynxeyed_atsu	0:d920d64db582	793	#define __STREXW(value, ptr) __strex(value, ptr)
lynxeyed_atsu	0:d920d64db582	794
lynxeyed_atsu	0:d920d64db582	795
lynxeyed_atsu	0:d920d64db582	796	/* intrinsic unsigned long long __ldrexd(volatile void ptr) /
lynxeyed_atsu	0:d920d64db582	797	/* intrinsic int __strexd(unsigned long long val, volatile void ptr) /
lynxeyed_atsu	0:d920d64db582	798	/* intrinsic void __enable_irq(); */
lynxeyed_atsu	0:d920d64db582	799	/* intrinsic void __disable_irq(); */
lynxeyed_atsu	0:d920d64db582	800
lynxeyed_atsu	0:d920d64db582	801
lynxeyed_atsu	0:d920d64db582	802	/**
lynxeyed_atsu	0:d920d64db582	803	* @brief Return the Process Stack Pointer
lynxeyed_atsu	0:d920d64db582	804	*
lynxeyed_atsu	0:d920d64db582	805	* @return ProcessStackPointer
lynxeyed_atsu	0:d920d64db582	806	*
lynxeyed_atsu	0:d920d64db582	807	* Return the actual process stack pointer
lynxeyed_atsu	0:d920d64db582	808	*/
lynxeyed_atsu	0:d920d64db582	809	extern uint32_t __get_PSP(void);
lynxeyed_atsu	0:d920d64db582	810
lynxeyed_atsu	0:d920d64db582	811	/**
lynxeyed_atsu	0:d920d64db582	812	* @brief Set the Process Stack Pointer
lynxeyed_atsu	0:d920d64db582	813	*
lynxeyed_atsu	0:d920d64db582	814	* @param topOfProcStack Process Stack Pointer
lynxeyed_atsu	0:d920d64db582	815	*
lynxeyed_atsu	0:d920d64db582	816	* Assign the value ProcessStackPointer to the MSP
lynxeyed_atsu	0:d920d64db582	817	* (process stack pointer) Cortex processor register
lynxeyed_atsu	0:d920d64db582	818	*/
lynxeyed_atsu	0:d920d64db582	819	extern void __set_PSP(uint32_t topOfProcStack);
lynxeyed_atsu	0:d920d64db582	820
lynxeyed_atsu	0:d920d64db582	821	/**
lynxeyed_atsu	0:d920d64db582	822	* @brief Return the Main Stack Pointer
lynxeyed_atsu	0:d920d64db582	823	*
lynxeyed_atsu	0:d920d64db582	824	* @return Main Stack Pointer
lynxeyed_atsu	0:d920d64db582	825	*
lynxeyed_atsu	0:d920d64db582	826	* Return the current value of the MSP (main stack pointer)
lynxeyed_atsu	0:d920d64db582	827	* Cortex processor register
lynxeyed_atsu	0:d920d64db582	828	*/
lynxeyed_atsu	0:d920d64db582	829	extern uint32_t __get_MSP(void);
lynxeyed_atsu	0:d920d64db582	830
lynxeyed_atsu	0:d920d64db582	831	/**
lynxeyed_atsu	0:d920d64db582	832	* @brief Set the Main Stack Pointer
lynxeyed_atsu	0:d920d64db582	833	*
lynxeyed_atsu	0:d920d64db582	834	* @param topOfMainStack Main Stack Pointer
lynxeyed_atsu	0:d920d64db582	835	*
lynxeyed_atsu	0:d920d64db582	836	* Assign the value mainStackPointer to the MSP
lynxeyed_atsu	0:d920d64db582	837	* (main stack pointer) Cortex processor register
lynxeyed_atsu	0:d920d64db582	838	*/
lynxeyed_atsu	0:d920d64db582	839	extern void __set_MSP(uint32_t topOfMainStack);
lynxeyed_atsu	0:d920d64db582	840
lynxeyed_atsu	0:d920d64db582	841	/**
lynxeyed_atsu	0:d920d64db582	842	* @brief Reverse byte order in unsigned short value
lynxeyed_atsu	0:d920d64db582	843	*
lynxeyed_atsu	0:d920d64db582	844	* @param value value to reverse
lynxeyed_atsu	0:d920d64db582	845	* @return reversed value
lynxeyed_atsu	0:d920d64db582	846	*
lynxeyed_atsu	0:d920d64db582	847	* Reverse byte order in unsigned short value
lynxeyed_atsu	0:d920d64db582	848	*/
lynxeyed_atsu	0:d920d64db582	849	extern uint32_t __REV16(uint16_t value);
lynxeyed_atsu	0:d920d64db582	850
lynxeyed_atsu	0:d920d64db582	851	/**
lynxeyed_atsu	0:d920d64db582	852	* @brief Reverse byte order in signed short value with sign extension to integer
lynxeyed_atsu	0:d920d64db582	853	*
lynxeyed_atsu	0:d920d64db582	854	* @param value value to reverse
lynxeyed_atsu	0:d920d64db582	855	* @return reversed value
lynxeyed_atsu	0:d920d64db582	856	*
lynxeyed_atsu	0:d920d64db582	857	* Reverse byte order in signed short value with sign extension to integer
lynxeyed_atsu	0:d920d64db582	858	*/
lynxeyed_atsu	0:d920d64db582	859	extern int32_t __REVSH(int16_t value);
lynxeyed_atsu	0:d920d64db582	860
lynxeyed_atsu	0:d920d64db582	861
lynxeyed_atsu	0:d920d64db582	862	#if (__ARMCC_VERSION < 400000)
lynxeyed_atsu	0:d920d64db582	863
lynxeyed_atsu	0:d920d64db582	864	/**
lynxeyed_atsu	0:d920d64db582	865	* @brief Remove the exclusive lock created by ldrex
lynxeyed_atsu	0:d920d64db582	866	*
lynxeyed_atsu	0:d920d64db582	867	* Removes the exclusive lock which is created by ldrex.
lynxeyed_atsu	0:d920d64db582	868	*/
lynxeyed_atsu	0:d920d64db582	869	extern void __CLREX(void);
lynxeyed_atsu	0:d920d64db582	870
lynxeyed_atsu	0:d920d64db582	871	/**
lynxeyed_atsu	0:d920d64db582	872	* @brief Return the Base Priority value
lynxeyed_atsu	0:d920d64db582	873	*
lynxeyed_atsu	0:d920d64db582	874	* @return BasePriority
lynxeyed_atsu	0:d920d64db582	875	*
lynxeyed_atsu	0:d920d64db582	876	* Return the content of the base priority register
lynxeyed_atsu	0:d920d64db582	877	*/
lynxeyed_atsu	0:d920d64db582	878	extern uint32_t __get_BASEPRI(void);
lynxeyed_atsu	0:d920d64db582	879
lynxeyed_atsu	0:d920d64db582	880	/**
lynxeyed_atsu	0:d920d64db582	881	* @brief Set the Base Priority value
lynxeyed_atsu	0:d920d64db582	882	*
lynxeyed_atsu	0:d920d64db582	883	* @param basePri BasePriority
lynxeyed_atsu	0:d920d64db582	884	*
lynxeyed_atsu	0:d920d64db582	885	* Set the base priority register
lynxeyed_atsu	0:d920d64db582	886	*/
lynxeyed_atsu	0:d920d64db582	887	extern void __set_BASEPRI(uint32_t basePri);
lynxeyed_atsu	0:d920d64db582	888
lynxeyed_atsu	0:d920d64db582	889	/**
lynxeyed_atsu	0:d920d64db582	890	* @brief Return the Priority Mask value
lynxeyed_atsu	0:d920d64db582	891	*
lynxeyed_atsu	0:d920d64db582	892	* @return PriMask
lynxeyed_atsu	0:d920d64db582	893	*
lynxeyed_atsu	0:d920d64db582	894	* Return state of the priority mask bit from the priority mask register
lynxeyed_atsu	0:d920d64db582	895	*/
lynxeyed_atsu	0:d920d64db582	896	extern uint32_t __get_PRIMASK(void);
lynxeyed_atsu	0:d920d64db582	897
lynxeyed_atsu	0:d920d64db582	898	/**
lynxeyed_atsu	0:d920d64db582	899	* @brief Set the Priority Mask value
lynxeyed_atsu	0:d920d64db582	900	*
lynxeyed_atsu	0:d920d64db582	901	* @param priMask PriMask
lynxeyed_atsu	0:d920d64db582	902	*
lynxeyed_atsu	0:d920d64db582	903	* Set the priority mask bit in the priority mask register
lynxeyed_atsu	0:d920d64db582	904	*/
lynxeyed_atsu	0:d920d64db582	905	extern void __set_PRIMASK(uint32_t priMask);
lynxeyed_atsu	0:d920d64db582	906
lynxeyed_atsu	0:d920d64db582	907	/**
lynxeyed_atsu	0:d920d64db582	908	* @brief Return the Fault Mask value
lynxeyed_atsu	0:d920d64db582	909	*
lynxeyed_atsu	0:d920d64db582	910	* @return FaultMask
lynxeyed_atsu	0:d920d64db582	911	*
lynxeyed_atsu	0:d920d64db582	912	* Return the content of the fault mask register
lynxeyed_atsu	0:d920d64db582	913	*/
lynxeyed_atsu	0:d920d64db582	914	extern uint32_t __get_FAULTMASK(void);
lynxeyed_atsu	0:d920d64db582	915
lynxeyed_atsu	0:d920d64db582	916	/**
lynxeyed_atsu	0:d920d64db582	917	* @brief Set the Fault Mask value
lynxeyed_atsu	0:d920d64db582	918	*
lynxeyed_atsu	0:d920d64db582	919	* @param faultMask faultMask value
lynxeyed_atsu	0:d920d64db582	920	*
lynxeyed_atsu	0:d920d64db582	921	* Set the fault mask register
lynxeyed_atsu	0:d920d64db582	922	*/
lynxeyed_atsu	0:d920d64db582	923	extern void __set_FAULTMASK(uint32_t faultMask);
lynxeyed_atsu	0:d920d64db582	924
lynxeyed_atsu	0:d920d64db582	925	/**
lynxeyed_atsu	0:d920d64db582	926	* @brief Return the Control Register value
lynxeyed_atsu	0:d920d64db582	927	*
lynxeyed_atsu	0:d920d64db582	928	* @return Control value
lynxeyed_atsu	0:d920d64db582	929	*
lynxeyed_atsu	0:d920d64db582	930	* Return the content of the control register
lynxeyed_atsu	0:d920d64db582	931	*/
lynxeyed_atsu	0:d920d64db582	932	extern uint32_t __get_CONTROL(void);
lynxeyed_atsu	0:d920d64db582	933
lynxeyed_atsu	0:d920d64db582	934	/**
lynxeyed_atsu	0:d920d64db582	935	* @brief Set the Control Register value
lynxeyed_atsu	0:d920d64db582	936	*
lynxeyed_atsu	0:d920d64db582	937	* @param control Control value
lynxeyed_atsu	0:d920d64db582	938	*
lynxeyed_atsu	0:d920d64db582	939	* Set the control register
lynxeyed_atsu	0:d920d64db582	940	*/
lynxeyed_atsu	0:d920d64db582	941	extern void __set_CONTROL(uint32_t control);
lynxeyed_atsu	0:d920d64db582	942
lynxeyed_atsu	0:d920d64db582	943	#else /* (__ARMCC_VERSION >= 400000) */
lynxeyed_atsu	0:d920d64db582	944
lynxeyed_atsu	0:d920d64db582	945	/**
lynxeyed_atsu	0:d920d64db582	946	* @brief Remove the exclusive lock created by ldrex
lynxeyed_atsu	0:d920d64db582	947	*
lynxeyed_atsu	0:d920d64db582	948	* Removes the exclusive lock which is created by ldrex.
lynxeyed_atsu	0:d920d64db582	949	*/
lynxeyed_atsu	0:d920d64db582	950	#define __CLREX __clrex
lynxeyed_atsu	0:d920d64db582	951
lynxeyed_atsu	0:d920d64db582	952	/**
lynxeyed_atsu	0:d920d64db582	953	* @brief Return the Base Priority value
lynxeyed_atsu	0:d920d64db582	954	*
lynxeyed_atsu	0:d920d64db582	955	* @return BasePriority
lynxeyed_atsu	0:d920d64db582	956	*
lynxeyed_atsu	0:d920d64db582	957	* Return the content of the base priority register
lynxeyed_atsu	0:d920d64db582	958	*/
lynxeyed_atsu	0:d920d64db582	959	static __INLINE uint32_t __get_BASEPRI(void)
lynxeyed_atsu	0:d920d64db582	960	{
lynxeyed_atsu	0:d920d64db582	961	register uint32_t __regBasePri __ASM("basepri");
lynxeyed_atsu	0:d920d64db582	962	return(__regBasePri);
lynxeyed_atsu	0:d920d64db582	963	}
lynxeyed_atsu	0:d920d64db582	964
lynxeyed_atsu	0:d920d64db582	965	/**
lynxeyed_atsu	0:d920d64db582	966	* @brief Set the Base Priority value
lynxeyed_atsu	0:d920d64db582	967	*
lynxeyed_atsu	0:d920d64db582	968	* @param basePri BasePriority
lynxeyed_atsu	0:d920d64db582	969	*
lynxeyed_atsu	0:d920d64db582	970	* Set the base priority register
lynxeyed_atsu	0:d920d64db582	971	*/
lynxeyed_atsu	0:d920d64db582	972	static __INLINE void __set_BASEPRI(uint32_t basePri)
lynxeyed_atsu	0:d920d64db582	973	{
lynxeyed_atsu	0:d920d64db582	974	register uint32_t __regBasePri __ASM("basepri");
lynxeyed_atsu	0:d920d64db582	975	__regBasePri = (basePri & 0xff);
lynxeyed_atsu	0:d920d64db582	976	}
lynxeyed_atsu	0:d920d64db582	977
lynxeyed_atsu	0:d920d64db582	978	/**
lynxeyed_atsu	0:d920d64db582	979	* @brief Return the Priority Mask value
lynxeyed_atsu	0:d920d64db582	980	*
lynxeyed_atsu	0:d920d64db582	981	* @return PriMask
lynxeyed_atsu	0:d920d64db582	982	*
lynxeyed_atsu	0:d920d64db582	983	* Return state of the priority mask bit from the priority mask register
lynxeyed_atsu	0:d920d64db582	984	*/
lynxeyed_atsu	0:d920d64db582	985	static __INLINE uint32_t __get_PRIMASK(void)
lynxeyed_atsu	0:d920d64db582	986	{
lynxeyed_atsu	0:d920d64db582	987	register uint32_t __regPriMask __ASM("primask");
lynxeyed_atsu	0:d920d64db582	988	return(__regPriMask);
lynxeyed_atsu	0:d920d64db582	989	}
lynxeyed_atsu	0:d920d64db582	990
lynxeyed_atsu	0:d920d64db582	991	/**
lynxeyed_atsu	0:d920d64db582	992	* @brief Set the Priority Mask value
lynxeyed_atsu	0:d920d64db582	993	*
lynxeyed_atsu	0:d920d64db582	994	* @param priMask PriMask
lynxeyed_atsu	0:d920d64db582	995	*
lynxeyed_atsu	0:d920d64db582	996	* Set the priority mask bit in the priority mask register
lynxeyed_atsu	0:d920d64db582	997	*/
lynxeyed_atsu	0:d920d64db582	998	static __INLINE void __set_PRIMASK(uint32_t priMask)
lynxeyed_atsu	0:d920d64db582	999	{
lynxeyed_atsu	0:d920d64db582	1000	register uint32_t __regPriMask __ASM("primask");
lynxeyed_atsu	0:d920d64db582	1001	__regPriMask = (priMask);
lynxeyed_atsu	0:d920d64db582	1002	}
lynxeyed_atsu	0:d920d64db582	1003
lynxeyed_atsu	0:d920d64db582	1004	/**
lynxeyed_atsu	0:d920d64db582	1005	* @brief Return the Fault Mask value
lynxeyed_atsu	0:d920d64db582	1006	*
lynxeyed_atsu	0:d920d64db582	1007	* @return FaultMask
lynxeyed_atsu	0:d920d64db582	1008	*
lynxeyed_atsu	0:d920d64db582	1009	* Return the content of the fault mask register
lynxeyed_atsu	0:d920d64db582	1010	*/
lynxeyed_atsu	0:d920d64db582	1011	static __INLINE uint32_t __get_FAULTMASK(void)
lynxeyed_atsu	0:d920d64db582	1012	{
lynxeyed_atsu	0:d920d64db582	1013	register uint32_t __regFaultMask __ASM("faultmask");
lynxeyed_atsu	0:d920d64db582	1014	return(__regFaultMask);
lynxeyed_atsu	0:d920d64db582	1015	}
lynxeyed_atsu	0:d920d64db582	1016
lynxeyed_atsu	0:d920d64db582	1017	/**
lynxeyed_atsu	0:d920d64db582	1018	* @brief Set the Fault Mask value
lynxeyed_atsu	0:d920d64db582	1019	*
lynxeyed_atsu	0:d920d64db582	1020	* @param faultMask faultMask value
lynxeyed_atsu	0:d920d64db582	1021	*
lynxeyed_atsu	0:d920d64db582	1022	* Set the fault mask register
lynxeyed_atsu	0:d920d64db582	1023	*/
lynxeyed_atsu	0:d920d64db582	1024	static __INLINE void __set_FAULTMASK(uint32_t faultMask)
lynxeyed_atsu	0:d920d64db582	1025	{
lynxeyed_atsu	0:d920d64db582	1026	register uint32_t __regFaultMask __ASM("faultmask");
lynxeyed_atsu	0:d920d64db582	1027	__regFaultMask = (faultMask & 1);
lynxeyed_atsu	0:d920d64db582	1028	}
lynxeyed_atsu	0:d920d64db582	1029
lynxeyed_atsu	0:d920d64db582	1030	/**
lynxeyed_atsu	0:d920d64db582	1031	* @brief Return the Control Register value
lynxeyed_atsu	0:d920d64db582	1032	*
lynxeyed_atsu	0:d920d64db582	1033	* @return Control value
lynxeyed_atsu	0:d920d64db582	1034	*
lynxeyed_atsu	0:d920d64db582	1035	* Return the content of the control register
lynxeyed_atsu	0:d920d64db582	1036	*/
lynxeyed_atsu	0:d920d64db582	1037	static __INLINE uint32_t __get_CONTROL(void)
lynxeyed_atsu	0:d920d64db582	1038	{
lynxeyed_atsu	0:d920d64db582	1039	register uint32_t __regControl __ASM("control");
lynxeyed_atsu	0:d920d64db582	1040	return(__regControl);
lynxeyed_atsu	0:d920d64db582	1041	}
lynxeyed_atsu	0:d920d64db582	1042
lynxeyed_atsu	0:d920d64db582	1043	/**
lynxeyed_atsu	0:d920d64db582	1044	* @brief Set the Control Register value
lynxeyed_atsu	0:d920d64db582	1045	*
lynxeyed_atsu	0:d920d64db582	1046	* @param control Control value
lynxeyed_atsu	0:d920d64db582	1047	*
lynxeyed_atsu	0:d920d64db582	1048	* Set the control register
lynxeyed_atsu	0:d920d64db582	1049	*/
lynxeyed_atsu	0:d920d64db582	1050	static __INLINE void __set_CONTROL(uint32_t control)
lynxeyed_atsu	0:d920d64db582	1051	{
lynxeyed_atsu	0:d920d64db582	1052	register uint32_t __regControl __ASM("control");
lynxeyed_atsu	0:d920d64db582	1053	__regControl = control;
lynxeyed_atsu	0:d920d64db582	1054	}
lynxeyed_atsu	0:d920d64db582	1055
lynxeyed_atsu	0:d920d64db582	1056	#endif /* __ARMCC_VERSION */
lynxeyed_atsu	0:d920d64db582	1057
lynxeyed_atsu	0:d920d64db582	1058
lynxeyed_atsu	0:d920d64db582	1059
lynxeyed_atsu	0:d920d64db582	1060	#elif (defined (__ICCARM__)) /------------------ ICC Compiler -------------------/
lynxeyed_atsu	0:d920d64db582	1061	/* IAR iccarm specific functions */
lynxeyed_atsu	0:d920d64db582	1062
lynxeyed_atsu	0:d920d64db582	1063	#define __enable_irq __enable_interrupt /!< global Interrupt enable /
lynxeyed_atsu	0:d920d64db582	1064	#define __disable_irq __disable_interrupt /!< global Interrupt disable /
lynxeyed_atsu	0:d920d64db582	1065
lynxeyed_atsu	0:d920d64db582	1066	static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
lynxeyed_atsu	0:d920d64db582	1067	static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
lynxeyed_atsu	0:d920d64db582	1068
lynxeyed_atsu	0:d920d64db582	1069	#define __NOP __no_operation /!< no operation intrinsic in IAR Compiler /
lynxeyed_atsu	0:d920d64db582	1070	static __INLINE void __WFI() { __ASM ("wfi"); }
lynxeyed_atsu	0:d920d64db582	1071	static __INLINE void __WFE() { __ASM ("wfe"); }
lynxeyed_atsu	0:d920d64db582	1072	static __INLINE void __SEV() { __ASM ("sev"); }
lynxeyed_atsu	0:d920d64db582	1073	static __INLINE void __CLREX() { __ASM ("clrex"); }
lynxeyed_atsu	0:d920d64db582	1074
lynxeyed_atsu	0:d920d64db582	1075	/* intrinsic void __ISB(void) */
lynxeyed_atsu	0:d920d64db582	1076	/* intrinsic void __DSB(void) */
lynxeyed_atsu	0:d920d64db582	1077	/* intrinsic void __DMB(void) */
lynxeyed_atsu	0:d920d64db582	1078	/* intrinsic void __set_PRIMASK(); */
lynxeyed_atsu	0:d920d64db582	1079	/* intrinsic void __get_PRIMASK(); */
lynxeyed_atsu	0:d920d64db582	1080	/* intrinsic void __set_FAULTMASK(); */
lynxeyed_atsu	0:d920d64db582	1081	/* intrinsic void __get_FAULTMASK(); */
lynxeyed_atsu	0:d920d64db582	1082	/* intrinsic uint32_t __REV(uint32_t value); */
lynxeyed_atsu	0:d920d64db582	1083	/* intrinsic uint32_t __REVSH(uint32_t value); */
lynxeyed_atsu	0:d920d64db582	1084	/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
lynxeyed_atsu	0:d920d64db582	1085	/* intrinsic unsigned long __LDREX(unsigned long ); /
lynxeyed_atsu	0:d920d64db582	1086
lynxeyed_atsu	0:d920d64db582	1087
lynxeyed_atsu	0:d920d64db582	1088	/**
lynxeyed_atsu	0:d920d64db582	1089	* @brief Return the Process Stack Pointer
lynxeyed_atsu	0:d920d64db582	1090	*
lynxeyed_atsu	0:d920d64db582	1091	* @return ProcessStackPointer
lynxeyed_atsu	0:d920d64db582	1092	*
lynxeyed_atsu	0:d920d64db582	1093	* Return the actual process stack pointer
lynxeyed_atsu	0:d920d64db582	1094	*/
lynxeyed_atsu	0:d920d64db582	1095	extern uint32_t __get_PSP(void);
lynxeyed_atsu	0:d920d64db582	1096
lynxeyed_atsu	0:d920d64db582	1097	/**
lynxeyed_atsu	0:d920d64db582	1098	* @brief Set the Process Stack Pointer
lynxeyed_atsu	0:d920d64db582	1099	*
lynxeyed_atsu	0:d920d64db582	1100	* @param topOfProcStack Process Stack Pointer
lynxeyed_atsu	0:d920d64db582	1101	*
lynxeyed_atsu	0:d920d64db582	1102	* Assign the value ProcessStackPointer to the MSP
lynxeyed_atsu	0:d920d64db582	1103	* (process stack pointer) Cortex processor register
lynxeyed_atsu	0:d920d64db582	1104	*/
lynxeyed_atsu	0:d920d64db582	1105	extern void __set_PSP(uint32_t topOfProcStack);
lynxeyed_atsu	0:d920d64db582	1106
lynxeyed_atsu	0:d920d64db582	1107	/**
lynxeyed_atsu	0:d920d64db582	1108	* @brief Return the Main Stack Pointer
lynxeyed_atsu	0:d920d64db582	1109	*
lynxeyed_atsu	0:d920d64db582	1110	* @return Main Stack Pointer
lynxeyed_atsu	0:d920d64db582	1111	*
lynxeyed_atsu	0:d920d64db582	1112	* Return the current value of the MSP (main stack pointer)
lynxeyed_atsu	0:d920d64db582	1113	* Cortex processor register
lynxeyed_atsu	0:d920d64db582	1114	*/
lynxeyed_atsu	0:d920d64db582	1115	extern uint32_t __get_MSP(void);
lynxeyed_atsu	0:d920d64db582	1116
lynxeyed_atsu	0:d920d64db582	1117	/**
lynxeyed_atsu	0:d920d64db582	1118	* @brief Set the Main Stack Pointer
lynxeyed_atsu	0:d920d64db582	1119	*
lynxeyed_atsu	0:d920d64db582	1120	* @param topOfMainStack Main Stack Pointer
lynxeyed_atsu	0:d920d64db582	1121	*
lynxeyed_atsu	0:d920d64db582	1122	* Assign the value mainStackPointer to the MSP
lynxeyed_atsu	0:d920d64db582	1123	* (main stack pointer) Cortex processor register
lynxeyed_atsu	0:d920d64db582	1124	*/
lynxeyed_atsu	0:d920d64db582	1125	extern void __set_MSP(uint32_t topOfMainStack);
lynxeyed_atsu	0:d920d64db582	1126
lynxeyed_atsu	0:d920d64db582	1127	/**
lynxeyed_atsu	0:d920d64db582	1128	* @brief Reverse byte order in unsigned short value
lynxeyed_atsu	0:d920d64db582	1129	*
lynxeyed_atsu	0:d920d64db582	1130	* @param value value to reverse
lynxeyed_atsu	0:d920d64db582	1131	* @return reversed value
lynxeyed_atsu	0:d920d64db582	1132	*
lynxeyed_atsu	0:d920d64db582	1133	* Reverse byte order in unsigned short value
lynxeyed_atsu	0:d920d64db582	1134	*/
lynxeyed_atsu	0:d920d64db582	1135	extern uint32_t __REV16(uint16_t value);
lynxeyed_atsu	0:d920d64db582	1136
lynxeyed_atsu	0:d920d64db582	1137	/**
lynxeyed_atsu	0:d920d64db582	1138	* @brief Reverse bit order of value
lynxeyed_atsu	0:d920d64db582	1139	*
lynxeyed_atsu	0:d920d64db582	1140	* @param value value to reverse
lynxeyed_atsu	0:d920d64db582	1141	* @return reversed value
lynxeyed_atsu	0:d920d64db582	1142	*
lynxeyed_atsu	0:d920d64db582	1143	* Reverse bit order of value
lynxeyed_atsu	0:d920d64db582	1144	*/
lynxeyed_atsu	0:d920d64db582	1145	extern uint32_t __RBIT(uint32_t value);
lynxeyed_atsu	0:d920d64db582	1146
lynxeyed_atsu	0:d920d64db582	1147	/**
lynxeyed_atsu	0:d920d64db582	1148	* @brief LDR Exclusive (8 bit)
lynxeyed_atsu	0:d920d64db582	1149	*
lynxeyed_atsu	0:d920d64db582	1150	* @param *addr address pointer
lynxeyed_atsu	0:d920d64db582	1151	* @return value of (*address)
lynxeyed_atsu	0:d920d64db582	1152	*
lynxeyed_atsu	0:d920d64db582	1153	* Exclusive LDR command for 8 bit values)
lynxeyed_atsu	0:d920d64db582	1154	*/
lynxeyed_atsu	0:d920d64db582	1155	extern uint8_t __LDREXB(uint8_t *addr);
lynxeyed_atsu	0:d920d64db582	1156
lynxeyed_atsu	0:d920d64db582	1157	/**
lynxeyed_atsu	0:d920d64db582	1158	* @brief LDR Exclusive (16 bit)
lynxeyed_atsu	0:d920d64db582	1159	*
lynxeyed_atsu	0:d920d64db582	1160	* @param *addr address pointer
lynxeyed_atsu	0:d920d64db582	1161	* @return value of (*address)
lynxeyed_atsu	0:d920d64db582	1162	*
lynxeyed_atsu	0:d920d64db582	1163	* Exclusive LDR command for 16 bit values
lynxeyed_atsu	0:d920d64db582	1164	*/
lynxeyed_atsu	0:d920d64db582	1165	extern uint16_t __LDREXH(uint16_t *addr);
lynxeyed_atsu	0:d920d64db582	1166
lynxeyed_atsu	0:d920d64db582	1167	/**
lynxeyed_atsu	0:d920d64db582	1168	* @brief LDR Exclusive (32 bit)
lynxeyed_atsu	0:d920d64db582	1169	*
lynxeyed_atsu	0:d920d64db582	1170	* @param *addr address pointer
lynxeyed_atsu	0:d920d64db582	1171	* @return value of (*address)
lynxeyed_atsu	0:d920d64db582	1172	*
lynxeyed_atsu	0:d920d64db582	1173	* Exclusive LDR command for 32 bit values
lynxeyed_atsu	0:d920d64db582	1174	*/
lynxeyed_atsu	0:d920d64db582	1175	extern uint32_t __LDREXW(uint32_t *addr);
lynxeyed_atsu	0:d920d64db582	1176
lynxeyed_atsu	0:d920d64db582	1177	/**
lynxeyed_atsu	0:d920d64db582	1178	* @brief STR Exclusive (8 bit)
lynxeyed_atsu	0:d920d64db582	1179	*
lynxeyed_atsu	0:d920d64db582	1180	* @param value value to store
lynxeyed_atsu	0:d920d64db582	1181	* @param *addr address pointer
lynxeyed_atsu	0:d920d64db582	1182	* @return successful / failed
lynxeyed_atsu	0:d920d64db582	1183	*
lynxeyed_atsu	0:d920d64db582	1184	* Exclusive STR command for 8 bit values
lynxeyed_atsu	0:d920d64db582	1185	*/
lynxeyed_atsu	0:d920d64db582	1186	extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
lynxeyed_atsu	0:d920d64db582	1187
lynxeyed_atsu	0:d920d64db582	1188	/**
lynxeyed_atsu	0:d920d64db582	1189	* @brief STR Exclusive (16 bit)
lynxeyed_atsu	0:d920d64db582	1190	*
lynxeyed_atsu	0:d920d64db582	1191	* @param value value to store
lynxeyed_atsu	0:d920d64db582	1192	* @param *addr address pointer
lynxeyed_atsu	0:d920d64db582	1193	* @return successful / failed
lynxeyed_atsu	0:d920d64db582	1194	*
lynxeyed_atsu	0:d920d64db582	1195	* Exclusive STR command for 16 bit values
lynxeyed_atsu	0:d920d64db582	1196	*/
lynxeyed_atsu	0:d920d64db582	1197	extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
lynxeyed_atsu	0:d920d64db582	1198
lynxeyed_atsu	0:d920d64db582	1199	/**
lynxeyed_atsu	0:d920d64db582	1200	* @brief STR Exclusive (32 bit)
lynxeyed_atsu	0:d920d64db582	1201	*
lynxeyed_atsu	0:d920d64db582	1202	* @param value value to store
lynxeyed_atsu	0:d920d64db582	1203	* @param *addr address pointer
lynxeyed_atsu	0:d920d64db582	1204	* @return successful / failed
lynxeyed_atsu	0:d920d64db582	1205	*
lynxeyed_atsu	0:d920d64db582	1206	* Exclusive STR command for 32 bit values
lynxeyed_atsu	0:d920d64db582	1207	*/
lynxeyed_atsu	0:d920d64db582	1208	extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
lynxeyed_atsu	0:d920d64db582	1209
lynxeyed_atsu	0:d920d64db582	1210
lynxeyed_atsu	0:d920d64db582	1211
lynxeyed_atsu	0:d920d64db582	1212	#elif (defined (__GNUC__)) /------------------ GNU Compiler ---------------------/
lynxeyed_atsu	0:d920d64db582	1213	/* GNU gcc specific functions */
lynxeyed_atsu	0:d920d64db582	1214
lynxeyed_atsu	0:d920d64db582	1215	static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
lynxeyed_atsu	0:d920d64db582	1216	static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
lynxeyed_atsu	0:d920d64db582	1217
lynxeyed_atsu	0:d920d64db582	1218	static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
lynxeyed_atsu	0:d920d64db582	1219	static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
lynxeyed_atsu	0:d920d64db582	1220
lynxeyed_atsu	0:d920d64db582	1221	static __INLINE void __NOP() { __ASM volatile ("nop"); }
lynxeyed_atsu	0:d920d64db582	1222	static __INLINE void __WFI() { __ASM volatile ("wfi"); }
lynxeyed_atsu	0:d920d64db582	1223	static __INLINE void __WFE() { __ASM volatile ("wfe"); }
lynxeyed_atsu	0:d920d64db582	1224	static __INLINE void __SEV() { __ASM volatile ("sev"); }
lynxeyed_atsu	0:d920d64db582	1225	static __INLINE void __ISB() { __ASM volatile ("isb"); }
lynxeyed_atsu	0:d920d64db582	1226	static __INLINE void __DSB() { __ASM volatile ("dsb"); }
lynxeyed_atsu	0:d920d64db582	1227	static __INLINE void __DMB() { __ASM volatile ("dmb"); }
lynxeyed_atsu	0:d920d64db582	1228	static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
lynxeyed_atsu	0:d920d64db582	1229
lynxeyed_atsu	0:d920d64db582	1230
lynxeyed_atsu	0:d920d64db582	1231	/**
lynxeyed_atsu	0:d920d64db582	1232	* @brief Return the Process Stack Pointer
lynxeyed_atsu	0:d920d64db582	1233	*
lynxeyed_atsu	0:d920d64db582	1234	* @return ProcessStackPointer
lynxeyed_atsu	0:d920d64db582	1235	*
lynxeyed_atsu	0:d920d64db582	1236	* Return the actual process stack pointer
lynxeyed_atsu	0:d920d64db582	1237	*/
lynxeyed_atsu	0:d920d64db582	1238	extern uint32_t __get_PSP(void);
lynxeyed_atsu	0:d920d64db582	1239
lynxeyed_atsu	0:d920d64db582	1240	/**
lynxeyed_atsu	0:d920d64db582	1241	* @brief Set the Process Stack Pointer
lynxeyed_atsu	0:d920d64db582	1242	*
lynxeyed_atsu	0:d920d64db582	1243	* @param topOfProcStack Process Stack Pointer
lynxeyed_atsu	0:d920d64db582	1244	*
lynxeyed_atsu	0:d920d64db582	1245	* Assign the value ProcessStackPointer to the MSP
lynxeyed_atsu	0:d920d64db582	1246	* (process stack pointer) Cortex processor register
lynxeyed_atsu	0:d920d64db582	1247	*/
lynxeyed_atsu	0:d920d64db582	1248	extern void __set_PSP(uint32_t topOfProcStack);
lynxeyed_atsu	0:d920d64db582	1249
lynxeyed_atsu	0:d920d64db582	1250	/**
lynxeyed_atsu	0:d920d64db582	1251	* @brief Return the Main Stack Pointer
lynxeyed_atsu	0:d920d64db582	1252	*
lynxeyed_atsu	0:d920d64db582	1253	* @return Main Stack Pointer
lynxeyed_atsu	0:d920d64db582	1254	*
lynxeyed_atsu	0:d920d64db582	1255	* Return the current value of the MSP (main stack pointer)
lynxeyed_atsu	0:d920d64db582	1256	* Cortex processor register
lynxeyed_atsu	0:d920d64db582	1257	*/
lynxeyed_atsu	0:d920d64db582	1258	extern uint32_t __get_MSP(void);
lynxeyed_atsu	0:d920d64db582	1259
lynxeyed_atsu	0:d920d64db582	1260	/**
lynxeyed_atsu	0:d920d64db582	1261	* @brief Set the Main Stack Pointer
lynxeyed_atsu	0:d920d64db582	1262	*
lynxeyed_atsu	0:d920d64db582	1263	* @param topOfMainStack Main Stack Pointer
lynxeyed_atsu	0:d920d64db582	1264	*
lynxeyed_atsu	0:d920d64db582	1265	* Assign the value mainStackPointer to the MSP
lynxeyed_atsu	0:d920d64db582	1266	* (main stack pointer) Cortex processor register
lynxeyed_atsu	0:d920d64db582	1267	*/
lynxeyed_atsu	0:d920d64db582	1268	extern void __set_MSP(uint32_t topOfMainStack);
lynxeyed_atsu	0:d920d64db582	1269
lynxeyed_atsu	0:d920d64db582	1270	/**
lynxeyed_atsu	0:d920d64db582	1271	* @brief Return the Base Priority value
lynxeyed_atsu	0:d920d64db582	1272	*
lynxeyed_atsu	0:d920d64db582	1273	* @return BasePriority
lynxeyed_atsu	0:d920d64db582	1274	*
lynxeyed_atsu	0:d920d64db582	1275	* Return the content of the base priority register
lynxeyed_atsu	0:d920d64db582	1276	*/
lynxeyed_atsu	0:d920d64db582	1277	extern uint32_t __get_BASEPRI(void);
lynxeyed_atsu	0:d920d64db582	1278
lynxeyed_atsu	0:d920d64db582	1279	/**
lynxeyed_atsu	0:d920d64db582	1280	* @brief Set the Base Priority value
lynxeyed_atsu	0:d920d64db582	1281	*
lynxeyed_atsu	0:d920d64db582	1282	* @param basePri BasePriority
lynxeyed_atsu	0:d920d64db582	1283	*
lynxeyed_atsu	0:d920d64db582	1284	* Set the base priority register
lynxeyed_atsu	0:d920d64db582	1285	*/
lynxeyed_atsu	0:d920d64db582	1286	extern void __set_BASEPRI(uint32_t basePri);
lynxeyed_atsu	0:d920d64db582	1287
lynxeyed_atsu	0:d920d64db582	1288	/**
lynxeyed_atsu	0:d920d64db582	1289	* @brief Return the Priority Mask value
lynxeyed_atsu	0:d920d64db582	1290	*
lynxeyed_atsu	0:d920d64db582	1291	* @return PriMask
lynxeyed_atsu	0:d920d64db582	1292	*
lynxeyed_atsu	0:d920d64db582	1293	* Return state of the priority mask bit from the priority mask register
lynxeyed_atsu	0:d920d64db582	1294	*/
lynxeyed_atsu	0:d920d64db582	1295	extern uint32_t __get_PRIMASK(void);
lynxeyed_atsu	0:d920d64db582	1296
lynxeyed_atsu	0:d920d64db582	1297	/**
lynxeyed_atsu	0:d920d64db582	1298	* @brief Set the Priority Mask value
lynxeyed_atsu	0:d920d64db582	1299	*
lynxeyed_atsu	0:d920d64db582	1300	* @param priMask PriMask
lynxeyed_atsu	0:d920d64db582	1301	*
lynxeyed_atsu	0:d920d64db582	1302	* Set the priority mask bit in the priority mask register
lynxeyed_atsu	0:d920d64db582	1303	*/
lynxeyed_atsu	0:d920d64db582	1304	extern void __set_PRIMASK(uint32_t priMask);
lynxeyed_atsu	0:d920d64db582	1305
lynxeyed_atsu	0:d920d64db582	1306	/**
lynxeyed_atsu	0:d920d64db582	1307	* @brief Return the Fault Mask value
lynxeyed_atsu	0:d920d64db582	1308	*
lynxeyed_atsu	0:d920d64db582	1309	* @return FaultMask
lynxeyed_atsu	0:d920d64db582	1310	*
lynxeyed_atsu	0:d920d64db582	1311	* Return the content of the fault mask register
lynxeyed_atsu	0:d920d64db582	1312	*/
lynxeyed_atsu	0:d920d64db582	1313	extern uint32_t __get_FAULTMASK(void);
lynxeyed_atsu	0:d920d64db582	1314
lynxeyed_atsu	0:d920d64db582	1315	/**
lynxeyed_atsu	0:d920d64db582	1316	* @brief Set the Fault Mask value
lynxeyed_atsu	0:d920d64db582	1317	*
lynxeyed_atsu	0:d920d64db582	1318	* @param faultMask faultMask value
lynxeyed_atsu	0:d920d64db582	1319	*
lynxeyed_atsu	0:d920d64db582	1320	* Set the fault mask register
lynxeyed_atsu	0:d920d64db582	1321	*/
lynxeyed_atsu	0:d920d64db582	1322	extern void __set_FAULTMASK(uint32_t faultMask);
lynxeyed_atsu	0:d920d64db582	1323
lynxeyed_atsu	0:d920d64db582	1324	/**
lynxeyed_atsu	0:d920d64db582	1325	* @brief Return the Control Register value
lynxeyed_atsu	0:d920d64db582	1326	*
lynxeyed_atsu	0:d920d64db582	1327	* @return Control value
lynxeyed_atsu	0:d920d64db582	1328	*
lynxeyed_atsu	0:d920d64db582	1329	* Return the content of the control register
lynxeyed_atsu	0:d920d64db582	1330	*/
lynxeyed_atsu	0:d920d64db582	1331	extern uint32_t __get_CONTROL(void);
lynxeyed_atsu	0:d920d64db582	1332
lynxeyed_atsu	0:d920d64db582	1333	/**
lynxeyed_atsu	0:d920d64db582	1334	* @brief Set the Control Register value
lynxeyed_atsu	0:d920d64db582	1335	*
lynxeyed_atsu	0:d920d64db582	1336	* @param control Control value
lynxeyed_atsu	0:d920d64db582	1337	*
lynxeyed_atsu	0:d920d64db582	1338	* Set the control register
lynxeyed_atsu	0:d920d64db582	1339	*/
lynxeyed_atsu	0:d920d64db582	1340	extern void __set_CONTROL(uint32_t control);
lynxeyed_atsu	0:d920d64db582	1341
lynxeyed_atsu	0:d920d64db582	1342	/**
lynxeyed_atsu	0:d920d64db582	1343	* @brief Reverse byte order in integer value
lynxeyed_atsu	0:d920d64db582	1344	*
lynxeyed_atsu	0:d920d64db582	1345	* @param value value to reverse
lynxeyed_atsu	0:d920d64db582	1346	* @return reversed value
lynxeyed_atsu	0:d920d64db582	1347	*
lynxeyed_atsu	0:d920d64db582	1348	* Reverse byte order in integer value
lynxeyed_atsu	0:d920d64db582	1349	*/
lynxeyed_atsu	0:d920d64db582	1350	extern uint32_t __REV(uint32_t value);
lynxeyed_atsu	0:d920d64db582	1351
lynxeyed_atsu	0:d920d64db582	1352	/**
lynxeyed_atsu	0:d920d64db582	1353	* @brief Reverse byte order in unsigned short value
lynxeyed_atsu	0:d920d64db582	1354	*
lynxeyed_atsu	0:d920d64db582	1355	* @param value value to reverse
lynxeyed_atsu	0:d920d64db582	1356	* @return reversed value
lynxeyed_atsu	0:d920d64db582	1357	*
lynxeyed_atsu	0:d920d64db582	1358	* Reverse byte order in unsigned short value
lynxeyed_atsu	0:d920d64db582	1359	*/
lynxeyed_atsu	0:d920d64db582	1360	extern uint32_t __REV16(uint16_t value);
lynxeyed_atsu	0:d920d64db582	1361
lynxeyed_atsu	0:d920d64db582	1362	/**
lynxeyed_atsu	0:d920d64db582	1363	* @brief Reverse byte order in signed short value with sign extension to integer
lynxeyed_atsu	0:d920d64db582	1364	*
lynxeyed_atsu	0:d920d64db582	1365	* @param value value to reverse
lynxeyed_atsu	0:d920d64db582	1366	* @return reversed value
lynxeyed_atsu	0:d920d64db582	1367	*
lynxeyed_atsu	0:d920d64db582	1368	* Reverse byte order in signed short value with sign extension to integer
lynxeyed_atsu	0:d920d64db582	1369	*/
lynxeyed_atsu	0:d920d64db582	1370	extern int32_t __REVSH(int16_t value);
lynxeyed_atsu	0:d920d64db582	1371
lynxeyed_atsu	0:d920d64db582	1372	/**
lynxeyed_atsu	0:d920d64db582	1373	* @brief Reverse bit order of value
lynxeyed_atsu	0:d920d64db582	1374	*
lynxeyed_atsu	0:d920d64db582	1375	* @param value value to reverse
lynxeyed_atsu	0:d920d64db582	1376	* @return reversed value
lynxeyed_atsu	0:d920d64db582	1377	*
lynxeyed_atsu	0:d920d64db582	1378	* Reverse bit order of value
lynxeyed_atsu	0:d920d64db582	1379	*/
lynxeyed_atsu	0:d920d64db582	1380	extern uint32_t __RBIT(uint32_t value);
lynxeyed_atsu	0:d920d64db582	1381
lynxeyed_atsu	0:d920d64db582	1382	/**
lynxeyed_atsu	0:d920d64db582	1383	* @brief LDR Exclusive (8 bit)
lynxeyed_atsu	0:d920d64db582	1384	*
lynxeyed_atsu	0:d920d64db582	1385	* @param *addr address pointer
lynxeyed_atsu	0:d920d64db582	1386	* @return value of (*address)
lynxeyed_atsu	0:d920d64db582	1387	*
lynxeyed_atsu	0:d920d64db582	1388	* Exclusive LDR command for 8 bit value
lynxeyed_atsu	0:d920d64db582	1389	*/
lynxeyed_atsu	0:d920d64db582	1390	extern uint8_t __LDREXB(uint8_t *addr);
lynxeyed_atsu	0:d920d64db582	1391
lynxeyed_atsu	0:d920d64db582	1392	/**
lynxeyed_atsu	0:d920d64db582	1393	* @brief LDR Exclusive (16 bit)
lynxeyed_atsu	0:d920d64db582	1394	*
lynxeyed_atsu	0:d920d64db582	1395	* @param *addr address pointer
lynxeyed_atsu	0:d920d64db582	1396	* @return value of (*address)
lynxeyed_atsu	0:d920d64db582	1397	*
lynxeyed_atsu	0:d920d64db582	1398	* Exclusive LDR command for 16 bit values
lynxeyed_atsu	0:d920d64db582	1399	*/
lynxeyed_atsu	0:d920d64db582	1400	extern uint16_t __LDREXH(uint16_t *addr);
lynxeyed_atsu	0:d920d64db582	1401
lynxeyed_atsu	0:d920d64db582	1402	/**
lynxeyed_atsu	0:d920d64db582	1403	* @brief LDR Exclusive (32 bit)
lynxeyed_atsu	0:d920d64db582	1404	*
lynxeyed_atsu	0:d920d64db582	1405	* @param *addr address pointer
lynxeyed_atsu	0:d920d64db582	1406	* @return value of (*address)
lynxeyed_atsu	0:d920d64db582	1407	*
lynxeyed_atsu	0:d920d64db582	1408	* Exclusive LDR command for 32 bit values
lynxeyed_atsu	0:d920d64db582	1409	*/
lynxeyed_atsu	0:d920d64db582	1410	extern uint32_t __LDREXW(uint32_t *addr);
lynxeyed_atsu	0:d920d64db582	1411
lynxeyed_atsu	0:d920d64db582	1412	/**
lynxeyed_atsu	0:d920d64db582	1413	* @brief STR Exclusive (8 bit)
lynxeyed_atsu	0:d920d64db582	1414	*
lynxeyed_atsu	0:d920d64db582	1415	* @param value value to store
lynxeyed_atsu	0:d920d64db582	1416	* @param *addr address pointer
lynxeyed_atsu	0:d920d64db582	1417	* @return successful / failed
lynxeyed_atsu	0:d920d64db582	1418	*
lynxeyed_atsu	0:d920d64db582	1419	* Exclusive STR command for 8 bit values
lynxeyed_atsu	0:d920d64db582	1420	*/
lynxeyed_atsu	0:d920d64db582	1421	extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
lynxeyed_atsu	0:d920d64db582	1422
lynxeyed_atsu	0:d920d64db582	1423	/**
lynxeyed_atsu	0:d920d64db582	1424	* @brief STR Exclusive (16 bit)
lynxeyed_atsu	0:d920d64db582	1425	*
lynxeyed_atsu	0:d920d64db582	1426	* @param value value to store
lynxeyed_atsu	0:d920d64db582	1427	* @param *addr address pointer
lynxeyed_atsu	0:d920d64db582	1428	* @return successful / failed
lynxeyed_atsu	0:d920d64db582	1429	*
lynxeyed_atsu	0:d920d64db582	1430	* Exclusive STR command for 16 bit values
lynxeyed_atsu	0:d920d64db582	1431	*/
lynxeyed_atsu	0:d920d64db582	1432	extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
lynxeyed_atsu	0:d920d64db582	1433
lynxeyed_atsu	0:d920d64db582	1434	/**
lynxeyed_atsu	0:d920d64db582	1435	* @brief STR Exclusive (32 bit)
lynxeyed_atsu	0:d920d64db582	1436	*
lynxeyed_atsu	0:d920d64db582	1437	* @param value value to store
lynxeyed_atsu	0:d920d64db582	1438	* @param *addr address pointer
lynxeyed_atsu	0:d920d64db582	1439	* @return successful / failed
lynxeyed_atsu	0:d920d64db582	1440	*
lynxeyed_atsu	0:d920d64db582	1441	* Exclusive STR command for 32 bit values
lynxeyed_atsu	0:d920d64db582	1442	*/
lynxeyed_atsu	0:d920d64db582	1443	extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
lynxeyed_atsu	0:d920d64db582	1444
lynxeyed_atsu	0:d920d64db582	1445
lynxeyed_atsu	0:d920d64db582	1446	#elif (defined (__TASKING__)) /------------------ TASKING Compiler ---------------------/
lynxeyed_atsu	0:d920d64db582	1447	/* TASKING carm specific functions */
lynxeyed_atsu	0:d920d64db582	1448
lynxeyed_atsu	0:d920d64db582	1449	/*
lynxeyed_atsu	0:d920d64db582	1450	* The CMSIS functions have been implemented as intrinsics in the compiler.
lynxeyed_atsu	0:d920d64db582	1451	* Please use "carm -?i" to get an up to date list of all instrinsics,
lynxeyed_atsu	0:d920d64db582	1452	* Including the CMSIS ones.
lynxeyed_atsu	0:d920d64db582	1453	*/
lynxeyed_atsu	0:d920d64db582	1454
lynxeyed_atsu	0:d920d64db582	1455	#endif
lynxeyed_atsu	0:d920d64db582	1456
lynxeyed_atsu	0:d920d64db582	1457
lynxeyed_atsu	0:d920d64db582	1458	/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
lynxeyed_atsu	0:d920d64db582	1459	Core Function Interface containing:
lynxeyed_atsu	0:d920d64db582	1460	- Core NVIC Functions
lynxeyed_atsu	0:d920d64db582	1461	- Core SysTick Functions
lynxeyed_atsu	0:d920d64db582	1462	- Core Reset Functions
lynxeyed_atsu	0:d920d64db582	1463	*/
lynxeyed_atsu	0:d920d64db582	1464	/@{/
lynxeyed_atsu	0:d920d64db582	1465
lynxeyed_atsu	0:d920d64db582	1466
lynxeyed_atsu	0:d920d64db582	1467	/* ########################## NVIC functions #################################### */
lynxeyed_atsu	0:d920d64db582	1468
lynxeyed_atsu	0:d920d64db582	1469	/**
lynxeyed_atsu	0:d920d64db582	1470	* @brief Set the Priority Grouping in NVIC Interrupt Controller
lynxeyed_atsu	0:d920d64db582	1471	*
lynxeyed_atsu	0:d920d64db582	1472	* @param PriorityGroup is priority grouping field
lynxeyed_atsu	0:d920d64db582	1473	*
lynxeyed_atsu	0:d920d64db582	1474	* Set the priority grouping field using the required unlock sequence.
lynxeyed_atsu	0:d920d64db582	1475	* The parameter priority_grouping is assigned to the field
lynxeyed_atsu	0:d920d64db582	1476	* SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
lynxeyed_atsu	0:d920d64db582	1477	* In case of a conflict between priority grouping and available
lynxeyed_atsu	0:d920d64db582	1478	* priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
lynxeyed_atsu	0:d920d64db582	1479	*/
lynxeyed_atsu	0:d920d64db582	1480	static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
lynxeyed_atsu	0:d920d64db582	1481	{
lynxeyed_atsu	0:d920d64db582	1482	uint32_t reg_value;
lynxeyed_atsu	0:d920d64db582	1483	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
lynxeyed_atsu	0:d920d64db582	1484
lynxeyed_atsu	0:d920d64db582	1485	reg_value = SCB->AIRCR; /* read old register configuration */
lynxeyed_atsu	0:d920d64db582	1486	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
lynxeyed_atsu	0:d920d64db582	1487	reg_value = (reg_value \|
lynxeyed_atsu	0:d920d64db582	1488	(0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
lynxeyed_atsu	0:d920d64db582	1489	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
lynxeyed_atsu	0:d920d64db582	1490	SCB->AIRCR = reg_value;
lynxeyed_atsu	0:d920d64db582	1491	}
lynxeyed_atsu	0:d920d64db582	1492
lynxeyed_atsu	0:d920d64db582	1493	/**
lynxeyed_atsu	0:d920d64db582	1494	* @brief Get the Priority Grouping from NVIC Interrupt Controller
lynxeyed_atsu	0:d920d64db582	1495	*
lynxeyed_atsu	0:d920d64db582	1496	* @return priority grouping field
lynxeyed_atsu	0:d920d64db582	1497	*
lynxeyed_atsu	0:d920d64db582	1498	* Get the priority grouping from NVIC Interrupt Controller.
lynxeyed_atsu	0:d920d64db582	1499	* priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
lynxeyed_atsu	0:d920d64db582	1500	*/
lynxeyed_atsu	0:d920d64db582	1501	static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
lynxeyed_atsu	0:d920d64db582	1502	{
lynxeyed_atsu	0:d920d64db582	1503	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
lynxeyed_atsu	0:d920d64db582	1504	}
lynxeyed_atsu	0:d920d64db582	1505
lynxeyed_atsu	0:d920d64db582	1506	/**
lynxeyed_atsu	0:d920d64db582	1507	* @brief Enable Interrupt in NVIC Interrupt Controller
lynxeyed_atsu	0:d920d64db582	1508	*
lynxeyed_atsu	0:d920d64db582	1509	* @param IRQn The positive number of the external interrupt to enable
lynxeyed_atsu	0:d920d64db582	1510	*
lynxeyed_atsu	0:d920d64db582	1511	* Enable a device specific interupt in the NVIC interrupt controller.
lynxeyed_atsu	0:d920d64db582	1512	* The interrupt number cannot be a negative value.
lynxeyed_atsu	0:d920d64db582	1513	*/
lynxeyed_atsu	0:d920d64db582	1514	static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
lynxeyed_atsu	0:d920d64db582	1515	{
lynxeyed_atsu	0:d920d64db582	1516	NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
lynxeyed_atsu	0:d920d64db582	1517	}
lynxeyed_atsu	0:d920d64db582	1518
lynxeyed_atsu	0:d920d64db582	1519	/**
lynxeyed_atsu	0:d920d64db582	1520	* @brief Disable the interrupt line for external interrupt specified
lynxeyed_atsu	0:d920d64db582	1521	*
lynxeyed_atsu	0:d920d64db582	1522	* @param IRQn The positive number of the external interrupt to disable
lynxeyed_atsu	0:d920d64db582	1523	*
lynxeyed_atsu	0:d920d64db582	1524	* Disable a device specific interupt in the NVIC interrupt controller.
lynxeyed_atsu	0:d920d64db582	1525	* The interrupt number cannot be a negative value.
lynxeyed_atsu	0:d920d64db582	1526	*/
lynxeyed_atsu	0:d920d64db582	1527	static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
lynxeyed_atsu	0:d920d64db582	1528	{
lynxeyed_atsu	0:d920d64db582	1529	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
lynxeyed_atsu	0:d920d64db582	1530	}
lynxeyed_atsu	0:d920d64db582	1531
lynxeyed_atsu	0:d920d64db582	1532	/**
lynxeyed_atsu	0:d920d64db582	1533	* @brief Read the interrupt pending bit for a device specific interrupt source
lynxeyed_atsu	0:d920d64db582	1534	*
lynxeyed_atsu	0:d920d64db582	1535	* @param IRQn The number of the device specifc interrupt
lynxeyed_atsu	0:d920d64db582	1536	* @return 1 = interrupt pending, 0 = interrupt not pending
lynxeyed_atsu	0:d920d64db582	1537	*
lynxeyed_atsu	0:d920d64db582	1538	* Read the pending register in NVIC and return 1 if its status is pending,
lynxeyed_atsu	0:d920d64db582	1539	* otherwise it returns 0
lynxeyed_atsu	0:d920d64db582	1540	*/
lynxeyed_atsu	0:d920d64db582	1541	static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
lynxeyed_atsu	0:d920d64db582	1542	{
lynxeyed_atsu	0:d920d64db582	1543	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
lynxeyed_atsu	0:d920d64db582	1544	}
lynxeyed_atsu	0:d920d64db582	1545
lynxeyed_atsu	0:d920d64db582	1546	/**
lynxeyed_atsu	0:d920d64db582	1547	* @brief Set the pending bit for an external interrupt
lynxeyed_atsu	0:d920d64db582	1548	*
lynxeyed_atsu	0:d920d64db582	1549	* @param IRQn The number of the interrupt for set pending
lynxeyed_atsu	0:d920d64db582	1550	*
lynxeyed_atsu	0:d920d64db582	1551	* Set the pending bit for the specified interrupt.
lynxeyed_atsu	0:d920d64db582	1552	* The interrupt number cannot be a negative value.
lynxeyed_atsu	0:d920d64db582	1553	*/
lynxeyed_atsu	0:d920d64db582	1554	static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
lynxeyed_atsu	0:d920d64db582	1555	{
lynxeyed_atsu	0:d920d64db582	1556	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
lynxeyed_atsu	0:d920d64db582	1557	}
lynxeyed_atsu	0:d920d64db582	1558
lynxeyed_atsu	0:d920d64db582	1559	/**
lynxeyed_atsu	0:d920d64db582	1560	* @brief Clear the pending bit for an external interrupt
lynxeyed_atsu	0:d920d64db582	1561	*
lynxeyed_atsu	0:d920d64db582	1562	* @param IRQn The number of the interrupt for clear pending
lynxeyed_atsu	0:d920d64db582	1563	*
lynxeyed_atsu	0:d920d64db582	1564	* Clear the pending bit for the specified interrupt.
lynxeyed_atsu	0:d920d64db582	1565	* The interrupt number cannot be a negative value.
lynxeyed_atsu	0:d920d64db582	1566	*/
lynxeyed_atsu	0:d920d64db582	1567	static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
lynxeyed_atsu	0:d920d64db582	1568	{
lynxeyed_atsu	0:d920d64db582	1569	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
lynxeyed_atsu	0:d920d64db582	1570	}
lynxeyed_atsu	0:d920d64db582	1571
lynxeyed_atsu	0:d920d64db582	1572	/**
lynxeyed_atsu	0:d920d64db582	1573	* @brief Read the active bit for an external interrupt
lynxeyed_atsu	0:d920d64db582	1574	*
lynxeyed_atsu	0:d920d64db582	1575	* @param IRQn The number of the interrupt for read active bit
lynxeyed_atsu	0:d920d64db582	1576	* @return 1 = interrupt active, 0 = interrupt not active
lynxeyed_atsu	0:d920d64db582	1577	*
lynxeyed_atsu	0:d920d64db582	1578	* Read the active register in NVIC and returns 1 if its status is active,
lynxeyed_atsu	0:d920d64db582	1579	* otherwise it returns 0.
lynxeyed_atsu	0:d920d64db582	1580	*/
lynxeyed_atsu	0:d920d64db582	1581	static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
lynxeyed_atsu	0:d920d64db582	1582	{
lynxeyed_atsu	0:d920d64db582	1583	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
lynxeyed_atsu	0:d920d64db582	1584	}
lynxeyed_atsu	0:d920d64db582	1585
lynxeyed_atsu	0:d920d64db582	1586	/**
lynxeyed_atsu	0:d920d64db582	1587	* @brief Set the priority for an interrupt
lynxeyed_atsu	0:d920d64db582	1588	*
lynxeyed_atsu	0:d920d64db582	1589	* @param IRQn The number of the interrupt for set priority
lynxeyed_atsu	0:d920d64db582	1590	* @param priority The priority to set
lynxeyed_atsu	0:d920d64db582	1591	*
lynxeyed_atsu	0:d920d64db582	1592	* Set the priority for the specified interrupt. The interrupt
lynxeyed_atsu	0:d920d64db582	1593	* number can be positive to specify an external (device specific)
lynxeyed_atsu	0:d920d64db582	1594	* interrupt, or negative to specify an internal (core) interrupt.
lynxeyed_atsu	0:d920d64db582	1595	*
lynxeyed_atsu	0:d920d64db582	1596	* Note: The priority cannot be set for every core interrupt.
lynxeyed_atsu	0:d920d64db582	1597	*/
lynxeyed_atsu	0:d920d64db582	1598	static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
lynxeyed_atsu	0:d920d64db582	1599	{
lynxeyed_atsu	0:d920d64db582	1600	if(IRQn < 0) {
lynxeyed_atsu	0:d920d64db582	1601	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
lynxeyed_atsu	0:d920d64db582	1602	else {
lynxeyed_atsu	0:d920d64db582	1603	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
lynxeyed_atsu	0:d920d64db582	1604	}
lynxeyed_atsu	0:d920d64db582	1605
lynxeyed_atsu	0:d920d64db582	1606	/**
lynxeyed_atsu	0:d920d64db582	1607	* @brief Read the priority for an interrupt
lynxeyed_atsu	0:d920d64db582	1608	*
lynxeyed_atsu	0:d920d64db582	1609	* @param IRQn The number of the interrupt for get priority
lynxeyed_atsu	0:d920d64db582	1610	* @return The priority for the interrupt
lynxeyed_atsu	0:d920d64db582	1611	*
lynxeyed_atsu	0:d920d64db582	1612	* Read the priority for the specified interrupt. The interrupt
lynxeyed_atsu	0:d920d64db582	1613	* number can be positive to specify an external (device specific)
lynxeyed_atsu	0:d920d64db582	1614	* interrupt, or negative to specify an internal (core) interrupt.
lynxeyed_atsu	0:d920d64db582	1615	*
lynxeyed_atsu	0:d920d64db582	1616	* The returned priority value is automatically aligned to the implemented
lynxeyed_atsu	0:d920d64db582	1617	* priority bits of the microcontroller.
lynxeyed_atsu	0:d920d64db582	1618	*
lynxeyed_atsu	0:d920d64db582	1619	* Note: The priority cannot be set for every core interrupt.
lynxeyed_atsu	0:d920d64db582	1620	*/
lynxeyed_atsu	0:d920d64db582	1621	static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
lynxeyed_atsu	0:d920d64db582	1622	{
lynxeyed_atsu	0:d920d64db582	1623
lynxeyed_atsu	0:d920d64db582	1624	if(IRQn < 0) {
lynxeyed_atsu	0:d920d64db582	1625	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
lynxeyed_atsu	0:d920d64db582	1626	else {
lynxeyed_atsu	0:d920d64db582	1627	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
lynxeyed_atsu	0:d920d64db582	1628	}
lynxeyed_atsu	0:d920d64db582	1629
lynxeyed_atsu	0:d920d64db582	1630
lynxeyed_atsu	0:d920d64db582	1631	/**
lynxeyed_atsu	0:d920d64db582	1632	* @brief Encode the priority for an interrupt
lynxeyed_atsu	0:d920d64db582	1633	*
lynxeyed_atsu	0:d920d64db582	1634	* @param PriorityGroup The used priority group
lynxeyed_atsu	0:d920d64db582	1635	* @param PreemptPriority The preemptive priority value (starting from 0)
lynxeyed_atsu	0:d920d64db582	1636	* @param SubPriority The sub priority value (starting from 0)
lynxeyed_atsu	0:d920d64db582	1637	* @return The encoded priority for the interrupt
lynxeyed_atsu	0:d920d64db582	1638	*
lynxeyed_atsu	0:d920d64db582	1639	* Encode the priority for an interrupt with the given priority group,
lynxeyed_atsu	0:d920d64db582	1640	* preemptive priority value and sub priority value.
lynxeyed_atsu	0:d920d64db582	1641	* In case of a conflict between priority grouping and available
lynxeyed_atsu	0:d920d64db582	1642	* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
lynxeyed_atsu	0:d920d64db582	1643	*
lynxeyed_atsu	0:d920d64db582	1644	* The returned priority value can be used for NVIC_SetPriority(...) function
lynxeyed_atsu	0:d920d64db582	1645	*/
lynxeyed_atsu	0:d920d64db582	1646	static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
lynxeyed_atsu	0:d920d64db582	1647	{
lynxeyed_atsu	0:d920d64db582	1648	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
lynxeyed_atsu	0:d920d64db582	1649	uint32_t PreemptPriorityBits;
lynxeyed_atsu	0:d920d64db582	1650	uint32_t SubPriorityBits;
lynxeyed_atsu	0:d920d64db582	1651
lynxeyed_atsu	0:d920d64db582	1652	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
lynxeyed_atsu	0:d920d64db582	1653	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
lynxeyed_atsu	0:d920d64db582	1654
lynxeyed_atsu	0:d920d64db582	1655	return (
lynxeyed_atsu	0:d920d64db582	1656	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
lynxeyed_atsu	0:d920d64db582	1657	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
lynxeyed_atsu	0:d920d64db582	1658	);
lynxeyed_atsu	0:d920d64db582	1659	}
lynxeyed_atsu	0:d920d64db582	1660
lynxeyed_atsu	0:d920d64db582	1661
lynxeyed_atsu	0:d920d64db582	1662	/**
lynxeyed_atsu	0:d920d64db582	1663	* @brief Decode the priority of an interrupt
lynxeyed_atsu	0:d920d64db582	1664	*
lynxeyed_atsu	0:d920d64db582	1665	* @param Priority The priority for the interrupt
lynxeyed_atsu	0:d920d64db582	1666	* @param PriorityGroup The used priority group
lynxeyed_atsu	0:d920d64db582	1667	* @param pPreemptPriority The preemptive priority value (starting from 0)
lynxeyed_atsu	0:d920d64db582	1668	* @param pSubPriority The sub priority value (starting from 0)
lynxeyed_atsu	0:d920d64db582	1669	*
lynxeyed_atsu	0:d920d64db582	1670	* Decode an interrupt priority value with the given priority group to
lynxeyed_atsu	0:d920d64db582	1671	* preemptive priority value and sub priority value.
lynxeyed_atsu	0:d920d64db582	1672	* In case of a conflict between priority grouping and available
lynxeyed_atsu	0:d920d64db582	1673	* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
lynxeyed_atsu	0:d920d64db582	1674	*
lynxeyed_atsu	0:d920d64db582	1675	* The priority value can be retrieved with NVIC_GetPriority(...) function
lynxeyed_atsu	0:d920d64db582	1676	*/
lynxeyed_atsu	0:d920d64db582	1677	static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
lynxeyed_atsu	0:d920d64db582	1678	{
lynxeyed_atsu	0:d920d64db582	1679	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
lynxeyed_atsu	0:d920d64db582	1680	uint32_t PreemptPriorityBits;
lynxeyed_atsu	0:d920d64db582	1681	uint32_t SubPriorityBits;
lynxeyed_atsu	0:d920d64db582	1682
lynxeyed_atsu	0:d920d64db582	1683	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
lynxeyed_atsu	0:d920d64db582	1684	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
lynxeyed_atsu	0:d920d64db582	1685
lynxeyed_atsu	0:d920d64db582	1686	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
lynxeyed_atsu	0:d920d64db582	1687	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
lynxeyed_atsu	0:d920d64db582	1688	}
lynxeyed_atsu	0:d920d64db582	1689
lynxeyed_atsu	0:d920d64db582	1690
lynxeyed_atsu	0:d920d64db582	1691
lynxeyed_atsu	0:d920d64db582	1692	/* ################################## SysTick function ############################################ */
lynxeyed_atsu	0:d920d64db582	1693
lynxeyed_atsu	0:d920d64db582	1694	#if (!defined (__Vendor_SysTickConfig)) \|\| (__Vendor_SysTickConfig == 0)
lynxeyed_atsu	0:d920d64db582	1695
lynxeyed_atsu	0:d920d64db582	1696	/**
lynxeyed_atsu	0:d920d64db582	1697	* @brief Initialize and start the SysTick counter and its interrupt.
lynxeyed_atsu	0:d920d64db582	1698	*
lynxeyed_atsu	0:d920d64db582	1699	* @param ticks number of ticks between two interrupts
lynxeyed_atsu	0:d920d64db582	1700	* @return 1 = failed, 0 = successful
lynxeyed_atsu	0:d920d64db582	1701	*
lynxeyed_atsu	0:d920d64db582	1702	* Initialise the system tick timer and its interrupt and start the
lynxeyed_atsu	0:d920d64db582	1703	* system tick timer / counter in free running mode to generate
lynxeyed_atsu	0:d920d64db582	1704	* periodical interrupts.
lynxeyed_atsu	0:d920d64db582	1705	*/
lynxeyed_atsu	0:d920d64db582	1706	static __INLINE uint32_t SysTick_Config(uint32_t ticks)
lynxeyed_atsu	0:d920d64db582	1707	{
lynxeyed_atsu	0:d920d64db582	1708	if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
lynxeyed_atsu	0:d920d64db582	1709
lynxeyed_atsu	0:d920d64db582	1710	SysTick->RELOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
lynxeyed_atsu	0:d920d64db582	1711	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
lynxeyed_atsu	0:d920d64db582	1712	SysTick->CURR = 0; /* Load the SysTick Counter Value */
lynxeyed_atsu	0:d920d64db582	1713	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
lynxeyed_atsu	0:d920d64db582	1714	SysTick_CTRL_TICKINT_Msk \|
lynxeyed_atsu	0:d920d64db582	1715	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
lynxeyed_atsu	0:d920d64db582	1716	return (0); /* Function successful */
lynxeyed_atsu	0:d920d64db582	1717	}
lynxeyed_atsu	0:d920d64db582	1718
lynxeyed_atsu	0:d920d64db582	1719	#endif
lynxeyed_atsu	0:d920d64db582	1720
lynxeyed_atsu	0:d920d64db582	1721
lynxeyed_atsu	0:d920d64db582	1722
lynxeyed_atsu	0:d920d64db582	1723
lynxeyed_atsu	0:d920d64db582	1724	/* ################################## Reset function ############################################ */
lynxeyed_atsu	0:d920d64db582	1725
lynxeyed_atsu	0:d920d64db582	1726	/**
lynxeyed_atsu	0:d920d64db582	1727	* @brief Initiate a system reset request.
lynxeyed_atsu	0:d920d64db582	1728	*
lynxeyed_atsu	0:d920d64db582	1729	* Initiate a system reset request to reset the MCU
lynxeyed_atsu	0:d920d64db582	1730	*/
lynxeyed_atsu	0:d920d64db582	1731	static __INLINE void NVIC_SystemReset(void)
lynxeyed_atsu	0:d920d64db582	1732	{
lynxeyed_atsu	0:d920d64db582	1733	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
lynxeyed_atsu	0:d920d64db582	1734	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
lynxeyed_atsu	0:d920d64db582	1735	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
lynxeyed_atsu	0:d920d64db582	1736	__DSB(); /* Ensure completion of memory access */
lynxeyed_atsu	0:d920d64db582	1737	while(1); /* wait until reset */
lynxeyed_atsu	0:d920d64db582	1738	}
lynxeyed_atsu	0:d920d64db582	1739
lynxeyed_atsu	0:d920d64db582	1740	/@}/ /* end of group CMSIS_CM3_Core_FunctionInterface */
lynxeyed_atsu	0:d920d64db582	1741
lynxeyed_atsu	0:d920d64db582	1742
lynxeyed_atsu	0:d920d64db582	1743
lynxeyed_atsu	0:d920d64db582	1744	/* ##################################### Debug In/Output function ########################################### */
lynxeyed_atsu	0:d920d64db582	1745
lynxeyed_atsu	0:d920d64db582	1746	/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
lynxeyed_atsu	0:d920d64db582	1747	Core Debug Interface containing:
lynxeyed_atsu	0:d920d64db582	1748	- Core Debug Receive / Transmit Functions
lynxeyed_atsu	0:d920d64db582	1749	- Core Debug Defines
lynxeyed_atsu	0:d920d64db582	1750	- Core Debug Variables
lynxeyed_atsu	0:d920d64db582	1751	*/
lynxeyed_atsu	0:d920d64db582	1752	/@{/
lynxeyed_atsu	0:d920d64db582	1753
lynxeyed_atsu	0:d920d64db582	1754	extern volatile int ITM_RxBuffer; /!< variable to receive characters /
lynxeyed_atsu	0:d920d64db582	1755	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< value identifying ITM_RxBuffer is ready for next character /
lynxeyed_atsu	0:d920d64db582	1756
lynxeyed_atsu	0:d920d64db582	1757
lynxeyed_atsu	0:d920d64db582	1758	/**
lynxeyed_atsu	0:d920d64db582	1759	* @brief Outputs a character via the ITM channel 0
lynxeyed_atsu	0:d920d64db582	1760	*
lynxeyed_atsu	0:d920d64db582	1761	* @param ch character to output
lynxeyed_atsu	0:d920d64db582	1762	* @return character to output
lynxeyed_atsu	0:d920d64db582	1763	*
lynxeyed_atsu	0:d920d64db582	1764	* The function outputs a character via the ITM channel 0.
lynxeyed_atsu	0:d920d64db582	1765	* The function returns when no debugger is connected that has booked the output.
lynxeyed_atsu	0:d920d64db582	1766	* It is blocking when a debugger is connected, but the previous character send is not transmitted.
lynxeyed_atsu	0:d920d64db582	1767	*/
lynxeyed_atsu	0:d920d64db582	1768	static __INLINE uint32_t ITM_SendChar (uint32_t ch)
lynxeyed_atsu	0:d920d64db582	1769	{
lynxeyed_atsu	0:d920d64db582	1770	if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
lynxeyed_atsu	0:d920d64db582	1771	(ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
lynxeyed_atsu	0:d920d64db582	1772	(ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
lynxeyed_atsu	0:d920d64db582	1773	{
lynxeyed_atsu	0:d920d64db582	1774	while (ITM->PORT[0].u32 == 0);
lynxeyed_atsu	0:d920d64db582	1775	ITM->PORT[0].u8 = (uint8_t) ch;
lynxeyed_atsu	0:d920d64db582	1776	}
lynxeyed_atsu	0:d920d64db582	1777	return (ch);
lynxeyed_atsu	0:d920d64db582	1778	}
lynxeyed_atsu	0:d920d64db582	1779
lynxeyed_atsu	0:d920d64db582	1780
lynxeyed_atsu	0:d920d64db582	1781	/**
lynxeyed_atsu	0:d920d64db582	1782	* @brief Inputs a character via variable ITM_RxBuffer
lynxeyed_atsu	0:d920d64db582	1783	*
lynxeyed_atsu	0:d920d64db582	1784	* @return received character, -1 = no character received
lynxeyed_atsu	0:d920d64db582	1785	*
lynxeyed_atsu	0:d920d64db582	1786	* The function inputs a character via variable ITM_RxBuffer.
lynxeyed_atsu	0:d920d64db582	1787	* The function returns when no debugger is connected that has booked the output.
lynxeyed_atsu	0:d920d64db582	1788	* It is blocking when a debugger is connected, but the previous character send is not transmitted.
lynxeyed_atsu	0:d920d64db582	1789	*/
lynxeyed_atsu	0:d920d64db582	1790	static __INLINE int ITM_ReceiveChar (void) {
lynxeyed_atsu	0:d920d64db582	1791	int ch = -1; /* no character available */
lynxeyed_atsu	0:d920d64db582	1792
lynxeyed_atsu	0:d920d64db582	1793	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
lynxeyed_atsu	0:d920d64db582	1794	ch = ITM_RxBuffer;
lynxeyed_atsu	0:d920d64db582	1795	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
lynxeyed_atsu	0:d920d64db582	1796	}
lynxeyed_atsu	0:d920d64db582	1797
lynxeyed_atsu	0:d920d64db582	1798	return (ch);
lynxeyed_atsu	0:d920d64db582	1799	}
lynxeyed_atsu	0:d920d64db582	1800
lynxeyed_atsu	0:d920d64db582	1801
lynxeyed_atsu	0:d920d64db582	1802	/**
lynxeyed_atsu	0:d920d64db582	1803	* @brief Check if a character via variable ITM_RxBuffer is available
lynxeyed_atsu	0:d920d64db582	1804	*
lynxeyed_atsu	0:d920d64db582	1805	* @return 1 = character available, 0 = no character available
lynxeyed_atsu	0:d920d64db582	1806	*
lynxeyed_atsu	0:d920d64db582	1807	* The function checks variable ITM_RxBuffer whether a character is available or not.
lynxeyed_atsu	0:d920d64db582	1808	* The function returns '1' if a character is available and '0' if no character is available.
lynxeyed_atsu	0:d920d64db582	1809	*/
lynxeyed_atsu	0:d920d64db582	1810	static __INLINE int ITM_CheckChar (void) {
lynxeyed_atsu	0:d920d64db582	1811
lynxeyed_atsu	0:d920d64db582	1812	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
lynxeyed_atsu	0:d920d64db582	1813	return (0); /* no character available */
lynxeyed_atsu	0:d920d64db582	1814	} else {
lynxeyed_atsu	0:d920d64db582	1815	return (1); /* character available */
lynxeyed_atsu	0:d920d64db582	1816	}
lynxeyed_atsu	0:d920d64db582	1817	}
lynxeyed_atsu	0:d920d64db582	1818
lynxeyed_atsu	0:d920d64db582	1819	/@}/ /* end of group CMSIS_CM3_core_DebugInterface */
lynxeyed_atsu	0:d920d64db582	1820
lynxeyed_atsu	0:d920d64db582	1821
lynxeyed_atsu	0:d920d64db582	1822	#ifdef __cplusplus
lynxeyed_atsu	0:d920d64db582	1823	}
lynxeyed_atsu	0:d920d64db582	1824	#endif
lynxeyed_atsu	0:d920d64db582	1825
lynxeyed_atsu	0:d920d64db582	1826	/@}/ /* end of group CMSIS_CM3_core_definitions */
lynxeyed_atsu	0:d920d64db582	1827
lynxeyed_atsu	0:d920d64db582	1828	#endif /* __CM3_CORE_H__ */
lynxeyed_atsu	0:d920d64db582	1829
lynxeyed_atsu	0:d920d64db582	1830	/**
lynxeyed_atsu	0:d920d64db582	1831	* @}
lynxeyed_atsu	0:d920d64db582	1832	*/
lynxeyed_atsu	0:d920d64db582	1833
lynxeyed_atsu	0:d920d64db582	1834	/lint -restore /

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	30 Mar 2011
Imports:	5
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	2

I2S_Example/core_cm3.h@0:d920d64db582, 2011-03-30 (annotated)

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