xeye_ atsu / Mbed 2 deprecated I2S_AIC23B_RiceGolomb

パラメータを適応変化させる事により圧縮率を向上させた動的ライス・ゴロム符号を利用した可逆圧縮方式。圧縮ソフト、圧縮率のMATLABシミュレーションは詳細はInterface誌2011年8月号に掲載されるRX62Nマイコン連動特集にて掲載予定。

Dependencies:   mbed

I2S_Example/lpc17xx_uart.h@0:d920d64db582, 2011-03-30 (annotated)

Committer:
lynxeyed_atsu
Date:
Wed Mar 30 06:05:24 2011 +0000
Revision:
0:d920d64db582
alpha

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lynxeyed_atsu 0:d920d64db582 1 /***********************************************************************//**
lynxeyed_atsu 0:d920d64db582 2 * @file lpc17xx_uart.h
lynxeyed_atsu 0:d920d64db582 3 * @brief Contains all macro definitions and function prototypes
lynxeyed_atsu 0:d920d64db582 4 * support for UART firmware library on LPC17xx
lynxeyed_atsu 0:d920d64db582 5 * @version 3.0
lynxeyed_atsu 0:d920d64db582 6 * @date 18. June. 2010
lynxeyed_atsu 0:d920d64db582 7 * @author NXP MCU SW Application Team
lynxeyed_atsu 0:d920d64db582 8 **************************************************************************
lynxeyed_atsu 0:d920d64db582 9 * Software that is described herein is for illustrative purposes only
lynxeyed_atsu 0:d920d64db582 10 * which provides customers with programming information regarding the
lynxeyed_atsu 0:d920d64db582 11 * products. This software is supplied "AS IS" without any warranties.
lynxeyed_atsu 0:d920d64db582 12 * NXP Semiconductors assumes no responsibility or liability for the
lynxeyed_atsu 0:d920d64db582 13 * use of the software, conveys no license or title under any patent,
lynxeyed_atsu 0:d920d64db582 14 * copyright, or mask work right to the product. NXP Semiconductors
lynxeyed_atsu 0:d920d64db582 15 * reserves the right to make changes in the software without
lynxeyed_atsu 0:d920d64db582 16 * notification. NXP Semiconductors also make no representation or
lynxeyed_atsu 0:d920d64db582 17 * warranty that such application will be suitable for the specified
lynxeyed_atsu 0:d920d64db582 18 * use without further testing or modification.
lynxeyed_atsu 0:d920d64db582 19 **************************************************************************/
lynxeyed_atsu 0:d920d64db582 20
lynxeyed_atsu 0:d920d64db582 21 /* Peripheral group ----------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 22 /** @defgroup UART UART
lynxeyed_atsu 0:d920d64db582 23 * @ingroup LPC1700CMSIS_FwLib_Drivers
lynxeyed_atsu 0:d920d64db582 24 * @{
lynxeyed_atsu 0:d920d64db582 25 */
lynxeyed_atsu 0:d920d64db582 26
lynxeyed_atsu 0:d920d64db582 27 #ifndef __LPC17XX_UART_H
lynxeyed_atsu 0:d920d64db582 28 #define __LPC17XX_UART_H
lynxeyed_atsu 0:d920d64db582 29
lynxeyed_atsu 0:d920d64db582 30 /* Includes ------------------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 31 #include "LPC17xx.h"
lynxeyed_atsu 0:d920d64db582 32 #include "lpc_types.h"
lynxeyed_atsu 0:d920d64db582 33
lynxeyed_atsu 0:d920d64db582 34
lynxeyed_atsu 0:d920d64db582 35 #ifdef __cplusplus
lynxeyed_atsu 0:d920d64db582 36 extern "C"
lynxeyed_atsu 0:d920d64db582 37 {
lynxeyed_atsu 0:d920d64db582 38 #endif
lynxeyed_atsu 0:d920d64db582 39
lynxeyed_atsu 0:d920d64db582 40 /* Public Macros -------------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 41 /** @defgroup UART_Public_Macros UART Public Macros
lynxeyed_atsu 0:d920d64db582 42 * @{
lynxeyed_atsu 0:d920d64db582 43 */
lynxeyed_atsu 0:d920d64db582 44
lynxeyed_atsu 0:d920d64db582 45 /** UART time-out definitions in case of using Read() and Write function
lynxeyed_atsu 0:d920d64db582 46 * with Blocking Flag mode
lynxeyed_atsu 0:d920d64db582 47 */
lynxeyed_atsu 0:d920d64db582 48 #define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL)
lynxeyed_atsu 0:d920d64db582 49
lynxeyed_atsu 0:d920d64db582 50 /**
lynxeyed_atsu 0:d920d64db582 51 * @}
lynxeyed_atsu 0:d920d64db582 52 */
lynxeyed_atsu 0:d920d64db582 53
lynxeyed_atsu 0:d920d64db582 54 /* Private Macros ------------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 55 /** @defgroup UART_Private_Macros UART Private Macros
lynxeyed_atsu 0:d920d64db582 56 * @{
lynxeyed_atsu 0:d920d64db582 57 */
lynxeyed_atsu 0:d920d64db582 58
lynxeyed_atsu 0:d920d64db582 59 /* Accepted Error baud rate value (in percent unit) */
lynxeyed_atsu 0:d920d64db582 60 #define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */
lynxeyed_atsu 0:d920d64db582 61
lynxeyed_atsu 0:d920d64db582 62
lynxeyed_atsu 0:d920d64db582 63 /* --------------------- BIT DEFINITIONS -------------------------------------- */
lynxeyed_atsu 0:d920d64db582 64 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 65 * Macro defines for Macro defines for UARTn Receiver Buffer Register
lynxeyed_atsu 0:d920d64db582 66 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 67 #define UART_RBR_MASKBIT ((uint8_t)0xFF) /*!< UART Received Buffer mask bit (8 bits) */
lynxeyed_atsu 0:d920d64db582 68
lynxeyed_atsu 0:d920d64db582 69 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 70 * Macro defines for Macro defines for UARTn Transmit Holding Register
lynxeyed_atsu 0:d920d64db582 71 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 72 #define UART_THR_MASKBIT ((uint8_t)0xFF) /*!< UART Transmit Holding mask bit (8 bits) */
lynxeyed_atsu 0:d920d64db582 73
lynxeyed_atsu 0:d920d64db582 74 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 75 * Macro defines for Macro defines for UARTn Divisor Latch LSB register
lynxeyed_atsu 0:d920d64db582 76 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 77 #define UART_LOAD_DLL(div) ((div) & 0xFF) /**< Macro for loading least significant halfs of divisors */
lynxeyed_atsu 0:d920d64db582 78 #define UART_DLL_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */
lynxeyed_atsu 0:d920d64db582 79
lynxeyed_atsu 0:d920d64db582 80 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 81 * Macro defines for Macro defines for UARTn Divisor Latch MSB register
lynxeyed_atsu 0:d920d64db582 82 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 83 #define UART_DLM_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch MSB bit mask */
lynxeyed_atsu 0:d920d64db582 84 #define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /**< Macro for loading most significant halfs of divisors */
lynxeyed_atsu 0:d920d64db582 85
lynxeyed_atsu 0:d920d64db582 86 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 87 * Macro defines for Macro defines for UART interrupt enable register
lynxeyed_atsu 0:d920d64db582 88 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 89 #define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /*!< RBR Interrupt enable*/
lynxeyed_atsu 0:d920d64db582 90 #define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /*!< THR Interrupt enable*/
lynxeyed_atsu 0:d920d64db582 91 #define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /*!< RX line status interrupt enable*/
lynxeyed_atsu 0:d920d64db582 92 #define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /*!< Modem status interrupt enable */
lynxeyed_atsu 0:d920d64db582 93 #define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /*!< CTS1 signal transition interrupt enable */
lynxeyed_atsu 0:d920d64db582 94 #define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /*!< Enables the end of auto-baud interrupt */
lynxeyed_atsu 0:d920d64db582 95 #define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /*!< Enables the auto-baud time-out interrupt */
lynxeyed_atsu 0:d920d64db582 96 #define UART_IER_BITMASK ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */
lynxeyed_atsu 0:d920d64db582 97 #define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */
lynxeyed_atsu 0:d920d64db582 98
lynxeyed_atsu 0:d920d64db582 99 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 100 * Macro defines for Macro defines for UART interrupt identification register
lynxeyed_atsu 0:d920d64db582 101 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 102 #define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /*!<Interrupt Status - Active low */
lynxeyed_atsu 0:d920d64db582 103 #define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /*!<Interrupt identification: Receive line status*/
lynxeyed_atsu 0:d920d64db582 104 #define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /*!<Interrupt identification: Receive data available*/
lynxeyed_atsu 0:d920d64db582 105 #define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /*!<Interrupt identification: Character time-out indicator*/
lynxeyed_atsu 0:d920d64db582 106 #define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /*!<Interrupt identification: THRE interrupt*/
lynxeyed_atsu 0:d920d64db582 107 #define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /*!<Interrupt identification: Modem interrupt*/
lynxeyed_atsu 0:d920d64db582 108 #define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /*!<Interrupt identification: Interrupt ID mask */
lynxeyed_atsu 0:d920d64db582 109 #define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /*!<These bits are equivalent to UnFCR[0] */
lynxeyed_atsu 0:d920d64db582 110 #define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /*!< End of auto-baud interrupt */
lynxeyed_atsu 0:d920d64db582 111 #define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /*!< Auto-baud time-out interrupt */
lynxeyed_atsu 0:d920d64db582 112 #define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */
lynxeyed_atsu 0:d920d64db582 113
lynxeyed_atsu 0:d920d64db582 114 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 115 * Macro defines for Macro defines for UART FIFO control register
lynxeyed_atsu 0:d920d64db582 116 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 117 #define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /*!< UART FIFO enable */
lynxeyed_atsu 0:d920d64db582 118 #define UART_FCR_RX_RS ((uint8_t)(1<<1)) /*!< UART FIFO RX reset */
lynxeyed_atsu 0:d920d64db582 119 #define UART_FCR_TX_RS ((uint8_t)(1<<2)) /*!< UART FIFO TX reset */
lynxeyed_atsu 0:d920d64db582 120 #define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /*!< UART DMA mode selection */
lynxeyed_atsu 0:d920d64db582 121 #define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /*!< UART FIFO trigger level 0: 1 character */
lynxeyed_atsu 0:d920d64db582 122 #define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /*!< UART FIFO trigger level 1: 4 character */
lynxeyed_atsu 0:d920d64db582 123 #define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /*!< UART FIFO trigger level 2: 8 character */
lynxeyed_atsu 0:d920d64db582 124 #define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /*!< UART FIFO trigger level 3: 14 character */
lynxeyed_atsu 0:d920d64db582 125 #define UART_FCR_BITMASK ((uint8_t)(0xCF)) /*!< UART FIFO control bit mask */
lynxeyed_atsu 0:d920d64db582 126 #define UART_TX_FIFO_SIZE (16)
lynxeyed_atsu 0:d920d64db582 127
lynxeyed_atsu 0:d920d64db582 128 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 129 * Macro defines for Macro defines for UART line control register
lynxeyed_atsu 0:d920d64db582 130 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 131 #define UART_LCR_WLEN5 ((uint8_t)(0)) /*!< UART 5 bit data mode */
lynxeyed_atsu 0:d920d64db582 132 #define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /*!< UART 6 bit data mode */
lynxeyed_atsu 0:d920d64db582 133 #define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /*!< UART 7 bit data mode */
lynxeyed_atsu 0:d920d64db582 134 #define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /*!< UART 8 bit data mode */
lynxeyed_atsu 0:d920d64db582 135 #define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /*!< UART Two Stop Bits Select */
lynxeyed_atsu 0:d920d64db582 136 #define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /*!< UART Parity Enable */
lynxeyed_atsu 0:d920d64db582 137 #define UART_LCR_PARITY_ODD ((uint8_t)(0)) /*!< UART Odd Parity Select */
lynxeyed_atsu 0:d920d64db582 138 #define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /*!< UART Even Parity Select */
lynxeyed_atsu 0:d920d64db582 139 #define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /*!< UART force 1 stick parity */
lynxeyed_atsu 0:d920d64db582 140 #define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /*!< UART force 0 stick parity */
lynxeyed_atsu 0:d920d64db582 141 #define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /*!< UART Transmission Break enable */
lynxeyed_atsu 0:d920d64db582 142 #define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /*!< UART Divisor Latches Access bit enable */
lynxeyed_atsu 0:d920d64db582 143 #define UART_LCR_BITMASK ((uint8_t)(0xFF)) /*!< UART line control bit mask */
lynxeyed_atsu 0:d920d64db582 144
lynxeyed_atsu 0:d920d64db582 145 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 146 * Macro defines for Macro defines for UART1 Modem Control Register
lynxeyed_atsu 0:d920d64db582 147 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 148 #define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /*!< Source for modem output pin DTR */
lynxeyed_atsu 0:d920d64db582 149 #define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /*!< Source for modem output pin RTS */
lynxeyed_atsu 0:d920d64db582 150 #define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /*!< Loop back mode select */
lynxeyed_atsu 0:d920d64db582 151 #define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /*!< Enable Auto RTS flow-control */
lynxeyed_atsu 0:d920d64db582 152 #define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /*!< Enable Auto CTS flow-control */
lynxeyed_atsu 0:d920d64db582 153 #define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /*!< UART1 bit mask value */
lynxeyed_atsu 0:d920d64db582 154
lynxeyed_atsu 0:d920d64db582 155 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 156 * Macro defines for Macro defines for UART line status register
lynxeyed_atsu 0:d920d64db582 157 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 158 #define UART_LSR_RDR ((uint8_t)(1<<0)) /*!<Line status register: Receive data ready*/
lynxeyed_atsu 0:d920d64db582 159 #define UART_LSR_OE ((uint8_t)(1<<1)) /*!<Line status register: Overrun error*/
lynxeyed_atsu 0:d920d64db582 160 #define UART_LSR_PE ((uint8_t)(1<<2)) /*!<Line status register: Parity error*/
lynxeyed_atsu 0:d920d64db582 161 #define UART_LSR_FE ((uint8_t)(1<<3)) /*!<Line status register: Framing error*/
lynxeyed_atsu 0:d920d64db582 162 #define UART_LSR_BI ((uint8_t)(1<<4)) /*!<Line status register: Break interrupt*/
lynxeyed_atsu 0:d920d64db582 163 #define UART_LSR_THRE ((uint8_t)(1<<5)) /*!<Line status register: Transmit holding register empty*/
lynxeyed_atsu 0:d920d64db582 164 #define UART_LSR_TEMT ((uint8_t)(1<<6)) /*!<Line status register: Transmitter empty*/
lynxeyed_atsu 0:d920d64db582 165 #define UART_LSR_RXFE ((uint8_t)(1<<7)) /*!<Error in RX FIFO*/
lynxeyed_atsu 0:d920d64db582 166 #define UART_LSR_BITMASK ((uint8_t)(0xFF)) /*!<UART Line status bit mask */
lynxeyed_atsu 0:d920d64db582 167
lynxeyed_atsu 0:d920d64db582 168 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 169 * Macro defines for Macro defines for UART Modem (UART1 only) status register
lynxeyed_atsu 0:d920d64db582 170 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 171 #define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /*!< Set upon state change of input CTS */
lynxeyed_atsu 0:d920d64db582 172 #define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /*!< Set upon state change of input DSR */
lynxeyed_atsu 0:d920d64db582 173 #define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /*!< Set upon low to high transition of input RI */
lynxeyed_atsu 0:d920d64db582 174 #define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /*!< Set upon state change of input DCD */
lynxeyed_atsu 0:d920d64db582 175 #define UART1_MSR_CTS ((uint8_t)(1<<4)) /*!< Clear To Send State */
lynxeyed_atsu 0:d920d64db582 176 #define UART1_MSR_DSR ((uint8_t)(1<<5)) /*!< Data Set Ready State */
lynxeyed_atsu 0:d920d64db582 177 #define UART1_MSR_RI ((uint8_t)(1<<6)) /*!< Ring Indicator State */
lynxeyed_atsu 0:d920d64db582 178 #define UART1_MSR_DCD ((uint8_t)(1<<7)) /*!< Data Carrier Detect State */
lynxeyed_atsu 0:d920d64db582 179 #define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /*!< MSR register bit-mask value */
lynxeyed_atsu 0:d920d64db582 180
lynxeyed_atsu 0:d920d64db582 181 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 182 * Macro defines for Macro defines for UART Scratch Pad Register
lynxeyed_atsu 0:d920d64db582 183 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 184 #define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*!< UART Scratch Pad bit mask */
lynxeyed_atsu 0:d920d64db582 185
lynxeyed_atsu 0:d920d64db582 186 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 187 * Macro defines for Macro defines for UART Auto baudrate control register
lynxeyed_atsu 0:d920d64db582 188 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 189 #define UART_ACR_START ((uint32_t)(1<<0)) /**< UART Auto-baud start */
lynxeyed_atsu 0:d920d64db582 190 #define UART_ACR_MODE ((uint32_t)(1<<1)) /**< UART Auto baudrate Mode 1 */
lynxeyed_atsu 0:d920d64db582 191 #define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /**< UART Auto baudrate restart */
lynxeyed_atsu 0:d920d64db582 192 #define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /**< UART End of auto-baud interrupt clear */
lynxeyed_atsu 0:d920d64db582 193 #define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /**< UART Auto-baud time-out interrupt clear */
lynxeyed_atsu 0:d920d64db582 194 #define UART_ACR_BITMASK ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */
lynxeyed_atsu 0:d920d64db582 195
lynxeyed_atsu 0:d920d64db582 196 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 197 * Macro defines for Macro defines for UART IrDA control register
lynxeyed_atsu 0:d920d64db582 198 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 199 #define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /**< IrDA mode enable */
lynxeyed_atsu 0:d920d64db582 200 #define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /**< IrDA serial input inverted */
lynxeyed_atsu 0:d920d64db582 201 #define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /**< IrDA fixed pulse width mode */
lynxeyed_atsu 0:d920d64db582 202 #define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu 0:d920d64db582 203 #define UART_ICR_BITMASK ((uint32_t)(0x3F)) /*!< UART IRDA bit mask */
lynxeyed_atsu 0:d920d64db582 204
lynxeyed_atsu 0:d920d64db582 205 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 206 * Macro defines for Macro defines for UART Fractional divider register
lynxeyed_atsu 0:d920d64db582 207 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 208 #define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /**< Baud-rate generation pre-scaler divisor */
lynxeyed_atsu 0:d920d64db582 209 #define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /**< Baud-rate pre-scaler multiplier value */
lynxeyed_atsu 0:d920d64db582 210 #define UART_FDR_BITMASK ((uint32_t)(0xFF)) /**< UART Fractional Divider register bit mask */
lynxeyed_atsu 0:d920d64db582 211
lynxeyed_atsu 0:d920d64db582 212 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 213 * Macro defines for Macro defines for UART Tx Enable register
lynxeyed_atsu 0:d920d64db582 214 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 215 #define UART_TER_TXEN ((uint8_t)(1<<7)) /*!< Transmit enable bit */
lynxeyed_atsu 0:d920d64db582 216 #define UART_TER_BITMASK ((uint8_t)(0x80)) /**< UART Transmit Enable Register bit mask */
lynxeyed_atsu 0:d920d64db582 217
lynxeyed_atsu 0:d920d64db582 218 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 219 * Macro defines for Macro defines for UART1 RS485 Control register
lynxeyed_atsu 0:d920d64db582 220 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 221 #define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM)
lynxeyed_atsu 0:d920d64db582 222 is disabled */
lynxeyed_atsu 0:d920d64db582 223 #define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /*!< The receiver is disabled */
lynxeyed_atsu 0:d920d64db582 224 #define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2)) /*!< Auto Address Detect (AAD) is enabled */
lynxeyed_atsu 0:d920d64db582 225 #define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /*!< If direction control is enabled
lynxeyed_atsu 0:d920d64db582 226 (bit DCTRL = 1), pin DTR is used for direction control */
lynxeyed_atsu 0:d920d64db582 227 #define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) /*!< Enable Auto Direction Control */
lynxeyed_atsu 0:d920d64db582 228 #define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /*!< This bit reverses the polarity of the direction
lynxeyed_atsu 0:d920d64db582 229 control signal on the RTS (or DTR) pin. The direction control pin
lynxeyed_atsu 0:d920d64db582 230 will be driven to logic "1" when the transmitter has data to be sent */
lynxeyed_atsu 0:d920d64db582 231 #define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /**< RS485 control bit-mask value */
lynxeyed_atsu 0:d920d64db582 232
lynxeyed_atsu 0:d920d64db582 233 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 234 * Macro defines for Macro defines for UART1 RS-485 Address Match register
lynxeyed_atsu 0:d920d64db582 235 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 236 #define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */
lynxeyed_atsu 0:d920d64db582 237
lynxeyed_atsu 0:d920d64db582 238 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 239 * Macro defines for Macro defines for UART1 RS-485 Delay value register
lynxeyed_atsu 0:d920d64db582 240 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 241 /* Macro defines for UART1 RS-485 Delay value register */
lynxeyed_atsu 0:d920d64db582 242 #define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */
lynxeyed_atsu 0:d920d64db582 243
lynxeyed_atsu 0:d920d64db582 244 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 245 * Macro defines for Macro defines for UART FIFO Level register
lynxeyed_atsu 0:d920d64db582 246 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 247 #define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /**< Reflects the current level of the UART receiver FIFO */
lynxeyed_atsu 0:d920d64db582 248 #define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /**< Reflects the current level of the UART transmitter FIFO */
lynxeyed_atsu 0:d920d64db582 249 #define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /**< UART FIFO Level Register bit mask */
lynxeyed_atsu 0:d920d64db582 250
lynxeyed_atsu 0:d920d64db582 251
lynxeyed_atsu 0:d920d64db582 252 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
lynxeyed_atsu 0:d920d64db582 253
lynxeyed_atsu 0:d920d64db582 254 /** Macro to check the input UART_DATABIT parameters */
lynxeyed_atsu 0:d920d64db582 255 #define PARAM_UART_DATABIT(databit) ((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\
lynxeyed_atsu 0:d920d64db582 256 || (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8))
lynxeyed_atsu 0:d920d64db582 257
lynxeyed_atsu 0:d920d64db582 258 /** Macro to check the input UART_STOPBIT parameters */
lynxeyed_atsu 0:d920d64db582 259 #define PARAM_UART_STOPBIT(stopbit) ((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2))
lynxeyed_atsu 0:d920d64db582 260
lynxeyed_atsu 0:d920d64db582 261 /** Macro to check the input UART_PARITY parameters */
lynxeyed_atsu 0:d920d64db582 262 #define PARAM_UART_PARITY(parity) ((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \
lynxeyed_atsu 0:d920d64db582 263 || (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \
lynxeyed_atsu 0:d920d64db582 264 || (parity==UART_PARITY_SP_0))
lynxeyed_atsu 0:d920d64db582 265
lynxeyed_atsu 0:d920d64db582 266 /** Macro to check the input UART_FIFO parameters */
lynxeyed_atsu 0:d920d64db582 267 #define PARAM_UART_FIFO_LEVEL(fifo) ((fifo==UART_FIFO_TRGLEV0) \
lynxeyed_atsu 0:d920d64db582 268 || (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \
lynxeyed_atsu 0:d920d64db582 269 || (fifo==UART_FIFO_TRGLEV3))
lynxeyed_atsu 0:d920d64db582 270
lynxeyed_atsu 0:d920d64db582 271 /** Macro to check the input UART_INTCFG parameters */
lynxeyed_atsu 0:d920d64db582 272 #define PARAM_UART_INTCFG(IntCfg) ((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \
lynxeyed_atsu 0:d920d64db582 273 || (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \
lynxeyed_atsu 0:d920d64db582 274 || (IntCfg==UART_INTCFG_ABTO))
lynxeyed_atsu 0:d920d64db582 275
lynxeyed_atsu 0:d920d64db582 276 /** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */
lynxeyed_atsu 0:d920d64db582 277 #define PARAM_UART1_INTCFG(IntCfg) ((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS))
lynxeyed_atsu 0:d920d64db582 278
lynxeyed_atsu 0:d920d64db582 279 /** Macro to check the input UART_AUTOBAUD_MODE parameters */
lynxeyed_atsu 0:d920d64db582 280 #define PARAM_UART_AUTOBAUD_MODE(ABmode) ((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1))
lynxeyed_atsu 0:d920d64db582 281
lynxeyed_atsu 0:d920d64db582 282 /** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */
lynxeyed_atsu 0:d920d64db582 283 #define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat) ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || \
lynxeyed_atsu 0:d920d64db582 284 (ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO))
lynxeyed_atsu 0:d920d64db582 285
lynxeyed_atsu 0:d920d64db582 286 /** Macro to check the input UART_IrDA_PULSEDIV parameters */
lynxeyed_atsu 0:d920d64db582 287 #define PARAM_UART_IrDA_PULSEDIV(PulseDiv) ((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \
lynxeyed_atsu 0:d920d64db582 288 || (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \
lynxeyed_atsu 0:d920d64db582 289 || (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \
lynxeyed_atsu 0:d920d64db582 290 || (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256))
lynxeyed_atsu 0:d920d64db582 291
lynxeyed_atsu 0:d920d64db582 292 /* Macro to check the input UART1_SignalState parameters */
lynxeyed_atsu 0:d920d64db582 293 #define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE))
lynxeyed_atsu 0:d920d64db582 294
lynxeyed_atsu 0:d920d64db582 295 /** Macro to check the input PARAM_UART1_MODEM_PIN parameters */
lynxeyed_atsu 0:d920d64db582 296 #define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS))
lynxeyed_atsu 0:d920d64db582 297
lynxeyed_atsu 0:d920d64db582 298 /** Macro to check the input PARAM_UART1_MODEM_MODE parameters */
lynxeyed_atsu 0:d920d64db582 299 #define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \
lynxeyed_atsu 0:d920d64db582 300 || (x==UART1_MODEM_MODE_AUTO_CTS))
lynxeyed_atsu 0:d920d64db582 301
lynxeyed_atsu 0:d920d64db582 302 /** Macro to check the direction control pin type */
lynxeyed_atsu 0:d920d64db582 303 #define PARAM_UART_RS485_DIRCTRL_PIN(x) ((x==UART1_RS485_DIRCTRL_RTS) || (x==UART1_RS485_DIRCTRL_DTR))
lynxeyed_atsu 0:d920d64db582 304
lynxeyed_atsu 0:d920d64db582 305 /* Macro to determine if it is valid UART port number */
lynxeyed_atsu 0:d920d64db582 306 #define PARAM_UARTx(x) ((((uint32_t *)x)==((uint32_t *)LPC_UART0)) \
lynxeyed_atsu 0:d920d64db582 307 || (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \
lynxeyed_atsu 0:d920d64db582 308 || (((uint32_t *)x)==((uint32_t *)LPC_UART2)) \
lynxeyed_atsu 0:d920d64db582 309 || (((uint32_t *)x)==((uint32_t *)LPC_UART3)))
lynxeyed_atsu 0:d920d64db582 310 #define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_UART3))
lynxeyed_atsu 0:d920d64db582 311 #define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1))
lynxeyed_atsu 0:d920d64db582 312
lynxeyed_atsu 0:d920d64db582 313 /** Macro to check the input value for UART1_RS485_CFG_MATCHADDRVALUE parameter */
lynxeyed_atsu 0:d920d64db582 314 #define PARAM_UART1_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF))
lynxeyed_atsu 0:d920d64db582 315
lynxeyed_atsu 0:d920d64db582 316 /** Macro to check the input value for UART1_RS485_CFG_DELAYVALUE parameter */
lynxeyed_atsu 0:d920d64db582 317 #define PARAM_UART1_RS485_CFG_DELAYVALUE(x) ((x<0xFF))
lynxeyed_atsu 0:d920d64db582 318
lynxeyed_atsu 0:d920d64db582 319 /**
lynxeyed_atsu 0:d920d64db582 320 * @}
lynxeyed_atsu 0:d920d64db582 321 */
lynxeyed_atsu 0:d920d64db582 322
lynxeyed_atsu 0:d920d64db582 323
lynxeyed_atsu 0:d920d64db582 324 /* Public Types --------------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 325 /** @defgroup UART_Public_Types UART Public Types
lynxeyed_atsu 0:d920d64db582 326 * @{
lynxeyed_atsu 0:d920d64db582 327 */
lynxeyed_atsu 0:d920d64db582 328
lynxeyed_atsu 0:d920d64db582 329 /**
lynxeyed_atsu 0:d920d64db582 330 * @brief UART Databit type definitions
lynxeyed_atsu 0:d920d64db582 331 */
lynxeyed_atsu 0:d920d64db582 332 typedef enum {
lynxeyed_atsu 0:d920d64db582 333 UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */
lynxeyed_atsu 0:d920d64db582 334 UART_DATABIT_6, /*!< UART 6 bit data mode */
lynxeyed_atsu 0:d920d64db582 335 UART_DATABIT_7, /*!< UART 7 bit data mode */
lynxeyed_atsu 0:d920d64db582 336 UART_DATABIT_8 /*!< UART 8 bit data mode */
lynxeyed_atsu 0:d920d64db582 337 } UART_DATABIT_Type;
lynxeyed_atsu 0:d920d64db582 338
lynxeyed_atsu 0:d920d64db582 339 /**
lynxeyed_atsu 0:d920d64db582 340 * @brief UART Stop bit type definitions
lynxeyed_atsu 0:d920d64db582 341 */
lynxeyed_atsu 0:d920d64db582 342 typedef enum {
lynxeyed_atsu 0:d920d64db582 343 UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */
lynxeyed_atsu 0:d920d64db582 344 UART_STOPBIT_2, /*!< UART Two Stop Bits Select */
lynxeyed_atsu 0:d920d64db582 345 } UART_STOPBIT_Type;
lynxeyed_atsu 0:d920d64db582 346
lynxeyed_atsu 0:d920d64db582 347 /**
lynxeyed_atsu 0:d920d64db582 348 * @brief UART Parity type definitions
lynxeyed_atsu 0:d920d64db582 349 */
lynxeyed_atsu 0:d920d64db582 350 typedef enum {
lynxeyed_atsu 0:d920d64db582 351 UART_PARITY_NONE = 0, /*!< No parity */
lynxeyed_atsu 0:d920d64db582 352 UART_PARITY_ODD, /*!< Odd parity */
lynxeyed_atsu 0:d920d64db582 353 UART_PARITY_EVEN, /*!< Even parity */
lynxeyed_atsu 0:d920d64db582 354 UART_PARITY_SP_1, /*!< Forced "1" stick parity */
lynxeyed_atsu 0:d920d64db582 355 UART_PARITY_SP_0 /*!< Forced "0" stick parity */
lynxeyed_atsu 0:d920d64db582 356 } UART_PARITY_Type;
lynxeyed_atsu 0:d920d64db582 357
lynxeyed_atsu 0:d920d64db582 358 /**
lynxeyed_atsu 0:d920d64db582 359 * @brief FIFO Level type definitions
lynxeyed_atsu 0:d920d64db582 360 */
lynxeyed_atsu 0:d920d64db582 361 typedef enum {
lynxeyed_atsu 0:d920d64db582 362 UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */
lynxeyed_atsu 0:d920d64db582 363 UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */
lynxeyed_atsu 0:d920d64db582 364 UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */
lynxeyed_atsu 0:d920d64db582 365 UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */
lynxeyed_atsu 0:d920d64db582 366 } UART_FITO_LEVEL_Type;
lynxeyed_atsu 0:d920d64db582 367
lynxeyed_atsu 0:d920d64db582 368 /********************************************************************//**
lynxeyed_atsu 0:d920d64db582 369 * @brief UART Interrupt Type definitions
lynxeyed_atsu 0:d920d64db582 370 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 371 typedef enum {
lynxeyed_atsu 0:d920d64db582 372 UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/
lynxeyed_atsu 0:d920d64db582 373 UART_INTCFG_THRE, /*!< THR Interrupt enable*/
lynxeyed_atsu 0:d920d64db582 374 UART_INTCFG_RLS, /*!< RX line status interrupt enable*/
lynxeyed_atsu 0:d920d64db582 375 UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */
lynxeyed_atsu 0:d920d64db582 376 UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */
lynxeyed_atsu 0:d920d64db582 377 UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */
lynxeyed_atsu 0:d920d64db582 378 UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */
lynxeyed_atsu 0:d920d64db582 379 } UART_INT_Type;
lynxeyed_atsu 0:d920d64db582 380
lynxeyed_atsu 0:d920d64db582 381 /**
lynxeyed_atsu 0:d920d64db582 382 * @brief UART Line Status Type definition
lynxeyed_atsu 0:d920d64db582 383 */
lynxeyed_atsu 0:d920d64db582 384 typedef enum {
lynxeyed_atsu 0:d920d64db582 385 UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/
lynxeyed_atsu 0:d920d64db582 386 UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/
lynxeyed_atsu 0:d920d64db582 387 UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/
lynxeyed_atsu 0:d920d64db582 388 UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/
lynxeyed_atsu 0:d920d64db582 389 UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/
lynxeyed_atsu 0:d920d64db582 390 UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/
lynxeyed_atsu 0:d920d64db582 391 UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/
lynxeyed_atsu 0:d920d64db582 392 UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/
lynxeyed_atsu 0:d920d64db582 393 } UART_LS_Type;
lynxeyed_atsu 0:d920d64db582 394
lynxeyed_atsu 0:d920d64db582 395 /**
lynxeyed_atsu 0:d920d64db582 396 * @brief UART Auto-baudrate mode type definition
lynxeyed_atsu 0:d920d64db582 397 */
lynxeyed_atsu 0:d920d64db582 398 typedef enum {
lynxeyed_atsu 0:d920d64db582 399 UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */
lynxeyed_atsu 0:d920d64db582 400 UART_AUTOBAUD_MODE1, /**< UART Auto baudrate Mode 1 */
lynxeyed_atsu 0:d920d64db582 401 } UART_AB_MODE_Type;
lynxeyed_atsu 0:d920d64db582 402
lynxeyed_atsu 0:d920d64db582 403 /**
lynxeyed_atsu 0:d920d64db582 404 * @brief Auto Baudrate mode configuration type definition
lynxeyed_atsu 0:d920d64db582 405 */
lynxeyed_atsu 0:d920d64db582 406 typedef struct {
lynxeyed_atsu 0:d920d64db582 407 UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */
lynxeyed_atsu 0:d920d64db582 408 FunctionalState AutoRestart; /**< Auto Restart state */
lynxeyed_atsu 0:d920d64db582 409 } UART_AB_CFG_Type;
lynxeyed_atsu 0:d920d64db582 410
lynxeyed_atsu 0:d920d64db582 411 /**
lynxeyed_atsu 0:d920d64db582 412 * @brief UART End of Auto-baudrate type definition
lynxeyed_atsu 0:d920d64db582 413 */
lynxeyed_atsu 0:d920d64db582 414 typedef enum {
lynxeyed_atsu 0:d920d64db582 415 UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */
lynxeyed_atsu 0:d920d64db582 416 UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */
lynxeyed_atsu 0:d920d64db582 417 }UART_ABEO_Type;
lynxeyed_atsu 0:d920d64db582 418
lynxeyed_atsu 0:d920d64db582 419 /**
lynxeyed_atsu 0:d920d64db582 420 * UART IrDA Control type Definition
lynxeyed_atsu 0:d920d64db582 421 */
lynxeyed_atsu 0:d920d64db582 422 typedef enum {
lynxeyed_atsu 0:d920d64db582 423 UART_IrDA_PULSEDIV2 = 0, /**< Pulse width = 2 * Tpclk
lynxeyed_atsu 0:d920d64db582 424 - Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu 0:d920d64db582 425 UART_IrDA_PULSEDIV4, /**< Pulse width = 4 * Tpclk
lynxeyed_atsu 0:d920d64db582 426 - Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu 0:d920d64db582 427 UART_IrDA_PULSEDIV8, /**< Pulse width = 8 * Tpclk
lynxeyed_atsu 0:d920d64db582 428 - Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu 0:d920d64db582 429 UART_IrDA_PULSEDIV16, /**< Pulse width = 16 * Tpclk
lynxeyed_atsu 0:d920d64db582 430 - Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu 0:d920d64db582 431 UART_IrDA_PULSEDIV32, /**< Pulse width = 32 * Tpclk
lynxeyed_atsu 0:d920d64db582 432 - Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu 0:d920d64db582 433 UART_IrDA_PULSEDIV64, /**< Pulse width = 64 * Tpclk
lynxeyed_atsu 0:d920d64db582 434 - Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu 0:d920d64db582 435 UART_IrDA_PULSEDIV128, /**< Pulse width = 128 * Tpclk
lynxeyed_atsu 0:d920d64db582 436 - Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu 0:d920d64db582 437 UART_IrDA_PULSEDIV256 /**< Pulse width = 256 * Tpclk
lynxeyed_atsu 0:d920d64db582 438 - Configures the pulse when FixPulseEn = 1 */
lynxeyed_atsu 0:d920d64db582 439 } UART_IrDA_PULSE_Type;
lynxeyed_atsu 0:d920d64db582 440
lynxeyed_atsu 0:d920d64db582 441 /********************************************************************//**
lynxeyed_atsu 0:d920d64db582 442 * @brief UART1 Full modem - Signal states definition
lynxeyed_atsu 0:d920d64db582 443 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 444 typedef enum {
lynxeyed_atsu 0:d920d64db582 445 INACTIVE = 0, /* In-active state */
lynxeyed_atsu 0:d920d64db582 446 ACTIVE = !INACTIVE /* Active state */
lynxeyed_atsu 0:d920d64db582 447 }UART1_SignalState;
lynxeyed_atsu 0:d920d64db582 448
lynxeyed_atsu 0:d920d64db582 449 /**
lynxeyed_atsu 0:d920d64db582 450 * @brief UART modem status type definition
lynxeyed_atsu 0:d920d64db582 451 */
lynxeyed_atsu 0:d920d64db582 452 typedef enum {
lynxeyed_atsu 0:d920d64db582 453 UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */
lynxeyed_atsu 0:d920d64db582 454 UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */
lynxeyed_atsu 0:d920d64db582 455 UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */
lynxeyed_atsu 0:d920d64db582 456 UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */
lynxeyed_atsu 0:d920d64db582 457 UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */
lynxeyed_atsu 0:d920d64db582 458 UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */
lynxeyed_atsu 0:d920d64db582 459 UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */
lynxeyed_atsu 0:d920d64db582 460 UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */
lynxeyed_atsu 0:d920d64db582 461 } UART_MODEM_STAT_type;
lynxeyed_atsu 0:d920d64db582 462
lynxeyed_atsu 0:d920d64db582 463 /**
lynxeyed_atsu 0:d920d64db582 464 * @brief Modem output pin type definition
lynxeyed_atsu 0:d920d64db582 465 */
lynxeyed_atsu 0:d920d64db582 466 typedef enum {
lynxeyed_atsu 0:d920d64db582 467 UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */
lynxeyed_atsu 0:d920d64db582 468 UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */
lynxeyed_atsu 0:d920d64db582 469 } UART_MODEM_PIN_Type;
lynxeyed_atsu 0:d920d64db582 470
lynxeyed_atsu 0:d920d64db582 471 /**
lynxeyed_atsu 0:d920d64db582 472 * @brief UART Modem mode type definition
lynxeyed_atsu 0:d920d64db582 473 */
lynxeyed_atsu 0:d920d64db582 474 typedef enum {
lynxeyed_atsu 0:d920d64db582 475 UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */
lynxeyed_atsu 0:d920d64db582 476 UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */
lynxeyed_atsu 0:d920d64db582 477 UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */
lynxeyed_atsu 0:d920d64db582 478 } UART_MODEM_MODE_Type;
lynxeyed_atsu 0:d920d64db582 479
lynxeyed_atsu 0:d920d64db582 480 /**
lynxeyed_atsu 0:d920d64db582 481 * @brief UART Direction Control Pin type definition
lynxeyed_atsu 0:d920d64db582 482 */
lynxeyed_atsu 0:d920d64db582 483 typedef enum {
lynxeyed_atsu 0:d920d64db582 484 UART1_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */
lynxeyed_atsu 0:d920d64db582 485 UART1_RS485_DIRCTRL_DTR /**< Pin DTR is used for direction control */
lynxeyed_atsu 0:d920d64db582 486 } UART_RS485_DIRCTRL_PIN_Type;
lynxeyed_atsu 0:d920d64db582 487
lynxeyed_atsu 0:d920d64db582 488 /********************************************************************//**
lynxeyed_atsu 0:d920d64db582 489 * @brief UART Configuration Structure definition
lynxeyed_atsu 0:d920d64db582 490 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 491 typedef struct {
lynxeyed_atsu 0:d920d64db582 492 uint32_t Baud_rate; /**< UART baud rate */
lynxeyed_atsu 0:d920d64db582 493 UART_PARITY_Type Parity; /**< Parity selection, should be:
lynxeyed_atsu 0:d920d64db582 494 - UART_PARITY_NONE: No parity
lynxeyed_atsu 0:d920d64db582 495 - UART_PARITY_ODD: Odd parity
lynxeyed_atsu 0:d920d64db582 496 - UART_PARITY_EVEN: Even parity
lynxeyed_atsu 0:d920d64db582 497 - UART_PARITY_SP_1: Forced "1" stick parity
lynxeyed_atsu 0:d920d64db582 498 - UART_PARITY_SP_0: Forced "0" stick parity
lynxeyed_atsu 0:d920d64db582 499 */
lynxeyed_atsu 0:d920d64db582 500 UART_DATABIT_Type Databits; /**< Number of data bits, should be:
lynxeyed_atsu 0:d920d64db582 501 - UART_DATABIT_5: UART 5 bit data mode
lynxeyed_atsu 0:d920d64db582 502 - UART_DATABIT_6: UART 6 bit data mode
lynxeyed_atsu 0:d920d64db582 503 - UART_DATABIT_7: UART 7 bit data mode
lynxeyed_atsu 0:d920d64db582 504 - UART_DATABIT_8: UART 8 bit data mode
lynxeyed_atsu 0:d920d64db582 505 */
lynxeyed_atsu 0:d920d64db582 506 UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be:
lynxeyed_atsu 0:d920d64db582 507 - UART_STOPBIT_1: UART 1 Stop Bits Select
lynxeyed_atsu 0:d920d64db582 508 - UART_STOPBIT_2: UART 2 Stop Bits Select
lynxeyed_atsu 0:d920d64db582 509 */
lynxeyed_atsu 0:d920d64db582 510 } UART_CFG_Type;
lynxeyed_atsu 0:d920d64db582 511
lynxeyed_atsu 0:d920d64db582 512 /********************************************************************//**
lynxeyed_atsu 0:d920d64db582 513 * @brief UART FIFO Configuration Structure definition
lynxeyed_atsu 0:d920d64db582 514 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 515
lynxeyed_atsu 0:d920d64db582 516 typedef struct {
lynxeyed_atsu 0:d920d64db582 517 FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be:
lynxeyed_atsu 0:d920d64db582 518 - ENABLE: Reset Rx FIFO in UART
lynxeyed_atsu 0:d920d64db582 519 - DISABLE: Do not reset Rx FIFO in UART
lynxeyed_atsu 0:d920d64db582 520 */
lynxeyed_atsu 0:d920d64db582 521 FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be:
lynxeyed_atsu 0:d920d64db582 522 - ENABLE: Reset Tx FIFO in UART
lynxeyed_atsu 0:d920d64db582 523 - DISABLE: Do not reset Tx FIFO in UART
lynxeyed_atsu 0:d920d64db582 524 */
lynxeyed_atsu 0:d920d64db582 525 FunctionalState FIFO_DMAMode; /**< DMA mode, should be:
lynxeyed_atsu 0:d920d64db582 526 - ENABLE: Enable DMA mode in UART
lynxeyed_atsu 0:d920d64db582 527 - DISABLE: Disable DMA mode in UART
lynxeyed_atsu 0:d920d64db582 528 */
lynxeyed_atsu 0:d920d64db582 529 UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be:
lynxeyed_atsu 0:d920d64db582 530 - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
lynxeyed_atsu 0:d920d64db582 531 - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
lynxeyed_atsu 0:d920d64db582 532 - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
lynxeyed_atsu 0:d920d64db582 533 - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
lynxeyed_atsu 0:d920d64db582 534 */
lynxeyed_atsu 0:d920d64db582 535 } UART_FIFO_CFG_Type;
lynxeyed_atsu 0:d920d64db582 536
lynxeyed_atsu 0:d920d64db582 537 /********************************************************************//**
lynxeyed_atsu 0:d920d64db582 538 * @brief UART1 Full modem - RS485 Control configuration type
lynxeyed_atsu 0:d920d64db582 539 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 540 typedef struct {
lynxeyed_atsu 0:d920d64db582 541 FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
lynxeyed_atsu 0:d920d64db582 542 - ENABLE: Enable this function.
lynxeyed_atsu 0:d920d64db582 543 - DISABLE: Disable this function. */
lynxeyed_atsu 0:d920d64db582 544 FunctionalState Rx_State; /*!< Receiver State:
lynxeyed_atsu 0:d920d64db582 545 - ENABLE: Enable Receiver.
lynxeyed_atsu 0:d920d64db582 546 - DISABLE: Disable Receiver. */
lynxeyed_atsu 0:d920d64db582 547 FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state:
lynxeyed_atsu 0:d920d64db582 548 - ENABLE: ENABLE this function.
lynxeyed_atsu 0:d920d64db582 549 - DISABLE: Disable this function. */
lynxeyed_atsu 0:d920d64db582 550 FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State:
lynxeyed_atsu 0:d920d64db582 551 - ENABLE: Enable this function.
lynxeyed_atsu 0:d920d64db582 552 - DISABLE: Disable this function. */
lynxeyed_atsu 0:d920d64db582 553 UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state:
lynxeyed_atsu 0:d920d64db582 554 - UART1_RS485_DIRCTRL_RTS:
lynxeyed_atsu 0:d920d64db582 555 pin RTS is used for direction control.
lynxeyed_atsu 0:d920d64db582 556 - UART1_RS485_DIRCTRL_DTR:
lynxeyed_atsu 0:d920d64db582 557 pin DTR is used for direction control. */
lynxeyed_atsu 0:d920d64db582 558 SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on
lynxeyed_atsu 0:d920d64db582 559 the RTS (or DTR) pin:
lynxeyed_atsu 0:d920d64db582 560 - RESET: The direction control pin will be driven
lynxeyed_atsu 0:d920d64db582 561 to logic "0" when the transmitter has data to be sent.
lynxeyed_atsu 0:d920d64db582 562 - SET: The direction control pin will be driven
lynxeyed_atsu 0:d920d64db582 563 to logic "1" when the transmitter has data to be sent. */
lynxeyed_atsu 0:d920d64db582 564 uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */
lynxeyed_atsu 0:d920d64db582 565 uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */
lynxeyed_atsu 0:d920d64db582 566 } UART1_RS485_CTRLCFG_Type;
lynxeyed_atsu 0:d920d64db582 567
lynxeyed_atsu 0:d920d64db582 568 /**
lynxeyed_atsu 0:d920d64db582 569 * @}
lynxeyed_atsu 0:d920d64db582 570 */
lynxeyed_atsu 0:d920d64db582 571
lynxeyed_atsu 0:d920d64db582 572
lynxeyed_atsu 0:d920d64db582 573 /* Public Functions ----------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 574 /** @defgroup UART_Public_Functions UART Public Functions
lynxeyed_atsu 0:d920d64db582 575 * @{
lynxeyed_atsu 0:d920d64db582 576 */
lynxeyed_atsu 0:d920d64db582 577 /* UART Init/DeInit functions --------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 578 void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct);
lynxeyed_atsu 0:d920d64db582 579 void UART_DeInit(LPC_UART_TypeDef* UARTx);
lynxeyed_atsu 0:d920d64db582 580 void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
lynxeyed_atsu 0:d920d64db582 581
lynxeyed_atsu 0:d920d64db582 582 /* UART Send/Receive functions -------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 583 void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data);
lynxeyed_atsu 0:d920d64db582 584 uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx);
lynxeyed_atsu 0:d920d64db582 585 uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf,
lynxeyed_atsu 0:d920d64db582 586 uint32_t buflen, TRANSFER_BLOCK_Type flag);
lynxeyed_atsu 0:d920d64db582 587 uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \
lynxeyed_atsu 0:d920d64db582 588 uint32_t buflen, TRANSFER_BLOCK_Type flag);
lynxeyed_atsu 0:d920d64db582 589
lynxeyed_atsu 0:d920d64db582 590 /* UART FIFO functions ----------------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 591 void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg);
lynxeyed_atsu 0:d920d64db582 592 void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
lynxeyed_atsu 0:d920d64db582 593
lynxeyed_atsu 0:d920d64db582 594 /* UART get information functions -----------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 595 uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx);
lynxeyed_atsu 0:d920d64db582 596 uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx);
lynxeyed_atsu 0:d920d64db582 597
lynxeyed_atsu 0:d920d64db582 598 /* UART operate functions -------------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 599 void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \
lynxeyed_atsu 0:d920d64db582 600 FunctionalState NewState);
lynxeyed_atsu 0:d920d64db582 601 void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState);
lynxeyed_atsu 0:d920d64db582 602 FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx);
lynxeyed_atsu 0:d920d64db582 603 void UART_ForceBreak(LPC_UART_TypeDef* UARTx);
lynxeyed_atsu 0:d920d64db582 604
lynxeyed_atsu 0:d920d64db582 605 /* UART Auto-baud functions -----------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 606 void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType);
lynxeyed_atsu 0:d920d64db582 607 void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
lynxeyed_atsu 0:d920d64db582 608 FunctionalState NewState);
lynxeyed_atsu 0:d920d64db582 609
lynxeyed_atsu 0:d920d64db582 610 /* UART1 FullModem functions ----------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 611 void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \
lynxeyed_atsu 0:d920d64db582 612 UART1_SignalState NewState);
lynxeyed_atsu 0:d920d64db582 613 void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \
lynxeyed_atsu 0:d920d64db582 614 FunctionalState NewState);
lynxeyed_atsu 0:d920d64db582 615 uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx);
lynxeyed_atsu 0:d920d64db582 616
lynxeyed_atsu 0:d920d64db582 617 /* UART RS485 functions ----------------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 618 void UART_RS485Config(LPC_UART1_TypeDef *UARTx, \
lynxeyed_atsu 0:d920d64db582 619 UART1_RS485_CTRLCFG_Type *RS485ConfigStruct);
lynxeyed_atsu 0:d920d64db582 620 void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState);
lynxeyed_atsu 0:d920d64db582 621 void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr);
lynxeyed_atsu 0:d920d64db582 622 uint32_t UART_RS485SendData(LPC_UART1_TypeDef *UARTx, uint8_t *pData, uint32_t size);
lynxeyed_atsu 0:d920d64db582 623
lynxeyed_atsu 0:d920d64db582 624 /* UART IrDA functions-------------------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 625 void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
lynxeyed_atsu 0:d920d64db582 626 void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
lynxeyed_atsu 0:d920d64db582 627 void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv);
lynxeyed_atsu 0:d920d64db582 628 /**
lynxeyed_atsu 0:d920d64db582 629 * @}
lynxeyed_atsu 0:d920d64db582 630 */
lynxeyed_atsu 0:d920d64db582 631
lynxeyed_atsu 0:d920d64db582 632
lynxeyed_atsu 0:d920d64db582 633 #ifdef __cplusplus
lynxeyed_atsu 0:d920d64db582 634 }
lynxeyed_atsu 0:d920d64db582 635 #endif
lynxeyed_atsu 0:d920d64db582 636
lynxeyed_atsu 0:d920d64db582 637
lynxeyed_atsu 0:d920d64db582 638 #endif /* __LPC17XX_UART_H */
lynxeyed_atsu 0:d920d64db582 639
lynxeyed_atsu 0:d920d64db582 640 /**
lynxeyed_atsu 0:d920d64db582 641 * @}
lynxeyed_atsu 0:d920d64db582 642 */
lynxeyed_atsu 0:d920d64db582 643
lynxeyed_atsu 0:d920d64db582 644 /* --------------------------------- End Of File ------------------------------ */