xeye_ atsu / Mbed 2 deprecated I2S_AIC23B_RiceGolomb

パラメータを適応変化させる事により圧縮率を向上させた動的ライス・ゴロム符号を利用した可逆圧縮方式。圧縮ソフト、圧縮率のMATLABシミュレーションは詳細はInterface誌2011年8月号に掲載されるRX62Nマイコン連動特集にて掲載予定。

Dependencies:   mbed

I2S_Example/LPC17xx.h@0:d920d64db582, 2011-03-30 (annotated)

Committer:
lynxeyed_atsu
Date:
Wed Mar 30 06:05:24 2011 +0000
Revision:
0:d920d64db582
alpha

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lynxeyed_atsu 0:d920d64db582 1 /**************************************************************************//**
lynxeyed_atsu 0:d920d64db582 2 * @file LPC17xx.h
lynxeyed_atsu 0:d920d64db582 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
lynxeyed_atsu 0:d920d64db582 4 * NXP LPC17xx Device Series
lynxeyed_atsu 0:d920d64db582 5 * @version: V1.08
lynxeyed_atsu 0:d920d64db582 6 * @date: 21. December 2009
lynxeyed_atsu 0:d920d64db582 7 *
lynxeyed_atsu 0:d920d64db582 8 * @note
lynxeyed_atsu 0:d920d64db582 9 * Copyright (C) 2009 ARM Limited. All rights reserved.
lynxeyed_atsu 0:d920d64db582 10 *
lynxeyed_atsu 0:d920d64db582 11 * @par
lynxeyed_atsu 0:d920d64db582 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
lynxeyed_atsu 0:d920d64db582 13 * processor based microcontrollers. This file can be freely distributed
lynxeyed_atsu 0:d920d64db582 14 * within development tools that are supporting such ARM based processors.
lynxeyed_atsu 0:d920d64db582 15 *
lynxeyed_atsu 0:d920d64db582 16 * @par
lynxeyed_atsu 0:d920d64db582 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
lynxeyed_atsu 0:d920d64db582 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
lynxeyed_atsu 0:d920d64db582 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
lynxeyed_atsu 0:d920d64db582 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
lynxeyed_atsu 0:d920d64db582 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
lynxeyed_atsu 0:d920d64db582 22 *
lynxeyed_atsu 0:d920d64db582 23 ******************************************************************************/
lynxeyed_atsu 0:d920d64db582 24
lynxeyed_atsu 0:d920d64db582 25
lynxeyed_atsu 0:d920d64db582 26 #ifndef __LPC17xx_H__
lynxeyed_atsu 0:d920d64db582 27 #define __LPC17xx_H__
lynxeyed_atsu 0:d920d64db582 28
lynxeyed_atsu 0:d920d64db582 29 /*
lynxeyed_atsu 0:d920d64db582 30 * ==========================================================================
lynxeyed_atsu 0:d920d64db582 31 * ---------- Interrupt Number Definition -----------------------------------
lynxeyed_atsu 0:d920d64db582 32 * ==========================================================================
lynxeyed_atsu 0:d920d64db582 33 */
lynxeyed_atsu 0:d920d64db582 34
lynxeyed_atsu 0:d920d64db582 35 /** @addtogroup LPC17xx_System
lynxeyed_atsu 0:d920d64db582 36 * @{
lynxeyed_atsu 0:d920d64db582 37 */
lynxeyed_atsu 0:d920d64db582 38
lynxeyed_atsu 0:d920d64db582 39 /** @brief IRQ interrupt source definition */
lynxeyed_atsu 0:d920d64db582 40 typedef enum IRQn
lynxeyed_atsu 0:d920d64db582 41 {
lynxeyed_atsu 0:d920d64db582 42 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
lynxeyed_atsu 0:d920d64db582 43 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
lynxeyed_atsu 0:d920d64db582 44 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
lynxeyed_atsu 0:d920d64db582 45 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
lynxeyed_atsu 0:d920d64db582 46 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
lynxeyed_atsu 0:d920d64db582 47 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
lynxeyed_atsu 0:d920d64db582 48 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
lynxeyed_atsu 0:d920d64db582 49 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
lynxeyed_atsu 0:d920d64db582 50 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
lynxeyed_atsu 0:d920d64db582 51
lynxeyed_atsu 0:d920d64db582 52 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
lynxeyed_atsu 0:d920d64db582 53 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
lynxeyed_atsu 0:d920d64db582 54 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
lynxeyed_atsu 0:d920d64db582 55 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
lynxeyed_atsu 0:d920d64db582 56 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
lynxeyed_atsu 0:d920d64db582 57 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
lynxeyed_atsu 0:d920d64db582 58 UART0_IRQn = 5, /*!< UART0 Interrupt */
lynxeyed_atsu 0:d920d64db582 59 UART1_IRQn = 6, /*!< UART1 Interrupt */
lynxeyed_atsu 0:d920d64db582 60 UART2_IRQn = 7, /*!< UART2 Interrupt */
lynxeyed_atsu 0:d920d64db582 61 UART3_IRQn = 8, /*!< UART3 Interrupt */
lynxeyed_atsu 0:d920d64db582 62 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
lynxeyed_atsu 0:d920d64db582 63 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
lynxeyed_atsu 0:d920d64db582 64 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
lynxeyed_atsu 0:d920d64db582 65 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
lynxeyed_atsu 0:d920d64db582 66 SPI_IRQn = 13, /*!< SPI Interrupt */
lynxeyed_atsu 0:d920d64db582 67 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
lynxeyed_atsu 0:d920d64db582 68 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
lynxeyed_atsu 0:d920d64db582 69 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
lynxeyed_atsu 0:d920d64db582 70 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
lynxeyed_atsu 0:d920d64db582 71 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
lynxeyed_atsu 0:d920d64db582 72 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
lynxeyed_atsu 0:d920d64db582 73 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
lynxeyed_atsu 0:d920d64db582 74 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
lynxeyed_atsu 0:d920d64db582 75 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
lynxeyed_atsu 0:d920d64db582 76 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
lynxeyed_atsu 0:d920d64db582 77 USB_IRQn = 24, /*!< USB Interrupt */
lynxeyed_atsu 0:d920d64db582 78 CAN_IRQn = 25, /*!< CAN Interrupt */
lynxeyed_atsu 0:d920d64db582 79 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
lynxeyed_atsu 0:d920d64db582 80 I2S_IRQn = 27, /*!< I2S Interrupt */
lynxeyed_atsu 0:d920d64db582 81 ENET_IRQn = 28, /*!< Ethernet Interrupt */
lynxeyed_atsu 0:d920d64db582 82 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
lynxeyed_atsu 0:d920d64db582 83 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
lynxeyed_atsu 0:d920d64db582 84 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
lynxeyed_atsu 0:d920d64db582 85 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
lynxeyed_atsu 0:d920d64db582 86 USBActivity_IRQn = 33, /*!< USB Activity Interrupt */
lynxeyed_atsu 0:d920d64db582 87 CANActivity_IRQn = 34, /*!< CAN Activity Interrupt */
lynxeyed_atsu 0:d920d64db582 88 } IRQn_Type;
lynxeyed_atsu 0:d920d64db582 89
lynxeyed_atsu 0:d920d64db582 90
lynxeyed_atsu 0:d920d64db582 91 /*
lynxeyed_atsu 0:d920d64db582 92 * ==========================================================================
lynxeyed_atsu 0:d920d64db582 93 * ----------- Processor and Core Peripheral Section ------------------------
lynxeyed_atsu 0:d920d64db582 94 * ==========================================================================
lynxeyed_atsu 0:d920d64db582 95 */
lynxeyed_atsu 0:d920d64db582 96
lynxeyed_atsu 0:d920d64db582 97 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
lynxeyed_atsu 0:d920d64db582 98 #define __MPU_PRESENT 1 /*!< MPU present or not */
lynxeyed_atsu 0:d920d64db582 99 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
lynxeyed_atsu 0:d920d64db582 100 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
lynxeyed_atsu 0:d920d64db582 101
lynxeyed_atsu 0:d920d64db582 102
lynxeyed_atsu 0:d920d64db582 103 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
lynxeyed_atsu 0:d920d64db582 104 #include "system_LPC17xx.h" /* System Header */
lynxeyed_atsu 0:d920d64db582 105
lynxeyed_atsu 0:d920d64db582 106
lynxeyed_atsu 0:d920d64db582 107 /******************************************************************************/
lynxeyed_atsu 0:d920d64db582 108 /* Device Specific Peripheral registers structures */
lynxeyed_atsu 0:d920d64db582 109 /******************************************************************************/
lynxeyed_atsu 0:d920d64db582 110
lynxeyed_atsu 0:d920d64db582 111 #if defined ( __CC_ARM )
lynxeyed_atsu 0:d920d64db582 112 #pragma anon_unions
lynxeyed_atsu 0:d920d64db582 113 #endif
lynxeyed_atsu 0:d920d64db582 114
lynxeyed_atsu 0:d920d64db582 115 /*------------- System Control (SC) ------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 116 /** @brief System Control (SC) register structure definition */
lynxeyed_atsu 0:d920d64db582 117 typedef struct
lynxeyed_atsu 0:d920d64db582 118 {
lynxeyed_atsu 0:d920d64db582 119 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
lynxeyed_atsu 0:d920d64db582 120 uint32_t RESERVED0[31];
lynxeyed_atsu 0:d920d64db582 121 __IO uint32_t PLL0CON; /* Clocking and Power Control */
lynxeyed_atsu 0:d920d64db582 122 __IO uint32_t PLL0CFG;
lynxeyed_atsu 0:d920d64db582 123 __I uint32_t PLL0STAT;
lynxeyed_atsu 0:d920d64db582 124 __O uint32_t PLL0FEED;
lynxeyed_atsu 0:d920d64db582 125 uint32_t RESERVED1[4];
lynxeyed_atsu 0:d920d64db582 126 __IO uint32_t PLL1CON;
lynxeyed_atsu 0:d920d64db582 127 __IO uint32_t PLL1CFG;
lynxeyed_atsu 0:d920d64db582 128 __I uint32_t PLL1STAT;
lynxeyed_atsu 0:d920d64db582 129 __O uint32_t PLL1FEED;
lynxeyed_atsu 0:d920d64db582 130 uint32_t RESERVED2[4];
lynxeyed_atsu 0:d920d64db582 131 __IO uint32_t PCON;
lynxeyed_atsu 0:d920d64db582 132 __IO uint32_t PCONP;
lynxeyed_atsu 0:d920d64db582 133 uint32_t RESERVED3[15];
lynxeyed_atsu 0:d920d64db582 134 __IO uint32_t CCLKCFG;
lynxeyed_atsu 0:d920d64db582 135 __IO uint32_t USBCLKCFG;
lynxeyed_atsu 0:d920d64db582 136 __IO uint32_t CLKSRCSEL;
lynxeyed_atsu 0:d920d64db582 137 __IO uint32_t CANSLEEPCLR;
lynxeyed_atsu 0:d920d64db582 138 __IO uint32_t CANWAKEFLAGS;
lynxeyed_atsu 0:d920d64db582 139 uint32_t RESERVED4[10];
lynxeyed_atsu 0:d920d64db582 140 __IO uint32_t EXTINT; /* External Interrupts */
lynxeyed_atsu 0:d920d64db582 141 uint32_t RESERVED5;
lynxeyed_atsu 0:d920d64db582 142 __IO uint32_t EXTMODE;
lynxeyed_atsu 0:d920d64db582 143 __IO uint32_t EXTPOLAR;
lynxeyed_atsu 0:d920d64db582 144 uint32_t RESERVED6[12];
lynxeyed_atsu 0:d920d64db582 145 __IO uint32_t RSID; /* Reset */
lynxeyed_atsu 0:d920d64db582 146 uint32_t RESERVED7[7];
lynxeyed_atsu 0:d920d64db582 147 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
lynxeyed_atsu 0:d920d64db582 148 __IO uint32_t IRCTRIM; /* Clock Dividers */
lynxeyed_atsu 0:d920d64db582 149 __IO uint32_t PCLKSEL0;
lynxeyed_atsu 0:d920d64db582 150 __IO uint32_t PCLKSEL1;
lynxeyed_atsu 0:d920d64db582 151 uint32_t RESERVED8[4];
lynxeyed_atsu 0:d920d64db582 152 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
lynxeyed_atsu 0:d920d64db582 153 __IO uint32_t DMAREQSEL;
lynxeyed_atsu 0:d920d64db582 154 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
lynxeyed_atsu 0:d920d64db582 155 } LPC_SC_TypeDef;
lynxeyed_atsu 0:d920d64db582 156
lynxeyed_atsu 0:d920d64db582 157 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
lynxeyed_atsu 0:d920d64db582 158 /** @brief Pin Connect Block (PINCON) register structure definition */
lynxeyed_atsu 0:d920d64db582 159 typedef struct
lynxeyed_atsu 0:d920d64db582 160 {
lynxeyed_atsu 0:d920d64db582 161 __IO uint32_t PINSEL0;
lynxeyed_atsu 0:d920d64db582 162 __IO uint32_t PINSEL1;
lynxeyed_atsu 0:d920d64db582 163 __IO uint32_t PINSEL2;
lynxeyed_atsu 0:d920d64db582 164 __IO uint32_t PINSEL3;
lynxeyed_atsu 0:d920d64db582 165 __IO uint32_t PINSEL4;
lynxeyed_atsu 0:d920d64db582 166 __IO uint32_t PINSEL5;
lynxeyed_atsu 0:d920d64db582 167 __IO uint32_t PINSEL6;
lynxeyed_atsu 0:d920d64db582 168 __IO uint32_t PINSEL7;
lynxeyed_atsu 0:d920d64db582 169 __IO uint32_t PINSEL8;
lynxeyed_atsu 0:d920d64db582 170 __IO uint32_t PINSEL9;
lynxeyed_atsu 0:d920d64db582 171 __IO uint32_t PINSEL10;
lynxeyed_atsu 0:d920d64db582 172 uint32_t RESERVED0[5];
lynxeyed_atsu 0:d920d64db582 173 __IO uint32_t PINMODE0;
lynxeyed_atsu 0:d920d64db582 174 __IO uint32_t PINMODE1;
lynxeyed_atsu 0:d920d64db582 175 __IO uint32_t PINMODE2;
lynxeyed_atsu 0:d920d64db582 176 __IO uint32_t PINMODE3;
lynxeyed_atsu 0:d920d64db582 177 __IO uint32_t PINMODE4;
lynxeyed_atsu 0:d920d64db582 178 __IO uint32_t PINMODE5;
lynxeyed_atsu 0:d920d64db582 179 __IO uint32_t PINMODE6;
lynxeyed_atsu 0:d920d64db582 180 __IO uint32_t PINMODE7;
lynxeyed_atsu 0:d920d64db582 181 __IO uint32_t PINMODE8;
lynxeyed_atsu 0:d920d64db582 182 __IO uint32_t PINMODE9;
lynxeyed_atsu 0:d920d64db582 183 __IO uint32_t PINMODE_OD0;
lynxeyed_atsu 0:d920d64db582 184 __IO uint32_t PINMODE_OD1;
lynxeyed_atsu 0:d920d64db582 185 __IO uint32_t PINMODE_OD2;
lynxeyed_atsu 0:d920d64db582 186 __IO uint32_t PINMODE_OD3;
lynxeyed_atsu 0:d920d64db582 187 __IO uint32_t PINMODE_OD4;
lynxeyed_atsu 0:d920d64db582 188 __IO uint32_t I2CPADCFG;
lynxeyed_atsu 0:d920d64db582 189 } LPC_PINCON_TypeDef;
lynxeyed_atsu 0:d920d64db582 190
lynxeyed_atsu 0:d920d64db582 191 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
lynxeyed_atsu 0:d920d64db582 192 /** @brief General Purpose Input/Output (GPIO) register structure definition */
lynxeyed_atsu 0:d920d64db582 193 typedef struct
lynxeyed_atsu 0:d920d64db582 194 {
lynxeyed_atsu 0:d920d64db582 195 union {
lynxeyed_atsu 0:d920d64db582 196 __IO uint32_t FIODIR;
lynxeyed_atsu 0:d920d64db582 197 struct {
lynxeyed_atsu 0:d920d64db582 198 __IO uint16_t FIODIRL;
lynxeyed_atsu 0:d920d64db582 199 __IO uint16_t FIODIRH;
lynxeyed_atsu 0:d920d64db582 200 };
lynxeyed_atsu 0:d920d64db582 201 struct {
lynxeyed_atsu 0:d920d64db582 202 __IO uint8_t FIODIR0;
lynxeyed_atsu 0:d920d64db582 203 __IO uint8_t FIODIR1;
lynxeyed_atsu 0:d920d64db582 204 __IO uint8_t FIODIR2;
lynxeyed_atsu 0:d920d64db582 205 __IO uint8_t FIODIR3;
lynxeyed_atsu 0:d920d64db582 206 };
lynxeyed_atsu 0:d920d64db582 207 };
lynxeyed_atsu 0:d920d64db582 208 uint32_t RESERVED0[3];
lynxeyed_atsu 0:d920d64db582 209 union {
lynxeyed_atsu 0:d920d64db582 210 __IO uint32_t FIOMASK;
lynxeyed_atsu 0:d920d64db582 211 struct {
lynxeyed_atsu 0:d920d64db582 212 __IO uint16_t FIOMASKL;
lynxeyed_atsu 0:d920d64db582 213 __IO uint16_t FIOMASKH;
lynxeyed_atsu 0:d920d64db582 214 };
lynxeyed_atsu 0:d920d64db582 215 struct {
lynxeyed_atsu 0:d920d64db582 216 __IO uint8_t FIOMASK0;
lynxeyed_atsu 0:d920d64db582 217 __IO uint8_t FIOMASK1;
lynxeyed_atsu 0:d920d64db582 218 __IO uint8_t FIOMASK2;
lynxeyed_atsu 0:d920d64db582 219 __IO uint8_t FIOMASK3;
lynxeyed_atsu 0:d920d64db582 220 };
lynxeyed_atsu 0:d920d64db582 221 };
lynxeyed_atsu 0:d920d64db582 222 union {
lynxeyed_atsu 0:d920d64db582 223 __IO uint32_t FIOPIN;
lynxeyed_atsu 0:d920d64db582 224 struct {
lynxeyed_atsu 0:d920d64db582 225 __IO uint16_t FIOPINL;
lynxeyed_atsu 0:d920d64db582 226 __IO uint16_t FIOPINH;
lynxeyed_atsu 0:d920d64db582 227 };
lynxeyed_atsu 0:d920d64db582 228 struct {
lynxeyed_atsu 0:d920d64db582 229 __IO uint8_t FIOPIN0;
lynxeyed_atsu 0:d920d64db582 230 __IO uint8_t FIOPIN1;
lynxeyed_atsu 0:d920d64db582 231 __IO uint8_t FIOPIN2;
lynxeyed_atsu 0:d920d64db582 232 __IO uint8_t FIOPIN3;
lynxeyed_atsu 0:d920d64db582 233 };
lynxeyed_atsu 0:d920d64db582 234 };
lynxeyed_atsu 0:d920d64db582 235 union {
lynxeyed_atsu 0:d920d64db582 236 __IO uint32_t FIOSET;
lynxeyed_atsu 0:d920d64db582 237 struct {
lynxeyed_atsu 0:d920d64db582 238 __IO uint16_t FIOSETL;
lynxeyed_atsu 0:d920d64db582 239 __IO uint16_t FIOSETH;
lynxeyed_atsu 0:d920d64db582 240 };
lynxeyed_atsu 0:d920d64db582 241 struct {
lynxeyed_atsu 0:d920d64db582 242 __IO uint8_t FIOSET0;
lynxeyed_atsu 0:d920d64db582 243 __IO uint8_t FIOSET1;
lynxeyed_atsu 0:d920d64db582 244 __IO uint8_t FIOSET2;
lynxeyed_atsu 0:d920d64db582 245 __IO uint8_t FIOSET3;
lynxeyed_atsu 0:d920d64db582 246 };
lynxeyed_atsu 0:d920d64db582 247 };
lynxeyed_atsu 0:d920d64db582 248 union {
lynxeyed_atsu 0:d920d64db582 249 __O uint32_t FIOCLR;
lynxeyed_atsu 0:d920d64db582 250 struct {
lynxeyed_atsu 0:d920d64db582 251 __O uint16_t FIOCLRL;
lynxeyed_atsu 0:d920d64db582 252 __O uint16_t FIOCLRH;
lynxeyed_atsu 0:d920d64db582 253 };
lynxeyed_atsu 0:d920d64db582 254 struct {
lynxeyed_atsu 0:d920d64db582 255 __O uint8_t FIOCLR0;
lynxeyed_atsu 0:d920d64db582 256 __O uint8_t FIOCLR1;
lynxeyed_atsu 0:d920d64db582 257 __O uint8_t FIOCLR2;
lynxeyed_atsu 0:d920d64db582 258 __O uint8_t FIOCLR3;
lynxeyed_atsu 0:d920d64db582 259 };
lynxeyed_atsu 0:d920d64db582 260 };
lynxeyed_atsu 0:d920d64db582 261 } LPC_GPIO_TypeDef;
lynxeyed_atsu 0:d920d64db582 262
lynxeyed_atsu 0:d920d64db582 263 /** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */
lynxeyed_atsu 0:d920d64db582 264 typedef struct
lynxeyed_atsu 0:d920d64db582 265 {
lynxeyed_atsu 0:d920d64db582 266 __I uint32_t IntStatus;
lynxeyed_atsu 0:d920d64db582 267 __I uint32_t IO0IntStatR;
lynxeyed_atsu 0:d920d64db582 268 __I uint32_t IO0IntStatF;
lynxeyed_atsu 0:d920d64db582 269 __O uint32_t IO0IntClr;
lynxeyed_atsu 0:d920d64db582 270 __IO uint32_t IO0IntEnR;
lynxeyed_atsu 0:d920d64db582 271 __IO uint32_t IO0IntEnF;
lynxeyed_atsu 0:d920d64db582 272 uint32_t RESERVED0[3];
lynxeyed_atsu 0:d920d64db582 273 __I uint32_t IO2IntStatR;
lynxeyed_atsu 0:d920d64db582 274 __I uint32_t IO2IntStatF;
lynxeyed_atsu 0:d920d64db582 275 __O uint32_t IO2IntClr;
lynxeyed_atsu 0:d920d64db582 276 __IO uint32_t IO2IntEnR;
lynxeyed_atsu 0:d920d64db582 277 __IO uint32_t IO2IntEnF;
lynxeyed_atsu 0:d920d64db582 278 } LPC_GPIOINT_TypeDef;
lynxeyed_atsu 0:d920d64db582 279
lynxeyed_atsu 0:d920d64db582 280 /*------------- Timer (TIM) --------------------------------------------------*/
lynxeyed_atsu 0:d920d64db582 281 /** @brief Timer (TIM) register structure definition */
lynxeyed_atsu 0:d920d64db582 282 typedef struct
lynxeyed_atsu 0:d920d64db582 283 {
lynxeyed_atsu 0:d920d64db582 284 __IO uint32_t IR;
lynxeyed_atsu 0:d920d64db582 285 __IO uint32_t TCR;
lynxeyed_atsu 0:d920d64db582 286 __IO uint32_t TC;
lynxeyed_atsu 0:d920d64db582 287 __IO uint32_t PR;
lynxeyed_atsu 0:d920d64db582 288 __IO uint32_t PC;
lynxeyed_atsu 0:d920d64db582 289 __IO uint32_t MCR;
lynxeyed_atsu 0:d920d64db582 290 __IO uint32_t MR0;
lynxeyed_atsu 0:d920d64db582 291 __IO uint32_t MR1;
lynxeyed_atsu 0:d920d64db582 292 __IO uint32_t MR2;
lynxeyed_atsu 0:d920d64db582 293 __IO uint32_t MR3;
lynxeyed_atsu 0:d920d64db582 294 __IO uint32_t CCR;
lynxeyed_atsu 0:d920d64db582 295 __I uint32_t CR0;
lynxeyed_atsu 0:d920d64db582 296 __I uint32_t CR1;
lynxeyed_atsu 0:d920d64db582 297 uint32_t RESERVED0[2];
lynxeyed_atsu 0:d920d64db582 298 __IO uint32_t EMR;
lynxeyed_atsu 0:d920d64db582 299 uint32_t RESERVED1[12];
lynxeyed_atsu 0:d920d64db582 300 __IO uint32_t CTCR;
lynxeyed_atsu 0:d920d64db582 301 } LPC_TIM_TypeDef;
lynxeyed_atsu 0:d920d64db582 302
lynxeyed_atsu 0:d920d64db582 303 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
lynxeyed_atsu 0:d920d64db582 304 /** @brief Pulse-Width Modulation (PWM) register structure definition */
lynxeyed_atsu 0:d920d64db582 305 typedef struct
lynxeyed_atsu 0:d920d64db582 306 {
lynxeyed_atsu 0:d920d64db582 307 __IO uint32_t IR;
lynxeyed_atsu 0:d920d64db582 308 __IO uint32_t TCR;
lynxeyed_atsu 0:d920d64db582 309 __IO uint32_t TC;
lynxeyed_atsu 0:d920d64db582 310 __IO uint32_t PR;
lynxeyed_atsu 0:d920d64db582 311 __IO uint32_t PC;
lynxeyed_atsu 0:d920d64db582 312 __IO uint32_t MCR;
lynxeyed_atsu 0:d920d64db582 313 __IO uint32_t MR0;
lynxeyed_atsu 0:d920d64db582 314 __IO uint32_t MR1;
lynxeyed_atsu 0:d920d64db582 315 __IO uint32_t MR2;
lynxeyed_atsu 0:d920d64db582 316 __IO uint32_t MR3;
lynxeyed_atsu 0:d920d64db582 317 __IO uint32_t CCR;
lynxeyed_atsu 0:d920d64db582 318 __I uint32_t CR0;
lynxeyed_atsu 0:d920d64db582 319 __I uint32_t CR1;
lynxeyed_atsu 0:d920d64db582 320 __I uint32_t CR2;
lynxeyed_atsu 0:d920d64db582 321 __I uint32_t CR3;
lynxeyed_atsu 0:d920d64db582 322 uint32_t RESERVED0;
lynxeyed_atsu 0:d920d64db582 323 __IO uint32_t MR4;
lynxeyed_atsu 0:d920d64db582 324 __IO uint32_t MR5;
lynxeyed_atsu 0:d920d64db582 325 __IO uint32_t MR6;
lynxeyed_atsu 0:d920d64db582 326 __IO uint32_t PCR;
lynxeyed_atsu 0:d920d64db582 327 __IO uint32_t LER;
lynxeyed_atsu 0:d920d64db582 328 uint32_t RESERVED1[7];
lynxeyed_atsu 0:d920d64db582 329 __IO uint32_t CTCR;
lynxeyed_atsu 0:d920d64db582 330 } LPC_PWM_TypeDef;
lynxeyed_atsu 0:d920d64db582 331
lynxeyed_atsu 0:d920d64db582 332 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
lynxeyed_atsu 0:d920d64db582 333 /** @brief Universal Asynchronous Receiver Transmitter (UART) register structure definition */
lynxeyed_atsu 0:d920d64db582 334 typedef struct
lynxeyed_atsu 0:d920d64db582 335 {
lynxeyed_atsu 0:d920d64db582 336 union {
lynxeyed_atsu 0:d920d64db582 337 __I uint8_t RBR;
lynxeyed_atsu 0:d920d64db582 338 __O uint8_t THR;
lynxeyed_atsu 0:d920d64db582 339 __IO uint8_t DLL;
lynxeyed_atsu 0:d920d64db582 340 uint32_t RESERVED0;
lynxeyed_atsu 0:d920d64db582 341 };
lynxeyed_atsu 0:d920d64db582 342 union {
lynxeyed_atsu 0:d920d64db582 343 __IO uint8_t DLM;
lynxeyed_atsu 0:d920d64db582 344 __IO uint32_t IER;
lynxeyed_atsu 0:d920d64db582 345 };
lynxeyed_atsu 0:d920d64db582 346 union {
lynxeyed_atsu 0:d920d64db582 347 __I uint32_t IIR;
lynxeyed_atsu 0:d920d64db582 348 __O uint8_t FCR;
lynxeyed_atsu 0:d920d64db582 349 };
lynxeyed_atsu 0:d920d64db582 350 __IO uint8_t LCR;
lynxeyed_atsu 0:d920d64db582 351 uint8_t RESERVED1[7];
lynxeyed_atsu 0:d920d64db582 352 __I uint8_t LSR;
lynxeyed_atsu 0:d920d64db582 353 uint8_t RESERVED2[7];
lynxeyed_atsu 0:d920d64db582 354 __IO uint8_t SCR;
lynxeyed_atsu 0:d920d64db582 355 uint8_t RESERVED3[3];
lynxeyed_atsu 0:d920d64db582 356 __IO uint32_t ACR;
lynxeyed_atsu 0:d920d64db582 357 __IO uint8_t ICR;
lynxeyed_atsu 0:d920d64db582 358 uint8_t RESERVED4[3];
lynxeyed_atsu 0:d920d64db582 359 __IO uint8_t FDR;
lynxeyed_atsu 0:d920d64db582 360 uint8_t RESERVED5[7];
lynxeyed_atsu 0:d920d64db582 361 __IO uint8_t TER;
lynxeyed_atsu 0:d920d64db582 362 uint8_t RESERVED6[39];
lynxeyed_atsu 0:d920d64db582 363 __I uint8_t FIFOLVL;
lynxeyed_atsu 0:d920d64db582 364 } LPC_UART_TypeDef;
lynxeyed_atsu 0:d920d64db582 365
lynxeyed_atsu 0:d920d64db582 366 /** @brief Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */
lynxeyed_atsu 0:d920d64db582 367 typedef struct
lynxeyed_atsu 0:d920d64db582 368 {
lynxeyed_atsu 0:d920d64db582 369 union {
lynxeyed_atsu 0:d920d64db582 370 __I uint8_t RBR;
lynxeyed_atsu 0:d920d64db582 371 __O uint8_t THR;
lynxeyed_atsu 0:d920d64db582 372 __IO uint8_t DLL;
lynxeyed_atsu 0:d920d64db582 373 uint32_t RESERVED0;
lynxeyed_atsu 0:d920d64db582 374 };
lynxeyed_atsu 0:d920d64db582 375 union {
lynxeyed_atsu 0:d920d64db582 376 __IO uint8_t DLM;
lynxeyed_atsu 0:d920d64db582 377 __IO uint32_t IER;
lynxeyed_atsu 0:d920d64db582 378 };
lynxeyed_atsu 0:d920d64db582 379 union {
lynxeyed_atsu 0:d920d64db582 380 __I uint32_t IIR;
lynxeyed_atsu 0:d920d64db582 381 __O uint8_t FCR;
lynxeyed_atsu 0:d920d64db582 382 };
lynxeyed_atsu 0:d920d64db582 383 __IO uint8_t LCR;
lynxeyed_atsu 0:d920d64db582 384 uint8_t RESERVED1[7];
lynxeyed_atsu 0:d920d64db582 385 __I uint8_t LSR;
lynxeyed_atsu 0:d920d64db582 386 uint8_t RESERVED2[7];
lynxeyed_atsu 0:d920d64db582 387 __IO uint8_t SCR;
lynxeyed_atsu 0:d920d64db582 388 uint8_t RESERVED3[3];
lynxeyed_atsu 0:d920d64db582 389 __IO uint32_t ACR;
lynxeyed_atsu 0:d920d64db582 390 __IO uint8_t ICR;
lynxeyed_atsu 0:d920d64db582 391 uint8_t RESERVED4[3];
lynxeyed_atsu 0:d920d64db582 392 __IO uint8_t FDR;
lynxeyed_atsu 0:d920d64db582 393 uint8_t RESERVED5[7];
lynxeyed_atsu 0:d920d64db582 394 __IO uint8_t TER;
lynxeyed_atsu 0:d920d64db582 395 uint8_t RESERVED6[39];
lynxeyed_atsu 0:d920d64db582 396 __I uint8_t FIFOLVL;
lynxeyed_atsu 0:d920d64db582 397 } LPC_UART0_TypeDef;
lynxeyed_atsu 0:d920d64db582 398
lynxeyed_atsu 0:d920d64db582 399 /** @brief Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition */
lynxeyed_atsu 0:d920d64db582 400 typedef struct
lynxeyed_atsu 0:d920d64db582 401 {
lynxeyed_atsu 0:d920d64db582 402 union {
lynxeyed_atsu 0:d920d64db582 403 __I uint8_t RBR;
lynxeyed_atsu 0:d920d64db582 404 __O uint8_t THR;
lynxeyed_atsu 0:d920d64db582 405 __IO uint8_t DLL;
lynxeyed_atsu 0:d920d64db582 406 uint32_t RESERVED0;
lynxeyed_atsu 0:d920d64db582 407 };
lynxeyed_atsu 0:d920d64db582 408 union {
lynxeyed_atsu 0:d920d64db582 409 __IO uint8_t DLM;
lynxeyed_atsu 0:d920d64db582 410 __IO uint32_t IER;
lynxeyed_atsu 0:d920d64db582 411 };
lynxeyed_atsu 0:d920d64db582 412 union {
lynxeyed_atsu 0:d920d64db582 413 __I uint32_t IIR;
lynxeyed_atsu 0:d920d64db582 414 __O uint8_t FCR;
lynxeyed_atsu 0:d920d64db582 415 };
lynxeyed_atsu 0:d920d64db582 416 __IO uint8_t LCR;
lynxeyed_atsu 0:d920d64db582 417 uint8_t RESERVED1[3];
lynxeyed_atsu 0:d920d64db582 418 __IO uint8_t MCR;
lynxeyed_atsu 0:d920d64db582 419 uint8_t RESERVED2[3];
lynxeyed_atsu 0:d920d64db582 420 __I uint8_t LSR;
lynxeyed_atsu 0:d920d64db582 421 uint8_t RESERVED3[3];
lynxeyed_atsu 0:d920d64db582 422 __I uint8_t MSR;
lynxeyed_atsu 0:d920d64db582 423 uint8_t RESERVED4[3];
lynxeyed_atsu 0:d920d64db582 424 __IO uint8_t SCR;
lynxeyed_atsu 0:d920d64db582 425 uint8_t RESERVED5[3];
lynxeyed_atsu 0:d920d64db582 426 __IO uint32_t ACR;
lynxeyed_atsu 0:d920d64db582 427 uint32_t RESERVED6;
lynxeyed_atsu 0:d920d64db582 428 __IO uint32_t FDR;
lynxeyed_atsu 0:d920d64db582 429 uint32_t RESERVED7;
lynxeyed_atsu 0:d920d64db582 430 __IO uint8_t TER;
lynxeyed_atsu 0:d920d64db582 431 uint8_t RESERVED8[27];
lynxeyed_atsu 0:d920d64db582 432 __IO uint8_t RS485CTRL;
lynxeyed_atsu 0:d920d64db582 433 uint8_t RESERVED9[3];
lynxeyed_atsu 0:d920d64db582 434 __IO uint8_t ADRMATCH;
lynxeyed_atsu 0:d920d64db582 435 uint8_t RESERVED10[3];
lynxeyed_atsu 0:d920d64db582 436 __IO uint8_t RS485DLY;
lynxeyed_atsu 0:d920d64db582 437 uint8_t RESERVED11[3];
lynxeyed_atsu 0:d920d64db582 438 __I uint8_t FIFOLVL;
lynxeyed_atsu 0:d920d64db582 439 } LPC_UART1_TypeDef;
lynxeyed_atsu 0:d920d64db582 440
lynxeyed_atsu 0:d920d64db582 441 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
lynxeyed_atsu 0:d920d64db582 442 /** @brief Serial Peripheral Interface (SPI) register structure definition */
lynxeyed_atsu 0:d920d64db582 443 typedef struct
lynxeyed_atsu 0:d920d64db582 444 {
lynxeyed_atsu 0:d920d64db582 445 __IO uint32_t SPCR;
lynxeyed_atsu 0:d920d64db582 446 __I uint32_t SPSR;
lynxeyed_atsu 0:d920d64db582 447 __IO uint32_t SPDR;
lynxeyed_atsu 0:d920d64db582 448 __IO uint32_t SPCCR;
lynxeyed_atsu 0:d920d64db582 449 uint32_t RESERVED0[3];
lynxeyed_atsu 0:d920d64db582 450 __IO uint32_t SPINT;
lynxeyed_atsu 0:d920d64db582 451 } LPC_SPI_TypeDef;
lynxeyed_atsu 0:d920d64db582 452
lynxeyed_atsu 0:d920d64db582 453 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
lynxeyed_atsu 0:d920d64db582 454 /** @brief Synchronous Serial Communication (SSP) register structure definition */
lynxeyed_atsu 0:d920d64db582 455 typedef struct
lynxeyed_atsu 0:d920d64db582 456 {
lynxeyed_atsu 0:d920d64db582 457 __IO uint32_t CR0;
lynxeyed_atsu 0:d920d64db582 458 __IO uint32_t CR1;
lynxeyed_atsu 0:d920d64db582 459 __IO uint32_t DR;
lynxeyed_atsu 0:d920d64db582 460 __I uint32_t SR;
lynxeyed_atsu 0:d920d64db582 461 __IO uint32_t CPSR;
lynxeyed_atsu 0:d920d64db582 462 __IO uint32_t IMSC;
lynxeyed_atsu 0:d920d64db582 463 __IO uint32_t RIS;
lynxeyed_atsu 0:d920d64db582 464 __IO uint32_t MIS;
lynxeyed_atsu 0:d920d64db582 465 __IO uint32_t ICR;
lynxeyed_atsu 0:d920d64db582 466 __IO uint32_t DMACR;
lynxeyed_atsu 0:d920d64db582 467 } LPC_SSP_TypeDef;
lynxeyed_atsu 0:d920d64db582 468
lynxeyed_atsu 0:d920d64db582 469 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
lynxeyed_atsu 0:d920d64db582 470 /** @brief Inter-Integrated Circuit (I2C) register structure definition */
lynxeyed_atsu 0:d920d64db582 471 typedef struct
lynxeyed_atsu 0:d920d64db582 472 {
lynxeyed_atsu 0:d920d64db582 473 __IO uint32_t I2CONSET;
lynxeyed_atsu 0:d920d64db582 474 __I uint32_t I2STAT;
lynxeyed_atsu 0:d920d64db582 475 __IO uint32_t I2DAT;
lynxeyed_atsu 0:d920d64db582 476 __IO uint32_t I2ADR0;
lynxeyed_atsu 0:d920d64db582 477 __IO uint32_t I2SCLH;
lynxeyed_atsu 0:d920d64db582 478 __IO uint32_t I2SCLL;
lynxeyed_atsu 0:d920d64db582 479 __O uint32_t I2CONCLR;
lynxeyed_atsu 0:d920d64db582 480 __IO uint32_t MMCTRL;
lynxeyed_atsu 0:d920d64db582 481 __IO uint32_t I2ADR1;
lynxeyed_atsu 0:d920d64db582 482 __IO uint32_t I2ADR2;
lynxeyed_atsu 0:d920d64db582 483 __IO uint32_t I2ADR3;
lynxeyed_atsu 0:d920d64db582 484 __I uint32_t I2DATA_BUFFER;
lynxeyed_atsu 0:d920d64db582 485 __IO uint32_t I2MASK0;
lynxeyed_atsu 0:d920d64db582 486 __IO uint32_t I2MASK1;
lynxeyed_atsu 0:d920d64db582 487 __IO uint32_t I2MASK2;
lynxeyed_atsu 0:d920d64db582 488 __IO uint32_t I2MASK3;
lynxeyed_atsu 0:d920d64db582 489 } LPC_I2C_TypeDef;
lynxeyed_atsu 0:d920d64db582 490
lynxeyed_atsu 0:d920d64db582 491 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
lynxeyed_atsu 0:d920d64db582 492 /** @brief Inter IC Sound (I2S) register structure definition */
lynxeyed_atsu 0:d920d64db582 493 typedef struct
lynxeyed_atsu 0:d920d64db582 494 {
lynxeyed_atsu 0:d920d64db582 495 __IO uint32_t I2SDAO;
lynxeyed_atsu 0:d920d64db582 496 __IO uint32_t I2SDAI;
lynxeyed_atsu 0:d920d64db582 497 __O uint32_t I2STXFIFO;
lynxeyed_atsu 0:d920d64db582 498 __I uint32_t I2SRXFIFO;
lynxeyed_atsu 0:d920d64db582 499 __I uint32_t I2SSTATE;
lynxeyed_atsu 0:d920d64db582 500 __IO uint32_t I2SDMA1;
lynxeyed_atsu 0:d920d64db582 501 __IO uint32_t I2SDMA2;
lynxeyed_atsu 0:d920d64db582 502 __IO uint32_t I2SIRQ;
lynxeyed_atsu 0:d920d64db582 503 __IO uint32_t I2STXRATE;
lynxeyed_atsu 0:d920d64db582 504 __IO uint32_t I2SRXRATE;
lynxeyed_atsu 0:d920d64db582 505 __IO uint32_t I2STXBITRATE;
lynxeyed_atsu 0:d920d64db582 506 __IO uint32_t I2SRXBITRATE;
lynxeyed_atsu 0:d920d64db582 507 __IO uint32_t I2STXMODE;
lynxeyed_atsu 0:d920d64db582 508 __IO uint32_t I2SRXMODE;
lynxeyed_atsu 0:d920d64db582 509 } LPC_I2S_TypeDef;
lynxeyed_atsu 0:d920d64db582 510
lynxeyed_atsu 0:d920d64db582 511 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
lynxeyed_atsu 0:d920d64db582 512 /** @brief Repetitive Interrupt Timer (RIT) register structure definition */
lynxeyed_atsu 0:d920d64db582 513 typedef struct
lynxeyed_atsu 0:d920d64db582 514 {
lynxeyed_atsu 0:d920d64db582 515 __IO uint32_t RICOMPVAL;
lynxeyed_atsu 0:d920d64db582 516 __IO uint32_t RIMASK;
lynxeyed_atsu 0:d920d64db582 517 __IO uint8_t RICTRL;
lynxeyed_atsu 0:d920d64db582 518 uint8_t RESERVED0[3];
lynxeyed_atsu 0:d920d64db582 519 __IO uint32_t RICOUNTER;
lynxeyed_atsu 0:d920d64db582 520 } LPC_RIT_TypeDef;
lynxeyed_atsu 0:d920d64db582 521
lynxeyed_atsu 0:d920d64db582 522 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
lynxeyed_atsu 0:d920d64db582 523 /** @brief Real-Time Clock (RTC) register structure definition */
lynxeyed_atsu 0:d920d64db582 524 typedef struct
lynxeyed_atsu 0:d920d64db582 525 {
lynxeyed_atsu 0:d920d64db582 526 __IO uint8_t ILR;
lynxeyed_atsu 0:d920d64db582 527 uint8_t RESERVED0[7];
lynxeyed_atsu 0:d920d64db582 528 __IO uint8_t CCR;
lynxeyed_atsu 0:d920d64db582 529 uint8_t RESERVED1[3];
lynxeyed_atsu 0:d920d64db582 530 __IO uint8_t CIIR;
lynxeyed_atsu 0:d920d64db582 531 uint8_t RESERVED2[3];
lynxeyed_atsu 0:d920d64db582 532 __IO uint8_t AMR;
lynxeyed_atsu 0:d920d64db582 533 uint8_t RESERVED3[3];
lynxeyed_atsu 0:d920d64db582 534 __I uint32_t CTIME0;
lynxeyed_atsu 0:d920d64db582 535 __I uint32_t CTIME1;
lynxeyed_atsu 0:d920d64db582 536 __I uint32_t CTIME2;
lynxeyed_atsu 0:d920d64db582 537 __IO uint8_t SEC;
lynxeyed_atsu 0:d920d64db582 538 uint8_t RESERVED4[3];
lynxeyed_atsu 0:d920d64db582 539 __IO uint8_t MIN;
lynxeyed_atsu 0:d920d64db582 540 uint8_t RESERVED5[3];
lynxeyed_atsu 0:d920d64db582 541 __IO uint8_t HOUR;
lynxeyed_atsu 0:d920d64db582 542 uint8_t RESERVED6[3];
lynxeyed_atsu 0:d920d64db582 543 __IO uint8_t DOM;
lynxeyed_atsu 0:d920d64db582 544 uint8_t RESERVED7[3];
lynxeyed_atsu 0:d920d64db582 545 __IO uint8_t DOW;
lynxeyed_atsu 0:d920d64db582 546 uint8_t RESERVED8[3];
lynxeyed_atsu 0:d920d64db582 547 __IO uint16_t DOY;
lynxeyed_atsu 0:d920d64db582 548 uint16_t RESERVED9;
lynxeyed_atsu 0:d920d64db582 549 __IO uint8_t MONTH;
lynxeyed_atsu 0:d920d64db582 550 uint8_t RESERVED10[3];
lynxeyed_atsu 0:d920d64db582 551 __IO uint16_t YEAR;
lynxeyed_atsu 0:d920d64db582 552 uint16_t RESERVED11;
lynxeyed_atsu 0:d920d64db582 553 __IO uint32_t CALIBRATION;
lynxeyed_atsu 0:d920d64db582 554 __IO uint32_t GPREG0;
lynxeyed_atsu 0:d920d64db582 555 __IO uint32_t GPREG1;
lynxeyed_atsu 0:d920d64db582 556 __IO uint32_t GPREG2;
lynxeyed_atsu 0:d920d64db582 557 __IO uint32_t GPREG3;
lynxeyed_atsu 0:d920d64db582 558 __IO uint32_t GPREG4;
lynxeyed_atsu 0:d920d64db582 559 __IO uint8_t RTC_AUXEN;
lynxeyed_atsu 0:d920d64db582 560 uint8_t RESERVED12[3];
lynxeyed_atsu 0:d920d64db582 561 __IO uint8_t RTC_AUX;
lynxeyed_atsu 0:d920d64db582 562 uint8_t RESERVED13[3];
lynxeyed_atsu 0:d920d64db582 563 __IO uint8_t ALSEC;
lynxeyed_atsu 0:d920d64db582 564 uint8_t RESERVED14[3];
lynxeyed_atsu 0:d920d64db582 565 __IO uint8_t ALMIN;
lynxeyed_atsu 0:d920d64db582 566 uint8_t RESERVED15[3];
lynxeyed_atsu 0:d920d64db582 567 __IO uint8_t ALHOUR;
lynxeyed_atsu 0:d920d64db582 568 uint8_t RESERVED16[3];
lynxeyed_atsu 0:d920d64db582 569 __IO uint8_t ALDOM;
lynxeyed_atsu 0:d920d64db582 570 uint8_t RESERVED17[3];
lynxeyed_atsu 0:d920d64db582 571 __IO uint8_t ALDOW;
lynxeyed_atsu 0:d920d64db582 572 uint8_t RESERVED18[3];
lynxeyed_atsu 0:d920d64db582 573 __IO uint16_t ALDOY;
lynxeyed_atsu 0:d920d64db582 574 uint16_t RESERVED19;
lynxeyed_atsu 0:d920d64db582 575 __IO uint8_t ALMON;
lynxeyed_atsu 0:d920d64db582 576 uint8_t RESERVED20[3];
lynxeyed_atsu 0:d920d64db582 577 __IO uint16_t ALYEAR;
lynxeyed_atsu 0:d920d64db582 578 uint16_t RESERVED21;
lynxeyed_atsu 0:d920d64db582 579 } LPC_RTC_TypeDef;
lynxeyed_atsu 0:d920d64db582 580
lynxeyed_atsu 0:d920d64db582 581 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
lynxeyed_atsu 0:d920d64db582 582 /** @brief Watchdog Timer (WDT) register structure definition */
lynxeyed_atsu 0:d920d64db582 583 typedef struct
lynxeyed_atsu 0:d920d64db582 584 {
lynxeyed_atsu 0:d920d64db582 585 __IO uint8_t WDMOD;
lynxeyed_atsu 0:d920d64db582 586 uint8_t RESERVED0[3];
lynxeyed_atsu 0:d920d64db582 587 __IO uint32_t WDTC;
lynxeyed_atsu 0:d920d64db582 588 __O uint8_t WDFEED;
lynxeyed_atsu 0:d920d64db582 589 uint8_t RESERVED1[3];
lynxeyed_atsu 0:d920d64db582 590 __I uint32_t WDTV;
lynxeyed_atsu 0:d920d64db582 591 __IO uint32_t WDCLKSEL;
lynxeyed_atsu 0:d920d64db582 592 } LPC_WDT_TypeDef;
lynxeyed_atsu 0:d920d64db582 593
lynxeyed_atsu 0:d920d64db582 594 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
lynxeyed_atsu 0:d920d64db582 595 /** @brief Analog-to-Digital Converter (ADC) register structure definition */
lynxeyed_atsu 0:d920d64db582 596 typedef struct
lynxeyed_atsu 0:d920d64db582 597 {
lynxeyed_atsu 0:d920d64db582 598 __IO uint32_t ADCR;
lynxeyed_atsu 0:d920d64db582 599 __IO uint32_t ADGDR;
lynxeyed_atsu 0:d920d64db582 600 uint32_t RESERVED0;
lynxeyed_atsu 0:d920d64db582 601 __IO uint32_t ADINTEN;
lynxeyed_atsu 0:d920d64db582 602 __I uint32_t ADDR0;
lynxeyed_atsu 0:d920d64db582 603 __I uint32_t ADDR1;
lynxeyed_atsu 0:d920d64db582 604 __I uint32_t ADDR2;
lynxeyed_atsu 0:d920d64db582 605 __I uint32_t ADDR3;
lynxeyed_atsu 0:d920d64db582 606 __I uint32_t ADDR4;
lynxeyed_atsu 0:d920d64db582 607 __I uint32_t ADDR5;
lynxeyed_atsu 0:d920d64db582 608 __I uint32_t ADDR6;
lynxeyed_atsu 0:d920d64db582 609 __I uint32_t ADDR7;
lynxeyed_atsu 0:d920d64db582 610 __I uint32_t ADSTAT;
lynxeyed_atsu 0:d920d64db582 611 __IO uint32_t ADTRM;
lynxeyed_atsu 0:d920d64db582 612 } LPC_ADC_TypeDef;
lynxeyed_atsu 0:d920d64db582 613
lynxeyed_atsu 0:d920d64db582 614 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
lynxeyed_atsu 0:d920d64db582 615 /** @brief Digital-to-Analog Converter (DAC) register structure definition */
lynxeyed_atsu 0:d920d64db582 616 typedef struct
lynxeyed_atsu 0:d920d64db582 617 {
lynxeyed_atsu 0:d920d64db582 618 __IO uint32_t DACR;
lynxeyed_atsu 0:d920d64db582 619 __IO uint32_t DACCTRL;
lynxeyed_atsu 0:d920d64db582 620 __IO uint16_t DACCNTVAL;
lynxeyed_atsu 0:d920d64db582 621 } LPC_DAC_TypeDef;
lynxeyed_atsu 0:d920d64db582 622
lynxeyed_atsu 0:d920d64db582 623 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
lynxeyed_atsu 0:d920d64db582 624 /** @brief Motor Control Pulse-Width Modulation (MCPWM) register structure definition */
lynxeyed_atsu 0:d920d64db582 625 typedef struct
lynxeyed_atsu 0:d920d64db582 626 {
lynxeyed_atsu 0:d920d64db582 627 __I uint32_t MCCON;
lynxeyed_atsu 0:d920d64db582 628 __O uint32_t MCCON_SET;
lynxeyed_atsu 0:d920d64db582 629 __O uint32_t MCCON_CLR;
lynxeyed_atsu 0:d920d64db582 630 __I uint32_t MCCAPCON;
lynxeyed_atsu 0:d920d64db582 631 __O uint32_t MCCAPCON_SET;
lynxeyed_atsu 0:d920d64db582 632 __O uint32_t MCCAPCON_CLR;
lynxeyed_atsu 0:d920d64db582 633 __IO uint32_t MCTIM0;
lynxeyed_atsu 0:d920d64db582 634 __IO uint32_t MCTIM1;
lynxeyed_atsu 0:d920d64db582 635 __IO uint32_t MCTIM2;
lynxeyed_atsu 0:d920d64db582 636 __IO uint32_t MCPER0;
lynxeyed_atsu 0:d920d64db582 637 __IO uint32_t MCPER1;
lynxeyed_atsu 0:d920d64db582 638 __IO uint32_t MCPER2;
lynxeyed_atsu 0:d920d64db582 639 __IO uint32_t MCPW0;
lynxeyed_atsu 0:d920d64db582 640 __IO uint32_t MCPW1;
lynxeyed_atsu 0:d920d64db582 641 __IO uint32_t MCPW2;
lynxeyed_atsu 0:d920d64db582 642 __IO uint32_t MCDEADTIME;
lynxeyed_atsu 0:d920d64db582 643 __IO uint32_t MCCCP;
lynxeyed_atsu 0:d920d64db582 644 __IO uint32_t MCCR0;
lynxeyed_atsu 0:d920d64db582 645 __IO uint32_t MCCR1;
lynxeyed_atsu 0:d920d64db582 646 __IO uint32_t MCCR2;
lynxeyed_atsu 0:d920d64db582 647 __I uint32_t MCINTEN;
lynxeyed_atsu 0:d920d64db582 648 __O uint32_t MCINTEN_SET;
lynxeyed_atsu 0:d920d64db582 649 __O uint32_t MCINTEN_CLR;
lynxeyed_atsu 0:d920d64db582 650 __I uint32_t MCCNTCON;
lynxeyed_atsu 0:d920d64db582 651 __O uint32_t MCCNTCON_SET;
lynxeyed_atsu 0:d920d64db582 652 __O uint32_t MCCNTCON_CLR;
lynxeyed_atsu 0:d920d64db582 653 __I uint32_t MCINTFLAG;
lynxeyed_atsu 0:d920d64db582 654 __O uint32_t MCINTFLAG_SET;
lynxeyed_atsu 0:d920d64db582 655 __O uint32_t MCINTFLAG_CLR;
lynxeyed_atsu 0:d920d64db582 656 __O uint32_t MCCAP_CLR;
lynxeyed_atsu 0:d920d64db582 657 } LPC_MCPWM_TypeDef;
lynxeyed_atsu 0:d920d64db582 658
lynxeyed_atsu 0:d920d64db582 659 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
lynxeyed_atsu 0:d920d64db582 660 /** @brief Quadrature Encoder Interface (QEI) register structure definition */
lynxeyed_atsu 0:d920d64db582 661 typedef struct
lynxeyed_atsu 0:d920d64db582 662 {
lynxeyed_atsu 0:d920d64db582 663 __O uint32_t QEICON;
lynxeyed_atsu 0:d920d64db582 664 __I uint32_t QEISTAT;
lynxeyed_atsu 0:d920d64db582 665 __IO uint32_t QEICONF;
lynxeyed_atsu 0:d920d64db582 666 __I uint32_t QEIPOS;
lynxeyed_atsu 0:d920d64db582 667 __IO uint32_t QEIMAXPOS;
lynxeyed_atsu 0:d920d64db582 668 __IO uint32_t CMPOS0;
lynxeyed_atsu 0:d920d64db582 669 __IO uint32_t CMPOS1;
lynxeyed_atsu 0:d920d64db582 670 __IO uint32_t CMPOS2;
lynxeyed_atsu 0:d920d64db582 671 __I uint32_t INXCNT;
lynxeyed_atsu 0:d920d64db582 672 __IO uint32_t INXCMP;
lynxeyed_atsu 0:d920d64db582 673 __IO uint32_t QEILOAD;
lynxeyed_atsu 0:d920d64db582 674 __I uint32_t QEITIME;
lynxeyed_atsu 0:d920d64db582 675 __I uint32_t QEIVEL;
lynxeyed_atsu 0:d920d64db582 676 __I uint32_t QEICAP;
lynxeyed_atsu 0:d920d64db582 677 __IO uint32_t VELCOMP;
lynxeyed_atsu 0:d920d64db582 678 __IO uint32_t FILTER;
lynxeyed_atsu 0:d920d64db582 679 uint32_t RESERVED0[998];
lynxeyed_atsu 0:d920d64db582 680 __O uint32_t QEIIEC;
lynxeyed_atsu 0:d920d64db582 681 __O uint32_t QEIIES;
lynxeyed_atsu 0:d920d64db582 682 __I uint32_t QEIINTSTAT;
lynxeyed_atsu 0:d920d64db582 683 __I uint32_t QEIIE;
lynxeyed_atsu 0:d920d64db582 684 __O uint32_t QEICLR;
lynxeyed_atsu 0:d920d64db582 685 __O uint32_t QEISET;
lynxeyed_atsu 0:d920d64db582 686 } LPC_QEI_TypeDef;
lynxeyed_atsu 0:d920d64db582 687
lynxeyed_atsu 0:d920d64db582 688 /*------------- Controller Area Network (CAN) --------------------------------*/
lynxeyed_atsu 0:d920d64db582 689 /** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */
lynxeyed_atsu 0:d920d64db582 690 typedef struct
lynxeyed_atsu 0:d920d64db582 691 {
lynxeyed_atsu 0:d920d64db582 692 __IO uint32_t mask[512]; /* ID Masks */
lynxeyed_atsu 0:d920d64db582 693 } LPC_CANAF_RAM_TypeDef;
lynxeyed_atsu 0:d920d64db582 694
lynxeyed_atsu 0:d920d64db582 695 /** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */
lynxeyed_atsu 0:d920d64db582 696 typedef struct /* Acceptance Filter Registers */
lynxeyed_atsu 0:d920d64db582 697 {
lynxeyed_atsu 0:d920d64db582 698 __IO uint32_t AFMR;
lynxeyed_atsu 0:d920d64db582 699 __IO uint32_t SFF_sa;
lynxeyed_atsu 0:d920d64db582 700 __IO uint32_t SFF_GRP_sa;
lynxeyed_atsu 0:d920d64db582 701 __IO uint32_t EFF_sa;
lynxeyed_atsu 0:d920d64db582 702 __IO uint32_t EFF_GRP_sa;
lynxeyed_atsu 0:d920d64db582 703 __IO uint32_t ENDofTable;
lynxeyed_atsu 0:d920d64db582 704 __I uint32_t LUTerrAd;
lynxeyed_atsu 0:d920d64db582 705 __I uint32_t LUTerr;
lynxeyed_atsu 0:d920d64db582 706 __IO uint32_t FCANIE;
lynxeyed_atsu 0:d920d64db582 707 __IO uint32_t FCANIC0;
lynxeyed_atsu 0:d920d64db582 708 __IO uint32_t FCANIC1;
lynxeyed_atsu 0:d920d64db582 709 } LPC_CANAF_TypeDef;
lynxeyed_atsu 0:d920d64db582 710
lynxeyed_atsu 0:d920d64db582 711 /** @brief Controller Area Network Central (CANCR) register structure definition */
lynxeyed_atsu 0:d920d64db582 712 typedef struct /* Central Registers */
lynxeyed_atsu 0:d920d64db582 713 {
lynxeyed_atsu 0:d920d64db582 714 __I uint32_t CANTxSR;
lynxeyed_atsu 0:d920d64db582 715 __I uint32_t CANRxSR;
lynxeyed_atsu 0:d920d64db582 716 __I uint32_t CANMSR;
lynxeyed_atsu 0:d920d64db582 717 } LPC_CANCR_TypeDef;
lynxeyed_atsu 0:d920d64db582 718
lynxeyed_atsu 0:d920d64db582 719 /** @brief Controller Area Network Controller (CAN) register structure definition */
lynxeyed_atsu 0:d920d64db582 720 typedef struct /* Controller Registers */
lynxeyed_atsu 0:d920d64db582 721 {
lynxeyed_atsu 0:d920d64db582 722 __IO uint32_t MOD;
lynxeyed_atsu 0:d920d64db582 723 __O uint32_t CMR;
lynxeyed_atsu 0:d920d64db582 724 __IO uint32_t GSR;
lynxeyed_atsu 0:d920d64db582 725 __I uint32_t ICR;
lynxeyed_atsu 0:d920d64db582 726 __IO uint32_t IER;
lynxeyed_atsu 0:d920d64db582 727 __IO uint32_t BTR;
lynxeyed_atsu 0:d920d64db582 728 __IO uint32_t EWL;
lynxeyed_atsu 0:d920d64db582 729 __I uint32_t SR;
lynxeyed_atsu 0:d920d64db582 730 __IO uint32_t RFS;
lynxeyed_atsu 0:d920d64db582 731 __IO uint32_t RID;
lynxeyed_atsu 0:d920d64db582 732 __IO uint32_t RDA;
lynxeyed_atsu 0:d920d64db582 733 __IO uint32_t RDB;
lynxeyed_atsu 0:d920d64db582 734 __IO uint32_t TFI1;
lynxeyed_atsu 0:d920d64db582 735 __IO uint32_t TID1;
lynxeyed_atsu 0:d920d64db582 736 __IO uint32_t TDA1;
lynxeyed_atsu 0:d920d64db582 737 __IO uint32_t TDB1;
lynxeyed_atsu 0:d920d64db582 738 __IO uint32_t TFI2;
lynxeyed_atsu 0:d920d64db582 739 __IO uint32_t TID2;
lynxeyed_atsu 0:d920d64db582 740 __IO uint32_t TDA2;
lynxeyed_atsu 0:d920d64db582 741 __IO uint32_t TDB2;
lynxeyed_atsu 0:d920d64db582 742 __IO uint32_t TFI3;
lynxeyed_atsu 0:d920d64db582 743 __IO uint32_t TID3;
lynxeyed_atsu 0:d920d64db582 744 __IO uint32_t TDA3;
lynxeyed_atsu 0:d920d64db582 745 __IO uint32_t TDB3;
lynxeyed_atsu 0:d920d64db582 746 } LPC_CAN_TypeDef;
lynxeyed_atsu 0:d920d64db582 747
lynxeyed_atsu 0:d920d64db582 748 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
lynxeyed_atsu 0:d920d64db582 749 /** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */
lynxeyed_atsu 0:d920d64db582 750 typedef struct /* Common Registers */
lynxeyed_atsu 0:d920d64db582 751 {
lynxeyed_atsu 0:d920d64db582 752 __I uint32_t DMACIntStat;
lynxeyed_atsu 0:d920d64db582 753 __I uint32_t DMACIntTCStat;
lynxeyed_atsu 0:d920d64db582 754 __O uint32_t DMACIntTCClear;
lynxeyed_atsu 0:d920d64db582 755 __I uint32_t DMACIntErrStat;
lynxeyed_atsu 0:d920d64db582 756 __O uint32_t DMACIntErrClr;
lynxeyed_atsu 0:d920d64db582 757 __I uint32_t DMACRawIntTCStat;
lynxeyed_atsu 0:d920d64db582 758 __I uint32_t DMACRawIntErrStat;
lynxeyed_atsu 0:d920d64db582 759 __I uint32_t DMACEnbldChns;
lynxeyed_atsu 0:d920d64db582 760 __IO uint32_t DMACSoftBReq;
lynxeyed_atsu 0:d920d64db582 761 __IO uint32_t DMACSoftSReq;
lynxeyed_atsu 0:d920d64db582 762 __IO uint32_t DMACSoftLBReq;
lynxeyed_atsu 0:d920d64db582 763 __IO uint32_t DMACSoftLSReq;
lynxeyed_atsu 0:d920d64db582 764 __IO uint32_t DMACConfig;
lynxeyed_atsu 0:d920d64db582 765 __IO uint32_t DMACSync;
lynxeyed_atsu 0:d920d64db582 766 } LPC_GPDMA_TypeDef;
lynxeyed_atsu 0:d920d64db582 767
lynxeyed_atsu 0:d920d64db582 768 /** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */
lynxeyed_atsu 0:d920d64db582 769 typedef struct /* Channel Registers */
lynxeyed_atsu 0:d920d64db582 770 {
lynxeyed_atsu 0:d920d64db582 771 __IO uint32_t DMACCSrcAddr;
lynxeyed_atsu 0:d920d64db582 772 __IO uint32_t DMACCDestAddr;
lynxeyed_atsu 0:d920d64db582 773 __IO uint32_t DMACCLLI;
lynxeyed_atsu 0:d920d64db582 774 __IO uint32_t DMACCControl;
lynxeyed_atsu 0:d920d64db582 775 __IO uint32_t DMACCConfig;
lynxeyed_atsu 0:d920d64db582 776 } LPC_GPDMACH_TypeDef;
lynxeyed_atsu 0:d920d64db582 777
lynxeyed_atsu 0:d920d64db582 778 /*------------- Universal Serial Bus (USB) -----------------------------------*/
lynxeyed_atsu 0:d920d64db582 779 /** @brief Universal Serial Bus (USB) register structure definition */
lynxeyed_atsu 0:d920d64db582 780 typedef struct
lynxeyed_atsu 0:d920d64db582 781 {
lynxeyed_atsu 0:d920d64db582 782 __I uint32_t HcRevision; /* USB Host Registers */
lynxeyed_atsu 0:d920d64db582 783 __IO uint32_t HcControl;
lynxeyed_atsu 0:d920d64db582 784 __IO uint32_t HcCommandStatus;
lynxeyed_atsu 0:d920d64db582 785 __IO uint32_t HcInterruptStatus;
lynxeyed_atsu 0:d920d64db582 786 __IO uint32_t HcInterruptEnable;
lynxeyed_atsu 0:d920d64db582 787 __IO uint32_t HcInterruptDisable;
lynxeyed_atsu 0:d920d64db582 788 __IO uint32_t HcHCCA;
lynxeyed_atsu 0:d920d64db582 789 __I uint32_t HcPeriodCurrentED;
lynxeyed_atsu 0:d920d64db582 790 __IO uint32_t HcControlHeadED;
lynxeyed_atsu 0:d920d64db582 791 __IO uint32_t HcControlCurrentED;
lynxeyed_atsu 0:d920d64db582 792 __IO uint32_t HcBulkHeadED;
lynxeyed_atsu 0:d920d64db582 793 __IO uint32_t HcBulkCurrentED;
lynxeyed_atsu 0:d920d64db582 794 __I uint32_t HcDoneHead;
lynxeyed_atsu 0:d920d64db582 795 __IO uint32_t HcFmInterval;
lynxeyed_atsu 0:d920d64db582 796 __I uint32_t HcFmRemaining;
lynxeyed_atsu 0:d920d64db582 797 __I uint32_t HcFmNumber;
lynxeyed_atsu 0:d920d64db582 798 __IO uint32_t HcPeriodicStart;
lynxeyed_atsu 0:d920d64db582 799 __IO uint32_t HcLSTreshold;
lynxeyed_atsu 0:d920d64db582 800 __IO uint32_t HcRhDescriptorA;
lynxeyed_atsu 0:d920d64db582 801 __IO uint32_t HcRhDescriptorB;
lynxeyed_atsu 0:d920d64db582 802 __IO uint32_t HcRhStatus;
lynxeyed_atsu 0:d920d64db582 803 __IO uint32_t HcRhPortStatus1;
lynxeyed_atsu 0:d920d64db582 804 __IO uint32_t HcRhPortStatus2;
lynxeyed_atsu 0:d920d64db582 805 uint32_t RESERVED0[40];
lynxeyed_atsu 0:d920d64db582 806 __I uint32_t Module_ID;
lynxeyed_atsu 0:d920d64db582 807
lynxeyed_atsu 0:d920d64db582 808 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
lynxeyed_atsu 0:d920d64db582 809 __IO uint32_t OTGIntEn;
lynxeyed_atsu 0:d920d64db582 810 __O uint32_t OTGIntSet;
lynxeyed_atsu 0:d920d64db582 811 __O uint32_t OTGIntClr;
lynxeyed_atsu 0:d920d64db582 812 __IO uint32_t OTGStCtrl;
lynxeyed_atsu 0:d920d64db582 813 __IO uint32_t OTGTmr;
lynxeyed_atsu 0:d920d64db582 814 uint32_t RESERVED1[58];
lynxeyed_atsu 0:d920d64db582 815
lynxeyed_atsu 0:d920d64db582 816 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
lynxeyed_atsu 0:d920d64db582 817 __IO uint32_t USBDevIntEn;
lynxeyed_atsu 0:d920d64db582 818 __O uint32_t USBDevIntClr;
lynxeyed_atsu 0:d920d64db582 819 __O uint32_t USBDevIntSet;
lynxeyed_atsu 0:d920d64db582 820
lynxeyed_atsu 0:d920d64db582 821 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
lynxeyed_atsu 0:d920d64db582 822 __I uint32_t USBCmdData;
lynxeyed_atsu 0:d920d64db582 823
lynxeyed_atsu 0:d920d64db582 824 __I uint32_t USBRxData; /* USB Device Transfer Registers */
lynxeyed_atsu 0:d920d64db582 825 __O uint32_t USBTxData;
lynxeyed_atsu 0:d920d64db582 826 __I uint32_t USBRxPLen;
lynxeyed_atsu 0:d920d64db582 827 __O uint32_t USBTxPLen;
lynxeyed_atsu 0:d920d64db582 828 __IO uint32_t USBCtrl;
lynxeyed_atsu 0:d920d64db582 829 __O uint32_t USBDevIntPri;
lynxeyed_atsu 0:d920d64db582 830
lynxeyed_atsu 0:d920d64db582 831 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
lynxeyed_atsu 0:d920d64db582 832 __IO uint32_t USBEpIntEn;
lynxeyed_atsu 0:d920d64db582 833 __O uint32_t USBEpIntClr;
lynxeyed_atsu 0:d920d64db582 834 __O uint32_t USBEpIntSet;
lynxeyed_atsu 0:d920d64db582 835 __O uint32_t USBEpIntPri;
lynxeyed_atsu 0:d920d64db582 836
lynxeyed_atsu 0:d920d64db582 837 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
lynxeyed_atsu 0:d920d64db582 838 __O uint32_t USBEpInd;
lynxeyed_atsu 0:d920d64db582 839 __IO uint32_t USBMaxPSize;
lynxeyed_atsu 0:d920d64db582 840
lynxeyed_atsu 0:d920d64db582 841 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
lynxeyed_atsu 0:d920d64db582 842 __O uint32_t USBDMARClr;
lynxeyed_atsu 0:d920d64db582 843 __O uint32_t USBDMARSet;
lynxeyed_atsu 0:d920d64db582 844 uint32_t RESERVED2[9];
lynxeyed_atsu 0:d920d64db582 845 __IO uint32_t USBUDCAH;
lynxeyed_atsu 0:d920d64db582 846 __I uint32_t USBEpDMASt;
lynxeyed_atsu 0:d920d64db582 847 __O uint32_t USBEpDMAEn;
lynxeyed_atsu 0:d920d64db582 848 __O uint32_t USBEpDMADis;
lynxeyed_atsu 0:d920d64db582 849 __I uint32_t USBDMAIntSt;
lynxeyed_atsu 0:d920d64db582 850 __IO uint32_t USBDMAIntEn;
lynxeyed_atsu 0:d920d64db582 851 uint32_t RESERVED3[2];
lynxeyed_atsu 0:d920d64db582 852 __I uint32_t USBEoTIntSt;
lynxeyed_atsu 0:d920d64db582 853 __O uint32_t USBEoTIntClr;
lynxeyed_atsu 0:d920d64db582 854 __O uint32_t USBEoTIntSet;
lynxeyed_atsu 0:d920d64db582 855 __I uint32_t USBNDDRIntSt;
lynxeyed_atsu 0:d920d64db582 856 __O uint32_t USBNDDRIntClr;
lynxeyed_atsu 0:d920d64db582 857 __O uint32_t USBNDDRIntSet;
lynxeyed_atsu 0:d920d64db582 858 __I uint32_t USBSysErrIntSt;
lynxeyed_atsu 0:d920d64db582 859 __O uint32_t USBSysErrIntClr;
lynxeyed_atsu 0:d920d64db582 860 __O uint32_t USBSysErrIntSet;
lynxeyed_atsu 0:d920d64db582 861 uint32_t RESERVED4[15];
lynxeyed_atsu 0:d920d64db582 862
lynxeyed_atsu 0:d920d64db582 863 union {
lynxeyed_atsu 0:d920d64db582 864 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
lynxeyed_atsu 0:d920d64db582 865 __O uint32_t I2C_TX;
lynxeyed_atsu 0:d920d64db582 866 };
lynxeyed_atsu 0:d920d64db582 867 __I uint32_t I2C_STS;
lynxeyed_atsu 0:d920d64db582 868 __IO uint32_t I2C_CTL;
lynxeyed_atsu 0:d920d64db582 869 __IO uint32_t I2C_CLKHI;
lynxeyed_atsu 0:d920d64db582 870 __O uint32_t I2C_CLKLO;
lynxeyed_atsu 0:d920d64db582 871 uint32_t RESERVED5[824];
lynxeyed_atsu 0:d920d64db582 872
lynxeyed_atsu 0:d920d64db582 873 union {
lynxeyed_atsu 0:d920d64db582 874 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
lynxeyed_atsu 0:d920d64db582 875 __IO uint32_t OTGClkCtrl;
lynxeyed_atsu 0:d920d64db582 876 };
lynxeyed_atsu 0:d920d64db582 877 union {
lynxeyed_atsu 0:d920d64db582 878 __I uint32_t USBClkSt;
lynxeyed_atsu 0:d920d64db582 879 __I uint32_t OTGClkSt;
lynxeyed_atsu 0:d920d64db582 880 };
lynxeyed_atsu 0:d920d64db582 881 } LPC_USB_TypeDef;
lynxeyed_atsu 0:d920d64db582 882
lynxeyed_atsu 0:d920d64db582 883 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
lynxeyed_atsu 0:d920d64db582 884 /** @brief Ethernet Media Access Controller (EMAC) register structure definition */
lynxeyed_atsu 0:d920d64db582 885 typedef struct
lynxeyed_atsu 0:d920d64db582 886 {
lynxeyed_atsu 0:d920d64db582 887 __IO uint32_t MAC1; /* MAC Registers */
lynxeyed_atsu 0:d920d64db582 888 __IO uint32_t MAC2;
lynxeyed_atsu 0:d920d64db582 889 __IO uint32_t IPGT;
lynxeyed_atsu 0:d920d64db582 890 __IO uint32_t IPGR;
lynxeyed_atsu 0:d920d64db582 891 __IO uint32_t CLRT;
lynxeyed_atsu 0:d920d64db582 892 __IO uint32_t MAXF;
lynxeyed_atsu 0:d920d64db582 893 __IO uint32_t SUPP;
lynxeyed_atsu 0:d920d64db582 894 __IO uint32_t TEST;
lynxeyed_atsu 0:d920d64db582 895 __IO uint32_t MCFG;
lynxeyed_atsu 0:d920d64db582 896 __IO uint32_t MCMD;
lynxeyed_atsu 0:d920d64db582 897 __IO uint32_t MADR;
lynxeyed_atsu 0:d920d64db582 898 __O uint32_t MWTD;
lynxeyed_atsu 0:d920d64db582 899 __I uint32_t MRDD;
lynxeyed_atsu 0:d920d64db582 900 __I uint32_t MIND;
lynxeyed_atsu 0:d920d64db582 901 uint32_t RESERVED0[2];
lynxeyed_atsu 0:d920d64db582 902 __IO uint32_t SA0;
lynxeyed_atsu 0:d920d64db582 903 __IO uint32_t SA1;
lynxeyed_atsu 0:d920d64db582 904 __IO uint32_t SA2;
lynxeyed_atsu 0:d920d64db582 905 uint32_t RESERVED1[45];
lynxeyed_atsu 0:d920d64db582 906 __IO uint32_t Command; /* Control Registers */
lynxeyed_atsu 0:d920d64db582 907 __I uint32_t Status;
lynxeyed_atsu 0:d920d64db582 908 __IO uint32_t RxDescriptor;
lynxeyed_atsu 0:d920d64db582 909 __IO uint32_t RxStatus;
lynxeyed_atsu 0:d920d64db582 910 __IO uint32_t RxDescriptorNumber;
lynxeyed_atsu 0:d920d64db582 911 __I uint32_t RxProduceIndex;
lynxeyed_atsu 0:d920d64db582 912 __IO uint32_t RxConsumeIndex;
lynxeyed_atsu 0:d920d64db582 913 __IO uint32_t TxDescriptor;
lynxeyed_atsu 0:d920d64db582 914 __IO uint32_t TxStatus;
lynxeyed_atsu 0:d920d64db582 915 __IO uint32_t TxDescriptorNumber;
lynxeyed_atsu 0:d920d64db582 916 __IO uint32_t TxProduceIndex;
lynxeyed_atsu 0:d920d64db582 917 __I uint32_t TxConsumeIndex;
lynxeyed_atsu 0:d920d64db582 918 uint32_t RESERVED2[10];
lynxeyed_atsu 0:d920d64db582 919 __I uint32_t TSV0;
lynxeyed_atsu 0:d920d64db582 920 __I uint32_t TSV1;
lynxeyed_atsu 0:d920d64db582 921 __I uint32_t RSV;
lynxeyed_atsu 0:d920d64db582 922 uint32_t RESERVED3[3];
lynxeyed_atsu 0:d920d64db582 923 __IO uint32_t FlowControlCounter;
lynxeyed_atsu 0:d920d64db582 924 __I uint32_t FlowControlStatus;
lynxeyed_atsu 0:d920d64db582 925 uint32_t RESERVED4[34];
lynxeyed_atsu 0:d920d64db582 926 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
lynxeyed_atsu 0:d920d64db582 927 __IO uint32_t RxFilterWoLStatus;
lynxeyed_atsu 0:d920d64db582 928 __IO uint32_t RxFilterWoLClear;
lynxeyed_atsu 0:d920d64db582 929 uint32_t RESERVED5;
lynxeyed_atsu 0:d920d64db582 930 __IO uint32_t HashFilterL;
lynxeyed_atsu 0:d920d64db582 931 __IO uint32_t HashFilterH;
lynxeyed_atsu 0:d920d64db582 932 uint32_t RESERVED6[882];
lynxeyed_atsu 0:d920d64db582 933 __I uint32_t IntStatus; /* Module Control Registers */
lynxeyed_atsu 0:d920d64db582 934 __IO uint32_t IntEnable;
lynxeyed_atsu 0:d920d64db582 935 __O uint32_t IntClear;
lynxeyed_atsu 0:d920d64db582 936 __O uint32_t IntSet;
lynxeyed_atsu 0:d920d64db582 937 uint32_t RESERVED7;
lynxeyed_atsu 0:d920d64db582 938 __IO uint32_t PowerDown;
lynxeyed_atsu 0:d920d64db582 939 uint32_t RESERVED8;
lynxeyed_atsu 0:d920d64db582 940 __IO uint32_t Module_ID;
lynxeyed_atsu 0:d920d64db582 941 } LPC_EMAC_TypeDef;
lynxeyed_atsu 0:d920d64db582 942
lynxeyed_atsu 0:d920d64db582 943
lynxeyed_atsu 0:d920d64db582 944 #if defined ( __CC_ARM )
lynxeyed_atsu 0:d920d64db582 945 #pragma no_anon_unions
lynxeyed_atsu 0:d920d64db582 946 #endif
lynxeyed_atsu 0:d920d64db582 947
lynxeyed_atsu 0:d920d64db582 948
lynxeyed_atsu 0:d920d64db582 949 /******************************************************************************/
lynxeyed_atsu 0:d920d64db582 950 /* Peripheral memory map */
lynxeyed_atsu 0:d920d64db582 951 /******************************************************************************/
lynxeyed_atsu 0:d920d64db582 952 /* Base addresses */
lynxeyed_atsu 0:d920d64db582 953 #define LPC_FLASH_BASE (0x00000000UL)
lynxeyed_atsu 0:d920d64db582 954 #define LPC_RAM_BASE (0x10000000UL)
lynxeyed_atsu 0:d920d64db582 955 #ifdef __LPC17XX_REV00
lynxeyed_atsu 0:d920d64db582 956 #define LPC_AHBRAM0_BASE (0x20000000UL)
lynxeyed_atsu 0:d920d64db582 957 #define LPC_AHBRAM1_BASE (0x20004000UL)
lynxeyed_atsu 0:d920d64db582 958 #else
lynxeyed_atsu 0:d920d64db582 959 #define LPC_AHBRAM0_BASE (0x2007C000UL)
lynxeyed_atsu 0:d920d64db582 960 #define LPC_AHBRAM1_BASE (0x20080000UL)
lynxeyed_atsu 0:d920d64db582 961 #endif
lynxeyed_atsu 0:d920d64db582 962 #define LPC_GPIO_BASE (0x2009C000UL)
lynxeyed_atsu 0:d920d64db582 963 #define LPC_APB0_BASE (0x40000000UL)
lynxeyed_atsu 0:d920d64db582 964 #define LPC_APB1_BASE (0x40080000UL)
lynxeyed_atsu 0:d920d64db582 965 #define LPC_AHB_BASE (0x50000000UL)
lynxeyed_atsu 0:d920d64db582 966 #define LPC_CM3_BASE (0xE0000000UL)
lynxeyed_atsu 0:d920d64db582 967
lynxeyed_atsu 0:d920d64db582 968 /* APB0 peripherals */
lynxeyed_atsu 0:d920d64db582 969 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
lynxeyed_atsu 0:d920d64db582 970 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
lynxeyed_atsu 0:d920d64db582 971 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
lynxeyed_atsu 0:d920d64db582 972 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
lynxeyed_atsu 0:d920d64db582 973 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
lynxeyed_atsu 0:d920d64db582 974 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
lynxeyed_atsu 0:d920d64db582 975 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
lynxeyed_atsu 0:d920d64db582 976 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
lynxeyed_atsu 0:d920d64db582 977 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
lynxeyed_atsu 0:d920d64db582 978 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
lynxeyed_atsu 0:d920d64db582 979 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
lynxeyed_atsu 0:d920d64db582 980 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
lynxeyed_atsu 0:d920d64db582 981 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
lynxeyed_atsu 0:d920d64db582 982 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
lynxeyed_atsu 0:d920d64db582 983 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
lynxeyed_atsu 0:d920d64db582 984 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
lynxeyed_atsu 0:d920d64db582 985 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
lynxeyed_atsu 0:d920d64db582 986 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
lynxeyed_atsu 0:d920d64db582 987 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
lynxeyed_atsu 0:d920d64db582 988
lynxeyed_atsu 0:d920d64db582 989 /* APB1 peripherals */
lynxeyed_atsu 0:d920d64db582 990 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
lynxeyed_atsu 0:d920d64db582 991 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
lynxeyed_atsu 0:d920d64db582 992 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
lynxeyed_atsu 0:d920d64db582 993 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
lynxeyed_atsu 0:d920d64db582 994 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
lynxeyed_atsu 0:d920d64db582 995 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
lynxeyed_atsu 0:d920d64db582 996 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
lynxeyed_atsu 0:d920d64db582 997 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
lynxeyed_atsu 0:d920d64db582 998 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
lynxeyed_atsu 0:d920d64db582 999 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
lynxeyed_atsu 0:d920d64db582 1000 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
lynxeyed_atsu 0:d920d64db582 1001 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
lynxeyed_atsu 0:d920d64db582 1002
lynxeyed_atsu 0:d920d64db582 1003 /* AHB peripherals */
lynxeyed_atsu 0:d920d64db582 1004 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
lynxeyed_atsu 0:d920d64db582 1005 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
lynxeyed_atsu 0:d920d64db582 1006 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
lynxeyed_atsu 0:d920d64db582 1007 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
lynxeyed_atsu 0:d920d64db582 1008 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
lynxeyed_atsu 0:d920d64db582 1009 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
lynxeyed_atsu 0:d920d64db582 1010 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
lynxeyed_atsu 0:d920d64db582 1011 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
lynxeyed_atsu 0:d920d64db582 1012 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
lynxeyed_atsu 0:d920d64db582 1013 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
lynxeyed_atsu 0:d920d64db582 1014 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
lynxeyed_atsu 0:d920d64db582 1015
lynxeyed_atsu 0:d920d64db582 1016 /* GPIOs */
lynxeyed_atsu 0:d920d64db582 1017 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
lynxeyed_atsu 0:d920d64db582 1018 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
lynxeyed_atsu 0:d920d64db582 1019 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
lynxeyed_atsu 0:d920d64db582 1020 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
lynxeyed_atsu 0:d920d64db582 1021 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
lynxeyed_atsu 0:d920d64db582 1022
lynxeyed_atsu 0:d920d64db582 1023 /******************************************************************************/
lynxeyed_atsu 0:d920d64db582 1024 /* Peripheral declaration */
lynxeyed_atsu 0:d920d64db582 1025 /******************************************************************************/
lynxeyed_atsu 0:d920d64db582 1026 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
lynxeyed_atsu 0:d920d64db582 1027 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
lynxeyed_atsu 0:d920d64db582 1028 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
lynxeyed_atsu 0:d920d64db582 1029 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
lynxeyed_atsu 0:d920d64db582 1030 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
lynxeyed_atsu 0:d920d64db582 1031 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
lynxeyed_atsu 0:d920d64db582 1032 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
lynxeyed_atsu 0:d920d64db582 1033 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
lynxeyed_atsu 0:d920d64db582 1034 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
lynxeyed_atsu 0:d920d64db582 1035 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
lynxeyed_atsu 0:d920d64db582 1036 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
lynxeyed_atsu 0:d920d64db582 1037 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
lynxeyed_atsu 0:d920d64db582 1038 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
lynxeyed_atsu 0:d920d64db582 1039 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
lynxeyed_atsu 0:d920d64db582 1040 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
lynxeyed_atsu 0:d920d64db582 1041 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
lynxeyed_atsu 0:d920d64db582 1042 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
lynxeyed_atsu 0:d920d64db582 1043 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
lynxeyed_atsu 0:d920d64db582 1044 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
lynxeyed_atsu 0:d920d64db582 1045 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
lynxeyed_atsu 0:d920d64db582 1046 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
lynxeyed_atsu 0:d920d64db582 1047 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
lynxeyed_atsu 0:d920d64db582 1048 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
lynxeyed_atsu 0:d920d64db582 1049 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
lynxeyed_atsu 0:d920d64db582 1050 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
lynxeyed_atsu 0:d920d64db582 1051 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
lynxeyed_atsu 0:d920d64db582 1052 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
lynxeyed_atsu 0:d920d64db582 1053 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
lynxeyed_atsu 0:d920d64db582 1054 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
lynxeyed_atsu 0:d920d64db582 1055 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
lynxeyed_atsu 0:d920d64db582 1056 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
lynxeyed_atsu 0:d920d64db582 1057 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
lynxeyed_atsu 0:d920d64db582 1058 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
lynxeyed_atsu 0:d920d64db582 1059 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
lynxeyed_atsu 0:d920d64db582 1060 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
lynxeyed_atsu 0:d920d64db582 1061 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
lynxeyed_atsu 0:d920d64db582 1062 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
lynxeyed_atsu 0:d920d64db582 1063 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
lynxeyed_atsu 0:d920d64db582 1064 #define DMAREQSEL (*(__IO uint32_t *) ( 0x4000C1C4))
lynxeyed_atsu 0:d920d64db582 1065 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
lynxeyed_atsu 0:d920d64db582 1066 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
lynxeyed_atsu 0:d920d64db582 1067 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
lynxeyed_atsu 0:d920d64db582 1068 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
lynxeyed_atsu 0:d920d64db582 1069 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
lynxeyed_atsu 0:d920d64db582 1070 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
lynxeyed_atsu 0:d920d64db582 1071 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
lynxeyed_atsu 0:d920d64db582 1072 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
lynxeyed_atsu 0:d920d64db582 1073 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
lynxeyed_atsu 0:d920d64db582 1074
lynxeyed_atsu 0:d920d64db582 1075 /**
lynxeyed_atsu 0:d920d64db582 1076 * @}
lynxeyed_atsu 0:d920d64db582 1077 */
lynxeyed_atsu 0:d920d64db582 1078
lynxeyed_atsu 0:d920d64db582 1079 #endif // __LPC17xx_H__