xeye_ atsu / Mbed 2 deprecated I2S_AIC23B_RiceGolomb

パラメータを適応変化させる事により圧縮率を向上させた動的ライス・ゴロム符号を利用した可逆圧縮方式。圧縮ソフト、圧縮率のMATLABシミュレーションは詳細はInterface誌2011年8月号に掲載されるRX62Nマイコン連動特集にて掲載予定。

Dependencies:   mbed

I2S_Example/lpc17xx_clkpwr.h@0:d920d64db582, 2011-03-30 (annotated)

Committer:
lynxeyed_atsu
Date:
Wed Mar 30 06:05:24 2011 +0000
Revision:
0:d920d64db582
alpha

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lynxeyed_atsu 0:d920d64db582 1 /***********************************************************************//**
lynxeyed_atsu 0:d920d64db582 2 * @file lpc17xx_clkpwr.h
lynxeyed_atsu 0:d920d64db582 3 * @brief Contains all macro definitions and function prototypes
lynxeyed_atsu 0:d920d64db582 4 * support for Clock and Power Control firmware library on LPC17xx
lynxeyed_atsu 0:d920d64db582 5 * @version 2.0
lynxeyed_atsu 0:d920d64db582 6 * @date 21. May. 2010
lynxeyed_atsu 0:d920d64db582 7 * @author NXP MCU SW Application Team
lynxeyed_atsu 0:d920d64db582 8 **************************************************************************
lynxeyed_atsu 0:d920d64db582 9 * Software that is described herein is for illustrative purposes only
lynxeyed_atsu 0:d920d64db582 10 * which provides customers with programming information regarding the
lynxeyed_atsu 0:d920d64db582 11 * products. This software is supplied "AS IS" without any warranties.
lynxeyed_atsu 0:d920d64db582 12 * NXP Semiconductors assumes no responsibility or liability for the
lynxeyed_atsu 0:d920d64db582 13 * use of the software, conveys no license or title under any patent,
lynxeyed_atsu 0:d920d64db582 14 * copyright, or mask work right to the product. NXP Semiconductors
lynxeyed_atsu 0:d920d64db582 15 * reserves the right to make changes in the software without
lynxeyed_atsu 0:d920d64db582 16 * notification. NXP Semiconductors also make no representation or
lynxeyed_atsu 0:d920d64db582 17 * warranty that such application will be suitable for the specified
lynxeyed_atsu 0:d920d64db582 18 * use without further testing or modification.
lynxeyed_atsu 0:d920d64db582 19 **************************************************************************/
lynxeyed_atsu 0:d920d64db582 20
lynxeyed_atsu 0:d920d64db582 21 /* Peripheral group ----------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 22 /** @defgroup CLKPWR CLKPWR
lynxeyed_atsu 0:d920d64db582 23 * @ingroup LPC1700CMSIS_FwLib_Drivers
lynxeyed_atsu 0:d920d64db582 24 * @{
lynxeyed_atsu 0:d920d64db582 25 */
lynxeyed_atsu 0:d920d64db582 26
lynxeyed_atsu 0:d920d64db582 27 #ifndef LPC17XX_CLKPWR_H_
lynxeyed_atsu 0:d920d64db582 28 #define LPC17XX_CLKPWR_H_
lynxeyed_atsu 0:d920d64db582 29
lynxeyed_atsu 0:d920d64db582 30 /* Includes ------------------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 31 #include "LPC17xx.h"
lynxeyed_atsu 0:d920d64db582 32 #include "lpc_types.h"
lynxeyed_atsu 0:d920d64db582 33
lynxeyed_atsu 0:d920d64db582 34 #ifdef __cplusplus
lynxeyed_atsu 0:d920d64db582 35 extern "C"
lynxeyed_atsu 0:d920d64db582 36 {
lynxeyed_atsu 0:d920d64db582 37 #endif
lynxeyed_atsu 0:d920d64db582 38
lynxeyed_atsu 0:d920d64db582 39 /* Public Macros -------------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 40 /** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
lynxeyed_atsu 0:d920d64db582 41 * @{
lynxeyed_atsu 0:d920d64db582 42 */
lynxeyed_atsu 0:d920d64db582 43
lynxeyed_atsu 0:d920d64db582 44 /**********************************************************************
lynxeyed_atsu 0:d920d64db582 45 * Peripheral Clock Selection Definitions
lynxeyed_atsu 0:d920d64db582 46 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 47 /** Peripheral clock divider bit position for WDT */
lynxeyed_atsu 0:d920d64db582 48 #define CLKPWR_PCLKSEL_WDT ((uint32_t)(0))
lynxeyed_atsu 0:d920d64db582 49 /** Peripheral clock divider bit position for TIMER0 */
lynxeyed_atsu 0:d920d64db582 50 #define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2))
lynxeyed_atsu 0:d920d64db582 51 /** Peripheral clock divider bit position for TIMER1 */
lynxeyed_atsu 0:d920d64db582 52 #define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4))
lynxeyed_atsu 0:d920d64db582 53 /** Peripheral clock divider bit position for UART0 */
lynxeyed_atsu 0:d920d64db582 54 #define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6))
lynxeyed_atsu 0:d920d64db582 55 /** Peripheral clock divider bit position for UART1 */
lynxeyed_atsu 0:d920d64db582 56 #define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8))
lynxeyed_atsu 0:d920d64db582 57 /** Peripheral clock divider bit position for PWM1 */
lynxeyed_atsu 0:d920d64db582 58 #define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12))
lynxeyed_atsu 0:d920d64db582 59 /** Peripheral clock divider bit position for I2C0 */
lynxeyed_atsu 0:d920d64db582 60 #define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14))
lynxeyed_atsu 0:d920d64db582 61 /** Peripheral clock divider bit position for SPI */
lynxeyed_atsu 0:d920d64db582 62 #define CLKPWR_PCLKSEL_SPI ((uint32_t)(16))
lynxeyed_atsu 0:d920d64db582 63 /** Peripheral clock divider bit position for SSP1 */
lynxeyed_atsu 0:d920d64db582 64 #define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20))
lynxeyed_atsu 0:d920d64db582 65 /** Peripheral clock divider bit position for DAC */
lynxeyed_atsu 0:d920d64db582 66 #define CLKPWR_PCLKSEL_DAC ((uint32_t)(22))
lynxeyed_atsu 0:d920d64db582 67 /** Peripheral clock divider bit position for ADC */
lynxeyed_atsu 0:d920d64db582 68 #define CLKPWR_PCLKSEL_ADC ((uint32_t)(24))
lynxeyed_atsu 0:d920d64db582 69 /** Peripheral clock divider bit position for CAN1 */
lynxeyed_atsu 0:d920d64db582 70 #define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26))
lynxeyed_atsu 0:d920d64db582 71 /** Peripheral clock divider bit position for CAN2 */
lynxeyed_atsu 0:d920d64db582 72 #define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28))
lynxeyed_atsu 0:d920d64db582 73 /** Peripheral clock divider bit position for ACF */
lynxeyed_atsu 0:d920d64db582 74 #define CLKPWR_PCLKSEL_ACF ((uint32_t)(30))
lynxeyed_atsu 0:d920d64db582 75 /** Peripheral clock divider bit position for QEI */
lynxeyed_atsu 0:d920d64db582 76 #define CLKPWR_PCLKSEL_QEI ((uint32_t)(32))
lynxeyed_atsu 0:d920d64db582 77 /** Peripheral clock divider bit position for PCB */
lynxeyed_atsu 0:d920d64db582 78 #define CLKPWR_PCLKSEL_PCB ((uint32_t)(36))
lynxeyed_atsu 0:d920d64db582 79 /** Peripheral clock divider bit position for I2C1 */
lynxeyed_atsu 0:d920d64db582 80 #define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38))
lynxeyed_atsu 0:d920d64db582 81 /** Peripheral clock divider bit position for SSP0 */
lynxeyed_atsu 0:d920d64db582 82 #define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42))
lynxeyed_atsu 0:d920d64db582 83 /** Peripheral clock divider bit position for TIMER2 */
lynxeyed_atsu 0:d920d64db582 84 #define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44))
lynxeyed_atsu 0:d920d64db582 85 /** Peripheral clock divider bit position for TIMER3 */
lynxeyed_atsu 0:d920d64db582 86 #define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46))
lynxeyed_atsu 0:d920d64db582 87 /** Peripheral clock divider bit position for UART2 */
lynxeyed_atsu 0:d920d64db582 88 #define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48))
lynxeyed_atsu 0:d920d64db582 89 /** Peripheral clock divider bit position for UART3 */
lynxeyed_atsu 0:d920d64db582 90 #define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50))
lynxeyed_atsu 0:d920d64db582 91 /** Peripheral clock divider bit position for I2C2 */
lynxeyed_atsu 0:d920d64db582 92 #define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52))
lynxeyed_atsu 0:d920d64db582 93 /** Peripheral clock divider bit position for I2S */
lynxeyed_atsu 0:d920d64db582 94 #define CLKPWR_PCLKSEL_I2S ((uint32_t)(54))
lynxeyed_atsu 0:d920d64db582 95 /** Peripheral clock divider bit position for RIT */
lynxeyed_atsu 0:d920d64db582 96 #define CLKPWR_PCLKSEL_RIT ((uint32_t)(58))
lynxeyed_atsu 0:d920d64db582 97 /** Peripheral clock divider bit position for SYSCON */
lynxeyed_atsu 0:d920d64db582 98 #define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60))
lynxeyed_atsu 0:d920d64db582 99 /** Peripheral clock divider bit position for MC */
lynxeyed_atsu 0:d920d64db582 100 #define CLKPWR_PCLKSEL_MC ((uint32_t)(62))
lynxeyed_atsu 0:d920d64db582 101
lynxeyed_atsu 0:d920d64db582 102 /** Macro for Peripheral Clock Selection register bit values
lynxeyed_atsu 0:d920d64db582 103 * Note: When CCLK_DIV_8, Peripheral�s clock is selected to
lynxeyed_atsu 0:d920d64db582 104 * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
lynxeyed_atsu 0:d920d64db582 105 * when �11�selects PCLK_xyz = CCLK/6 */
lynxeyed_atsu 0:d920d64db582 106 /* Peripheral clock divider is set to 4 from CCLK */
lynxeyed_atsu 0:d920d64db582 107 #define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0))
lynxeyed_atsu 0:d920d64db582 108 /** Peripheral clock divider is the same with CCLK */
lynxeyed_atsu 0:d920d64db582 109 #define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1))
lynxeyed_atsu 0:d920d64db582 110 /** Peripheral clock divider is set to 2 from CCLK */
lynxeyed_atsu 0:d920d64db582 111 #define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2))
lynxeyed_atsu 0:d920d64db582 112
lynxeyed_atsu 0:d920d64db582 113
lynxeyed_atsu 0:d920d64db582 114 /********************************************************************
lynxeyed_atsu 0:d920d64db582 115 * Power Control for Peripherals Definitions
lynxeyed_atsu 0:d920d64db582 116 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 117 /** Timer/Counter 0 power/clock control bit */
lynxeyed_atsu 0:d920d64db582 118 #define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
lynxeyed_atsu 0:d920d64db582 119 /* Timer/Counter 1 power/clock control bit */
lynxeyed_atsu 0:d920d64db582 120 #define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
lynxeyed_atsu 0:d920d64db582 121 /** UART0 power/clock control bit */
lynxeyed_atsu 0:d920d64db582 122 #define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
lynxeyed_atsu 0:d920d64db582 123 /** UART1 power/clock control bit */
lynxeyed_atsu 0:d920d64db582 124 #define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
lynxeyed_atsu 0:d920d64db582 125 /** PWM1 power/clock control bit */
lynxeyed_atsu 0:d920d64db582 126 #define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
lynxeyed_atsu 0:d920d64db582 127 /** The I2C0 interface power/clock control bit */
lynxeyed_atsu 0:d920d64db582 128 #define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
lynxeyed_atsu 0:d920d64db582 129 /** The SPI interface power/clock control bit */
lynxeyed_atsu 0:d920d64db582 130 #define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8))
lynxeyed_atsu 0:d920d64db582 131 /** The RTC power/clock control bit */
lynxeyed_atsu 0:d920d64db582 132 #define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
lynxeyed_atsu 0:d920d64db582 133 /** The SSP1 interface power/clock control bit */
lynxeyed_atsu 0:d920d64db582 134 #define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
lynxeyed_atsu 0:d920d64db582 135 /** A/D converter 0 (ADC0) power/clock control bit */
lynxeyed_atsu 0:d920d64db582 136 #define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12))
lynxeyed_atsu 0:d920d64db582 137 /** CAN Controller 1 power/clock control bit */
lynxeyed_atsu 0:d920d64db582 138 #define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
lynxeyed_atsu 0:d920d64db582 139 /** CAN Controller 2 power/clock control bit */
lynxeyed_atsu 0:d920d64db582 140 #define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
lynxeyed_atsu 0:d920d64db582 141 /** GPIO power/clock control bit */
lynxeyed_atsu 0:d920d64db582 142 #define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
lynxeyed_atsu 0:d920d64db582 143 /** Repetitive Interrupt Timer power/clock control bit */
lynxeyed_atsu 0:d920d64db582 144 #define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16))
lynxeyed_atsu 0:d920d64db582 145 /** Motor Control PWM */
lynxeyed_atsu 0:d920d64db582 146 #define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17))
lynxeyed_atsu 0:d920d64db582 147 /** Quadrature Encoder Interface power/clock control bit */
lynxeyed_atsu 0:d920d64db582 148 #define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
lynxeyed_atsu 0:d920d64db582 149 /** The I2C1 interface power/clock control bit */
lynxeyed_atsu 0:d920d64db582 150 #define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
lynxeyed_atsu 0:d920d64db582 151 /** The SSP0 interface power/clock control bit */
lynxeyed_atsu 0:d920d64db582 152 #define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
lynxeyed_atsu 0:d920d64db582 153 /** Timer 2 power/clock control bit */
lynxeyed_atsu 0:d920d64db582 154 #define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
lynxeyed_atsu 0:d920d64db582 155 /** Timer 3 power/clock control bit */
lynxeyed_atsu 0:d920d64db582 156 #define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
lynxeyed_atsu 0:d920d64db582 157 /** UART 2 power/clock control bit */
lynxeyed_atsu 0:d920d64db582 158 #define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
lynxeyed_atsu 0:d920d64db582 159 /** UART 3 power/clock control bit */
lynxeyed_atsu 0:d920d64db582 160 #define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
lynxeyed_atsu 0:d920d64db582 161 /** I2C interface 2 power/clock control bit */
lynxeyed_atsu 0:d920d64db582 162 #define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
lynxeyed_atsu 0:d920d64db582 163 /** I2S interface power/clock control bit*/
lynxeyed_atsu 0:d920d64db582 164 #define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
lynxeyed_atsu 0:d920d64db582 165 /** GP DMA function power/clock control bit*/
lynxeyed_atsu 0:d920d64db582 166 #define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
lynxeyed_atsu 0:d920d64db582 167 /** Ethernet block power/clock control bit*/
lynxeyed_atsu 0:d920d64db582 168 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
lynxeyed_atsu 0:d920d64db582 169 /** USB interface power/clock control bit*/
lynxeyed_atsu 0:d920d64db582 170 #define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
lynxeyed_atsu 0:d920d64db582 171
lynxeyed_atsu 0:d920d64db582 172
lynxeyed_atsu 0:d920d64db582 173 /**
lynxeyed_atsu 0:d920d64db582 174 * @}
lynxeyed_atsu 0:d920d64db582 175 */
lynxeyed_atsu 0:d920d64db582 176 /* Private Macros ------------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 177 /** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros
lynxeyed_atsu 0:d920d64db582 178 * @{
lynxeyed_atsu 0:d920d64db582 179 */
lynxeyed_atsu 0:d920d64db582 180
lynxeyed_atsu 0:d920d64db582 181 /* --------------------- BIT DEFINITIONS -------------------------------------- */
lynxeyed_atsu 0:d920d64db582 182 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 183 * Macro defines for Clock Source Select Register
lynxeyed_atsu 0:d920d64db582 184 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 185 /** Internal RC oscillator */
lynxeyed_atsu 0:d920d64db582 186 #define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00))
lynxeyed_atsu 0:d920d64db582 187 /** Main oscillator */
lynxeyed_atsu 0:d920d64db582 188 #define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01))
lynxeyed_atsu 0:d920d64db582 189 /** RTC oscillator */
lynxeyed_atsu 0:d920d64db582 190 #define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02))
lynxeyed_atsu 0:d920d64db582 191 /** Clock source selection bit mask */
lynxeyed_atsu 0:d920d64db582 192 #define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03))
lynxeyed_atsu 0:d920d64db582 193
lynxeyed_atsu 0:d920d64db582 194 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 195 * Macro defines for Clock Output Configuration Register
lynxeyed_atsu 0:d920d64db582 196 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 197 /* Clock Output Configuration register definition */
lynxeyed_atsu 0:d920d64db582 198 /** Selects the CPU clock as the CLKOUT source */
lynxeyed_atsu 0:d920d64db582 199 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00))
lynxeyed_atsu 0:d920d64db582 200 /** Selects the main oscillator as the CLKOUT source */
lynxeyed_atsu 0:d920d64db582 201 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01))
lynxeyed_atsu 0:d920d64db582 202 /** Selects the Internal RC oscillator as the CLKOUT source */
lynxeyed_atsu 0:d920d64db582 203 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02))
lynxeyed_atsu 0:d920d64db582 204 /** Selects the USB clock as the CLKOUT source */
lynxeyed_atsu 0:d920d64db582 205 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03))
lynxeyed_atsu 0:d920d64db582 206 /** Selects the RTC oscillator as the CLKOUT source */
lynxeyed_atsu 0:d920d64db582 207 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04))
lynxeyed_atsu 0:d920d64db582 208 /** Integer value to divide the output clock by, minus one */
lynxeyed_atsu 0:d920d64db582 209 #define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4))
lynxeyed_atsu 0:d920d64db582 210 /** CLKOUT enable control */
lynxeyed_atsu 0:d920d64db582 211 #define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8))
lynxeyed_atsu 0:d920d64db582 212 /** CLKOUT activity indication */
lynxeyed_atsu 0:d920d64db582 213 #define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9))
lynxeyed_atsu 0:d920d64db582 214 /** Clock source selection bit mask */
lynxeyed_atsu 0:d920d64db582 215 #define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF))
lynxeyed_atsu 0:d920d64db582 216
lynxeyed_atsu 0:d920d64db582 217 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 218 * Macro defines for PPL0 Control Register
lynxeyed_atsu 0:d920d64db582 219 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 220 /** PLL 0 control enable */
lynxeyed_atsu 0:d920d64db582 221 #define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01))
lynxeyed_atsu 0:d920d64db582 222 /** PLL 0 control connect */
lynxeyed_atsu 0:d920d64db582 223 #define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02))
lynxeyed_atsu 0:d920d64db582 224 /** PLL 0 control bit mask */
lynxeyed_atsu 0:d920d64db582 225 #define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03))
lynxeyed_atsu 0:d920d64db582 226
lynxeyed_atsu 0:d920d64db582 227 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 228 * Macro defines for PPL0 Configuration Register
lynxeyed_atsu 0:d920d64db582 229 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 230 /** PLL 0 Configuration MSEL field */
lynxeyed_atsu 0:d920d64db582 231 #define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF))
lynxeyed_atsu 0:d920d64db582 232 /** PLL 0 Configuration NSEL field */
lynxeyed_atsu 0:d920d64db582 233 #define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000))
lynxeyed_atsu 0:d920d64db582 234 /** PLL 0 Configuration bit mask */
lynxeyed_atsu 0:d920d64db582 235 #define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF))
lynxeyed_atsu 0:d920d64db582 236
lynxeyed_atsu 0:d920d64db582 237
lynxeyed_atsu 0:d920d64db582 238 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 239 * Macro defines for PPL0 Status Register
lynxeyed_atsu 0:d920d64db582 240 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 241 /** PLL 0 MSEL value */
lynxeyed_atsu 0:d920d64db582 242 #define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF))
lynxeyed_atsu 0:d920d64db582 243 /** PLL NSEL get value */
lynxeyed_atsu 0:d920d64db582 244 #define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF))
lynxeyed_atsu 0:d920d64db582 245 /** PLL status enable bit */
lynxeyed_atsu 0:d920d64db582 246 #define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24))
lynxeyed_atsu 0:d920d64db582 247 /** PLL status Connect bit */
lynxeyed_atsu 0:d920d64db582 248 #define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25))
lynxeyed_atsu 0:d920d64db582 249 /** PLL status lock */
lynxeyed_atsu 0:d920d64db582 250 #define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26))
lynxeyed_atsu 0:d920d64db582 251
lynxeyed_atsu 0:d920d64db582 252 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 253 * Macro defines for PPL0 Feed Register
lynxeyed_atsu 0:d920d64db582 254 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 255 /** PLL0 Feed bit mask */
lynxeyed_atsu 0:d920d64db582 256 #define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF)
lynxeyed_atsu 0:d920d64db582 257
lynxeyed_atsu 0:d920d64db582 258 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 259 * Macro defines for PLL1 Control Register
lynxeyed_atsu 0:d920d64db582 260 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 261 /** USB PLL control enable */
lynxeyed_atsu 0:d920d64db582 262 #define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01))
lynxeyed_atsu 0:d920d64db582 263 /** USB PLL control connect */
lynxeyed_atsu 0:d920d64db582 264 #define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02))
lynxeyed_atsu 0:d920d64db582 265 /** USB PLL control bit mask */
lynxeyed_atsu 0:d920d64db582 266 #define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03))
lynxeyed_atsu 0:d920d64db582 267
lynxeyed_atsu 0:d920d64db582 268 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 269 * Macro defines for PLL1 Configuration Register
lynxeyed_atsu 0:d920d64db582 270 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 271 /** USB PLL MSEL set value */
lynxeyed_atsu 0:d920d64db582 272 #define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F))
lynxeyed_atsu 0:d920d64db582 273 /** USB PLL PSEL set value */
lynxeyed_atsu 0:d920d64db582 274 #define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5))
lynxeyed_atsu 0:d920d64db582 275 /** USB PLL configuration bit mask */
lynxeyed_atsu 0:d920d64db582 276 #define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F))
lynxeyed_atsu 0:d920d64db582 277
lynxeyed_atsu 0:d920d64db582 278 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 279 * Macro defines for PLL1 Status Register
lynxeyed_atsu 0:d920d64db582 280 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 281 /** USB PLL MSEL get value */
lynxeyed_atsu 0:d920d64db582 282 #define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F))
lynxeyed_atsu 0:d920d64db582 283 /** USB PLL PSEL get value */
lynxeyed_atsu 0:d920d64db582 284 #define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03))
lynxeyed_atsu 0:d920d64db582 285 /** USB PLL status enable bit */
lynxeyed_atsu 0:d920d64db582 286 #define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8))
lynxeyed_atsu 0:d920d64db582 287 /** USB PLL status Connect bit */
lynxeyed_atsu 0:d920d64db582 288 #define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9))
lynxeyed_atsu 0:d920d64db582 289 /** USB PLL status lock */
lynxeyed_atsu 0:d920d64db582 290 #define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10))
lynxeyed_atsu 0:d920d64db582 291
lynxeyed_atsu 0:d920d64db582 292 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 293 * Macro defines for PLL1 Feed Register
lynxeyed_atsu 0:d920d64db582 294 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 295 /** PLL1 Feed bit mask */
lynxeyed_atsu 0:d920d64db582 296 #define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF)
lynxeyed_atsu 0:d920d64db582 297
lynxeyed_atsu 0:d920d64db582 298 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 299 * Macro defines for CPU Clock Configuration Register
lynxeyed_atsu 0:d920d64db582 300 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 301 /** CPU Clock configuration bit mask */
lynxeyed_atsu 0:d920d64db582 302 #define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF))
lynxeyed_atsu 0:d920d64db582 303
lynxeyed_atsu 0:d920d64db582 304 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 305 * Macro defines for USB Clock Configuration Register
lynxeyed_atsu 0:d920d64db582 306 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 307 /** USB Clock Configuration bit mask */
lynxeyed_atsu 0:d920d64db582 308 #define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F))
lynxeyed_atsu 0:d920d64db582 309
lynxeyed_atsu 0:d920d64db582 310 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 311 * Macro defines for IRC Trim Register
lynxeyed_atsu 0:d920d64db582 312 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 313 /** IRC Trim bit mask */
lynxeyed_atsu 0:d920d64db582 314 #define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F))
lynxeyed_atsu 0:d920d64db582 315
lynxeyed_atsu 0:d920d64db582 316 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 317 * Macro defines for Peripheral Clock Selection Register 0 and 1
lynxeyed_atsu 0:d920d64db582 318 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 319 /** Peripheral Clock Selection 0 mask bit */
lynxeyed_atsu 0:d920d64db582 320 #define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF))
lynxeyed_atsu 0:d920d64db582 321 /** Peripheral Clock Selection 1 mask bit */
lynxeyed_atsu 0:d920d64db582 322 #define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3))
lynxeyed_atsu 0:d920d64db582 323 /** Macro to set peripheral clock of each type
lynxeyed_atsu 0:d920d64db582 324 * p: position of two bits that hold divider of peripheral clock
lynxeyed_atsu 0:d920d64db582 325 * n: value of divider of peripheral clock to be set */
lynxeyed_atsu 0:d920d64db582 326 #define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n)
lynxeyed_atsu 0:d920d64db582 327 /** Macro to mask peripheral clock of each type */
lynxeyed_atsu 0:d920d64db582 328 #define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03)
lynxeyed_atsu 0:d920d64db582 329 /** Macro to get peripheral clock of each type */
lynxeyed_atsu 0:d920d64db582 330 #define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03))
lynxeyed_atsu 0:d920d64db582 331
lynxeyed_atsu 0:d920d64db582 332 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 333 * Macro defines for Power Mode Control Register
lynxeyed_atsu 0:d920d64db582 334 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 335 /** Power mode control bit 0 */
lynxeyed_atsu 0:d920d64db582 336 #define CLKPWR_PCON_PM0 ((uint32_t)(1<<0))
lynxeyed_atsu 0:d920d64db582 337 /** Power mode control bit 1 */
lynxeyed_atsu 0:d920d64db582 338 #define CLKPWR_PCON_PM1 ((uint32_t)(1<<1))
lynxeyed_atsu 0:d920d64db582 339 /** Brown-Out Reduced Power Mode */
lynxeyed_atsu 0:d920d64db582 340 #define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2))
lynxeyed_atsu 0:d920d64db582 341 /** Brown-Out Global Disable */
lynxeyed_atsu 0:d920d64db582 342 #define CLKPWR_PCON_BOGD ((uint32_t)(1<<3))
lynxeyed_atsu 0:d920d64db582 343 /** Brown Out Reset Disable */
lynxeyed_atsu 0:d920d64db582 344 #define CLKPWR_PCON_BORD ((uint32_t)(1<<4))
lynxeyed_atsu 0:d920d64db582 345 /** Sleep Mode entry flag */
lynxeyed_atsu 0:d920d64db582 346 #define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8))
lynxeyed_atsu 0:d920d64db582 347 /** Deep Sleep entry flag */
lynxeyed_atsu 0:d920d64db582 348 #define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9))
lynxeyed_atsu 0:d920d64db582 349 /** Power-down entry flag */
lynxeyed_atsu 0:d920d64db582 350 #define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10))
lynxeyed_atsu 0:d920d64db582 351 /** Deep Power-down entry flag */
lynxeyed_atsu 0:d920d64db582 352 #define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11))
lynxeyed_atsu 0:d920d64db582 353
lynxeyed_atsu 0:d920d64db582 354 /*********************************************************************//**
lynxeyed_atsu 0:d920d64db582 355 * Macro defines for Power Control for Peripheral Register
lynxeyed_atsu 0:d920d64db582 356 **********************************************************************/
lynxeyed_atsu 0:d920d64db582 357 /** Power Control for Peripherals bit mask */
lynxeyed_atsu 0:d920d64db582 358 #define CLKPWR_PCONP_BITMASK 0xEFEFF7DE
lynxeyed_atsu 0:d920d64db582 359
lynxeyed_atsu 0:d920d64db582 360 /**
lynxeyed_atsu 0:d920d64db582 361 * @}
lynxeyed_atsu 0:d920d64db582 362 */
lynxeyed_atsu 0:d920d64db582 363
lynxeyed_atsu 0:d920d64db582 364
lynxeyed_atsu 0:d920d64db582 365 /* Public Functions ----------------------------------------------------------- */
lynxeyed_atsu 0:d920d64db582 366 /** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
lynxeyed_atsu 0:d920d64db582 367 * @{
lynxeyed_atsu 0:d920d64db582 368 */
lynxeyed_atsu 0:d920d64db582 369
lynxeyed_atsu 0:d920d64db582 370 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
lynxeyed_atsu 0:d920d64db582 371 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
lynxeyed_atsu 0:d920d64db582 372 uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
lynxeyed_atsu 0:d920d64db582 373 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
lynxeyed_atsu 0:d920d64db582 374 void CLKPWR_Sleep(void);
lynxeyed_atsu 0:d920d64db582 375 void CLKPWR_DeepSleep(void);
lynxeyed_atsu 0:d920d64db582 376 void CLKPWR_PowerDown(void);
lynxeyed_atsu 0:d920d64db582 377 void CLKPWR_DeepPowerDown(void);
lynxeyed_atsu 0:d920d64db582 378
lynxeyed_atsu 0:d920d64db582 379 /**
lynxeyed_atsu 0:d920d64db582 380 * @}
lynxeyed_atsu 0:d920d64db582 381 */
lynxeyed_atsu 0:d920d64db582 382
lynxeyed_atsu 0:d920d64db582 383
lynxeyed_atsu 0:d920d64db582 384 #ifdef __cplusplus
lynxeyed_atsu 0:d920d64db582 385 }
lynxeyed_atsu 0:d920d64db582 386 #endif
lynxeyed_atsu 0:d920d64db582 387
lynxeyed_atsu 0:d920d64db582 388 #endif /* LPC17XX_CLKPWR_H_ */
lynxeyed_atsu 0:d920d64db582 389
lynxeyed_atsu 0:d920d64db582 390 /**
lynxeyed_atsu 0:d920d64db582 391 * @}
lynxeyed_atsu 0:d920d64db582 392 */
lynxeyed_atsu 0:d920d64db582 393
lynxeyed_atsu 0:d920d64db582 394 /* --------------------------------- End Of File ------------------------------ */