Freescale_Cachan
/
Programme_course_30Tr
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Fork of
Programme_course_vir_am_2
by 
Freescale_Cachan
Embed:
(wiki syntax)
Show/hide line numbers
MKL25Z4.h
Go to the documentation of this file.
00001 /* 00002 ** ################################################################### 00003 ** Processors: MKL25Z128FM4 00004 ** MKL25Z128FT4 00005 ** MKL25Z128LH4 00006 ** MKL25Z128VLK4 00007 ** 00008 ** Compilers: ARM Compiler 00009 ** Freescale C/C++ for Embedded ARM 00010 ** GNU C Compiler 00011 ** IAR ANSI C/C++ Compiler for ARM 00012 ** 00013 ** Reference manual: KL25P80M48SF0RM, Rev.3, Sep 2012 00014 ** Version: rev. 1.6, 2013-04-05 00015 ** 00016 ** Abstract: 00017 ** This header file implements peripheral memory map for MKL25Z4 00018 ** processor. 00019 ** 00020 ** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved. 00021 ** 00022 ** http: www.freescale.com 00023 ** mail: support@freescale.com 00024 ** 00025 ** Revisions: 00026 ** - rev. 1.0 (2012-05-17) 00027 ** Initial version. 00028 ** - rev. 1.1 (2012-06-08) 00029 ** Update according to reference manual rev. 0, draft B. 00030 ** - rev. 1.2 (2012-06-21) 00031 ** Update according to reference manual rev. 1. 00032 ** - rev. 1.3 (2012-08-01) 00033 ** Device type UARTLP changed to UART0. 00034 ** - rev. 1.4 (2012-10-04) 00035 ** Update according to reference manual rev. 3. 00036 ** - rev. 1.5 (2012-11-22) 00037 ** MCG module - bit LOLS in MCG_S register renamed to LOLS0. 00038 ** NV registers - bit EZPORT_DIS in NV_FOPT register removed. 00039 ** - rev. 1.6 (2013-04-05) 00040 ** Changed start of doxygen comment. 00041 ** 00042 ** ################################################################### 00043 */ 00044 00045 /*! 00046 * @file MKL25Z4.h 00047 * @version 1.6 00048 * @date 2013-04-05 00049 * @brief Peripheral memory map for MKL25Z4 00050 * 00051 * This header file implements peripheral memory map for MKL25Z4 processor. 00052 */ 00053 00054 00055 /* ---------------------------------------------------------------------------- 00056 -- MCU activation 00057 ---------------------------------------------------------------------------- */ 00058 00059 /* Prevention from multiple including the same memory map */ 00060 #if !defined(MCU_MKL25Z4) /* Check if memory map has not been already included */ 00061 #define MCU_MKL25Z4 00062 00063 /* Check if another memory map has not been also included */ 00064 #if (defined(MCU_ACTIVE)) 00065 #error MKL25Z4 memory map: There is already included another memory map. Only one memory map can be included. 00066 #endif /* (defined(MCU_ACTIVE)) */ 00067 #define MCU_ACTIVE 00068 00069 #include <stdint.h> 00070 00071 /** Memory map major version (memory maps with equal major version number are 00072 * compatible) */ 00073 #define MCU_MEM_MAP_VERSION 0x0100u 00074 /** Memory map minor version */ 00075 //#define MCU_MEM_MAP_VERSION_MINOR 0x0006u 00076 00077 00078 /* ---------------------------------------------------------------------------- 00079 -- Interrupt vector numbers 00080 ---------------------------------------------------------------------------- */ 00081 00082 /*! 00083 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 00084 * @{ 00085 */ 00086 00087 /** Interrupt Number Definitions */ 00088 typedef enum { 00089 INT_Initial_Stack_Pointer = 0, /**< Initial stack pointer */ 00090 INT_Initial_Program_Counter = 1, /**< Initial program counter */ 00091 INT_NMI = 2, /**< Non-maskable interrupt */ 00092 INT_Hard_Fault = 3, /**< Hard fault exception */ 00093 INT_Reserved4 = 4, /**< Reserved interrupt 4 */ 00094 INT_Reserved5 = 5, /**< Reserved interrupt 5 */ 00095 INT_Reserved6 = 6, /**< Reserved interrupt 6 */ 00096 INT_Reserved7 = 7, /**< Reserved interrupt 7 */ 00097 INT_Reserved8 = 8, /**< Reserved interrupt 8 */ 00098 INT_Reserved9 = 9, /**< Reserved interrupt 9 */ 00099 INT_Reserved10 = 10, /**< Reserved interrupt 10 */ 00100 INT_SVCall = 11, /**< A supervisor call exception */ 00101 INT_Reserved12 = 12, /**< Reserved interrupt 12 */ 00102 INT_Reserved13 = 13, /**< Reserved interrupt 13 */ 00103 INT_PendableSrvReq = 14, /**< PendSV exception - request for system level service */ 00104 INT_SysTick = 15, /**< SysTick interrupt */ 00105 INT_DMA0 = 16, /**< DMA channel 0 transfer complete/error interrupt */ 00106 INT_DMA1 = 17, /**< DMA channel 1 transfer complete/error interrupt */ 00107 INT_DMA2 = 18, /**< DMA channel 2 transfer complete/error interrupt */ 00108 INT_DMA3 = 19, /**< DMA channel 3 transfer complete/error interrupt */ 00109 INT_Reserved20 = 20, /**< Reserved interrupt 20 */ 00110 INT_FTFA = 21, /**< FTFA command complete/read collision interrupt */ 00111 INT_LVD_LVW = 22, /**< Low Voltage Detect, Low Voltage Warning */ 00112 INT_LLW = 23, /**< Low Leakage Wakeup */ 00113 INT_I2C0 = 24, /**< I2C0 interrupt */ 00114 INT_I2C1 = 25, /**< I2C0 interrupt 25 */ 00115 INT_SPI0 = 26, /**< SPI0 interrupt */ 00116 INT_SPI1 = 27, /**< SPI1 interrupt */ 00117 INT_UART0 = 28, /**< UART0 status/error interrupt */ 00118 INT_UART1 = 29, /**< UART1 status/error interrupt */ 00119 INT_UART2 = 30, /**< UART2 status/error interrupt */ 00120 INT_ADC0 = 31, /**< ADC0 interrupt */ 00121 INT_CMP0 = 32, /**< CMP0 interrupt */ 00122 INT_TPM0 = 33, /**< TPM0 fault, overflow and channels interrupt */ 00123 INT_TPM1 = 34, /**< TPM1 fault, overflow and channels interrupt */ 00124 INT_TPM2 = 35, /**< TPM2 fault, overflow and channels interrupt */ 00125 INT_RTC = 36, /**< RTC interrupt */ 00126 INT_RTC_Seconds = 37, /**< RTC seconds interrupt */ 00127 INT_PIT = 38, /**< PIT timer interrupt */ 00128 INT_Reserved39 = 39, /**< Reserved interrupt 39 */ 00129 INT_USB0 = 40, /**< USB0 interrupt */ 00130 INT_DAC0 = 41, /**< DAC0 interrupt */ 00131 INT_TSI0 = 42, /**< TSI0 interrupt */ 00132 INT_MCG = 43, /**< MCG interrupt */ 00133 INT_LPTimer = 44, /**< LPTimer interrupt */ 00134 INT_Reserved45 = 45, /**< Reserved interrupt 45 */ 00135 INT_PORTA = 46, /**< Port A interrupt */ 00136 INT_PORTD = 47 /**< Port D interrupt */ 00137 } IRQInterruptIndex; 00138 00139 /*! 00140 * @} 00141 */ /* end of group Interrupt_vector_numbers */ 00142 00143 00144 /* ---------------------------------------------------------------------------- 00145 -- Peripheral type defines 00146 ---------------------------------------------------------------------------- */ 00147 00148 /*! 00149 * @addtogroup Peripheral_defines Peripheral type defines 00150 * @{ 00151 */ 00152 00153 00154 /* 00155 ** Start of section using anonymous unions 00156 */ 00157 00158 #if defined(__ARMCC_VERSION) 00159 #pragma push 00160 #pragma anon_unions 00161 #elif defined(__CWCC__) 00162 #pragma push 00163 #pragma cpp_extensions on 00164 #elif defined(__GNUC__) 00165 /* anonymous unions are enabled by default */ 00166 #elif defined(__IAR_SYSTEMS_ICC__) 00167 #pragma language=extended 00168 #else 00169 #error Not supported compiler type 00170 #endif 00171 00172 /* ---------------------------------------------------------------------------- 00173 -- ADC 00174 ---------------------------------------------------------------------------- */ 00175 00176 /*! 00177 * @addtogroup ADC_Peripheral ADC 00178 * @{ 00179 */ 00180 00181 /** ADC - Peripheral register structure */ 00182 typedef struct ADC_MemMap { 00183 uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ 00184 uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ 00185 uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ 00186 uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ 00187 uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ 00188 uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ 00189 uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ 00190 uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ 00191 uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ 00192 uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ 00193 uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ 00194 uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ 00195 uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ 00196 uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ 00197 uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ 00198 uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ 00199 uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ 00200 uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ 00201 uint8_t RESERVED_0[4]; 00202 uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ 00203 uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ 00204 uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ 00205 uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ 00206 uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ 00207 uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ 00208 uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ 00209 } volatile *ADC_MemMapPtr; 00210 00211 /* ---------------------------------------------------------------------------- 00212 -- ADC - Register accessor macros 00213 ---------------------------------------------------------------------------- */ 00214 00215 /*! 00216 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros 00217 * @{ 00218 */ 00219 00220 00221 /* ADC - Register accessors */ 00222 #define ADC_SC1_REG(base,index) ((base)->SC1[index]) 00223 #define ADC_CFG1_REG(base) ((base)->CFG1) 00224 #define ADC_CFG2_REG(base) ((base)->CFG2) 00225 #define ADC_R_REG(base,index) ((base)->R[index]) 00226 #define ADC_CV1_REG(base) ((base)->CV1) 00227 #define ADC_CV2_REG(base) ((base)->CV2) 00228 #define ADC_SC2_REG(base) ((base)->SC2) 00229 #define ADC_SC3_REG(base) ((base)->SC3) 00230 #define ADC_OFS_REG(base) ((base)->OFS) 00231 #define ADC_PG_REG(base) ((base)->PG) 00232 #define ADC_MG_REG(base) ((base)->MG) 00233 #define ADC_CLPD_REG(base) ((base)->CLPD) 00234 #define ADC_CLPS_REG(base) ((base)->CLPS) 00235 #define ADC_CLP4_REG(base) ((base)->CLP4) 00236 #define ADC_CLP3_REG(base) ((base)->CLP3) 00237 #define ADC_CLP2_REG(base) ((base)->CLP2) 00238 #define ADC_CLP1_REG(base) ((base)->CLP1) 00239 #define ADC_CLP0_REG(base) ((base)->CLP0) 00240 #define ADC_CLMD_REG(base) ((base)->CLMD) 00241 #define ADC_CLMS_REG(base) ((base)->CLMS) 00242 #define ADC_CLM4_REG(base) ((base)->CLM4) 00243 #define ADC_CLM3_REG(base) ((base)->CLM3) 00244 #define ADC_CLM2_REG(base) ((base)->CLM2) 00245 #define ADC_CLM1_REG(base) ((base)->CLM1) 00246 #define ADC_CLM0_REG(base) ((base)->CLM0) 00247 00248 /*! 00249 * @} 00250 */ /* end of group ADC_Register_Accessor_Macros */ 00251 00252 00253 /* ---------------------------------------------------------------------------- 00254 -- ADC Register Masks 00255 ---------------------------------------------------------------------------- */ 00256 00257 /*! 00258 * @addtogroup ADC_Register_Masks ADC Register Masks 00259 * @{ 00260 */ 00261 00262 /* SC1 Bit Fields */ 00263 #define ADC_SC1_ADCH_MASK 0x1Fu 00264 #define ADC_SC1_ADCH_SHIFT 0 00265 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK) 00266 #define ADC_SC1_DIFF_MASK 0x20u 00267 #define ADC_SC1_DIFF_SHIFT 5 00268 #define ADC_SC1_AIEN_MASK 0x40u 00269 #define ADC_SC1_AIEN_SHIFT 6 00270 #define ADC_SC1_COCO_MASK 0x80u 00271 #define ADC_SC1_COCO_SHIFT 7 00272 /* CFG1 Bit Fields */ 00273 #define ADC_CFG1_ADICLK_MASK 0x3u 00274 #define ADC_CFG1_ADICLK_SHIFT 0 00275 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK) 00276 #define ADC_CFG1_MODE_MASK 0xCu 00277 #define ADC_CFG1_MODE_SHIFT 2 00278 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK) 00279 #define ADC_CFG1_ADLSMP_MASK 0x10u 00280 #define ADC_CFG1_ADLSMP_SHIFT 4 00281 #define ADC_CFG1_ADIV_MASK 0x60u 00282 #define ADC_CFG1_ADIV_SHIFT 5 00283 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK) 00284 #define ADC_CFG1_ADLPC_MASK 0x80u 00285 #define ADC_CFG1_ADLPC_SHIFT 7 00286 /* CFG2 Bit Fields */ 00287 #define ADC_CFG2_ADLSTS_MASK 0x3u 00288 #define ADC_CFG2_ADLSTS_SHIFT 0 00289 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK) 00290 #define ADC_CFG2_ADHSC_MASK 0x4u 00291 #define ADC_CFG2_ADHSC_SHIFT 2 00292 #define ADC_CFG2_ADACKEN_MASK 0x8u 00293 #define ADC_CFG2_ADACKEN_SHIFT 3 00294 #define ADC_CFG2_MUXSEL_MASK 0x10u 00295 #define ADC_CFG2_MUXSEL_SHIFT 4 00296 /* R Bit Fields */ 00297 #define ADC_R_D_MASK 0xFFFFu 00298 #define ADC_R_D_SHIFT 0 00299 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK) 00300 /* CV1 Bit Fields */ 00301 #define ADC_CV1_CV_MASK 0xFFFFu 00302 #define ADC_CV1_CV_SHIFT 0 00303 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK) 00304 /* CV2 Bit Fields */ 00305 #define ADC_CV2_CV_MASK 0xFFFFu 00306 #define ADC_CV2_CV_SHIFT 0 00307 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK) 00308 /* SC2 Bit Fields */ 00309 #define ADC_SC2_REFSEL_MASK 0x3u 00310 #define ADC_SC2_REFSEL_SHIFT 0 00311 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK) 00312 #define ADC_SC2_DMAEN_MASK 0x4u 00313 #define ADC_SC2_DMAEN_SHIFT 2 00314 #define ADC_SC2_ACREN_MASK 0x8u 00315 #define ADC_SC2_ACREN_SHIFT 3 00316 #define ADC_SC2_ACFGT_MASK 0x10u 00317 #define ADC_SC2_ACFGT_SHIFT 4 00318 #define ADC_SC2_ACFE_MASK 0x20u 00319 #define ADC_SC2_ACFE_SHIFT 5 00320 #define ADC_SC2_ADTRG_MASK 0x40u 00321 #define ADC_SC2_ADTRG_SHIFT 6 00322 #define ADC_SC2_ADACT_MASK 0x80u 00323 #define ADC_SC2_ADACT_SHIFT 7 00324 /* SC3 Bit Fields */ 00325 #define ADC_SC3_AVGS_MASK 0x3u 00326 #define ADC_SC3_AVGS_SHIFT 0 00327 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK) 00328 #define ADC_SC3_AVGE_MASK 0x4u 00329 #define ADC_SC3_AVGE_SHIFT 2 00330 #define ADC_SC3_ADCO_MASK 0x8u 00331 #define ADC_SC3_ADCO_SHIFT 3 00332 #define ADC_SC3_CALF_MASK 0x40u 00333 #define ADC_SC3_CALF_SHIFT 6 00334 #define ADC_SC3_CAL_MASK 0x80u 00335 #define ADC_SC3_CAL_SHIFT 7 00336 /* OFS Bit Fields */ 00337 #define ADC_OFS_OFS_MASK 0xFFFFu 00338 #define ADC_OFS_OFS_SHIFT 0 00339 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK) 00340 /* PG Bit Fields */ 00341 #define ADC_PG_PG_MASK 0xFFFFu 00342 #define ADC_PG_PG_SHIFT 0 00343 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK) 00344 /* MG Bit Fields */ 00345 #define ADC_MG_MG_MASK 0xFFFFu 00346 #define ADC_MG_MG_SHIFT 0 00347 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK) 00348 /* CLPD Bit Fields */ 00349 #define ADC_CLPD_CLPD_MASK 0x3Fu 00350 #define ADC_CLPD_CLPD_SHIFT 0 00351 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK) 00352 /* CLPS Bit Fields */ 00353 #define ADC_CLPS_CLPS_MASK 0x3Fu 00354 #define ADC_CLPS_CLPS_SHIFT 0 00355 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK) 00356 /* CLP4 Bit Fields */ 00357 #define ADC_CLP4_CLP4_MASK 0x3FFu 00358 #define ADC_CLP4_CLP4_SHIFT 0 00359 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK) 00360 /* CLP3 Bit Fields */ 00361 #define ADC_CLP3_CLP3_MASK 0x1FFu 00362 #define ADC_CLP3_CLP3_SHIFT 0 00363 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK) 00364 /* CLP2 Bit Fields */ 00365 #define ADC_CLP2_CLP2_MASK 0xFFu 00366 #define ADC_CLP2_CLP2_SHIFT 0 00367 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK) 00368 /* CLP1 Bit Fields */ 00369 #define ADC_CLP1_CLP1_MASK 0x7Fu 00370 #define ADC_CLP1_CLP1_SHIFT 0 00371 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK) 00372 /* CLP0 Bit Fields */ 00373 #define ADC_CLP0_CLP0_MASK 0x3Fu 00374 #define ADC_CLP0_CLP0_SHIFT 0 00375 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK) 00376 /* CLMD Bit Fields */ 00377 #define ADC_CLMD_CLMD_MASK 0x3Fu 00378 #define ADC_CLMD_CLMD_SHIFT 0 00379 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK) 00380 /* CLMS Bit Fields */ 00381 #define ADC_CLMS_CLMS_MASK 0x3Fu 00382 #define ADC_CLMS_CLMS_SHIFT 0 00383 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK) 00384 /* CLM4 Bit Fields */ 00385 #define ADC_CLM4_CLM4_MASK 0x3FFu 00386 #define ADC_CLM4_CLM4_SHIFT 0 00387 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK) 00388 /* CLM3 Bit Fields */ 00389 #define ADC_CLM3_CLM3_MASK 0x1FFu 00390 #define ADC_CLM3_CLM3_SHIFT 0 00391 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK) 00392 /* CLM2 Bit Fields */ 00393 #define ADC_CLM2_CLM2_MASK 0xFFu 00394 #define ADC_CLM2_CLM2_SHIFT 0 00395 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK) 00396 /* CLM1 Bit Fields */ 00397 #define ADC_CLM1_CLM1_MASK 0x7Fu 00398 #define ADC_CLM1_CLM1_SHIFT 0 00399 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK) 00400 /* CLM0 Bit Fields */ 00401 #define ADC_CLM0_CLM0_MASK 0x3Fu 00402 #define ADC_CLM0_CLM0_SHIFT 0 00403 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK) 00404 00405 /*! 00406 * @} 00407 */ /* end of group ADC_Register_Masks */ 00408 00409 00410 /* ADC - Peripheral instance base addresses */ 00411 /** Peripheral ADC0 base pointer */ 00412 #define ADC0_BASE_PTR ((ADC_MemMapPtr)0x4003B000u) 00413 /** Array initializer of ADC peripheral base pointers */ 00414 #define ADC_BASE_PTRS { ADC0_BASE_PTR } 00415 00416 /* ---------------------------------------------------------------------------- 00417 -- ADC - Register accessor macros 00418 ---------------------------------------------------------------------------- */ 00419 00420 /*! 00421 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros 00422 * @{ 00423 */ 00424 00425 00426 /* ADC - Register instance definitions */ 00427 /* ADC0 */ 00428 #define ADC0_SC1A ADC_SC1_REG(ADC0_BASE_PTR,0) 00429 #define ADC0_SC1B ADC_SC1_REG(ADC0_BASE_PTR,1) 00430 #define ADC0_CFG1 ADC_CFG1_REG(ADC0_BASE_PTR) 00431 #define ADC0_CFG2 ADC_CFG2_REG(ADC0_BASE_PTR) 00432 #define ADC0_RA ADC_R_REG(ADC0_BASE_PTR,0) 00433 #define ADC0_RB ADC_R_REG(ADC0_BASE_PTR,1) 00434 #define ADC0_CV1 ADC_CV1_REG(ADC0_BASE_PTR) 00435 #define ADC0_CV2 ADC_CV2_REG(ADC0_BASE_PTR) 00436 #define ADC0_SC2 ADC_SC2_REG(ADC0_BASE_PTR) 00437 #define ADC0_SC3 ADC_SC3_REG(ADC0_BASE_PTR) 00438 #define ADC0_OFS ADC_OFS_REG(ADC0_BASE_PTR) 00439 #define ADC0_PG ADC_PG_REG(ADC0_BASE_PTR) 00440 #define ADC0_MG ADC_MG_REG(ADC0_BASE_PTR) 00441 #define ADC0_CLPD ADC_CLPD_REG(ADC0_BASE_PTR) 00442 #define ADC0_CLPS ADC_CLPS_REG(ADC0_BASE_PTR) 00443 #define ADC0_CLP4 ADC_CLP4_REG(ADC0_BASE_PTR) 00444 #define ADC0_CLP3 ADC_CLP3_REG(ADC0_BASE_PTR) 00445 #define ADC0_CLP2 ADC_CLP2_REG(ADC0_BASE_PTR) 00446 #define ADC0_CLP1 ADC_CLP1_REG(ADC0_BASE_PTR) 00447 #define ADC0_CLP0 ADC_CLP0_REG(ADC0_BASE_PTR) 00448 #define ADC0_CLMD ADC_CLMD_REG(ADC0_BASE_PTR) 00449 #define ADC0_CLMS ADC_CLMS_REG(ADC0_BASE_PTR) 00450 #define ADC0_CLM4 ADC_CLM4_REG(ADC0_BASE_PTR) 00451 #define ADC0_CLM3 ADC_CLM3_REG(ADC0_BASE_PTR) 00452 #define ADC0_CLM2 ADC_CLM2_REG(ADC0_BASE_PTR) 00453 #define ADC0_CLM1 ADC_CLM1_REG(ADC0_BASE_PTR) 00454 #define ADC0_CLM0 ADC_CLM0_REG(ADC0_BASE_PTR) 00455 00456 /* ADC - Register array accessors */ 00457 #define ADC0_SC1(index) ADC_SC1_REG(ADC0_BASE_PTR,index) 00458 #define ADC0_R(index) ADC_R_REG(ADC0_BASE_PTR,index) 00459 00460 /*! 00461 * @} 00462 */ /* end of group ADC_Register_Accessor_Macros */ 00463 00464 00465 /*! 00466 * @} 00467 */ /* end of group ADC_Peripheral */ 00468 00469 00470 /* ---------------------------------------------------------------------------- 00471 -- BP 00472 ---------------------------------------------------------------------------- */ 00473 00474 /*! 00475 * @addtogroup BP_Peripheral BP 00476 * @{ 00477 */ 00478 00479 /** BP - Peripheral register structure */ 00480 typedef struct BP_MemMap { 00481 uint32_t CTRL; /**< FlashPatch Control Register, offset: 0x0 */ 00482 uint8_t RESERVED_0[4]; 00483 uint32_t COMP[2]; /**< FlashPatch Comparator Register 0..FlashPatch Comparator Register 1, array offset: 0x8, array step: 0x4 */ 00484 uint8_t RESERVED_1[4032]; 00485 uint32_t PID4; /**< Peripheral Identification Register 4., offset: 0xFD0 */ 00486 uint32_t PID5; /**< Peripheral Identification Register 5., offset: 0xFD4 */ 00487 uint32_t PID6; /**< Peripheral Identification Register 6., offset: 0xFD8 */ 00488 uint32_t PID7; /**< Peripheral Identification Register 7., offset: 0xFDC */ 00489 uint32_t PID0; /**< Peripheral Identification Register 0., offset: 0xFE0 */ 00490 uint32_t PID1; /**< Peripheral Identification Register 1., offset: 0xFE4 */ 00491 uint32_t PID2; /**< Peripheral Identification Register 2., offset: 0xFE8 */ 00492 uint32_t PID3; /**< Peripheral Identification Register 3., offset: 0xFEC */ 00493 uint32_t CID0; /**< Component Identification Register 0., offset: 0xFF0 */ 00494 uint32_t CID1; /**< Component Identification Register 1., offset: 0xFF4 */ 00495 uint32_t CID2; /**< Component Identification Register 2., offset: 0xFF8 */ 00496 uint32_t CID3; /**< Component Identification Register 3., offset: 0xFFC */ 00497 } volatile *BP_MemMapPtr; 00498 00499 /* ---------------------------------------------------------------------------- 00500 -- BP - Register accessor macros 00501 ---------------------------------------------------------------------------- */ 00502 00503 /*! 00504 * @addtogroup BP_Register_Accessor_Macros BP - Register accessor macros 00505 * @{ 00506 */ 00507 00508 00509 /* BP - Register accessors */ 00510 #define BP_CTRL_REG(base) ((base)->CTRL) 00511 #define BP_COMP_REG(base,index) ((base)->COMP[index]) 00512 #define BP_PID4_REG(base) ((base)->PID4) 00513 #define BP_PID5_REG(base) ((base)->PID5) 00514 #define BP_PID6_REG(base) ((base)->PID6) 00515 #define BP_PID7_REG(base) ((base)->PID7) 00516 #define BP_PID0_REG(base) ((base)->PID0) 00517 #define BP_PID1_REG(base) ((base)->PID1) 00518 #define BP_PID2_REG(base) ((base)->PID2) 00519 #define BP_PID3_REG(base) ((base)->PID3) 00520 #define BP_CID0_REG(base) ((base)->CID0) 00521 #define BP_CID1_REG(base) ((base)->CID1) 00522 #define BP_CID2_REG(base) ((base)->CID2) 00523 #define BP_CID3_REG(base) ((base)->CID3) 00524 00525 /*! 00526 * @} 00527 */ /* end of group BP_Register_Accessor_Macros */ 00528 00529 00530 /* ---------------------------------------------------------------------------- 00531 -- BP Register Masks 00532 ---------------------------------------------------------------------------- */ 00533 00534 /*! 00535 * @addtogroup BP_Register_Masks BP Register Masks 00536 * @{ 00537 */ 00538 00539 00540 /*! 00541 * @} 00542 */ /* end of group BP_Register_Masks */ 00543 00544 00545 /* BP - Peripheral instance base addresses */ 00546 /** Peripheral BP base pointer */ 00547 #define BP_BASE_PTR ((BP_MemMapPtr)0xE0002000u) 00548 /** Array initializer of BP peripheral base pointers */ 00549 #define BP_BASE_PTRS { BP_BASE_PTR } 00550 00551 /* ---------------------------------------------------------------------------- 00552 -- BP - Register accessor macros 00553 ---------------------------------------------------------------------------- */ 00554 00555 /*! 00556 * @addtogroup BP_Register_Accessor_Macros BP - Register accessor macros 00557 * @{ 00558 */ 00559 00560 00561 /* BP - Register instance definitions */ 00562 /* BP */ 00563 #define BP_CTRL BP_CTRL_REG(BP_BASE_PTR) 00564 #define BP_COMP0 BP_COMP_REG(BP_BASE_PTR,0) 00565 #define BP_COMP1 BP_COMP_REG(BP_BASE_PTR,1) 00566 #define BP_PID4 BP_PID4_REG(BP_BASE_PTR) 00567 #define BP_PID5 BP_PID5_REG(BP_BASE_PTR) 00568 #define BP_PID6 BP_PID6_REG(BP_BASE_PTR) 00569 #define BP_PID7 BP_PID7_REG(BP_BASE_PTR) 00570 #define BP_PID0 BP_PID0_REG(BP_BASE_PTR) 00571 #define BP_PID1 BP_PID1_REG(BP_BASE_PTR) 00572 #define BP_PID2 BP_PID2_REG(BP_BASE_PTR) 00573 #define BP_PID3 BP_PID3_REG(BP_BASE_PTR) 00574 #define BP_CID0 BP_CID0_REG(BP_BASE_PTR) 00575 #define BP_CID1 BP_CID1_REG(BP_BASE_PTR) 00576 #define BP_CID2 BP_CID2_REG(BP_BASE_PTR) 00577 #define BP_CID3 BP_CID3_REG(BP_BASE_PTR) 00578 00579 /* BP - Register array accessors */ 00580 #define BP_COMP(index) BP_COMP_REG(BP_BASE_PTR,index) 00581 00582 /*! 00583 * @} 00584 */ /* end of group BP_Register_Accessor_Macros */ 00585 00586 00587 /*! 00588 * @} 00589 */ /* end of group BP_Peripheral */ 00590 00591 00592 /* ---------------------------------------------------------------------------- 00593 -- CMP 00594 ---------------------------------------------------------------------------- */ 00595 00596 /*! 00597 * @addtogroup CMP_Peripheral CMP 00598 * @{ 00599 */ 00600 00601 /** CMP - Peripheral register structure */ 00602 typedef struct CMP_MemMap { 00603 uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ 00604 uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ 00605 uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ 00606 uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ 00607 uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ 00608 uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ 00609 } volatile *CMP_MemMapPtr; 00610 00611 /* ---------------------------------------------------------------------------- 00612 -- CMP - Register accessor macros 00613 ---------------------------------------------------------------------------- */ 00614 00615 /*! 00616 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros 00617 * @{ 00618 */ 00619 00620 00621 /* CMP - Register accessors */ 00622 #define CMP_CR0_REG(base) ((base)->CR0) 00623 #define CMP_CR1_REG(base) ((base)->CR1) 00624 #define CMP_FPR_REG(base) ((base)->FPR) 00625 #define CMP_SCR_REG(base) ((base)->SCR) 00626 #define CMP_DACCR_REG(base) ((base)->DACCR) 00627 #define CMP_MUXCR_REG(base) ((base)->MUXCR) 00628 00629 /*! 00630 * @} 00631 */ /* end of group CMP_Register_Accessor_Macros */ 00632 00633 00634 /* ---------------------------------------------------------------------------- 00635 -- CMP Register Masks 00636 ---------------------------------------------------------------------------- */ 00637 00638 /*! 00639 * @addtogroup CMP_Register_Masks CMP Register Masks 00640 * @{ 00641 */ 00642 00643 /* CR0 Bit Fields */ 00644 #define CMP_CR0_HYSTCTR_MASK 0x3u 00645 #define CMP_CR0_HYSTCTR_SHIFT 0 00646 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK) 00647 #define CMP_CR0_FILTER_CNT_MASK 0x70u 00648 #define CMP_CR0_FILTER_CNT_SHIFT 4 00649 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK) 00650 /* CR1 Bit Fields */ 00651 #define CMP_CR1_EN_MASK 0x1u 00652 #define CMP_CR1_EN_SHIFT 0 00653 #define CMP_CR1_OPE_MASK 0x2u 00654 #define CMP_CR1_OPE_SHIFT 1 00655 #define CMP_CR1_COS_MASK 0x4u 00656 #define CMP_CR1_COS_SHIFT 2 00657 #define CMP_CR1_INV_MASK 0x8u 00658 #define CMP_CR1_INV_SHIFT 3 00659 #define CMP_CR1_PMODE_MASK 0x10u 00660 #define CMP_CR1_PMODE_SHIFT 4 00661 #define CMP_CR1_TRIGM_MASK 0x20u 00662 #define CMP_CR1_TRIGM_SHIFT 5 00663 #define CMP_CR1_WE_MASK 0x40u 00664 #define CMP_CR1_WE_SHIFT 6 00665 #define CMP_CR1_SE_MASK 0x80u 00666 #define CMP_CR1_SE_SHIFT 7 00667 /* FPR Bit Fields */ 00668 #define CMP_FPR_FILT_PER_MASK 0xFFu 00669 #define CMP_FPR_FILT_PER_SHIFT 0 00670 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK) 00671 /* SCR Bit Fields */ 00672 #define CMP_SCR_COUT_MASK 0x1u 00673 #define CMP_SCR_COUT_SHIFT 0 00674 #define CMP_SCR_CFF_MASK 0x2u 00675 #define CMP_SCR_CFF_SHIFT 1 00676 #define CMP_SCR_CFR_MASK 0x4u 00677 #define CMP_SCR_CFR_SHIFT 2 00678 #define CMP_SCR_IEF_MASK 0x8u 00679 #define CMP_SCR_IEF_SHIFT 3 00680 #define CMP_SCR_IER_MASK 0x10u 00681 #define CMP_SCR_IER_SHIFT 4 00682 #define CMP_SCR_DMAEN_MASK 0x40u 00683 #define CMP_SCR_DMAEN_SHIFT 6 00684 /* DACCR Bit Fields */ 00685 #define CMP_DACCR_VOSEL_MASK 0x3Fu 00686 #define CMP_DACCR_VOSEL_SHIFT 0 00687 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK) 00688 #define CMP_DACCR_VRSEL_MASK 0x40u 00689 #define CMP_DACCR_VRSEL_SHIFT 6 00690 #define CMP_DACCR_DACEN_MASK 0x80u 00691 #define CMP_DACCR_DACEN_SHIFT 7 00692 /* MUXCR Bit Fields */ 00693 #define CMP_MUXCR_MSEL_MASK 0x7u 00694 #define CMP_MUXCR_MSEL_SHIFT 0 00695 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK) 00696 #define CMP_MUXCR_PSEL_MASK 0x38u 00697 #define CMP_MUXCR_PSEL_SHIFT 3 00698 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK) 00699 //#define CMP_MUXCR_PSTM_MASK 0x80u 00700 //#define CMP_MUXCR_PSTM_SHIFT 7 00701 00702 /*! 00703 * @} 00704 */ /* end of group CMP_Register_Masks */ 00705 00706 00707 /* CMP - Peripheral instance base addresses */ 00708 /** Peripheral CMP0 base pointer */ 00709 #define CMP0_BASE_PTR ((CMP_MemMapPtr)0x40073000u) 00710 /** Array initializer of CMP peripheral base pointers */ 00711 #define CMP_BASE_PTRS { CMP0_BASE_PTR } 00712 00713 /* ---------------------------------------------------------------------------- 00714 -- CMP - Register accessor macros 00715 ---------------------------------------------------------------------------- */ 00716 00717 /*! 00718 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros 00719 * @{ 00720 */ 00721 00722 00723 /* CMP - Register instance definitions */ 00724 /* CMP0 */ 00725 #define CMP0_CR0 CMP_CR0_REG(CMP0_BASE_PTR) 00726 #define CMP0_CR1 CMP_CR1_REG(CMP0_BASE_PTR) 00727 #define CMP0_FPR CMP_FPR_REG(CMP0_BASE_PTR) 00728 #define CMP0_SCR CMP_SCR_REG(CMP0_BASE_PTR) 00729 #define CMP0_DACCR CMP_DACCR_REG(CMP0_BASE_PTR) 00730 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0_BASE_PTR) 00731 00732 /*! 00733 * @} 00734 */ /* end of group CMP_Register_Accessor_Macros */ 00735 00736 00737 /*! 00738 * @} 00739 */ /* end of group CMP_Peripheral */ 00740 00741 00742 /* ---------------------------------------------------------------------------- 00743 -- CoreDebug 00744 ---------------------------------------------------------------------------- */ 00745 00746 /*! 00747 * @addtogroup CoreDebug_Peripheral CoreDebug 00748 * @{ 00749 */ 00750 00751 /** CoreDebug - Peripheral register structure */ 00752 typedef struct CoreDebug_MemMap { 00753 union { /* offset: 0x0 */ 00754 uint32_t base_DHCSR_Read; /**< Debug Halting Control and Status Register, offset: 0x0 */ 00755 uint32_t base_DHCSR_Write; /**< Debug Halting Control and Status Register, offset: 0x0 */ 00756 }; 00757 uint32_t base_DCRSR; /**< Debug Core Register Selector Register, offset: 0x4 */ 00758 uint32_t base_DCRDR; /**< Debug Core Register Data Register, offset: 0x8 */ 00759 uint32_t base_DEMCR; /**< Debug Exception and Monitor Control Register, offset: 0xC */ 00760 } volatile *CoreDebug_MemMapPtr; 00761 00762 /* ---------------------------------------------------------------------------- 00763 -- CoreDebug - Register accessor macros 00764 ---------------------------------------------------------------------------- */ 00765 00766 /*! 00767 * @addtogroup CoreDebug_Register_Accessor_Macros CoreDebug - Register accessor macros 00768 * @{ 00769 */ 00770 00771 00772 /* CoreDebug - Register accessors */ 00773 #define CoreDebug_base_DHCSR_Read_REG(base) ((base)->base_DHCSR_Read) 00774 #define CoreDebug_base_DHCSR_Write_REG(base) ((base)->base_DHCSR_Write) 00775 #define CoreDebug_base_DCRSR_REG(base) ((base)->base_DCRSR) 00776 #define CoreDebug_base_DCRDR_REG(base) ((base)->base_DCRDR) 00777 #define CoreDebug_base_DEMCR_REG(base) ((base)->base_DEMCR) 00778 00779 /*! 00780 * @} 00781 */ /* end of group CoreDebug_Register_Accessor_Macros */ 00782 00783 00784 /* ---------------------------------------------------------------------------- 00785 -- CoreDebug Register Masks 00786 ---------------------------------------------------------------------------- */ 00787 00788 /*! 00789 * @addtogroup CoreDebug_Register_Masks CoreDebug Register Masks 00790 * @{ 00791 */ 00792 00793 00794 /*! 00795 * @} 00796 */ /* end of group CoreDebug_Register_Masks */ 00797 00798 00799 /* CoreDebug - Peripheral instance base addresses */ 00800 /** Peripheral CoreDebug base pointer */ 00801 #define CoreDebug_BASE_PTR ((CoreDebug_MemMapPtr)0xE000EDF0u) 00802 /** Array initializer of CoreDebug peripheral base pointers */ 00803 #define CoreDebug_BASE_PTRS { CoreDebug_BASE_PTR } 00804 00805 /* ---------------------------------------------------------------------------- 00806 -- CoreDebug - Register accessor macros 00807 ---------------------------------------------------------------------------- */ 00808 00809 /*! 00810 * @addtogroup CoreDebug_Register_Accessor_Macros CoreDebug - Register accessor macros 00811 * @{ 00812 */ 00813 00814 00815 /* CoreDebug - Register instance definitions */ 00816 /* CoreDebug */ 00817 #define DHCSR_Read CoreDebug_base_DHCSR_Read_REG(CoreDebug_BASE_PTR) 00818 #define DHCSR_Write CoreDebug_base_DHCSR_Write_REG(CoreDebug_BASE_PTR) 00819 #define DCRSR CoreDebug_base_DCRSR_REG(CoreDebug_BASE_PTR) 00820 #define DCRDR CoreDebug_base_DCRDR_REG(CoreDebug_BASE_PTR) 00821 #define DEMCR CoreDebug_base_DEMCR_REG(CoreDebug_BASE_PTR) 00822 00823 /*! 00824 * @} 00825 */ /* end of group CoreDebug_Register_Accessor_Macros */ 00826 00827 00828 /*! 00829 * @} 00830 */ /* end of group CoreDebug_Peripheral */ 00831 00832 00833 /* ---------------------------------------------------------------------------- 00834 -- DAC 00835 ---------------------------------------------------------------------------- */ 00836 00837 /*! 00838 * @addtogroup DAC_Peripheral DAC 00839 * @{ 00840 */ 00841 00842 /** DAC - Peripheral register structure */ 00843 typedef struct DAC_MemMap { 00844 struct { /* offset: 0x0, array step: 0x2 */ 00845 uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ 00846 uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ 00847 } DAT[2]; 00848 uint8_t RESERVED_0[28]; 00849 uint8_t SR; /**< DAC Status Register, offset: 0x20 */ 00850 uint8_t C0; /**< DAC Control Register, offset: 0x21 */ 00851 uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ 00852 uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ 00853 } volatile *DAC_MemMapPtr; 00854 00855 /* ---------------------------------------------------------------------------- 00856 -- DAC - Register accessor macros 00857 ---------------------------------------------------------------------------- */ 00858 00859 /*! 00860 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros 00861 * @{ 00862 */ 00863 00864 00865 /* DAC - Register accessors */ 00866 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL) 00867 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) 00868 #define DAC_SR_REG(base) ((base)->SR) 00869 #define DAC_C0_REG(base) ((base)->C0) 00870 #define DAC_C1_REG(base) ((base)->C1) 00871 #define DAC_C2_REG(base) ((base)->C2) 00872 00873 /*! 00874 * @} 00875 */ /* end of group DAC_Register_Accessor_Macros */ 00876 00877 00878 /* ---------------------------------------------------------------------------- 00879 -- DAC Register Masks 00880 ---------------------------------------------------------------------------- */ 00881 00882 /*! 00883 * @addtogroup DAC_Register_Masks DAC Register Masks 00884 * @{ 00885 */ 00886 00887 /* DATL Bit Fields */ 00888 #define DAC_DATL_DATA0_MASK 0xFFu 00889 #define DAC_DATL_DATA0_SHIFT 0 00890 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK) 00891 /* DATH Bit Fields */ 00892 #define DAC_DATH_DATA1_MASK 0xFu 00893 #define DAC_DATH_DATA1_SHIFT 0 00894 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK) 00895 /* SR Bit Fields */ 00896 #define DAC_SR_DACBFRPBF_MASK 0x1u 00897 #define DAC_SR_DACBFRPBF_SHIFT 0 00898 #define DAC_SR_DACBFRPTF_MASK 0x2u 00899 #define DAC_SR_DACBFRPTF_SHIFT 1 00900 /* C0 Bit Fields */ 00901 #define DAC_C0_DACBBIEN_MASK 0x1u 00902 #define DAC_C0_DACBBIEN_SHIFT 0 00903 #define DAC_C0_DACBTIEN_MASK 0x2u 00904 #define DAC_C0_DACBTIEN_SHIFT 1 00905 #define DAC_C0_LPEN_MASK 0x8u 00906 #define DAC_C0_LPEN_SHIFT 3 00907 #define DAC_C0_DACSWTRG_MASK 0x10u 00908 #define DAC_C0_DACSWTRG_SHIFT 4 00909 #define DAC_C0_DACTRGSEL_MASK 0x20u 00910 #define DAC_C0_DACTRGSEL_SHIFT 5 00911 #define DAC_C0_DACRFS_MASK 0x40u 00912 #define DAC_C0_DACRFS_SHIFT 6 00913 #define DAC_C0_DACEN_MASK 0x80u 00914 #define DAC_C0_DACEN_SHIFT 7 00915 /* C1 Bit Fields */ 00916 #define DAC_C1_DACBFEN_MASK 0x1u 00917 #define DAC_C1_DACBFEN_SHIFT 0 00918 #define DAC_C1_DACBFMD_MASK 0x4u 00919 #define DAC_C1_DACBFMD_SHIFT 2 00920 #define DAC_C1_DMAEN_MASK 0x80u 00921 #define DAC_C1_DMAEN_SHIFT 7 00922 /* C2 Bit Fields */ 00923 #define DAC_C2_DACBFUP_MASK 0x1u 00924 #define DAC_C2_DACBFUP_SHIFT 0 00925 #define DAC_C2_DACBFRP_MASK 0x10u 00926 #define DAC_C2_DACBFRP_SHIFT 4 00927 00928 /*! 00929 * @} 00930 */ /* end of group DAC_Register_Masks */ 00931 00932 00933 /* DAC - Peripheral instance base addresses */ 00934 /** Peripheral DAC0 base pointer */ 00935 #define DAC0_BASE_PTR ((DAC_MemMapPtr)0x4003F000u) 00936 /** Array initializer of DAC peripheral base pointers */ 00937 #define DAC_BASE_PTRS { DAC0_BASE_PTR } 00938 00939 /* ---------------------------------------------------------------------------- 00940 -- DAC - Register accessor macros 00941 ---------------------------------------------------------------------------- */ 00942 00943 /*! 00944 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros 00945 * @{ 00946 */ 00947 00948 00949 /* DAC - Register instance definitions */ 00950 /* DAC0 */ 00951 #define DAC0_DAT0L DAC_DATL_REG(DAC0_BASE_PTR,0) 00952 #define DAC0_DAT0H DAC_DATH_REG(DAC0_BASE_PTR,0) 00953 #define DAC0_DAT1L DAC_DATL_REG(DAC0_BASE_PTR,1) 00954 #define DAC0_DAT1H DAC_DATH_REG(DAC0_BASE_PTR,1) 00955 #define DAC0_SR DAC_SR_REG(DAC0_BASE_PTR) 00956 #define DAC0_C0 DAC_C0_REG(DAC0_BASE_PTR) 00957 #define DAC0_C1 DAC_C1_REG(DAC0_BASE_PTR) 00958 #define DAC0_C2 DAC_C2_REG(DAC0_BASE_PTR) 00959 00960 /* DAC - Register array accessors */ 00961 #define DAC0_DATL(index) DAC_DATL_REG(DAC0_BASE_PTR,index) 00962 #define DAC0_DATH(index) DAC_DATH_REG(DAC0_BASE_PTR,index) 00963 00964 /*! 00965 * @} 00966 */ /* end of group DAC_Register_Accessor_Macros */ 00967 00968 00969 /*! 00970 * @} 00971 */ /* end of group DAC_Peripheral */ 00972 00973 00974 /* ---------------------------------------------------------------------------- 00975 -- DMA 00976 ---------------------------------------------------------------------------- */ 00977 00978 /*! 00979 * @addtogroup DMA_Peripheral DMA 00980 * @{ 00981 */ 00982 00983 /** DMA - Peripheral register structure */ 00984 typedef struct DMA_MemMap { 00985 uint8_t RESERVED_0[256]; 00986 struct { /* offset: 0x100, array step: 0x10 */ 00987 uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */ 00988 uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */ 00989 union { /* offset: 0x108, array step: 0x10 */ 00990 uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */ 00991 struct { /* offset: 0x108, array step: 0x10 */ 00992 uint8_t RESERVED_0[3]; 00993 uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */ 00994 } DMA_DSR_ACCESS8BIT; 00995 }; 00996 uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */ 00997 } DMA[4]; 00998 } volatile *DMA_MemMapPtr; 00999 01000 /* ---------------------------------------------------------------------------- 01001 -- DMA - Register accessor macros 01002 ---------------------------------------------------------------------------- */ 01003 01004 /*! 01005 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros 01006 * @{ 01007 */ 01008 01009 01010 /* DMA - Register accessors */ 01011 #define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR) 01012 #define DMA_DAR_REG(base,index) ((base)->DMA[index].DAR) 01013 #define DMA_DSR_BCR_REG(base,index) ((base)->DMA[index].DSR_BCR) 01014 #define DMA_DSR_REG(base,index) ((base)->DMA[index].DMA_DSR_ACCESS8BIT.DSR) 01015 #define DMA_DCR_REG(base,index) ((base)->DMA[index].DCR) 01016 01017 /*! 01018 * @} 01019 */ /* end of group DMA_Register_Accessor_Macros */ 01020 01021 01022 /* ---------------------------------------------------------------------------- 01023 -- DMA Register Masks 01024 ---------------------------------------------------------------------------- */ 01025 01026 /*! 01027 * @addtogroup DMA_Register_Masks DMA Register Masks 01028 * @{ 01029 */ 01030 01031 /* SAR Bit Fields */ 01032 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu 01033 #define DMA_SAR_SAR_SHIFT 0 01034 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK) 01035 /* DAR Bit Fields */ 01036 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu 01037 #define DMA_DAR_DAR_SHIFT 0 01038 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK) 01039 /* DSR_BCR Bit Fields */ 01040 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu 01041 #define DMA_DSR_BCR_BCR_SHIFT 0 01042 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK) 01043 #define DMA_DSR_BCR_DONE_MASK 0x1000000u 01044 #define DMA_DSR_BCR_DONE_SHIFT 24 01045 #define DMA_DSR_BCR_BSY_MASK 0x2000000u 01046 #define DMA_DSR_BCR_BSY_SHIFT 25 01047 #define DMA_DSR_BCR_REQ_MASK 0x4000000u 01048 #define DMA_DSR_BCR_REQ_SHIFT 26 01049 #define DMA_DSR_BCR_BED_MASK 0x10000000u 01050 #define DMA_DSR_BCR_BED_SHIFT 28 01051 #define DMA_DSR_BCR_BES_MASK 0x20000000u 01052 #define DMA_DSR_BCR_BES_SHIFT 29 01053 #define DMA_DSR_BCR_CE_MASK 0x40000000u 01054 #define DMA_DSR_BCR_CE_SHIFT 30 01055 /* DCR Bit Fields */ 01056 #define DMA_DCR_LCH2_MASK 0x3u 01057 #define DMA_DCR_LCH2_SHIFT 0 01058 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK) 01059 #define DMA_DCR_LCH1_MASK 0xCu 01060 #define DMA_DCR_LCH1_SHIFT 2 01061 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK) 01062 #define DMA_DCR_LINKCC_MASK 0x30u 01063 #define DMA_DCR_LINKCC_SHIFT 4 01064 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK) 01065 #define DMA_DCR_D_REQ_MASK 0x80u 01066 #define DMA_DCR_D_REQ_SHIFT 7 01067 #define DMA_DCR_DMOD_MASK 0xF00u 01068 #define DMA_DCR_DMOD_SHIFT 8 01069 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK) 01070 #define DMA_DCR_SMOD_MASK 0xF000u 01071 #define DMA_DCR_SMOD_SHIFT 12 01072 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK) 01073 #define DMA_DCR_START_MASK 0x10000u 01074 #define DMA_DCR_START_SHIFT 16 01075 #define DMA_DCR_DSIZE_MASK 0x60000u 01076 #define DMA_DCR_DSIZE_SHIFT 17 01077 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK) 01078 #define DMA_DCR_DINC_MASK 0x80000u 01079 #define DMA_DCR_DINC_SHIFT 19 01080 #define DMA_DCR_SSIZE_MASK 0x300000u 01081 #define DMA_DCR_SSIZE_SHIFT 20 01082 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK) 01083 #define DMA_DCR_SINC_MASK 0x400000u 01084 #define DMA_DCR_SINC_SHIFT 22 01085 #define DMA_DCR_EADREQ_MASK 0x800000u 01086 #define DMA_DCR_EADREQ_SHIFT 23 01087 #define DMA_DCR_AA_MASK 0x10000000u 01088 #define DMA_DCR_AA_SHIFT 28 01089 #define DMA_DCR_CS_MASK 0x20000000u 01090 #define DMA_DCR_CS_SHIFT 29 01091 #define DMA_DCR_ERQ_MASK 0x40000000u 01092 #define DMA_DCR_ERQ_SHIFT 30 01093 #define DMA_DCR_EINT_MASK 0x80000000u 01094 #define DMA_DCR_EINT_SHIFT 31 01095 01096 /*! 01097 * @} 01098 */ /* end of group DMA_Register_Masks */ 01099 01100 01101 /* DMA - Peripheral instance base addresses */ 01102 /** Peripheral DMA base pointer */ 01103 #define DMA_BASE_PTR ((DMA_MemMapPtr)0x40008000u) 01104 /** Array initializer of DMA peripheral base pointers */ 01105 #define DMA_BASE_PTRS { DMA_BASE_PTR } 01106 01107 /* ---------------------------------------------------------------------------- 01108 -- DMA - Register accessor macros 01109 ---------------------------------------------------------------------------- */ 01110 01111 /*! 01112 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros 01113 * @{ 01114 */ 01115 01116 01117 /* DMA - Register instance definitions */ 01118 /* DMA */ 01119 #define DMA_SAR0 DMA_SAR_REG(DMA_BASE_PTR,0) 01120 #define DMA_DAR0 DMA_DAR_REG(DMA_BASE_PTR,0) 01121 #define DMA_DSR_BCR0 DMA_DSR_BCR_REG(DMA_BASE_PTR,0) 01122 #define DMA_DSR0 DMA_DSR_REG(DMA_BASE_PTR,0) 01123 #define DMA_DCR0 DMA_DCR_REG(DMA_BASE_PTR,0) 01124 #define DMA_SAR1 DMA_SAR_REG(DMA_BASE_PTR,1) 01125 #define DMA_DAR1 DMA_DAR_REG(DMA_BASE_PTR,1) 01126 #define DMA_DSR_BCR1 DMA_DSR_BCR_REG(DMA_BASE_PTR,1) 01127 #define DMA_DSR1 DMA_DSR_REG(DMA_BASE_PTR,1) 01128 #define DMA_DCR1 DMA_DCR_REG(DMA_BASE_PTR,1) 01129 #define DMA_SAR2 DMA_SAR_REG(DMA_BASE_PTR,2) 01130 #define DMA_DAR2 DMA_DAR_REG(DMA_BASE_PTR,2) 01131 #define DMA_DSR_BCR2 DMA_DSR_BCR_REG(DMA_BASE_PTR,2) 01132 #define DMA_DSR2 DMA_DSR_REG(DMA_BASE_PTR,2) 01133 #define DMA_DCR2 DMA_DCR_REG(DMA_BASE_PTR,2) 01134 #define DMA_SAR3 DMA_SAR_REG(DMA_BASE_PTR,3) 01135 #define DMA_DAR3 DMA_DAR_REG(DMA_BASE_PTR,3) 01136 #define DMA_DSR_BCR3 DMA_DSR_BCR_REG(DMA_BASE_PTR,3) 01137 #define DMA_DSR3 DMA_DSR_REG(DMA_BASE_PTR,3) 01138 #define DMA_DCR3 DMA_DCR_REG(DMA_BASE_PTR,3) 01139 01140 /* DMA - Register array accessors */ 01141 #define DMA_SAR(index) DMA_SAR_REG(DMA_BASE_PTR,index) 01142 #define DMA_DAR(index) DMA_DAR_REG(DMA_BASE_PTR,index) 01143 #define DMA_DSR_BCR(index) DMA_DSR_BCR_REG(DMA_BASE_PTR,index) 01144 #define DMA_DSR(index) DMA_DSR_REG(DMA_BASE_PTR,index) 01145 #define DMA_DCR(index) DMA_DCR_REG(DMA_BASE_PTR,index) 01146 01147 /*! 01148 * @} 01149 */ /* end of group DMA_Register_Accessor_Macros */ 01150 01151 01152 /*! 01153 * @} 01154 */ /* end of group DMA_Peripheral */ 01155 01156 01157 /* ---------------------------------------------------------------------------- 01158 -- DMAMUX 01159 ---------------------------------------------------------------------------- */ 01160 01161 /*! 01162 * @addtogroup DMAMUX_Peripheral DMAMUX 01163 * @{ 01164 */ 01165 01166 /** DMAMUX - Peripheral register structure */ 01167 typedef struct DMAMUX_MemMap { 01168 uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ 01169 } volatile *DMAMUX_MemMapPtr; 01170 01171 /* ---------------------------------------------------------------------------- 01172 -- DMAMUX - Register accessor macros 01173 ---------------------------------------------------------------------------- */ 01174 01175 /*! 01176 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros 01177 * @{ 01178 */ 01179 01180 01181 /* DMAMUX - Register accessors */ 01182 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index]) 01183 01184 /*! 01185 * @} 01186 */ /* end of group DMAMUX_Register_Accessor_Macros */ 01187 01188 01189 /* ---------------------------------------------------------------------------- 01190 -- DMAMUX Register Masks 01191 ---------------------------------------------------------------------------- */ 01192 01193 /*! 01194 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks 01195 * @{ 01196 */ 01197 01198 /* CHCFG Bit Fields */ 01199 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu 01200 #define DMAMUX_CHCFG_SOURCE_SHIFT 0 01201 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK) 01202 #define DMAMUX_CHCFG_TRIG_MASK 0x40u 01203 #define DMAMUX_CHCFG_TRIG_SHIFT 6 01204 #define DMAMUX_CHCFG_ENBL_MASK 0x80u 01205 #define DMAMUX_CHCFG_ENBL_SHIFT 7 01206 01207 /*! 01208 * @} 01209 */ /* end of group DMAMUX_Register_Masks */ 01210 01211 01212 /* DMAMUX - Peripheral instance base addresses */ 01213 /** Peripheral DMAMUX0 base pointer */ 01214 #define DMAMUX0_BASE_PTR ((DMAMUX_MemMapPtr)0x40021000u) 01215 /** Array initializer of DMAMUX peripheral base pointers */ 01216 #define DMAMUX_BASE_PTRS { DMAMUX0_BASE_PTR } 01217 01218 /* ---------------------------------------------------------------------------- 01219 -- DMAMUX - Register accessor macros 01220 ---------------------------------------------------------------------------- */ 01221 01222 /*! 01223 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros 01224 * @{ 01225 */ 01226 01227 01228 /* DMAMUX - Register instance definitions */ 01229 /* DMAMUX0 */ 01230 #define DMAMUX0_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,0) 01231 #define DMAMUX0_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,1) 01232 #define DMAMUX0_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,2) 01233 #define DMAMUX0_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,3) 01234 01235 /* DMAMUX - Register array accessors */ 01236 #define DMAMUX0_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX0_BASE_PTR,index) 01237 01238 /*! 01239 * @} 01240 */ /* end of group DMAMUX_Register_Accessor_Macros */ 01241 01242 01243 /*! 01244 * @} 01245 */ /* end of group DMAMUX_Peripheral */ 01246 01247 01248 /* ---------------------------------------------------------------------------- 01249 -- DWT 01250 ---------------------------------------------------------------------------- */ 01251 01252 /*! 01253 * @addtogroup DWT_Peripheral DWT 01254 * @{ 01255 */ 01256 01257 /** DWT - Peripheral register structure */ 01258 typedef struct DWT_MemMap { 01259 uint32_t CTRL; /**< Control Register, offset: 0x0 */ 01260 uint8_t RESERVED_0[24]; 01261 uint32_t PCSR; /**< Program Counter Sample Register, offset: 0x1C */ 01262 struct { /* offset: 0x20, array step: 0x10 */ 01263 uint32_t COMP; /**< Comparator Register 0..Comparator Register 1, array offset: 0x20, array step: 0x10 */ 01264 uint32_t MASK; /**< Mask Register 0..Mask Register 1, array offset: 0x24, array step: 0x10 */ 01265 uint32_t FUNCTION; /**< Function Register 0..Function Register 1, array offset: 0x28, array step: 0x10 */ 01266 uint8_t RESERVED_0[4]; 01267 } COMPARATOR[2]; 01268 } volatile *DWT_MemMapPtr; 01269 01270 /* ---------------------------------------------------------------------------- 01271 -- DWT - Register accessor macros 01272 ---------------------------------------------------------------------------- */ 01273 01274 /*! 01275 * @addtogroup DWT_Register_Accessor_Macros DWT - Register accessor macros 01276 * @{ 01277 */ 01278 01279 01280 /* DWT - Register accessors */ 01281 #define DWT_CTRL_REG(base) ((base)->CTRL) 01282 #define DWT_PCSR_REG(base) ((base)->PCSR) 01283 #define DWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP) 01284 #define DWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK) 01285 #define DWT_FUNCTION_REG(base,index) ((base)->COMPARATOR[index].FUNCTION) 01286 01287 /*! 01288 * @} 01289 */ /* end of group DWT_Register_Accessor_Macros */ 01290 01291 01292 /* ---------------------------------------------------------------------------- 01293 -- DWT Register Masks 01294 ---------------------------------------------------------------------------- */ 01295 01296 /*! 01297 * @addtogroup DWT_Register_Masks DWT Register Masks 01298 * @{ 01299 */ 01300 01301 01302 /*! 01303 * @} 01304 */ /* end of group DWT_Register_Masks */ 01305 01306 01307 /* DWT - Peripheral instance base addresses */ 01308 /** Peripheral DWT base pointer */ 01309 #define DWT_BASE_PTR ((DWT_MemMapPtr)0xE0001000u) 01310 /** Array initializer of DWT peripheral base pointers */ 01311 #define DWT_BASE_PTRS { DWT_BASE_PTR } 01312 01313 /* ---------------------------------------------------------------------------- 01314 -- DWT - Register accessor macros 01315 ---------------------------------------------------------------------------- */ 01316 01317 /*! 01318 * @addtogroup DWT_Register_Accessor_Macros DWT - Register accessor macros 01319 * @{ 01320 */ 01321 01322 01323 /* DWT - Register instance definitions */ 01324 /* DWT */ 01325 #define DWT_CTRL DWT_CTRL_REG(DWT_BASE_PTR) 01326 #define DWT_PCSR DWT_PCSR_REG(DWT_BASE_PTR) 01327 #define DWT_COMP0 DWT_COMP_REG(DWT_BASE_PTR,0) 01328 #define DWT_MASK0 DWT_MASK_REG(DWT_BASE_PTR,0) 01329 #define DWT_FUNCTION0 DWT_FUNCTION_REG(DWT_BASE_PTR,0) 01330 #define DWT_COMP1 DWT_COMP_REG(DWT_BASE_PTR,1) 01331 #define DWT_MASK1 DWT_MASK_REG(DWT_BASE_PTR,1) 01332 #define DWT_FUNCTION1 DWT_FUNCTION_REG(DWT_BASE_PTR,1) 01333 01334 /* DWT - Register array accessors */ 01335 #define DWT_COMP(index) DWT_COMP_REG(DWT_BASE_PTR,index) 01336 #define DWT_MASK(index) DWT_MASK_REG(DWT_BASE_PTR,index) 01337 #define DWT_FUNCTION(index) DWT_FUNCTION_REG(DWT_BASE_PTR,index) 01338 01339 /*! 01340 * @} 01341 */ /* end of group DWT_Register_Accessor_Macros */ 01342 01343 01344 /*! 01345 * @} 01346 */ /* end of group DWT_Peripheral */ 01347 01348 01349 /* ---------------------------------------------------------------------------- 01350 -- FGPIO 01351 ---------------------------------------------------------------------------- */ 01352 01353 /*! 01354 * @addtogroup FGPIO_Peripheral FGPIO 01355 * @{ 01356 */ 01357 01358 /** FGPIO - Peripheral register structure */ 01359 typedef struct FGPIO_MemMap { 01360 uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 01361 uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 01362 uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 01363 uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 01364 uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 01365 uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 01366 } volatile *FGPIO_MemMapPtr; 01367 01368 /* ---------------------------------------------------------------------------- 01369 -- FGPIO - Register accessor macros 01370 ---------------------------------------------------------------------------- */ 01371 01372 /*! 01373 * @addtogroup FGPIO_Register_Accessor_Macros FGPIO - Register accessor macros 01374 * @{ 01375 */ 01376 01377 01378 /* FGPIO - Register accessors */ 01379 #define FGPIO_PDOR_REG(base) ((base)->PDOR) 01380 #define FGPIO_PSOR_REG(base) ((base)->PSOR) 01381 #define FGPIO_PCOR_REG(base) ((base)->PCOR) 01382 #define FGPIO_PTOR_REG(base) ((base)->PTOR) 01383 #define FGPIO_PDIR_REG(base) ((base)->PDIR) 01384 #define FGPIO_PDDR_REG(base) ((base)->PDDR) 01385 01386 /*! 01387 * @} 01388 */ /* end of group FGPIO_Register_Accessor_Macros */ 01389 01390 01391 /* ---------------------------------------------------------------------------- 01392 -- FGPIO Register Masks 01393 ---------------------------------------------------------------------------- */ 01394 01395 /*! 01396 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks 01397 * @{ 01398 */ 01399 01400 /* PDOR Bit Fields */ 01401 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu 01402 #define FGPIO_PDOR_PDO_SHIFT 0 01403 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK) 01404 /* PSOR Bit Fields */ 01405 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu 01406 #define FGPIO_PSOR_PTSO_SHIFT 0 01407 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK) 01408 /* PCOR Bit Fields */ 01409 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu 01410 #define FGPIO_PCOR_PTCO_SHIFT 0 01411 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK) 01412 /* PTOR Bit Fields */ 01413 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu 01414 #define FGPIO_PTOR_PTTO_SHIFT 0 01415 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK) 01416 /* PDIR Bit Fields */ 01417 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu 01418 #define FGPIO_PDIR_PDI_SHIFT 0 01419 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK) 01420 /* PDDR Bit Fields */ 01421 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu 01422 #define FGPIO_PDDR_PDD_SHIFT 0 01423 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK) 01424 01425 /*! 01426 * @} 01427 */ /* end of group FGPIO_Register_Masks */ 01428 01429 01430 /* FGPIO - Peripheral instance base addresses */ 01431 /** Peripheral FPTA base pointer */ 01432 #define FPTA_BASE_PTR ((FGPIO_MemMapPtr)0xF80FF000u) 01433 /** Peripheral FPTB base pointer */ 01434 #define FPTB_BASE_PTR ((FGPIO_MemMapPtr)0xF80FF040u) 01435 /** Peripheral FPTC base pointer */ 01436 #define FPTC_BASE_PTR ((FGPIO_MemMapPtr)0xF80FF080u) 01437 /** Peripheral FPTD base pointer */ 01438 #define FPTD_BASE_PTR ((FGPIO_MemMapPtr)0xF80FF0C0u) 01439 /** Peripheral FPTE base pointer */ 01440 #define FPTE_BASE_PTR ((FGPIO_MemMapPtr)0xF80FF100u) 01441 /** Array initializer of FGPIO peripheral base pointers */ 01442 #define FGPIO_BASE_PTRS { FPTA_BASE_PTR, FPTB_BASE_PTR, FPTC_BASE_PTR, FPTD_BASE_PTR, FPTE_BASE_PTR } 01443 01444 /* ---------------------------------------------------------------------------- 01445 -- FGPIO - Register accessor macros 01446 ---------------------------------------------------------------------------- */ 01447 01448 /*! 01449 * @addtogroup FGPIO_Register_Accessor_Macros FGPIO - Register accessor macros 01450 * @{ 01451 */ 01452 01453 01454 /* FGPIO - Register instance definitions */ 01455 /* FPTA */ 01456 #define FGPIOA_PDOR FGPIO_PDOR_REG(FPTA_BASE_PTR) 01457 #define FGPIOA_PSOR FGPIO_PSOR_REG(FPTA_BASE_PTR) 01458 #define FGPIOA_PCOR FGPIO_PCOR_REG(FPTA_BASE_PTR) 01459 #define FGPIOA_PTOR FGPIO_PTOR_REG(FPTA_BASE_PTR) 01460 #define FGPIOA_PDIR FGPIO_PDIR_REG(FPTA_BASE_PTR) 01461 #define FGPIOA_PDDR FGPIO_PDDR_REG(FPTA_BASE_PTR) 01462 /* FPTB */ 01463 #define FGPIOB_PDOR FGPIO_PDOR_REG(FPTB_BASE_PTR) 01464 #define FGPIOB_PSOR FGPIO_PSOR_REG(FPTB_BASE_PTR) 01465 #define FGPIOB_PCOR FGPIO_PCOR_REG(FPTB_BASE_PTR) 01466 #define FGPIOB_PTOR FGPIO_PTOR_REG(FPTB_BASE_PTR) 01467 #define FGPIOB_PDIR FGPIO_PDIR_REG(FPTB_BASE_PTR) 01468 #define FGPIOB_PDDR FGPIO_PDDR_REG(FPTB_BASE_PTR) 01469 /* FPTC */ 01470 #define FGPIOC_PDOR FGPIO_PDOR_REG(FPTC_BASE_PTR) 01471 #define FGPIOC_PSOR FGPIO_PSOR_REG(FPTC_BASE_PTR) 01472 #define FGPIOC_PCOR FGPIO_PCOR_REG(FPTC_BASE_PTR) 01473 #define FGPIOC_PTOR FGPIO_PTOR_REG(FPTC_BASE_PTR) 01474 #define FGPIOC_PDIR FGPIO_PDIR_REG(FPTC_BASE_PTR) 01475 #define FGPIOC_PDDR FGPIO_PDDR_REG(FPTC_BASE_PTR) 01476 /* FPTD */ 01477 #define FGPIOD_PDOR FGPIO_PDOR_REG(FPTD_BASE_PTR) 01478 #define FGPIOD_PSOR FGPIO_PSOR_REG(FPTD_BASE_PTR) 01479 #define FGPIOD_PCOR FGPIO_PCOR_REG(FPTD_BASE_PTR) 01480 #define FGPIOD_PTOR FGPIO_PTOR_REG(FPTD_BASE_PTR) 01481 #define FGPIOD_PDIR FGPIO_PDIR_REG(FPTD_BASE_PTR) 01482 #define FGPIOD_PDDR FGPIO_PDDR_REG(FPTD_BASE_PTR) 01483 /* FPTE */ 01484 #define FGPIOE_PDOR FGPIO_PDOR_REG(FPTE_BASE_PTR) 01485 #define FGPIOE_PSOR FGPIO_PSOR_REG(FPTE_BASE_PTR) 01486 #define FGPIOE_PCOR FGPIO_PCOR_REG(FPTE_BASE_PTR) 01487 #define FGPIOE_PTOR FGPIO_PTOR_REG(FPTE_BASE_PTR) 01488 #define FGPIOE_PDIR FGPIO_PDIR_REG(FPTE_BASE_PTR) 01489 #define FGPIOE_PDDR FGPIO_PDDR_REG(FPTE_BASE_PTR) 01490 01491 /*! 01492 * @} 01493 */ /* end of group FGPIO_Register_Accessor_Macros */ 01494 01495 01496 /*! 01497 * @} 01498 */ /* end of group FGPIO_Peripheral */ 01499 01500 01501 /* ---------------------------------------------------------------------------- 01502 -- FTFA 01503 ---------------------------------------------------------------------------- */ 01504 01505 /*! 01506 * @addtogroup FTFA_Peripheral FTFA 01507 * @{ 01508 */ 01509 01510 /** FTFA - Peripheral register structure */ 01511 typedef struct FTFA_MemMap { 01512 uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ 01513 uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ 01514 uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ 01515 uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ 01516 uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ 01517 uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ 01518 uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ 01519 uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ 01520 uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ 01521 uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ 01522 uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ 01523 uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ 01524 uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ 01525 uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ 01526 uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ 01527 uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ 01528 uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ 01529 uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ 01530 uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ 01531 uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ 01532 } volatile *FTFA_MemMapPtr; 01533 01534 /* ---------------------------------------------------------------------------- 01535 -- FTFA - Register accessor macros 01536 ---------------------------------------------------------------------------- */ 01537 01538 /*! 01539 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros 01540 * @{ 01541 */ 01542 01543 01544 /* FTFA - Register accessors */ 01545 #define FTFA_FSTAT_REG(base) ((base)->FSTAT) 01546 #define FTFA_FCNFG_REG(base) ((base)->FCNFG) 01547 #define FTFA_FSEC_REG(base) ((base)->FSEC) 01548 #define FTFA_FOPT_REG(base) ((base)->FOPT) 01549 #define FTFA_FCCOB3_REG(base) ((base)->FCCOB3) 01550 #define FTFA_FCCOB2_REG(base) ((base)->FCCOB2) 01551 #define FTFA_FCCOB1_REG(base) ((base)->FCCOB1) 01552 #define FTFA_FCCOB0_REG(base) ((base)->FCCOB0) 01553 #define FTFA_FCCOB7_REG(base) ((base)->FCCOB7) 01554 #define FTFA_FCCOB6_REG(base) ((base)->FCCOB6) 01555 #define FTFA_FCCOB5_REG(base) ((base)->FCCOB5) 01556 #define FTFA_FCCOB4_REG(base) ((base)->FCCOB4) 01557 #define FTFA_FCCOBB_REG(base) ((base)->FCCOBB) 01558 #define FTFA_FCCOBA_REG(base) ((base)->FCCOBA) 01559 #define FTFA_FCCOB9_REG(base) ((base)->FCCOB9) 01560 #define FTFA_FCCOB8_REG(base) ((base)->FCCOB8) 01561 #define FTFA_FPROT3_REG(base) ((base)->FPROT3) 01562 #define FTFA_FPROT2_REG(base) ((base)->FPROT2) 01563 #define FTFA_FPROT1_REG(base) ((base)->FPROT1) 01564 #define FTFA_FPROT0_REG(base) ((base)->FPROT0) 01565 01566 /*! 01567 * @} 01568 */ /* end of group FTFA_Register_Accessor_Macros */ 01569 01570 01571 /* ---------------------------------------------------------------------------- 01572 -- FTFA Register Masks 01573 ---------------------------------------------------------------------------- */ 01574 01575 /*! 01576 * @addtogroup FTFA_Register_Masks FTFA Register Masks 01577 * @{ 01578 */ 01579 01580 /* FSTAT Bit Fields */ 01581 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u 01582 #define FTFA_FSTAT_MGSTAT0_SHIFT 0 01583 #define FTFA_FSTAT_FPVIOL_MASK 0x10u 01584 #define FTFA_FSTAT_FPVIOL_SHIFT 4 01585 #define FTFA_FSTAT_ACCERR_MASK 0x20u 01586 #define FTFA_FSTAT_ACCERR_SHIFT 5 01587 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u 01588 #define FTFA_FSTAT_RDCOLERR_SHIFT 6 01589 #define FTFA_FSTAT_CCIF_MASK 0x80u 01590 #define FTFA_FSTAT_CCIF_SHIFT 7 01591 /* FCNFG Bit Fields */ 01592 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u 01593 #define FTFA_FCNFG_ERSSUSP_SHIFT 4 01594 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u 01595 #define FTFA_FCNFG_ERSAREQ_SHIFT 5 01596 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u 01597 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6 01598 #define FTFA_FCNFG_CCIE_MASK 0x80u 01599 #define FTFA_FCNFG_CCIE_SHIFT 7 01600 /* FSEC Bit Fields */ 01601 #define FTFA_FSEC_SEC_MASK 0x3u 01602 #define FTFA_FSEC_SEC_SHIFT 0 01603 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK) 01604 #define FTFA_FSEC_FSLACC_MASK 0xCu 01605 #define FTFA_FSEC_FSLACC_SHIFT 2 01606 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK) 01607 #define FTFA_FSEC_MEEN_MASK 0x30u 01608 #define FTFA_FSEC_MEEN_SHIFT 4 01609 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK) 01610 #define FTFA_FSEC_KEYEN_MASK 0xC0u 01611 #define FTFA_FSEC_KEYEN_SHIFT 6 01612 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK) 01613 /* FOPT Bit Fields */ 01614 #define FTFA_FOPT_OPT_MASK 0xFFu 01615 #define FTFA_FOPT_OPT_SHIFT 0 01616 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK) 01617 /* FCCOB3 Bit Fields */ 01618 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu 01619 #define FTFA_FCCOB3_CCOBn_SHIFT 0 01620 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK) 01621 /* FCCOB2 Bit Fields */ 01622 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu 01623 #define FTFA_FCCOB2_CCOBn_SHIFT 0 01624 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK) 01625 /* FCCOB1 Bit Fields */ 01626 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu 01627 #define FTFA_FCCOB1_CCOBn_SHIFT 0 01628 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK) 01629 /* FCCOB0 Bit Fields */ 01630 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu 01631 #define FTFA_FCCOB0_CCOBn_SHIFT 0 01632 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK) 01633 /* FCCOB7 Bit Fields */ 01634 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu 01635 #define FTFA_FCCOB7_CCOBn_SHIFT 0 01636 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK) 01637 /* FCCOB6 Bit Fields */ 01638 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu 01639 #define FTFA_FCCOB6_CCOBn_SHIFT 0 01640 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK) 01641 /* FCCOB5 Bit Fields */ 01642 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu 01643 #define FTFA_FCCOB5_CCOBn_SHIFT 0 01644 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK) 01645 /* FCCOB4 Bit Fields */ 01646 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu 01647 #define FTFA_FCCOB4_CCOBn_SHIFT 0 01648 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK) 01649 /* FCCOBB Bit Fields */ 01650 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu 01651 #define FTFA_FCCOBB_CCOBn_SHIFT 0 01652 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK) 01653 /* FCCOBA Bit Fields */ 01654 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu 01655 #define FTFA_FCCOBA_CCOBn_SHIFT 0 01656 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK) 01657 /* FCCOB9 Bit Fields */ 01658 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu 01659 #define FTFA_FCCOB9_CCOBn_SHIFT 0 01660 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK) 01661 /* FCCOB8 Bit Fields */ 01662 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu 01663 #define FTFA_FCCOB8_CCOBn_SHIFT 0 01664 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK) 01665 /* FPROT3 Bit Fields */ 01666 #define FTFA_FPROT3_PROT_MASK 0xFFu 01667 #define FTFA_FPROT3_PROT_SHIFT 0 01668 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK) 01669 /* FPROT2 Bit Fields */ 01670 #define FTFA_FPROT2_PROT_MASK 0xFFu 01671 #define FTFA_FPROT2_PROT_SHIFT 0 01672 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK) 01673 /* FPROT1 Bit Fields */ 01674 #define FTFA_FPROT1_PROT_MASK 0xFFu 01675 #define FTFA_FPROT1_PROT_SHIFT 0 01676 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK) 01677 /* FPROT0 Bit Fields */ 01678 #define FTFA_FPROT0_PROT_MASK 0xFFu 01679 #define FTFA_FPROT0_PROT_SHIFT 0 01680 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK) 01681 01682 /*! 01683 * @} 01684 */ /* end of group FTFA_Register_Masks */ 01685 01686 01687 /* FTFA - Peripheral instance base addresses */ 01688 /** Peripheral FTFA base pointer */ 01689 #define FTFA_BASE_PTR ((FTFA_MemMapPtr)0x40020000u) 01690 /** Array initializer of FTFA peripheral base pointers */ 01691 #define FTFA_BASE_PTRS { FTFA_BASE_PTR } 01692 01693 /* ---------------------------------------------------------------------------- 01694 -- FTFA - Register accessor macros 01695 ---------------------------------------------------------------------------- */ 01696 01697 /*! 01698 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros 01699 * @{ 01700 */ 01701 01702 01703 /* FTFA - Register instance definitions */ 01704 /* FTFA */ 01705 #define FTFA_FSTAT FTFA_FSTAT_REG(FTFA_BASE_PTR) 01706 #define FTFA_FCNFG FTFA_FCNFG_REG(FTFA_BASE_PTR) 01707 #define FTFA_FSEC FTFA_FSEC_REG(FTFA_BASE_PTR) 01708 #define FTFA_FOPT FTFA_FOPT_REG(FTFA_BASE_PTR) 01709 #define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA_BASE_PTR) 01710 #define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA_BASE_PTR) 01711 #define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA_BASE_PTR) 01712 #define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA_BASE_PTR) 01713 #define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA_BASE_PTR) 01714 #define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA_BASE_PTR) 01715 #define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA_BASE_PTR) 01716 #define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA_BASE_PTR) 01717 #define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA_BASE_PTR) 01718 #define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA_BASE_PTR) 01719 #define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA_BASE_PTR) 01720 #define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA_BASE_PTR) 01721 #define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA_BASE_PTR) 01722 #define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA_BASE_PTR) 01723 #define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA_BASE_PTR) 01724 #define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA_BASE_PTR) 01725 01726 /*! 01727 * @} 01728 */ /* end of group FTFA_Register_Accessor_Macros */ 01729 01730 01731 /*! 01732 * @} 01733 */ /* end of group FTFA_Peripheral */ 01734 01735 01736 /* ---------------------------------------------------------------------------- 01737 -- GPIO 01738 ---------------------------------------------------------------------------- */ 01739 01740 /*! 01741 * @addtogroup GPIO_Peripheral GPIO 01742 * @{ 01743 */ 01744 01745 /** GPIO - Peripheral register structure */ 01746 typedef struct GPIO_MemMap { 01747 uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 01748 uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 01749 uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 01750 uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 01751 uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 01752 uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 01753 } volatile *GPIO_MemMapPtr; 01754 01755 /* ---------------------------------------------------------------------------- 01756 -- GPIO - Register accessor macros 01757 ---------------------------------------------------------------------------- */ 01758 01759 /*! 01760 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros 01761 * @{ 01762 */ 01763 01764 01765 /* GPIO - Register accessors */ 01766 #define GPIO_PDOR_REG(base) ((base)->PDOR) 01767 #define GPIO_PSOR_REG(base) ((base)->PSOR) 01768 #define GPIO_PCOR_REG(base) ((base)->PCOR) 01769 #define GPIO_PTOR_REG(base) ((base)->PTOR) 01770 #define GPIO_PDIR_REG(base) ((base)->PDIR) 01771 #define GPIO_PDDR_REG(base) ((base)->PDDR) 01772 01773 /*! 01774 * @} 01775 */ /* end of group GPIO_Register_Accessor_Macros */ 01776 01777 01778 /* ---------------------------------------------------------------------------- 01779 -- GPIO Register Masks 01780 ---------------------------------------------------------------------------- */ 01781 01782 /*! 01783 * @addtogroup GPIO_Register_Masks GPIO Register Masks 01784 * @{ 01785 */ 01786 01787 /* PDOR Bit Fields */ 01788 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu 01789 #define GPIO_PDOR_PDO_SHIFT 0 01790 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK) 01791 /* PSOR Bit Fields */ 01792 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu 01793 #define GPIO_PSOR_PTSO_SHIFT 0 01794 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK) 01795 /* PCOR Bit Fields */ 01796 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu 01797 #define GPIO_PCOR_PTCO_SHIFT 0 01798 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK) 01799 /* PTOR Bit Fields */ 01800 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu 01801 #define GPIO_PTOR_PTTO_SHIFT 0 01802 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK) 01803 /* PDIR Bit Fields */ 01804 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu 01805 #define GPIO_PDIR_PDI_SHIFT 0 01806 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK) 01807 /* PDDR Bit Fields */ 01808 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu 01809 #define GPIO_PDDR_PDD_SHIFT 0 01810 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK) 01811 01812 /*! 01813 * @} 01814 */ /* end of group GPIO_Register_Masks */ 01815 01816 01817 /* GPIO - Peripheral instance base addresses */ 01818 /** Peripheral PTA base pointer */ 01819 #define PTA_BASE_PTR ((GPIO_MemMapPtr)0x400FF000u) 01820 /** Peripheral PTB base pointer */ 01821 #define PTB_BASE_PTR ((GPIO_MemMapPtr)0x400FF040u) 01822 /** Peripheral PTC base pointer */ 01823 #define PTC_BASE_PTR ((GPIO_MemMapPtr)0x400FF080u) 01824 /** Peripheral PTD base pointer */ 01825 #define PTD_BASE_PTR ((GPIO_MemMapPtr)0x400FF0C0u) 01826 /** Peripheral PTE base pointer */ 01827 #define PTE_BASE_PTR ((GPIO_MemMapPtr)0x400FF100u) 01828 /** Array initializer of GPIO peripheral base pointers */ 01829 #define GPIO_BASE_PTRS { PTA_BASE_PTR, PTB_BASE_PTR, PTC_BASE_PTR, PTD_BASE_PTR, PTE_BASE_PTR } 01830 01831 /* ---------------------------------------------------------------------------- 01832 -- GPIO - Register accessor macros 01833 ---------------------------------------------------------------------------- */ 01834 01835 /*! 01836 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros 01837 * @{ 01838 */ 01839 01840 01841 /* GPIO - Register instance definitions */ 01842 /* PTA */ 01843 #define GPIOA_PDOR GPIO_PDOR_REG(PTA_BASE_PTR) 01844 #define GPIOA_PSOR GPIO_PSOR_REG(PTA_BASE_PTR) 01845 #define GPIOA_PCOR GPIO_PCOR_REG(PTA_BASE_PTR) 01846 #define GPIOA_PTOR GPIO_PTOR_REG(PTA_BASE_PTR) 01847 #define GPIOA_PDIR GPIO_PDIR_REG(PTA_BASE_PTR) 01848 #define GPIOA_PDDR GPIO_PDDR_REG(PTA_BASE_PTR) 01849 /* PTB */ 01850 #define GPIOB_PDOR GPIO_PDOR_REG(PTB_BASE_PTR) 01851 #define GPIOB_PSOR GPIO_PSOR_REG(PTB_BASE_PTR) 01852 #define GPIOB_PCOR GPIO_PCOR_REG(PTB_BASE_PTR) 01853 #define GPIOB_PTOR GPIO_PTOR_REG(PTB_BASE_PTR) 01854 #define GPIOB_PDIR GPIO_PDIR_REG(PTB_BASE_PTR) 01855 #define GPIOB_PDDR GPIO_PDDR_REG(PTB_BASE_PTR) 01856 /* PTC */ 01857 #define GPIOC_PDOR GPIO_PDOR_REG(PTC_BASE_PTR) 01858 #define GPIOC_PSOR GPIO_PSOR_REG(PTC_BASE_PTR) 01859 #define GPIOC_PCOR GPIO_PCOR_REG(PTC_BASE_PTR) 01860 #define GPIOC_PTOR GPIO_PTOR_REG(PTC_BASE_PTR) 01861 #define GPIOC_PDIR GPIO_PDIR_REG(PTC_BASE_PTR) 01862 #define GPIOC_PDDR GPIO_PDDR_REG(PTC_BASE_PTR) 01863 /* PTD */ 01864 #define GPIOD_PDOR GPIO_PDOR_REG(PTD_BASE_PTR) 01865 #define GPIOD_PSOR GPIO_PSOR_REG(PTD_BASE_PTR) 01866 #define GPIOD_PCOR GPIO_PCOR_REG(PTD_BASE_PTR) 01867 #define GPIOD_PTOR GPIO_PTOR_REG(PTD_BASE_PTR) 01868 #define GPIOD_PDIR GPIO_PDIR_REG(PTD_BASE_PTR) 01869 #define GPIOD_PDDR GPIO_PDDR_REG(PTD_BASE_PTR) 01870 /* PTE */ 01871 #define GPIOE_PDOR GPIO_PDOR_REG(PTE_BASE_PTR) 01872 #define GPIOE_PSOR GPIO_PSOR_REG(PTE_BASE_PTR) 01873 #define GPIOE_PCOR GPIO_PCOR_REG(PTE_BASE_PTR) 01874 #define GPIOE_PTOR GPIO_PTOR_REG(PTE_BASE_PTR) 01875 #define GPIOE_PDIR GPIO_PDIR_REG(PTE_BASE_PTR) 01876 #define GPIOE_PDDR GPIO_PDDR_REG(PTE_BASE_PTR) 01877 01878 /*! 01879 * @} 01880 */ /* end of group GPIO_Register_Accessor_Macros */ 01881 01882 01883 /*! 01884 * @} 01885 */ /* end of group GPIO_Peripheral */ 01886 01887 01888 /* ---------------------------------------------------------------------------- 01889 -- I2C 01890 ---------------------------------------------------------------------------- */ 01891 01892 /*! 01893 * @addtogroup I2C_Peripheral I2C 01894 * @{ 01895 */ 01896 01897 /** I2C - Peripheral register structure */ 01898 typedef struct I2C_MemMap { 01899 uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ 01900 uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ 01901 uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ 01902 uint8_t S; /**< I2C Status register, offset: 0x3 */ 01903 uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ 01904 uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ 01905 uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ 01906 uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ 01907 uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ 01908 uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ 01909 uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ 01910 uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ 01911 } volatile *I2C_MemMapPtr; 01912 01913 /* ---------------------------------------------------------------------------- 01914 -- I2C - Register accessor macros 01915 ---------------------------------------------------------------------------- */ 01916 01917 /*! 01918 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros 01919 * @{ 01920 */ 01921 01922 01923 /* I2C - Register accessors */ 01924 #define I2C_A1_REG(base) ((base)->A1) 01925 #define I2C_F_REG(base) ((base)->F) 01926 #define I2C_C1_REG(base) ((base)->C1) 01927 #define I2C_S_REG(base) ((base)->S) 01928 #define I2C_D_REG(base) ((base)->D) 01929 #define I2C_C2_REG(base) ((base)->C2) 01930 #define I2C_FLT_REG(base) ((base)->FLT) 01931 #define I2C_RA_REG(base) ((base)->RA) 01932 #define I2C_SMB_REG(base) ((base)->SMB) 01933 #define I2C_A2_REG(base) ((base)->A2) 01934 #define I2C_SLTH_REG(base) ((base)->SLTH) 01935 #define I2C_SLTL_REG(base) ((base)->SLTL) 01936 01937 /*! 01938 * @} 01939 */ /* end of group I2C_Register_Accessor_Macros */ 01940 01941 01942 /* ---------------------------------------------------------------------------- 01943 -- I2C Register Masks 01944 ---------------------------------------------------------------------------- */ 01945 01946 /*! 01947 * @addtogroup I2C_Register_Masks I2C Register Masks 01948 * @{ 01949 */ 01950 01951 /* A1 Bit Fields */ 01952 #define I2C_A1_AD_MASK 0xFEu 01953 #define I2C_A1_AD_SHIFT 1 01954 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK) 01955 /* F Bit Fields */ 01956 #define I2C_F_ICR_MASK 0x3Fu 01957 #define I2C_F_ICR_SHIFT 0 01958 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK) 01959 #define I2C_F_MULT_MASK 0xC0u 01960 #define I2C_F_MULT_SHIFT 6 01961 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK) 01962 /* C1 Bit Fields */ 01963 #define I2C_C1_DMAEN_MASK 0x1u 01964 #define I2C_C1_DMAEN_SHIFT 0 01965 #define I2C_C1_WUEN_MASK 0x2u 01966 #define I2C_C1_WUEN_SHIFT 1 01967 #define I2C_C1_RSTA_MASK 0x4u 01968 #define I2C_C1_RSTA_SHIFT 2 01969 #define I2C_C1_TXAK_MASK 0x8u 01970 #define I2C_C1_TXAK_SHIFT 3 01971 #define I2C_C1_TX_MASK 0x10u 01972 #define I2C_C1_TX_SHIFT 4 01973 #define I2C_C1_MST_MASK 0x20u 01974 #define I2C_C1_MST_SHIFT 5 01975 #define I2C_C1_IICIE_MASK 0x40u 01976 #define I2C_C1_IICIE_SHIFT 6 01977 #define I2C_C1_IICEN_MASK 0x80u 01978 #define I2C_C1_IICEN_SHIFT 7 01979 /* S Bit Fields */ 01980 #define I2C_S_RXAK_MASK 0x1u 01981 #define I2C_S_RXAK_SHIFT 0 01982 #define I2C_S_IICIF_MASK 0x2u 01983 #define I2C_S_IICIF_SHIFT 1 01984 #define I2C_S_SRW_MASK 0x4u 01985 #define I2C_S_SRW_SHIFT 2 01986 #define I2C_S_RAM_MASK 0x8u 01987 #define I2C_S_RAM_SHIFT 3 01988 #define I2C_S_ARBL_MASK 0x10u 01989 #define I2C_S_ARBL_SHIFT 4 01990 #define I2C_S_BUSY_MASK 0x20u 01991 #define I2C_S_BUSY_SHIFT 5 01992 #define I2C_S_IAAS_MASK 0x40u 01993 #define I2C_S_IAAS_SHIFT 6 01994 #define I2C_S_TCF_MASK 0x80u 01995 #define I2C_S_TCF_SHIFT 7 01996 /* D Bit Fields */ 01997 #define I2C_D_DATA_MASK 0xFFu 01998 #define I2C_D_DATA_SHIFT 0 01999 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK) 02000 /* C2 Bit Fields */ 02001 #define I2C_C2_AD_MASK 0x7u 02002 #define I2C_C2_AD_SHIFT 0 02003 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK) 02004 #define I2C_C2_RMEN_MASK 0x8u 02005 #define I2C_C2_RMEN_SHIFT 3 02006 #define I2C_C2_SBRC_MASK 0x10u 02007 #define I2C_C2_SBRC_SHIFT 4 02008 #define I2C_C2_HDRS_MASK 0x20u 02009 #define I2C_C2_HDRS_SHIFT 5 02010 #define I2C_C2_ADEXT_MASK 0x40u 02011 #define I2C_C2_ADEXT_SHIFT 6 02012 #define I2C_C2_GCAEN_MASK 0x80u 02013 #define I2C_C2_GCAEN_SHIFT 7 02014 /* FLT Bit Fields */ 02015 #define I2C_FLT_FLT_MASK 0x1Fu 02016 #define I2C_FLT_FLT_SHIFT 0 02017 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK) 02018 #define I2C_FLT_STOPIE_MASK 0x20u 02019 #define I2C_FLT_STOPIE_SHIFT 5 02020 #define I2C_FLT_STOPF_MASK 0x40u 02021 #define I2C_FLT_STOPF_SHIFT 6 02022 #define I2C_FLT_SHEN_MASK 0x80u 02023 #define I2C_FLT_SHEN_SHIFT 7 02024 /* RA Bit Fields */ 02025 #define I2C_RA_RAD_MASK 0xFEu 02026 #define I2C_RA_RAD_SHIFT 1 02027 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK) 02028 /* SMB Bit Fields */ 02029 #define I2C_SMB_SHTF2IE_MASK 0x1u 02030 #define I2C_SMB_SHTF2IE_SHIFT 0 02031 #define I2C_SMB_SHTF2_MASK 0x2u 02032 #define I2C_SMB_SHTF2_SHIFT 1 02033 #define I2C_SMB_SHTF1_MASK 0x4u 02034 #define I2C_SMB_SHTF1_SHIFT 2 02035 #define I2C_SMB_SLTF_MASK 0x8u 02036 #define I2C_SMB_SLTF_SHIFT 3 02037 #define I2C_SMB_TCKSEL_MASK 0x10u 02038 #define I2C_SMB_TCKSEL_SHIFT 4 02039 #define I2C_SMB_SIICAEN_MASK 0x20u 02040 #define I2C_SMB_SIICAEN_SHIFT 5 02041 #define I2C_SMB_ALERTEN_MASK 0x40u 02042 #define I2C_SMB_ALERTEN_SHIFT 6 02043 #define I2C_SMB_FACK_MASK 0x80u 02044 #define I2C_SMB_FACK_SHIFT 7 02045 /* A2 Bit Fields */ 02046 #define I2C_A2_SAD_MASK 0xFEu 02047 #define I2C_A2_SAD_SHIFT 1 02048 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK) 02049 /* SLTH Bit Fields */ 02050 #define I2C_SLTH_SSLT_MASK 0xFFu 02051 #define I2C_SLTH_SSLT_SHIFT 0 02052 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK) 02053 /* SLTL Bit Fields */ 02054 #define I2C_SLTL_SSLT_MASK 0xFFu 02055 #define I2C_SLTL_SSLT_SHIFT 0 02056 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK) 02057 02058 /*! 02059 * @} 02060 */ /* end of group I2C_Register_Masks */ 02061 02062 02063 /* I2C - Peripheral instance base addresses */ 02064 /** Peripheral I2C0 base pointer */ 02065 #define I2C0_BASE_PTR ((I2C_MemMapPtr)0x40066000u) 02066 /** Peripheral I2C1 base pointer */ 02067 #define I2C1_BASE_PTR ((I2C_MemMapPtr)0x40067000u) 02068 /** Array initializer of I2C peripheral base pointers */ 02069 #define I2C_BASE_PTRS { I2C0_BASE_PTR, I2C1_BASE_PTR } 02070 02071 /* ---------------------------------------------------------------------------- 02072 -- I2C - Register accessor macros 02073 ---------------------------------------------------------------------------- */ 02074 02075 /*! 02076 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros 02077 * @{ 02078 */ 02079 02080 02081 /* I2C - Register instance definitions */ 02082 /* I2C0 */ 02083 #define I2C0_A1 I2C_A1_REG(I2C0_BASE_PTR) 02084 #define I2C0_F I2C_F_REG(I2C0_BASE_PTR) 02085 #define I2C0_C1 I2C_C1_REG(I2C0_BASE_PTR) 02086 #define I2C0_S I2C_S_REG(I2C0_BASE_PTR) 02087 #define I2C0_D I2C_D_REG(I2C0_BASE_PTR) 02088 #define I2C0_C2 I2C_C2_REG(I2C0_BASE_PTR) 02089 #define I2C0_FLT I2C_FLT_REG(I2C0_BASE_PTR) 02090 #define I2C0_RA I2C_RA_REG(I2C0_BASE_PTR) 02091 #define I2C0_SMB I2C_SMB_REG(I2C0_BASE_PTR) 02092 #define I2C0_A2 I2C_A2_REG(I2C0_BASE_PTR) 02093 #define I2C0_SLTH I2C_SLTH_REG(I2C0_BASE_PTR) 02094 #define I2C0_SLTL I2C_SLTL_REG(I2C0_BASE_PTR) 02095 /* I2C1 */ 02096 #define I2C1_A1 I2C_A1_REG(I2C1_BASE_PTR) 02097 #define I2C1_F I2C_F_REG(I2C1_BASE_PTR) 02098 #define I2C1_C1 I2C_C1_REG(I2C1_BASE_PTR) 02099 #define I2C1_S I2C_S_REG(I2C1_BASE_PTR) 02100 #define I2C1_D I2C_D_REG(I2C1_BASE_PTR) 02101 #define I2C1_C2 I2C_C2_REG(I2C1_BASE_PTR) 02102 #define I2C1_FLT I2C_FLT_REG(I2C1_BASE_PTR) 02103 #define I2C1_RA I2C_RA_REG(I2C1_BASE_PTR) 02104 #define I2C1_SMB I2C_SMB_REG(I2C1_BASE_PTR) 02105 #define I2C1_A2 I2C_A2_REG(I2C1_BASE_PTR) 02106 #define I2C1_SLTH I2C_SLTH_REG(I2C1_BASE_PTR) 02107 #define I2C1_SLTL I2C_SLTL_REG(I2C1_BASE_PTR) 02108 02109 /*! 02110 * @} 02111 */ /* end of group I2C_Register_Accessor_Macros */ 02112 02113 02114 /*! 02115 * @} 02116 */ /* end of group I2C_Peripheral */ 02117 02118 02119 /* ---------------------------------------------------------------------------- 02120 -- LLWU 02121 ---------------------------------------------------------------------------- */ 02122 02123 /*! 02124 * @addtogroup LLWU_Peripheral LLWU 02125 * @{ 02126 */ 02127 02128 /** LLWU - Peripheral register structure */ 02129 typedef struct LLWU_MemMap { 02130 uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ 02131 uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ 02132 uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ 02133 uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ 02134 uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ 02135 uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ 02136 uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ 02137 uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ 02138 uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ 02139 uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ 02140 } volatile *LLWU_MemMapPtr; 02141 02142 /* ---------------------------------------------------------------------------- 02143 -- LLWU - Register accessor macros 02144 ---------------------------------------------------------------------------- */ 02145 02146 /*! 02147 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros 02148 * @{ 02149 */ 02150 02151 02152 /* LLWU - Register accessors */ 02153 #define LLWU_PE1_REG(base) ((base)->PE1) 02154 #define LLWU_PE2_REG(base) ((base)->PE2) 02155 #define LLWU_PE3_REG(base) ((base)->PE3) 02156 #define LLWU_PE4_REG(base) ((base)->PE4) 02157 #define LLWU_ME_REG(base) ((base)->ME) 02158 #define LLWU_F1_REG(base) ((base)->F1) 02159 #define LLWU_F2_REG(base) ((base)->F2) 02160 #define LLWU_F3_REG(base) ((base)->F3) 02161 #define LLWU_FILT1_REG(base) ((base)->FILT1) 02162 #define LLWU_FILT2_REG(base) ((base)->FILT2) 02163 02164 /*! 02165 * @} 02166 */ /* end of group LLWU_Register_Accessor_Macros */ 02167 02168 02169 /* ---------------------------------------------------------------------------- 02170 -- LLWU Register Masks 02171 ---------------------------------------------------------------------------- */ 02172 02173 /*! 02174 * @addtogroup LLWU_Register_Masks LLWU Register Masks 02175 * @{ 02176 */ 02177 02178 /* PE1 Bit Fields */ 02179 #define LLWU_PE1_WUPE0_MASK 0x3u 02180 #define LLWU_PE1_WUPE0_SHIFT 0 02181 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK) 02182 #define LLWU_PE1_WUPE1_MASK 0xCu 02183 #define LLWU_PE1_WUPE1_SHIFT 2 02184 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK) 02185 #define LLWU_PE1_WUPE2_MASK 0x30u 02186 #define LLWU_PE1_WUPE2_SHIFT 4 02187 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK) 02188 #define LLWU_PE1_WUPE3_MASK 0xC0u 02189 #define LLWU_PE1_WUPE3_SHIFT 6 02190 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK) 02191 /* PE2 Bit Fields */ 02192 #define LLWU_PE2_WUPE4_MASK 0x3u 02193 #define LLWU_PE2_WUPE4_SHIFT 0 02194 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK) 02195 #define LLWU_PE2_WUPE5_MASK 0xCu 02196 #define LLWU_PE2_WUPE5_SHIFT 2 02197 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK) 02198 #define LLWU_PE2_WUPE6_MASK 0x30u 02199 #define LLWU_PE2_WUPE6_SHIFT 4 02200 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK) 02201 #define LLWU_PE2_WUPE7_MASK 0xC0u 02202 #define LLWU_PE2_WUPE7_SHIFT 6 02203 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK) 02204 /* PE3 Bit Fields */ 02205 #define LLWU_PE3_WUPE8_MASK 0x3u 02206 #define LLWU_PE3_WUPE8_SHIFT 0 02207 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK) 02208 #define LLWU_PE3_WUPE9_MASK 0xCu 02209 #define LLWU_PE3_WUPE9_SHIFT 2 02210 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK) 02211 #define LLWU_PE3_WUPE10_MASK 0x30u 02212 #define LLWU_PE3_WUPE10_SHIFT 4 02213 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK) 02214 #define LLWU_PE3_WUPE11_MASK 0xC0u 02215 #define LLWU_PE3_WUPE11_SHIFT 6 02216 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK) 02217 /* PE4 Bit Fields */ 02218 #define LLWU_PE4_WUPE12_MASK 0x3u 02219 #define LLWU_PE4_WUPE12_SHIFT 0 02220 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK) 02221 #define LLWU_PE4_WUPE13_MASK 0xCu 02222 #define LLWU_PE4_WUPE13_SHIFT 2 02223 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK) 02224 #define LLWU_PE4_WUPE14_MASK 0x30u 02225 #define LLWU_PE4_WUPE14_SHIFT 4 02226 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK) 02227 #define LLWU_PE4_WUPE15_MASK 0xC0u 02228 #define LLWU_PE4_WUPE15_SHIFT 6 02229 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK) 02230 /* ME Bit Fields */ 02231 #define LLWU_ME_WUME0_MASK 0x1u 02232 #define LLWU_ME_WUME0_SHIFT 0 02233 #define LLWU_ME_WUME1_MASK 0x2u 02234 #define LLWU_ME_WUME1_SHIFT 1 02235 #define LLWU_ME_WUME2_MASK 0x4u 02236 #define LLWU_ME_WUME2_SHIFT 2 02237 #define LLWU_ME_WUME3_MASK 0x8u 02238 #define LLWU_ME_WUME3_SHIFT 3 02239 #define LLWU_ME_WUME4_MASK 0x10u 02240 #define LLWU_ME_WUME4_SHIFT 4 02241 #define LLWU_ME_WUME5_MASK 0x20u 02242 #define LLWU_ME_WUME5_SHIFT 5 02243 #define LLWU_ME_WUME6_MASK 0x40u 02244 #define LLWU_ME_WUME6_SHIFT 6 02245 #define LLWU_ME_WUME7_MASK 0x80u 02246 #define LLWU_ME_WUME7_SHIFT 7 02247 /* F1 Bit Fields */ 02248 #define LLWU_F1_WUF0_MASK 0x1u 02249 #define LLWU_F1_WUF0_SHIFT 0 02250 #define LLWU_F1_WUF1_MASK 0x2u 02251 #define LLWU_F1_WUF1_SHIFT 1 02252 #define LLWU_F1_WUF2_MASK 0x4u 02253 #define LLWU_F1_WUF2_SHIFT 2 02254 #define LLWU_F1_WUF3_MASK 0x8u 02255 #define LLWU_F1_WUF3_SHIFT 3 02256 #define LLWU_F1_WUF4_MASK 0x10u 02257 #define LLWU_F1_WUF4_SHIFT 4 02258 #define LLWU_F1_WUF5_MASK 0x20u 02259 #define LLWU_F1_WUF5_SHIFT 5 02260 #define LLWU_F1_WUF6_MASK 0x40u 02261 #define LLWU_F1_WUF6_SHIFT 6 02262 #define LLWU_F1_WUF7_MASK 0x80u 02263 #define LLWU_F1_WUF7_SHIFT 7 02264 /* F2 Bit Fields */ 02265 #define LLWU_F2_WUF8_MASK 0x1u 02266 #define LLWU_F2_WUF8_SHIFT 0 02267 #define LLWU_F2_WUF9_MASK 0x2u 02268 #define LLWU_F2_WUF9_SHIFT 1 02269 #define LLWU_F2_WUF10_MASK 0x4u 02270 #define LLWU_F2_WUF10_SHIFT 2 02271 #define LLWU_F2_WUF11_MASK 0x8u 02272 #define LLWU_F2_WUF11_SHIFT 3 02273 #define LLWU_F2_WUF12_MASK 0x10u 02274 #define LLWU_F2_WUF12_SHIFT 4 02275 #define LLWU_F2_WUF13_MASK 0x20u 02276 #define LLWU_F2_WUF13_SHIFT 5 02277 #define LLWU_F2_WUF14_MASK 0x40u 02278 #define LLWU_F2_WUF14_SHIFT 6 02279 #define LLWU_F2_WUF15_MASK 0x80u 02280 #define LLWU_F2_WUF15_SHIFT 7 02281 /* F3 Bit Fields */ 02282 #define LLWU_F3_MWUF0_MASK 0x1u 02283 #define LLWU_F3_MWUF0_SHIFT 0 02284 #define LLWU_F3_MWUF1_MASK 0x2u 02285 #define LLWU_F3_MWUF1_SHIFT 1 02286 #define LLWU_F3_MWUF2_MASK 0x4u 02287 #define LLWU_F3_MWUF2_SHIFT 2 02288 #define LLWU_F3_MWUF3_MASK 0x8u 02289 #define LLWU_F3_MWUF3_SHIFT 3 02290 #define LLWU_F3_MWUF4_MASK 0x10u 02291 #define LLWU_F3_MWUF4_SHIFT 4 02292 #define LLWU_F3_MWUF5_MASK 0x20u 02293 #define LLWU_F3_MWUF5_SHIFT 5 02294 #define LLWU_F3_MWUF6_MASK 0x40u 02295 #define LLWU_F3_MWUF6_SHIFT 6 02296 #define LLWU_F3_MWUF7_MASK 0x80u 02297 #define LLWU_F3_MWUF7_SHIFT 7 02298 /* FILT1 Bit Fields */ 02299 #define LLWU_FILT1_FILTSEL_MASK 0xFu 02300 #define LLWU_FILT1_FILTSEL_SHIFT 0 02301 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK) 02302 #define LLWU_FILT1_FILTE_MASK 0x60u 02303 #define LLWU_FILT1_FILTE_SHIFT 5 02304 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK) 02305 #define LLWU_FILT1_FILTF_MASK 0x80u 02306 #define LLWU_FILT1_FILTF_SHIFT 7 02307 /* FILT2 Bit Fields */ 02308 #define LLWU_FILT2_FILTSEL_MASK 0xFu 02309 #define LLWU_FILT2_FILTSEL_SHIFT 0 02310 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK) 02311 #define LLWU_FILT2_FILTE_MASK 0x60u 02312 #define LLWU_FILT2_FILTE_SHIFT 5 02313 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK) 02314 #define LLWU_FILT2_FILTF_MASK 0x80u 02315 #define LLWU_FILT2_FILTF_SHIFT 7 02316 02317 /*! 02318 * @} 02319 */ /* end of group LLWU_Register_Masks */ 02320 02321 02322 /* LLWU - Peripheral instance base addresses */ 02323 /** Peripheral LLWU base pointer */ 02324 #define LLWU_BASE_PTR ((LLWU_MemMapPtr)0x4007C000u) 02325 /** Array initializer of LLWU peripheral base pointers */ 02326 #define LLWU_BASE_PTRS { LLWU_BASE_PTR } 02327 02328 /* ---------------------------------------------------------------------------- 02329 -- LLWU - Register accessor macros 02330 ---------------------------------------------------------------------------- */ 02331 02332 /*! 02333 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros 02334 * @{ 02335 */ 02336 02337 02338 /* LLWU - Register instance definitions */ 02339 /* LLWU */ 02340 #define LLWU_PE1 LLWU_PE1_REG(LLWU_BASE_PTR) 02341 #define LLWU_PE2 LLWU_PE2_REG(LLWU_BASE_PTR) 02342 #define LLWU_PE3 LLWU_PE3_REG(LLWU_BASE_PTR) 02343 #define LLWU_PE4 LLWU_PE4_REG(LLWU_BASE_PTR) 02344 #define LLWU_ME LLWU_ME_REG(LLWU_BASE_PTR) 02345 #define LLWU_F1 LLWU_F1_REG(LLWU_BASE_PTR) 02346 #define LLWU_F2 LLWU_F2_REG(LLWU_BASE_PTR) 02347 #define LLWU_F3 LLWU_F3_REG(LLWU_BASE_PTR) 02348 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU_BASE_PTR) 02349 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU_BASE_PTR) 02350 02351 /*! 02352 * @} 02353 */ /* end of group LLWU_Register_Accessor_Macros */ 02354 02355 02356 /*! 02357 * @} 02358 */ /* end of group LLWU_Peripheral */ 02359 02360 02361 /* ---------------------------------------------------------------------------- 02362 -- LPTMR 02363 ---------------------------------------------------------------------------- */ 02364 02365 /*! 02366 * @addtogroup LPTMR_Peripheral LPTMR 02367 * @{ 02368 */ 02369 02370 /** LPTMR - Peripheral register structure */ 02371 typedef struct LPTMR_MemMap { 02372 uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ 02373 uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ 02374 uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ 02375 uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ 02376 } volatile *LPTMR_MemMapPtr; 02377 02378 /* ---------------------------------------------------------------------------- 02379 -- LPTMR - Register accessor macros 02380 ---------------------------------------------------------------------------- */ 02381 02382 /*! 02383 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros 02384 * @{ 02385 */ 02386 02387 02388 /* LPTMR - Register accessors */ 02389 #define LPTMR_CSR_REG(base) ((base)->CSR) 02390 #define LPTMR_PSR_REG(base) ((base)->PSR) 02391 #define LPTMR_CMR_REG(base) ((base)->CMR) 02392 #define LPTMR_CNR_REG(base) ((base)->CNR) 02393 02394 /*! 02395 * @} 02396 */ /* end of group LPTMR_Register_Accessor_Macros */ 02397 02398 02399 /* ---------------------------------------------------------------------------- 02400 -- LPTMR Register Masks 02401 ---------------------------------------------------------------------------- */ 02402 02403 /*! 02404 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks 02405 * @{ 02406 */ 02407 02408 /* CSR Bit Fields */ 02409 #define LPTMR_CSR_TEN_MASK 0x1u 02410 #define LPTMR_CSR_TEN_SHIFT 0 02411 #define LPTMR_CSR_TMS_MASK 0x2u 02412 #define LPTMR_CSR_TMS_SHIFT 1 02413 #define LPTMR_CSR_TFC_MASK 0x4u 02414 #define LPTMR_CSR_TFC_SHIFT 2 02415 #define LPTMR_CSR_TPP_MASK 0x8u 02416 #define LPTMR_CSR_TPP_SHIFT 3 02417 #define LPTMR_CSR_TPS_MASK 0x30u 02418 #define LPTMR_CSR_TPS_SHIFT 4 02419 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK) 02420 #define LPTMR_CSR_TIE_MASK 0x40u 02421 #define LPTMR_CSR_TIE_SHIFT 6 02422 #define LPTMR_CSR_TCF_MASK 0x80u 02423 #define LPTMR_CSR_TCF_SHIFT 7 02424 /* PSR Bit Fields */ 02425 #define LPTMR_PSR_PCS_MASK 0x3u 02426 #define LPTMR_PSR_PCS_SHIFT 0 02427 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK) 02428 #define LPTMR_PSR_PBYP_MASK 0x4u 02429 #define LPTMR_PSR_PBYP_SHIFT 2 02430 #define LPTMR_PSR_PRESCALE_MASK 0x78u 02431 #define LPTMR_PSR_PRESCALE_SHIFT 3 02432 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK) 02433 /* CMR Bit Fields */ 02434 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu 02435 #define LPTMR_CMR_COMPARE_SHIFT 0 02436 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK) 02437 /* CNR Bit Fields */ 02438 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu 02439 #define LPTMR_CNR_COUNTER_SHIFT 0 02440 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK) 02441 02442 /*! 02443 * @} 02444 */ /* end of group LPTMR_Register_Masks */ 02445 02446 02447 /* LPTMR - Peripheral instance base addresses */ 02448 /** Peripheral LPTMR0 base pointer */ 02449 #define LPTMR0_BASE_PTR ((LPTMR_MemMapPtr)0x40040000u) 02450 /** Array initializer of LPTMR peripheral base pointers */ 02451 #define LPTMR_BASE_PTRS { LPTMR0_BASE_PTR } 02452 02453 /* ---------------------------------------------------------------------------- 02454 -- LPTMR - Register accessor macros 02455 ---------------------------------------------------------------------------- */ 02456 02457 /*! 02458 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros 02459 * @{ 02460 */ 02461 02462 02463 /* LPTMR - Register instance definitions */ 02464 /* LPTMR0 */ 02465 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0_BASE_PTR) 02466 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0_BASE_PTR) 02467 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0_BASE_PTR) 02468 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0_BASE_PTR) 02469 02470 /*! 02471 * @} 02472 */ /* end of group LPTMR_Register_Accessor_Macros */ 02473 02474 02475 /*! 02476 * @} 02477 */ /* end of group LPTMR_Peripheral */ 02478 02479 02480 /* ---------------------------------------------------------------------------- 02481 -- MCG 02482 ---------------------------------------------------------------------------- */ 02483 02484 /*! 02485 * @addtogroup MCG_Peripheral MCG 02486 * @{ 02487 */ 02488 02489 /** MCG - Peripheral register structure */ 02490 typedef struct MCG_MemMap { 02491 uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ 02492 uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ 02493 uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ 02494 uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ 02495 uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ 02496 uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ 02497 uint8_t S; /**< MCG Status Register, offset: 0x6 */ 02498 uint8_t RESERVED_0[1]; 02499 uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ 02500 uint8_t RESERVED_1[1]; 02501 uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ 02502 uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ 02503 uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ 02504 uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ 02505 uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */ 02506 uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */ 02507 } volatile *MCG_MemMapPtr; 02508 02509 /* ---------------------------------------------------------------------------- 02510 -- MCG - Register accessor macros 02511 ---------------------------------------------------------------------------- */ 02512 02513 /*! 02514 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros 02515 * @{ 02516 */ 02517 02518 02519 /* MCG - Register accessors */ 02520 #define MCG_C1_REG(base) ((base)->C1) 02521 #define MCG_C2_REG(base) ((base)->C2) 02522 #define MCG_C3_REG(base) ((base)->C3) 02523 #define MCG_C4_REG(base) ((base)->C4) 02524 #define MCG_C5_REG(base) ((base)->C5) 02525 #define MCG_C6_REG(base) ((base)->C6) 02526 #define MCG_S_REG(base) ((base)->S) 02527 #define MCG_SC_REG(base) ((base)->SC) 02528 #define MCG_ATCVH_REG(base) ((base)->ATCVH) 02529 #define MCG_ATCVL_REG(base) ((base)->ATCVL) 02530 #define MCG_C7_REG(base) ((base)->C7) 02531 #define MCG_C8_REG(base) ((base)->C8) 02532 #define MCG_C9_REG(base) ((base)->C9) 02533 #define MCG_C10_REG(base) ((base)->C10) 02534 02535 /*! 02536 * @} 02537 */ /* end of group MCG_Register_Accessor_Macros */ 02538 02539 02540 /* ---------------------------------------------------------------------------- 02541 -- MCG Register Masks 02542 ---------------------------------------------------------------------------- */ 02543 02544 /*! 02545 * @addtogroup MCG_Register_Masks MCG Register Masks 02546 * @{ 02547 */ 02548 02549 /* C1 Bit Fields */ 02550 #define MCG_C1_IREFSTEN_MASK 0x1u 02551 #define MCG_C1_IREFSTEN_SHIFT 0 02552 #define MCG_C1_IRCLKEN_MASK 0x2u 02553 #define MCG_C1_IRCLKEN_SHIFT 1 02554 #define MCG_C1_IREFS_MASK 0x4u 02555 #define MCG_C1_IREFS_SHIFT 2 02556 #define MCG_C1_FRDIV_MASK 0x38u 02557 #define MCG_C1_FRDIV_SHIFT 3 02558 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK) 02559 #define MCG_C1_CLKS_MASK 0xC0u 02560 #define MCG_C1_CLKS_SHIFT 6 02561 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK) 02562 /* C2 Bit Fields */ 02563 #define MCG_C2_IRCS_MASK 0x1u 02564 #define MCG_C2_IRCS_SHIFT 0 02565 #define MCG_C2_LP_MASK 0x2u 02566 #define MCG_C2_LP_SHIFT 1 02567 #define MCG_C2_EREFS0_MASK 0x4u 02568 #define MCG_C2_EREFS0_SHIFT 2 02569 #define MCG_C2_HGO0_MASK 0x8u 02570 #define MCG_C2_HGO0_SHIFT 3 02571 #define MCG_C2_RANGE0_MASK 0x30u 02572 #define MCG_C2_RANGE0_SHIFT 4 02573 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK) 02574 #define MCG_C2_LOCRE0_MASK 0x80u 02575 #define MCG_C2_LOCRE0_SHIFT 7 02576 /* C3 Bit Fields */ 02577 #define MCG_C3_SCTRIM_MASK 0xFFu 02578 #define MCG_C3_SCTRIM_SHIFT 0 02579 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK) 02580 /* C4 Bit Fields */ 02581 #define MCG_C4_SCFTRIM_MASK 0x1u 02582 #define MCG_C4_SCFTRIM_SHIFT 0 02583 #define MCG_C4_FCTRIM_MASK 0x1Eu 02584 #define MCG_C4_FCTRIM_SHIFT 1 02585 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK) 02586 #define MCG_C4_DRST_DRS_MASK 0x60u 02587 #define MCG_C4_DRST_DRS_SHIFT 5 02588 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK) 02589 #define MCG_C4_DMX32_MASK 0x80u 02590 #define MCG_C4_DMX32_SHIFT 7 02591 /* C5 Bit Fields */ 02592 #define MCG_C5_PRDIV0_MASK 0x1Fu 02593 #define MCG_C5_PRDIV0_SHIFT 0 02594 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK) 02595 #define MCG_C5_PLLSTEN0_MASK 0x20u 02596 #define MCG_C5_PLLSTEN0_SHIFT 5 02597 #define MCG_C5_PLLCLKEN0_MASK 0x40u 02598 #define MCG_C5_PLLCLKEN0_SHIFT 6 02599 /* C6 Bit Fields */ 02600 #define MCG_C6_VDIV0_MASK 0x1Fu 02601 #define MCG_C6_VDIV0_SHIFT 0 02602 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK) 02603 #define MCG_C6_CME0_MASK 0x20u 02604 #define MCG_C6_CME0_SHIFT 5 02605 #define MCG_C6_PLLS_MASK 0x40u 02606 #define MCG_C6_PLLS_SHIFT 6 02607 #define MCG_C6_LOLIE0_MASK 0x80u 02608 #define MCG_C6_LOLIE0_SHIFT 7 02609 /* S Bit Fields */ 02610 #define MCG_S_IRCST_MASK 0x1u 02611 #define MCG_S_IRCST_SHIFT 0 02612 #define MCG_S_OSCINIT0_MASK 0x2u 02613 #define MCG_S_OSCINIT0_SHIFT 1 02614 #define MCG_S_CLKST_MASK 0xCu 02615 #define MCG_S_CLKST_SHIFT 2 02616 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK) 02617 #define MCG_S_IREFST_MASK 0x10u 02618 #define MCG_S_IREFST_SHIFT 4 02619 #define MCG_S_PLLST_MASK 0x20u 02620 #define MCG_S_PLLST_SHIFT 5 02621 #define MCG_S_LOCK0_MASK 0x40u 02622 #define MCG_S_LOCK0_SHIFT 6 02623 #define MCG_S_LOLS0_MASK 0x80u 02624 #define MCG_S_LOLS0_SHIFT 7 02625 /* SC Bit Fields */ 02626 #define MCG_SC_LOCS0_MASK 0x1u 02627 #define MCG_SC_LOCS0_SHIFT 0 02628 #define MCG_SC_FCRDIV_MASK 0xEu 02629 #define MCG_SC_FCRDIV_SHIFT 1 02630 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK) 02631 #define MCG_SC_FLTPRSRV_MASK 0x10u 02632 #define MCG_SC_FLTPRSRV_SHIFT 4 02633 #define MCG_SC_ATMF_MASK 0x20u 02634 #define MCG_SC_ATMF_SHIFT 5 02635 #define MCG_SC_ATMS_MASK 0x40u 02636 #define MCG_SC_ATMS_SHIFT 6 02637 #define MCG_SC_ATME_MASK 0x80u 02638 #define MCG_SC_ATME_SHIFT 7 02639 /* ATCVH Bit Fields */ 02640 #define MCG_ATCVH_ATCVH_MASK 0xFFu 02641 #define MCG_ATCVH_ATCVH_SHIFT 0 02642 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK) 02643 /* ATCVL Bit Fields */ 02644 #define MCG_ATCVL_ATCVL_MASK 0xFFu 02645 #define MCG_ATCVL_ATCVL_SHIFT 0 02646 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK) 02647 /* C8 Bit Fields */ 02648 #define MCG_C8_LOLRE_MASK 0x40u 02649 #define MCG_C8_LOLRE_SHIFT 6 02650 02651 /*! 02652 * @} 02653 */ /* end of group MCG_Register_Masks */ 02654 02655 02656 /* MCG - Peripheral instance base addresses */ 02657 /** Peripheral MCG base pointer */ 02658 #define MCG_BASE_PTR ((MCG_MemMapPtr)0x40064000u) 02659 /** Array initializer of MCG peripheral base pointers */ 02660 #define MCG_BASE_PTRS { MCG_BASE_PTR } 02661 02662 /* ---------------------------------------------------------------------------- 02663 -- MCG - Register accessor macros 02664 ---------------------------------------------------------------------------- */ 02665 02666 /*! 02667 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros 02668 * @{ 02669 */ 02670 02671 02672 /* MCG - Register instance definitions */ 02673 /* MCG */ 02674 #define MCG_C1 MCG_C1_REG(MCG_BASE_PTR) 02675 #define MCG_C2 MCG_C2_REG(MCG_BASE_PTR) 02676 #define MCG_C3 MCG_C3_REG(MCG_BASE_PTR) 02677 #define MCG_C4 MCG_C4_REG(MCG_BASE_PTR) 02678 #define MCG_C5 MCG_C5_REG(MCG_BASE_PTR) 02679 #define MCG_C6 MCG_C6_REG(MCG_BASE_PTR) 02680 #define MCG_S MCG_S_REG(MCG_BASE_PTR) 02681 #define MCG_SC MCG_SC_REG(MCG_BASE_PTR) 02682 #define MCG_ATCVH MCG_ATCVH_REG(MCG_BASE_PTR) 02683 #define MCG_ATCVL MCG_ATCVL_REG(MCG_BASE_PTR) 02684 #define MCG_C7 MCG_C7_REG(MCG_BASE_PTR) 02685 #define MCG_C8 MCG_C8_REG(MCG_BASE_PTR) 02686 #define MCG_C9 MCG_C9_REG(MCG_BASE_PTR) 02687 #define MCG_C10 MCG_C10_REG(MCG_BASE_PTR) 02688 02689 /*! 02690 * @} 02691 */ /* end of group MCG_Register_Accessor_Macros */ 02692 02693 02694 /*! 02695 * @} 02696 */ /* end of group MCG_Peripheral */ 02697 02698 02699 /* ---------------------------------------------------------------------------- 02700 -- MCM 02701 ---------------------------------------------------------------------------- */ 02702 02703 /*! 02704 * @addtogroup MCM_Peripheral MCM 02705 * @{ 02706 */ 02707 02708 /** MCM - Peripheral register structure */ 02709 typedef struct MCM_MemMap { 02710 uint8_t RESERVED_0[8]; 02711 uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 02712 uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ 02713 uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ 02714 uint8_t RESERVED_1[48]; 02715 uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ 02716 } volatile *MCM_MemMapPtr; 02717 02718 /* ---------------------------------------------------------------------------- 02719 -- MCM - Register accessor macros 02720 ---------------------------------------------------------------------------- */ 02721 02722 /*! 02723 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros 02724 * @{ 02725 */ 02726 02727 02728 /* MCM - Register accessors */ 02729 #define MCM_PLASC_REG(base) ((base)->PLASC) 02730 #define MCM_PLAMC_REG(base) ((base)->PLAMC) 02731 #define MCM_PLACR_REG(base) ((base)->PLACR) 02732 #define MCM_CPO_REG(base) ((base)->CPO) 02733 02734 /*! 02735 * @} 02736 */ /* end of group MCM_Register_Accessor_Macros */ 02737 02738 02739 /* ---------------------------------------------------------------------------- 02740 -- MCM Register Masks 02741 ---------------------------------------------------------------------------- */ 02742 02743 /*! 02744 * @addtogroup MCM_Register_Masks MCM Register Masks 02745 * @{ 02746 */ 02747 02748 /* PLASC Bit Fields */ 02749 #define MCM_PLASC_ASC_MASK 0xFFu 02750 #define MCM_PLASC_ASC_SHIFT 0 02751 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK) 02752 /* PLAMC Bit Fields */ 02753 #define MCM_PLAMC_AMC_MASK 0xFFu 02754 #define MCM_PLAMC_AMC_SHIFT 0 02755 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK) 02756 /* PLACR Bit Fields */ 02757 #define MCM_PLACR_ARB_MASK 0x200u 02758 #define MCM_PLACR_ARB_SHIFT 9 02759 #define MCM_PLACR_CFCC_MASK 0x400u 02760 #define MCM_PLACR_CFCC_SHIFT 10 02761 #define MCM_PLACR_DFCDA_MASK 0x800u 02762 #define MCM_PLACR_DFCDA_SHIFT 11 02763 #define MCM_PLACR_DFCIC_MASK 0x1000u 02764 #define MCM_PLACR_DFCIC_SHIFT 12 02765 #define MCM_PLACR_DFCC_MASK 0x2000u 02766 #define MCM_PLACR_DFCC_SHIFT 13 02767 #define MCM_PLACR_EFDS_MASK 0x4000u 02768 #define MCM_PLACR_EFDS_SHIFT 14 02769 #define MCM_PLACR_DFCS_MASK 0x8000u 02770 #define MCM_PLACR_DFCS_SHIFT 15 02771 #define MCM_PLACR_ESFC_MASK 0x10000u 02772 #define MCM_PLACR_ESFC_SHIFT 16 02773 /* CPO Bit Fields */ 02774 #define MCM_CPO_CPOREQ_MASK 0x1u 02775 #define MCM_CPO_CPOREQ_SHIFT 0 02776 #define MCM_CPO_CPOACK_MASK 0x2u 02777 #define MCM_CPO_CPOACK_SHIFT 1 02778 #define MCM_CPO_CPOWOI_MASK 0x4u 02779 #define MCM_CPO_CPOWOI_SHIFT 2 02780 02781 /*! 02782 * @} 02783 */ /* end of group MCM_Register_Masks */ 02784 02785 02786 /* MCM - Peripheral instance base addresses */ 02787 /** Peripheral MCM base pointer */ 02788 #define MCM_BASE_PTR ((MCM_MemMapPtr)0xF0003000u) 02789 /** Array initializer of MCM peripheral base pointers */ 02790 #define MCM_BASE_PTRS { MCM_BASE_PTR } 02791 02792 /* ---------------------------------------------------------------------------- 02793 -- MCM - Register accessor macros 02794 ---------------------------------------------------------------------------- */ 02795 02796 /*! 02797 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros 02798 * @{ 02799 */ 02800 02801 02802 /* MCM - Register instance definitions */ 02803 /* MCM */ 02804 #define MCM_PLASC MCM_PLASC_REG(MCM_BASE_PTR) 02805 #define MCM_PLAMC MCM_PLAMC_REG(MCM_BASE_PTR) 02806 #define MCM_PLACR MCM_PLACR_REG(MCM_BASE_PTR) 02807 #define MCM_CPO MCM_CPO_REG(MCM_BASE_PTR) 02808 02809 /*! 02810 * @} 02811 */ /* end of group MCM_Register_Accessor_Macros */ 02812 02813 02814 /*! 02815 * @} 02816 */ /* end of group MCM_Peripheral */ 02817 02818 02819 /* ---------------------------------------------------------------------------- 02820 -- MTB 02821 ---------------------------------------------------------------------------- */ 02822 02823 /*! 02824 * @addtogroup MTB_Peripheral MTB 02825 * @{ 02826 */ 02827 02828 /** MTB - Peripheral register structure */ 02829 typedef struct MTB_MemMap { 02830 uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ 02831 uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ 02832 uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ 02833 uint32_t BASE; /**< MTB Base Register, offset: 0xC */ 02834 uint8_t RESERVED_0[3824]; 02835 uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ 02836 uint8_t RESERVED_1[156]; 02837 uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ 02838 uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ 02839 uint8_t RESERVED_2[8]; 02840 uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ 02841 uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ 02842 uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ 02843 uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ 02844 uint8_t RESERVED_3[8]; 02845 uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 02846 uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 02847 uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */ 02848 uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 02849 } volatile *MTB_MemMapPtr; 02850 02851 /* ---------------------------------------------------------------------------- 02852 -- MTB - Register accessor macros 02853 ---------------------------------------------------------------------------- */ 02854 02855 /*! 02856 * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros 02857 * @{ 02858 */ 02859 02860 02861 /* MTB - Register accessors */ 02862 #define MTB_POSITION_REG(base) ((base)->POSITION) 02863 #define MTB_MASTER_REG(base) ((base)->MASTER) 02864 #define MTB_FLOW_REG(base) ((base)->FLOW) 02865 #define MTB_BASE_REG(base) ((base)->BASE) 02866 #define MTB_MODECTRL_REG(base) ((base)->MODECTRL) 02867 #define MTB_TAGSET_REG(base) ((base)->TAGSET) 02868 #define MTB_TAGCLEAR_REG(base) ((base)->TAGCLEAR) 02869 #define MTB_LOCKACCESS_REG(base) ((base)->LOCKACCESS) 02870 #define MTB_LOCKSTAT_REG(base) ((base)->LOCKSTAT) 02871 #define MTB_AUTHSTAT_REG(base) ((base)->AUTHSTAT) 02872 #define MTB_DEVICEARCH_REG(base) ((base)->DEVICEARCH) 02873 #define MTB_DEVICECFG_REG(base) ((base)->DEVICECFG) 02874 #define MTB_DEVICETYPID_REG(base) ((base)->DEVICETYPID) 02875 #define MTB_PERIPHID_REG(base,index) ((base)->PERIPHID[index]) 02876 #define MTB_COMPID_REG(base,index) ((base)->COMPID[index]) 02877 02878 /*! 02879 * @} 02880 */ /* end of group MTB_Register_Accessor_Macros */ 02881 02882 02883 /* ---------------------------------------------------------------------------- 02884 -- MTB Register Masks 02885 ---------------------------------------------------------------------------- */ 02886 02887 /*! 02888 * @addtogroup MTB_Register_Masks MTB Register Masks 02889 * @{ 02890 */ 02891 02892 /* POSITION Bit Fields */ 02893 #define MTB_POSITION_WRAP_MASK 0x4u 02894 #define MTB_POSITION_WRAP_SHIFT 2 02895 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u 02896 #define MTB_POSITION_POINTER_SHIFT 3 02897 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK) 02898 /* MASTER Bit Fields */ 02899 #define MTB_MASTER_MASK_MASK 0x1Fu 02900 #define MTB_MASTER_MASK_SHIFT 0 02901 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK) 02902 #define MTB_MASTER_TSTARTEN_MASK 0x20u 02903 #define MTB_MASTER_TSTARTEN_SHIFT 5 02904 #define MTB_MASTER_TSTOPEN_MASK 0x40u 02905 #define MTB_MASTER_TSTOPEN_SHIFT 6 02906 #define MTB_MASTER_SFRWPRIV_MASK 0x80u 02907 #define MTB_MASTER_SFRWPRIV_SHIFT 7 02908 #define MTB_MASTER_RAMPRIV_MASK 0x100u 02909 #define MTB_MASTER_RAMPRIV_SHIFT 8 02910 #define MTB_MASTER_HALTREQ_MASK 0x200u 02911 #define MTB_MASTER_HALTREQ_SHIFT 9 02912 #define MTB_MASTER_EN_MASK 0x80000000u 02913 #define MTB_MASTER_EN_SHIFT 31 02914 /* FLOW Bit Fields */ 02915 #define MTB_FLOW_AUTOSTOP_MASK 0x1u 02916 #define MTB_FLOW_AUTOSTOP_SHIFT 0 02917 #define MTB_FLOW_AUTOHALT_MASK 0x2u 02918 #define MTB_FLOW_AUTOHALT_SHIFT 1 02919 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u 02920 #define MTB_FLOW_WATERMARK_SHIFT 3 02921 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK) 02922 /* BASE Bit Fields */ 02923 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu 02924 #define MTB_BASE_BASEADDR_SHIFT 0 02925 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK) 02926 /* MODECTRL Bit Fields */ 02927 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu 02928 #define MTB_MODECTRL_MODECTRL_SHIFT 0 02929 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK) 02930 /* TAGSET Bit Fields */ 02931 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu 02932 #define MTB_TAGSET_TAGSET_SHIFT 0 02933 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK) 02934 /* TAGCLEAR Bit Fields */ 02935 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu 02936 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0 02937 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK) 02938 /* LOCKACCESS Bit Fields */ 02939 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu 02940 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0 02941 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK) 02942 /* LOCKSTAT Bit Fields */ 02943 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu 02944 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0 02945 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK) 02946 /* AUTHSTAT Bit Fields */ 02947 #define MTB_AUTHSTAT_BIT0_MASK 0x1u 02948 #define MTB_AUTHSTAT_BIT0_SHIFT 0 02949 #define MTB_AUTHSTAT_BIT1_MASK 0x2u 02950 #define MTB_AUTHSTAT_BIT1_SHIFT 1 02951 #define MTB_AUTHSTAT_BIT2_MASK 0x4u 02952 #define MTB_AUTHSTAT_BIT2_SHIFT 2 02953 #define MTB_AUTHSTAT_BIT3_MASK 0x8u 02954 #define MTB_AUTHSTAT_BIT3_SHIFT 3 02955 /* DEVICEARCH Bit Fields */ 02956 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu 02957 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0 02958 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK) 02959 /* DEVICECFG Bit Fields */ 02960 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu 02961 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0 02962 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK) 02963 /* DEVICETYPID Bit Fields */ 02964 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu 02965 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0 02966 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK) 02967 /* PERIPHID Bit Fields */ 02968 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu 02969 #define MTB_PERIPHID_PERIPHID_SHIFT 0 02970 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK) 02971 /* COMPID Bit Fields */ 02972 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu 02973 #define MTB_COMPID_COMPID_SHIFT 0 02974 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK) 02975 02976 /*! 02977 * @} 02978 */ /* end of group MTB_Register_Masks */ 02979 02980 02981 /* MTB - Peripheral instance base addresses */ 02982 /** Peripheral MTB base pointer */ 02983 #define MTB_BASE_PTR ((MTB_MemMapPtr)0xF0000000u) 02984 /** Array initializer of MTB peripheral base pointers */ 02985 #define MTB_BASE_PTRS { MTB_BASE_PTR } 02986 02987 /* ---------------------------------------------------------------------------- 02988 -- MTB - Register accessor macros 02989 ---------------------------------------------------------------------------- */ 02990 02991 /*! 02992 * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros 02993 * @{ 02994 */ 02995 02996 02997 /* MTB - Register instance definitions */ 02998 /* MTB */ 02999 #define MTB_POSITION MTB_POSITION_REG(MTB_BASE_PTR) 03000 #define MTB_MASTER MTB_MASTER_REG(MTB_BASE_PTR) 03001 #define MTB_FLOW MTB_FLOW_REG(MTB_BASE_PTR) 03002 //#define MTB_BASE MTB_BASE_REG(MTB_BASE_PTR) 03003 #define MTB_MODECTRL MTB_MODECTRL_REG(MTB_BASE_PTR) 03004 #define MTB_TAGSET MTB_TAGSET_REG(MTB_BASE_PTR) 03005 #define MTB_TAGCLEAR MTB_TAGCLEAR_REG(MTB_BASE_PTR) 03006 #define MTB_LOCKACCESS MTB_LOCKACCESS_REG(MTB_BASE_PTR) 03007 #define MTB_LOCKSTAT MTB_LOCKSTAT_REG(MTB_BASE_PTR) 03008 #define MTB_AUTHSTAT MTB_AUTHSTAT_REG(MTB_BASE_PTR) 03009 #define MTB_DEVICEARCH MTB_DEVICEARCH_REG(MTB_BASE_PTR) 03010 #define MTB_DEVICECFG MTB_DEVICECFG_REG(MTB_BASE_PTR) 03011 #define MTB_DEVICETYPID MTB_DEVICETYPID_REG(MTB_BASE_PTR) 03012 #define MTB_PERIPHID4 MTB_PERIPHID_REG(MTB_BASE_PTR,0) 03013 #define MTB_PERIPHID5 MTB_PERIPHID_REG(MTB_BASE_PTR,1) 03014 #define MTB_PERIPHID6 MTB_PERIPHID_REG(MTB_BASE_PTR,2) 03015 #define MTB_PERIPHID7 MTB_PERIPHID_REG(MTB_BASE_PTR,3) 03016 #define MTB_PERIPHID0 MTB_PERIPHID_REG(MTB_BASE_PTR,4) 03017 #define MTB_PERIPHID1 MTB_PERIPHID_REG(MTB_BASE_PTR,5) 03018 #define MTB_PERIPHID2 MTB_PERIPHID_REG(MTB_BASE_PTR,6) 03019 #define MTB_PERIPHID3 MTB_PERIPHID_REG(MTB_BASE_PTR,7) 03020 #define MTB_COMPID0 MTB_COMPID_REG(MTB_BASE_PTR,0) 03021 #define MTB_COMPID1 MTB_COMPID_REG(MTB_BASE_PTR,1) 03022 #define MTB_COMPID2 MTB_COMPID_REG(MTB_BASE_PTR,2) 03023 #define MTB_COMPID3 MTB_COMPID_REG(MTB_BASE_PTR,3) 03024 03025 /* MTB - Register array accessors */ 03026 #define MTB_PERIPHID(index) MTB_PERIPHID_REG(MTB_BASE_PTR,index) 03027 #define MTB_COMPID(index) MTB_COMPID_REG(MTB_BASE_PTR,index) 03028 03029 /*! 03030 * @} 03031 */ /* end of group MTB_Register_Accessor_Macros */ 03032 03033 03034 /*! 03035 * @} 03036 */ /* end of group MTB_Peripheral */ 03037 03038 03039 /* ---------------------------------------------------------------------------- 03040 -- MTBDWT 03041 ---------------------------------------------------------------------------- */ 03042 03043 /*! 03044 * @addtogroup MTBDWT_Peripheral MTBDWT 03045 * @{ 03046 */ 03047 03048 /** MTBDWT - Peripheral register structure */ 03049 typedef struct MTBDWT_MemMap { 03050 uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ 03051 uint8_t RESERVED_0[28]; 03052 struct { /* offset: 0x20, array step: 0x10 */ 03053 uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ 03054 uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ 03055 uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ 03056 uint8_t RESERVED_0[4]; 03057 } COMPARATOR[2]; 03058 uint8_t RESERVED_1[448]; 03059 uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ 03060 uint8_t RESERVED_2[3524]; 03061 uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 03062 uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 03063 uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */ 03064 uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 03065 } volatile *MTBDWT_MemMapPtr; 03066 03067 /* ---------------------------------------------------------------------------- 03068 -- MTBDWT - Register accessor macros 03069 ---------------------------------------------------------------------------- */ 03070 03071 /*! 03072 * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros 03073 * @{ 03074 */ 03075 03076 03077 /* MTBDWT - Register accessors */ 03078 #define MTBDWT_CTRL_REG(base) ((base)->CTRL) 03079 #define MTBDWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP) 03080 #define MTBDWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK) 03081 #define MTBDWT_FCT_REG(base,index) ((base)->COMPARATOR[index].FCT) 03082 #define MTBDWT_TBCTRL_REG(base) ((base)->TBCTRL) 03083 #define MTBDWT_DEVICECFG_REG(base) ((base)->DEVICECFG) 03084 #define MTBDWT_DEVICETYPID_REG(base) ((base)->DEVICETYPID) 03085 #define MTBDWT_PERIPHID_REG(base,index) ((base)->PERIPHID[index]) 03086 #define MTBDWT_COMPID_REG(base,index) ((base)->COMPID[index]) 03087 03088 /*! 03089 * @} 03090 */ /* end of group MTBDWT_Register_Accessor_Macros */ 03091 03092 03093 /* ---------------------------------------------------------------------------- 03094 -- MTBDWT Register Masks 03095 ---------------------------------------------------------------------------- */ 03096 03097 /*! 03098 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks 03099 * @{ 03100 */ 03101 03102 /* CTRL Bit Fields */ 03103 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu 03104 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0 03105 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK) 03106 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u 03107 #define MTBDWT_CTRL_NUMCMP_SHIFT 28 03108 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK) 03109 /* COMP Bit Fields */ 03110 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu 03111 #define MTBDWT_COMP_COMP_SHIFT 0 03112 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK) 03113 /* MASK Bit Fields */ 03114 #define MTBDWT_MASK_MASK_MASK 0x1Fu 03115 #define MTBDWT_MASK_MASK_SHIFT 0 03116 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK) 03117 /* FCT Bit Fields */ 03118 #define MTBDWT_FCT_FUNCTION_MASK 0xFu 03119 #define MTBDWT_FCT_FUNCTION_SHIFT 0 03120 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK) 03121 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u 03122 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8 03123 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u 03124 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10 03125 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK) 03126 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u 03127 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12 03128 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK) 03129 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u 03130 #define MTBDWT_FCT_MATCHED_SHIFT 24 03131 /* TBCTRL Bit Fields */ 03132 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u 03133 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0 03134 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u 03135 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1 03136 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u 03137 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28 03138 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK) 03139 /* DEVICECFG Bit Fields */ 03140 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu 03141 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0 03142 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK) 03143 /* DEVICETYPID Bit Fields */ 03144 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu 03145 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0 03146 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK) 03147 /* PERIPHID Bit Fields */ 03148 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu 03149 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0 03150 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK) 03151 /* COMPID Bit Fields */ 03152 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu 03153 #define MTBDWT_COMPID_COMPID_SHIFT 0 03154 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK) 03155 03156 /*! 03157 * @} 03158 */ /* end of group MTBDWT_Register_Masks */ 03159 03160 03161 /* MTBDWT - Peripheral instance base addresses */ 03162 /** Peripheral MTBDWT base pointer */ 03163 #define MTBDWT_BASE_PTR ((MTBDWT_MemMapPtr)0xF0001000u) 03164 /** Array initializer of MTBDWT peripheral base pointers */ 03165 #define MTBDWT_BASE_PTRS { MTBDWT_BASE_PTR } 03166 03167 /* ---------------------------------------------------------------------------- 03168 -- MTBDWT - Register accessor macros 03169 ---------------------------------------------------------------------------- */ 03170 03171 /*! 03172 * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros 03173 * @{ 03174 */ 03175 03176 03177 /* MTBDWT - Register instance definitions */ 03178 /* MTBDWT */ 03179 #define MTBDWT_CTRL MTBDWT_CTRL_REG(MTBDWT_BASE_PTR) 03180 #define MTBDWT_COMP0 MTBDWT_COMP_REG(MTBDWT_BASE_PTR,0) 03181 #define MTBDWT_MASK0 MTBDWT_MASK_REG(MTBDWT_BASE_PTR,0) 03182 #define MTBDWT_FCT0 MTBDWT_FCT_REG(MTBDWT_BASE_PTR,0) 03183 #define MTBDWT_COMP1 MTBDWT_COMP_REG(MTBDWT_BASE_PTR,1) 03184 #define MTBDWT_MASK1 MTBDWT_MASK_REG(MTBDWT_BASE_PTR,1) 03185 #define MTBDWT_FCT1 MTBDWT_FCT_REG(MTBDWT_BASE_PTR,1) 03186 #define MTBDWT_TBCTRL MTBDWT_TBCTRL_REG(MTBDWT_BASE_PTR) 03187 #define MTBDWT_DEVICECFG MTBDWT_DEVICECFG_REG(MTBDWT_BASE_PTR) 03188 #define MTBDWT_DEVICETYPID MTBDWT_DEVICETYPID_REG(MTBDWT_BASE_PTR) 03189 #define MTBDWT_PERIPHID4 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,0) 03190 #define MTBDWT_PERIPHID5 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,1) 03191 #define MTBDWT_PERIPHID6 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,2) 03192 #define MTBDWT_PERIPHID7 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,3) 03193 #define MTBDWT_PERIPHID0 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,4) 03194 #define MTBDWT_PERIPHID1 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,5) 03195 #define MTBDWT_PERIPHID2 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,6) 03196 #define MTBDWT_PERIPHID3 MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,7) 03197 #define MTBDWT_COMPID0 MTBDWT_COMPID_REG(MTBDWT_BASE_PTR,0) 03198 #define MTBDWT_COMPID1 MTBDWT_COMPID_REG(MTBDWT_BASE_PTR,1) 03199 #define MTBDWT_COMPID2 MTBDWT_COMPID_REG(MTBDWT_BASE_PTR,2) 03200 #define MTBDWT_COMPID3 MTBDWT_COMPID_REG(MTBDWT_BASE_PTR,3) 03201 03202 /* MTBDWT - Register array accessors */ 03203 #define MTBDWT_COMP(index) MTBDWT_COMP_REG(MTBDWT_BASE_PTR,index) 03204 #define MTBDWT_MASK(index) MTBDWT_MASK_REG(MTBDWT_BASE_PTR,index) 03205 #define MTBDWT_FCT(index) MTBDWT_FCT_REG(MTBDWT_BASE_PTR,index) 03206 #define MTBDWT_PERIPHID(index) MTBDWT_PERIPHID_REG(MTBDWT_BASE_PTR,index) 03207 #define MTBDWT_COMPID(index) MTBDWT_COMPID_REG(MTBDWT_BASE_PTR,index) 03208 03209 /*! 03210 * @} 03211 */ /* end of group MTBDWT_Register_Accessor_Macros */ 03212 03213 03214 /*! 03215 * @} 03216 */ /* end of group MTBDWT_Peripheral */ 03217 03218 03219 /* ---------------------------------------------------------------------------- 03220 -- NV 03221 ---------------------------------------------------------------------------- */ 03222 03223 /*! 03224 * @addtogroup NV_Peripheral NV 03225 * @{ 03226 */ 03227 03228 /** NV - Peripheral register structure */ 03229 typedef struct NV_MemMap { 03230 uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ 03231 uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ 03232 uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ 03233 uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ 03234 uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ 03235 uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ 03236 uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ 03237 uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ 03238 uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ 03239 uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ 03240 uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ 03241 uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ 03242 uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ 03243 uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ 03244 } volatile *NV_MemMapPtr; 03245 03246 /* ---------------------------------------------------------------------------- 03247 -- NV - Register accessor macros 03248 ---------------------------------------------------------------------------- */ 03249 03250 /*! 03251 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros 03252 * @{ 03253 */ 03254 03255 03256 /* NV - Register accessors */ 03257 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3) 03258 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) 03259 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) 03260 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) 03261 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) 03262 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) 03263 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) 03264 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) 03265 #define NV_FPROT3_REG(base) ((base)->FPROT3) 03266 #define NV_FPROT2_REG(base) ((base)->FPROT2) 03267 #define NV_FPROT1_REG(base) ((base)->FPROT1) 03268 #define NV_FPROT0_REG(base) ((base)->FPROT0) 03269 #define NV_FSEC_REG(base) ((base)->FSEC) 03270 #define NV_FOPT_REG(base) ((base)->FOPT) 03271 03272 /*! 03273 * @} 03274 */ /* end of group NV_Register_Accessor_Macros */ 03275 03276 03277 /* ---------------------------------------------------------------------------- 03278 -- NV Register Masks 03279 ---------------------------------------------------------------------------- */ 03280 03281 /*! 03282 * @addtogroup NV_Register_Masks NV Register Masks 03283 * @{ 03284 */ 03285 03286 /* BACKKEY3 Bit Fields */ 03287 #define NV_BACKKEY3_KEY_MASK 0xFFu 03288 #define NV_BACKKEY3_KEY_SHIFT 0 03289 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK) 03290 /* BACKKEY2 Bit Fields */ 03291 #define NV_BACKKEY2_KEY_MASK 0xFFu 03292 #define NV_BACKKEY2_KEY_SHIFT 0 03293 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK) 03294 /* BACKKEY1 Bit Fields */ 03295 #define NV_BACKKEY1_KEY_MASK 0xFFu 03296 #define NV_BACKKEY1_KEY_SHIFT 0 03297 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK) 03298 /* BACKKEY0 Bit Fields */ 03299 #define NV_BACKKEY0_KEY_MASK 0xFFu 03300 #define NV_BACKKEY0_KEY_SHIFT 0 03301 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK) 03302 /* BACKKEY7 Bit Fields */ 03303 #define NV_BACKKEY7_KEY_MASK 0xFFu 03304 #define NV_BACKKEY7_KEY_SHIFT 0 03305 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK) 03306 /* BACKKEY6 Bit Fields */ 03307 #define NV_BACKKEY6_KEY_MASK 0xFFu 03308 #define NV_BACKKEY6_KEY_SHIFT 0 03309 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK) 03310 /* BACKKEY5 Bit Fields */ 03311 #define NV_BACKKEY5_KEY_MASK 0xFFu 03312 #define NV_BACKKEY5_KEY_SHIFT 0 03313 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK) 03314 /* BACKKEY4 Bit Fields */ 03315 #define NV_BACKKEY4_KEY_MASK 0xFFu 03316 #define NV_BACKKEY4_KEY_SHIFT 0 03317 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK) 03318 /* FPROT3 Bit Fields */ 03319 #define NV_FPROT3_PROT_MASK 0xFFu 03320 #define NV_FPROT3_PROT_SHIFT 0 03321 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK) 03322 /* FPROT2 Bit Fields */ 03323 #define NV_FPROT2_PROT_MASK 0xFFu 03324 #define NV_FPROT2_PROT_SHIFT 0 03325 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK) 03326 /* FPROT1 Bit Fields */ 03327 #define NV_FPROT1_PROT_MASK 0xFFu 03328 #define NV_FPROT1_PROT_SHIFT 0 03329 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK) 03330 /* FPROT0 Bit Fields */ 03331 #define NV_FPROT0_PROT_MASK 0xFFu 03332 #define NV_FPROT0_PROT_SHIFT 0 03333 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK) 03334 /* FSEC Bit Fields */ 03335 #define NV_FSEC_SEC_MASK 0x3u 03336 #define NV_FSEC_SEC_SHIFT 0 03337 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK) 03338 #define NV_FSEC_FSLACC_MASK 0xCu 03339 #define NV_FSEC_FSLACC_SHIFT 2 03340 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK) 03341 #define NV_FSEC_MEEN_MASK 0x30u 03342 #define NV_FSEC_MEEN_SHIFT 4 03343 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK) 03344 #define NV_FSEC_KEYEN_MASK 0xC0u 03345 #define NV_FSEC_KEYEN_SHIFT 6 03346 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK) 03347 /* FOPT Bit Fields */ 03348 #define NV_FOPT_LPBOOT0_MASK 0x1u 03349 #define NV_FOPT_LPBOOT0_SHIFT 0 03350 #define NV_FOPT_NMI_DIS_MASK 0x4u 03351 #define NV_FOPT_NMI_DIS_SHIFT 2 03352 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u 03353 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3 03354 #define NV_FOPT_LPBOOT1_MASK 0x10u 03355 #define NV_FOPT_LPBOOT1_SHIFT 4 03356 #define NV_FOPT_FAST_INIT_MASK 0x20u 03357 #define NV_FOPT_FAST_INIT_SHIFT 5 03358 03359 /*! 03360 * @} 03361 */ /* end of group NV_Register_Masks */ 03362 03363 03364 /* NV - Peripheral instance base addresses */ 03365 /** Peripheral FTFA_FlashConfig base pointer */ 03366 #define FTFA_FlashConfig_BASE_PTR ((NV_MemMapPtr)0x400u) 03367 /** Array initializer of NV peripheral base pointers */ 03368 #define NV_BASE_PTRS { FTFA_FlashConfig_BASE_PTR } 03369 03370 /* ---------------------------------------------------------------------------- 03371 -- NV - Register accessor macros 03372 ---------------------------------------------------------------------------- */ 03373 03374 /*! 03375 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros 03376 * @{ 03377 */ 03378 03379 03380 /* NV - Register instance definitions */ 03381 /* FTFA_FlashConfig */ 03382 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig_BASE_PTR) 03383 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig_BASE_PTR) 03384 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig_BASE_PTR) 03385 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig_BASE_PTR) 03386 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig_BASE_PTR) 03387 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig_BASE_PTR) 03388 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig_BASE_PTR) 03389 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig_BASE_PTR) 03390 #define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig_BASE_PTR) 03391 #define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig_BASE_PTR) 03392 #define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig_BASE_PTR) 03393 #define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig_BASE_PTR) 03394 #define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig_BASE_PTR) 03395 #define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig_BASE_PTR) 03396 03397 /*! 03398 * @} 03399 */ /* end of group NV_Register_Accessor_Macros */ 03400 03401 03402 /*! 03403 * @} 03404 */ /* end of group NV_Peripheral */ 03405 03406 03407 /* ---------------------------------------------------------------------------- 03408 -- NVIC 03409 ---------------------------------------------------------------------------- */ 03410 03411 /*! 03412 * @addtogroup NVIC_Peripheral NVIC 03413 * @{ 03414 */ 03415 03416 /** NVIC - Peripheral register structure */ 03417 typedef struct NVIC_MemMap { 03418 uint32_t ISER; /**< Interrupt Set Enable Register, offset: 0x0 */ 03419 uint8_t RESERVED_0[124]; 03420 uint32_t ICER; /**< Interrupt Clear Enable Register, offset: 0x80 */ 03421 uint8_t RESERVED_1[124]; 03422 uint32_t ISPR; /**< Interrupt Set Pending Register, offset: 0x100 */ 03423 uint8_t RESERVED_2[124]; 03424 uint32_t ICPR; /**< Interrupt Clear Pending Register, offset: 0x180 */ 03425 uint8_t RESERVED_3[380]; 03426 uint32_t IP[8]; /**< Interrupt Priority Register n, array offset: 0x300, array step: 0x4 */ 03427 } volatile *NVIC_MemMapPtr; 03428 03429 /* ---------------------------------------------------------------------------- 03430 -- NVIC - Register accessor macros 03431 ---------------------------------------------------------------------------- */ 03432 03433 /*! 03434 * @addtogroup NVIC_Register_Accessor_Macros NVIC - Register accessor macros 03435 * @{ 03436 */ 03437 03438 03439 /* NVIC - Register accessors */ 03440 #define NVIC_ISER_REG(base) ((base)->ISER) 03441 #define NVIC_ICER_REG(base) ((base)->ICER) 03442 #define NVIC_ISPR_REG(base) ((base)->ISPR) 03443 #define NVIC_ICPR_REG(base) ((base)->ICPR) 03444 #define NVIC_IP_REG(base,index) ((base)->IP[index]) 03445 03446 /*! 03447 * @} 03448 */ /* end of group NVIC_Register_Accessor_Macros */ 03449 03450 03451 /* ---------------------------------------------------------------------------- 03452 -- NVIC Register Masks 03453 ---------------------------------------------------------------------------- */ 03454 03455 /*! 03456 * @addtogroup NVIC_Register_Masks NVIC Register Masks 03457 * @{ 03458 */ 03459 03460 /* ISER Bit Fields */ 03461 #define NVIC_ISER_SETENA_MASK 0xFFFFFFFFu 03462 #define NVIC_ISER_SETENA_SHIFT 0 03463 #define NVIC_ISER_SETENA(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ISER_SETENA_SHIFT))&NVIC_ISER_SETENA_MASK) 03464 /* ICER Bit Fields */ 03465 #define NVIC_ICER_CLRENA_MASK 0xFFFFFFFFu 03466 #define NVIC_ICER_CLRENA_SHIFT 0 03467 #define NVIC_ICER_CLRENA(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ICER_CLRENA_SHIFT))&NVIC_ICER_CLRENA_MASK) 03468 /* ISPR Bit Fields */ 03469 #define NVIC_ISPR_SETPEND_MASK 0xFFFFFFFFu 03470 #define NVIC_ISPR_SETPEND_SHIFT 0 03471 #define NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ISPR_SETPEND_SHIFT))&NVIC_ISPR_SETPEND_MASK) 03472 /* ICPR Bit Fields */ 03473 #define NVIC_ICPR_CLRPEND_MASK 0xFFFFFFFFu 03474 #define NVIC_ICPR_CLRPEND_SHIFT 0 03475 #define NVIC_ICPR_CLRPEND(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ICPR_CLRPEND_SHIFT))&NVIC_ICPR_CLRPEND_MASK) 03476 /* IP Bit Fields */ 03477 #define NVIC_IP_PRI_0_MASK 0xFFu 03478 #define NVIC_IP_PRI_0_SHIFT 0 03479 #define NVIC_IP_PRI_0(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_0_SHIFT))&NVIC_IP_PRI_0_MASK) 03480 #define NVIC_IP_PRI_28_MASK 0xFFu 03481 #define NVIC_IP_PRI_28_SHIFT 0 03482 #define NVIC_IP_PRI_28(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_28_SHIFT))&NVIC_IP_PRI_28_MASK) 03483 #define NVIC_IP_PRI_24_MASK 0xFFu 03484 #define NVIC_IP_PRI_24_SHIFT 0 03485 #define NVIC_IP_PRI_24(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_24_SHIFT))&NVIC_IP_PRI_24_MASK) 03486 #define NVIC_IP_PRI_20_MASK 0xFFu 03487 #define NVIC_IP_PRI_20_SHIFT 0 03488 #define NVIC_IP_PRI_20(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_20_SHIFT))&NVIC_IP_PRI_20_MASK) 03489 #define NVIC_IP_PRI_4_MASK 0xFFu 03490 #define NVIC_IP_PRI_4_SHIFT 0 03491 #define NVIC_IP_PRI_4(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_4_SHIFT))&NVIC_IP_PRI_4_MASK) 03492 #define NVIC_IP_PRI_16_MASK 0xFFu 03493 #define NVIC_IP_PRI_16_SHIFT 0 03494 #define NVIC_IP_PRI_16(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_16_SHIFT))&NVIC_IP_PRI_16_MASK) 03495 #define NVIC_IP_PRI_12_MASK 0xFFu 03496 #define NVIC_IP_PRI_12_SHIFT 0 03497 #define NVIC_IP_PRI_12(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_12_SHIFT))&NVIC_IP_PRI_12_MASK) 03498 #define NVIC_IP_PRI_8_MASK 0xFFu 03499 #define NVIC_IP_PRI_8_SHIFT 0 03500 #define NVIC_IP_PRI_8(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_8_SHIFT))&NVIC_IP_PRI_8_MASK) 03501 #define NVIC_IP_PRI_13_MASK 0xFF00u 03502 #define NVIC_IP_PRI_13_SHIFT 8 03503 #define NVIC_IP_PRI_13(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_13_SHIFT))&NVIC_IP_PRI_13_MASK) 03504 #define NVIC_IP_PRI_21_MASK 0xFF00u 03505 #define NVIC_IP_PRI_21_SHIFT 8 03506 #define NVIC_IP_PRI_21(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_21_SHIFT))&NVIC_IP_PRI_21_MASK) 03507 #define NVIC_IP_PRI_29_MASK 0xFF00u 03508 #define NVIC_IP_PRI_29_SHIFT 8 03509 #define NVIC_IP_PRI_29(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_29_SHIFT))&NVIC_IP_PRI_29_MASK) 03510 #define NVIC_IP_PRI_1_MASK 0xFF00u 03511 #define NVIC_IP_PRI_1_SHIFT 8 03512 #define NVIC_IP_PRI_1(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_1_SHIFT))&NVIC_IP_PRI_1_MASK) 03513 #define NVIC_IP_PRI_9_MASK 0xFF00u 03514 #define NVIC_IP_PRI_9_SHIFT 8 03515 #define NVIC_IP_PRI_9(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_9_SHIFT))&NVIC_IP_PRI_9_MASK) 03516 #define NVIC_IP_PRI_17_MASK 0xFF00u 03517 #define NVIC_IP_PRI_17_SHIFT 8 03518 #define NVIC_IP_PRI_17(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_17_SHIFT))&NVIC_IP_PRI_17_MASK) 03519 #define NVIC_IP_PRI_25_MASK 0xFF00u 03520 #define NVIC_IP_PRI_25_SHIFT 8 03521 #define NVIC_IP_PRI_25(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_25_SHIFT))&NVIC_IP_PRI_25_MASK) 03522 #define NVIC_IP_PRI_5_MASK 0xFF00u 03523 #define NVIC_IP_PRI_5_SHIFT 8 03524 #define NVIC_IP_PRI_5(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_5_SHIFT))&NVIC_IP_PRI_5_MASK) 03525 #define NVIC_IP_PRI_2_MASK 0xFF0000u 03526 #define NVIC_IP_PRI_2_SHIFT 16 03527 #define NVIC_IP_PRI_2(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_2_SHIFT))&NVIC_IP_PRI_2_MASK) 03528 #define NVIC_IP_PRI_26_MASK 0xFF0000u 03529 #define NVIC_IP_PRI_26_SHIFT 16 03530 #define NVIC_IP_PRI_26(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_26_SHIFT))&NVIC_IP_PRI_26_MASK) 03531 #define NVIC_IP_PRI_18_MASK 0xFF0000u 03532 #define NVIC_IP_PRI_18_SHIFT 16 03533 #define NVIC_IP_PRI_18(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_18_SHIFT))&NVIC_IP_PRI_18_MASK) 03534 #define NVIC_IP_PRI_14_MASK 0xFF0000u 03535 #define NVIC_IP_PRI_14_SHIFT 16 03536 #define NVIC_IP_PRI_14(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_14_SHIFT))&NVIC_IP_PRI_14_MASK) 03537 #define NVIC_IP_PRI_6_MASK 0xFF0000u 03538 #define NVIC_IP_PRI_6_SHIFT 16 03539 #define NVIC_IP_PRI_6(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_6_SHIFT))&NVIC_IP_PRI_6_MASK) 03540 #define NVIC_IP_PRI_30_MASK 0xFF0000u 03541 #define NVIC_IP_PRI_30_SHIFT 16 03542 #define NVIC_IP_PRI_30(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_30_SHIFT))&NVIC_IP_PRI_30_MASK) 03543 #define NVIC_IP_PRI_22_MASK 0xFF0000u 03544 #define NVIC_IP_PRI_22_SHIFT 16 03545 #define NVIC_IP_PRI_22(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_22_SHIFT))&NVIC_IP_PRI_22_MASK) 03546 #define NVIC_IP_PRI_10_MASK 0xFF0000u 03547 #define NVIC_IP_PRI_10_SHIFT 16 03548 #define NVIC_IP_PRI_10(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_10_SHIFT))&NVIC_IP_PRI_10_MASK) 03549 #define NVIC_IP_PRI_31_MASK 0xFF000000u 03550 #define NVIC_IP_PRI_31_SHIFT 24 03551 #define NVIC_IP_PRI_31(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_31_SHIFT))&NVIC_IP_PRI_31_MASK) 03552 #define NVIC_IP_PRI_27_MASK 0xFF000000u 03553 #define NVIC_IP_PRI_27_SHIFT 24 03554 #define NVIC_IP_PRI_27(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_27_SHIFT))&NVIC_IP_PRI_27_MASK) 03555 #define NVIC_IP_PRI_23_MASK 0xFF000000u 03556 #define NVIC_IP_PRI_23_SHIFT 24 03557 #define NVIC_IP_PRI_23(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_23_SHIFT))&NVIC_IP_PRI_23_MASK) 03558 #define NVIC_IP_PRI_3_MASK 0xFF000000u 03559 #define NVIC_IP_PRI_3_SHIFT 24 03560 #define NVIC_IP_PRI_3(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_3_SHIFT))&NVIC_IP_PRI_3_MASK) 03561 #define NVIC_IP_PRI_19_MASK 0xFF000000u 03562 #define NVIC_IP_PRI_19_SHIFT 24 03563 #define NVIC_IP_PRI_19(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_19_SHIFT))&NVIC_IP_PRI_19_MASK) 03564 #define NVIC_IP_PRI_15_MASK 0xFF000000u 03565 #define NVIC_IP_PRI_15_SHIFT 24 03566 #define NVIC_IP_PRI_15(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_15_SHIFT))&NVIC_IP_PRI_15_MASK) 03567 #define NVIC_IP_PRI_11_MASK 0xFF000000u 03568 #define NVIC_IP_PRI_11_SHIFT 24 03569 #define NVIC_IP_PRI_11(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_11_SHIFT))&NVIC_IP_PRI_11_MASK) 03570 #define NVIC_IP_PRI_7_MASK 0xFF000000u 03571 #define NVIC_IP_PRI_7_SHIFT 24 03572 #define NVIC_IP_PRI_7(x) (((uint32_t)(((uint32_t)(x))<<NVIC_IP_PRI_7_SHIFT))&NVIC_IP_PRI_7_MASK) 03573 03574 /*! 03575 * @} 03576 */ /* end of group NVIC_Register_Masks */ 03577 03578 03579 /* NVIC - Peripheral instance base addresses */ 03580 /** Peripheral NVIC base pointer */ 03581 #define NVIC_BASE_PTR ((NVIC_MemMapPtr)0xE000E100u) 03582 /** Array initializer of NVIC peripheral base pointers */ 03583 #define NVIC_BASE_PTRS { NVIC_BASE_PTR } 03584 03585 /* ---------------------------------------------------------------------------- 03586 -- NVIC - Register accessor macros 03587 ---------------------------------------------------------------------------- */ 03588 03589 /*! 03590 * @addtogroup NVIC_Register_Accessor_Macros NVIC - Register accessor macros 03591 * @{ 03592 */ 03593 03594 03595 /* NVIC - Register instance definitions */ 03596 /* NVIC */ 03597 #define NVIC_ISER NVIC_ISER_REG(NVIC_BASE_PTR) 03598 #define NVIC_ICER NVIC_ICER_REG(NVIC_BASE_PTR) 03599 #define NVIC_ISPR NVIC_ISPR_REG(NVIC_BASE_PTR) 03600 #define NVIC_ICPR NVIC_ICPR_REG(NVIC_BASE_PTR) 03601 #define NVIC_IPR0 NVIC_IP_REG(NVIC_BASE_PTR,0) 03602 #define NVIC_IPR1 NVIC_IP_REG(NVIC_BASE_PTR,1) 03603 #define NVIC_IPR2 NVIC_IP_REG(NVIC_BASE_PTR,2) 03604 #define NVIC_IPR3 NVIC_IP_REG(NVIC_BASE_PTR,3) 03605 #define NVIC_IPR4 NVIC_IP_REG(NVIC_BASE_PTR,4) 03606 #define NVIC_IPR5 NVIC_IP_REG(NVIC_BASE_PTR,5) 03607 #define NVIC_IPR6 NVIC_IP_REG(NVIC_BASE_PTR,6) 03608 #define NVIC_IPR7 NVIC_IP_REG(NVIC_BASE_PTR,7) 03609 03610 /* NVIC - Register array accessors */ 03611 #define NVIC_IP(index) NVIC_IP_REG(NVIC_BASE_PTR,index) 03612 03613 /*! 03614 * @} 03615 */ /* end of group NVIC_Register_Accessor_Macros */ 03616 03617 03618 /*! 03619 * @} 03620 */ /* end of group NVIC_Peripheral */ 03621 03622 03623 /* ---------------------------------------------------------------------------- 03624 -- OSC 03625 ---------------------------------------------------------------------------- */ 03626 03627 /*! 03628 * @addtogroup OSC_Peripheral OSC 03629 * @{ 03630 */ 03631 03632 /** OSC - Peripheral register structure */ 03633 typedef struct OSC_MemMap { 03634 uint8_t CR; /**< OSC Control Register, offset: 0x0 */ 03635 } volatile *OSC_MemMapPtr; 03636 03637 /* ---------------------------------------------------------------------------- 03638 -- OSC - Register accessor macros 03639 ---------------------------------------------------------------------------- */ 03640 03641 /*! 03642 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros 03643 * @{ 03644 */ 03645 03646 03647 /* OSC - Register accessors */ 03648 #define OSC_CR_REG(base) ((base)->CR) 03649 03650 /*! 03651 * @} 03652 */ /* end of group OSC_Register_Accessor_Macros */ 03653 03654 03655 /* ---------------------------------------------------------------------------- 03656 -- OSC Register Masks 03657 ---------------------------------------------------------------------------- */ 03658 03659 /*! 03660 * @addtogroup OSC_Register_Masks OSC Register Masks 03661 * @{ 03662 */ 03663 03664 /* CR Bit Fields */ 03665 #define OSC_CR_SC16P_MASK 0x1u 03666 #define OSC_CR_SC16P_SHIFT 0 03667 #define OSC_CR_SC8P_MASK 0x2u 03668 #define OSC_CR_SC8P_SHIFT 1 03669 #define OSC_CR_SC4P_MASK 0x4u 03670 #define OSC_CR_SC4P_SHIFT 2 03671 #define OSC_CR_SC2P_MASK 0x8u 03672 #define OSC_CR_SC2P_SHIFT 3 03673 #define OSC_CR_EREFSTEN_MASK 0x20u 03674 #define OSC_CR_EREFSTEN_SHIFT 5 03675 #define OSC_CR_ERCLKEN_MASK 0x80u 03676 #define OSC_CR_ERCLKEN_SHIFT 7 03677 03678 /*! 03679 * @} 03680 */ /* end of group OSC_Register_Masks */ 03681 03682 03683 /* OSC - Peripheral instance base addresses */ 03684 /** Peripheral OSC0 base pointer */ 03685 #define OSC0_BASE_PTR ((OSC_MemMapPtr)0x40065000u) 03686 /** Array initializer of OSC peripheral base pointers */ 03687 #define OSC_BASE_PTRS { OSC0_BASE_PTR } 03688 03689 /* ---------------------------------------------------------------------------- 03690 -- OSC - Register accessor macros 03691 ---------------------------------------------------------------------------- */ 03692 03693 /*! 03694 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros 03695 * @{ 03696 */ 03697 03698 03699 /* OSC - Register instance definitions */ 03700 /* OSC0 */ 03701 #define OSC0_CR OSC_CR_REG(OSC0_BASE_PTR) 03702 03703 /*! 03704 * @} 03705 */ /* end of group OSC_Register_Accessor_Macros */ 03706 03707 03708 /*! 03709 * @} 03710 */ /* end of group OSC_Peripheral */ 03711 03712 03713 /* ---------------------------------------------------------------------------- 03714 -- PIT 03715 ---------------------------------------------------------------------------- */ 03716 03717 /*! 03718 * @addtogroup PIT_Peripheral PIT 03719 * @{ 03720 */ 03721 03722 /** PIT - Peripheral register structure */ 03723 typedef struct PIT_MemMap { 03724 uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ 03725 uint8_t RESERVED_0[220]; 03726 uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ 03727 uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ 03728 uint8_t RESERVED_1[24]; 03729 struct { /* offset: 0x100, array step: 0x10 */ 03730 uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ 03731 uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ 03732 uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ 03733 uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ 03734 } CHANNEL[2]; 03735 } volatile *PIT_MemMapPtr; 03736 03737 /* ---------------------------------------------------------------------------- 03738 -- PIT - Register accessor macros 03739 ---------------------------------------------------------------------------- */ 03740 03741 /*! 03742 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros 03743 * @{ 03744 */ 03745 03746 03747 /* PIT - Register accessors */ 03748 #define PIT_MCR_REG(base) ((base)->MCR) 03749 #define PIT_LTMR64H_REG(base) ((base)->LTMR64H) 03750 #define PIT_LTMR64L_REG(base) ((base)->LTMR64L) 03751 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) 03752 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) 03753 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) 03754 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) 03755 03756 /*! 03757 * @} 03758 */ /* end of group PIT_Register_Accessor_Macros */ 03759 03760 03761 /* ---------------------------------------------------------------------------- 03762 -- PIT Register Masks 03763 ---------------------------------------------------------------------------- */ 03764 03765 /*! 03766 * @addtogroup PIT_Register_Masks PIT Register Masks 03767 * @{ 03768 */ 03769 03770 /* MCR Bit Fields */ 03771 #define PIT_MCR_FRZ_MASK 0x1u 03772 #define PIT_MCR_FRZ_SHIFT 0 03773 #define PIT_MCR_MDIS_MASK 0x2u 03774 #define PIT_MCR_MDIS_SHIFT 1 03775 /* LTMR64H Bit Fields */ 03776 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu 03777 #define PIT_LTMR64H_LTH_SHIFT 0 03778 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK) 03779 /* LTMR64L Bit Fields */ 03780 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu 03781 #define PIT_LTMR64L_LTL_SHIFT 0 03782 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK) 03783 /* LDVAL Bit Fields */ 03784 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu 03785 #define PIT_LDVAL_TSV_SHIFT 0 03786 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK) 03787 /* CVAL Bit Fields */ 03788 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu 03789 #define PIT_CVAL_TVL_SHIFT 0 03790 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK) 03791 /* TCTRL Bit Fields */ 03792 #define PIT_TCTRL_TEN_MASK 0x1u 03793 #define PIT_TCTRL_TEN_SHIFT 0 03794 #define PIT_TCTRL_TIE_MASK 0x2u 03795 #define PIT_TCTRL_TIE_SHIFT 1 03796 #define PIT_TCTRL_CHN_MASK 0x4u 03797 #define PIT_TCTRL_CHN_SHIFT 2 03798 /* TFLG Bit Fields */ 03799 #define PIT_TFLG_TIF_MASK 0x1u 03800 #define PIT_TFLG_TIF_SHIFT 0 03801 03802 /*! 03803 * @} 03804 */ /* end of group PIT_Register_Masks */ 03805 03806 03807 /* PIT - Peripheral instance base addresses */ 03808 /** Peripheral PIT base pointer */ 03809 #define PIT_BASE_PTR ((PIT_MemMapPtr)0x40037000u) 03810 /** Array initializer of PIT peripheral base pointers */ 03811 #define PIT_BASE_PTRS { PIT_BASE_PTR } 03812 03813 /* ---------------------------------------------------------------------------- 03814 -- PIT - Register accessor macros 03815 ---------------------------------------------------------------------------- */ 03816 03817 /*! 03818 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros 03819 * @{ 03820 */ 03821 03822 03823 /* PIT - Register instance definitions */ 03824 /* PIT */ 03825 #define PIT_MCR PIT_MCR_REG(PIT_BASE_PTR) 03826 #define PIT_LTMR64H PIT_LTMR64H_REG(PIT_BASE_PTR) 03827 #define PIT_LTMR64L PIT_LTMR64L_REG(PIT_BASE_PTR) 03828 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT_BASE_PTR,0) 03829 #define PIT_CVAL0 PIT_CVAL_REG(PIT_BASE_PTR,0) 03830 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT_BASE_PTR,0) 03831 #define PIT_TFLG0 PIT_TFLG_REG(PIT_BASE_PTR,0) 03832 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT_BASE_PTR,1) 03833 #define PIT_CVAL1 PIT_CVAL_REG(PIT_BASE_PTR,1) 03834 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT_BASE_PTR,1) 03835 #define PIT_TFLG1 PIT_TFLG_REG(PIT_BASE_PTR,1) 03836 03837 /* PIT - Register array accessors */ 03838 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT_BASE_PTR,index) 03839 #define PIT_CVAL(index) PIT_CVAL_REG(PIT_BASE_PTR,index) 03840 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT_BASE_PTR,index) 03841 #define PIT_TFLG(index) PIT_TFLG_REG(PIT_BASE_PTR,index) 03842 03843 /*! 03844 * @} 03845 */ /* end of group PIT_Register_Accessor_Macros */ 03846 03847 03848 /*! 03849 * @} 03850 */ /* end of group PIT_Peripheral */ 03851 03852 03853 /* ---------------------------------------------------------------------------- 03854 -- PMC 03855 ---------------------------------------------------------------------------- */ 03856 03857 /*! 03858 * @addtogroup PMC_Peripheral PMC 03859 * @{ 03860 */ 03861 03862 /** PMC - Peripheral register structure */ 03863 typedef struct PMC_MemMap { 03864 uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ 03865 uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ 03866 uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ 03867 } volatile *PMC_MemMapPtr; 03868 03869 /* ---------------------------------------------------------------------------- 03870 -- PMC - Register accessor macros 03871 ---------------------------------------------------------------------------- */ 03872 03873 /*! 03874 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros 03875 * @{ 03876 */ 03877 03878 03879 /* PMC - Register accessors */ 03880 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1) 03881 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2) 03882 #define PMC_REGSC_REG(base) ((base)->REGSC) 03883 03884 /*! 03885 * @} 03886 */ /* end of group PMC_Register_Accessor_Macros */ 03887 03888 03889 /* ---------------------------------------------------------------------------- 03890 -- PMC Register Masks 03891 ---------------------------------------------------------------------------- */ 03892 03893 /*! 03894 * @addtogroup PMC_Register_Masks PMC Register Masks 03895 * @{ 03896 */ 03897 03898 /* LVDSC1 Bit Fields */ 03899 #define PMC_LVDSC1_LVDV_MASK 0x3u 03900 #define PMC_LVDSC1_LVDV_SHIFT 0 03901 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) 03902 #define PMC_LVDSC1_LVDRE_MASK 0x10u 03903 #define PMC_LVDSC1_LVDRE_SHIFT 4 03904 #define PMC_LVDSC1_LVDIE_MASK 0x20u 03905 #define PMC_LVDSC1_LVDIE_SHIFT 5 03906 #define PMC_LVDSC1_LVDACK_MASK 0x40u 03907 #define PMC_LVDSC1_LVDACK_SHIFT 6 03908 #define PMC_LVDSC1_LVDF_MASK 0x80u 03909 #define PMC_LVDSC1_LVDF_SHIFT 7 03910 /* LVDSC2 Bit Fields */ 03911 #define PMC_LVDSC2_LVWV_MASK 0x3u 03912 #define PMC_LVDSC2_LVWV_SHIFT 0 03913 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) 03914 #define PMC_LVDSC2_LVWIE_MASK 0x20u 03915 #define PMC_LVDSC2_LVWIE_SHIFT 5 03916 #define PMC_LVDSC2_LVWACK_MASK 0x40u 03917 #define PMC_LVDSC2_LVWACK_SHIFT 6 03918 #define PMC_LVDSC2_LVWF_MASK 0x80u 03919 #define PMC_LVDSC2_LVWF_SHIFT 7 03920 /* REGSC Bit Fields */ 03921 #define PMC_REGSC_BGBE_MASK 0x1u 03922 #define PMC_REGSC_BGBE_SHIFT 0 03923 #define PMC_REGSC_REGONS_MASK 0x4u 03924 #define PMC_REGSC_REGONS_SHIFT 2 03925 #define PMC_REGSC_ACKISO_MASK 0x8u 03926 #define PMC_REGSC_ACKISO_SHIFT 3 03927 #define PMC_REGSC_BGEN_MASK 0x10u 03928 #define PMC_REGSC_BGEN_SHIFT 4 03929 03930 /*! 03931 * @} 03932 */ /* end of group PMC_Register_Masks */ 03933 03934 03935 /* PMC - Peripheral instance base addresses */ 03936 /** Peripheral PMC base pointer */ 03937 #define PMC_BASE_PTR ((PMC_MemMapPtr)0x4007D000u) 03938 /** Array initializer of PMC peripheral base pointers */ 03939 #define PMC_BASE_PTRS { PMC_BASE_PTR } 03940 03941 /* ---------------------------------------------------------------------------- 03942 -- PMC - Register accessor macros 03943 ---------------------------------------------------------------------------- */ 03944 03945 /*! 03946 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros 03947 * @{ 03948 */ 03949 03950 03951 /* PMC - Register instance definitions */ 03952 /* PMC */ 03953 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC_BASE_PTR) 03954 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC_BASE_PTR) 03955 #define PMC_REGSC PMC_REGSC_REG(PMC_BASE_PTR) 03956 03957 /*! 03958 * @} 03959 */ /* end of group PMC_Register_Accessor_Macros */ 03960 03961 03962 /*! 03963 * @} 03964 */ /* end of group PMC_Peripheral */ 03965 03966 03967 /* ---------------------------------------------------------------------------- 03968 -- PORT 03969 ---------------------------------------------------------------------------- */ 03970 03971 /*! 03972 * @addtogroup PORT_Peripheral PORT 03973 * @{ 03974 */ 03975 03976 /** PORT - Peripheral register structure */ 03977 typedef struct PORT_MemMap { 03978 uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ 03979 uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ 03980 uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ 03981 uint8_t RESERVED_0[24]; 03982 uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ 03983 } volatile *PORT_MemMapPtr; 03984 03985 /* ---------------------------------------------------------------------------- 03986 -- PORT - Register accessor macros 03987 ---------------------------------------------------------------------------- */ 03988 03989 /*! 03990 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros 03991 * @{ 03992 */ 03993 03994 03995 /* PORT - Register accessors */ 03996 #define PORT_PCR_REG(base,index) ((base)->PCR[index]) 03997 #define PORT_GPCLR_REG(base) ((base)->GPCLR) 03998 #define PORT_GPCHR_REG(base) ((base)->GPCHR) 03999 #define PORT_ISFR_REG(base) ((base)->ISFR) 04000 04001 /*! 04002 * @} 04003 */ /* end of group PORT_Register_Accessor_Macros */ 04004 04005 04006 /* ---------------------------------------------------------------------------- 04007 -- PORT Register Masks 04008 ---------------------------------------------------------------------------- */ 04009 04010 /*! 04011 * @addtogroup PORT_Register_Masks PORT Register Masks 04012 * @{ 04013 */ 04014 04015 /* PCR Bit Fields */ 04016 #define PORT_PCR_PS_MASK 0x1u 04017 #define PORT_PCR_PS_SHIFT 0 04018 #define PORT_PCR_PE_MASK 0x2u 04019 #define PORT_PCR_PE_SHIFT 1 04020 #define PORT_PCR_SRE_MASK 0x4u 04021 #define PORT_PCR_SRE_SHIFT 2 04022 #define PORT_PCR_PFE_MASK 0x10u 04023 #define PORT_PCR_PFE_SHIFT 4 04024 #define PORT_PCR_DSE_MASK 0x40u 04025 #define PORT_PCR_DSE_SHIFT 6 04026 #define PORT_PCR_MUX_MASK 0x700u 04027 #define PORT_PCR_MUX_SHIFT 8 04028 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK) 04029 #define PORT_PCR_IRQC_MASK 0xF0000u 04030 #define PORT_PCR_IRQC_SHIFT 16 04031 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK) 04032 #define PORT_PCR_ISF_MASK 0x1000000u 04033 #define PORT_PCR_ISF_SHIFT 24 04034 /* GPCLR Bit Fields */ 04035 #define PORT_GPCLR_GPWD_MASK 0xFFFFu 04036 #define PORT_GPCLR_GPWD_SHIFT 0 04037 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK) 04038 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u 04039 #define PORT_GPCLR_GPWE_SHIFT 16 04040 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK) 04041 /* GPCHR Bit Fields */ 04042 #define PORT_GPCHR_GPWD_MASK 0xFFFFu 04043 #define PORT_GPCHR_GPWD_SHIFT 0 04044 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK) 04045 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u 04046 #define PORT_GPCHR_GPWE_SHIFT 16 04047 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK) 04048 /* ISFR Bit Fields */ 04049 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu 04050 #define PORT_ISFR_ISF_SHIFT 0 04051 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK) 04052 04053 /*! 04054 * @} 04055 */ /* end of group PORT_Register_Masks */ 04056 04057 04058 /* PORT - Peripheral instance base addresses */ 04059 /** Peripheral PORTA base pointer */ 04060 #define PORTA_BASE_PTR ((PORT_MemMapPtr)0x40049000u) 04061 /** Peripheral PORTB base pointer */ 04062 #define PORTB_BASE_PTR ((PORT_MemMapPtr)0x4004A000u) 04063 /** Peripheral PORTC base pointer */ 04064 #define PORTC_BASE_PTR ((PORT_MemMapPtr)0x4004B000u) 04065 /** Peripheral PORTD base pointer */ 04066 #define PORTD_BASE_PTR ((PORT_MemMapPtr)0x4004C000u) 04067 /** Peripheral PORTE base pointer */ 04068 #define PORTE_BASE_PTR ((PORT_MemMapPtr)0x4004D000u) 04069 /** Array initializer of PORT peripheral base pointers */ 04070 #define PORT_BASE_PTRS { PORTA_BASE_PTR, PORTB_BASE_PTR, PORTC_BASE_PTR, PORTD_BASE_PTR, PORTE_BASE_PTR } 04071 04072 /* ---------------------------------------------------------------------------- 04073 -- PORT - Register accessor macros 04074 ---------------------------------------------------------------------------- */ 04075 04076 /*! 04077 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros 04078 * @{ 04079 */ 04080 04081 04082 /* PORT - Register instance definitions */ 04083 /* PORTA */ 04084 #define PORTA_PCR0 PORT_PCR_REG(PORTA_BASE_PTR,0) 04085 #define PORTA_PCR1 PORT_PCR_REG(PORTA_BASE_PTR,1) 04086 #define PORTA_PCR2 PORT_PCR_REG(PORTA_BASE_PTR,2) 04087 #define PORTA_PCR3 PORT_PCR_REG(PORTA_BASE_PTR,3) 04088 #define PORTA_PCR4 PORT_PCR_REG(PORTA_BASE_PTR,4) 04089 #define PORTA_PCR5 PORT_PCR_REG(PORTA_BASE_PTR,5) 04090 #define PORTA_PCR6 PORT_PCR_REG(PORTA_BASE_PTR,6) 04091 #define PORTA_PCR7 PORT_PCR_REG(PORTA_BASE_PTR,7) 04092 #define PORTA_PCR8 PORT_PCR_REG(PORTA_BASE_PTR,8) 04093 #define PORTA_PCR9 PORT_PCR_REG(PORTA_BASE_PTR,9) 04094 #define PORTA_PCR10 PORT_PCR_REG(PORTA_BASE_PTR,10) 04095 #define PORTA_PCR11 PORT_PCR_REG(PORTA_BASE_PTR,11) 04096 #define PORTA_PCR12 PORT_PCR_REG(PORTA_BASE_PTR,12) 04097 #define PORTA_PCR13 PORT_PCR_REG(PORTA_BASE_PTR,13) 04098 #define PORTA_PCR14 PORT_PCR_REG(PORTA_BASE_PTR,14) 04099 #define PORTA_PCR15 PORT_PCR_REG(PORTA_BASE_PTR,15) 04100 #define PORTA_PCR16 PORT_PCR_REG(PORTA_BASE_PTR,16) 04101 #define PORTA_PCR17 PORT_PCR_REG(PORTA_BASE_PTR,17) 04102 #define PORTA_PCR18 PORT_PCR_REG(PORTA_BASE_PTR,18) 04103 #define PORTA_PCR19 PORT_PCR_REG(PORTA_BASE_PTR,19) 04104 #define PORTA_PCR20 PORT_PCR_REG(PORTA_BASE_PTR,20) 04105 #define PORTA_PCR21 PORT_PCR_REG(PORTA_BASE_PTR,21) 04106 #define PORTA_PCR22 PORT_PCR_REG(PORTA_BASE_PTR,22) 04107 #define PORTA_PCR23 PORT_PCR_REG(PORTA_BASE_PTR,23) 04108 #define PORTA_PCR24 PORT_PCR_REG(PORTA_BASE_PTR,24) 04109 #define PORTA_PCR25 PORT_PCR_REG(PORTA_BASE_PTR,25) 04110 #define PORTA_PCR26 PORT_PCR_REG(PORTA_BASE_PTR,26) 04111 #define PORTA_PCR27 PORT_PCR_REG(PORTA_BASE_PTR,27) 04112 #define PORTA_PCR28 PORT_PCR_REG(PORTA_BASE_PTR,28) 04113 #define PORTA_PCR29 PORT_PCR_REG(PORTA_BASE_PTR,29) 04114 #define PORTA_PCR30 PORT_PCR_REG(PORTA_BASE_PTR,30) 04115 #define PORTA_PCR31 PORT_PCR_REG(PORTA_BASE_PTR,31) 04116 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA_BASE_PTR) 04117 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA_BASE_PTR) 04118 #define PORTA_ISFR PORT_ISFR_REG(PORTA_BASE_PTR) 04119 /* PORTB */ 04120 #define PORTB_PCR0 PORT_PCR_REG(PORTB_BASE_PTR,0) 04121 #define PORTB_PCR1 PORT_PCR_REG(PORTB_BASE_PTR,1) 04122 #define PORTB_PCR2 PORT_PCR_REG(PORTB_BASE_PTR,2) 04123 #define PORTB_PCR3 PORT_PCR_REG(PORTB_BASE_PTR,3) 04124 #define PORTB_PCR4 PORT_PCR_REG(PORTB_BASE_PTR,4) 04125 #define PORTB_PCR5 PORT_PCR_REG(PORTB_BASE_PTR,5) 04126 #define PORTB_PCR6 PORT_PCR_REG(PORTB_BASE_PTR,6) 04127 #define PORTB_PCR7 PORT_PCR_REG(PORTB_BASE_PTR,7) 04128 #define PORTB_PCR8 PORT_PCR_REG(PORTB_BASE_PTR,8) 04129 #define PORTB_PCR9 PORT_PCR_REG(PORTB_BASE_PTR,9) 04130 #define PORTB_PCR10 PORT_PCR_REG(PORTB_BASE_PTR,10) 04131 #define PORTB_PCR11 PORT_PCR_REG(PORTB_BASE_PTR,11) 04132 #define PORTB_PCR12 PORT_PCR_REG(PORTB_BASE_PTR,12) 04133 #define PORTB_PCR13 PORT_PCR_REG(PORTB_BASE_PTR,13) 04134 #define PORTB_PCR14 PORT_PCR_REG(PORTB_BASE_PTR,14) 04135 #define PORTB_PCR15 PORT_PCR_REG(PORTB_BASE_PTR,15) 04136 #define PORTB_PCR16 PORT_PCR_REG(PORTB_BASE_PTR,16) 04137 #define PORTB_PCR17 PORT_PCR_REG(PORTB_BASE_PTR,17) 04138 #define PORTB_PCR18 PORT_PCR_REG(PORTB_BASE_PTR,18) 04139 #define PORTB_PCR19 PORT_PCR_REG(PORTB_BASE_PTR,19) 04140 #define PORTB_PCR20 PORT_PCR_REG(PORTB_BASE_PTR,20) 04141 #define PORTB_PCR21 PORT_PCR_REG(PORTB_BASE_PTR,21) 04142 #define PORTB_PCR22 PORT_PCR_REG(PORTB_BASE_PTR,22) 04143 #define PORTB_PCR23 PORT_PCR_REG(PORTB_BASE_PTR,23) 04144 #define PORTB_PCR24 PORT_PCR_REG(PORTB_BASE_PTR,24) 04145 #define PORTB_PCR25 PORT_PCR_REG(PORTB_BASE_PTR,25) 04146 #define PORTB_PCR26 PORT_PCR_REG(PORTB_BASE_PTR,26) 04147 #define PORTB_PCR27 PORT_PCR_REG(PORTB_BASE_PTR,27) 04148 #define PORTB_PCR28 PORT_PCR_REG(PORTB_BASE_PTR,28) 04149 #define PORTB_PCR29 PORT_PCR_REG(PORTB_BASE_PTR,29) 04150 #define PORTB_PCR30 PORT_PCR_REG(PORTB_BASE_PTR,30) 04151 #define PORTB_PCR31 PORT_PCR_REG(PORTB_BASE_PTR,31) 04152 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB_BASE_PTR) 04153 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB_BASE_PTR) 04154 #define PORTB_ISFR PORT_ISFR_REG(PORTB_BASE_PTR) 04155 /* PORTC */ 04156 #define PORTC_PCR0 PORT_PCR_REG(PORTC_BASE_PTR,0) 04157 #define PORTC_PCR1 PORT_PCR_REG(PORTC_BASE_PTR,1) 04158 #define PORTC_PCR2 PORT_PCR_REG(PORTC_BASE_PTR,2) 04159 #define PORTC_PCR3 PORT_PCR_REG(PORTC_BASE_PTR,3) 04160 #define PORTC_PCR4 PORT_PCR_REG(PORTC_BASE_PTR,4) 04161 #define PORTC_PCR5 PORT_PCR_REG(PORTC_BASE_PTR,5) 04162 #define PORTC_PCR6 PORT_PCR_REG(PORTC_BASE_PTR,6) 04163 #define PORTC_PCR7 PORT_PCR_REG(PORTC_BASE_PTR,7) 04164 #define PORTC_PCR8 PORT_PCR_REG(PORTC_BASE_PTR,8) 04165 #define PORTC_PCR9 PORT_PCR_REG(PORTC_BASE_PTR,9) 04166 #define PORTC_PCR10 PORT_PCR_REG(PORTC_BASE_PTR,10) 04167 #define PORTC_PCR11 PORT_PCR_REG(PORTC_BASE_PTR,11) 04168 #define PORTC_PCR12 PORT_PCR_REG(PORTC_BASE_PTR,12) 04169 #define PORTC_PCR13 PORT_PCR_REG(PORTC_BASE_PTR,13) 04170 #define PORTC_PCR14 PORT_PCR_REG(PORTC_BASE_PTR,14) 04171 #define PORTC_PCR15 PORT_PCR_REG(PORTC_BASE_PTR,15) 04172 #define PORTC_PCR16 PORT_PCR_REG(PORTC_BASE_PTR,16) 04173 #define PORTC_PCR17 PORT_PCR_REG(PORTC_BASE_PTR,17) 04174 #define PORTC_PCR18 PORT_PCR_REG(PORTC_BASE_PTR,18) 04175 #define PORTC_PCR19 PORT_PCR_REG(PORTC_BASE_PTR,19) 04176 #define PORTC_PCR20 PORT_PCR_REG(PORTC_BASE_PTR,20) 04177 #define PORTC_PCR21 PORT_PCR_REG(PORTC_BASE_PTR,21) 04178 #define PORTC_PCR22 PORT_PCR_REG(PORTC_BASE_PTR,22) 04179 #define PORTC_PCR23 PORT_PCR_REG(PORTC_BASE_PTR,23) 04180 #define PORTC_PCR24 PORT_PCR_REG(PORTC_BASE_PTR,24) 04181 #define PORTC_PCR25 PORT_PCR_REG(PORTC_BASE_PTR,25) 04182 #define PORTC_PCR26 PORT_PCR_REG(PORTC_BASE_PTR,26) 04183 #define PORTC_PCR27 PORT_PCR_REG(PORTC_BASE_PTR,27) 04184 #define PORTC_PCR28 PORT_PCR_REG(PORTC_BASE_PTR,28) 04185 #define PORTC_PCR29 PORT_PCR_REG(PORTC_BASE_PTR,29) 04186 #define PORTC_PCR30 PORT_PCR_REG(PORTC_BASE_PTR,30) 04187 #define PORTC_PCR31 PORT_PCR_REG(PORTC_BASE_PTR,31) 04188 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC_BASE_PTR) 04189 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC_BASE_PTR) 04190 #define PORTC_ISFR PORT_ISFR_REG(PORTC_BASE_PTR) 04191 /* PORTD */ 04192 #define PORTD_PCR0 PORT_PCR_REG(PORTD_BASE_PTR,0) 04193 #define PORTD_PCR1 PORT_PCR_REG(PORTD_BASE_PTR,1) 04194 #define PORTD_PCR2 PORT_PCR_REG(PORTD_BASE_PTR,2) 04195 #define PORTD_PCR3 PORT_PCR_REG(PORTD_BASE_PTR,3) 04196 #define PORTD_PCR4 PORT_PCR_REG(PORTD_BASE_PTR,4) 04197 #define PORTD_PCR5 PORT_PCR_REG(PORTD_BASE_PTR,5) 04198 #define PORTD_PCR6 PORT_PCR_REG(PORTD_BASE_PTR,6) 04199 #define PORTD_PCR7 PORT_PCR_REG(PORTD_BASE_PTR,7) 04200 #define PORTD_PCR8 PORT_PCR_REG(PORTD_BASE_PTR,8) 04201 #define PORTD_PCR9 PORT_PCR_REG(PORTD_BASE_PTR,9) 04202 #define PORTD_PCR10 PORT_PCR_REG(PORTD_BASE_PTR,10) 04203 #define PORTD_PCR11 PORT_PCR_REG(PORTD_BASE_PTR,11) 04204 #define PORTD_PCR12 PORT_PCR_REG(PORTD_BASE_PTR,12) 04205 #define PORTD_PCR13 PORT_PCR_REG(PORTD_BASE_PTR,13) 04206 #define PORTD_PCR14 PORT_PCR_REG(PORTD_BASE_PTR,14) 04207 #define PORTD_PCR15 PORT_PCR_REG(PORTD_BASE_PTR,15) 04208 #define PORTD_PCR16 PORT_PCR_REG(PORTD_BASE_PTR,16) 04209 #define PORTD_PCR17 PORT_PCR_REG(PORTD_BASE_PTR,17) 04210 #define PORTD_PCR18 PORT_PCR_REG(PORTD_BASE_PTR,18) 04211 #define PORTD_PCR19 PORT_PCR_REG(PORTD_BASE_PTR,19) 04212 #define PORTD_PCR20 PORT_PCR_REG(PORTD_BASE_PTR,20) 04213 #define PORTD_PCR21 PORT_PCR_REG(PORTD_BASE_PTR,21) 04214 #define PORTD_PCR22 PORT_PCR_REG(PORTD_BASE_PTR,22) 04215 #define PORTD_PCR23 PORT_PCR_REG(PORTD_BASE_PTR,23) 04216 #define PORTD_PCR24 PORT_PCR_REG(PORTD_BASE_PTR,24) 04217 #define PORTD_PCR25 PORT_PCR_REG(PORTD_BASE_PTR,25) 04218 #define PORTD_PCR26 PORT_PCR_REG(PORTD_BASE_PTR,26) 04219 #define PORTD_PCR27 PORT_PCR_REG(PORTD_BASE_PTR,27) 04220 #define PORTD_PCR28 PORT_PCR_REG(PORTD_BASE_PTR,28) 04221 #define PORTD_PCR29 PORT_PCR_REG(PORTD_BASE_PTR,29) 04222 #define PORTD_PCR30 PORT_PCR_REG(PORTD_BASE_PTR,30) 04223 #define PORTD_PCR31 PORT_PCR_REG(PORTD_BASE_PTR,31) 04224 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD_BASE_PTR) 04225 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD_BASE_PTR) 04226 #define PORTD_ISFR PORT_ISFR_REG(PORTD_BASE_PTR) 04227 /* PORTE */ 04228 #define PORTE_PCR0 PORT_PCR_REG(PORTE_BASE_PTR,0) 04229 #define PORTE_PCR1 PORT_PCR_REG(PORTE_BASE_PTR,1) 04230 #define PORTE_PCR2 PORT_PCR_REG(PORTE_BASE_PTR,2) 04231 #define PORTE_PCR3 PORT_PCR_REG(PORTE_BASE_PTR,3) 04232 #define PORTE_PCR4 PORT_PCR_REG(PORTE_BASE_PTR,4) 04233 #define PORTE_PCR5 PORT_PCR_REG(PORTE_BASE_PTR,5) 04234 #define PORTE_PCR6 PORT_PCR_REG(PORTE_BASE_PTR,6) 04235 #define PORTE_PCR7 PORT_PCR_REG(PORTE_BASE_PTR,7) 04236 #define PORTE_PCR8 PORT_PCR_REG(PORTE_BASE_PTR,8) 04237 #define PORTE_PCR9 PORT_PCR_REG(PORTE_BASE_PTR,9) 04238 #define PORTE_PCR10 PORT_PCR_REG(PORTE_BASE_PTR,10) 04239 #define PORTE_PCR11 PORT_PCR_REG(PORTE_BASE_PTR,11) 04240 #define PORTE_PCR12 PORT_PCR_REG(PORTE_BASE_PTR,12) 04241 #define PORTE_PCR13 PORT_PCR_REG(PORTE_BASE_PTR,13) 04242 #define PORTE_PCR14 PORT_PCR_REG(PORTE_BASE_PTR,14) 04243 #define PORTE_PCR15 PORT_PCR_REG(PORTE_BASE_PTR,15) 04244 #define PORTE_PCR16 PORT_PCR_REG(PORTE_BASE_PTR,16) 04245 #define PORTE_PCR17 PORT_PCR_REG(PORTE_BASE_PTR,17) 04246 #define PORTE_PCR18 PORT_PCR_REG(PORTE_BASE_PTR,18) 04247 #define PORTE_PCR19 PORT_PCR_REG(PORTE_BASE_PTR,19) 04248 #define PORTE_PCR20 PORT_PCR_REG(PORTE_BASE_PTR,20) 04249 #define PORTE_PCR21 PORT_PCR_REG(PORTE_BASE_PTR,21) 04250 #define PORTE_PCR22 PORT_PCR_REG(PORTE_BASE_PTR,22) 04251 #define PORTE_PCR23 PORT_PCR_REG(PORTE_BASE_PTR,23) 04252 #define PORTE_PCR24 PORT_PCR_REG(PORTE_BASE_PTR,24) 04253 #define PORTE_PCR25 PORT_PCR_REG(PORTE_BASE_PTR,25) 04254 #define PORTE_PCR26 PORT_PCR_REG(PORTE_BASE_PTR,26) 04255 #define PORTE_PCR27 PORT_PCR_REG(PORTE_BASE_PTR,27) 04256 #define PORTE_PCR28 PORT_PCR_REG(PORTE_BASE_PTR,28) 04257 #define PORTE_PCR29 PORT_PCR_REG(PORTE_BASE_PTR,29) 04258 #define PORTE_PCR30 PORT_PCR_REG(PORTE_BASE_PTR,30) 04259 #define PORTE_PCR31 PORT_PCR_REG(PORTE_BASE_PTR,31) 04260 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE_BASE_PTR) 04261 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE_BASE_PTR) 04262 #define PORTE_ISFR PORT_ISFR_REG(PORTE_BASE_PTR) 04263 04264 /* PORT - Register array accessors */ 04265 #define PORTA_PCR(index) PORT_PCR_REG(PORTA_BASE_PTR,index) 04266 #define PORTB_PCR(index) PORT_PCR_REG(PORTB_BASE_PTR,index) 04267 #define PORTC_PCR(index) PORT_PCR_REG(PORTC_BASE_PTR,index) 04268 #define PORTD_PCR(index) PORT_PCR_REG(PORTD_BASE_PTR,index) 04269 #define PORTE_PCR(index) PORT_PCR_REG(PORTE_BASE_PTR,index) 04270 04271 /*! 04272 * @} 04273 */ /* end of group PORT_Register_Accessor_Macros */ 04274 04275 04276 /*! 04277 * @} 04278 */ /* end of group PORT_Peripheral */ 04279 04280 04281 /* ---------------------------------------------------------------------------- 04282 -- RCM 04283 ---------------------------------------------------------------------------- */ 04284 04285 /*! 04286 * @addtogroup RCM_Peripheral RCM 04287 * @{ 04288 */ 04289 04290 /** RCM - Peripheral register structure */ 04291 typedef struct RCM_MemMap { 04292 uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ 04293 uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ 04294 uint8_t RESERVED_0[2]; 04295 uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ 04296 uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ 04297 } volatile *RCM_MemMapPtr; 04298 04299 /* ---------------------------------------------------------------------------- 04300 -- RCM - Register accessor macros 04301 ---------------------------------------------------------------------------- */ 04302 04303 /*! 04304 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros 04305 * @{ 04306 */ 04307 04308 04309 /* RCM - Register accessors */ 04310 #define RCM_SRS0_REG(base) ((base)->SRS0) 04311 #define RCM_SRS1_REG(base) ((base)->SRS1) 04312 #define RCM_RPFC_REG(base) ((base)->RPFC) 04313 #define RCM_RPFW_REG(base) ((base)->RPFW) 04314 04315 /*! 04316 * @} 04317 */ /* end of group RCM_Register_Accessor_Macros */ 04318 04319 04320 /* ---------------------------------------------------------------------------- 04321 -- RCM Register Masks 04322 ---------------------------------------------------------------------------- */ 04323 04324 /*! 04325 * @addtogroup RCM_Register_Masks RCM Register Masks 04326 * @{ 04327 */ 04328 04329 /* SRS0 Bit Fields */ 04330 #define RCM_SRS0_WAKEUP_MASK 0x1u 04331 #define RCM_SRS0_WAKEUP_SHIFT 0 04332 #define RCM_SRS0_LVD_MASK 0x2u 04333 #define RCM_SRS0_LVD_SHIFT 1 04334 #define RCM_SRS0_LOC_MASK 0x4u 04335 #define RCM_SRS0_LOC_SHIFT 2 04336 #define RCM_SRS0_LOL_MASK 0x8u 04337 #define RCM_SRS0_LOL_SHIFT 3 04338 #define RCM_SRS0_WDOG_MASK 0x20u 04339 #define RCM_SRS0_WDOG_SHIFT 5 04340 #define RCM_SRS0_PIN_MASK 0x40u 04341 #define RCM_SRS0_PIN_SHIFT 6 04342 #define RCM_SRS0_POR_MASK 0x80u 04343 #define RCM_SRS0_POR_SHIFT 7 04344 /* SRS1 Bit Fields */ 04345 #define RCM_SRS1_LOCKUP_MASK 0x2u 04346 #define RCM_SRS1_LOCKUP_SHIFT 1 04347 #define RCM_SRS1_SW_MASK 0x4u 04348 #define RCM_SRS1_SW_SHIFT 2 04349 #define RCM_SRS1_MDM_AP_MASK 0x8u 04350 #define RCM_SRS1_MDM_AP_SHIFT 3 04351 #define RCM_SRS1_SACKERR_MASK 0x20u 04352 #define RCM_SRS1_SACKERR_SHIFT 5 04353 /* RPFC Bit Fields */ 04354 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u 04355 #define RCM_RPFC_RSTFLTSRW_SHIFT 0 04356 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK) 04357 #define RCM_RPFC_RSTFLTSS_MASK 0x4u 04358 #define RCM_RPFC_RSTFLTSS_SHIFT 2 04359 /* RPFW Bit Fields */ 04360 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu 04361 #define RCM_RPFW_RSTFLTSEL_SHIFT 0 04362 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK) 04363 04364 /*! 04365 * @} 04366 */ /* end of group RCM_Register_Masks */ 04367 04368 04369 /* RCM - Peripheral instance base addresses */ 04370 /** Peripheral RCM base pointer */ 04371 #define RCM_BASE_PTR ((RCM_MemMapPtr)0x4007F000u) 04372 /** Array initializer of RCM peripheral base pointers */ 04373 #define RCM_BASE_PTRS { RCM_BASE_PTR } 04374 04375 /* ---------------------------------------------------------------------------- 04376 -- RCM - Register accessor macros 04377 ---------------------------------------------------------------------------- */ 04378 04379 /*! 04380 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros 04381 * @{ 04382 */ 04383 04384 04385 /* RCM - Register instance definitions */ 04386 /* RCM */ 04387 #define RCM_SRS0 RCM_SRS0_REG(RCM_BASE_PTR) 04388 #define RCM_SRS1 RCM_SRS1_REG(RCM_BASE_PTR) 04389 #define RCM_RPFC RCM_RPFC_REG(RCM_BASE_PTR) 04390 #define RCM_RPFW RCM_RPFW_REG(RCM_BASE_PTR) 04391 04392 /*! 04393 * @} 04394 */ /* end of group RCM_Register_Accessor_Macros */ 04395 04396 04397 /*! 04398 * @} 04399 */ /* end of group RCM_Peripheral */ 04400 04401 04402 /* ---------------------------------------------------------------------------- 04403 -- ROM 04404 ---------------------------------------------------------------------------- */ 04405 04406 /*! 04407 * @addtogroup ROM_Peripheral ROM 04408 * @{ 04409 */ 04410 04411 /** ROM - Peripheral register structure */ 04412 typedef struct ROM_MemMap { 04413 uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */ 04414 uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */ 04415 uint8_t RESERVED_0[4028]; 04416 uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ 04417 uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 04418 uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 04419 uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 04420 uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 04421 uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 04422 uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 04423 uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 04424 uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 04425 uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 04426 } volatile *ROM_MemMapPtr; 04427 04428 /* ---------------------------------------------------------------------------- 04429 -- ROM - Register accessor macros 04430 ---------------------------------------------------------------------------- */ 04431 04432 /*! 04433 * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros 04434 * @{ 04435 */ 04436 04437 04438 /* ROM - Register accessors */ 04439 #define ROM_ENTRY_REG(base,index) ((base)->ENTRY[index]) 04440 #define ROM_TABLEMARK_REG(base) ((base)->TABLEMARK) 04441 #define ROM_SYSACCESS_REG(base) ((base)->SYSACCESS) 04442 #define ROM_PERIPHID4_REG(base) ((base)->PERIPHID4) 04443 #define ROM_PERIPHID5_REG(base) ((base)->PERIPHID5) 04444 #define ROM_PERIPHID6_REG(base) ((base)->PERIPHID6) 04445 #define ROM_PERIPHID7_REG(base) ((base)->PERIPHID7) 04446 #define ROM_PERIPHID0_REG(base) ((base)->PERIPHID0) 04447 #define ROM_PERIPHID1_REG(base) ((base)->PERIPHID1) 04448 #define ROM_PERIPHID2_REG(base) ((base)->PERIPHID2) 04449 #define ROM_PERIPHID3_REG(base) ((base)->PERIPHID3) 04450 #define ROM_COMPID_REG(base,index) ((base)->COMPID[index]) 04451 04452 /*! 04453 * @} 04454 */ /* end of group ROM_Register_Accessor_Macros */ 04455 04456 04457 /* ---------------------------------------------------------------------------- 04458 -- ROM Register Masks 04459 ---------------------------------------------------------------------------- */ 04460 04461 /*! 04462 * @addtogroup ROM_Register_Masks ROM Register Masks 04463 * @{ 04464 */ 04465 04466 /* ENTRY Bit Fields */ 04467 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu 04468 #define ROM_ENTRY_ENTRY_SHIFT 0 04469 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK) 04470 /* TABLEMARK Bit Fields */ 04471 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu 04472 #define ROM_TABLEMARK_MARK_SHIFT 0 04473 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK) 04474 /* SYSACCESS Bit Fields */ 04475 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu 04476 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0 04477 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK) 04478 /* PERIPHID4 Bit Fields */ 04479 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu 04480 #define ROM_PERIPHID4_PERIPHID_SHIFT 0 04481 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK) 04482 /* PERIPHID5 Bit Fields */ 04483 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu 04484 #define ROM_PERIPHID5_PERIPHID_SHIFT 0 04485 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK) 04486 /* PERIPHID6 Bit Fields */ 04487 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu 04488 #define ROM_PERIPHID6_PERIPHID_SHIFT 0 04489 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK) 04490 /* PERIPHID7 Bit Fields */ 04491 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu 04492 #define ROM_PERIPHID7_PERIPHID_SHIFT 0 04493 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK) 04494 /* PERIPHID0 Bit Fields */ 04495 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu 04496 #define ROM_PERIPHID0_PERIPHID_SHIFT 0 04497 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK) 04498 /* PERIPHID1 Bit Fields */ 04499 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu 04500 #define ROM_PERIPHID1_PERIPHID_SHIFT 0 04501 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK) 04502 /* PERIPHID2 Bit Fields */ 04503 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu 04504 #define ROM_PERIPHID2_PERIPHID_SHIFT 0 04505 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK) 04506 /* PERIPHID3 Bit Fields */ 04507 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu 04508 #define ROM_PERIPHID3_PERIPHID_SHIFT 0 04509 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK) 04510 /* COMPID Bit Fields */ 04511 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu 04512 #define ROM_COMPID_COMPID_SHIFT 0 04513 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK) 04514 04515 /*! 04516 * @} 04517 */ /* end of group ROM_Register_Masks */ 04518 04519 04520 /* ROM - Peripheral instance base addresses */ 04521 /** Peripheral ROM base pointer */ 04522 #define ROM_BASE_PTR ((ROM_MemMapPtr)0xF0002000u) 04523 /** Array initializer of ROM peripheral base pointers */ 04524 #define ROM_BASE_PTRS { ROM_BASE_PTR } 04525 04526 /* ---------------------------------------------------------------------------- 04527 -- ROM - Register accessor macros 04528 ---------------------------------------------------------------------------- */ 04529 04530 /*! 04531 * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros 04532 * @{ 04533 */ 04534 04535 04536 /* ROM - Register instance definitions */ 04537 /* ROM */ 04538 #define ROM_ENTRY0 ROM_ENTRY_REG(ROM_BASE_PTR,0) 04539 #define ROM_ENTRY1 ROM_ENTRY_REG(ROM_BASE_PTR,1) 04540 #define ROM_ENTRY2 ROM_ENTRY_REG(ROM_BASE_PTR,2) 04541 #define ROM_TABLEMARK ROM_TABLEMARK_REG(ROM_BASE_PTR) 04542 #define ROM_SYSACCESS ROM_SYSACCESS_REG(ROM_BASE_PTR) 04543 #define ROM_PERIPHID4 ROM_PERIPHID4_REG(ROM_BASE_PTR) 04544 #define ROM_PERIPHID5 ROM_PERIPHID5_REG(ROM_BASE_PTR) 04545 #define ROM_PERIPHID6 ROM_PERIPHID6_REG(ROM_BASE_PTR) 04546 #define ROM_PERIPHID7 ROM_PERIPHID7_REG(ROM_BASE_PTR) 04547 #define ROM_PERIPHID0 ROM_PERIPHID0_REG(ROM_BASE_PTR) 04548 #define ROM_PERIPHID1 ROM_PERIPHID1_REG(ROM_BASE_PTR) 04549 #define ROM_PERIPHID2 ROM_PERIPHID2_REG(ROM_BASE_PTR) 04550 #define ROM_PERIPHID3 ROM_PERIPHID3_REG(ROM_BASE_PTR) 04551 #define ROM_COMPID0 ROM_COMPID_REG(ROM_BASE_PTR,0) 04552 #define ROM_COMPID1 ROM_COMPID_REG(ROM_BASE_PTR,1) 04553 #define ROM_COMPID2 ROM_COMPID_REG(ROM_BASE_PTR,2) 04554 #define ROM_COMPID3 ROM_COMPID_REG(ROM_BASE_PTR,3) 04555 04556 /* ROM - Register array accessors */ 04557 #define ROM_ENTRY(index) ROM_ENTRY_REG(ROM_BASE_PTR,index) 04558 #define ROM_COMPID(index) ROM_COMPID_REG(ROM_BASE_PTR,index) 04559 04560 /*! 04561 * @} 04562 */ /* end of group ROM_Register_Accessor_Macros */ 04563 04564 04565 /*! 04566 * @} 04567 */ /* end of group ROM_Peripheral */ 04568 04569 04570 /* ---------------------------------------------------------------------------- 04571 -- RTC 04572 ---------------------------------------------------------------------------- */ 04573 04574 /*! 04575 * @addtogroup RTC_Peripheral RTC 04576 * @{ 04577 */ 04578 04579 /** RTC - Peripheral register structure */ 04580 typedef struct RTC_MemMap { 04581 uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ 04582 uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ 04583 uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ 04584 uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ 04585 uint32_t CR; /**< RTC Control Register, offset: 0x10 */ 04586 uint32_t SR; /**< RTC Status Register, offset: 0x14 */ 04587 uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ 04588 uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ 04589 } volatile *RTC_MemMapPtr; 04590 04591 /* ---------------------------------------------------------------------------- 04592 -- RTC - Register accessor macros 04593 ---------------------------------------------------------------------------- */ 04594 04595 /*! 04596 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros 04597 * @{ 04598 */ 04599 04600 04601 /* RTC - Register accessors */ 04602 #define RTC_TSR_REG(base) ((base)->TSR) 04603 #define RTC_TPR_REG(base) ((base)->TPR) 04604 #define RTC_TAR_REG(base) ((base)->TAR) 04605 #define RTC_TCR_REG(base) ((base)->TCR) 04606 #define RTC_CR_REG(base) ((base)->CR) 04607 #define RTC_SR_REG(base) ((base)->SR) 04608 #define RTC_LR_REG(base) ((base)->LR) 04609 #define RTC_IER_REG(base) ((base)->IER) 04610 04611 /*! 04612 * @} 04613 */ /* end of group RTC_Register_Accessor_Macros */ 04614 04615 04616 /* ---------------------------------------------------------------------------- 04617 -- RTC Register Masks 04618 ---------------------------------------------------------------------------- */ 04619 04620 /*! 04621 * @addtogroup RTC_Register_Masks RTC Register Masks 04622 * @{ 04623 */ 04624 04625 /* TSR Bit Fields */ 04626 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu 04627 #define RTC_TSR_TSR_SHIFT 0 04628 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK) 04629 /* TPR Bit Fields */ 04630 #define RTC_TPR_TPR_MASK 0xFFFFu 04631 #define RTC_TPR_TPR_SHIFT 0 04632 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK) 04633 /* TAR Bit Fields */ 04634 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu 04635 #define RTC_TAR_TAR_SHIFT 0 04636 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK) 04637 /* TCR Bit Fields */ 04638 #define RTC_TCR_TCR_MASK 0xFFu 04639 #define RTC_TCR_TCR_SHIFT 0 04640 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK) 04641 #define RTC_TCR_CIR_MASK 0xFF00u 04642 #define RTC_TCR_CIR_SHIFT 8 04643 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK) 04644 #define RTC_TCR_TCV_MASK 0xFF0000u 04645 #define RTC_TCR_TCV_SHIFT 16 04646 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK) 04647 #define RTC_TCR_CIC_MASK 0xFF000000u 04648 #define RTC_TCR_CIC_SHIFT 24 04649 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK) 04650 /* CR Bit Fields */ 04651 #define RTC_CR_SWR_MASK 0x1u 04652 #define RTC_CR_SWR_SHIFT 0 04653 #define RTC_CR_WPE_MASK 0x2u 04654 #define RTC_CR_WPE_SHIFT 1 04655 #define RTC_CR_SUP_MASK 0x4u 04656 #define RTC_CR_SUP_SHIFT 2 04657 #define RTC_CR_UM_MASK 0x8u 04658 #define RTC_CR_UM_SHIFT 3 04659 #define RTC_CR_OSCE_MASK 0x100u 04660 #define RTC_CR_OSCE_SHIFT 8 04661 #define RTC_CR_CLKO_MASK 0x200u 04662 #define RTC_CR_CLKO_SHIFT 9 04663 #define RTC_CR_SC16P_MASK 0x400u 04664 #define RTC_CR_SC16P_SHIFT 10 04665 #define RTC_CR_SC8P_MASK 0x800u 04666 #define RTC_CR_SC8P_SHIFT 11 04667 #define RTC_CR_SC4P_MASK 0x1000u 04668 #define RTC_CR_SC4P_SHIFT 12 04669 #define RTC_CR_SC2P_MASK 0x2000u 04670 #define RTC_CR_SC2P_SHIFT 13 04671 /* SR Bit Fields */ 04672 #define RTC_SR_TIF_MASK 0x1u 04673 #define RTC_SR_TIF_SHIFT 0 04674 #define RTC_SR_TOF_MASK 0x2u 04675 #define RTC_SR_TOF_SHIFT 1 04676 #define RTC_SR_TAF_MASK 0x4u 04677 #define RTC_SR_TAF_SHIFT 2 04678 #define RTC_SR_TCE_MASK 0x10u 04679 #define RTC_SR_TCE_SHIFT 4 04680 /* LR Bit Fields */ 04681 #define RTC_LR_TCL_MASK 0x8u 04682 #define RTC_LR_TCL_SHIFT 3 04683 #define RTC_LR_CRL_MASK 0x10u 04684 #define RTC_LR_CRL_SHIFT 4 04685 #define RTC_LR_SRL_MASK 0x20u 04686 #define RTC_LR_SRL_SHIFT 5 04687 #define RTC_LR_LRL_MASK 0x40u 04688 #define RTC_LR_LRL_SHIFT 6 04689 /* IER Bit Fields */ 04690 #define RTC_IER_TIIE_MASK 0x1u 04691 #define RTC_IER_TIIE_SHIFT 0 04692 #define RTC_IER_TOIE_MASK 0x2u 04693 #define RTC_IER_TOIE_SHIFT 1 04694 #define RTC_IER_TAIE_MASK 0x4u 04695 #define RTC_IER_TAIE_SHIFT 2 04696 #define RTC_IER_TSIE_MASK 0x10u 04697 #define RTC_IER_TSIE_SHIFT 4 04698 #define RTC_IER_WPON_MASK 0x80u 04699 #define RTC_IER_WPON_SHIFT 7 04700 04701 /*! 04702 * @} 04703 */ /* end of group RTC_Register_Masks */ 04704 04705 04706 /* RTC - Peripheral instance base addresses */ 04707 /** Peripheral RTC base pointer */ 04708 #define RTC_BASE_PTR ((RTC_MemMapPtr)0x4003D000u) 04709 /** Array initializer of RTC peripheral base pointers */ 04710 #define RTC_BASE_PTRS { RTC_BASE_PTR } 04711 04712 /* ---------------------------------------------------------------------------- 04713 -- RTC - Register accessor macros 04714 ---------------------------------------------------------------------------- */ 04715 04716 /*! 04717 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros 04718 * @{ 04719 */ 04720 04721 04722 /* RTC - Register instance definitions */ 04723 /* RTC */ 04724 #define RTC_TSR RTC_TSR_REG(RTC_BASE_PTR) 04725 #define RTC_TPR RTC_TPR_REG(RTC_BASE_PTR) 04726 #define RTC_TAR RTC_TAR_REG(RTC_BASE_PTR) 04727 #define RTC_TCR RTC_TCR_REG(RTC_BASE_PTR) 04728 #define RTC_CR RTC_CR_REG(RTC_BASE_PTR) 04729 #define RTC_SR RTC_SR_REG(RTC_BASE_PTR) 04730 #define RTC_LR RTC_LR_REG(RTC_BASE_PTR) 04731 #define RTC_IER RTC_IER_REG(RTC_BASE_PTR) 04732 04733 /*! 04734 * @} 04735 */ /* end of group RTC_Register_Accessor_Macros */ 04736 04737 04738 /*! 04739 * @} 04740 */ /* end of group RTC_Peripheral */ 04741 04742 04743 /* ---------------------------------------------------------------------------- 04744 -- SCB 04745 ---------------------------------------------------------------------------- */ 04746 04747 /*! 04748 * @addtogroup SCB_Peripheral SCB 04749 * @{ 04750 */ 04751 04752 /** SCB - Peripheral register structure */ 04753 typedef struct SCB_MemMap { 04754 uint8_t RESERVED_0[8]; 04755 uint32_t ACTLR; /**< Auxiliary Control Register,, offset: 0x8 */ 04756 uint8_t RESERVED_1[3316]; 04757 uint32_t CPUID; /**< CPUID Base Register, offset: 0xD00 */ 04758 uint32_t ICSR; /**< Interrupt Control and State Register, offset: 0xD04 */ 04759 uint32_t VTOR; /**< Vector Table Offset Register, offset: 0xD08 */ 04760 uint32_t AIRCR; /**< Application Interrupt and Reset Control Register, offset: 0xD0C */ 04761 uint32_t SCR; /**< System Control Register, offset: 0xD10 */ 04762 uint32_t CCR; /**< Configuration and Control Register, offset: 0xD14 */ 04763 uint8_t RESERVED_2[4]; 04764 uint32_t SHPR2; /**< System Handler Priority Register 2, offset: 0xD1C */ 04765 uint32_t SHPR3; /**< System Handler Priority Register 3, offset: 0xD20 */ 04766 uint32_t SHCSR; /**< System Handler Control and State Register, offset: 0xD24 */ 04767 uint8_t RESERVED_3[8]; 04768 uint32_t DFSR; /**< Debug Fault Status Register, offset: 0xD30 */ 04769 } volatile *SCB_MemMapPtr; 04770 04771 /* ---------------------------------------------------------------------------- 04772 -- SCB - Register accessor macros 04773 ---------------------------------------------------------------------------- */ 04774 04775 /*! 04776 * @addtogroup SCB_Register_Accessor_Macros SCB - Register accessor macros 04777 * @{ 04778 */ 04779 04780 04781 /* SCB - Register accessors */ 04782 #define SCB_ACTLR_REG(base) ((base)->ACTLR) 04783 #define SCB_CPUID_REG(base) ((base)->CPUID) 04784 #define SCB_ICSR_REG(base) ((base)->ICSR) 04785 #define SCB_VTOR_REG(base) ((base)->VTOR) 04786 #define SCB_AIRCR_REG(base) ((base)->AIRCR) 04787 #define SCB_SCR_REG(base) ((base)->SCR) 04788 #define SCB_CCR_REG(base) ((base)->CCR) 04789 #define SCB_SHPR2_REG(base) ((base)->SHPR2) 04790 #define SCB_SHPR3_REG(base) ((base)->SHPR3) 04791 #define SCB_SHCSR_REG(base) ((base)->SHCSR) 04792 #define SCB_DFSR_REG(base) ((base)->DFSR) 04793 04794 /*! 04795 * @} 04796 */ /* end of group SCB_Register_Accessor_Macros */ 04797 04798 04799 /* ---------------------------------------------------------------------------- 04800 -- SCB Register Masks 04801 ---------------------------------------------------------------------------- */ 04802 04803 /*! 04804 * @addtogroup SCB_Register_Masks SCB Register Masks 04805 * @{ 04806 */ 04807 04808 /* CPUID Bit Fields */ 04809 #define SCB_CPUID_REVISION_MASK 0xFu 04810 #define SCB_CPUID_REVISION_SHIFT 0 04811 #define SCB_CPUID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_REVISION_SHIFT))&SCB_CPUID_REVISION_MASK) 04812 #define SCB_CPUID_PARTNO_MASK 0xFFF0u 04813 #define SCB_CPUID_PARTNO_SHIFT 4 04814 #define SCB_CPUID_PARTNO(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_PARTNO_SHIFT))&SCB_CPUID_PARTNO_MASK) 04815 #define SCB_CPUID_VARIANT_MASK 0xF00000u 04816 #define SCB_CPUID_VARIANT_SHIFT 20 04817 #define SCB_CPUID_VARIANT(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_VARIANT_SHIFT))&SCB_CPUID_VARIANT_MASK) 04818 #define SCB_CPUID_IMPLEMENTER_MASK 0xFF000000u 04819 #define SCB_CPUID_IMPLEMENTER_SHIFT 24 04820 #define SCB_CPUID_IMPLEMENTER(x) (((uint32_t)(((uint32_t)(x))<<SCB_CPUID_IMPLEMENTER_SHIFT))&SCB_CPUID_IMPLEMENTER_MASK) 04821 /* ICSR Bit Fields */ 04822 #define SCB_ICSR_VECTACTIVE_MASK 0x3Fu 04823 #define SCB_ICSR_VECTACTIVE_SHIFT 0 04824 #define SCB_ICSR_VECTACTIVE(x) (((uint32_t)(((uint32_t)(x))<<SCB_ICSR_VECTACTIVE_SHIFT))&SCB_ICSR_VECTACTIVE_MASK) 04825 #define SCB_ICSR_VECTPENDING_MASK 0x3F000u 04826 #define SCB_ICSR_VECTPENDING_SHIFT 12 04827 #define SCB_ICSR_VECTPENDING(x) (((uint32_t)(((uint32_t)(x))<<SCB_ICSR_VECTPENDING_SHIFT))&SCB_ICSR_VECTPENDING_MASK) 04828 #define SCB_ICSR_ISRPENDING_MASK 0x400000u 04829 #define SCB_ICSR_ISRPENDING_SHIFT 22 04830 #define SCB_ICSR_PENDSTCLR_MASK 0x2000000u 04831 #define SCB_ICSR_PENDSTCLR_SHIFT 25 04832 #define SCB_ICSR_PENDSTSET_MASK 0x4000000u 04833 #define SCB_ICSR_PENDSTSET_SHIFT 26 04834 #define SCB_ICSR_PENDSVCLR_MASK 0x8000000u 04835 #define SCB_ICSR_PENDSVCLR_SHIFT 27 04836 #define SCB_ICSR_PENDSVSET_MASK 0x10000000u 04837 #define SCB_ICSR_PENDSVSET_SHIFT 28 04838 #define SCB_ICSR_NMIPENDSET_MASK 0x80000000u 04839 #define SCB_ICSR_NMIPENDSET_SHIFT 31 04840 /* VTOR Bit Fields */ 04841 #define SCB_VTOR_TBLOFF_MASK 0xFFFFFF80u 04842 #define SCB_VTOR_TBLOFF_SHIFT 7 04843 #define SCB_VTOR_TBLOFF(x) (((uint32_t)(((uint32_t)(x))<<SCB_VTOR_TBLOFF_SHIFT))&SCB_VTOR_TBLOFF_MASK) 04844 /* AIRCR Bit Fields */ 04845 #define SCB_AIRCR_VECTCLRACTIVE_MASK 0x2u 04846 #define SCB_AIRCR_VECTCLRACTIVE_SHIFT 1 04847 #define SCB_AIRCR_SYSRESETREQ_MASK 0x4u 04848 #define SCB_AIRCR_SYSRESETREQ_SHIFT 2 04849 #define SCB_AIRCR_ENDIANNESS_MASK 0x8000u 04850 #define SCB_AIRCR_ENDIANNESS_SHIFT 15 04851 #define SCB_AIRCR_VECTKEY_MASK 0xFFFF0000u 04852 #define SCB_AIRCR_VECTKEY_SHIFT 16 04853 #define SCB_AIRCR_VECTKEY(x) (((uint32_t)(((uint32_t)(x))<<SCB_AIRCR_VECTKEY_SHIFT))&SCB_AIRCR_VECTKEY_MASK) 04854 /* SCR Bit Fields */ 04855 #define SCB_SCR_SLEEPONEXIT_MASK 0x2u 04856 #define SCB_SCR_SLEEPONEXIT_SHIFT 1 04857 #define SCB_SCR_SLEEPDEEP_MASK 0x4u 04858 #define SCB_SCR_SLEEPDEEP_SHIFT 2 04859 #define SCB_SCR_SEVONPEND_MASK 0x10u 04860 #define SCB_SCR_SEVONPEND_SHIFT 4 04861 /* CCR Bit Fields */ 04862 #define SCB_CCR_UNALIGN_TRP_MASK 0x8u 04863 #define SCB_CCR_UNALIGN_TRP_SHIFT 3 04864 #define SCB_CCR_STKALIGN_MASK 0x200u 04865 #define SCB_CCR_STKALIGN_SHIFT 9 04866 /* SHPR2 Bit Fields */ 04867 #define SCB_SHPR2_PRI_11_MASK 0xFF000000u 04868 #define SCB_SHPR2_PRI_11_SHIFT 24 04869 #define SCB_SHPR2_PRI_11(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR2_PRI_11_SHIFT))&SCB_SHPR2_PRI_11_MASK) 04870 /* SHPR3 Bit Fields */ 04871 #define SCB_SHPR3_PRI_14_MASK 0xFF0000u 04872 #define SCB_SHPR3_PRI_14_SHIFT 16 04873 #define SCB_SHPR3_PRI_14(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR3_PRI_14_SHIFT))&SCB_SHPR3_PRI_14_MASK) 04874 #define SCB_SHPR3_PRI_15_MASK 0xFF000000u 04875 #define SCB_SHPR3_PRI_15_SHIFT 24 04876 #define SCB_SHPR3_PRI_15(x) (((uint32_t)(((uint32_t)(x))<<SCB_SHPR3_PRI_15_SHIFT))&SCB_SHPR3_PRI_15_MASK) 04877 /* SHCSR Bit Fields */ 04878 #define SCB_SHCSR_SVCALLPENDED_MASK 0x8000u 04879 #define SCB_SHCSR_SVCALLPENDED_SHIFT 15 04880 /* DFSR Bit Fields */ 04881 #define SCB_DFSR_HALTED_MASK 0x1u 04882 #define SCB_DFSR_HALTED_SHIFT 0 04883 #define SCB_DFSR_BKPT_MASK 0x2u 04884 #define SCB_DFSR_BKPT_SHIFT 1 04885 #define SCB_DFSR_DWTTRAP_MASK 0x4u 04886 #define SCB_DFSR_DWTTRAP_SHIFT 2 04887 #define SCB_DFSR_VCATCH_MASK 0x8u 04888 #define SCB_DFSR_VCATCH_SHIFT 3 04889 #define SCB_DFSR_EXTERNAL_MASK 0x10u 04890 #define SCB_DFSR_EXTERNAL_SHIFT 4 04891 04892 /*! 04893 * @} 04894 */ /* end of group SCB_Register_Masks */ 04895 04896 04897 /* SCB - Peripheral instance base addresses */ 04898 /** Peripheral SystemControl base pointer */ 04899 #define SystemControl_BASE_PTR ((SCB_MemMapPtr)0xE000E000u) 04900 /** Array initializer of SCB peripheral base pointers */ 04901 #define SCB_BASE_PTRS { SystemControl_BASE_PTR } 04902 04903 /* ---------------------------------------------------------------------------- 04904 -- SCB - Register accessor macros 04905 ---------------------------------------------------------------------------- */ 04906 04907 /*! 04908 * @addtogroup SCB_Register_Accessor_Macros SCB - Register accessor macros 04909 * @{ 04910 */ 04911 04912 04913 /* SCB - Register instance definitions */ 04914 /* SystemControl */ 04915 #define SCB_ACTLR SCB_ACTLR_REG(SystemControl_BASE_PTR) 04916 #define SCB_CPUID SCB_CPUID_REG(SystemControl_BASE_PTR) 04917 #define SCB_ICSR SCB_ICSR_REG(SystemControl_BASE_PTR) 04918 #define SCB_VTOR SCB_VTOR_REG(SystemControl_BASE_PTR) 04919 #define SCB_AIRCR SCB_AIRCR_REG(SystemControl_BASE_PTR) 04920 #define SCB_SCR SCB_SCR_REG(SystemControl_BASE_PTR) 04921 #define SCB_CCR SCB_CCR_REG(SystemControl_BASE_PTR) 04922 #define SCB_SHPR2 SCB_SHPR2_REG(SystemControl_BASE_PTR) 04923 #define SCB_SHPR3 SCB_SHPR3_REG(SystemControl_BASE_PTR) 04924 #define SCB_SHCSR SCB_SHCSR_REG(SystemControl_BASE_PTR) 04925 #define SCB_DFSR SCB_DFSR_REG(SystemControl_BASE_PTR) 04926 04927 /*! 04928 * @} 04929 */ /* end of group SCB_Register_Accessor_Macros */ 04930 04931 04932 /*! 04933 * @} 04934 */ /* end of group SCB_Peripheral */ 04935 04936 04937 /* ---------------------------------------------------------------------------- 04938 -- SIM 04939 ---------------------------------------------------------------------------- */ 04940 04941 /*! 04942 * @addtogroup SIM_Peripheral SIM 04943 * @{ 04944 */ 04945 04946 /** SIM - Peripheral register structure */ 04947 typedef struct SIM_MemMap { 04948 uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ 04949 uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ 04950 uint8_t RESERVED_0[4092]; 04951 uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ 04952 uint8_t RESERVED_1[4]; 04953 uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ 04954 uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ 04955 uint8_t RESERVED_2[4]; 04956 uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ 04957 uint8_t RESERVED_3[8]; 04958 uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ 04959 uint8_t RESERVED_4[12]; 04960 uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ 04961 uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ 04962 uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ 04963 uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ 04964 uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ 04965 uint8_t RESERVED_5[4]; 04966 uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ 04967 uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ 04968 uint8_t RESERVED_6[4]; 04969 uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ 04970 uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ 04971 uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ 04972 uint8_t RESERVED_7[156]; 04973 uint32_t COPC; /**< COP Control Register, offset: 0x1100 */ 04974 uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */ 04975 } volatile *SIM_MemMapPtr; 04976 04977 /* ---------------------------------------------------------------------------- 04978 -- SIM - Register accessor macros 04979 ---------------------------------------------------------------------------- */ 04980 04981 /*! 04982 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros 04983 * @{ 04984 */ 04985 04986 04987 /* SIM - Register accessors */ 04988 #define SIM_SOPT1_REG(base) ((base)->SOPT1) 04989 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) 04990 #define SIM_SOPT2_REG(base) ((base)->SOPT2) 04991 #define SIM_SOPT4_REG(base) ((base)->SOPT4) 04992 #define SIM_SOPT5_REG(base) ((base)->SOPT5) 04993 #define SIM_SOPT7_REG(base) ((base)->SOPT7) 04994 #define SIM_SDID_REG(base) ((base)->SDID) 04995 #define SIM_SCGC4_REG(base) ((base)->SCGC4) 04996 #define SIM_SCGC5_REG(base) ((base)->SCGC5) 04997 #define SIM_SCGC6_REG(base) ((base)->SCGC6) 04998 #define SIM_SCGC7_REG(base) ((base)->SCGC7) 04999 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) 05000 #define SIM_FCFG1_REG(base) ((base)->FCFG1) 05001 #define SIM_FCFG2_REG(base) ((base)->FCFG2) 05002 #define SIM_UIDMH_REG(base) ((base)->UIDMH) 05003 #define SIM_UIDML_REG(base) ((base)->UIDML) 05004 #define SIM_UIDL_REG(base) ((base)->UIDL) 05005 #define SIM_COPC_REG(base) ((base)->COPC) 05006 #define SIM_SRVCOP_REG(base) ((base)->SRVCOP) 05007 05008 /*! 05009 * @} 05010 */ /* end of group SIM_Register_Accessor_Macros */ 05011 05012 05013 /* ---------------------------------------------------------------------------- 05014 -- SIM Register Masks 05015 ---------------------------------------------------------------------------- */ 05016 05017 /*! 05018 * @addtogroup SIM_Register_Masks SIM Register Masks 05019 * @{ 05020 */ 05021 05022 /* SOPT1 Bit Fields */ 05023 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u 05024 #define SIM_SOPT1_OSC32KSEL_SHIFT 18 05025 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK) 05026 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u 05027 #define SIM_SOPT1_USBVSTBY_SHIFT 29 05028 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u 05029 #define SIM_SOPT1_USBSSTBY_SHIFT 30 05030 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u 05031 #define SIM_SOPT1_USBREGEN_SHIFT 31 05032 /* SOPT1CFG Bit Fields */ 05033 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u 05034 #define SIM_SOPT1CFG_URWE_SHIFT 24 05035 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u 05036 #define SIM_SOPT1CFG_UVSWE_SHIFT 25 05037 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u 05038 #define SIM_SOPT1CFG_USSWE_SHIFT 26 05039 /* SOPT2 Bit Fields */ 05040 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u 05041 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4 05042 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u 05043 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5 05044 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK) 05045 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u 05046 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16 05047 #define SIM_SOPT2_USBSRC_MASK 0x40000u 05048 #define SIM_SOPT2_USBSRC_SHIFT 18 05049 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u 05050 #define SIM_SOPT2_TPMSRC_SHIFT 24 05051 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK) 05052 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u 05053 #define SIM_SOPT2_UART0SRC_SHIFT 26 05054 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK) 05055 /* SOPT4 Bit Fields */ 05056 #define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u 05057 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18 05058 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u 05059 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20 05060 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u 05061 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24 05062 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u 05063 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25 05064 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u 05065 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26 05066 /* SOPT5 Bit Fields */ 05067 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u 05068 #define SIM_SOPT5_UART0TXSRC_SHIFT 0 05069 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK) 05070 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u 05071 #define SIM_SOPT5_UART0RXSRC_SHIFT 2 05072 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u 05073 #define SIM_SOPT5_UART1TXSRC_SHIFT 4 05074 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK) 05075 #define SIM_SOPT5_UART1RXSRC_MASK 0x40u 05076 #define SIM_SOPT5_UART1RXSRC_SHIFT 6 05077 #define SIM_SOPT5_UART0ODE_MASK 0x10000u 05078 #define SIM_SOPT5_UART0ODE_SHIFT 16 05079 #define SIM_SOPT5_UART1ODE_MASK 0x20000u 05080 #define SIM_SOPT5_UART1ODE_SHIFT 17 05081 #define SIM_SOPT5_UART2ODE_MASK 0x40000u 05082 #define SIM_SOPT5_UART2ODE_SHIFT 18 05083 /* SOPT7 Bit Fields */ 05084 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu 05085 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 05086 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK) 05087 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u 05088 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4 05089 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u 05090 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7 05091 /* SDID Bit Fields */ 05092 #define SIM_SDID_PINID_MASK 0xFu 05093 #define SIM_SDID_PINID_SHIFT 0 05094 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK) 05095 #define SIM_SDID_DIEID_MASK 0xF80u 05096 #define SIM_SDID_DIEID_SHIFT 7 05097 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK) 05098 #define SIM_SDID_REVID_MASK 0xF000u 05099 #define SIM_SDID_REVID_SHIFT 12 05100 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK) 05101 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u 05102 #define SIM_SDID_SRAMSIZE_SHIFT 16 05103 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK) 05104 #define SIM_SDID_SERIESID_MASK 0xF00000u 05105 #define SIM_SDID_SERIESID_SHIFT 20 05106 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK) 05107 #define SIM_SDID_SUBFAMID_MASK 0xF000000u 05108 #define SIM_SDID_SUBFAMID_SHIFT 24 05109 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK) 05110 #define SIM_SDID_FAMID_MASK 0xF0000000u 05111 #define SIM_SDID_FAMID_SHIFT 28 05112 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK) 05113 /* SCGC4 Bit Fields */ 05114 #define SIM_SCGC4_I2C0_MASK 0x40u 05115 #define SIM_SCGC4_I2C0_SHIFT 6 05116 #define SIM_SCGC4_I2C1_MASK 0x80u 05117 #define SIM_SCGC4_I2C1_SHIFT 7 05118 #define SIM_SCGC4_UART0_MASK 0x400u 05119 #define SIM_SCGC4_UART0_SHIFT 10 05120 #define SIM_SCGC4_UART1_MASK 0x800u 05121 #define SIM_SCGC4_UART1_SHIFT 11 05122 #define SIM_SCGC4_UART2_MASK 0x1000u 05123 #define SIM_SCGC4_UART2_SHIFT 12 05124 #define SIM_SCGC4_USBOTG_MASK 0x40000u 05125 #define SIM_SCGC4_USBOTG_SHIFT 18 05126 #define SIM_SCGC4_CMP_MASK 0x80000u 05127 #define SIM_SCGC4_CMP_SHIFT 19 05128 #define SIM_SCGC4_SPI0_MASK 0x400000u 05129 #define SIM_SCGC4_SPI0_SHIFT 22 05130 #define SIM_SCGC4_SPI1_MASK 0x800000u 05131 #define SIM_SCGC4_SPI1_SHIFT 23 05132 /* SCGC5 Bit Fields */ 05133 #define SIM_SCGC5_LPTMR_MASK 0x1u 05134 #define SIM_SCGC5_LPTMR_SHIFT 0 05135 #define SIM_SCGC5_TSI_MASK 0x20u 05136 #define SIM_SCGC5_TSI_SHIFT 5 05137 #define SIM_SCGC5_PORTA_MASK 0x200u 05138 #define SIM_SCGC5_PORTA_SHIFT 9 05139 #define SIM_SCGC5_PORTB_MASK 0x400u 05140 #define SIM_SCGC5_PORTB_SHIFT 10 05141 #define SIM_SCGC5_PORTC_MASK 0x800u 05142 #define SIM_SCGC5_PORTC_SHIFT 11 05143 #define SIM_SCGC5_PORTD_MASK 0x1000u 05144 #define SIM_SCGC5_PORTD_SHIFT 12 05145 #define SIM_SCGC5_PORTE_MASK 0x2000u 05146 #define SIM_SCGC5_PORTE_SHIFT 13 05147 /* SCGC6 Bit Fields */ 05148 #define SIM_SCGC6_FTF_MASK 0x1u 05149 #define SIM_SCGC6_FTF_SHIFT 0 05150 #define SIM_SCGC6_DMAMUX_MASK 0x2u 05151 #define SIM_SCGC6_DMAMUX_SHIFT 1 05152 #define SIM_SCGC6_PIT_MASK 0x800000u 05153 #define SIM_SCGC6_PIT_SHIFT 23 05154 #define SIM_SCGC6_TPM0_MASK 0x1000000u 05155 #define SIM_SCGC6_TPM0_SHIFT 24 05156 #define SIM_SCGC6_TPM1_MASK 0x2000000u 05157 #define SIM_SCGC6_TPM1_SHIFT 25 05158 #define SIM_SCGC6_TPM2_MASK 0x4000000u 05159 #define SIM_SCGC6_TPM2_SHIFT 26 05160 #define SIM_SCGC6_ADC0_MASK 0x8000000u 05161 #define SIM_SCGC6_ADC0_SHIFT 27 05162 #define SIM_SCGC6_RTC_MASK 0x20000000u 05163 #define SIM_SCGC6_RTC_SHIFT 29 05164 #define SIM_SCGC6_DAC0_MASK 0x80000000u 05165 #define SIM_SCGC6_DAC0_SHIFT 31 05166 /* SCGC7 Bit Fields */ 05167 #define SIM_SCGC7_DMA_MASK 0x100u 05168 #define SIM_SCGC7_DMA_SHIFT 8 05169 /* CLKDIV1 Bit Fields */ 05170 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u 05171 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16 05172 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK) 05173 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u 05174 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28 05175 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK) 05176 /* FCFG1 Bit Fields */ 05177 #define SIM_FCFG1_FLASHDIS_MASK 0x1u 05178 #define SIM_FCFG1_FLASHDIS_SHIFT 0 05179 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u 05180 #define SIM_FCFG1_FLASHDOZE_SHIFT 1 05181 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u 05182 #define SIM_FCFG1_PFSIZE_SHIFT 24 05183 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK) 05184 /* FCFG2 Bit Fields */ 05185 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u 05186 #define SIM_FCFG2_MAXADDR0_SHIFT 24 05187 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK) 05188 /* UIDMH Bit Fields */ 05189 #define SIM_UIDMH_UID_MASK 0xFFFFu 05190 #define SIM_UIDMH_UID_SHIFT 0 05191 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK) 05192 /* UIDML Bit Fields */ 05193 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu 05194 #define SIM_UIDML_UID_SHIFT 0 05195 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK) 05196 /* UIDL Bit Fields */ 05197 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu 05198 #define SIM_UIDL_UID_SHIFT 0 05199 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK) 05200 /* COPC Bit Fields */ 05201 #define SIM_COPC_COPW_MASK 0x1u 05202 #define SIM_COPC_COPW_SHIFT 0 05203 #define SIM_COPC_COPCLKS_MASK 0x2u 05204 #define SIM_COPC_COPCLKS_SHIFT 1 05205 #define SIM_COPC_COPT_MASK 0xCu 05206 #define SIM_COPC_COPT_SHIFT 2 05207 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK) 05208 /* SRVCOP Bit Fields */ 05209 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu 05210 #define SIM_SRVCOP_SRVCOP_SHIFT 0 05211 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK) 05212 05213 /*! 05214 * @} 05215 */ /* end of group SIM_Register_Masks */ 05216 05217 05218 /* SIM - Peripheral instance base addresses */ 05219 /** Peripheral SIM base pointer */ 05220 #define SIM_BASE_PTR ((SIM_MemMapPtr)0x40047000u) 05221 /** Array initializer of SIM peripheral base pointers */ 05222 #define SIM_BASE_PTRS { SIM_BASE_PTR } 05223 05224 /* ---------------------------------------------------------------------------- 05225 -- SIM - Register accessor macros 05226 ---------------------------------------------------------------------------- */ 05227 05228 /*! 05229 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros 05230 * @{ 05231 */ 05232 05233 05234 /* SIM - Register instance definitions */ 05235 /* SIM */ 05236 #define SIM_SOPT1 SIM_SOPT1_REG(SIM_BASE_PTR) 05237 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM_BASE_PTR) 05238 #define SIM_SOPT2 SIM_SOPT2_REG(SIM_BASE_PTR) 05239 #define SIM_SOPT4 SIM_SOPT4_REG(SIM_BASE_PTR) 05240 #define SIM_SOPT5 SIM_SOPT5_REG(SIM_BASE_PTR) 05241 #define SIM_SOPT7 SIM_SOPT7_REG(SIM_BASE_PTR) 05242 #define SIM_SDID SIM_SDID_REG(SIM_BASE_PTR) 05243 #define SIM_SCGC4 SIM_SCGC4_REG(SIM_BASE_PTR) 05244 #define SIM_SCGC5 SIM_SCGC5_REG(SIM_BASE_PTR) 05245 #define SIM_SCGC6 SIM_SCGC6_REG(SIM_BASE_PTR) 05246 #define SIM_SCGC7 SIM_SCGC7_REG(SIM_BASE_PTR) 05247 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM_BASE_PTR) 05248 #define SIM_FCFG1 SIM_FCFG1_REG(SIM_BASE_PTR) 05249 #define SIM_FCFG2 SIM_FCFG2_REG(SIM_BASE_PTR) 05250 #define SIM_UIDMH SIM_UIDMH_REG(SIM_BASE_PTR) 05251 #define SIM_UIDML SIM_UIDML_REG(SIM_BASE_PTR) 05252 #define SIM_UIDL SIM_UIDL_REG(SIM_BASE_PTR) 05253 #define SIM_COPC SIM_COPC_REG(SIM_BASE_PTR) 05254 #define SIM_SRVCOP SIM_SRVCOP_REG(SIM_BASE_PTR) 05255 05256 /*! 05257 * @} 05258 */ /* end of group SIM_Register_Accessor_Macros */ 05259 05260 05261 /*! 05262 * @} 05263 */ /* end of group SIM_Peripheral */ 05264 05265 05266 /* ---------------------------------------------------------------------------- 05267 -- SMC 05268 ---------------------------------------------------------------------------- */ 05269 05270 /*! 05271 * @addtogroup SMC_Peripheral SMC 05272 * @{ 05273 */ 05274 05275 /** SMC - Peripheral register structure */ 05276 typedef struct SMC_MemMap { 05277 uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ 05278 uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ 05279 uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */ 05280 uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ 05281 } volatile *SMC_MemMapPtr; 05282 05283 /* ---------------------------------------------------------------------------- 05284 -- SMC - Register accessor macros 05285 ---------------------------------------------------------------------------- */ 05286 05287 /*! 05288 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros 05289 * @{ 05290 */ 05291 05292 05293 /* SMC - Register accessors */ 05294 #define SMC_PMPROT_REG(base) ((base)->PMPROT) 05295 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL) 05296 #define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL) 05297 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT) 05298 05299 /*! 05300 * @} 05301 */ /* end of group SMC_Register_Accessor_Macros */ 05302 05303 05304 /* ---------------------------------------------------------------------------- 05305 -- SMC Register Masks 05306 ---------------------------------------------------------------------------- */ 05307 05308 /*! 05309 * @addtogroup SMC_Register_Masks SMC Register Masks 05310 * @{ 05311 */ 05312 05313 /* PMPROT Bit Fields */ 05314 #define SMC_PMPROT_AVLLS_MASK 0x2u 05315 #define SMC_PMPROT_AVLLS_SHIFT 1 05316 #define SMC_PMPROT_ALLS_MASK 0x8u 05317 #define SMC_PMPROT_ALLS_SHIFT 3 05318 #define SMC_PMPROT_AVLP_MASK 0x20u 05319 #define SMC_PMPROT_AVLP_SHIFT 5 05320 /* PMCTRL Bit Fields */ 05321 #define SMC_PMCTRL_STOPM_MASK 0x7u 05322 #define SMC_PMCTRL_STOPM_SHIFT 0 05323 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK) 05324 #define SMC_PMCTRL_STOPA_MASK 0x8u 05325 #define SMC_PMCTRL_STOPA_SHIFT 3 05326 #define SMC_PMCTRL_RUNM_MASK 0x60u 05327 #define SMC_PMCTRL_RUNM_SHIFT 5 05328 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK) 05329 /* STOPCTRL Bit Fields */ 05330 #define SMC_STOPCTRL_VLLSM_MASK 0x7u 05331 #define SMC_STOPCTRL_VLLSM_SHIFT 0 05332 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK) 05333 #define SMC_STOPCTRL_PORPO_MASK 0x20u 05334 #define SMC_STOPCTRL_PORPO_SHIFT 5 05335 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u 05336 #define SMC_STOPCTRL_PSTOPO_SHIFT 6 05337 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK) 05338 /* PMSTAT Bit Fields */ 05339 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu 05340 #define SMC_PMSTAT_PMSTAT_SHIFT 0 05341 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK) 05342 05343 /*! 05344 * @} 05345 */ /* end of group SMC_Register_Masks */ 05346 05347 05348 /* SMC - Peripheral instance base addresses */ 05349 /** Peripheral SMC base pointer */ 05350 #define SMC_BASE_PTR ((SMC_MemMapPtr)0x4007E000u) 05351 /** Array initializer of SMC peripheral base pointers */ 05352 #define SMC_BASE_PTRS { SMC_BASE_PTR } 05353 05354 /* ---------------------------------------------------------------------------- 05355 -- SMC - Register accessor macros 05356 ---------------------------------------------------------------------------- */ 05357 05358 /*! 05359 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros 05360 * @{ 05361 */ 05362 05363 05364 /* SMC - Register instance definitions */ 05365 /* SMC */ 05366 #define SMC_PMPROT SMC_PMPROT_REG(SMC_BASE_PTR) 05367 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC_BASE_PTR) 05368 #define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC_BASE_PTR) 05369 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC_BASE_PTR) 05370 05371 /*! 05372 * @} 05373 */ /* end of group SMC_Register_Accessor_Macros */ 05374 05375 05376 /*! 05377 * @} 05378 */ /* end of group SMC_Peripheral */ 05379 05380 05381 /* ---------------------------------------------------------------------------- 05382 -- SPI 05383 ---------------------------------------------------------------------------- */ 05384 05385 /*! 05386 * @addtogroup SPI_Peripheral SPI 05387 * @{ 05388 */ 05389 05390 /** SPI - Peripheral register structure */ 05391 typedef struct SPI_MemMap { 05392 uint8_t C1; /**< SPI control register 1, offset: 0x0 */ 05393 uint8_t C2; /**< SPI control register 2, offset: 0x1 */ 05394 uint8_t BR; /**< SPI baud rate register, offset: 0x2 */ 05395 uint8_t S; /**< SPI status register, offset: 0x3 */ 05396 uint8_t RESERVED_0[1]; 05397 uint8_t D; /**< SPI data register, offset: 0x5 */ 05398 uint8_t RESERVED_1[1]; 05399 uint8_t M; /**< SPI match register, offset: 0x7 */ 05400 } volatile *SPI_MemMapPtr; 05401 05402 /* ---------------------------------------------------------------------------- 05403 -- SPI - Register accessor macros 05404 ---------------------------------------------------------------------------- */ 05405 05406 /*! 05407 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros 05408 * @{ 05409 */ 05410 05411 05412 /* SPI - Register accessors */ 05413 #define SPI_C1_REG(base) ((base)->C1) 05414 #define SPI_C2_REG(base) ((base)->C2) 05415 #define SPI_BR_REG(base) ((base)->BR) 05416 #define SPI_S_REG(base) ((base)->S) 05417 #define SPI_D_REG(base) ((base)->D) 05418 #define SPI_M_REG(base) ((base)->M) 05419 05420 /*! 05421 * @} 05422 */ /* end of group SPI_Register_Accessor_Macros */ 05423 05424 05425 /* ---------------------------------------------------------------------------- 05426 -- SPI Register Masks 05427 ---------------------------------------------------------------------------- */ 05428 05429 /*! 05430 * @addtogroup SPI_Register_Masks SPI Register Masks 05431 * @{ 05432 */ 05433 05434 /* C1 Bit Fields */ 05435 #define SPI_C1_LSBFE_MASK 0x1u 05436 #define SPI_C1_LSBFE_SHIFT 0 05437 #define SPI_C1_SSOE_MASK 0x2u 05438 #define SPI_C1_SSOE_SHIFT 1 05439 #define SPI_C1_CPHA_MASK 0x4u 05440 #define SPI_C1_CPHA_SHIFT 2 05441 #define SPI_C1_CPOL_MASK 0x8u 05442 #define SPI_C1_CPOL_SHIFT 3 05443 #define SPI_C1_MSTR_MASK 0x10u 05444 #define SPI_C1_MSTR_SHIFT 4 05445 #define SPI_C1_SPTIE_MASK 0x20u 05446 #define SPI_C1_SPTIE_SHIFT 5 05447 #define SPI_C1_SPE_MASK 0x40u 05448 #define SPI_C1_SPE_SHIFT 6 05449 #define SPI_C1_SPIE_MASK 0x80u 05450 #define SPI_C1_SPIE_SHIFT 7 05451 /* C2 Bit Fields */ 05452 #define SPI_C2_SPC0_MASK 0x1u 05453 #define SPI_C2_SPC0_SHIFT 0 05454 #define SPI_C2_SPISWAI_MASK 0x2u 05455 #define SPI_C2_SPISWAI_SHIFT 1 05456 #define SPI_C2_RXDMAE_MASK 0x4u 05457 #define SPI_C2_RXDMAE_SHIFT 2 05458 #define SPI_C2_BIDIROE_MASK 0x8u 05459 #define SPI_C2_BIDIROE_SHIFT 3 05460 #define SPI_C2_MODFEN_MASK 0x10u 05461 #define SPI_C2_MODFEN_SHIFT 4 05462 #define SPI_C2_TXDMAE_MASK 0x20u 05463 #define SPI_C2_TXDMAE_SHIFT 5 05464 #define SPI_C2_SPMIE_MASK 0x80u 05465 #define SPI_C2_SPMIE_SHIFT 7 05466 /* BR Bit Fields */ 05467 #define SPI_BR_SPR_MASK 0xFu 05468 #define SPI_BR_SPR_SHIFT 0 05469 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK) 05470 #define SPI_BR_SPPR_MASK 0x70u 05471 #define SPI_BR_SPPR_SHIFT 4 05472 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK) 05473 /* S Bit Fields */ 05474 #define SPI_S_MODF_MASK 0x10u 05475 #define SPI_S_MODF_SHIFT 4 05476 #define SPI_S_SPTEF_MASK 0x20u 05477 #define SPI_S_SPTEF_SHIFT 5 05478 #define SPI_S_SPMF_MASK 0x40u 05479 #define SPI_S_SPMF_SHIFT 6 05480 #define SPI_S_SPRF_MASK 0x80u 05481 #define SPI_S_SPRF_SHIFT 7 05482 /* D Bit Fields */ 05483 #define SPI_D_Bits_MASK 0xFFu 05484 #define SPI_D_Bits_SHIFT 0 05485 #define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK) 05486 /* M Bit Fields */ 05487 #define SPI_M_Bits_MASK 0xFFu 05488 #define SPI_M_Bits_SHIFT 0 05489 #define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK) 05490 05491 /*! 05492 * @} 05493 */ /* end of group SPI_Register_Masks */ 05494 05495 05496 /* SPI - Peripheral instance base addresses */ 05497 /** Peripheral SPI0 base pointer */ 05498 #define SPI0_BASE_PTR ((SPI_MemMapPtr)0x40076000u) 05499 /** Peripheral SPI1 base pointer */ 05500 #define SPI1_BASE_PTR ((SPI_MemMapPtr)0x40077000u) 05501 /** Array initializer of SPI peripheral base pointers */ 05502 #define SPI_BASE_PTRS { SPI0_BASE_PTR, SPI1_BASE_PTR } 05503 05504 /* ---------------------------------------------------------------------------- 05505 -- SPI - Register accessor macros 05506 ---------------------------------------------------------------------------- */ 05507 05508 /*! 05509 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros 05510 * @{ 05511 */ 05512 05513 05514 /* SPI - Register instance definitions */ 05515 /* SPI0 */ 05516 #define SPI0_C1 SPI_C1_REG(SPI0_BASE_PTR) 05517 #define SPI0_C2 SPI_C2_REG(SPI0_BASE_PTR) 05518 #define SPI0_BR SPI_BR_REG(SPI0_BASE_PTR) 05519 #define SPI0_S SPI_S_REG(SPI0_BASE_PTR) 05520 #define SPI0_D SPI_D_REG(SPI0_BASE_PTR) 05521 #define SPI0_M SPI_M_REG(SPI0_BASE_PTR) 05522 /* SPI1 */ 05523 #define SPI1_C1 SPI_C1_REG(SPI1_BASE_PTR) 05524 #define SPI1_C2 SPI_C2_REG(SPI1_BASE_PTR) 05525 #define SPI1_BR SPI_BR_REG(SPI1_BASE_PTR) 05526 #define SPI1_S SPI_S_REG(SPI1_BASE_PTR) 05527 #define SPI1_D SPI_D_REG(SPI1_BASE_PTR) 05528 #define SPI1_M SPI_M_REG(SPI1_BASE_PTR) 05529 05530 /*! 05531 * @} 05532 */ /* end of group SPI_Register_Accessor_Macros */ 05533 05534 05535 /*! 05536 * @} 05537 */ /* end of group SPI_Peripheral */ 05538 05539 05540 /* ---------------------------------------------------------------------------- 05541 -- SysTick 05542 ---------------------------------------------------------------------------- */ 05543 05544 /*! 05545 * @addtogroup SysTick_Peripheral SysTick 05546 * @{ 05547 */ 05548 05549 /** SysTick - Peripheral register structure */ 05550 typedef struct SysTick_MemMap { 05551 uint32_t CSR; /**< SysTick Control and Status Register, offset: 0x0 */ 05552 uint32_t RVR; /**< SysTick Reload Value Register, offset: 0x4 */ 05553 uint32_t CVR; /**< SysTick Current Value Register, offset: 0x8 */ 05554 uint32_t CALIB; /**< SysTick Calibration Value Register, offset: 0xC */ 05555 } volatile *SysTick_MemMapPtr; 05556 05557 /* ---------------------------------------------------------------------------- 05558 -- SysTick - Register accessor macros 05559 ---------------------------------------------------------------------------- */ 05560 05561 /*! 05562 * @addtogroup SysTick_Register_Accessor_Macros SysTick - Register accessor macros 05563 * @{ 05564 */ 05565 05566 05567 /* SysTick - Register accessors */ 05568 #define SysTick_CSR_REG(base) ((base)->CSR) 05569 #define SysTick_RVR_REG(base) ((base)->RVR) 05570 #define SysTick_CVR_REG(base) ((base)->CVR) 05571 #define SysTick_CALIB_REG(base) ((base)->CALIB) 05572 05573 /*! 05574 * @} 05575 */ /* end of group SysTick_Register_Accessor_Macros */ 05576 05577 05578 /* ---------------------------------------------------------------------------- 05579 -- SysTick Register Masks 05580 ---------------------------------------------------------------------------- */ 05581 05582 /*! 05583 * @addtogroup SysTick_Register_Masks SysTick Register Masks 05584 * @{ 05585 */ 05586 05587 /* CSR Bit Fields */ 05588 #define SysTick_CSR_ENABLE_MASK 0x1u 05589 #define SysTick_CSR_ENABLE_SHIFT 0 05590 #define SysTick_CSR_TICKINT_MASK 0x2u 05591 #define SysTick_CSR_TICKINT_SHIFT 1 05592 #define SysTick_CSR_CLKSOURCE_MASK 0x4u 05593 #define SysTick_CSR_CLKSOURCE_SHIFT 2 05594 #define SysTick_CSR_COUNTFLAG_MASK 0x10000u 05595 #define SysTick_CSR_COUNTFLAG_SHIFT 16 05596 /* RVR Bit Fields */ 05597 #define SysTick_RVR_RELOAD_MASK 0xFFFFFFu 05598 #define SysTick_RVR_RELOAD_SHIFT 0 05599 #define SysTick_RVR_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<SysTick_RVR_RELOAD_SHIFT))&SysTick_RVR_RELOAD_MASK) 05600 /* CVR Bit Fields */ 05601 #define SysTick_CVR_CURRENT_MASK 0xFFFFFFu 05602 #define SysTick_CVR_CURRENT_SHIFT 0 05603 #define SysTick_CVR_CURRENT(x) (((uint32_t)(((uint32_t)(x))<<SysTick_CVR_CURRENT_SHIFT))&SysTick_CVR_CURRENT_MASK) 05604 /* CALIB Bit Fields */ 05605 #define SysTick_CALIB_TENMS_MASK 0xFFFFFFu 05606 #define SysTick_CALIB_TENMS_SHIFT 0 05607 #define SysTick_CALIB_TENMS(x) (((uint32_t)(((uint32_t)(x))<<SysTick_CALIB_TENMS_SHIFT))&SysTick_CALIB_TENMS_MASK) 05608 #define SysTick_CALIB_SKEW_MASK 0x40000000u 05609 #define SysTick_CALIB_SKEW_SHIFT 30 05610 #define SysTick_CALIB_NOREF_MASK 0x80000000u 05611 #define SysTick_CALIB_NOREF_SHIFT 31 05612 05613 /*! 05614 * @} 05615 */ /* end of group SysTick_Register_Masks */ 05616 05617 05618 /* SysTick - Peripheral instance base addresses */ 05619 /** Peripheral SysTick base pointer */ 05620 #define SysTick_BASE_PTR ((SysTick_MemMapPtr)0xE000E010u) 05621 /** Array initializer of SysTick peripheral base pointers */ 05622 #define SysTick_BASE_PTRS { SysTick_BASE_PTR } 05623 05624 /* ---------------------------------------------------------------------------- 05625 -- SysTick - Register accessor macros 05626 ---------------------------------------------------------------------------- */ 05627 05628 /*! 05629 * @addtogroup SysTick_Register_Accessor_Macros SysTick - Register accessor macros 05630 * @{ 05631 */ 05632 05633 05634 /* SysTick - Register instance definitions */ 05635 /* SysTick */ 05636 #define SYST_CSR SysTick_CSR_REG(SysTick_BASE_PTR) 05637 #define SYST_RVR SysTick_RVR_REG(SysTick_BASE_PTR) 05638 #define SYST_CVR SysTick_CVR_REG(SysTick_BASE_PTR) 05639 #define SYST_CALIB SysTick_CALIB_REG(SysTick_BASE_PTR) 05640 05641 /*! 05642 * @} 05643 */ /* end of group SysTick_Register_Accessor_Macros */ 05644 05645 05646 /*! 05647 * @} 05648 */ /* end of group SysTick_Peripheral */ 05649 05650 05651 /* ---------------------------------------------------------------------------- 05652 -- TPM 05653 ---------------------------------------------------------------------------- */ 05654 05655 /*! 05656 * @addtogroup TPM_Peripheral TPM 05657 * @{ 05658 */ 05659 05660 /** TPM - Peripheral register structure */ 05661 typedef struct TPM_MemMap { 05662 uint32_t SC; /**< Status and Control, offset: 0x0 */ 05663 uint32_t CNT; /**< Counter, offset: 0x4 */ 05664 uint32_t MOD; /**< Modulo, offset: 0x8 */ 05665 struct { /* offset: 0xC, array step: 0x8 */ 05666 uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ 05667 uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ 05668 } CONTROLS[6]; 05669 uint8_t RESERVED_0[20]; 05670 uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ 05671 uint8_t RESERVED_1[48]; 05672 uint32_t CONF; /**< Configuration, offset: 0x84 */ 05673 } volatile *TPM_MemMapPtr; 05674 05675 /* ---------------------------------------------------------------------------- 05676 -- TPM - Register accessor macros 05677 ---------------------------------------------------------------------------- */ 05678 05679 /*! 05680 * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros 05681 * @{ 05682 */ 05683 05684 05685 /* TPM - Register accessors */ 05686 #define TPM_SC_REG(base) ((base)->SC) 05687 #define TPM_CNT_REG(base) ((base)->CNT) 05688 #define TPM_MOD_REG(base) ((base)->MOD) 05689 #define TPM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) 05690 #define TPM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) 05691 #define TPM_STATUS_REG(base) ((base)->STATUS) 05692 #define TPM_CONF_REG(base) ((base)->CONF) 05693 05694 /*! 05695 * @} 05696 */ /* end of group TPM_Register_Accessor_Macros */ 05697 05698 05699 /* ---------------------------------------------------------------------------- 05700 -- TPM Register Masks 05701 ---------------------------------------------------------------------------- */ 05702 05703 /*! 05704 * @addtogroup TPM_Register_Masks TPM Register Masks 05705 * @{ 05706 */ 05707 05708 /* SC Bit Fields */ 05709 #define TPM_SC_PS_MASK 0x7u 05710 #define TPM_SC_PS_SHIFT 0 05711 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK) 05712 #define TPM_SC_CMOD_MASK 0x18u 05713 #define TPM_SC_CMOD_SHIFT 3 05714 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK) 05715 #define TPM_SC_CPWMS_MASK 0x20u 05716 #define TPM_SC_CPWMS_SHIFT 5 05717 #define TPM_SC_TOIE_MASK 0x40u 05718 #define TPM_SC_TOIE_SHIFT 6 05719 #define TPM_SC_TOF_MASK 0x80u 05720 #define TPM_SC_TOF_SHIFT 7 05721 #define TPM_SC_DMA_MASK 0x100u 05722 #define TPM_SC_DMA_SHIFT 8 05723 /* CNT Bit Fields */ 05724 #define TPM_CNT_COUNT_MASK 0xFFFFu 05725 #define TPM_CNT_COUNT_SHIFT 0 05726 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK) 05727 /* MOD Bit Fields */ 05728 #define TPM_MOD_MOD_MASK 0xFFFFu 05729 #define TPM_MOD_MOD_SHIFT 0 05730 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK) 05731 /* CnSC Bit Fields */ 05732 #define TPM_CnSC_DMA_MASK 0x1u 05733 #define TPM_CnSC_DMA_SHIFT 0 05734 #define TPM_CnSC_ELSA_MASK 0x4u 05735 #define TPM_CnSC_ELSA_SHIFT 2 05736 #define TPM_CnSC_ELSB_MASK 0x8u 05737 #define TPM_CnSC_ELSB_SHIFT 3 05738 #define TPM_CnSC_MSA_MASK 0x10u 05739 #define TPM_CnSC_MSA_SHIFT 4 05740 #define TPM_CnSC_MSB_MASK 0x20u 05741 #define TPM_CnSC_MSB_SHIFT 5 05742 #define TPM_CnSC_CHIE_MASK 0x40u 05743 #define TPM_CnSC_CHIE_SHIFT 6 05744 #define TPM_CnSC_CHF_MASK 0x80u 05745 #define TPM_CnSC_CHF_SHIFT 7 05746 /* CnV Bit Fields */ 05747 #define TPM_CnV_VAL_MASK 0xFFFFu 05748 #define TPM_CnV_VAL_SHIFT 0 05749 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK) 05750 /* STATUS Bit Fields */ 05751 #define TPM_STATUS_CH0F_MASK 0x1u 05752 #define TPM_STATUS_CH0F_SHIFT 0 05753 #define TPM_STATUS_CH1F_MASK 0x2u 05754 #define TPM_STATUS_CH1F_SHIFT 1 05755 #define TPM_STATUS_CH2F_MASK 0x4u 05756 #define TPM_STATUS_CH2F_SHIFT 2 05757 #define TPM_STATUS_CH3F_MASK 0x8u 05758 #define TPM_STATUS_CH3F_SHIFT 3 05759 #define TPM_STATUS_CH4F_MASK 0x10u 05760 #define TPM_STATUS_CH4F_SHIFT 4 05761 #define TPM_STATUS_CH5F_MASK 0x20u 05762 #define TPM_STATUS_CH5F_SHIFT 5 05763 #define TPM_STATUS_TOF_MASK 0x100u 05764 #define TPM_STATUS_TOF_SHIFT 8 05765 /* CONF Bit Fields */ 05766 #define TPM_CONF_DOZEEN_MASK 0x20u 05767 #define TPM_CONF_DOZEEN_SHIFT 5 05768 #define TPM_CONF_DBGMODE_MASK 0xC0u 05769 #define TPM_CONF_DBGMODE_SHIFT 6 05770 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK) 05771 #define TPM_CONF_GTBEEN_MASK 0x200u 05772 #define TPM_CONF_GTBEEN_SHIFT 9 05773 #define TPM_CONF_CSOT_MASK 0x10000u 05774 #define TPM_CONF_CSOT_SHIFT 16 05775 #define TPM_CONF_CSOO_MASK 0x20000u 05776 #define TPM_CONF_CSOO_SHIFT 17 05777 #define TPM_CONF_CROT_MASK 0x40000u 05778 #define TPM_CONF_CROT_SHIFT 18 05779 #define TPM_CONF_TRGSEL_MASK 0xF000000u 05780 #define TPM_CONF_TRGSEL_SHIFT 24 05781 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK) 05782 05783 /*! 05784 * @} 05785 */ /* end of group TPM_Register_Masks */ 05786 05787 05788 /* TPM - Peripheral instance base addresses */ 05789 /** Peripheral TPM0 base pointer */ 05790 #define TPM0_BASE_PTR ((TPM_MemMapPtr)0x40038000u) 05791 /** Peripheral TPM1 base pointer */ 05792 #define TPM1_BASE_PTR ((TPM_MemMapPtr)0x40039000u) 05793 /** Peripheral TPM2 base pointer */ 05794 #define TPM2_BASE_PTR ((TPM_MemMapPtr)0x4003A000u) 05795 /** Array initializer of TPM peripheral base pointers */ 05796 #define TPM_BASE_PTRS { TPM0_BASE_PTR, TPM1_BASE_PTR, TPM2_BASE_PTR } 05797 05798 /* ---------------------------------------------------------------------------- 05799 -- TPM - Register accessor macros 05800 ---------------------------------------------------------------------------- */ 05801 05802 /*! 05803 * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros 05804 * @{ 05805 */ 05806 05807 05808 /* TPM - Register instance definitions */ 05809 /* TPM0 */ 05810 #define TPM0_SC TPM_SC_REG(TPM0_BASE_PTR) 05811 #define TPM0_CNT TPM_CNT_REG(TPM0_BASE_PTR) 05812 #define TPM0_MOD TPM_MOD_REG(TPM0_BASE_PTR) 05813 #define TPM0_C0SC TPM_CnSC_REG(TPM0_BASE_PTR,0) 05814 #define TPM0_C0V TPM_CnV_REG(TPM0_BASE_PTR,0) 05815 #define TPM0_C1SC TPM_CnSC_REG(TPM0_BASE_PTR,1) 05816 #define TPM0_C1V TPM_CnV_REG(TPM0_BASE_PTR,1) 05817 #define TPM0_C2SC TPM_CnSC_REG(TPM0_BASE_PTR,2) 05818 #define TPM0_C2V TPM_CnV_REG(TPM0_BASE_PTR,2) 05819 #define TPM0_C3SC TPM_CnSC_REG(TPM0_BASE_PTR,3) 05820 #define TPM0_C3V TPM_CnV_REG(TPM0_BASE_PTR,3) 05821 #define TPM0_C4SC TPM_CnSC_REG(TPM0_BASE_PTR,4) 05822 #define TPM0_C4V TPM_CnV_REG(TPM0_BASE_PTR,4) 05823 #define TPM0_C5SC TPM_CnSC_REG(TPM0_BASE_PTR,5) 05824 #define TPM0_C5V TPM_CnV_REG(TPM0_BASE_PTR,5) 05825 #define TPM0_STATUS TPM_STATUS_REG(TPM0_BASE_PTR) 05826 #define TPM0_CONF TPM_CONF_REG(TPM0_BASE_PTR) 05827 /* TPM1 */ 05828 #define TPM1_SC TPM_SC_REG(TPM1_BASE_PTR) 05829 #define TPM1_CNT TPM_CNT_REG(TPM1_BASE_PTR) 05830 #define TPM1_MOD TPM_MOD_REG(TPM1_BASE_PTR) 05831 #define TPM1_C0SC TPM_CnSC_REG(TPM1_BASE_PTR,0) 05832 #define TPM1_C0V TPM_CnV_REG(TPM1_BASE_PTR,0) 05833 #define TPM1_C1SC TPM_CnSC_REG(TPM1_BASE_PTR,1) 05834 #define TPM1_C1V TPM_CnV_REG(TPM1_BASE_PTR,1) 05835 #define TPM1_STATUS TPM_STATUS_REG(TPM1_BASE_PTR) 05836 #define TPM1_CONF TPM_CONF_REG(TPM1_BASE_PTR) 05837 /* TPM2 */ 05838 #define TPM2_SC TPM_SC_REG(TPM2_BASE_PTR) 05839 #define TPM2_CNT TPM_CNT_REG(TPM2_BASE_PTR) 05840 #define TPM2_MOD TPM_MOD_REG(TPM2_BASE_PTR) 05841 #define TPM2_C0SC TPM_CnSC_REG(TPM2_BASE_PTR,0) 05842 #define TPM2_C0V TPM_CnV_REG(TPM2_BASE_PTR,0) 05843 #define TPM2_C1SC TPM_CnSC_REG(TPM2_BASE_PTR,1) 05844 #define TPM2_C1V TPM_CnV_REG(TPM2_BASE_PTR,1) 05845 #define TPM2_STATUS TPM_STATUS_REG(TPM2_BASE_PTR) 05846 #define TPM2_CONF TPM_CONF_REG(TPM2_BASE_PTR) 05847 05848 /* TPM - Register array accessors */ 05849 #define TPM0_CnSC(index) TPM_CnSC_REG(TPM0_BASE_PTR,index) 05850 #define TPM1_CnSC(index) TPM_CnSC_REG(TPM1_BASE_PTR,index) 05851 #define TPM2_CnSC(index) TPM_CnSC_REG(TPM2_BASE_PTR,index) 05852 #define TPM0_CnV(index) TPM_CnV_REG(TPM0_BASE_PTR,index) 05853 #define TPM1_CnV(index) TPM_CnV_REG(TPM1_BASE_PTR,index) 05854 #define TPM2_CnV(index) TPM_CnV_REG(TPM2_BASE_PTR,index) 05855 05856 /*! 05857 * @} 05858 */ /* end of group TPM_Register_Accessor_Macros */ 05859 05860 05861 /*! 05862 * @} 05863 */ /* end of group TPM_Peripheral */ 05864 05865 05866 /* ---------------------------------------------------------------------------- 05867 -- TSI 05868 ---------------------------------------------------------------------------- */ 05869 05870 /*! 05871 * @addtogroup TSI_Peripheral TSI 05872 * @{ 05873 */ 05874 05875 /** TSI - Peripheral register structure */ 05876 typedef struct TSI_MemMap { 05877 uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */ 05878 uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */ 05879 uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ 05880 } volatile *TSI_MemMapPtr; 05881 05882 /* ---------------------------------------------------------------------------- 05883 -- TSI - Register accessor macros 05884 ---------------------------------------------------------------------------- */ 05885 05886 /*! 05887 * @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros 05888 * @{ 05889 */ 05890 05891 05892 /* TSI - Register accessors */ 05893 #define TSI_GENCS_REG(base) ((base)->GENCS) 05894 #define TSI_DATA_REG(base) ((base)->DATA) 05895 #define TSI_TSHD_REG(base) ((base)->TSHD) 05896 05897 /*! 05898 * @} 05899 */ /* end of group TSI_Register_Accessor_Macros */ 05900 05901 05902 /* ---------------------------------------------------------------------------- 05903 -- TSI Register Masks 05904 ---------------------------------------------------------------------------- */ 05905 05906 /*! 05907 * @addtogroup TSI_Register_Masks TSI Register Masks 05908 * @{ 05909 */ 05910 05911 /* GENCS Bit Fields */ 05912 #define TSI_GENCS_CURSW_MASK 0x2u 05913 #define TSI_GENCS_CURSW_SHIFT 1 05914 #define TSI_GENCS_EOSF_MASK 0x4u 05915 #define TSI_GENCS_EOSF_SHIFT 2 05916 #define TSI_GENCS_SCNIP_MASK 0x8u 05917 #define TSI_GENCS_SCNIP_SHIFT 3 05918 #define TSI_GENCS_STM_MASK 0x10u 05919 #define TSI_GENCS_STM_SHIFT 4 05920 #define TSI_GENCS_STPE_MASK 0x20u 05921 #define TSI_GENCS_STPE_SHIFT 5 05922 #define TSI_GENCS_TSIIEN_MASK 0x40u 05923 #define TSI_GENCS_TSIIEN_SHIFT 6 05924 #define TSI_GENCS_TSIEN_MASK 0x80u 05925 #define TSI_GENCS_TSIEN_SHIFT 7 05926 #define TSI_GENCS_NSCN_MASK 0x1F00u 05927 #define TSI_GENCS_NSCN_SHIFT 8 05928 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK) 05929 #define TSI_GENCS_PS_MASK 0xE000u 05930 #define TSI_GENCS_PS_SHIFT 13 05931 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK) 05932 #define TSI_GENCS_EXTCHRG_MASK 0x70000u 05933 #define TSI_GENCS_EXTCHRG_SHIFT 16 05934 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK) 05935 #define TSI_GENCS_DVOLT_MASK 0x180000u 05936 #define TSI_GENCS_DVOLT_SHIFT 19 05937 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK) 05938 #define TSI_GENCS_REFCHRG_MASK 0xE00000u 05939 #define TSI_GENCS_REFCHRG_SHIFT 21 05940 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK) 05941 #define TSI_GENCS_MODE_MASK 0xF000000u 05942 #define TSI_GENCS_MODE_SHIFT 24 05943 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK) 05944 #define TSI_GENCS_ESOR_MASK 0x10000000u 05945 #define TSI_GENCS_ESOR_SHIFT 28 05946 #define TSI_GENCS_OUTRGF_MASK 0x80000000u 05947 #define TSI_GENCS_OUTRGF_SHIFT 31 05948 /* DATA Bit Fields */ 05949 #define TSI_DATA_TSICNT_MASK 0xFFFFu 05950 #define TSI_DATA_TSICNT_SHIFT 0 05951 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK) 05952 #define TSI_DATA_SWTS_MASK 0x400000u 05953 #define TSI_DATA_SWTS_SHIFT 22 05954 #define TSI_DATA_DMAEN_MASK 0x800000u 05955 #define TSI_DATA_DMAEN_SHIFT 23 05956 #define TSI_DATA_TSICH_MASK 0xF0000000u 05957 #define TSI_DATA_TSICH_SHIFT 28 05958 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK) 05959 /* TSHD Bit Fields */ 05960 #define TSI_TSHD_THRESL_MASK 0xFFFFu 05961 #define TSI_TSHD_THRESL_SHIFT 0 05962 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK) 05963 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u 05964 #define TSI_TSHD_THRESH_SHIFT 16 05965 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK) 05966 05967 /*! 05968 * @} 05969 */ /* end of group TSI_Register_Masks */ 05970 05971 05972 /* TSI - Peripheral instance base addresses */ 05973 /** Peripheral TSI0 base pointer */ 05974 #define TSI0_BASE_PTR ((TSI_MemMapPtr)0x40045000u) 05975 /** Array initializer of TSI peripheral base pointers */ 05976 #define TSI_BASE_PTRS { TSI0_BASE_PTR } 05977 05978 /* ---------------------------------------------------------------------------- 05979 -- TSI - Register accessor macros 05980 ---------------------------------------------------------------------------- */ 05981 05982 /*! 05983 * @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros 05984 * @{ 05985 */ 05986 05987 05988 /* TSI - Register instance definitions */ 05989 /* TSI0 */ 05990 #define TSI0_GENCS TSI_GENCS_REG(TSI0_BASE_PTR) 05991 #define TSI0_DATA TSI_DATA_REG(TSI0_BASE_PTR) 05992 #define TSI0_TSHD TSI_TSHD_REG(TSI0_BASE_PTR) 05993 05994 /*! 05995 * @} 05996 */ /* end of group TSI_Register_Accessor_Macros */ 05997 05998 05999 /*! 06000 * @} 06001 */ /* end of group TSI_Peripheral */ 06002 06003 06004 /* ---------------------------------------------------------------------------- 06005 -- UART 06006 ---------------------------------------------------------------------------- */ 06007 06008 /*! 06009 * @addtogroup UART_Peripheral UART 06010 * @{ 06011 */ 06012 06013 /** UART - Peripheral register structure */ 06014 typedef struct UART_MemMap { 06015 uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */ 06016 uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */ 06017 uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 06018 uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 06019 uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 06020 uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 06021 uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 06022 uint8_t D; /**< UART Data Register, offset: 0x7 */ 06023 uint8_t C4; /**< UART Control Register 4, offset: 0x8 */ 06024 } volatile *UART_MemMapPtr; 06025 06026 /* ---------------------------------------------------------------------------- 06027 -- UART - Register accessor macros 06028 ---------------------------------------------------------------------------- */ 06029 06030 /*! 06031 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros 06032 * @{ 06033 */ 06034 06035 06036 /* UART - Register accessors */ 06037 #define UART_BDH_REG(base) ((base)->BDH) 06038 #define UART_BDL_REG(base) ((base)->BDL) 06039 #define UART_C1_REG(base) ((base)->C1) 06040 #define UART_C2_REG(base) ((base)->C2) 06041 #define UART_S1_REG(base) ((base)->S1) 06042 #define UART_S2_REG(base) ((base)->S2) 06043 #define UART_C3_REG(base) ((base)->C3) 06044 #define UART_D_REG(base) ((base)->D) 06045 #define UART_C4_REG(base) ((base)->C4) 06046 06047 /*! 06048 * @} 06049 */ /* end of group UART_Register_Accessor_Macros */ 06050 06051 06052 /* ---------------------------------------------------------------------------- 06053 -- UART Register Masks 06054 ---------------------------------------------------------------------------- */ 06055 06056 /*! 06057 * @addtogroup UART_Register_Masks UART Register Masks 06058 * @{ 06059 */ 06060 06061 /* BDH Bit Fields */ 06062 #define UART_BDH_SBR_MASK 0x1Fu 06063 #define UART_BDH_SBR_SHIFT 0 06064 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK) 06065 #define UART_BDH_SBNS_MASK 0x20u 06066 #define UART_BDH_SBNS_SHIFT 5 06067 #define UART_BDH_RXEDGIE_MASK 0x40u 06068 #define UART_BDH_RXEDGIE_SHIFT 6 06069 #define UART_BDH_LBKDIE_MASK 0x80u 06070 #define UART_BDH_LBKDIE_SHIFT 7 06071 /* BDL Bit Fields */ 06072 #define UART_BDL_SBR_MASK 0xFFu 06073 #define UART_BDL_SBR_SHIFT 0 06074 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK) 06075 /* C1 Bit Fields */ 06076 #define UART_C1_PT_MASK 0x1u 06077 #define UART_C1_PT_SHIFT 0 06078 #define UART_C1_PE_MASK 0x2u 06079 #define UART_C1_PE_SHIFT 1 06080 #define UART_C1_ILT_MASK 0x4u 06081 #define UART_C1_ILT_SHIFT 2 06082 #define UART_C1_WAKE_MASK 0x8u 06083 #define UART_C1_WAKE_SHIFT 3 06084 #define UART_C1_M_MASK 0x10u 06085 #define UART_C1_M_SHIFT 4 06086 #define UART_C1_RSRC_MASK 0x20u 06087 #define UART_C1_RSRC_SHIFT 5 06088 #define UART_C1_UARTSWAI_MASK 0x40u 06089 #define UART_C1_UARTSWAI_SHIFT 6 06090 #define UART_C1_LOOPS_MASK 0x80u 06091 #define UART_C1_LOOPS_SHIFT 7 06092 /* C2 Bit Fields */ 06093 #define UART_C2_SBK_MASK 0x1u 06094 #define UART_C2_SBK_SHIFT 0 06095 #define UART_C2_RWU_MASK 0x2u 06096 #define UART_C2_RWU_SHIFT 1 06097 #define UART_C2_RE_MASK 0x4u 06098 #define UART_C2_RE_SHIFT 2 06099 #define UART_C2_TE_MASK 0x8u 06100 #define UART_C2_TE_SHIFT 3 06101 #define UART_C2_ILIE_MASK 0x10u 06102 #define UART_C2_ILIE_SHIFT 4 06103 #define UART_C2_RIE_MASK 0x20u 06104 #define UART_C2_RIE_SHIFT 5 06105 #define UART_C2_TCIE_MASK 0x40u 06106 #define UART_C2_TCIE_SHIFT 6 06107 #define UART_C2_TIE_MASK 0x80u 06108 #define UART_C2_TIE_SHIFT 7 06109 /* S1 Bit Fields */ 06110 #define UART_S1_PF_MASK 0x1u 06111 #define UART_S1_PF_SHIFT 0 06112 #define UART_S1_FE_MASK 0x2u 06113 #define UART_S1_FE_SHIFT 1 06114 #define UART_S1_NF_MASK 0x4u 06115 #define UART_S1_NF_SHIFT 2 06116 #define UART_S1_OR_MASK 0x8u 06117 #define UART_S1_OR_SHIFT 3 06118 #define UART_S1_IDLE_MASK 0x10u 06119 #define UART_S1_IDLE_SHIFT 4 06120 #define UART_S1_RDRF_MASK 0x20u 06121 #define UART_S1_RDRF_SHIFT 5 06122 #define UART_S1_TC_MASK 0x40u 06123 #define UART_S1_TC_SHIFT 6 06124 #define UART_S1_TDRE_MASK 0x80u 06125 #define UART_S1_TDRE_SHIFT 7 06126 /* S2 Bit Fields */ 06127 #define UART_S2_RAF_MASK 0x1u 06128 #define UART_S2_RAF_SHIFT 0 06129 #define UART_S2_LBKDE_MASK 0x2u 06130 #define UART_S2_LBKDE_SHIFT 1 06131 #define UART_S2_BRK13_MASK 0x4u 06132 #define UART_S2_BRK13_SHIFT 2 06133 #define UART_S2_RWUID_MASK 0x8u 06134 #define UART_S2_RWUID_SHIFT 3 06135 #define UART_S2_RXINV_MASK 0x10u 06136 #define UART_S2_RXINV_SHIFT 4 06137 #define UART_S2_RXEDGIF_MASK 0x40u 06138 #define UART_S2_RXEDGIF_SHIFT 6 06139 #define UART_S2_LBKDIF_MASK 0x80u 06140 #define UART_S2_LBKDIF_SHIFT 7 06141 /* C3 Bit Fields */ 06142 #define UART_C3_PEIE_MASK 0x1u 06143 #define UART_C3_PEIE_SHIFT 0 06144 #define UART_C3_FEIE_MASK 0x2u 06145 #define UART_C3_FEIE_SHIFT 1 06146 #define UART_C3_NEIE_MASK 0x4u 06147 #define UART_C3_NEIE_SHIFT 2 06148 #define UART_C3_ORIE_MASK 0x8u 06149 #define UART_C3_ORIE_SHIFT 3 06150 #define UART_C3_TXINV_MASK 0x10u 06151 #define UART_C3_TXINV_SHIFT 4 06152 #define UART_C3_TXDIR_MASK 0x20u 06153 #define UART_C3_TXDIR_SHIFT 5 06154 #define UART_C3_T8_MASK 0x40u 06155 #define UART_C3_T8_SHIFT 6 06156 #define UART_C3_R8_MASK 0x80u 06157 #define UART_C3_R8_SHIFT 7 06158 /* D Bit Fields */ 06159 #define UART_D_R0T0_MASK 0x1u 06160 #define UART_D_R0T0_SHIFT 0 06161 #define UART_D_R1T1_MASK 0x2u 06162 #define UART_D_R1T1_SHIFT 1 06163 #define UART_D_R2T2_MASK 0x4u 06164 #define UART_D_R2T2_SHIFT 2 06165 #define UART_D_R3T3_MASK 0x8u 06166 #define UART_D_R3T3_SHIFT 3 06167 #define UART_D_R4T4_MASK 0x10u 06168 #define UART_D_R4T4_SHIFT 4 06169 #define UART_D_R5T5_MASK 0x20u 06170 #define UART_D_R5T5_SHIFT 5 06171 #define UART_D_R6T6_MASK 0x40u 06172 #define UART_D_R6T6_SHIFT 6 06173 #define UART_D_R7T7_MASK 0x80u 06174 #define UART_D_R7T7_SHIFT 7 06175 /* C4 Bit Fields */ 06176 #define UART_C4_RDMAS_MASK 0x20u 06177 #define UART_C4_RDMAS_SHIFT 5 06178 #define UART_C4_TDMAS_MASK 0x80u 06179 #define UART_C4_TDMAS_SHIFT 7 06180 06181 /*! 06182 * @} 06183 */ /* end of group UART_Register_Masks */ 06184 06185 06186 /* UART - Peripheral instance base addresses */ 06187 /** Peripheral UART1 base pointer */ 06188 #define UART1_BASE_PTR ((UART_MemMapPtr)0x4006B000u) 06189 /** Peripheral UART2 base pointer */ 06190 #define UART2_BASE_PTR ((UART_MemMapPtr)0x4006C000u) 06191 /** Array initializer of UART peripheral base pointers */ 06192 #define UART_BASE_PTRS { UART1_BASE_PTR, UART2_BASE_PTR } 06193 06194 /* ---------------------------------------------------------------------------- 06195 -- UART - Register accessor macros 06196 ---------------------------------------------------------------------------- */ 06197 06198 /*! 06199 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros 06200 * @{ 06201 */ 06202 06203 06204 /* UART - Register instance definitions */ 06205 /* UART1 */ 06206 #define UART1_BDH UART_BDH_REG(UART1_BASE_PTR) 06207 #define UART1_BDL UART_BDL_REG(UART1_BASE_PTR) 06208 #define UART1_C1 UART_C1_REG(UART1_BASE_PTR) 06209 #define UART1_C2 UART_C2_REG(UART1_BASE_PTR) 06210 #define UART1_S1 UART_S1_REG(UART1_BASE_PTR) 06211 #define UART1_S2 UART_S2_REG(UART1_BASE_PTR) 06212 #define UART1_C3 UART_C3_REG(UART1_BASE_PTR) 06213 #define UART1_D UART_D_REG(UART1_BASE_PTR) 06214 #define UART1_C4 UART_C4_REG(UART1_BASE_PTR) 06215 /* UART2 */ 06216 #define UART2_BDH UART_BDH_REG(UART2_BASE_PTR) 06217 #define UART2_BDL UART_BDL_REG(UART2_BASE_PTR) 06218 #define UART2_C1 UART_C1_REG(UART2_BASE_PTR) 06219 #define UART2_C2 UART_C2_REG(UART2_BASE_PTR) 06220 #define UART2_S1 UART_S1_REG(UART2_BASE_PTR) 06221 #define UART2_S2 UART_S2_REG(UART2_BASE_PTR) 06222 #define UART2_C3 UART_C3_REG(UART2_BASE_PTR) 06223 #define UART2_D UART_D_REG(UART2_BASE_PTR) 06224 #define UART2_C4 UART_C4_REG(UART2_BASE_PTR) 06225 06226 /*! 06227 * @} 06228 */ /* end of group UART_Register_Accessor_Macros */ 06229 06230 06231 /*! 06232 * @} 06233 */ /* end of group UART_Peripheral */ 06234 06235 06236 /* ---------------------------------------------------------------------------- 06237 -- UART0 06238 ---------------------------------------------------------------------------- */ 06239 06240 /*! 06241 * @addtogroup UART0_Peripheral UART0 06242 * @{ 06243 */ 06244 06245 /** UART0 - Peripheral register structure */ 06246 typedef struct UART0_MemMap { 06247 uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */ 06248 uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */ 06249 uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 06250 uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 06251 uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 06252 uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 06253 uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 06254 uint8_t D; /**< UART Data Register, offset: 0x7 */ 06255 uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ 06256 uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ 06257 uint8_t C4; /**< UART Control Register 4, offset: 0xA */ 06258 uint8_t C5; /**< UART Control Register 5, offset: 0xB */ 06259 } volatile *UART0_MemMapPtr; 06260 06261 /* ---------------------------------------------------------------------------- 06262 -- UART0 - Register accessor macros 06263 ---------------------------------------------------------------------------- */ 06264 06265 /*! 06266 * @addtogroup UART0_Register_Accessor_Macros UART0 - Register accessor macros 06267 * @{ 06268 */ 06269 06270 06271 /* UART0 - Register accessors */ 06272 #define UART0_BDH_REG(base) ((base)->BDH) 06273 #define UART0_BDL_REG(base) ((base)->BDL) 06274 #define UART0_C1_REG(base) ((base)->C1) 06275 #define UART0_C2_REG(base) ((base)->C2) 06276 #define UART0_S1_REG(base) ((base)->S1) 06277 #define UART0_S2_REG(base) ((base)->S2) 06278 #define UART0_C3_REG(base) ((base)->C3) 06279 #define UART0_D_REG(base) ((base)->D) 06280 #define UART0_MA1_REG(base) ((base)->MA1) 06281 #define UART0_MA2_REG(base) ((base)->MA2) 06282 #define UART0_C4_REG(base) ((base)->C4) 06283 #define UART0_C5_REG(base) ((base)->C5) 06284 06285 /*! 06286 * @} 06287 */ /* end of group UART0_Register_Accessor_Macros */ 06288 06289 06290 /* ---------------------------------------------------------------------------- 06291 -- UART0 Register Masks 06292 ---------------------------------------------------------------------------- */ 06293 06294 /*! 06295 * @addtogroup UART0_Register_Masks UART0 Register Masks 06296 * @{ 06297 */ 06298 06299 /* BDH Bit Fields */ 06300 #define UART0_BDH_SBR_MASK 0x1Fu 06301 #define UART0_BDH_SBR_SHIFT 0 06302 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK) 06303 #define UART0_BDH_SBNS_MASK 0x20u 06304 #define UART0_BDH_SBNS_SHIFT 5 06305 #define UART0_BDH_RXEDGIE_MASK 0x40u 06306 #define UART0_BDH_RXEDGIE_SHIFT 6 06307 #define UART0_BDH_LBKDIE_MASK 0x80u 06308 #define UART0_BDH_LBKDIE_SHIFT 7 06309 /* BDL Bit Fields */ 06310 #define UART0_BDL_SBR_MASK 0xFFu 06311 #define UART0_BDL_SBR_SHIFT 0 06312 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK) 06313 /* C1 Bit Fields */ 06314 #define UART0_C1_PT_MASK 0x1u 06315 #define UART0_C1_PT_SHIFT 0 06316 #define UART0_C1_PE_MASK 0x2u 06317 #define UART0_C1_PE_SHIFT 1 06318 #define UART0_C1_ILT_MASK 0x4u 06319 #define UART0_C1_ILT_SHIFT 2 06320 #define UART0_C1_WAKE_MASK 0x8u 06321 #define UART0_C1_WAKE_SHIFT 3 06322 #define UART0_C1_M_MASK 0x10u 06323 #define UART0_C1_M_SHIFT 4 06324 #define UART0_C1_RSRC_MASK 0x20u 06325 #define UART0_C1_RSRC_SHIFT 5 06326 #define UART0_C1_DOZEEN_MASK 0x40u 06327 #define UART0_C1_DOZEEN_SHIFT 6 06328 #define UART0_C1_LOOPS_MASK 0x80u 06329 #define UART0_C1_LOOPS_SHIFT 7 06330 /* C2 Bit Fields */ 06331 #define UART0_C2_SBK_MASK 0x1u 06332 #define UART0_C2_SBK_SHIFT 0 06333 #define UART0_C2_RWU_MASK 0x2u 06334 #define UART0_C2_RWU_SHIFT 1 06335 #define UART0_C2_RE_MASK 0x4u 06336 #define UART0_C2_RE_SHIFT 2 06337 #define UART0_C2_TE_MASK 0x8u 06338 #define UART0_C2_TE_SHIFT 3 06339 #define UART0_C2_ILIE_MASK 0x10u 06340 #define UART0_C2_ILIE_SHIFT 4 06341 #define UART0_C2_RIE_MASK 0x20u 06342 #define UART0_C2_RIE_SHIFT 5 06343 #define UART0_C2_TCIE_MASK 0x40u 06344 #define UART0_C2_TCIE_SHIFT 6 06345 #define UART0_C2_TIE_MASK 0x80u 06346 #define UART0_C2_TIE_SHIFT 7 06347 /* S1 Bit Fields */ 06348 #define UART0_S1_PF_MASK 0x1u 06349 #define UART0_S1_PF_SHIFT 0 06350 #define UART0_S1_FE_MASK 0x2u 06351 #define UART0_S1_FE_SHIFT 1 06352 #define UART0_S1_NF_MASK 0x4u 06353 #define UART0_S1_NF_SHIFT 2 06354 #define UART0_S1_OR_MASK 0x8u 06355 #define UART0_S1_OR_SHIFT 3 06356 #define UART0_S1_IDLE_MASK 0x10u 06357 #define UART0_S1_IDLE_SHIFT 4 06358 #define UART0_S1_RDRF_MASK 0x20u 06359 #define UART0_S1_RDRF_SHIFT 5 06360 #define UART0_S1_TC_MASK 0x40u 06361 #define UART0_S1_TC_SHIFT 6 06362 #define UART0_S1_TDRE_MASK 0x80u 06363 #define UART0_S1_TDRE_SHIFT 7 06364 /* S2 Bit Fields */ 06365 #define UART0_S2_RAF_MASK 0x1u 06366 #define UART0_S2_RAF_SHIFT 0 06367 #define UART0_S2_LBKDE_MASK 0x2u 06368 #define UART0_S2_LBKDE_SHIFT 1 06369 #define UART0_S2_BRK13_MASK 0x4u 06370 #define UART0_S2_BRK13_SHIFT 2 06371 #define UART0_S2_RWUID_MASK 0x8u 06372 #define UART0_S2_RWUID_SHIFT 3 06373 #define UART0_S2_RXINV_MASK 0x10u 06374 #define UART0_S2_RXINV_SHIFT 4 06375 #define UART0_S2_MSBF_MASK 0x20u 06376 #define UART0_S2_MSBF_SHIFT 5 06377 #define UART0_S2_RXEDGIF_MASK 0x40u 06378 #define UART0_S2_RXEDGIF_SHIFT 6 06379 #define UART0_S2_LBKDIF_MASK 0x80u 06380 #define UART0_S2_LBKDIF_SHIFT 7 06381 /* C3 Bit Fields */ 06382 #define UART0_C3_PEIE_MASK 0x1u 06383 #define UART0_C3_PEIE_SHIFT 0 06384 #define UART0_C3_FEIE_MASK 0x2u 06385 #define UART0_C3_FEIE_SHIFT 1 06386 #define UART0_C3_NEIE_MASK 0x4u 06387 #define UART0_C3_NEIE_SHIFT 2 06388 #define UART0_C3_ORIE_MASK 0x8u 06389 #define UART0_C3_ORIE_SHIFT 3 06390 #define UART0_C3_TXINV_MASK 0x10u 06391 #define UART0_C3_TXINV_SHIFT 4 06392 #define UART0_C3_TXDIR_MASK 0x20u 06393 #define UART0_C3_TXDIR_SHIFT 5 06394 #define UART0_C3_R9T8_MASK 0x40u 06395 #define UART0_C3_R9T8_SHIFT 6 06396 #define UART0_C3_R8T9_MASK 0x80u 06397 #define UART0_C3_R8T9_SHIFT 7 06398 /* D Bit Fields */ 06399 #define UART0_D_R0T0_MASK 0x1u 06400 #define UART0_D_R0T0_SHIFT 0 06401 #define UART0_D_R1T1_MASK 0x2u 06402 #define UART0_D_R1T1_SHIFT 1 06403 #define UART0_D_R2T2_MASK 0x4u 06404 #define UART0_D_R2T2_SHIFT 2 06405 #define UART0_D_R3T3_MASK 0x8u 06406 #define UART0_D_R3T3_SHIFT 3 06407 #define UART0_D_R4T4_MASK 0x10u 06408 #define UART0_D_R4T4_SHIFT 4 06409 #define UART0_D_R5T5_MASK 0x20u 06410 #define UART0_D_R5T5_SHIFT 5 06411 #define UART0_D_R6T6_MASK 0x40u 06412 #define UART0_D_R6T6_SHIFT 6 06413 #define UART0_D_R7T7_MASK 0x80u 06414 #define UART0_D_R7T7_SHIFT 7 06415 /* MA1 Bit Fields */ 06416 #define UART0_MA1_MA_MASK 0xFFu 06417 #define UART0_MA1_MA_SHIFT 0 06418 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK) 06419 /* MA2 Bit Fields */ 06420 #define UART0_MA2_MA_MASK 0xFFu 06421 #define UART0_MA2_MA_SHIFT 0 06422 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK) 06423 /* C4 Bit Fields */ 06424 #define UART0_C4_OSR_MASK 0x1Fu 06425 #define UART0_C4_OSR_SHIFT 0 06426 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK) 06427 #define UART0_C4_M10_MASK 0x20u 06428 #define UART0_C4_M10_SHIFT 5 06429 #define UART0_C4_MAEN2_MASK 0x40u 06430 #define UART0_C4_MAEN2_SHIFT 6 06431 #define UART0_C4_MAEN1_MASK 0x80u 06432 #define UART0_C4_MAEN1_SHIFT 7 06433 /* C5 Bit Fields */ 06434 #define UART0_C5_RESYNCDIS_MASK 0x1u 06435 #define UART0_C5_RESYNCDIS_SHIFT 0 06436 #define UART0_C5_BOTHEDGE_MASK 0x2u 06437 #define UART0_C5_BOTHEDGE_SHIFT 1 06438 #define UART0_C5_RDMAE_MASK 0x20u 06439 #define UART0_C5_RDMAE_SHIFT 5 06440 #define UART0_C5_TDMAE_MASK 0x80u 06441 #define UART0_C5_TDMAE_SHIFT 7 06442 06443 /*! 06444 * @} 06445 */ /* end of group UART0_Register_Masks */ 06446 06447 06448 /* UART0 - Peripheral instance base addresses */ 06449 /** Peripheral UART0 base pointer */ 06450 #define UART0_BASE_PTR ((UART0_MemMapPtr)0x4006A000u) 06451 /** Array initializer of UART0 peripheral base pointers */ 06452 #define UART0_BASE_PTRS { UART0_BASE_PTR } 06453 06454 /* ---------------------------------------------------------------------------- 06455 -- UART0 - Register accessor macros 06456 ---------------------------------------------------------------------------- */ 06457 06458 /*! 06459 * @addtogroup UART0_Register_Accessor_Macros UART0 - Register accessor macros 06460 * @{ 06461 */ 06462 06463 06464 /* UART0 - Register instance definitions */ 06465 /* UART0 */ 06466 #define UART0_BDH UART0_BDH_REG(UART0_BASE_PTR) 06467 #define UART0_BDL UART0_BDL_REG(UART0_BASE_PTR) 06468 #define UART0_C1 UART0_C1_REG(UART0_BASE_PTR) 06469 #define UART0_C2 UART0_C2_REG(UART0_BASE_PTR) 06470 #define UART0_S1 UART0_S1_REG(UART0_BASE_PTR) 06471 #define UART0_S2 UART0_S2_REG(UART0_BASE_PTR) 06472 #define UART0_C3 UART0_C3_REG(UART0_BASE_PTR) 06473 #define UART0_D UART0_D_REG(UART0_BASE_PTR) 06474 #define UART0_MA1 UART0_MA1_REG(UART0_BASE_PTR) 06475 #define UART0_MA2 UART0_MA2_REG(UART0_BASE_PTR) 06476 #define UART0_C4 UART0_C4_REG(UART0_BASE_PTR) 06477 #define UART0_C5 UART0_C5_REG(UART0_BASE_PTR) 06478 06479 /*! 06480 * @} 06481 */ /* end of group UART0_Register_Accessor_Macros */ 06482 06483 06484 /*! 06485 * @} 06486 */ /* end of group UART0_Peripheral */ 06487 06488 06489 /* ---------------------------------------------------------------------------- 06490 -- USB 06491 ---------------------------------------------------------------------------- */ 06492 06493 /*! 06494 * @addtogroup USB_Peripheral USB 06495 * @{ 06496 */ 06497 06498 /** USB - Peripheral register structure */ 06499 typedef struct USB_MemMap { 06500 uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ 06501 uint8_t RESERVED_0[3]; 06502 uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ 06503 uint8_t RESERVED_1[3]; 06504 uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ 06505 uint8_t RESERVED_2[3]; 06506 uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ 06507 uint8_t RESERVED_3[3]; 06508 uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */ 06509 uint8_t RESERVED_4[3]; 06510 uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */ 06511 uint8_t RESERVED_5[3]; 06512 uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */ 06513 uint8_t RESERVED_6[3]; 06514 uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ 06515 uint8_t RESERVED_7[99]; 06516 uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ 06517 uint8_t RESERVED_8[3]; 06518 uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ 06519 uint8_t RESERVED_9[3]; 06520 uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ 06521 uint8_t RESERVED_10[3]; 06522 uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ 06523 uint8_t RESERVED_11[3]; 06524 uint8_t STAT; /**< Status register, offset: 0x90 */ 06525 uint8_t RESERVED_12[3]; 06526 uint8_t CTL; /**< Control register, offset: 0x94 */ 06527 uint8_t RESERVED_13[3]; 06528 uint8_t ADDR; /**< Address register, offset: 0x98 */ 06529 uint8_t RESERVED_14[3]; 06530 uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */ 06531 uint8_t RESERVED_15[3]; 06532 uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */ 06533 uint8_t RESERVED_16[3]; 06534 uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */ 06535 uint8_t RESERVED_17[3]; 06536 uint8_t TOKEN; /**< Token register, offset: 0xA8 */ 06537 uint8_t RESERVED_18[3]; 06538 uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */ 06539 uint8_t RESERVED_19[3]; 06540 uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ 06541 uint8_t RESERVED_20[3]; 06542 uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ 06543 uint8_t RESERVED_21[11]; 06544 struct { /* offset: 0xC0, array step: 0x4 */ 06545 uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ 06546 uint8_t RESERVED_0[3]; 06547 } ENDPOINT[16]; 06548 uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ 06549 uint8_t RESERVED_22[3]; 06550 uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ 06551 uint8_t RESERVED_23[3]; 06552 uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ 06553 uint8_t RESERVED_24[3]; 06554 uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */ 06555 uint8_t RESERVED_25[7]; 06556 uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ 06557 } volatile *USB_MemMapPtr; 06558 06559 /* ---------------------------------------------------------------------------- 06560 -- USB - Register accessor macros 06561 ---------------------------------------------------------------------------- */ 06562 06563 /*! 06564 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros 06565 * @{ 06566 */ 06567 06568 06569 /* USB - Register accessors */ 06570 #define USB_PERID_REG(base) ((base)->PERID) 06571 #define USB_IDCOMP_REG(base) ((base)->IDCOMP) 06572 #define USB_REV_REG(base) ((base)->REV) 06573 #define USB_ADDINFO_REG(base) ((base)->ADDINFO) 06574 #define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) 06575 #define USB_OTGICR_REG(base) ((base)->OTGICR) 06576 #define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) 06577 #define USB_OTGCTL_REG(base) ((base)->OTGCTL) 06578 #define USB_ISTAT_REG(base) ((base)->ISTAT) 06579 #define USB_INTEN_REG(base) ((base)->INTEN) 06580 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) 06581 #define USB_ERREN_REG(base) ((base)->ERREN) 06582 #define USB_STAT_REG(base) ((base)->STAT) 06583 #define USB_CTL_REG(base) ((base)->CTL) 06584 #define USB_ADDR_REG(base) ((base)->ADDR) 06585 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) 06586 #define USB_FRMNUML_REG(base) ((base)->FRMNUML) 06587 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) 06588 #define USB_TOKEN_REG(base) ((base)->TOKEN) 06589 #define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) 06590 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) 06591 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) 06592 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) 06593 #define USB_USBCTRL_REG(base) ((base)->USBCTRL) 06594 #define USB_OBSERVE_REG(base) ((base)->OBSERVE) 06595 #define USB_CONTROL_REG(base) ((base)->CONTROL) 06596 #define USB_USBTRC0_REG(base) ((base)->USBTRC0) 06597 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) 06598 06599 /*! 06600 * @} 06601 */ /* end of group USB_Register_Accessor_Macros */ 06602 06603 06604 /* ---------------------------------------------------------------------------- 06605 -- USB Register Masks 06606 ---------------------------------------------------------------------------- */ 06607 06608 /*! 06609 * @addtogroup USB_Register_Masks USB Register Masks 06610 * @{ 06611 */ 06612 06613 /* PERID Bit Fields */ 06614 #define USB_PERID_ID_MASK 0x3Fu 06615 #define USB_PERID_ID_SHIFT 0 06616 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK) 06617 /* IDCOMP Bit Fields */ 06618 #define USB_IDCOMP_NID_MASK 0x3Fu 06619 #define USB_IDCOMP_NID_SHIFT 0 06620 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK) 06621 /* REV Bit Fields */ 06622 #define USB_REV_REV_MASK 0xFFu 06623 #define USB_REV_REV_SHIFT 0 06624 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK) 06625 /* ADDINFO Bit Fields */ 06626 #define USB_ADDINFO_IEHOST_MASK 0x1u 06627 #define USB_ADDINFO_IEHOST_SHIFT 0 06628 #define USB_ADDINFO_IRQNUM_MASK 0xF8u 06629 #define USB_ADDINFO_IRQNUM_SHIFT 3 06630 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK) 06631 /* OTGISTAT Bit Fields */ 06632 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u 06633 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0 06634 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u 06635 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2 06636 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u 06637 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3 06638 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u 06639 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5 06640 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u 06641 #define USB_OTGISTAT_ONEMSEC_SHIFT 6 06642 #define USB_OTGISTAT_IDCHG_MASK 0x80u 06643 #define USB_OTGISTAT_IDCHG_SHIFT 7 06644 /* OTGICR Bit Fields */ 06645 #define USB_OTGICR_AVBUSEN_MASK 0x1u 06646 #define USB_OTGICR_AVBUSEN_SHIFT 0 06647 #define USB_OTGICR_BSESSEN_MASK 0x4u 06648 #define USB_OTGICR_BSESSEN_SHIFT 2 06649 #define USB_OTGICR_SESSVLDEN_MASK 0x8u 06650 #define USB_OTGICR_SESSVLDEN_SHIFT 3 06651 #define USB_OTGICR_LINESTATEEN_MASK 0x20u 06652 #define USB_OTGICR_LINESTATEEN_SHIFT 5 06653 #define USB_OTGICR_ONEMSECEN_MASK 0x40u 06654 #define USB_OTGICR_ONEMSECEN_SHIFT 6 06655 #define USB_OTGICR_IDEN_MASK 0x80u 06656 #define USB_OTGICR_IDEN_SHIFT 7 06657 /* OTGSTAT Bit Fields */ 06658 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u 06659 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0 06660 #define USB_OTGSTAT_BSESSEND_MASK 0x4u 06661 #define USB_OTGSTAT_BSESSEND_SHIFT 2 06662 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u 06663 #define USB_OTGSTAT_SESS_VLD_SHIFT 3 06664 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u 06665 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5 06666 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u 06667 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6 06668 #define USB_OTGSTAT_ID_MASK 0x80u 06669 #define USB_OTGSTAT_ID_SHIFT 7 06670 /* OTGCTL Bit Fields */ 06671 #define USB_OTGCTL_OTGEN_MASK 0x4u 06672 #define USB_OTGCTL_OTGEN_SHIFT 2 06673 #define USB_OTGCTL_DMLOW_MASK 0x10u 06674 #define USB_OTGCTL_DMLOW_SHIFT 4 06675 #define USB_OTGCTL_DPLOW_MASK 0x20u 06676 #define USB_OTGCTL_DPLOW_SHIFT 5 06677 #define USB_OTGCTL_DPHIGH_MASK 0x80u 06678 #define USB_OTGCTL_DPHIGH_SHIFT 7 06679 /* ISTAT Bit Fields */ 06680 #define USB_ISTAT_USBRST_MASK 0x1u 06681 #define USB_ISTAT_USBRST_SHIFT 0 06682 #define USB_ISTAT_ERROR_MASK 0x2u 06683 #define USB_ISTAT_ERROR_SHIFT 1 06684 #define USB_ISTAT_SOFTOK_MASK 0x4u 06685 #define USB_ISTAT_SOFTOK_SHIFT 2 06686 #define USB_ISTAT_TOKDNE_MASK 0x8u 06687 #define USB_ISTAT_TOKDNE_SHIFT 3 06688 #define USB_ISTAT_SLEEP_MASK 0x10u 06689 #define USB_ISTAT_SLEEP_SHIFT 4 06690 #define USB_ISTAT_RESUME_MASK 0x20u 06691 #define USB_ISTAT_RESUME_SHIFT 5 06692 #define USB_ISTAT_ATTACH_MASK 0x40u 06693 #define USB_ISTAT_ATTACH_SHIFT 6 06694 #define USB_ISTAT_STALL_MASK 0x80u 06695 #define USB_ISTAT_STALL_SHIFT 7 06696 /* INTEN Bit Fields */ 06697 #define USB_INTEN_USBRSTEN_MASK 0x1u 06698 #define USB_INTEN_USBRSTEN_SHIFT 0 06699 #define USB_INTEN_ERROREN_MASK 0x2u 06700 #define USB_INTEN_ERROREN_SHIFT 1 06701 #define USB_INTEN_SOFTOKEN_MASK 0x4u 06702 #define USB_INTEN_SOFTOKEN_SHIFT 2 06703 #define USB_INTEN_TOKDNEEN_MASK 0x8u 06704 #define USB_INTEN_TOKDNEEN_SHIFT 3 06705 #define USB_INTEN_SLEEPEN_MASK 0x10u 06706 #define USB_INTEN_SLEEPEN_SHIFT 4 06707 #define USB_INTEN_RESUMEEN_MASK 0x20u 06708 #define USB_INTEN_RESUMEEN_SHIFT 5 06709 #define USB_INTEN_ATTACHEN_MASK 0x40u 06710 #define USB_INTEN_ATTACHEN_SHIFT 6 06711 #define USB_INTEN_STALLEN_MASK 0x80u 06712 #define USB_INTEN_STALLEN_SHIFT 7 06713 /* ERRSTAT Bit Fields */ 06714 #define USB_ERRSTAT_PIDERR_MASK 0x1u 06715 #define USB_ERRSTAT_PIDERR_SHIFT 0 06716 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u 06717 #define USB_ERRSTAT_CRC5EOF_SHIFT 1 06718 #define USB_ERRSTAT_CRC16_MASK 0x4u 06719 #define USB_ERRSTAT_CRC16_SHIFT 2 06720 #define USB_ERRSTAT_DFN8_MASK 0x8u 06721 #define USB_ERRSTAT_DFN8_SHIFT 3 06722 #define USB_ERRSTAT_BTOERR_MASK 0x10u 06723 #define USB_ERRSTAT_BTOERR_SHIFT 4 06724 #define USB_ERRSTAT_DMAERR_MASK 0x20u 06725 #define USB_ERRSTAT_DMAERR_SHIFT 5 06726 #define USB_ERRSTAT_BTSERR_MASK 0x80u 06727 #define USB_ERRSTAT_BTSERR_SHIFT 7 06728 /* ERREN Bit Fields */ 06729 #define USB_ERREN_PIDERREN_MASK 0x1u 06730 #define USB_ERREN_PIDERREN_SHIFT 0 06731 #define USB_ERREN_CRC5EOFEN_MASK 0x2u 06732 #define USB_ERREN_CRC5EOFEN_SHIFT 1 06733 #define USB_ERREN_CRC16EN_MASK 0x4u 06734 #define USB_ERREN_CRC16EN_SHIFT 2 06735 #define USB_ERREN_DFN8EN_MASK 0x8u 06736 #define USB_ERREN_DFN8EN_SHIFT 3 06737 #define USB_ERREN_BTOERREN_MASK 0x10u 06738 #define USB_ERREN_BTOERREN_SHIFT 4 06739 #define USB_ERREN_DMAERREN_MASK 0x20u 06740 #define USB_ERREN_DMAERREN_SHIFT 5 06741 #define USB_ERREN_BTSERREN_MASK 0x80u 06742 #define USB_ERREN_BTSERREN_SHIFT 7 06743 /* STAT Bit Fields */ 06744 #define USB_STAT_ODD_MASK 0x4u 06745 #define USB_STAT_ODD_SHIFT 2 06746 #define USB_STAT_TX_MASK 0x8u 06747 #define USB_STAT_TX_SHIFT 3 06748 #define USB_STAT_ENDP_MASK 0xF0u 06749 #define USB_STAT_ENDP_SHIFT 4 06750 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK) 06751 /* CTL Bit Fields */ 06752 #define USB_CTL_USBENSOFEN_MASK 0x1u 06753 #define USB_CTL_USBENSOFEN_SHIFT 0 06754 #define USB_CTL_ODDRST_MASK 0x2u 06755 #define USB_CTL_ODDRST_SHIFT 1 06756 #define USB_CTL_RESUME_MASK 0x4u 06757 #define USB_CTL_RESUME_SHIFT 2 06758 #define USB_CTL_HOSTMODEEN_MASK 0x8u 06759 #define USB_CTL_HOSTMODEEN_SHIFT 3 06760 #define USB_CTL_RESET_MASK 0x10u 06761 #define USB_CTL_RESET_SHIFT 4 06762 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u 06763 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5 06764 #define USB_CTL_SE0_MASK 0x40u 06765 #define USB_CTL_SE0_SHIFT 6 06766 #define USB_CTL_JSTATE_MASK 0x80u 06767 #define USB_CTL_JSTATE_SHIFT 7 06768 /* ADDR Bit Fields */ 06769 #define USB_ADDR_ADDR_MASK 0x7Fu 06770 #define USB_ADDR_ADDR_SHIFT 0 06771 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK) 06772 #define USB_ADDR_LSEN_MASK 0x80u 06773 #define USB_ADDR_LSEN_SHIFT 7 06774 /* BDTPAGE1 Bit Fields */ 06775 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu 06776 #define USB_BDTPAGE1_BDTBA_SHIFT 1 06777 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK) 06778 /* FRMNUML Bit Fields */ 06779 #define USB_FRMNUML_FRM_MASK 0xFFu 06780 #define USB_FRMNUML_FRM_SHIFT 0 06781 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK) 06782 /* FRMNUMH Bit Fields */ 06783 #define USB_FRMNUMH_FRM_MASK 0x7u 06784 #define USB_FRMNUMH_FRM_SHIFT 0 06785 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK) 06786 /* TOKEN Bit Fields */ 06787 #define USB_TOKEN_TOKENENDPT_MASK 0xFu 06788 #define USB_TOKEN_TOKENENDPT_SHIFT 0 06789 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK) 06790 #define USB_TOKEN_TOKENPID_MASK 0xF0u 06791 #define USB_TOKEN_TOKENPID_SHIFT 4 06792 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK) 06793 /* SOFTHLD Bit Fields */ 06794 #define USB_SOFTHLD_CNT_MASK 0xFFu 06795 #define USB_SOFTHLD_CNT_SHIFT 0 06796 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK) 06797 /* BDTPAGE2 Bit Fields */ 06798 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu 06799 #define USB_BDTPAGE2_BDTBA_SHIFT 0 06800 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK) 06801 /* BDTPAGE3 Bit Fields */ 06802 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu 06803 #define USB_BDTPAGE3_BDTBA_SHIFT 0 06804 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK) 06805 /* ENDPT Bit Fields */ 06806 #define USB_ENDPT_EPHSHK_MASK 0x1u 06807 #define USB_ENDPT_EPHSHK_SHIFT 0 06808 #define USB_ENDPT_EPSTALL_MASK 0x2u 06809 #define USB_ENDPT_EPSTALL_SHIFT 1 06810 #define USB_ENDPT_EPTXEN_MASK 0x4u 06811 #define USB_ENDPT_EPTXEN_SHIFT 2 06812 #define USB_ENDPT_EPRXEN_MASK 0x8u 06813 #define USB_ENDPT_EPRXEN_SHIFT 3 06814 #define USB_ENDPT_EPCTLDIS_MASK 0x10u 06815 #define USB_ENDPT_EPCTLDIS_SHIFT 4 06816 #define USB_ENDPT_RETRYDIS_MASK 0x40u 06817 #define USB_ENDPT_RETRYDIS_SHIFT 6 06818 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u 06819 #define USB_ENDPT_HOSTWOHUB_SHIFT 7 06820 /* USBCTRL Bit Fields */ 06821 #define USB_USBCTRL_PDE_MASK 0x40u 06822 #define USB_USBCTRL_PDE_SHIFT 6 06823 #define USB_USBCTRL_SUSP_MASK 0x80u 06824 #define USB_USBCTRL_SUSP_SHIFT 7 06825 /* OBSERVE Bit Fields */ 06826 #define USB_OBSERVE_DMPD_MASK 0x10u 06827 #define USB_OBSERVE_DMPD_SHIFT 4 06828 #define USB_OBSERVE_DPPD_MASK 0x40u 06829 #define USB_OBSERVE_DPPD_SHIFT 6 06830 #define USB_OBSERVE_DPPU_MASK 0x80u 06831 #define USB_OBSERVE_DPPU_SHIFT 7 06832 /* CONTROL Bit Fields */ 06833 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u 06834 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4 06835 /* USBTRC0 Bit Fields */ 06836 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u 06837 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0 06838 #define USB_USBTRC0_SYNC_DET_MASK 0x2u 06839 #define USB_USBTRC0_SYNC_DET_SHIFT 1 06840 #define USB_USBTRC0_USBRESMEN_MASK 0x20u 06841 #define USB_USBTRC0_USBRESMEN_SHIFT 5 06842 #define USB_USBTRC0_USBRESET_MASK 0x80u 06843 #define USB_USBTRC0_USBRESET_SHIFT 7 06844 /* USBFRMADJUST Bit Fields */ 06845 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu 06846 #define USB_USBFRMADJUST_ADJ_SHIFT 0 06847 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK) 06848 06849 /*! 06850 * @} 06851 */ /* end of group USB_Register_Masks */ 06852 06853 06854 /* USB - Peripheral instance base addresses */ 06855 /** Peripheral USB0 base pointer */ 06856 #define USB0_BASE_PTR ((USB_MemMapPtr)0x40072000u) 06857 /** Array initializer of USB peripheral base pointers */ 06858 #define USB_BASE_PTRS { USB0_BASE_PTR } 06859 06860 /* ---------------------------------------------------------------------------- 06861 -- USB - Register accessor macros 06862 ---------------------------------------------------------------------------- */ 06863 06864 /*! 06865 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros 06866 * @{ 06867 */ 06868 06869 06870 /* USB - Register instance definitions */ 06871 /* USB0 */ 06872 #define USB0_PERID USB_PERID_REG(USB0_BASE_PTR) 06873 #define USB0_IDCOMP USB_IDCOMP_REG(USB0_BASE_PTR) 06874 #define USB0_REV USB_REV_REG(USB0_BASE_PTR) 06875 #define USB0_ADDINFO USB_ADDINFO_REG(USB0_BASE_PTR) 06876 #define USB0_OTGISTAT USB_OTGISTAT_REG(USB0_BASE_PTR) 06877 #define USB0_OTGICR USB_OTGICR_REG(USB0_BASE_PTR) 06878 #define USB0_OTGSTAT USB_OTGSTAT_REG(USB0_BASE_PTR) 06879 #define USB0_OTGCTL USB_OTGCTL_REG(USB0_BASE_PTR) 06880 #define USB0_ISTAT USB_ISTAT_REG(USB0_BASE_PTR) 06881 #define USB0_INTEN USB_INTEN_REG(USB0_BASE_PTR) 06882 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0_BASE_PTR) 06883 #define USB0_ERREN USB_ERREN_REG(USB0_BASE_PTR) 06884 #define USB0_STAT USB_STAT_REG(USB0_BASE_PTR) 06885 #define USB0_CTL USB_CTL_REG(USB0_BASE_PTR) 06886 #define USB0_ADDR USB_ADDR_REG(USB0_BASE_PTR) 06887 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0_BASE_PTR) 06888 #define USB0_FRMNUML USB_FRMNUML_REG(USB0_BASE_PTR) 06889 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0_BASE_PTR) 06890 #define USB0_TOKEN USB_TOKEN_REG(USB0_BASE_PTR) 06891 #define USB0_SOFTHLD USB_SOFTHLD_REG(USB0_BASE_PTR) 06892 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0_BASE_PTR) 06893 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0_BASE_PTR) 06894 #define USB0_ENDPT0 USB_ENDPT_REG(USB0_BASE_PTR,0) 06895 #define USB0_ENDPT1 USB_ENDPT_REG(USB0_BASE_PTR,1) 06896 #define USB0_ENDPT2 USB_ENDPT_REG(USB0_BASE_PTR,2) 06897 #define USB0_ENDPT3 USB_ENDPT_REG(USB0_BASE_PTR,3) 06898 #define USB0_ENDPT4 USB_ENDPT_REG(USB0_BASE_PTR,4) 06899 #define USB0_ENDPT5 USB_ENDPT_REG(USB0_BASE_PTR,5) 06900 #define USB0_ENDPT6 USB_ENDPT_REG(USB0_BASE_PTR,6) 06901 #define USB0_ENDPT7 USB_ENDPT_REG(USB0_BASE_PTR,7) 06902 #define USB0_ENDPT8 USB_ENDPT_REG(USB0_BASE_PTR,8) 06903 #define USB0_ENDPT9 USB_ENDPT_REG(USB0_BASE_PTR,9) 06904 #define USB0_ENDPT10 USB_ENDPT_REG(USB0_BASE_PTR,10) 06905 #define USB0_ENDPT11 USB_ENDPT_REG(USB0_BASE_PTR,11) 06906 #define USB0_ENDPT12 USB_ENDPT_REG(USB0_BASE_PTR,12) 06907 #define USB0_ENDPT13 USB_ENDPT_REG(USB0_BASE_PTR,13) 06908 #define USB0_ENDPT14 USB_ENDPT_REG(USB0_BASE_PTR,14) 06909 #define USB0_ENDPT15 USB_ENDPT_REG(USB0_BASE_PTR,15) 06910 #define USB0_USBCTRL USB_USBCTRL_REG(USB0_BASE_PTR) 06911 #define USB0_OBSERVE USB_OBSERVE_REG(USB0_BASE_PTR) 06912 #define USB0_CONTROL USB_CONTROL_REG(USB0_BASE_PTR) 06913 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0_BASE_PTR) 06914 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0_BASE_PTR) 06915 06916 /* USB - Register array accessors */ 06917 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0_BASE_PTR,index) 06918 06919 /*! 06920 * @} 06921 */ /* end of group USB_Register_Accessor_Macros */ 06922 06923 06924 /*! 06925 * @} 06926 */ /* end of group USB_Peripheral */ 06927 06928 06929 /* 06930 ** End of section using anonymous unions 06931 */ 06932 06933 #if defined(__ARMCC_VERSION) 06934 #pragma pop 06935 #elif defined(__CWCC__) 06936 #pragma pop 06937 #elif defined(__GNUC__) 06938 /* leave anonymous unions enabled */ 06939 #elif defined(__IAR_SYSTEMS_ICC__) 06940 #pragma language=default 06941 #else 06942 #error Not supported compiler type 06943 #endif 06944 06945 /*! 06946 * @} 06947 */ /* end of group Peripheral_defines */ 06948 06949 06950 /* ---------------------------------------------------------------------------- 06951 -- Backward Compatibility 06952 ---------------------------------------------------------------------------- */ 06953 06954 /*! 06955 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility 06956 * @{ 06957 */ 06958 06959 #define DMA_REQC_ARR_REG(base,index2) This_symbol_has_been_deprecated 06960 //#define DMA_REQC_ARR_DMAC_MASK This_symbol_has_been_deprecated 06961 //#define DMA_REQC_ARR_DMAC_SHIFT This_symbol_has_been_deprecated 06962 //#define DMA_REQC_ARR_DMAC(x) This_symbol_has_been_deprecated 06963 //#define DMA_REQC_ARR_CFSM_MASK This_symbol_has_been_deprecated 06964 //#define DMA_REQC_ARR_CFSM_SHIFT This_symbol_has_been_deprecated 06965 #define DMA_REQC0 This_symbol_has_been_deprecated 06966 #define DMA_REQC1 This_symbol_has_been_deprecated 06967 #define DMA_REQC2 This_symbol_has_been_deprecated 06968 #define DMA_REQC3 This_symbol_has_been_deprecated 06969 #define DMA_REQC_ARR(index2) This_symbol_has_been_deprecated 06970 //#define MCG_S_LOLS_MASK MCG_S_LOLS0_MASK 06971 //#define MCG_S_LOLS_SHIFT MCG_S_LOLS0_SHIFT 06972 //#define SIM_FCFG2_MAXADDR_MASK SIM_FCFG2_MAXADDR0_MASK 06973 //#define SIM_FCFG2_MAXADDR_SHIFT SIM_FCFG2_MAXADDR0_SHIFT 06974 //#define SIM_FCFG2_MAXADDR SIM_FCFG2_MAXADDR0 06975 //#define SPI_C2_SPLPIE_MASK This_symbol_has_been_deprecated 06976 //#define SPI_C2_SPLPIE_SHIFT This_symbol_has_been_deprecated 06977 //#define UART_C4_LBKDDMAS_MASK This_symbol_has_been_deprecated 06978 //#define UART_C4_LBKDDMAS_SHIFT This_symbol_has_been_deprecated 06979 //#define UART_C4_ILDMAS_MASK This_symbol_has_been_deprecated 06980 //#define UART_C4_ILDMAS_SHIFT This_symbol_has_been_deprecated 06981 //#define UART_C4_TCDMAS_MASK This_symbol_has_been_deprecated 06982 //#define UART_C4_TCDMAS_SHIFT This_symbol_has_been_deprecated 06983 #define UARTLP_MemMap UART0_MemMap 06984 #define UARTLP_MemMapPtr UART0_MemMapPtr 06985 #define UARTLP_BDH_REG UART0_BDH_REG 06986 #define UARTLP_BDL_REG UART0_BDL_REG 06987 #define UARTLP_C1_REG UART0_C1_REG 06988 #define UARTLP_C2_REG UART0_C2_REG 06989 #define UARTLP_S1_REG UART0_S1_REG 06990 #define UARTLP_S2_REG UART0_S2_REG 06991 #define UARTLP_C3_REG UART0_C3_REG 06992 #define UARTLP_D_REG UART0_D_REG 06993 #define UARTLP_MA1_REG UART0_MA1_REG 06994 #define UARTLP_MA2_REG UART0_MA2_REG 06995 #define UARTLP_C4_REG UART0_C4_REG 06996 #define UARTLP_C5_REG UART0_C5_REG 06997 //#define UARTLP_BDH_SBR_MASK UART0_BDH_SBR_MASK 06998 //#define UARTLP_BDH_SBR_SHIFT UART0_BDH_SBR_SHIFT 06999 //#define UARTLP_BDH_SBR(x) UART0_BDH_SBR(x) 07000 //#define UARTLP_BDH_SBNS_MASK UART0_BDH_SBNS_MASK 07001 //#define UARTLP_BDH_SBNS_SHIFT UART0_BDH_SBNS_SHIFT 07002 //#define UARTLP_BDH_RXEDGIE_MASK UART0_BDH_RXEDGIE_MASK 07003 //#define UARTLP_BDH_RXEDGIE_SHIFT UART0_BDH_RXEDGIE_SHIFT 07004 //#define UARTLP_BDH_LBKDIE_MASK UART0_BDH_LBKDIE_MASK 07005 //#define UARTLP_BDH_LBKDIE_SHIFT UART0_BDH_LBKDIE_SHIFT 07006 //#define UARTLP_BDL_SBR_MASK UART0_BDL_SBR_MASK 07007 //#define UARTLP_BDL_SBR_SHIFT UART0_BDL_SBR_SHIFT 07008 //#define UARTLP_BDL_SBR(x) UART0_BDL_SBR(x) 07009 /*#define UARTLP_C1_PT_MASK UART0_C1_PT_MASK 07010 #define UARTLP_C1_PT_SHIFT UART0_C1_PT_SHIFT 07011 #define UARTLP_C1_PE_MASK UART0_C1_PE_MASK 07012 #define UARTLP_C1_PE_SHIFT UART0_C1_PE_SHIFT 07013 #define UARTLP_C1_ILT_MASK UART0_C1_ILT_MASK 07014 #define UARTLP_C1_ILT_SHIFT UART0_C1_ILT_SHIFT 07015 #define UARTLP_C1_WAKE_MASK UART0_C1_WAKE_MASK 07016 #define UARTLP_C1_WAKE_SHIFT UART0_C1_WAKE_SHIFT 07017 #define UARTLP_C1_M_MASK UART0_C1_M_MASK 07018 #define UARTLP_C1_M_SHIFT UART0_C1_M_SHIFT 07019 #define UARTLP_C1_RSRC_MASK UART0_C1_RSRC_MASK 07020 #define UARTLP_C1_RSRC_SHIFT UART0_C1_RSRC_SHIFT 07021 #define UARTLP_C1_DOZEEN_MASK UART0_C1_DOZEEN_MASK 07022 #define UARTLP_C1_DOZEEN_SHIFT UART0_C1_DOZEEN_SHIFT 07023 #define UARTLP_C1_LOOPS_MASK UART0_C1_LOOPS_MASK 07024 #define UARTLP_C1_LOOPS_SHIFT UART0_C1_LOOPS_SHIFT 07025 #define UARTLP_C2_SBK_MASK UART0_C2_SBK_MASK 07026 #define UARTLP_C2_SBK_SHIFT UART0_C2_SBK_SHIFT*/ 07027 /*#define UARTLP_C2_RWU_MASK UART0_C2_RWU_MASK 07028 #define UARTLP_C2_RWU_SHIFT UART0_C2_RWU_SHIFT 07029 #define UARTLP_C2_RE_MASK UART0_C2_RE_MASK 07030 #define UARTLP_C2_RE_SHIFT UART0_C2_RE_SHIFT 07031 #define UARTLP_C2_TE_MASK UART0_C2_TE_MASK 07032 #define UARTLP_C2_TE_SHIFT UART0_C2_TE_SHIFT 07033 #define UARTLP_C2_ILIE_MASK UART0_C2_ILIE_MASK 07034 #define UARTLP_C2_ILIE_SHIFT UART0_C2_ILIE_SHIFT 07035 #define UARTLP_C2_RIE_MASK UART0_C2_RIE_MASK 07036 #define UARTLP_C2_RIE_SHIFT UART0_C2_RIE_SHIFT 07037 #define UARTLP_C2_TCIE_MASK UART0_C2_TCIE_MASK 07038 #define UARTLP_C2_TCIE_SHIFT UART0_C2_TCIE_SHIFT 07039 #define UARTLP_C2_TIE_MASK UART0_C2_TIE_MASK 07040 #define UARTLP_C2_TIE_SHIFT UART0_C2_TIE_SHIFT 07041 #define UARTLP_S1_PF_MASK UART0_S1_PF_MASK 07042 #define UARTLP_S1_PF_SHIFT UART0_S1_PF_SHIFT 07043 #define UARTLP_S1_FE_MASK UART0_S1_FE_MASK 07044 #define UARTLP_S1_FE_SHIFT UART0_S1_FE_SHIFT 07045 #define UARTLP_S1_NF_MASK UART0_S1_NF_MASK 07046 #define UARTLP_S1_NF_SHIFT UART0_S1_NF_SHIFT 07047 #define UARTLP_S1_OR_MASK UART0_S1_OR_MASK 07048 #define UARTLP_S1_OR_SHIFT UART0_S1_OR_SHIFT 07049 #define UARTLP_S1_IDLE_MASK UART0_S1_IDLE_MASK 07050 #define UARTLP_S1_IDLE_SHIFT UART0_S1_IDLE_SHIFT 07051 #define UARTLP_S1_RDRF_MASK UART0_S1_RDRF_MASK 07052 #define UARTLP_S1_RDRF_SHIFT UART0_S1_RDRF_SHIFT 07053 #define UARTLP_S1_TC_MASK UART0_S1_TC_MASK 07054 #define UARTLP_S1_TC_SHIFT UART0_S1_TC_SHIFT 07055 #define UARTLP_S1_TDRE_MASK UART0_S1_TDRE_MASK 07056 #define UARTLP_S1_TDRE_SHIFT UART0_S1_TDRE_SHIFT 07057 #define UARTLP_S2_RAF_MASK UART0_S2_RAF_MASK 07058 #define UARTLP_S2_RAF_SHIFT UART0_S2_RAF_SHIFT 07059 #define UARTLP_S2_LBKDE_MASK UART0_S2_LBKDE_MASK 07060 #define UARTLP_S2_LBKDE_SHIFT UART0_S2_LBKDE_SHIFT 07061 #define UARTLP_S2_BRK13_MASK UART0_S2_BRK13_MASK 07062 #define UARTLP_S2_BRK13_SHIFT UART0_S2_BRK13_SHIFT 07063 #define UARTLP_S2_RWUID_MASK UART0_S2_RWUID_MASK 07064 #define UARTLP_S2_RWUID_SHIFT UART0_S2_RWUID_SHIFT 07065 #define UARTLP_S2_RXINV_MASK UART0_S2_RXINV_MASK 07066 #define UARTLP_S2_RXINV_SHIFT UART0_S2_RXINV_SHIFT 07067 #define UARTLP_S2_MSBF_MASK UART0_S2_MSBF_MASK 07068 #define UARTLP_S2_MSBF_SHIFT UART0_S2_MSBF_SHIFT 07069 #define UARTLP_S2_RXEDGIF_MASK UART0_S2_RXEDGIF_MASK 07070 #define UARTLP_S2_RXEDGIF_SHIFT UART0_S2_RXEDGIF_SHIFT 07071 #define UARTLP_S2_LBKDIF_MASK UART0_S2_LBKDIF_MASK 07072 #define UARTLP_S2_LBKDIF_SHIFT UART0_S2_LBKDIF_SHIFT 07073 #define UARTLP_C3_PEIE_MASK UART0_C3_PEIE_MASK 07074 #define UARTLP_C3_PEIE_SHIFT UART0_C3_PEIE_SHIFT 07075 #define UARTLP_C3_FEIE_MASK UART0_C3_FEIE_MASK 07076 #define UARTLP_C3_FEIE_SHIFT UART0_C3_FEIE_SHIFT 07077 #define UARTLP_C3_NEIE_MASK UART0_C3_NEIE_MASK 07078 #define UARTLP_C3_NEIE_SHIFT UART0_C3_NEIE_SHIFT 07079 #define UARTLP_C3_ORIE_MASK UART0_C3_ORIE_MASK 07080 #define UARTLP_C3_ORIE_SHIFT UART0_C3_ORIE_SHIFT 07081 #define UARTLP_C3_TXINV_MASK UART0_C3_TXINV_MASK 07082 #define UARTLP_C3_TXINV_SHIFT UART0_C3_TXINV_SHIFT 07083 #define UARTLP_C3_TXDIR_MASK UART0_C3_TXDIR_MASK 07084 #define UARTLP_C3_TXDIR_SHIFT UART0_C3_TXDIR_SHIFT 07085 #define UARTLP_C3_R9T8_MASK UART0_C3_R9T8_MASK 07086 #define UARTLP_C3_R9T8_SHIFT UART0_C3_R9T8_SHIFT 07087 #define UARTLP_C3_R8T9_MASK UART0_C3_R8T9_MASK 07088 #define UARTLP_C3_R8T9_SHIFT UART0_C3_R8T9_SHIFT 07089 #define UARTLP_D_R0T0_MASK UART0_D_R0T0_MASK 07090 #define UARTLP_D_R0T0_SHIFT UART0_D_R0T0_SHIFT 07091 #define UARTLP_D_R1T1_MASK UART0_D_R1T1_MASK 07092 #define UARTLP_D_R1T1_SHIFT UART0_D_R1T1_SHIFT 07093 #define UARTLP_D_R2T2_MASK UART0_D_R2T2_MASK 07094 #define UARTLP_D_R2T2_SHIFT UART0_D_R2T2_SHIFT 07095 #define UARTLP_D_R3T3_MASK UART0_D_R3T3_MASK 07096 #define UARTLP_D_R3T3_SHIFT UART0_D_R3T3_SHIFT 07097 #define UARTLP_D_R4T4_MASK UART0_D_R4T4_MASK 07098 #define UARTLP_D_R4T4_SHIFT UART0_D_R4T4_SHIFT 07099 #define UARTLP_D_R5T5_MASK UART0_D_R5T5_MASK 07100 #define UARTLP_D_R5T5_SHIFT UART0_D_R5T5_SHIFT 07101 #define UARTLP_D_R6T6_MASK UART0_D_R6T6_MASK 07102 #define UARTLP_D_R6T6_SHIFT UART0_D_R6T6_SHIFT 07103 #define UARTLP_D_R7T7_MASK UART0_D_R7T7_MASK 07104 #define UARTLP_D_R7T7_SHIFT UART0_D_R7T7_SHIFT 07105 #define UARTLP_MA1_MA_MASK UART0_MA1_MA_MASK 07106 #define UARTLP_MA1_MA_SHIFT UART0_MA1_MA_SHIFT 07107 #define UARTLP_MA1_MA(x) UART0_MA1_MA(x) 07108 #define UARTLP_MA2_MA_MASK UART0_MA2_MA_MASK 07109 #define UARTLP_MA2_MA_SHIFT UART0_MA2_MA_SHIFT 07110 #define UARTLP_MA2_MA(x) UART0_MA2_MA(x) 07111 #define UARTLP_C4_OSR_MASK UART0_C4_OSR_MASK 07112 #define UARTLP_C4_OSR_SHIFT UART0_C4_OSR_SHIFT 07113 #define UARTLP_C4_OSR(x) UART0_C4_OSR(x) 07114 #define UARTLP_C4_M10_MASK UART0_C4_M10_MASK 07115 #define UARTLP_C4_M10_SHIFT UART0_C4_M10_SHIFT 07116 #define UARTLP_C4_MAEN2_MASK UART0_C4_MAEN2_MASK 07117 #define UARTLP_C4_MAEN2_SHIFT UART0_C4_MAEN2_SHIFT 07118 #define UARTLP_C4_MAEN1_MASK UART0_C4_MAEN1_MASK 07119 #define UARTLP_C4_MAEN1_SHIFT UART0_C4_MAEN1_SHIFT 07120 #define UARTLP_C5_RESYNCDIS_MASK UART0_C5_RESYNCDIS_MASK 07121 #define UARTLP_C5_RESYNCDIS_SHIFT UART0_C5_RESYNCDIS_SHIFT 07122 #define UARTLP_C5_BOTHEDGE_MASK UART0_C5_BOTHEDGE_MASK 07123 #define UARTLP_C5_BOTHEDGE_SHIFT UART0_C5_BOTHEDGE_SHIFT 07124 #define UARTLP_C5_RDMAE_MASK UART0_C5_RDMAE_MASK 07125 #define UARTLP_C5_RDMAE_SHIFT UART0_C5_RDMAE_SHIFT 07126 #define UARTLP_C5_TDMAE_MASK UART0_C5_TDMAE_MASK 07127 #define UARTLP_C5_TDMAE_SHIFT UART0_C5_TDMAE_SHIFT*/ 07128 #define UARTLP_BASE_PTRS UART0_BASE_PTRS 07129 #define NV_FOPT_EZPORT_DIS_MASK This_symbol_has_been_deprecated 07130 #define NV_FOPT_EZPORT_DIS_SHIFT This_symbol_has_been_deprecated 07131 07132 /*! 07133 * @} 07134 */ /* end of group Backward_Compatibility_Symbols */ 07135 07136 07137 #else /* #if !defined(MCU_MKL25Z4) */ 07138 /* There is already included the same memory map. Check if it is compatible (has the same major version) */ 07139 #if (MCU_MEM_MAP_VERSION != 0x0100u) 07140 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) 07141 #warning There are included two not compatible versions of memory maps. Please check possible differences. 07142 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */ 07143 #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */ 07144 #endif /* #if !defined(MCU_MKL25Z4) */ 07145 07146 /* MKL25Z4.h, eof. */
Generated on Tue Jul 12 2022 16:20:09 by
1.7.2