Freescale_Cachan
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Programme_course_30Tr
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Programme_course_vir_am_2
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SCB_MemMap Struct Reference
[SCB]
SCB - Peripheral register structure. More...
#include <MKL25Z4.h>
Data Fields | |
| uint32_t | ACTLR |
| Auxiliary Control Register,, offset: 0x8. | |
| uint32_t | CPUID |
| CPUID Base Register, offset: 0xD00. | |
| uint32_t | ICSR |
| Interrupt Control and State Register, offset: 0xD04. | |
| uint32_t | VTOR |
| Vector Table Offset Register, offset: 0xD08. | |
| uint32_t | AIRCR |
| Application Interrupt and Reset Control Register, offset: 0xD0C. | |
| uint32_t | SCR |
| System Control Register, offset: 0xD10. | |
| uint32_t | CCR |
| Configuration and Control Register, offset: 0xD14. | |
| uint32_t | SHPR2 |
| System Handler Priority Register 2, offset: 0xD1C. | |
| uint32_t | SHPR3 |
| System Handler Priority Register 3, offset: 0xD20. | |
| uint32_t | SHCSR |
| System Handler Control and State Register, offset: 0xD24. | |
| uint32_t | DFSR |
| Debug Fault Status Register, offset: 0xD30. | |
Detailed Description
SCB - Peripheral register structure.
Definition at line 4753 of file MKL25Z4.h.
Field Documentation
| uint32_t AIRCR |
| uint32_t CCR |
| uint32_t DFSR |
| uint32_t ICSR |
| uint32_t SHCSR |
| uint32_t SHPR2 |
| uint32_t SHPR3 |
Generated on Tue Jul 12 2022 16:20:12 by
1.7.2