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Programme_course_30Tr
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UART0_MemMap Struct Reference
[UART0]
UART0 - Peripheral register structure. More...
#include <MKL25Z4.h>
Data Fields | |
| uint8_t | BDH |
| UART Baud Rate Register High, offset: 0x0. | |
| uint8_t | BDL |
| UART Baud Rate Register Low, offset: 0x1. | |
| uint8_t | C1 |
| UART Control Register 1, offset: 0x2. | |
| uint8_t | C2 |
| UART Control Register 2, offset: 0x3. | |
| uint8_t | S1 |
| UART Status Register 1, offset: 0x4. | |
| uint8_t | S2 |
| UART Status Register 2, offset: 0x5. | |
| uint8_t | C3 |
| UART Control Register 3, offset: 0x6. | |
| uint8_t | D |
| UART Data Register, offset: 0x7. | |
| uint8_t | MA1 |
| UART Match Address Registers 1, offset: 0x8. | |
| uint8_t | MA2 |
| UART Match Address Registers 2, offset: 0x9. | |
| uint8_t | C4 |
| UART Control Register 4, offset: 0xA. | |
| uint8_t | C5 |
| UART Control Register 5, offset: 0xB. | |
Detailed Description
UART0 - Peripheral register structure.
Definition at line 6246 of file MKL25Z4.h.
Field Documentation
Generated on Tue Jul 12 2022 16:20:12 by
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