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Programme_course_30Tr
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LLWU_MemMap Struct Reference
[LLWU]
LLWU - Peripheral register structure. More...
#include <MKL25Z4.h>
Data Fields | |
| uint8_t | PE1 |
| LLWU Pin Enable 1 register, offset: 0x0. | |
| uint8_t | PE2 |
| LLWU Pin Enable 2 register, offset: 0x1. | |
| uint8_t | PE3 |
| LLWU Pin Enable 3 register, offset: 0x2. | |
| uint8_t | PE4 |
| LLWU Pin Enable 4 register, offset: 0x3. | |
| uint8_t | ME |
| LLWU Module Enable register, offset: 0x4. | |
| uint8_t | F1 |
| LLWU Flag 1 register, offset: 0x5. | |
| uint8_t | F2 |
| LLWU Flag 2 register, offset: 0x6. | |
| uint8_t | F3 |
| LLWU Flag 3 register, offset: 0x7. | |
| uint8_t | FILT1 |
| LLWU Pin Filter 1 register, offset: 0x8. | |
| uint8_t | FILT2 |
| LLWU Pin Filter 2 register, offset: 0x9. | |
Detailed Description
LLWU - Peripheral register structure.
Definition at line 2129 of file MKL25Z4.h.
Field Documentation
Generated on Tue Jul 12 2022 16:20:12 by
1.7.2