Freescale_Cachan
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Programme_course_30Tr
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Programme_course_vir_am_2
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CoreDebug_MemMap Struct Reference
[CoreDebug]
CoreDebug - Peripheral register structure. More...
#include <MKL25Z4.h>
Data Fields | |
| uint32_t | base_DCRSR |
| Debug Core Register Selector Register, offset: 0x4. | |
| uint32_t | base_DCRDR |
| Debug Core Register Data Register, offset: 0x8. | |
| uint32_t | base_DEMCR |
| Debug Exception and Monitor Control Register, offset: 0xC. | |
| uint32_t | base_DHCSR_Read |
| Debug Halting Control and Status Register, offset: 0x0. | |
| uint32_t | base_DHCSR_Write |
| Debug Halting Control and Status Register, offset: 0x0. | |
Detailed Description
CoreDebug - Peripheral register structure.
Definition at line 752 of file MKL25Z4.h.
Field Documentation
| uint32_t base_DCRDR |
| uint32_t base_DCRSR |
| uint32_t base_DEMCR |
| uint32_t base_DHCSR_Read |
| uint32_t base_DHCSR_Write |
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