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MKL26Z4.h
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00001 /* 00002 ** ################################################################### 00003 ** Processors: MKL26Z128CAL4 00004 ** MKL26Z128VFM4 00005 ** MKL26Z128VFT4 00006 ** MKL26Z128VLH4 00007 ** MKL26Z128VLL4 00008 ** MKL26Z128VMC4 00009 ** MKL26Z256VLH4 00010 ** MKL26Z256VLL4 00011 ** MKL26Z256VMC4 00012 ** MKL26Z256VMP4 00013 ** MKL26Z32VFM4 00014 ** MKL26Z32VFT4 00015 ** MKL26Z32VLH4 00016 ** MKL26Z64VFM4 00017 ** MKL26Z64VFT4 00018 ** MKL26Z64VLH4 00019 ** 00020 ** Compilers: Keil ARM C/C++ Compiler 00021 ** Freescale C/C++ for Embedded ARM 00022 ** GNU C Compiler 00023 ** IAR ANSI C/C++ Compiler for ARM 00024 ** 00025 ** Reference manuals: KL26P121M48SF4RM Rev. 3.2, October 2013 00026 ** KL26P121M48SF4RM, Rev.2, Dec 2012 00027 ** 00028 ** Version: rev. 1.8, 2015-07-29 00029 ** Build: b160126 00030 ** 00031 ** Abstract: 00032 ** CMSIS Peripheral Access Layer for MKL26Z4 00033 ** 00034 ** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. 00035 ** All rights reserved. 00036 ** 00037 ** Redistribution and use in source and binary forms, with or without modification, 00038 ** are permitted provided that the following conditions are met: 00039 ** 00040 ** o Redistributions of source code must retain the above copyright notice, this list 00041 ** of conditions and the following disclaimer. 00042 ** 00043 ** o Redistributions in binary form must reproduce the above copyright notice, this 00044 ** list of conditions and the following disclaimer in the documentation and/or 00045 ** other materials provided with the distribution. 00046 ** 00047 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its 00048 ** contributors may be used to endorse or promote products derived from this 00049 ** software without specific prior written permission. 00050 ** 00051 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00052 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00053 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00054 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00055 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00056 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00057 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00058 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00059 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00060 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00061 ** 00062 ** http: www.freescale.com 00063 ** mail: support@freescale.com 00064 ** 00065 ** Revisions: 00066 ** - rev. 1.0 (2012-12-12) 00067 ** Initial version. 00068 ** - rev. 1.1 (2013-04-05) 00069 ** Changed start of doxygen comment. 00070 ** - rev. 1.2 (2013-04-12) 00071 ** SystemInit function fixed for clock configuration 1. 00072 ** Name of the interrupt num. 31 updated to reflect proper function. 00073 ** - rev. 1.3 (2014-05-27) 00074 ** Updated to Kinetis SDK support standard. 00075 ** MCG OSC clock select supported (MCG_C7[OSCSEL]). 00076 ** - rev. 1.4 (2014-07-25) 00077 ** System initialization updated: 00078 ** - Prefix added to the system initialization parameterization constants to avoid name conflicts.. 00079 ** - VLLSx wake-up recovery added. 00080 ** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes. 00081 ** - rev. 1.5 (2014-08-28) 00082 ** Update of system files - default clock configuration changed, fix of OSC initialization. 00083 ** Update of startup files - possibility to override DefaultISR added. 00084 ** - rev. 1.6 (2014-10-14) 00085 ** Renamed interrupt vector LPTimer to LPTMR0 00086 ** - rev. 1.7 (2015-02-18) 00087 ** Renamed interrupt vector LLW to LLWU 00088 ** - rev. 1.8 (2015-07-29) 00089 ** Correction of backward compatibility. 00090 ** 00091 ** ################################################################### 00092 */ 00093 00094 /*! 00095 * @file MKL26Z4.h 00096 * @version 1.8 00097 * @date 2015-07-29 00098 * @brief CMSIS Peripheral Access Layer for MKL26Z4 00099 * 00100 * CMSIS Peripheral Access Layer for MKL26Z4 00101 */ 00102 00103 #ifndef _MKL26Z4_H_ 00104 #define _MKL26Z4_H_ /**< Symbol preventing repeated inclusion */ 00105 00106 /** Memory map major version (memory maps with equal major version number are 00107 * compatible) */ 00108 #define MCU_MEM_MAP_VERSION 0x0100U 00109 /** Memory map minor version */ 00110 #define MCU_MEM_MAP_VERSION_MINOR 0x0008U 00111 00112 00113 /* ---------------------------------------------------------------------------- 00114 -- Interrupt vector numbers 00115 ---------------------------------------------------------------------------- */ 00116 00117 /*! 00118 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 00119 * @{ 00120 */ 00121 00122 /** Interrupt Number Definitions */ 00123 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ 00124 00125 typedef enum IRQn { 00126 /* Auxiliary constants */ 00127 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 00128 00129 /* Core interrupts */ 00130 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 00131 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ 00132 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ 00133 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ 00134 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ 00135 00136 /* Device specific interrupts */ 00137 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete and error interrupt */ 00138 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete and error interrupt */ 00139 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete and error interrupt */ 00140 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete and error interrupt */ 00141 Reserved20_IRQn = 4, /**< Reserved interrupt */ 00142 FTFA_IRQn = 5, /**< FTFA command complete and read collision */ 00143 LVD_LVW_IRQn = 6, /**< Low-voltage detect, low-voltage warning */ 00144 LLWU_IRQn = 7, /**< Low Leakage Wakeup */ 00145 I2C0_IRQn = 8, /**< I2C0 interrupt */ 00146 I2C1_IRQn = 9, /**< I2C1 interrupt */ 00147 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */ 00148 SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */ 00149 UART0_IRQn = 12, /**< UART0 status and error */ 00150 UART1_IRQn = 13, /**< UART1 status and error */ 00151 UART2_IRQn = 14, /**< UART2 status and error */ 00152 ADC0_IRQn = 15, /**< ADC0 interrupt */ 00153 CMP0_IRQn = 16, /**< CMP0 interrupt */ 00154 TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */ 00155 TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */ 00156 TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */ 00157 RTC_IRQn = 20, /**< RTC alarm interrupt */ 00158 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */ 00159 PIT_IRQn = 22, /**< PIT single interrupt vector for all channels */ 00160 I2S0_IRQn = 23, /**< I2S0 Single interrupt vector for all sources */ 00161 USB0_IRQn = 24, /**< USB0 OTG */ 00162 DAC0_IRQn = 25, /**< DAC0 interrupt */ 00163 TSI0_IRQn = 26, /**< TSI0 interrupt */ 00164 MCG_IRQn = 27, /**< MCG interrupt */ 00165 LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */ 00166 Reserved45_IRQn = 29, /**< Reserved interrupt */ 00167 PORTA_IRQn = 30, /**< PORTA pin detect */ 00168 PORTC_PORTD_IRQn = 31 /**< Single interrupt vector for PORTC and PORTD pin detect */ 00169 } IRQn_Type ; 00170 00171 /*! 00172 * @} 00173 */ /* end of group Interrupt_vector_numbers */ 00174 00175 00176 /* ---------------------------------------------------------------------------- 00177 -- Cortex M0 Core Configuration 00178 ---------------------------------------------------------------------------- */ 00179 00180 /*! 00181 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 00182 * @{ 00183 */ 00184 00185 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ 00186 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 00187 #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ 00188 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ 00189 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 00190 00191 #include "core_cm0plus.h" /* Core Peripheral Access Layer */ 00192 #include "system_MKL26Z4.h" /* Device specific configuration file */ 00193 00194 /*! 00195 * @} 00196 */ /* end of group Cortex_Core_Configuration */ 00197 00198 00199 /* ---------------------------------------------------------------------------- 00200 -- Mapping Information 00201 ---------------------------------------------------------------------------- */ 00202 00203 /*! 00204 * @addtogroup Mapping_Information Mapping Information 00205 * @{ 00206 */ 00207 00208 /** Mapping Information */ 00209 /*! 00210 * @addtogroup edma_request 00211 * @{ 00212 */ 00213 00214 /******************************************************************************* 00215 * Definitions 00216 ******************************************************************************/ 00217 00218 /*! 00219 * @brief Structure for the DMA hardware request 00220 * 00221 * Defines the structure for the DMA hardware request collections. The user can configure the 00222 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index 00223 * of the hardware request varies according to the to SoC. 00224 */ 00225 typedef enum _dma_request_source 00226 { 00227 kDmaRequestMux0Disable = 0|0x100U, /**< Disable */ 00228 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ 00229 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 receive complete */ 00230 kDmaRequestMux0LPSCI0Rx = 2|0x100U, /**< UART0 receive complete */ 00231 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 transmit complete */ 00232 kDmaRequestMux0LPSCI0Tx = 3|0x100U, /**< UART0 transmit complete */ 00233 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 receive complete */ 00234 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 transmit complete */ 00235 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 receive complete */ 00236 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 transmit complete */ 00237 kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ 00238 kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ 00239 kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */ 00240 kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */ 00241 kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */ 00242 kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */ 00243 kDmaRequestMux0I2S0Rx = 14|0x100U, /**< I2S0 receive complete */ 00244 kDmaRequestMux0I2S0Tx = 15|0x100U, /**< I2S0 transmit complete */ 00245 kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 receive complete */ 00246 kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 transmit complete */ 00247 kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 receive complete */ 00248 kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 transmit complete */ 00249 kDmaRequestMux0Reserved20 = 20|0x100U, /**< Reserved20 */ 00250 kDmaRequestMux0Reserved21 = 21|0x100U, /**< Reserved21 */ 00251 kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0 transmission complete */ 00252 kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1 transmission complete */ 00253 kDmaRequestMux0TPM0Channel0 = 24|0x100U, /**< TPM0 channel 0 event (CMP or CAP) */ 00254 kDmaRequestMux0TPM0Channel1 = 25|0x100U, /**< TPM0 channel 1 event (CMP or CAP) */ 00255 kDmaRequestMux0TPM0Channel2 = 26|0x100U, /**< TPM0 channel 2 event (CMP or CAP) */ 00256 kDmaRequestMux0TPM0Channel3 = 27|0x100U, /**< TPM0 channel 3 event (CMP or CAP) */ 00257 kDmaRequestMux0TPM0Channel4 = 28|0x100U, /**< TPM0 channel 4 event (CMP or CAP) */ 00258 kDmaRequestMux0TPM0Channel5 = 29|0x100U, /**< TPM0 channel 5 event (CMP or CAP) */ 00259 kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */ 00260 kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */ 00261 kDmaRequestMux0TPM1Channel0 = 32|0x100U, /**< TPM1 channel 0 event (CMP or CAP) */ 00262 kDmaRequestMux0TPM1Channel1 = 33|0x100U, /**< TPM1 channel 1 event (CMP or CAP) */ 00263 kDmaRequestMux0TPM2Channel0 = 34|0x100U, /**< TPM2 channel 0 event (CMP or CAP) */ 00264 kDmaRequestMux0TPM2Channel1 = 35|0x100U, /**< TPM2 channel 1 event (CMP or CAP) */ 00265 kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */ 00266 kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */ 00267 kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */ 00268 kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */ 00269 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0 conversion complete */ 00270 kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */ 00271 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0 Output */ 00272 kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */ 00273 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ 00274 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0 buffer pointer reaches upper or lower limit */ 00275 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ 00276 kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */ 00277 kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */ 00278 kDmaRequestMux0PortA = 49|0x100U, /**< PORTA rising, falling or both edges */ 00279 kDmaRequestMux0Reserved50 = 50|0x100U, /**< Reserved50 */ 00280 kDmaRequestMux0PortC = 51|0x100U, /**< PORTC rising, falling or both edges */ 00281 kDmaRequestMux0PortD = 52|0x100U, /**< PORTD rising, falling or both edges */ 00282 kDmaRequestMux0Reserved53 = 53|0x100U, /**< Reserved53 */ 00283 kDmaRequestMux0TPM0Overflow = 54|0x100U, /**< TPM0 overflow */ 00284 kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1 overflow */ 00285 kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2 overflow */ 00286 kDmaRequestMux0TSI = 57|0x100U, /**< TSI0 event */ 00287 kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */ 00288 kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */ 00289 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< Always enabled 60 */ 00290 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< Always enabled 61 */ 00291 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< Always enabled 62 */ 00292 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< Always enabled 63 */ 00293 } dma_request_source_t; 00294 00295 /* @} */ 00296 00297 00298 /*! 00299 * @} 00300 */ /* end of group Mapping_Information */ 00301 00302 00303 /* ---------------------------------------------------------------------------- 00304 -- Device Peripheral Access Layer 00305 ---------------------------------------------------------------------------- */ 00306 00307 /*! 00308 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 00309 * @{ 00310 */ 00311 00312 00313 /* 00314 ** Start of section using anonymous unions 00315 */ 00316 00317 #if defined(__ARMCC_VERSION) 00318 #pragma push 00319 #pragma anon_unions 00320 #elif defined(__CWCC__) 00321 #pragma push 00322 #pragma cpp_extensions on 00323 #elif defined(__GNUC__) 00324 /* anonymous unions are enabled by default */ 00325 #elif defined(__IAR_SYSTEMS_ICC__) 00326 #pragma language=extended 00327 #else 00328 #error Not supported compiler type 00329 #endif 00330 00331 /* ---------------------------------------------------------------------------- 00332 -- ADC Peripheral Access Layer 00333 ---------------------------------------------------------------------------- */ 00334 00335 /*! 00336 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 00337 * @{ 00338 */ 00339 00340 /** ADC - Register Layout Typedef */ 00341 typedef struct { 00342 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ 00343 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ 00344 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ 00345 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ 00346 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ 00347 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ 00348 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ 00349 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ 00350 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ 00351 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ 00352 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ 00353 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ 00354 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ 00355 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ 00356 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ 00357 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ 00358 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ 00359 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ 00360 uint8_t RESERVED_0[4]; 00361 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ 00362 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ 00363 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ 00364 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ 00365 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ 00366 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ 00367 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ 00368 } ADC_Type; 00369 00370 /* ---------------------------------------------------------------------------- 00371 -- ADC Register Masks 00372 ---------------------------------------------------------------------------- */ 00373 00374 /*! 00375 * @addtogroup ADC_Register_Masks ADC Register Masks 00376 * @{ 00377 */ 00378 00379 /*! @name SC1 - ADC Status and Control Registers 1 */ 00380 #define ADC_SC1_ADCH_MASK (0x1FU) 00381 #define ADC_SC1_ADCH_SHIFT (0U) 00382 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) 00383 #define ADC_SC1_DIFF_MASK (0x20U) 00384 #define ADC_SC1_DIFF_SHIFT (5U) 00385 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) 00386 #define ADC_SC1_AIEN_MASK (0x40U) 00387 #define ADC_SC1_AIEN_SHIFT (6U) 00388 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) 00389 #define ADC_SC1_COCO_MASK (0x80U) 00390 #define ADC_SC1_COCO_SHIFT (7U) 00391 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) 00392 00393 /* The count of ADC_SC1 */ 00394 #define ADC_SC1_COUNT (2U) 00395 00396 /*! @name CFG1 - ADC Configuration Register 1 */ 00397 #define ADC_CFG1_ADICLK_MASK (0x3U) 00398 #define ADC_CFG1_ADICLK_SHIFT (0U) 00399 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) 00400 #define ADC_CFG1_MODE_MASK (0xCU) 00401 #define ADC_CFG1_MODE_SHIFT (2U) 00402 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) 00403 #define ADC_CFG1_ADLSMP_MASK (0x10U) 00404 #define ADC_CFG1_ADLSMP_SHIFT (4U) 00405 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) 00406 #define ADC_CFG1_ADIV_MASK (0x60U) 00407 #define ADC_CFG1_ADIV_SHIFT (5U) 00408 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) 00409 #define ADC_CFG1_ADLPC_MASK (0x80U) 00410 #define ADC_CFG1_ADLPC_SHIFT (7U) 00411 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) 00412 00413 /*! @name CFG2 - ADC Configuration Register 2 */ 00414 #define ADC_CFG2_ADLSTS_MASK (0x3U) 00415 #define ADC_CFG2_ADLSTS_SHIFT (0U) 00416 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) 00417 #define ADC_CFG2_ADHSC_MASK (0x4U) 00418 #define ADC_CFG2_ADHSC_SHIFT (2U) 00419 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) 00420 #define ADC_CFG2_ADACKEN_MASK (0x8U) 00421 #define ADC_CFG2_ADACKEN_SHIFT (3U) 00422 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) 00423 #define ADC_CFG2_MUXSEL_MASK (0x10U) 00424 #define ADC_CFG2_MUXSEL_SHIFT (4U) 00425 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) 00426 00427 /*! @name R - ADC Data Result Register */ 00428 #define ADC_R_D_MASK (0xFFFFU) 00429 #define ADC_R_D_SHIFT (0U) 00430 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) 00431 00432 /* The count of ADC_R */ 00433 #define ADC_R_COUNT (2U) 00434 00435 /*! @name CV1 - Compare Value Registers */ 00436 #define ADC_CV1_CV_MASK (0xFFFFU) 00437 #define ADC_CV1_CV_SHIFT (0U) 00438 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) 00439 00440 /*! @name CV2 - Compare Value Registers */ 00441 #define ADC_CV2_CV_MASK (0xFFFFU) 00442 #define ADC_CV2_CV_SHIFT (0U) 00443 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) 00444 00445 /*! @name SC2 - Status and Control Register 2 */ 00446 #define ADC_SC2_REFSEL_MASK (0x3U) 00447 #define ADC_SC2_REFSEL_SHIFT (0U) 00448 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) 00449 #define ADC_SC2_DMAEN_MASK (0x4U) 00450 #define ADC_SC2_DMAEN_SHIFT (2U) 00451 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) 00452 #define ADC_SC2_ACREN_MASK (0x8U) 00453 #define ADC_SC2_ACREN_SHIFT (3U) 00454 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) 00455 #define ADC_SC2_ACFGT_MASK (0x10U) 00456 #define ADC_SC2_ACFGT_SHIFT (4U) 00457 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) 00458 #define ADC_SC2_ACFE_MASK (0x20U) 00459 #define ADC_SC2_ACFE_SHIFT (5U) 00460 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) 00461 #define ADC_SC2_ADTRG_MASK (0x40U) 00462 #define ADC_SC2_ADTRG_SHIFT (6U) 00463 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) 00464 #define ADC_SC2_ADACT_MASK (0x80U) 00465 #define ADC_SC2_ADACT_SHIFT (7U) 00466 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) 00467 00468 /*! @name SC3 - Status and Control Register 3 */ 00469 #define ADC_SC3_AVGS_MASK (0x3U) 00470 #define ADC_SC3_AVGS_SHIFT (0U) 00471 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) 00472 #define ADC_SC3_AVGE_MASK (0x4U) 00473 #define ADC_SC3_AVGE_SHIFT (2U) 00474 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) 00475 #define ADC_SC3_ADCO_MASK (0x8U) 00476 #define ADC_SC3_ADCO_SHIFT (3U) 00477 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) 00478 #define ADC_SC3_CALF_MASK (0x40U) 00479 #define ADC_SC3_CALF_SHIFT (6U) 00480 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) 00481 #define ADC_SC3_CAL_MASK (0x80U) 00482 #define ADC_SC3_CAL_SHIFT (7U) 00483 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) 00484 00485 /*! @name OFS - ADC Offset Correction Register */ 00486 #define ADC_OFS_OFS_MASK (0xFFFFU) 00487 #define ADC_OFS_OFS_SHIFT (0U) 00488 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) 00489 00490 /*! @name PG - ADC Plus-Side Gain Register */ 00491 #define ADC_PG_PG_MASK (0xFFFFU) 00492 #define ADC_PG_PG_SHIFT (0U) 00493 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) 00494 00495 /*! @name MG - ADC Minus-Side Gain Register */ 00496 #define ADC_MG_MG_MASK (0xFFFFU) 00497 #define ADC_MG_MG_SHIFT (0U) 00498 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) 00499 00500 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */ 00501 #define ADC_CLPD_CLPD_MASK (0x3FU) 00502 #define ADC_CLPD_CLPD_SHIFT (0U) 00503 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) 00504 00505 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */ 00506 #define ADC_CLPS_CLPS_MASK (0x3FU) 00507 #define ADC_CLPS_CLPS_SHIFT (0U) 00508 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) 00509 00510 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ 00511 #define ADC_CLP4_CLP4_MASK (0x3FFU) 00512 #define ADC_CLP4_CLP4_SHIFT (0U) 00513 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) 00514 00515 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ 00516 #define ADC_CLP3_CLP3_MASK (0x1FFU) 00517 #define ADC_CLP3_CLP3_SHIFT (0U) 00518 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) 00519 00520 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ 00521 #define ADC_CLP2_CLP2_MASK (0xFFU) 00522 #define ADC_CLP2_CLP2_SHIFT (0U) 00523 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) 00524 00525 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ 00526 #define ADC_CLP1_CLP1_MASK (0x7FU) 00527 #define ADC_CLP1_CLP1_SHIFT (0U) 00528 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) 00529 00530 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ 00531 #define ADC_CLP0_CLP0_MASK (0x3FU) 00532 #define ADC_CLP0_CLP0_SHIFT (0U) 00533 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) 00534 00535 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */ 00536 #define ADC_CLMD_CLMD_MASK (0x3FU) 00537 #define ADC_CLMD_CLMD_SHIFT (0U) 00538 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) 00539 00540 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */ 00541 #define ADC_CLMS_CLMS_MASK (0x3FU) 00542 #define ADC_CLMS_CLMS_SHIFT (0U) 00543 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) 00544 00545 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ 00546 #define ADC_CLM4_CLM4_MASK (0x3FFU) 00547 #define ADC_CLM4_CLM4_SHIFT (0U) 00548 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) 00549 00550 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ 00551 #define ADC_CLM3_CLM3_MASK (0x1FFU) 00552 #define ADC_CLM3_CLM3_SHIFT (0U) 00553 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) 00554 00555 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ 00556 #define ADC_CLM2_CLM2_MASK (0xFFU) 00557 #define ADC_CLM2_CLM2_SHIFT (0U) 00558 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) 00559 00560 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ 00561 #define ADC_CLM1_CLM1_MASK (0x7FU) 00562 #define ADC_CLM1_CLM1_SHIFT (0U) 00563 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) 00564 00565 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ 00566 #define ADC_CLM0_CLM0_MASK (0x3FU) 00567 #define ADC_CLM0_CLM0_SHIFT (0U) 00568 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) 00569 00570 00571 /*! 00572 * @} 00573 */ /* end of group ADC_Register_Masks */ 00574 00575 00576 /* ADC - Peripheral instance base addresses */ 00577 /** Peripheral ADC0 base address */ 00578 #define ADC0_BASE (0x4003B000u) 00579 /** Peripheral ADC0 base pointer */ 00580 #define ADC0 ((ADC_Type *)ADC0_BASE) 00581 /** Array initializer of ADC peripheral base addresses */ 00582 #define ADC_BASE_ADDRS { ADC0_BASE } 00583 /** Array initializer of ADC peripheral base pointers */ 00584 #define ADC_BASE_PTRS { ADC0 } 00585 /** Interrupt vectors for the ADC peripheral type */ 00586 #define ADC_IRQS { ADC0_IRQn } 00587 00588 /*! 00589 * @} 00590 */ /* end of group ADC_Peripheral_Access_Layer */ 00591 00592 00593 /* ---------------------------------------------------------------------------- 00594 -- CMP Peripheral Access Layer 00595 ---------------------------------------------------------------------------- */ 00596 00597 /*! 00598 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer 00599 * @{ 00600 */ 00601 00602 /** CMP - Register Layout Typedef */ 00603 typedef struct { 00604 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ 00605 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ 00606 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ 00607 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ 00608 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ 00609 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ 00610 } CMP_Type; 00611 00612 /* ---------------------------------------------------------------------------- 00613 -- CMP Register Masks 00614 ---------------------------------------------------------------------------- */ 00615 00616 /*! 00617 * @addtogroup CMP_Register_Masks CMP Register Masks 00618 * @{ 00619 */ 00620 00621 /*! @name CR0 - CMP Control Register 0 */ 00622 #define CMP_CR0_HYSTCTR_MASK (0x3U) 00623 #define CMP_CR0_HYSTCTR_SHIFT (0U) 00624 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) 00625 #define CMP_CR0_FILTER_CNT_MASK (0x70U) 00626 #define CMP_CR0_FILTER_CNT_SHIFT (4U) 00627 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) 00628 00629 /*! @name CR1 - CMP Control Register 1 */ 00630 #define CMP_CR1_EN_MASK (0x1U) 00631 #define CMP_CR1_EN_SHIFT (0U) 00632 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) 00633 #define CMP_CR1_OPE_MASK (0x2U) 00634 #define CMP_CR1_OPE_SHIFT (1U) 00635 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) 00636 #define CMP_CR1_COS_MASK (0x4U) 00637 #define CMP_CR1_COS_SHIFT (2U) 00638 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) 00639 #define CMP_CR1_INV_MASK (0x8U) 00640 #define CMP_CR1_INV_SHIFT (3U) 00641 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) 00642 #define CMP_CR1_PMODE_MASK (0x10U) 00643 #define CMP_CR1_PMODE_SHIFT (4U) 00644 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) 00645 #define CMP_CR1_TRIGM_MASK (0x20U) 00646 #define CMP_CR1_TRIGM_SHIFT (5U) 00647 #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK) 00648 #define CMP_CR1_WE_MASK (0x40U) 00649 #define CMP_CR1_WE_SHIFT (6U) 00650 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) 00651 #define CMP_CR1_SE_MASK (0x80U) 00652 #define CMP_CR1_SE_SHIFT (7U) 00653 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) 00654 00655 /*! @name FPR - CMP Filter Period Register */ 00656 #define CMP_FPR_FILT_PER_MASK (0xFFU) 00657 #define CMP_FPR_FILT_PER_SHIFT (0U) 00658 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) 00659 00660 /*! @name SCR - CMP Status and Control Register */ 00661 #define CMP_SCR_COUT_MASK (0x1U) 00662 #define CMP_SCR_COUT_SHIFT (0U) 00663 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) 00664 #define CMP_SCR_CFF_MASK (0x2U) 00665 #define CMP_SCR_CFF_SHIFT (1U) 00666 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) 00667 #define CMP_SCR_CFR_MASK (0x4U) 00668 #define CMP_SCR_CFR_SHIFT (2U) 00669 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) 00670 #define CMP_SCR_IEF_MASK (0x8U) 00671 #define CMP_SCR_IEF_SHIFT (3U) 00672 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) 00673 #define CMP_SCR_IER_MASK (0x10U) 00674 #define CMP_SCR_IER_SHIFT (4U) 00675 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) 00676 #define CMP_SCR_DMAEN_MASK (0x40U) 00677 #define CMP_SCR_DMAEN_SHIFT (6U) 00678 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) 00679 00680 /*! @name DACCR - DAC Control Register */ 00681 #define CMP_DACCR_VOSEL_MASK (0x3FU) 00682 #define CMP_DACCR_VOSEL_SHIFT (0U) 00683 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) 00684 #define CMP_DACCR_VRSEL_MASK (0x40U) 00685 #define CMP_DACCR_VRSEL_SHIFT (6U) 00686 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) 00687 #define CMP_DACCR_DACEN_MASK (0x80U) 00688 #define CMP_DACCR_DACEN_SHIFT (7U) 00689 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) 00690 00691 /*! @name MUXCR - MUX Control Register */ 00692 #define CMP_MUXCR_MSEL_MASK (0x7U) 00693 #define CMP_MUXCR_MSEL_SHIFT (0U) 00694 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) 00695 #define CMP_MUXCR_PSEL_MASK (0x38U) 00696 #define CMP_MUXCR_PSEL_SHIFT (3U) 00697 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) 00698 #define CMP_MUXCR_PSTM_MASK (0x80U) 00699 #define CMP_MUXCR_PSTM_SHIFT (7U) 00700 #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK) 00701 00702 00703 /*! 00704 * @} 00705 */ /* end of group CMP_Register_Masks */ 00706 00707 00708 /* CMP - Peripheral instance base addresses */ 00709 /** Peripheral CMP0 base address */ 00710 #define CMP0_BASE (0x40073000u) 00711 /** Peripheral CMP0 base pointer */ 00712 #define CMP0 ((CMP_Type *)CMP0_BASE) 00713 /** Array initializer of CMP peripheral base addresses */ 00714 #define CMP_BASE_ADDRS { CMP0_BASE } 00715 /** Array initializer of CMP peripheral base pointers */ 00716 #define CMP_BASE_PTRS { CMP0 } 00717 /** Interrupt vectors for the CMP peripheral type */ 00718 #define CMP_IRQS { CMP0_IRQn } 00719 00720 /*! 00721 * @} 00722 */ /* end of group CMP_Peripheral_Access_Layer */ 00723 00724 00725 /* ---------------------------------------------------------------------------- 00726 -- DAC Peripheral Access Layer 00727 ---------------------------------------------------------------------------- */ 00728 00729 /*! 00730 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer 00731 * @{ 00732 */ 00733 00734 /** DAC - Register Layout Typedef */ 00735 typedef struct { 00736 struct { /* offset: 0x0, array step: 0x2 */ 00737 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ 00738 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ 00739 } DAT[2]; 00740 uint8_t RESERVED_0[28]; 00741 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ 00742 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ 00743 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ 00744 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ 00745 } DAC_Type; 00746 00747 /* ---------------------------------------------------------------------------- 00748 -- DAC Register Masks 00749 ---------------------------------------------------------------------------- */ 00750 00751 /*! 00752 * @addtogroup DAC_Register_Masks DAC Register Masks 00753 * @{ 00754 */ 00755 00756 /*! @name DATL - DAC Data Low Register */ 00757 #define DAC_DATL_DATA0_MASK (0xFFU) 00758 #define DAC_DATL_DATA0_SHIFT (0U) 00759 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK) 00760 00761 /* The count of DAC_DATL */ 00762 #define DAC_DATL_COUNT (2U) 00763 00764 /*! @name DATH - DAC Data High Register */ 00765 #define DAC_DATH_DATA1_MASK (0xFU) 00766 #define DAC_DATH_DATA1_SHIFT (0U) 00767 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK) 00768 00769 /* The count of DAC_DATH */ 00770 #define DAC_DATH_COUNT (2U) 00771 00772 /*! @name SR - DAC Status Register */ 00773 #define DAC_SR_DACBFRPBF_MASK (0x1U) 00774 #define DAC_SR_DACBFRPBF_SHIFT (0U) 00775 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK) 00776 #define DAC_SR_DACBFRPTF_MASK (0x2U) 00777 #define DAC_SR_DACBFRPTF_SHIFT (1U) 00778 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK) 00779 00780 /*! @name C0 - DAC Control Register */ 00781 #define DAC_C0_DACBBIEN_MASK (0x1U) 00782 #define DAC_C0_DACBBIEN_SHIFT (0U) 00783 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK) 00784 #define DAC_C0_DACBTIEN_MASK (0x2U) 00785 #define DAC_C0_DACBTIEN_SHIFT (1U) 00786 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK) 00787 #define DAC_C0_LPEN_MASK (0x8U) 00788 #define DAC_C0_LPEN_SHIFT (3U) 00789 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK) 00790 #define DAC_C0_DACSWTRG_MASK (0x10U) 00791 #define DAC_C0_DACSWTRG_SHIFT (4U) 00792 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK) 00793 #define DAC_C0_DACTRGSEL_MASK (0x20U) 00794 #define DAC_C0_DACTRGSEL_SHIFT (5U) 00795 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK) 00796 #define DAC_C0_DACRFS_MASK (0x40U) 00797 #define DAC_C0_DACRFS_SHIFT (6U) 00798 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK) 00799 #define DAC_C0_DACEN_MASK (0x80U) 00800 #define DAC_C0_DACEN_SHIFT (7U) 00801 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK) 00802 00803 /*! @name C1 - DAC Control Register 1 */ 00804 #define DAC_C1_DACBFEN_MASK (0x1U) 00805 #define DAC_C1_DACBFEN_SHIFT (0U) 00806 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK) 00807 #define DAC_C1_DACBFMD_MASK (0x4U) 00808 #define DAC_C1_DACBFMD_SHIFT (2U) 00809 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK) 00810 #define DAC_C1_DMAEN_MASK (0x80U) 00811 #define DAC_C1_DMAEN_SHIFT (7U) 00812 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK) 00813 00814 /*! @name C2 - DAC Control Register 2 */ 00815 #define DAC_C2_DACBFUP_MASK (0x1U) 00816 #define DAC_C2_DACBFUP_SHIFT (0U) 00817 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK) 00818 #define DAC_C2_DACBFRP_MASK (0x10U) 00819 #define DAC_C2_DACBFRP_SHIFT (4U) 00820 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK) 00821 00822 00823 /*! 00824 * @} 00825 */ /* end of group DAC_Register_Masks */ 00826 00827 00828 /* DAC - Peripheral instance base addresses */ 00829 /** Peripheral DAC0 base address */ 00830 #define DAC0_BASE (0x4003F000u) 00831 /** Peripheral DAC0 base pointer */ 00832 #define DAC0 ((DAC_Type *)DAC0_BASE) 00833 /** Array initializer of DAC peripheral base addresses */ 00834 #define DAC_BASE_ADDRS { DAC0_BASE } 00835 /** Array initializer of DAC peripheral base pointers */ 00836 #define DAC_BASE_PTRS { DAC0 } 00837 /** Interrupt vectors for the DAC peripheral type */ 00838 #define DAC_IRQS { DAC0_IRQn } 00839 00840 /*! 00841 * @} 00842 */ /* end of group DAC_Peripheral_Access_Layer */ 00843 00844 00845 /* ---------------------------------------------------------------------------- 00846 -- DMA Peripheral Access Layer 00847 ---------------------------------------------------------------------------- */ 00848 00849 /*! 00850 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer 00851 * @{ 00852 */ 00853 00854 /** DMA - Register Layout Typedef */ 00855 typedef struct { 00856 uint8_t RESERVED_0[256]; 00857 struct { /* offset: 0x100, array step: 0x10 */ 00858 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */ 00859 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */ 00860 union { /* offset: 0x108, array step: 0x10 */ 00861 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */ 00862 struct { /* offset: 0x108, array step: 0x10 */ 00863 uint8_t RESERVED_0[3]; 00864 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */ 00865 } DMA_DSR_ACCESS8BIT; 00866 }; 00867 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */ 00868 } DMA[4]; 00869 } DMA_Type; 00870 00871 /* ---------------------------------------------------------------------------- 00872 -- DMA Register Masks 00873 ---------------------------------------------------------------------------- */ 00874 00875 /*! 00876 * @addtogroup DMA_Register_Masks DMA Register Masks 00877 * @{ 00878 */ 00879 00880 /*! @name SAR - Source Address Register */ 00881 #define DMA_SAR_SAR_MASK (0xFFFFFFFFU) 00882 #define DMA_SAR_SAR_SHIFT (0U) 00883 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SAR_SAR_SHIFT)) & DMA_SAR_SAR_MASK) 00884 00885 /* The count of DMA_SAR */ 00886 #define DMA_SAR_COUNT (4U) 00887 00888 /*! @name DAR - Destination Address Register */ 00889 #define DMA_DAR_DAR_MASK (0xFFFFFFFFU) 00890 #define DMA_DAR_DAR_SHIFT (0U) 00891 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DAR_DAR_SHIFT)) & DMA_DAR_DAR_MASK) 00892 00893 /* The count of DMA_DAR */ 00894 #define DMA_DAR_COUNT (4U) 00895 00896 /*! @name DSR_BCR - DMA Status Register / Byte Count Register */ 00897 #define DMA_DSR_BCR_BCR_MASK (0xFFFFFFU) 00898 #define DMA_DSR_BCR_BCR_SHIFT (0U) 00899 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BCR_SHIFT)) & DMA_DSR_BCR_BCR_MASK) 00900 #define DMA_DSR_BCR_DONE_MASK (0x1000000U) 00901 #define DMA_DSR_BCR_DONE_SHIFT (24U) 00902 #define DMA_DSR_BCR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_DONE_SHIFT)) & DMA_DSR_BCR_DONE_MASK) 00903 #define DMA_DSR_BCR_BSY_MASK (0x2000000U) 00904 #define DMA_DSR_BCR_BSY_SHIFT (25U) 00905 #define DMA_DSR_BCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BSY_SHIFT)) & DMA_DSR_BCR_BSY_MASK) 00906 #define DMA_DSR_BCR_REQ_MASK (0x4000000U) 00907 #define DMA_DSR_BCR_REQ_SHIFT (26U) 00908 #define DMA_DSR_BCR_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_REQ_SHIFT)) & DMA_DSR_BCR_REQ_MASK) 00909 #define DMA_DSR_BCR_BED_MASK (0x10000000U) 00910 #define DMA_DSR_BCR_BED_SHIFT (28U) 00911 #define DMA_DSR_BCR_BED(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BED_SHIFT)) & DMA_DSR_BCR_BED_MASK) 00912 #define DMA_DSR_BCR_BES_MASK (0x20000000U) 00913 #define DMA_DSR_BCR_BES_SHIFT (29U) 00914 #define DMA_DSR_BCR_BES(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BES_SHIFT)) & DMA_DSR_BCR_BES_MASK) 00915 #define DMA_DSR_BCR_CE_MASK (0x40000000U) 00916 #define DMA_DSR_BCR_CE_SHIFT (30U) 00917 #define DMA_DSR_BCR_CE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_CE_SHIFT)) & DMA_DSR_BCR_CE_MASK) 00918 00919 /* The count of DMA_DSR_BCR */ 00920 #define DMA_DSR_BCR_COUNT (4U) 00921 00922 /* The count of DMA_DSR */ 00923 #define DMA_DSR_COUNT (4U) 00924 00925 /*! @name DCR - DMA Control Register */ 00926 #define DMA_DCR_LCH2_MASK (0x3U) 00927 #define DMA_DCR_LCH2_SHIFT (0U) 00928 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH2_SHIFT)) & DMA_DCR_LCH2_MASK) 00929 #define DMA_DCR_LCH1_MASK (0xCU) 00930 #define DMA_DCR_LCH1_SHIFT (2U) 00931 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH1_SHIFT)) & DMA_DCR_LCH1_MASK) 00932 #define DMA_DCR_LINKCC_MASK (0x30U) 00933 #define DMA_DCR_LINKCC_SHIFT (4U) 00934 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LINKCC_SHIFT)) & DMA_DCR_LINKCC_MASK) 00935 #define DMA_DCR_D_REQ_MASK (0x80U) 00936 #define DMA_DCR_D_REQ_SHIFT (7U) 00937 #define DMA_DCR_D_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_D_REQ_SHIFT)) & DMA_DCR_D_REQ_MASK) 00938 #define DMA_DCR_DMOD_MASK (0xF00U) 00939 #define DMA_DCR_DMOD_SHIFT (8U) 00940 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DMOD_SHIFT)) & DMA_DCR_DMOD_MASK) 00941 #define DMA_DCR_SMOD_MASK (0xF000U) 00942 #define DMA_DCR_SMOD_SHIFT (12U) 00943 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SMOD_SHIFT)) & DMA_DCR_SMOD_MASK) 00944 #define DMA_DCR_START_MASK (0x10000U) 00945 #define DMA_DCR_START_SHIFT (16U) 00946 #define DMA_DCR_START(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_START_SHIFT)) & DMA_DCR_START_MASK) 00947 #define DMA_DCR_DSIZE_MASK (0x60000U) 00948 #define DMA_DCR_DSIZE_SHIFT (17U) 00949 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DSIZE_SHIFT)) & DMA_DCR_DSIZE_MASK) 00950 #define DMA_DCR_DINC_MASK (0x80000U) 00951 #define DMA_DCR_DINC_SHIFT (19U) 00952 #define DMA_DCR_DINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DINC_SHIFT)) & DMA_DCR_DINC_MASK) 00953 #define DMA_DCR_SSIZE_MASK (0x300000U) 00954 #define DMA_DCR_SSIZE_SHIFT (20U) 00955 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SSIZE_SHIFT)) & DMA_DCR_SSIZE_MASK) 00956 #define DMA_DCR_SINC_MASK (0x400000U) 00957 #define DMA_DCR_SINC_SHIFT (22U) 00958 #define DMA_DCR_SINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SINC_SHIFT)) & DMA_DCR_SINC_MASK) 00959 #define DMA_DCR_EADREQ_MASK (0x800000U) 00960 #define DMA_DCR_EADREQ_SHIFT (23U) 00961 #define DMA_DCR_EADREQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EADREQ_SHIFT)) & DMA_DCR_EADREQ_MASK) 00962 #define DMA_DCR_AA_MASK (0x10000000U) 00963 #define DMA_DCR_AA_SHIFT (28U) 00964 #define DMA_DCR_AA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_AA_SHIFT)) & DMA_DCR_AA_MASK) 00965 #define DMA_DCR_CS_MASK (0x20000000U) 00966 #define DMA_DCR_CS_SHIFT (29U) 00967 #define DMA_DCR_CS(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CS_SHIFT)) & DMA_DCR_CS_MASK) 00968 #define DMA_DCR_ERQ_MASK (0x40000000U) 00969 #define DMA_DCR_ERQ_SHIFT (30U) 00970 #define DMA_DCR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_ERQ_SHIFT)) & DMA_DCR_ERQ_MASK) 00971 #define DMA_DCR_EINT_MASK (0x80000000U) 00972 #define DMA_DCR_EINT_SHIFT (31U) 00973 #define DMA_DCR_EINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EINT_SHIFT)) & DMA_DCR_EINT_MASK) 00974 00975 /* The count of DMA_DCR */ 00976 #define DMA_DCR_COUNT (4U) 00977 00978 00979 /*! 00980 * @} 00981 */ /* end of group DMA_Register_Masks */ 00982 00983 00984 /* DMA - Peripheral instance base addresses */ 00985 /** Peripheral DMA base address */ 00986 #define DMA_BASE (0x40008000u) 00987 /** Peripheral DMA base pointer */ 00988 #define DMA0 ((DMA_Type *)DMA_BASE) 00989 /** Array initializer of DMA peripheral base addresses */ 00990 #define DMA_BASE_ADDRS { DMA_BASE } 00991 /** Array initializer of DMA peripheral base pointers */ 00992 #define DMA_BASE_PTRS { DMA0 } 00993 /** Interrupt vectors for the DMA peripheral type */ 00994 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } 00995 00996 /*! 00997 * @} 00998 */ /* end of group DMA_Peripheral_Access_Layer */ 00999 01000 01001 /* ---------------------------------------------------------------------------- 01002 -- DMAMUX Peripheral Access Layer 01003 ---------------------------------------------------------------------------- */ 01004 01005 /*! 01006 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer 01007 * @{ 01008 */ 01009 01010 /** DMAMUX - Register Layout Typedef */ 01011 typedef struct { 01012 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ 01013 } DMAMUX_Type; 01014 01015 /* ---------------------------------------------------------------------------- 01016 -- DMAMUX Register Masks 01017 ---------------------------------------------------------------------------- */ 01018 01019 /*! 01020 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks 01021 * @{ 01022 */ 01023 01024 /*! @name CHCFG - Channel Configuration register */ 01025 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) 01026 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) 01027 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) 01028 #define DMAMUX_CHCFG_TRIG_MASK (0x40U) 01029 #define DMAMUX_CHCFG_TRIG_SHIFT (6U) 01030 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) 01031 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) 01032 #define DMAMUX_CHCFG_ENBL_SHIFT (7U) 01033 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) 01034 01035 /* The count of DMAMUX_CHCFG */ 01036 #define DMAMUX_CHCFG_COUNT (4U) 01037 01038 01039 /*! 01040 * @} 01041 */ /* end of group DMAMUX_Register_Masks */ 01042 01043 01044 /* DMAMUX - Peripheral instance base addresses */ 01045 /** Peripheral DMAMUX0 base address */ 01046 #define DMAMUX0_BASE (0x40021000u) 01047 /** Peripheral DMAMUX0 base pointer */ 01048 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE) 01049 /** Array initializer of DMAMUX peripheral base addresses */ 01050 #define DMAMUX_BASE_ADDRS { DMAMUX0_BASE } 01051 /** Array initializer of DMAMUX peripheral base pointers */ 01052 #define DMAMUX_BASE_PTRS { DMAMUX0 } 01053 01054 /*! 01055 * @} 01056 */ /* end of group DMAMUX_Peripheral_Access_Layer */ 01057 01058 01059 /* ---------------------------------------------------------------------------- 01060 -- FGPIO Peripheral Access Layer 01061 ---------------------------------------------------------------------------- */ 01062 01063 /*! 01064 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer 01065 * @{ 01066 */ 01067 01068 /** FGPIO - Register Layout Typedef */ 01069 typedef struct { 01070 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 01071 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 01072 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 01073 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 01074 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 01075 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 01076 } FGPIO_Type; 01077 01078 /* ---------------------------------------------------------------------------- 01079 -- FGPIO Register Masks 01080 ---------------------------------------------------------------------------- */ 01081 01082 /*! 01083 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks 01084 * @{ 01085 */ 01086 01087 /*! @name PDOR - Port Data Output Register */ 01088 #define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 01089 #define FGPIO_PDOR_PDO_SHIFT (0U) 01090 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK) 01091 01092 /*! @name PSOR - Port Set Output Register */ 01093 #define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 01094 #define FGPIO_PSOR_PTSO_SHIFT (0U) 01095 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK) 01096 01097 /*! @name PCOR - Port Clear Output Register */ 01098 #define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 01099 #define FGPIO_PCOR_PTCO_SHIFT (0U) 01100 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK) 01101 01102 /*! @name PTOR - Port Toggle Output Register */ 01103 #define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 01104 #define FGPIO_PTOR_PTTO_SHIFT (0U) 01105 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK) 01106 01107 /*! @name PDIR - Port Data Input Register */ 01108 #define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 01109 #define FGPIO_PDIR_PDI_SHIFT (0U) 01110 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK) 01111 01112 /*! @name PDDR - Port Data Direction Register */ 01113 #define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 01114 #define FGPIO_PDDR_PDD_SHIFT (0U) 01115 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK) 01116 01117 01118 /*! 01119 * @} 01120 */ /* end of group FGPIO_Register_Masks */ 01121 01122 01123 /* FGPIO - Peripheral instance base addresses */ 01124 /** Peripheral FGPIOA base address */ 01125 #define FGPIOA_BASE (0xF8000000u) 01126 /** Peripheral FGPIOA base pointer */ 01127 #define FGPIOA ((FGPIO_Type *)FGPIOA_BASE) 01128 /** Peripheral FGPIOB base address */ 01129 #define FGPIOB_BASE (0xF8000040u) 01130 /** Peripheral FGPIOB base pointer */ 01131 #define FGPIOB ((FGPIO_Type *)FGPIOB_BASE) 01132 /** Peripheral FGPIOC base address */ 01133 #define FGPIOC_BASE (0xF8000080u) 01134 /** Peripheral FGPIOC base pointer */ 01135 #define FGPIOC ((FGPIO_Type *)FGPIOC_BASE) 01136 /** Peripheral FGPIOD base address */ 01137 #define FGPIOD_BASE (0xF80000C0u) 01138 /** Peripheral FGPIOD base pointer */ 01139 #define FGPIOD ((FGPIO_Type *)FGPIOD_BASE) 01140 /** Peripheral FGPIOE base address */ 01141 #define FGPIOE_BASE (0xF8000100u) 01142 /** Peripheral FGPIOE base pointer */ 01143 #define FGPIOE ((FGPIO_Type *)FGPIOE_BASE) 01144 /** Array initializer of FGPIO peripheral base addresses */ 01145 #define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE } 01146 /** Array initializer of FGPIO peripheral base pointers */ 01147 #define FGPIO_BASE_PTRS { FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE } 01148 01149 /*! 01150 * @} 01151 */ /* end of group FGPIO_Peripheral_Access_Layer */ 01152 01153 01154 /* ---------------------------------------------------------------------------- 01155 -- FTFA Peripheral Access Layer 01156 ---------------------------------------------------------------------------- */ 01157 01158 /*! 01159 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer 01160 * @{ 01161 */ 01162 01163 /** FTFA - Register Layout Typedef */ 01164 typedef struct { 01165 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ 01166 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ 01167 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ 01168 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ 01169 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ 01170 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ 01171 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ 01172 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ 01173 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ 01174 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ 01175 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ 01176 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ 01177 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ 01178 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ 01179 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ 01180 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ 01181 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ 01182 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ 01183 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ 01184 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ 01185 } FTFA_Type; 01186 01187 /* ---------------------------------------------------------------------------- 01188 -- FTFA Register Masks 01189 ---------------------------------------------------------------------------- */ 01190 01191 /*! 01192 * @addtogroup FTFA_Register_Masks FTFA Register Masks 01193 * @{ 01194 */ 01195 01196 /*! @name FSTAT - Flash Status Register */ 01197 #define FTFA_FSTAT_MGSTAT0_MASK (0x1U) 01198 #define FTFA_FSTAT_MGSTAT0_SHIFT (0U) 01199 #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK) 01200 #define FTFA_FSTAT_FPVIOL_MASK (0x10U) 01201 #define FTFA_FSTAT_FPVIOL_SHIFT (4U) 01202 #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK) 01203 #define FTFA_FSTAT_ACCERR_MASK (0x20U) 01204 #define FTFA_FSTAT_ACCERR_SHIFT (5U) 01205 #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK) 01206 #define FTFA_FSTAT_RDCOLERR_MASK (0x40U) 01207 #define FTFA_FSTAT_RDCOLERR_SHIFT (6U) 01208 #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK) 01209 #define FTFA_FSTAT_CCIF_MASK (0x80U) 01210 #define FTFA_FSTAT_CCIF_SHIFT (7U) 01211 #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK) 01212 01213 /*! @name FCNFG - Flash Configuration Register */ 01214 #define FTFA_FCNFG_ERSSUSP_MASK (0x10U) 01215 #define FTFA_FCNFG_ERSSUSP_SHIFT (4U) 01216 #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK) 01217 #define FTFA_FCNFG_ERSAREQ_MASK (0x20U) 01218 #define FTFA_FCNFG_ERSAREQ_SHIFT (5U) 01219 #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK) 01220 #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U) 01221 #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U) 01222 #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK) 01223 #define FTFA_FCNFG_CCIE_MASK (0x80U) 01224 #define FTFA_FCNFG_CCIE_SHIFT (7U) 01225 #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK) 01226 01227 /*! @name FSEC - Flash Security Register */ 01228 #define FTFA_FSEC_SEC_MASK (0x3U) 01229 #define FTFA_FSEC_SEC_SHIFT (0U) 01230 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK) 01231 #define FTFA_FSEC_FSLACC_MASK (0xCU) 01232 #define FTFA_FSEC_FSLACC_SHIFT (2U) 01233 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK) 01234 #define FTFA_FSEC_MEEN_MASK (0x30U) 01235 #define FTFA_FSEC_MEEN_SHIFT (4U) 01236 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK) 01237 #define FTFA_FSEC_KEYEN_MASK (0xC0U) 01238 #define FTFA_FSEC_KEYEN_SHIFT (6U) 01239 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK) 01240 01241 /*! @name FOPT - Flash Option Register */ 01242 #define FTFA_FOPT_OPT_MASK (0xFFU) 01243 #define FTFA_FOPT_OPT_SHIFT (0U) 01244 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK) 01245 01246 /*! @name FCCOB3 - Flash Common Command Object Registers */ 01247 #define FTFA_FCCOB3_CCOBn_MASK (0xFFU) 01248 #define FTFA_FCCOB3_CCOBn_SHIFT (0U) 01249 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK) 01250 01251 /*! @name FCCOB2 - Flash Common Command Object Registers */ 01252 #define FTFA_FCCOB2_CCOBn_MASK (0xFFU) 01253 #define FTFA_FCCOB2_CCOBn_SHIFT (0U) 01254 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK) 01255 01256 /*! @name FCCOB1 - Flash Common Command Object Registers */ 01257 #define FTFA_FCCOB1_CCOBn_MASK (0xFFU) 01258 #define FTFA_FCCOB1_CCOBn_SHIFT (0U) 01259 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK) 01260 01261 /*! @name FCCOB0 - Flash Common Command Object Registers */ 01262 #define FTFA_FCCOB0_CCOBn_MASK (0xFFU) 01263 #define FTFA_FCCOB0_CCOBn_SHIFT (0U) 01264 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK) 01265 01266 /*! @name FCCOB7 - Flash Common Command Object Registers */ 01267 #define FTFA_FCCOB7_CCOBn_MASK (0xFFU) 01268 #define FTFA_FCCOB7_CCOBn_SHIFT (0U) 01269 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK) 01270 01271 /*! @name FCCOB6 - Flash Common Command Object Registers */ 01272 #define FTFA_FCCOB6_CCOBn_MASK (0xFFU) 01273 #define FTFA_FCCOB6_CCOBn_SHIFT (0U) 01274 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK) 01275 01276 /*! @name FCCOB5 - Flash Common Command Object Registers */ 01277 #define FTFA_FCCOB5_CCOBn_MASK (0xFFU) 01278 #define FTFA_FCCOB5_CCOBn_SHIFT (0U) 01279 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK) 01280 01281 /*! @name FCCOB4 - Flash Common Command Object Registers */ 01282 #define FTFA_FCCOB4_CCOBn_MASK (0xFFU) 01283 #define FTFA_FCCOB4_CCOBn_SHIFT (0U) 01284 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK) 01285 01286 /*! @name FCCOBB - Flash Common Command Object Registers */ 01287 #define FTFA_FCCOBB_CCOBn_MASK (0xFFU) 01288 #define FTFA_FCCOBB_CCOBn_SHIFT (0U) 01289 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK) 01290 01291 /*! @name FCCOBA - Flash Common Command Object Registers */ 01292 #define FTFA_FCCOBA_CCOBn_MASK (0xFFU) 01293 #define FTFA_FCCOBA_CCOBn_SHIFT (0U) 01294 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK) 01295 01296 /*! @name FCCOB9 - Flash Common Command Object Registers */ 01297 #define FTFA_FCCOB9_CCOBn_MASK (0xFFU) 01298 #define FTFA_FCCOB9_CCOBn_SHIFT (0U) 01299 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK) 01300 01301 /*! @name FCCOB8 - Flash Common Command Object Registers */ 01302 #define FTFA_FCCOB8_CCOBn_MASK (0xFFU) 01303 #define FTFA_FCCOB8_CCOBn_SHIFT (0U) 01304 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK) 01305 01306 /*! @name FPROT3 - Program Flash Protection Registers */ 01307 #define FTFA_FPROT3_PROT_MASK (0xFFU) 01308 #define FTFA_FPROT3_PROT_SHIFT (0U) 01309 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK) 01310 01311 /*! @name FPROT2 - Program Flash Protection Registers */ 01312 #define FTFA_FPROT2_PROT_MASK (0xFFU) 01313 #define FTFA_FPROT2_PROT_SHIFT (0U) 01314 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK) 01315 01316 /*! @name FPROT1 - Program Flash Protection Registers */ 01317 #define FTFA_FPROT1_PROT_MASK (0xFFU) 01318 #define FTFA_FPROT1_PROT_SHIFT (0U) 01319 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK) 01320 01321 /*! @name FPROT0 - Program Flash Protection Registers */ 01322 #define FTFA_FPROT0_PROT_MASK (0xFFU) 01323 #define FTFA_FPROT0_PROT_SHIFT (0U) 01324 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK) 01325 01326 01327 /*! 01328 * @} 01329 */ /* end of group FTFA_Register_Masks */ 01330 01331 01332 /* FTFA - Peripheral instance base addresses */ 01333 /** Peripheral FTFA base address */ 01334 #define FTFA_BASE (0x40020000u) 01335 /** Peripheral FTFA base pointer */ 01336 #define FTFA ((FTFA_Type *)FTFA_BASE) 01337 /** Array initializer of FTFA peripheral base addresses */ 01338 #define FTFA_BASE_ADDRS { FTFA_BASE } 01339 /** Array initializer of FTFA peripheral base pointers */ 01340 #define FTFA_BASE_PTRS { FTFA } 01341 /** Interrupt vectors for the FTFA peripheral type */ 01342 #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn } 01343 01344 /*! 01345 * @} 01346 */ /* end of group FTFA_Peripheral_Access_Layer */ 01347 01348 01349 /* ---------------------------------------------------------------------------- 01350 -- GPIO Peripheral Access Layer 01351 ---------------------------------------------------------------------------- */ 01352 01353 /*! 01354 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 01355 * @{ 01356 */ 01357 01358 /** GPIO - Register Layout Typedef */ 01359 typedef struct { 01360 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 01361 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 01362 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 01363 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 01364 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 01365 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 01366 } GPIO_Type; 01367 01368 /* ---------------------------------------------------------------------------- 01369 -- GPIO Register Masks 01370 ---------------------------------------------------------------------------- */ 01371 01372 /*! 01373 * @addtogroup GPIO_Register_Masks GPIO Register Masks 01374 * @{ 01375 */ 01376 01377 /*! @name PDOR - Port Data Output Register */ 01378 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 01379 #define GPIO_PDOR_PDO_SHIFT (0U) 01380 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) 01381 01382 /*! @name PSOR - Port Set Output Register */ 01383 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 01384 #define GPIO_PSOR_PTSO_SHIFT (0U) 01385 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) 01386 01387 /*! @name PCOR - Port Clear Output Register */ 01388 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 01389 #define GPIO_PCOR_PTCO_SHIFT (0U) 01390 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) 01391 01392 /*! @name PTOR - Port Toggle Output Register */ 01393 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 01394 #define GPIO_PTOR_PTTO_SHIFT (0U) 01395 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) 01396 01397 /*! @name PDIR - Port Data Input Register */ 01398 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 01399 #define GPIO_PDIR_PDI_SHIFT (0U) 01400 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) 01401 01402 /*! @name PDDR - Port Data Direction Register */ 01403 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 01404 #define GPIO_PDDR_PDD_SHIFT (0U) 01405 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) 01406 01407 01408 /*! 01409 * @} 01410 */ /* end of group GPIO_Register_Masks */ 01411 01412 01413 /* GPIO - Peripheral instance base addresses */ 01414 /** Peripheral GPIOA base address */ 01415 #define GPIOA_BASE (0x400FF000u) 01416 /** Peripheral GPIOA base pointer */ 01417 #define GPIOA ((GPIO_Type *)GPIOA_BASE) 01418 /** Peripheral GPIOB base address */ 01419 #define GPIOB_BASE (0x400FF040u) 01420 /** Peripheral GPIOB base pointer */ 01421 #define GPIOB ((GPIO_Type *)GPIOB_BASE) 01422 /** Peripheral GPIOC base address */ 01423 #define GPIOC_BASE (0x400FF080u) 01424 /** Peripheral GPIOC base pointer */ 01425 #define GPIOC ((GPIO_Type *)GPIOC_BASE) 01426 /** Peripheral GPIOD base address */ 01427 #define GPIOD_BASE (0x400FF0C0u) 01428 /** Peripheral GPIOD base pointer */ 01429 #define GPIOD ((GPIO_Type *)GPIOD_BASE) 01430 /** Peripheral GPIOE base address */ 01431 #define GPIOE_BASE (0x400FF100u) 01432 /** Peripheral GPIOE base pointer */ 01433 #define GPIOE ((GPIO_Type *)GPIOE_BASE) 01434 /** Array initializer of GPIO peripheral base addresses */ 01435 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE } 01436 /** Array initializer of GPIO peripheral base pointers */ 01437 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE } 01438 01439 /*! 01440 * @} 01441 */ /* end of group GPIO_Peripheral_Access_Layer */ 01442 01443 01444 /* ---------------------------------------------------------------------------- 01445 -- I2C Peripheral Access Layer 01446 ---------------------------------------------------------------------------- */ 01447 01448 /*! 01449 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 01450 * @{ 01451 */ 01452 01453 /** I2C - Register Layout Typedef */ 01454 typedef struct { 01455 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ 01456 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ 01457 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ 01458 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ 01459 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ 01460 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ 01461 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ 01462 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ 01463 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ 01464 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ 01465 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ 01466 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ 01467 } I2C_Type; 01468 01469 /* ---------------------------------------------------------------------------- 01470 -- I2C Register Masks 01471 ---------------------------------------------------------------------------- */ 01472 01473 /*! 01474 * @addtogroup I2C_Register_Masks I2C Register Masks 01475 * @{ 01476 */ 01477 01478 /*! @name A1 - I2C Address Register 1 */ 01479 #define I2C_A1_AD_MASK (0xFEU) 01480 #define I2C_A1_AD_SHIFT (1U) 01481 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) 01482 01483 /*! @name F - I2C Frequency Divider register */ 01484 #define I2C_F_ICR_MASK (0x3FU) 01485 #define I2C_F_ICR_SHIFT (0U) 01486 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) 01487 #define I2C_F_MULT_MASK (0xC0U) 01488 #define I2C_F_MULT_SHIFT (6U) 01489 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) 01490 01491 /*! @name C1 - I2C Control Register 1 */ 01492 #define I2C_C1_DMAEN_MASK (0x1U) 01493 #define I2C_C1_DMAEN_SHIFT (0U) 01494 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) 01495 #define I2C_C1_WUEN_MASK (0x2U) 01496 #define I2C_C1_WUEN_SHIFT (1U) 01497 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) 01498 #define I2C_C1_RSTA_MASK (0x4U) 01499 #define I2C_C1_RSTA_SHIFT (2U) 01500 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) 01501 #define I2C_C1_TXAK_MASK (0x8U) 01502 #define I2C_C1_TXAK_SHIFT (3U) 01503 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) 01504 #define I2C_C1_TX_MASK (0x10U) 01505 #define I2C_C1_TX_SHIFT (4U) 01506 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) 01507 #define I2C_C1_MST_MASK (0x20U) 01508 #define I2C_C1_MST_SHIFT (5U) 01509 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) 01510 #define I2C_C1_IICIE_MASK (0x40U) 01511 #define I2C_C1_IICIE_SHIFT (6U) 01512 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) 01513 #define I2C_C1_IICEN_MASK (0x80U) 01514 #define I2C_C1_IICEN_SHIFT (7U) 01515 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) 01516 01517 /*! @name S - I2C Status register */ 01518 #define I2C_S_RXAK_MASK (0x1U) 01519 #define I2C_S_RXAK_SHIFT (0U) 01520 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) 01521 #define I2C_S_IICIF_MASK (0x2U) 01522 #define I2C_S_IICIF_SHIFT (1U) 01523 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) 01524 #define I2C_S_SRW_MASK (0x4U) 01525 #define I2C_S_SRW_SHIFT (2U) 01526 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) 01527 #define I2C_S_RAM_MASK (0x8U) 01528 #define I2C_S_RAM_SHIFT (3U) 01529 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) 01530 #define I2C_S_ARBL_MASK (0x10U) 01531 #define I2C_S_ARBL_SHIFT (4U) 01532 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) 01533 #define I2C_S_BUSY_MASK (0x20U) 01534 #define I2C_S_BUSY_SHIFT (5U) 01535 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) 01536 #define I2C_S_IAAS_MASK (0x40U) 01537 #define I2C_S_IAAS_SHIFT (6U) 01538 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) 01539 #define I2C_S_TCF_MASK (0x80U) 01540 #define I2C_S_TCF_SHIFT (7U) 01541 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) 01542 01543 /*! @name D - I2C Data I/O register */ 01544 #define I2C_D_DATA_MASK (0xFFU) 01545 #define I2C_D_DATA_SHIFT (0U) 01546 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) 01547 01548 /*! @name C2 - I2C Control Register 2 */ 01549 #define I2C_C2_AD_MASK (0x7U) 01550 #define I2C_C2_AD_SHIFT (0U) 01551 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) 01552 #define I2C_C2_RMEN_MASK (0x8U) 01553 #define I2C_C2_RMEN_SHIFT (3U) 01554 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) 01555 #define I2C_C2_SBRC_MASK (0x10U) 01556 #define I2C_C2_SBRC_SHIFT (4U) 01557 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) 01558 #define I2C_C2_HDRS_MASK (0x20U) 01559 #define I2C_C2_HDRS_SHIFT (5U) 01560 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) 01561 #define I2C_C2_ADEXT_MASK (0x40U) 01562 #define I2C_C2_ADEXT_SHIFT (6U) 01563 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) 01564 #define I2C_C2_GCAEN_MASK (0x80U) 01565 #define I2C_C2_GCAEN_SHIFT (7U) 01566 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) 01567 01568 /*! @name FLT - I2C Programmable Input Glitch Filter register */ 01569 #define I2C_FLT_FLT_MASK (0xFU) 01570 #define I2C_FLT_FLT_SHIFT (0U) 01571 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) 01572 #define I2C_FLT_STARTF_MASK (0x10U) 01573 #define I2C_FLT_STARTF_SHIFT (4U) 01574 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) 01575 #define I2C_FLT_SSIE_MASK (0x20U) 01576 #define I2C_FLT_SSIE_SHIFT (5U) 01577 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) 01578 #define I2C_FLT_STOPF_MASK (0x40U) 01579 #define I2C_FLT_STOPF_SHIFT (6U) 01580 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) 01581 #define I2C_FLT_SHEN_MASK (0x80U) 01582 #define I2C_FLT_SHEN_SHIFT (7U) 01583 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) 01584 01585 /*! @name RA - I2C Range Address register */ 01586 #define I2C_RA_RAD_MASK (0xFEU) 01587 #define I2C_RA_RAD_SHIFT (1U) 01588 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) 01589 01590 /*! @name SMB - I2C SMBus Control and Status register */ 01591 #define I2C_SMB_SHTF2IE_MASK (0x1U) 01592 #define I2C_SMB_SHTF2IE_SHIFT (0U) 01593 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) 01594 #define I2C_SMB_SHTF2_MASK (0x2U) 01595 #define I2C_SMB_SHTF2_SHIFT (1U) 01596 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) 01597 #define I2C_SMB_SHTF1_MASK (0x4U) 01598 #define I2C_SMB_SHTF1_SHIFT (2U) 01599 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) 01600 #define I2C_SMB_SLTF_MASK (0x8U) 01601 #define I2C_SMB_SLTF_SHIFT (3U) 01602 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) 01603 #define I2C_SMB_TCKSEL_MASK (0x10U) 01604 #define I2C_SMB_TCKSEL_SHIFT (4U) 01605 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) 01606 #define I2C_SMB_SIICAEN_MASK (0x20U) 01607 #define I2C_SMB_SIICAEN_SHIFT (5U) 01608 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) 01609 #define I2C_SMB_ALERTEN_MASK (0x40U) 01610 #define I2C_SMB_ALERTEN_SHIFT (6U) 01611 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) 01612 #define I2C_SMB_FACK_MASK (0x80U) 01613 #define I2C_SMB_FACK_SHIFT (7U) 01614 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) 01615 01616 /*! @name A2 - I2C Address Register 2 */ 01617 #define I2C_A2_SAD_MASK (0xFEU) 01618 #define I2C_A2_SAD_SHIFT (1U) 01619 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) 01620 01621 /*! @name SLTH - I2C SCL Low Timeout Register High */ 01622 #define I2C_SLTH_SSLT_MASK (0xFFU) 01623 #define I2C_SLTH_SSLT_SHIFT (0U) 01624 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) 01625 01626 /*! @name SLTL - I2C SCL Low Timeout Register Low */ 01627 #define I2C_SLTL_SSLT_MASK (0xFFU) 01628 #define I2C_SLTL_SSLT_SHIFT (0U) 01629 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) 01630 01631 01632 /*! 01633 * @} 01634 */ /* end of group I2C_Register_Masks */ 01635 01636 01637 /* I2C - Peripheral instance base addresses */ 01638 /** Peripheral I2C0 base address */ 01639 #define I2C0_BASE (0x40066000u) 01640 /** Peripheral I2C0 base pointer */ 01641 #define I2C0 ((I2C_Type *)I2C0_BASE) 01642 /** Peripheral I2C1 base address */ 01643 #define I2C1_BASE (0x40067000u) 01644 /** Peripheral I2C1 base pointer */ 01645 #define I2C1 ((I2C_Type *)I2C1_BASE) 01646 /** Array initializer of I2C peripheral base addresses */ 01647 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE } 01648 /** Array initializer of I2C peripheral base pointers */ 01649 #define I2C_BASE_PTRS { I2C0, I2C1 } 01650 /** Interrupt vectors for the I2C peripheral type */ 01651 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn } 01652 01653 /*! 01654 * @} 01655 */ /* end of group I2C_Peripheral_Access_Layer */ 01656 01657 01658 /* ---------------------------------------------------------------------------- 01659 -- I2S Peripheral Access Layer 01660 ---------------------------------------------------------------------------- */ 01661 01662 /*! 01663 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer 01664 * @{ 01665 */ 01666 01667 /** I2S - Register Layout Typedef */ 01668 typedef struct { 01669 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ 01670 uint8_t RESERVED_0[4]; 01671 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ 01672 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ 01673 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ 01674 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ 01675 uint8_t RESERVED_1[8]; 01676 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ 01677 uint8_t RESERVED_2[60]; 01678 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ 01679 uint8_t RESERVED_3[28]; 01680 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ 01681 uint8_t RESERVED_4[4]; 01682 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ 01683 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ 01684 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ 01685 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ 01686 uint8_t RESERVED_5[8]; 01687 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ 01688 uint8_t RESERVED_6[60]; 01689 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ 01690 uint8_t RESERVED_7[28]; 01691 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */ 01692 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */ 01693 } I2S_Type; 01694 01695 /* ---------------------------------------------------------------------------- 01696 -- I2S Register Masks 01697 ---------------------------------------------------------------------------- */ 01698 01699 /*! 01700 * @addtogroup I2S_Register_Masks I2S Register Masks 01701 * @{ 01702 */ 01703 01704 /*! @name TCSR - SAI Transmit Control Register */ 01705 #define I2S_TCSR_FWDE_MASK (0x2U) 01706 #define I2S_TCSR_FWDE_SHIFT (1U) 01707 #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) 01708 #define I2S_TCSR_FWIE_MASK (0x200U) 01709 #define I2S_TCSR_FWIE_SHIFT (9U) 01710 #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) 01711 #define I2S_TCSR_FEIE_MASK (0x400U) 01712 #define I2S_TCSR_FEIE_SHIFT (10U) 01713 #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) 01714 #define I2S_TCSR_SEIE_MASK (0x800U) 01715 #define I2S_TCSR_SEIE_SHIFT (11U) 01716 #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) 01717 #define I2S_TCSR_WSIE_MASK (0x1000U) 01718 #define I2S_TCSR_WSIE_SHIFT (12U) 01719 #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) 01720 #define I2S_TCSR_FWF_MASK (0x20000U) 01721 #define I2S_TCSR_FWF_SHIFT (17U) 01722 #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) 01723 #define I2S_TCSR_FEF_MASK (0x40000U) 01724 #define I2S_TCSR_FEF_SHIFT (18U) 01725 #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) 01726 #define I2S_TCSR_SEF_MASK (0x80000U) 01727 #define I2S_TCSR_SEF_SHIFT (19U) 01728 #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) 01729 #define I2S_TCSR_WSF_MASK (0x100000U) 01730 #define I2S_TCSR_WSF_SHIFT (20U) 01731 #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) 01732 #define I2S_TCSR_SR_MASK (0x1000000U) 01733 #define I2S_TCSR_SR_SHIFT (24U) 01734 #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) 01735 #define I2S_TCSR_FR_MASK (0x2000000U) 01736 #define I2S_TCSR_FR_SHIFT (25U) 01737 #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) 01738 #define I2S_TCSR_BCE_MASK (0x10000000U) 01739 #define I2S_TCSR_BCE_SHIFT (28U) 01740 #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) 01741 #define I2S_TCSR_DBGE_MASK (0x20000000U) 01742 #define I2S_TCSR_DBGE_SHIFT (29U) 01743 #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) 01744 #define I2S_TCSR_STOPE_MASK (0x40000000U) 01745 #define I2S_TCSR_STOPE_SHIFT (30U) 01746 #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) 01747 #define I2S_TCSR_TE_MASK (0x80000000U) 01748 #define I2S_TCSR_TE_SHIFT (31U) 01749 #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) 01750 01751 /*! @name TCR2 - SAI Transmit Configuration 2 Register */ 01752 #define I2S_TCR2_DIV_MASK (0xFFU) 01753 #define I2S_TCR2_DIV_SHIFT (0U) 01754 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) 01755 #define I2S_TCR2_BCD_MASK (0x1000000U) 01756 #define I2S_TCR2_BCD_SHIFT (24U) 01757 #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) 01758 #define I2S_TCR2_BCP_MASK (0x2000000U) 01759 #define I2S_TCR2_BCP_SHIFT (25U) 01760 #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) 01761 #define I2S_TCR2_MSEL_MASK (0xC000000U) 01762 #define I2S_TCR2_MSEL_SHIFT (26U) 01763 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) 01764 #define I2S_TCR2_BCI_MASK (0x10000000U) 01765 #define I2S_TCR2_BCI_SHIFT (28U) 01766 #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) 01767 #define I2S_TCR2_BCS_MASK (0x20000000U) 01768 #define I2S_TCR2_BCS_SHIFT (29U) 01769 #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) 01770 #define I2S_TCR2_SYNC_MASK (0xC0000000U) 01771 #define I2S_TCR2_SYNC_SHIFT (30U) 01772 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) 01773 01774 /*! @name TCR3 - SAI Transmit Configuration 3 Register */ 01775 #define I2S_TCR3_WDFL_MASK (0x1U) 01776 #define I2S_TCR3_WDFL_SHIFT (0U) 01777 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) 01778 #define I2S_TCR3_TCE_MASK (0x10000U) 01779 #define I2S_TCR3_TCE_SHIFT (16U) 01780 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) 01781 01782 /*! @name TCR4 - SAI Transmit Configuration 4 Register */ 01783 #define I2S_TCR4_FSD_MASK (0x1U) 01784 #define I2S_TCR4_FSD_SHIFT (0U) 01785 #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) 01786 #define I2S_TCR4_FSP_MASK (0x2U) 01787 #define I2S_TCR4_FSP_SHIFT (1U) 01788 #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) 01789 #define I2S_TCR4_FSE_MASK (0x8U) 01790 #define I2S_TCR4_FSE_SHIFT (3U) 01791 #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) 01792 #define I2S_TCR4_MF_MASK (0x10U) 01793 #define I2S_TCR4_MF_SHIFT (4U) 01794 #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) 01795 #define I2S_TCR4_SYWD_MASK (0x1F00U) 01796 #define I2S_TCR4_SYWD_SHIFT (8U) 01797 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) 01798 #define I2S_TCR4_FRSZ_MASK (0x10000U) 01799 #define I2S_TCR4_FRSZ_SHIFT (16U) 01800 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) 01801 01802 /*! @name TCR5 - SAI Transmit Configuration 5 Register */ 01803 #define I2S_TCR5_FBT_MASK (0x1F00U) 01804 #define I2S_TCR5_FBT_SHIFT (8U) 01805 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) 01806 #define I2S_TCR5_W0W_MASK (0x1F0000U) 01807 #define I2S_TCR5_W0W_SHIFT (16U) 01808 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) 01809 #define I2S_TCR5_WNW_MASK (0x1F000000U) 01810 #define I2S_TCR5_WNW_SHIFT (24U) 01811 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) 01812 01813 /*! @name TDR - SAI Transmit Data Register */ 01814 #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) 01815 #define I2S_TDR_TDR_SHIFT (0U) 01816 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) 01817 01818 /* The count of I2S_TDR */ 01819 #define I2S_TDR_COUNT (1U) 01820 01821 /*! @name TMR - SAI Transmit Mask Register */ 01822 #define I2S_TMR_TWM_MASK (0x3U) 01823 #define I2S_TMR_TWM_SHIFT (0U) 01824 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) 01825 01826 /*! @name RCSR - SAI Receive Control Register */ 01827 #define I2S_RCSR_FWDE_MASK (0x2U) 01828 #define I2S_RCSR_FWDE_SHIFT (1U) 01829 #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) 01830 #define I2S_RCSR_FWIE_MASK (0x200U) 01831 #define I2S_RCSR_FWIE_SHIFT (9U) 01832 #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) 01833 #define I2S_RCSR_FEIE_MASK (0x400U) 01834 #define I2S_RCSR_FEIE_SHIFT (10U) 01835 #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) 01836 #define I2S_RCSR_SEIE_MASK (0x800U) 01837 #define I2S_RCSR_SEIE_SHIFT (11U) 01838 #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) 01839 #define I2S_RCSR_WSIE_MASK (0x1000U) 01840 #define I2S_RCSR_WSIE_SHIFT (12U) 01841 #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) 01842 #define I2S_RCSR_FWF_MASK (0x20000U) 01843 #define I2S_RCSR_FWF_SHIFT (17U) 01844 #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) 01845 #define I2S_RCSR_FEF_MASK (0x40000U) 01846 #define I2S_RCSR_FEF_SHIFT (18U) 01847 #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) 01848 #define I2S_RCSR_SEF_MASK (0x80000U) 01849 #define I2S_RCSR_SEF_SHIFT (19U) 01850 #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) 01851 #define I2S_RCSR_WSF_MASK (0x100000U) 01852 #define I2S_RCSR_WSF_SHIFT (20U) 01853 #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) 01854 #define I2S_RCSR_SR_MASK (0x1000000U) 01855 #define I2S_RCSR_SR_SHIFT (24U) 01856 #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) 01857 #define I2S_RCSR_FR_MASK (0x2000000U) 01858 #define I2S_RCSR_FR_SHIFT (25U) 01859 #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) 01860 #define I2S_RCSR_BCE_MASK (0x10000000U) 01861 #define I2S_RCSR_BCE_SHIFT (28U) 01862 #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) 01863 #define I2S_RCSR_DBGE_MASK (0x20000000U) 01864 #define I2S_RCSR_DBGE_SHIFT (29U) 01865 #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) 01866 #define I2S_RCSR_STOPE_MASK (0x40000000U) 01867 #define I2S_RCSR_STOPE_SHIFT (30U) 01868 #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) 01869 #define I2S_RCSR_RE_MASK (0x80000000U) 01870 #define I2S_RCSR_RE_SHIFT (31U) 01871 #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) 01872 01873 /*! @name RCR2 - SAI Receive Configuration 2 Register */ 01874 #define I2S_RCR2_DIV_MASK (0xFFU) 01875 #define I2S_RCR2_DIV_SHIFT (0U) 01876 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) 01877 #define I2S_RCR2_BCD_MASK (0x1000000U) 01878 #define I2S_RCR2_BCD_SHIFT (24U) 01879 #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) 01880 #define I2S_RCR2_BCP_MASK (0x2000000U) 01881 #define I2S_RCR2_BCP_SHIFT (25U) 01882 #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) 01883 #define I2S_RCR2_MSEL_MASK (0xC000000U) 01884 #define I2S_RCR2_MSEL_SHIFT (26U) 01885 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) 01886 #define I2S_RCR2_BCI_MASK (0x10000000U) 01887 #define I2S_RCR2_BCI_SHIFT (28U) 01888 #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) 01889 #define I2S_RCR2_BCS_MASK (0x20000000U) 01890 #define I2S_RCR2_BCS_SHIFT (29U) 01891 #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) 01892 #define I2S_RCR2_SYNC_MASK (0xC0000000U) 01893 #define I2S_RCR2_SYNC_SHIFT (30U) 01894 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) 01895 01896 /*! @name RCR3 - SAI Receive Configuration 3 Register */ 01897 #define I2S_RCR3_WDFL_MASK (0x1U) 01898 #define I2S_RCR3_WDFL_SHIFT (0U) 01899 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) 01900 #define I2S_RCR3_RCE_MASK (0x10000U) 01901 #define I2S_RCR3_RCE_SHIFT (16U) 01902 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) 01903 01904 /*! @name RCR4 - SAI Receive Configuration 4 Register */ 01905 #define I2S_RCR4_FSD_MASK (0x1U) 01906 #define I2S_RCR4_FSD_SHIFT (0U) 01907 #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) 01908 #define I2S_RCR4_FSP_MASK (0x2U) 01909 #define I2S_RCR4_FSP_SHIFT (1U) 01910 #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) 01911 #define I2S_RCR4_FSE_MASK (0x8U) 01912 #define I2S_RCR4_FSE_SHIFT (3U) 01913 #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) 01914 #define I2S_RCR4_MF_MASK (0x10U) 01915 #define I2S_RCR4_MF_SHIFT (4U) 01916 #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) 01917 #define I2S_RCR4_SYWD_MASK (0x1F00U) 01918 #define I2S_RCR4_SYWD_SHIFT (8U) 01919 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) 01920 #define I2S_RCR4_FRSZ_MASK (0x10000U) 01921 #define I2S_RCR4_FRSZ_SHIFT (16U) 01922 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) 01923 01924 /*! @name RCR5 - SAI Receive Configuration 5 Register */ 01925 #define I2S_RCR5_FBT_MASK (0x1F00U) 01926 #define I2S_RCR5_FBT_SHIFT (8U) 01927 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) 01928 #define I2S_RCR5_W0W_MASK (0x1F0000U) 01929 #define I2S_RCR5_W0W_SHIFT (16U) 01930 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) 01931 #define I2S_RCR5_WNW_MASK (0x1F000000U) 01932 #define I2S_RCR5_WNW_SHIFT (24U) 01933 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) 01934 01935 /*! @name RDR - SAI Receive Data Register */ 01936 #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) 01937 #define I2S_RDR_RDR_SHIFT (0U) 01938 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) 01939 01940 /* The count of I2S_RDR */ 01941 #define I2S_RDR_COUNT (1U) 01942 01943 /*! @name RMR - SAI Receive Mask Register */ 01944 #define I2S_RMR_RWM_MASK (0x3U) 01945 #define I2S_RMR_RWM_SHIFT (0U) 01946 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) 01947 01948 /*! @name MCR - SAI MCLK Control Register */ 01949 #define I2S_MCR_MICS_MASK (0x3000000U) 01950 #define I2S_MCR_MICS_SHIFT (24U) 01951 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK) 01952 #define I2S_MCR_MOE_MASK (0x40000000U) 01953 #define I2S_MCR_MOE_SHIFT (30U) 01954 #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) 01955 #define I2S_MCR_DUF_MASK (0x80000000U) 01956 #define I2S_MCR_DUF_SHIFT (31U) 01957 #define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK) 01958 01959 /*! @name MDR - SAI MCLK Divide Register */ 01960 #define I2S_MDR_DIVIDE_MASK (0xFFFU) 01961 #define I2S_MDR_DIVIDE_SHIFT (0U) 01962 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK) 01963 #define I2S_MDR_FRACT_MASK (0xFF000U) 01964 #define I2S_MDR_FRACT_SHIFT (12U) 01965 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK) 01966 01967 01968 /*! 01969 * @} 01970 */ /* end of group I2S_Register_Masks */ 01971 01972 01973 /* I2S - Peripheral instance base addresses */ 01974 /** Peripheral I2S0 base address */ 01975 #define I2S0_BASE (0x4002F000u) 01976 /** Peripheral I2S0 base pointer */ 01977 #define I2S0 ((I2S_Type *)I2S0_BASE) 01978 /** Array initializer of I2S peripheral base addresses */ 01979 #define I2S_BASE_ADDRS { I2S0_BASE } 01980 /** Array initializer of I2S peripheral base pointers */ 01981 #define I2S_BASE_PTRS { I2S0 } 01982 /** Interrupt vectors for the I2S peripheral type */ 01983 #define I2S_RX_IRQS { I2S0_IRQn } 01984 #define I2S_TX_IRQS { I2S0_IRQn } 01985 01986 /*! 01987 * @} 01988 */ /* end of group I2S_Peripheral_Access_Layer */ 01989 01990 01991 /* ---------------------------------------------------------------------------- 01992 -- LLWU Peripheral Access Layer 01993 ---------------------------------------------------------------------------- */ 01994 01995 /*! 01996 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer 01997 * @{ 01998 */ 01999 02000 /** LLWU - Register Layout Typedef */ 02001 typedef struct { 02002 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ 02003 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ 02004 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ 02005 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ 02006 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ 02007 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ 02008 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ 02009 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ 02010 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ 02011 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ 02012 } LLWU_Type; 02013 02014 /* ---------------------------------------------------------------------------- 02015 -- LLWU Register Masks 02016 ---------------------------------------------------------------------------- */ 02017 02018 /*! 02019 * @addtogroup LLWU_Register_Masks LLWU Register Masks 02020 * @{ 02021 */ 02022 02023 /*! @name PE1 - LLWU Pin Enable 1 register */ 02024 #define LLWU_PE1_WUPE0_MASK (0x3U) 02025 #define LLWU_PE1_WUPE0_SHIFT (0U) 02026 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) 02027 #define LLWU_PE1_WUPE1_MASK (0xCU) 02028 #define LLWU_PE1_WUPE1_SHIFT (2U) 02029 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) 02030 #define LLWU_PE1_WUPE2_MASK (0x30U) 02031 #define LLWU_PE1_WUPE2_SHIFT (4U) 02032 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) 02033 #define LLWU_PE1_WUPE3_MASK (0xC0U) 02034 #define LLWU_PE1_WUPE3_SHIFT (6U) 02035 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) 02036 02037 /*! @name PE2 - LLWU Pin Enable 2 register */ 02038 #define LLWU_PE2_WUPE4_MASK (0x3U) 02039 #define LLWU_PE2_WUPE4_SHIFT (0U) 02040 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) 02041 #define LLWU_PE2_WUPE5_MASK (0xCU) 02042 #define LLWU_PE2_WUPE5_SHIFT (2U) 02043 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) 02044 #define LLWU_PE2_WUPE6_MASK (0x30U) 02045 #define LLWU_PE2_WUPE6_SHIFT (4U) 02046 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) 02047 #define LLWU_PE2_WUPE7_MASK (0xC0U) 02048 #define LLWU_PE2_WUPE7_SHIFT (6U) 02049 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) 02050 02051 /*! @name PE3 - LLWU Pin Enable 3 register */ 02052 #define LLWU_PE3_WUPE8_MASK (0x3U) 02053 #define LLWU_PE3_WUPE8_SHIFT (0U) 02054 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) 02055 #define LLWU_PE3_WUPE9_MASK (0xCU) 02056 #define LLWU_PE3_WUPE9_SHIFT (2U) 02057 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) 02058 #define LLWU_PE3_WUPE10_MASK (0x30U) 02059 #define LLWU_PE3_WUPE10_SHIFT (4U) 02060 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) 02061 #define LLWU_PE3_WUPE11_MASK (0xC0U) 02062 #define LLWU_PE3_WUPE11_SHIFT (6U) 02063 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) 02064 02065 /*! @name PE4 - LLWU Pin Enable 4 register */ 02066 #define LLWU_PE4_WUPE12_MASK (0x3U) 02067 #define LLWU_PE4_WUPE12_SHIFT (0U) 02068 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) 02069 #define LLWU_PE4_WUPE13_MASK (0xCU) 02070 #define LLWU_PE4_WUPE13_SHIFT (2U) 02071 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) 02072 #define LLWU_PE4_WUPE14_MASK (0x30U) 02073 #define LLWU_PE4_WUPE14_SHIFT (4U) 02074 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) 02075 #define LLWU_PE4_WUPE15_MASK (0xC0U) 02076 #define LLWU_PE4_WUPE15_SHIFT (6U) 02077 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) 02078 02079 /*! @name ME - LLWU Module Enable register */ 02080 #define LLWU_ME_WUME0_MASK (0x1U) 02081 #define LLWU_ME_WUME0_SHIFT (0U) 02082 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) 02083 #define LLWU_ME_WUME1_MASK (0x2U) 02084 #define LLWU_ME_WUME1_SHIFT (1U) 02085 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) 02086 #define LLWU_ME_WUME2_MASK (0x4U) 02087 #define LLWU_ME_WUME2_SHIFT (2U) 02088 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) 02089 #define LLWU_ME_WUME3_MASK (0x8U) 02090 #define LLWU_ME_WUME3_SHIFT (3U) 02091 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) 02092 #define LLWU_ME_WUME4_MASK (0x10U) 02093 #define LLWU_ME_WUME4_SHIFT (4U) 02094 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) 02095 #define LLWU_ME_WUME5_MASK (0x20U) 02096 #define LLWU_ME_WUME5_SHIFT (5U) 02097 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) 02098 #define LLWU_ME_WUME6_MASK (0x40U) 02099 #define LLWU_ME_WUME6_SHIFT (6U) 02100 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) 02101 #define LLWU_ME_WUME7_MASK (0x80U) 02102 #define LLWU_ME_WUME7_SHIFT (7U) 02103 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) 02104 02105 /*! @name F1 - LLWU Flag 1 register */ 02106 #define LLWU_F1_WUF0_MASK (0x1U) 02107 #define LLWU_F1_WUF0_SHIFT (0U) 02108 #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK) 02109 #define LLWU_F1_WUF1_MASK (0x2U) 02110 #define LLWU_F1_WUF1_SHIFT (1U) 02111 #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK) 02112 #define LLWU_F1_WUF2_MASK (0x4U) 02113 #define LLWU_F1_WUF2_SHIFT (2U) 02114 #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK) 02115 #define LLWU_F1_WUF3_MASK (0x8U) 02116 #define LLWU_F1_WUF3_SHIFT (3U) 02117 #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK) 02118 #define LLWU_F1_WUF4_MASK (0x10U) 02119 #define LLWU_F1_WUF4_SHIFT (4U) 02120 #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK) 02121 #define LLWU_F1_WUF5_MASK (0x20U) 02122 #define LLWU_F1_WUF5_SHIFT (5U) 02123 #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK) 02124 #define LLWU_F1_WUF6_MASK (0x40U) 02125 #define LLWU_F1_WUF6_SHIFT (6U) 02126 #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK) 02127 #define LLWU_F1_WUF7_MASK (0x80U) 02128 #define LLWU_F1_WUF7_SHIFT (7U) 02129 #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK) 02130 02131 /*! @name F2 - LLWU Flag 2 register */ 02132 #define LLWU_F2_WUF8_MASK (0x1U) 02133 #define LLWU_F2_WUF8_SHIFT (0U) 02134 #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK) 02135 #define LLWU_F2_WUF9_MASK (0x2U) 02136 #define LLWU_F2_WUF9_SHIFT (1U) 02137 #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK) 02138 #define LLWU_F2_WUF10_MASK (0x4U) 02139 #define LLWU_F2_WUF10_SHIFT (2U) 02140 #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK) 02141 #define LLWU_F2_WUF11_MASK (0x8U) 02142 #define LLWU_F2_WUF11_SHIFT (3U) 02143 #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK) 02144 #define LLWU_F2_WUF12_MASK (0x10U) 02145 #define LLWU_F2_WUF12_SHIFT (4U) 02146 #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK) 02147 #define LLWU_F2_WUF13_MASK (0x20U) 02148 #define LLWU_F2_WUF13_SHIFT (5U) 02149 #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK) 02150 #define LLWU_F2_WUF14_MASK (0x40U) 02151 #define LLWU_F2_WUF14_SHIFT (6U) 02152 #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK) 02153 #define LLWU_F2_WUF15_MASK (0x80U) 02154 #define LLWU_F2_WUF15_SHIFT (7U) 02155 #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK) 02156 02157 /*! @name F3 - LLWU Flag 3 register */ 02158 #define LLWU_F3_MWUF0_MASK (0x1U) 02159 #define LLWU_F3_MWUF0_SHIFT (0U) 02160 #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK) 02161 #define LLWU_F3_MWUF1_MASK (0x2U) 02162 #define LLWU_F3_MWUF1_SHIFT (1U) 02163 #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK) 02164 #define LLWU_F3_MWUF2_MASK (0x4U) 02165 #define LLWU_F3_MWUF2_SHIFT (2U) 02166 #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK) 02167 #define LLWU_F3_MWUF3_MASK (0x8U) 02168 #define LLWU_F3_MWUF3_SHIFT (3U) 02169 #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK) 02170 #define LLWU_F3_MWUF4_MASK (0x10U) 02171 #define LLWU_F3_MWUF4_SHIFT (4U) 02172 #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK) 02173 #define LLWU_F3_MWUF5_MASK (0x20U) 02174 #define LLWU_F3_MWUF5_SHIFT (5U) 02175 #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK) 02176 #define LLWU_F3_MWUF6_MASK (0x40U) 02177 #define LLWU_F3_MWUF6_SHIFT (6U) 02178 #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK) 02179 #define LLWU_F3_MWUF7_MASK (0x80U) 02180 #define LLWU_F3_MWUF7_SHIFT (7U) 02181 #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK) 02182 02183 /*! @name FILT1 - LLWU Pin Filter 1 register */ 02184 #define LLWU_FILT1_FILTSEL_MASK (0xFU) 02185 #define LLWU_FILT1_FILTSEL_SHIFT (0U) 02186 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) 02187 #define LLWU_FILT1_FILTE_MASK (0x60U) 02188 #define LLWU_FILT1_FILTE_SHIFT (5U) 02189 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) 02190 #define LLWU_FILT1_FILTF_MASK (0x80U) 02191 #define LLWU_FILT1_FILTF_SHIFT (7U) 02192 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) 02193 02194 /*! @name FILT2 - LLWU Pin Filter 2 register */ 02195 #define LLWU_FILT2_FILTSEL_MASK (0xFU) 02196 #define LLWU_FILT2_FILTSEL_SHIFT (0U) 02197 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) 02198 #define LLWU_FILT2_FILTE_MASK (0x60U) 02199 #define LLWU_FILT2_FILTE_SHIFT (5U) 02200 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) 02201 #define LLWU_FILT2_FILTF_MASK (0x80U) 02202 #define LLWU_FILT2_FILTF_SHIFT (7U) 02203 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) 02204 02205 02206 /*! 02207 * @} 02208 */ /* end of group LLWU_Register_Masks */ 02209 02210 02211 /* LLWU - Peripheral instance base addresses */ 02212 /** Peripheral LLWU base address */ 02213 #define LLWU_BASE (0x4007C000u) 02214 /** Peripheral LLWU base pointer */ 02215 #define LLWU ((LLWU_Type *)LLWU_BASE) 02216 /** Array initializer of LLWU peripheral base addresses */ 02217 #define LLWU_BASE_ADDRS { LLWU_BASE } 02218 /** Array initializer of LLWU peripheral base pointers */ 02219 #define LLWU_BASE_PTRS { LLWU } 02220 /** Interrupt vectors for the LLWU peripheral type */ 02221 #define LLWU_IRQS { LLWU_IRQn } 02222 02223 /*! 02224 * @} 02225 */ /* end of group LLWU_Peripheral_Access_Layer */ 02226 02227 02228 /* ---------------------------------------------------------------------------- 02229 -- LPTMR Peripheral Access Layer 02230 ---------------------------------------------------------------------------- */ 02231 02232 /*! 02233 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer 02234 * @{ 02235 */ 02236 02237 /** LPTMR - Register Layout Typedef */ 02238 typedef struct { 02239 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ 02240 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ 02241 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ 02242 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ 02243 } LPTMR_Type; 02244 02245 /* ---------------------------------------------------------------------------- 02246 -- LPTMR Register Masks 02247 ---------------------------------------------------------------------------- */ 02248 02249 /*! 02250 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks 02251 * @{ 02252 */ 02253 02254 /*! @name CSR - Low Power Timer Control Status Register */ 02255 #define LPTMR_CSR_TEN_MASK (0x1U) 02256 #define LPTMR_CSR_TEN_SHIFT (0U) 02257 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) 02258 #define LPTMR_CSR_TMS_MASK (0x2U) 02259 #define LPTMR_CSR_TMS_SHIFT (1U) 02260 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) 02261 #define LPTMR_CSR_TFC_MASK (0x4U) 02262 #define LPTMR_CSR_TFC_SHIFT (2U) 02263 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) 02264 #define LPTMR_CSR_TPP_MASK (0x8U) 02265 #define LPTMR_CSR_TPP_SHIFT (3U) 02266 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) 02267 #define LPTMR_CSR_TPS_MASK (0x30U) 02268 #define LPTMR_CSR_TPS_SHIFT (4U) 02269 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) 02270 #define LPTMR_CSR_TIE_MASK (0x40U) 02271 #define LPTMR_CSR_TIE_SHIFT (6U) 02272 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) 02273 #define LPTMR_CSR_TCF_MASK (0x80U) 02274 #define LPTMR_CSR_TCF_SHIFT (7U) 02275 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) 02276 02277 /*! @name PSR - Low Power Timer Prescale Register */ 02278 #define LPTMR_PSR_PCS_MASK (0x3U) 02279 #define LPTMR_PSR_PCS_SHIFT (0U) 02280 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) 02281 #define LPTMR_PSR_PBYP_MASK (0x4U) 02282 #define LPTMR_PSR_PBYP_SHIFT (2U) 02283 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) 02284 #define LPTMR_PSR_PRESCALE_MASK (0x78U) 02285 #define LPTMR_PSR_PRESCALE_SHIFT (3U) 02286 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) 02287 02288 /*! @name CMR - Low Power Timer Compare Register */ 02289 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU) 02290 #define LPTMR_CMR_COMPARE_SHIFT (0U) 02291 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) 02292 02293 /*! @name CNR - Low Power Timer Counter Register */ 02294 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU) 02295 #define LPTMR_CNR_COUNTER_SHIFT (0U) 02296 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) 02297 02298 02299 /*! 02300 * @} 02301 */ /* end of group LPTMR_Register_Masks */ 02302 02303 02304 /* LPTMR - Peripheral instance base addresses */ 02305 /** Peripheral LPTMR0 base address */ 02306 #define LPTMR0_BASE (0x40040000u) 02307 /** Peripheral LPTMR0 base pointer */ 02308 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 02309 /** Array initializer of LPTMR peripheral base addresses */ 02310 #define LPTMR_BASE_ADDRS { LPTMR0_BASE } 02311 /** Array initializer of LPTMR peripheral base pointers */ 02312 #define LPTMR_BASE_PTRS { LPTMR0 } 02313 /** Interrupt vectors for the LPTMR peripheral type */ 02314 #define LPTMR_IRQS { LPTMR0_IRQn } 02315 02316 /*! 02317 * @} 02318 */ /* end of group LPTMR_Peripheral_Access_Layer */ 02319 02320 02321 /* ---------------------------------------------------------------------------- 02322 -- MCG Peripheral Access Layer 02323 ---------------------------------------------------------------------------- */ 02324 02325 /*! 02326 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer 02327 * @{ 02328 */ 02329 02330 /** MCG - Register Layout Typedef */ 02331 typedef struct { 02332 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ 02333 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ 02334 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ 02335 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ 02336 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ 02337 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ 02338 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */ 02339 uint8_t RESERVED_0[1]; 02340 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ 02341 uint8_t RESERVED_1[1]; 02342 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ 02343 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ 02344 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ 02345 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ 02346 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */ 02347 __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */ 02348 } MCG_Type; 02349 02350 /* ---------------------------------------------------------------------------- 02351 -- MCG Register Masks 02352 ---------------------------------------------------------------------------- */ 02353 02354 /*! 02355 * @addtogroup MCG_Register_Masks MCG Register Masks 02356 * @{ 02357 */ 02358 02359 /*! @name C1 - MCG Control 1 Register */ 02360 #define MCG_C1_IREFSTEN_MASK (0x1U) 02361 #define MCG_C1_IREFSTEN_SHIFT (0U) 02362 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) 02363 #define MCG_C1_IRCLKEN_MASK (0x2U) 02364 #define MCG_C1_IRCLKEN_SHIFT (1U) 02365 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) 02366 #define MCG_C1_IREFS_MASK (0x4U) 02367 #define MCG_C1_IREFS_SHIFT (2U) 02368 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK) 02369 #define MCG_C1_FRDIV_MASK (0x38U) 02370 #define MCG_C1_FRDIV_SHIFT (3U) 02371 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK) 02372 #define MCG_C1_CLKS_MASK (0xC0U) 02373 #define MCG_C1_CLKS_SHIFT (6U) 02374 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) 02375 02376 /*! @name C2 - MCG Control 2 Register */ 02377 #define MCG_C2_IRCS_MASK (0x1U) 02378 #define MCG_C2_IRCS_SHIFT (0U) 02379 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) 02380 #define MCG_C2_LP_MASK (0x2U) 02381 #define MCG_C2_LP_SHIFT (1U) 02382 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK) 02383 #define MCG_C2_EREFS0_MASK (0x4U) 02384 #define MCG_C2_EREFS0_SHIFT (2U) 02385 #define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK) 02386 #define MCG_C2_HGO0_MASK (0x8U) 02387 #define MCG_C2_HGO0_SHIFT (3U) 02388 #define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK) 02389 #define MCG_C2_RANGE0_MASK (0x30U) 02390 #define MCG_C2_RANGE0_SHIFT (4U) 02391 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK) 02392 #define MCG_C2_FCFTRIM_MASK (0x40U) 02393 #define MCG_C2_FCFTRIM_SHIFT (6U) 02394 #define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK) 02395 #define MCG_C2_LOCRE0_MASK (0x80U) 02396 #define MCG_C2_LOCRE0_SHIFT (7U) 02397 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK) 02398 02399 /*! @name C3 - MCG Control 3 Register */ 02400 #define MCG_C3_SCTRIM_MASK (0xFFU) 02401 #define MCG_C3_SCTRIM_SHIFT (0U) 02402 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK) 02403 02404 /*! @name C4 - MCG Control 4 Register */ 02405 #define MCG_C4_SCFTRIM_MASK (0x1U) 02406 #define MCG_C4_SCFTRIM_SHIFT (0U) 02407 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK) 02408 #define MCG_C4_FCTRIM_MASK (0x1EU) 02409 #define MCG_C4_FCTRIM_SHIFT (1U) 02410 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK) 02411 #define MCG_C4_DRST_DRS_MASK (0x60U) 02412 #define MCG_C4_DRST_DRS_SHIFT (5U) 02413 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK) 02414 #define MCG_C4_DMX32_MASK (0x80U) 02415 #define MCG_C4_DMX32_SHIFT (7U) 02416 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK) 02417 02418 /*! @name C5 - MCG Control 5 Register */ 02419 #define MCG_C5_PRDIV0_MASK (0x1FU) 02420 #define MCG_C5_PRDIV0_SHIFT (0U) 02421 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK) 02422 #define MCG_C5_PLLSTEN0_MASK (0x20U) 02423 #define MCG_C5_PLLSTEN0_SHIFT (5U) 02424 #define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK) 02425 #define MCG_C5_PLLCLKEN0_MASK (0x40U) 02426 #define MCG_C5_PLLCLKEN0_SHIFT (6U) 02427 #define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK) 02428 02429 /*! @name C6 - MCG Control 6 Register */ 02430 #define MCG_C6_VDIV0_MASK (0x1FU) 02431 #define MCG_C6_VDIV0_SHIFT (0U) 02432 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK) 02433 #define MCG_C6_CME0_MASK (0x20U) 02434 #define MCG_C6_CME0_SHIFT (5U) 02435 #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK) 02436 #define MCG_C6_PLLS_MASK (0x40U) 02437 #define MCG_C6_PLLS_SHIFT (6U) 02438 #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK) 02439 #define MCG_C6_LOLIE0_MASK (0x80U) 02440 #define MCG_C6_LOLIE0_SHIFT (7U) 02441 #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK) 02442 02443 /*! @name S - MCG Status Register */ 02444 #define MCG_S_IRCST_MASK (0x1U) 02445 #define MCG_S_IRCST_SHIFT (0U) 02446 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK) 02447 #define MCG_S_OSCINIT0_MASK (0x2U) 02448 #define MCG_S_OSCINIT0_SHIFT (1U) 02449 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) 02450 #define MCG_S_CLKST_MASK (0xCU) 02451 #define MCG_S_CLKST_SHIFT (2U) 02452 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) 02453 #define MCG_S_IREFST_MASK (0x10U) 02454 #define MCG_S_IREFST_SHIFT (4U) 02455 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK) 02456 #define MCG_S_PLLST_MASK (0x20U) 02457 #define MCG_S_PLLST_SHIFT (5U) 02458 #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK) 02459 #define MCG_S_LOCK0_MASK (0x40U) 02460 #define MCG_S_LOCK0_SHIFT (6U) 02461 #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK) 02462 #define MCG_S_LOLS0_MASK (0x80U) 02463 #define MCG_S_LOLS0_SHIFT (7U) 02464 #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK) 02465 02466 /*! @name SC - MCG Status and Control Register */ 02467 #define MCG_SC_LOCS0_MASK (0x1U) 02468 #define MCG_SC_LOCS0_SHIFT (0U) 02469 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK) 02470 #define MCG_SC_FCRDIV_MASK (0xEU) 02471 #define MCG_SC_FCRDIV_SHIFT (1U) 02472 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) 02473 #define MCG_SC_FLTPRSRV_MASK (0x10U) 02474 #define MCG_SC_FLTPRSRV_SHIFT (4U) 02475 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK) 02476 #define MCG_SC_ATMF_MASK (0x20U) 02477 #define MCG_SC_ATMF_SHIFT (5U) 02478 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK) 02479 #define MCG_SC_ATMS_MASK (0x40U) 02480 #define MCG_SC_ATMS_SHIFT (6U) 02481 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK) 02482 #define MCG_SC_ATME_MASK (0x80U) 02483 #define MCG_SC_ATME_SHIFT (7U) 02484 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK) 02485 02486 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */ 02487 #define MCG_ATCVH_ATCVH_MASK (0xFFU) 02488 #define MCG_ATCVH_ATCVH_SHIFT (0U) 02489 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK) 02490 02491 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */ 02492 #define MCG_ATCVL_ATCVL_MASK (0xFFU) 02493 #define MCG_ATCVL_ATCVL_SHIFT (0U) 02494 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK) 02495 02496 /*! @name C7 - MCG Control 7 Register */ 02497 #define MCG_C7_OSCSEL_MASK (0x1U) 02498 #define MCG_C7_OSCSEL_SHIFT (0U) 02499 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK) 02500 02501 /*! @name C8 - MCG Control 8 Register */ 02502 #define MCG_C8_LOLRE_MASK (0x40U) 02503 #define MCG_C8_LOLRE_SHIFT (6U) 02504 #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK) 02505 02506 02507 /*! 02508 * @} 02509 */ /* end of group MCG_Register_Masks */ 02510 02511 02512 /* MCG - Peripheral instance base addresses */ 02513 /** Peripheral MCG base address */ 02514 #define MCG_BASE (0x40064000u) 02515 /** Peripheral MCG base pointer */ 02516 #define MCG ((MCG_Type *)MCG_BASE) 02517 /** Array initializer of MCG peripheral base addresses */ 02518 #define MCG_BASE_ADDRS { MCG_BASE } 02519 /** Array initializer of MCG peripheral base pointers */ 02520 #define MCG_BASE_PTRS { MCG } 02521 /** Interrupt vectors for the MCG peripheral type */ 02522 #define MCG_IRQS { MCG_IRQn } 02523 /* MCG C2[EREFS] backward compatibility */ 02524 #define MCG_C2_EREFS_MASK (MCG_C2_EREFS0_MASK) 02525 #define MCG_C2_EREFS_SHIFT (MCG_C2_EREFS0_SHIFT) 02526 #define MCG_C2_EREFS_WIDTH (MCG_C2_EREFS0_WIDTH) 02527 #define MCG_C2_EREFS(x) (MCG_C2_EREFS0(x)) 02528 02529 /* MCG C2[HGO] backward compatibility */ 02530 #define MCG_C2_HGO_MASK (MCG_C2_HGO0_MASK) 02531 #define MCG_C2_HGO_SHIFT (MCG_C2_HGO0_SHIFT) 02532 #define MCG_C2_HGO_WIDTH (MCG_C2_HGO0_WIDTH) 02533 #define MCG_C2_HGO(x) (MCG_C2_HGO0(x)) 02534 02535 /* MCG C2[RANGE] backward compatibility */ 02536 #define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK) 02537 #define MCG_C2_RANGE_SHIFT (MCG_C2_RANGE0_SHIFT) 02538 #define MCG_C2_RANGE_WIDTH (MCG_C2_RANGE0_WIDTH) 02539 #define MCG_C2_RANGE(x) (MCG_C2_RANGE0(x)) 02540 02541 02542 /*! 02543 * @} 02544 */ /* end of group MCG_Peripheral_Access_Layer */ 02545 02546 02547 /* ---------------------------------------------------------------------------- 02548 -- MCM Peripheral Access Layer 02549 ---------------------------------------------------------------------------- */ 02550 02551 /*! 02552 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer 02553 * @{ 02554 */ 02555 02556 /** MCM - Register Layout Typedef */ 02557 typedef struct { 02558 uint8_t RESERVED_0[8]; 02559 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 02560 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ 02561 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ 02562 uint8_t RESERVED_1[48]; 02563 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ 02564 } MCM_Type; 02565 02566 /* ---------------------------------------------------------------------------- 02567 -- MCM Register Masks 02568 ---------------------------------------------------------------------------- */ 02569 02570 /*! 02571 * @addtogroup MCM_Register_Masks MCM Register Masks 02572 * @{ 02573 */ 02574 02575 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ 02576 #define MCM_PLASC_ASC_MASK (0xFFU) 02577 #define MCM_PLASC_ASC_SHIFT (0U) 02578 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) 02579 02580 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ 02581 #define MCM_PLAMC_AMC_MASK (0xFFU) 02582 #define MCM_PLAMC_AMC_SHIFT (0U) 02583 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) 02584 02585 /*! @name PLACR - Platform Control Register */ 02586 #define MCM_PLACR_ARB_MASK (0x200U) 02587 #define MCM_PLACR_ARB_SHIFT (9U) 02588 #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK) 02589 #define MCM_PLACR_CFCC_MASK (0x400U) 02590 #define MCM_PLACR_CFCC_SHIFT (10U) 02591 #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK) 02592 #define MCM_PLACR_DFCDA_MASK (0x800U) 02593 #define MCM_PLACR_DFCDA_SHIFT (11U) 02594 #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK) 02595 #define MCM_PLACR_DFCIC_MASK (0x1000U) 02596 #define MCM_PLACR_DFCIC_SHIFT (12U) 02597 #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK) 02598 #define MCM_PLACR_DFCC_MASK (0x2000U) 02599 #define MCM_PLACR_DFCC_SHIFT (13U) 02600 #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK) 02601 #define MCM_PLACR_EFDS_MASK (0x4000U) 02602 #define MCM_PLACR_EFDS_SHIFT (14U) 02603 #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK) 02604 #define MCM_PLACR_DFCS_MASK (0x8000U) 02605 #define MCM_PLACR_DFCS_SHIFT (15U) 02606 #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK) 02607 #define MCM_PLACR_ESFC_MASK (0x10000U) 02608 #define MCM_PLACR_ESFC_SHIFT (16U) 02609 #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK) 02610 02611 /*! @name CPO - Compute Operation Control Register */ 02612 #define MCM_CPO_CPOREQ_MASK (0x1U) 02613 #define MCM_CPO_CPOREQ_SHIFT (0U) 02614 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) 02615 #define MCM_CPO_CPOACK_MASK (0x2U) 02616 #define MCM_CPO_CPOACK_SHIFT (1U) 02617 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) 02618 #define MCM_CPO_CPOWOI_MASK (0x4U) 02619 #define MCM_CPO_CPOWOI_SHIFT (2U) 02620 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) 02621 02622 02623 /*! 02624 * @} 02625 */ /* end of group MCM_Register_Masks */ 02626 02627 02628 /* MCM - Peripheral instance base addresses */ 02629 /** Peripheral MCM base address */ 02630 #define MCM_BASE (0xF0003000u) 02631 /** Peripheral MCM base pointer */ 02632 #define MCM ((MCM_Type *)MCM_BASE) 02633 /** Array initializer of MCM peripheral base addresses */ 02634 #define MCM_BASE_ADDRS { MCM_BASE } 02635 /** Array initializer of MCM peripheral base pointers */ 02636 #define MCM_BASE_PTRS { MCM } 02637 02638 /*! 02639 * @} 02640 */ /* end of group MCM_Peripheral_Access_Layer */ 02641 02642 02643 /* ---------------------------------------------------------------------------- 02644 -- MTB Peripheral Access Layer 02645 ---------------------------------------------------------------------------- */ 02646 02647 /*! 02648 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer 02649 * @{ 02650 */ 02651 02652 /** MTB - Register Layout Typedef */ 02653 typedef struct { 02654 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ 02655 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ 02656 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ 02657 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */ 02658 uint8_t RESERVED_0[3824]; 02659 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ 02660 uint8_t RESERVED_1[156]; 02661 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ 02662 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ 02663 uint8_t RESERVED_2[8]; 02664 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ 02665 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ 02666 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ 02667 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ 02668 uint8_t RESERVED_3[8]; 02669 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 02670 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 02671 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 02672 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 02673 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 02674 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 02675 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 02676 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 02677 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 02678 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 02679 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 02680 } MTB_Type; 02681 02682 /* ---------------------------------------------------------------------------- 02683 -- MTB Register Masks 02684 ---------------------------------------------------------------------------- */ 02685 02686 /*! 02687 * @addtogroup MTB_Register_Masks MTB Register Masks 02688 * @{ 02689 */ 02690 02691 /*! @name POSITION - MTB Position Register */ 02692 #define MTB_POSITION_WRAP_MASK (0x4U) 02693 #define MTB_POSITION_WRAP_SHIFT (2U) 02694 #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK) 02695 #define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U) 02696 #define MTB_POSITION_POINTER_SHIFT (3U) 02697 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK) 02698 02699 /*! @name MASTER - MTB Master Register */ 02700 #define MTB_MASTER_MASK_MASK (0x1FU) 02701 #define MTB_MASTER_MASK_SHIFT (0U) 02702 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK) 02703 #define MTB_MASTER_TSTARTEN_MASK (0x20U) 02704 #define MTB_MASTER_TSTARTEN_SHIFT (5U) 02705 #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK) 02706 #define MTB_MASTER_TSTOPEN_MASK (0x40U) 02707 #define MTB_MASTER_TSTOPEN_SHIFT (6U) 02708 #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK) 02709 #define MTB_MASTER_SFRWPRIV_MASK (0x80U) 02710 #define MTB_MASTER_SFRWPRIV_SHIFT (7U) 02711 #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK) 02712 #define MTB_MASTER_RAMPRIV_MASK (0x100U) 02713 #define MTB_MASTER_RAMPRIV_SHIFT (8U) 02714 #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK) 02715 #define MTB_MASTER_HALTREQ_MASK (0x200U) 02716 #define MTB_MASTER_HALTREQ_SHIFT (9U) 02717 #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK) 02718 #define MTB_MASTER_EN_MASK (0x80000000U) 02719 #define MTB_MASTER_EN_SHIFT (31U) 02720 #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK) 02721 02722 /*! @name FLOW - MTB Flow Register */ 02723 #define MTB_FLOW_AUTOSTOP_MASK (0x1U) 02724 #define MTB_FLOW_AUTOSTOP_SHIFT (0U) 02725 #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK) 02726 #define MTB_FLOW_AUTOHALT_MASK (0x2U) 02727 #define MTB_FLOW_AUTOHALT_SHIFT (1U) 02728 #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK) 02729 #define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U) 02730 #define MTB_FLOW_WATERMARK_SHIFT (3U) 02731 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK) 02732 02733 /*! @name BASE - MTB Base Register */ 02734 #define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU) 02735 #define MTB_BASE_BASEADDR_SHIFT (0U) 02736 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK) 02737 02738 /*! @name MODECTRL - Integration Mode Control Register */ 02739 #define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU) 02740 #define MTB_MODECTRL_MODECTRL_SHIFT (0U) 02741 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK) 02742 02743 /*! @name TAGSET - Claim TAG Set Register */ 02744 #define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU) 02745 #define MTB_TAGSET_TAGSET_SHIFT (0U) 02746 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK) 02747 02748 /*! @name TAGCLEAR - Claim TAG Clear Register */ 02749 #define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU) 02750 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U) 02751 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK) 02752 02753 /*! @name LOCKACCESS - Lock Access Register */ 02754 #define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU) 02755 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U) 02756 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK) 02757 02758 /*! @name LOCKSTAT - Lock Status Register */ 02759 #define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU) 02760 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U) 02761 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK) 02762 02763 /*! @name AUTHSTAT - Authentication Status Register */ 02764 #define MTB_AUTHSTAT_BIT0_MASK (0x1U) 02765 #define MTB_AUTHSTAT_BIT0_SHIFT (0U) 02766 #define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK) 02767 #define MTB_AUTHSTAT_BIT1_MASK (0x2U) 02768 #define MTB_AUTHSTAT_BIT1_SHIFT (1U) 02769 #define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK) 02770 #define MTB_AUTHSTAT_BIT2_MASK (0x4U) 02771 #define MTB_AUTHSTAT_BIT2_SHIFT (2U) 02772 #define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK) 02773 #define MTB_AUTHSTAT_BIT3_MASK (0x8U) 02774 #define MTB_AUTHSTAT_BIT3_SHIFT (3U) 02775 #define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK) 02776 02777 /*! @name DEVICEARCH - Device Architecture Register */ 02778 #define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU) 02779 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U) 02780 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK) 02781 02782 /*! @name DEVICECFG - Device Configuration Register */ 02783 #define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) 02784 #define MTB_DEVICECFG_DEVICECFG_SHIFT (0U) 02785 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK) 02786 02787 /*! @name DEVICETYPID - Device Type Identifier Register */ 02788 #define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) 02789 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U) 02790 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK) 02791 02792 /*! @name PERIPHID4 - Peripheral ID Register */ 02793 #define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 02794 #define MTB_PERIPHID4_PERIPHID_SHIFT (0U) 02795 #define MTB_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK) 02796 02797 /*! @name PERIPHID5 - Peripheral ID Register */ 02798 #define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 02799 #define MTB_PERIPHID5_PERIPHID_SHIFT (0U) 02800 #define MTB_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK) 02801 02802 /*! @name PERIPHID6 - Peripheral ID Register */ 02803 #define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 02804 #define MTB_PERIPHID6_PERIPHID_SHIFT (0U) 02805 #define MTB_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK) 02806 02807 /*! @name PERIPHID7 - Peripheral ID Register */ 02808 #define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 02809 #define MTB_PERIPHID7_PERIPHID_SHIFT (0U) 02810 #define MTB_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK) 02811 02812 /*! @name PERIPHID0 - Peripheral ID Register */ 02813 #define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 02814 #define MTB_PERIPHID0_PERIPHID_SHIFT (0U) 02815 #define MTB_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK) 02816 02817 /*! @name PERIPHID1 - Peripheral ID Register */ 02818 #define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 02819 #define MTB_PERIPHID1_PERIPHID_SHIFT (0U) 02820 #define MTB_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK) 02821 02822 /*! @name PERIPHID2 - Peripheral ID Register */ 02823 #define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 02824 #define MTB_PERIPHID2_PERIPHID_SHIFT (0U) 02825 #define MTB_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK) 02826 02827 /*! @name PERIPHID3 - Peripheral ID Register */ 02828 #define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 02829 #define MTB_PERIPHID3_PERIPHID_SHIFT (0U) 02830 #define MTB_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK) 02831 02832 /*! @name COMPID - Component ID Register */ 02833 #define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU) 02834 #define MTB_COMPID_COMPID_SHIFT (0U) 02835 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK) 02836 02837 /* The count of MTB_COMPID */ 02838 #define MTB_COMPID_COUNT (4U) 02839 02840 02841 /*! 02842 * @} 02843 */ /* end of group MTB_Register_Masks */ 02844 02845 02846 /* MTB - Peripheral instance base addresses */ 02847 /** Peripheral MTB base address */ 02848 #define MTB_BASE (0xF0000000u) 02849 /** Peripheral MTB base pointer */ 02850 #define MTB ((MTB_Type *)MTB_BASE) 02851 /** Array initializer of MTB peripheral base addresses */ 02852 #define MTB_BASE_ADDRS { MTB_BASE } 02853 /** Array initializer of MTB peripheral base pointers */ 02854 #define MTB_BASE_PTRS { MTB } 02855 02856 /*! 02857 * @} 02858 */ /* end of group MTB_Peripheral_Access_Layer */ 02859 02860 02861 /* ---------------------------------------------------------------------------- 02862 -- MTBDWT Peripheral Access Layer 02863 ---------------------------------------------------------------------------- */ 02864 02865 /*! 02866 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer 02867 * @{ 02868 */ 02869 02870 /** MTBDWT - Register Layout Typedef */ 02871 typedef struct { 02872 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ 02873 uint8_t RESERVED_0[28]; 02874 struct { /* offset: 0x20, array step: 0x10 */ 02875 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ 02876 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ 02877 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ 02878 uint8_t RESERVED_0[4]; 02879 } COMPARATOR[2]; 02880 uint8_t RESERVED_1[448]; 02881 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ 02882 uint8_t RESERVED_2[3524]; 02883 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 02884 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 02885 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 02886 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 02887 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 02888 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 02889 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 02890 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 02891 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 02892 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 02893 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 02894 } MTBDWT_Type; 02895 02896 /* ---------------------------------------------------------------------------- 02897 -- MTBDWT Register Masks 02898 ---------------------------------------------------------------------------- */ 02899 02900 /*! 02901 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks 02902 * @{ 02903 */ 02904 02905 /*! @name CTRL - MTB DWT Control Register */ 02906 #define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU) 02907 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U) 02908 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK) 02909 #define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U) 02910 #define MTBDWT_CTRL_NUMCMP_SHIFT (28U) 02911 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK) 02912 02913 /*! @name COMP - MTB_DWT Comparator Register */ 02914 #define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU) 02915 #define MTBDWT_COMP_COMP_SHIFT (0U) 02916 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK) 02917 02918 /* The count of MTBDWT_COMP */ 02919 #define MTBDWT_COMP_COUNT (2U) 02920 02921 /*! @name MASK - MTB_DWT Comparator Mask Register */ 02922 #define MTBDWT_MASK_MASK_MASK (0x1FU) 02923 #define MTBDWT_MASK_MASK_SHIFT (0U) 02924 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK) 02925 02926 /* The count of MTBDWT_MASK */ 02927 #define MTBDWT_MASK_COUNT (2U) 02928 02929 /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */ 02930 #define MTBDWT_FCT_FUNCTION_MASK (0xFU) 02931 #define MTBDWT_FCT_FUNCTION_SHIFT (0U) 02932 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK) 02933 #define MTBDWT_FCT_DATAVMATCH_MASK (0x100U) 02934 #define MTBDWT_FCT_DATAVMATCH_SHIFT (8U) 02935 #define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK) 02936 #define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U) 02937 #define MTBDWT_FCT_DATAVSIZE_SHIFT (10U) 02938 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK) 02939 #define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U) 02940 #define MTBDWT_FCT_DATAVADDR0_SHIFT (12U) 02941 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK) 02942 #define MTBDWT_FCT_MATCHED_MASK (0x1000000U) 02943 #define MTBDWT_FCT_MATCHED_SHIFT (24U) 02944 #define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK) 02945 02946 /* The count of MTBDWT_FCT */ 02947 #define MTBDWT_FCT_COUNT (2U) 02948 02949 /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */ 02950 #define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U) 02951 #define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U) 02952 #define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK) 02953 #define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U) 02954 #define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U) 02955 #define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK) 02956 #define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U) 02957 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U) 02958 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK) 02959 02960 /*! @name DEVICECFG - Device Configuration Register */ 02961 #define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) 02962 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U) 02963 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK) 02964 02965 /*! @name DEVICETYPID - Device Type Identifier Register */ 02966 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) 02967 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U) 02968 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK) 02969 02970 /*! @name PERIPHID4 - Peripheral ID Register */ 02971 #define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 02972 #define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U) 02973 #define MTBDWT_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK) 02974 02975 /*! @name PERIPHID5 - Peripheral ID Register */ 02976 #define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 02977 #define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U) 02978 #define MTBDWT_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK) 02979 02980 /*! @name PERIPHID6 - Peripheral ID Register */ 02981 #define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 02982 #define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U) 02983 #define MTBDWT_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK) 02984 02985 /*! @name PERIPHID7 - Peripheral ID Register */ 02986 #define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 02987 #define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U) 02988 #define MTBDWT_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK) 02989 02990 /*! @name PERIPHID0 - Peripheral ID Register */ 02991 #define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 02992 #define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U) 02993 #define MTBDWT_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK) 02994 02995 /*! @name PERIPHID1 - Peripheral ID Register */ 02996 #define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 02997 #define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U) 02998 #define MTBDWT_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK) 02999 03000 /*! @name PERIPHID2 - Peripheral ID Register */ 03001 #define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 03002 #define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U) 03003 #define MTBDWT_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK) 03004 03005 /*! @name PERIPHID3 - Peripheral ID Register */ 03006 #define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 03007 #define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U) 03008 #define MTBDWT_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK) 03009 03010 /*! @name COMPID - Component ID Register */ 03011 #define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU) 03012 #define MTBDWT_COMPID_COMPID_SHIFT (0U) 03013 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK) 03014 03015 /* The count of MTBDWT_COMPID */ 03016 #define MTBDWT_COMPID_COUNT (4U) 03017 03018 03019 /*! 03020 * @} 03021 */ /* end of group MTBDWT_Register_Masks */ 03022 03023 03024 /* MTBDWT - Peripheral instance base addresses */ 03025 /** Peripheral MTBDWT base address */ 03026 #define MTBDWT_BASE (0xF0001000u) 03027 /** Peripheral MTBDWT base pointer */ 03028 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE) 03029 /** Array initializer of MTBDWT peripheral base addresses */ 03030 #define MTBDWT_BASE_ADDRS { MTBDWT_BASE } 03031 /** Array initializer of MTBDWT peripheral base pointers */ 03032 #define MTBDWT_BASE_PTRS { MTBDWT } 03033 03034 /*! 03035 * @} 03036 */ /* end of group MTBDWT_Peripheral_Access_Layer */ 03037 03038 03039 /* ---------------------------------------------------------------------------- 03040 -- NV Peripheral Access Layer 03041 ---------------------------------------------------------------------------- */ 03042 03043 /*! 03044 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer 03045 * @{ 03046 */ 03047 03048 /** NV - Register Layout Typedef */ 03049 typedef struct { 03050 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ 03051 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ 03052 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ 03053 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ 03054 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ 03055 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ 03056 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ 03057 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ 03058 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ 03059 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ 03060 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ 03061 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ 03062 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ 03063 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ 03064 } NV_Type; 03065 03066 /* ---------------------------------------------------------------------------- 03067 -- NV Register Masks 03068 ---------------------------------------------------------------------------- */ 03069 03070 /*! 03071 * @addtogroup NV_Register_Masks NV Register Masks 03072 * @{ 03073 */ 03074 03075 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */ 03076 #define NV_BACKKEY3_KEY_MASK (0xFFU) 03077 #define NV_BACKKEY3_KEY_SHIFT (0U) 03078 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) 03079 03080 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */ 03081 #define NV_BACKKEY2_KEY_MASK (0xFFU) 03082 #define NV_BACKKEY2_KEY_SHIFT (0U) 03083 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) 03084 03085 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */ 03086 #define NV_BACKKEY1_KEY_MASK (0xFFU) 03087 #define NV_BACKKEY1_KEY_SHIFT (0U) 03088 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) 03089 03090 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */ 03091 #define NV_BACKKEY0_KEY_MASK (0xFFU) 03092 #define NV_BACKKEY0_KEY_SHIFT (0U) 03093 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) 03094 03095 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */ 03096 #define NV_BACKKEY7_KEY_MASK (0xFFU) 03097 #define NV_BACKKEY7_KEY_SHIFT (0U) 03098 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) 03099 03100 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */ 03101 #define NV_BACKKEY6_KEY_MASK (0xFFU) 03102 #define NV_BACKKEY6_KEY_SHIFT (0U) 03103 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) 03104 03105 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */ 03106 #define NV_BACKKEY5_KEY_MASK (0xFFU) 03107 #define NV_BACKKEY5_KEY_SHIFT (0U) 03108 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) 03109 03110 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */ 03111 #define NV_BACKKEY4_KEY_MASK (0xFFU) 03112 #define NV_BACKKEY4_KEY_SHIFT (0U) 03113 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) 03114 03115 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ 03116 #define NV_FPROT3_PROT_MASK (0xFFU) 03117 #define NV_FPROT3_PROT_SHIFT (0U) 03118 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) 03119 03120 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ 03121 #define NV_FPROT2_PROT_MASK (0xFFU) 03122 #define NV_FPROT2_PROT_SHIFT (0U) 03123 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) 03124 03125 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ 03126 #define NV_FPROT1_PROT_MASK (0xFFU) 03127 #define NV_FPROT1_PROT_SHIFT (0U) 03128 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) 03129 03130 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ 03131 #define NV_FPROT0_PROT_MASK (0xFFU) 03132 #define NV_FPROT0_PROT_SHIFT (0U) 03133 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) 03134 03135 /*! @name FSEC - Non-volatile Flash Security Register */ 03136 #define NV_FSEC_SEC_MASK (0x3U) 03137 #define NV_FSEC_SEC_SHIFT (0U) 03138 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) 03139 #define NV_FSEC_FSLACC_MASK (0xCU) 03140 #define NV_FSEC_FSLACC_SHIFT (2U) 03141 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) 03142 #define NV_FSEC_MEEN_MASK (0x30U) 03143 #define NV_FSEC_MEEN_SHIFT (4U) 03144 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) 03145 #define NV_FSEC_KEYEN_MASK (0xC0U) 03146 #define NV_FSEC_KEYEN_SHIFT (6U) 03147 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) 03148 03149 /*! @name FOPT - Non-volatile Flash Option Register */ 03150 #define NV_FOPT_LPBOOT0_MASK (0x1U) 03151 #define NV_FOPT_LPBOOT0_SHIFT (0U) 03152 #define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK) 03153 #define NV_FOPT_NMI_DIS_MASK (0x4U) 03154 #define NV_FOPT_NMI_DIS_SHIFT (2U) 03155 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK) 03156 #define NV_FOPT_RESET_PIN_CFG_MASK (0x8U) 03157 #define NV_FOPT_RESET_PIN_CFG_SHIFT (3U) 03158 #define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK) 03159 #define NV_FOPT_LPBOOT1_MASK (0x10U) 03160 #define NV_FOPT_LPBOOT1_SHIFT (4U) 03161 #define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK) 03162 #define NV_FOPT_FAST_INIT_MASK (0x20U) 03163 #define NV_FOPT_FAST_INIT_SHIFT (5U) 03164 #define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK) 03165 03166 03167 /*! 03168 * @} 03169 */ /* end of group NV_Register_Masks */ 03170 03171 03172 /* NV - Peripheral instance base addresses */ 03173 /** Peripheral FTFA_FlashConfig base address */ 03174 #define FTFA_FlashConfig_BASE (0x400u) 03175 /** Peripheral FTFA_FlashConfig base pointer */ 03176 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE) 03177 /** Array initializer of NV peripheral base addresses */ 03178 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE } 03179 /** Array initializer of NV peripheral base pointers */ 03180 #define NV_BASE_PTRS { FTFA_FlashConfig } 03181 03182 /*! 03183 * @} 03184 */ /* end of group NV_Peripheral_Access_Layer */ 03185 03186 03187 /* ---------------------------------------------------------------------------- 03188 -- OSC Peripheral Access Layer 03189 ---------------------------------------------------------------------------- */ 03190 03191 /*! 03192 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer 03193 * @{ 03194 */ 03195 03196 /** OSC - Register Layout Typedef */ 03197 typedef struct { 03198 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ 03199 } OSC_Type; 03200 03201 /* ---------------------------------------------------------------------------- 03202 -- OSC Register Masks 03203 ---------------------------------------------------------------------------- */ 03204 03205 /*! 03206 * @addtogroup OSC_Register_Masks OSC Register Masks 03207 * @{ 03208 */ 03209 03210 /*! @name CR - OSC Control Register */ 03211 #define OSC_CR_SC16P_MASK (0x1U) 03212 #define OSC_CR_SC16P_SHIFT (0U) 03213 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) 03214 #define OSC_CR_SC8P_MASK (0x2U) 03215 #define OSC_CR_SC8P_SHIFT (1U) 03216 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) 03217 #define OSC_CR_SC4P_MASK (0x4U) 03218 #define OSC_CR_SC4P_SHIFT (2U) 03219 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) 03220 #define OSC_CR_SC2P_MASK (0x8U) 03221 #define OSC_CR_SC2P_SHIFT (3U) 03222 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) 03223 #define OSC_CR_EREFSTEN_MASK (0x20U) 03224 #define OSC_CR_EREFSTEN_SHIFT (5U) 03225 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) 03226 #define OSC_CR_ERCLKEN_MASK (0x80U) 03227 #define OSC_CR_ERCLKEN_SHIFT (7U) 03228 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) 03229 03230 03231 /*! 03232 * @} 03233 */ /* end of group OSC_Register_Masks */ 03234 03235 03236 /* OSC - Peripheral instance base addresses */ 03237 /** Peripheral OSC0 base address */ 03238 #define OSC0_BASE (0x40065000u) 03239 /** Peripheral OSC0 base pointer */ 03240 #define OSC0 ((OSC_Type *)OSC0_BASE) 03241 /** Array initializer of OSC peripheral base addresses */ 03242 #define OSC_BASE_ADDRS { OSC0_BASE } 03243 /** Array initializer of OSC peripheral base pointers */ 03244 #define OSC_BASE_PTRS { OSC0 } 03245 03246 /*! 03247 * @} 03248 */ /* end of group OSC_Peripheral_Access_Layer */ 03249 03250 03251 /* ---------------------------------------------------------------------------- 03252 -- PIT Peripheral Access Layer 03253 ---------------------------------------------------------------------------- */ 03254 03255 /*! 03256 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer 03257 * @{ 03258 */ 03259 03260 /** PIT - Register Layout Typedef */ 03261 typedef struct { 03262 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ 03263 uint8_t RESERVED_0[220]; 03264 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ 03265 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ 03266 uint8_t RESERVED_1[24]; 03267 struct { /* offset: 0x100, array step: 0x10 */ 03268 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ 03269 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ 03270 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ 03271 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ 03272 } CHANNEL[2]; 03273 } PIT_Type; 03274 03275 /* ---------------------------------------------------------------------------- 03276 -- PIT Register Masks 03277 ---------------------------------------------------------------------------- */ 03278 03279 /*! 03280 * @addtogroup PIT_Register_Masks PIT Register Masks 03281 * @{ 03282 */ 03283 03284 /*! @name MCR - PIT Module Control Register */ 03285 #define PIT_MCR_FRZ_MASK (0x1U) 03286 #define PIT_MCR_FRZ_SHIFT (0U) 03287 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) 03288 #define PIT_MCR_MDIS_MASK (0x2U) 03289 #define PIT_MCR_MDIS_SHIFT (1U) 03290 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) 03291 03292 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */ 03293 #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) 03294 #define PIT_LTMR64H_LTH_SHIFT (0U) 03295 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) 03296 03297 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */ 03298 #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) 03299 #define PIT_LTMR64L_LTL_SHIFT (0U) 03300 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) 03301 03302 /*! @name LDVAL - Timer Load Value Register */ 03303 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) 03304 #define PIT_LDVAL_TSV_SHIFT (0U) 03305 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) 03306 03307 /* The count of PIT_LDVAL */ 03308 #define PIT_LDVAL_COUNT (2U) 03309 03310 /*! @name CVAL - Current Timer Value Register */ 03311 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) 03312 #define PIT_CVAL_TVL_SHIFT (0U) 03313 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) 03314 03315 /* The count of PIT_CVAL */ 03316 #define PIT_CVAL_COUNT (2U) 03317 03318 /*! @name TCTRL - Timer Control Register */ 03319 #define PIT_TCTRL_TEN_MASK (0x1U) 03320 #define PIT_TCTRL_TEN_SHIFT (0U) 03321 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) 03322 #define PIT_TCTRL_TIE_MASK (0x2U) 03323 #define PIT_TCTRL_TIE_SHIFT (1U) 03324 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) 03325 #define PIT_TCTRL_CHN_MASK (0x4U) 03326 #define PIT_TCTRL_CHN_SHIFT (2U) 03327 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) 03328 03329 /* The count of PIT_TCTRL */ 03330 #define PIT_TCTRL_COUNT (2U) 03331 03332 /*! @name TFLG - Timer Flag Register */ 03333 #define PIT_TFLG_TIF_MASK (0x1U) 03334 #define PIT_TFLG_TIF_SHIFT (0U) 03335 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) 03336 03337 /* The count of PIT_TFLG */ 03338 #define PIT_TFLG_COUNT (2U) 03339 03340 03341 /*! 03342 * @} 03343 */ /* end of group PIT_Register_Masks */ 03344 03345 03346 /* PIT - Peripheral instance base addresses */ 03347 /** Peripheral PIT base address */ 03348 #define PIT_BASE (0x40037000u) 03349 /** Peripheral PIT base pointer */ 03350 #define PIT ((PIT_Type *)PIT_BASE) 03351 /** Array initializer of PIT peripheral base addresses */ 03352 #define PIT_BASE_ADDRS { PIT_BASE } 03353 /** Array initializer of PIT peripheral base pointers */ 03354 #define PIT_BASE_PTRS { PIT } 03355 /** Interrupt vectors for the PIT peripheral type */ 03356 #define PIT_IRQS { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } 03357 03358 /*! 03359 * @} 03360 */ /* end of group PIT_Peripheral_Access_Layer */ 03361 03362 03363 /* ---------------------------------------------------------------------------- 03364 -- PMC Peripheral Access Layer 03365 ---------------------------------------------------------------------------- */ 03366 03367 /*! 03368 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer 03369 * @{ 03370 */ 03371 03372 /** PMC - Register Layout Typedef */ 03373 typedef struct { 03374 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ 03375 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ 03376 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ 03377 } PMC_Type; 03378 03379 /* ---------------------------------------------------------------------------- 03380 -- PMC Register Masks 03381 ---------------------------------------------------------------------------- */ 03382 03383 /*! 03384 * @addtogroup PMC_Register_Masks PMC Register Masks 03385 * @{ 03386 */ 03387 03388 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ 03389 #define PMC_LVDSC1_LVDV_MASK (0x3U) 03390 #define PMC_LVDSC1_LVDV_SHIFT (0U) 03391 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) 03392 #define PMC_LVDSC1_LVDRE_MASK (0x10U) 03393 #define PMC_LVDSC1_LVDRE_SHIFT (4U) 03394 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) 03395 #define PMC_LVDSC1_LVDIE_MASK (0x20U) 03396 #define PMC_LVDSC1_LVDIE_SHIFT (5U) 03397 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) 03398 #define PMC_LVDSC1_LVDACK_MASK (0x40U) 03399 #define PMC_LVDSC1_LVDACK_SHIFT (6U) 03400 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) 03401 #define PMC_LVDSC1_LVDF_MASK (0x80U) 03402 #define PMC_LVDSC1_LVDF_SHIFT (7U) 03403 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) 03404 03405 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ 03406 #define PMC_LVDSC2_LVWV_MASK (0x3U) 03407 #define PMC_LVDSC2_LVWV_SHIFT (0U) 03408 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) 03409 #define PMC_LVDSC2_LVWIE_MASK (0x20U) 03410 #define PMC_LVDSC2_LVWIE_SHIFT (5U) 03411 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) 03412 #define PMC_LVDSC2_LVWACK_MASK (0x40U) 03413 #define PMC_LVDSC2_LVWACK_SHIFT (6U) 03414 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) 03415 #define PMC_LVDSC2_LVWF_MASK (0x80U) 03416 #define PMC_LVDSC2_LVWF_SHIFT (7U) 03417 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) 03418 03419 /*! @name REGSC - Regulator Status And Control register */ 03420 #define PMC_REGSC_BGBE_MASK (0x1U) 03421 #define PMC_REGSC_BGBE_SHIFT (0U) 03422 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) 03423 #define PMC_REGSC_REGONS_MASK (0x4U) 03424 #define PMC_REGSC_REGONS_SHIFT (2U) 03425 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) 03426 #define PMC_REGSC_ACKISO_MASK (0x8U) 03427 #define PMC_REGSC_ACKISO_SHIFT (3U) 03428 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) 03429 #define PMC_REGSC_BGEN_MASK (0x10U) 03430 #define PMC_REGSC_BGEN_SHIFT (4U) 03431 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK) 03432 03433 03434 /*! 03435 * @} 03436 */ /* end of group PMC_Register_Masks */ 03437 03438 03439 /* PMC - Peripheral instance base addresses */ 03440 /** Peripheral PMC base address */ 03441 #define PMC_BASE (0x4007D000u) 03442 /** Peripheral PMC base pointer */ 03443 #define PMC ((PMC_Type *)PMC_BASE) 03444 /** Array initializer of PMC peripheral base addresses */ 03445 #define PMC_BASE_ADDRS { PMC_BASE } 03446 /** Array initializer of PMC peripheral base pointers */ 03447 #define PMC_BASE_PTRS { PMC } 03448 /** Interrupt vectors for the PMC peripheral type */ 03449 #define PMC_IRQS { LVD_LVW_IRQn } 03450 03451 /*! 03452 * @} 03453 */ /* end of group PMC_Peripheral_Access_Layer */ 03454 03455 03456 /* ---------------------------------------------------------------------------- 03457 -- PORT Peripheral Access Layer 03458 ---------------------------------------------------------------------------- */ 03459 03460 /*! 03461 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer 03462 * @{ 03463 */ 03464 03465 /** PORT - Register Layout Typedef */ 03466 typedef struct { 03467 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ 03468 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ 03469 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ 03470 uint8_t RESERVED_0[24]; 03471 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ 03472 } PORT_Type; 03473 03474 /* ---------------------------------------------------------------------------- 03475 -- PORT Register Masks 03476 ---------------------------------------------------------------------------- */ 03477 03478 /*! 03479 * @addtogroup PORT_Register_Masks PORT Register Masks 03480 * @{ 03481 */ 03482 03483 /*! @name PCR - Pin Control Register n */ 03484 #define PORT_PCR_PS_MASK (0x1U) 03485 #define PORT_PCR_PS_SHIFT (0U) 03486 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) 03487 #define PORT_PCR_PE_MASK (0x2U) 03488 #define PORT_PCR_PE_SHIFT (1U) 03489 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) 03490 #define PORT_PCR_SRE_MASK (0x4U) 03491 #define PORT_PCR_SRE_SHIFT (2U) 03492 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) 03493 #define PORT_PCR_PFE_MASK (0x10U) 03494 #define PORT_PCR_PFE_SHIFT (4U) 03495 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) 03496 #define PORT_PCR_DSE_MASK (0x40U) 03497 #define PORT_PCR_DSE_SHIFT (6U) 03498 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) 03499 #define PORT_PCR_MUX_MASK (0x700U) 03500 #define PORT_PCR_MUX_SHIFT (8U) 03501 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) 03502 #define PORT_PCR_IRQC_MASK (0xF0000U) 03503 #define PORT_PCR_IRQC_SHIFT (16U) 03504 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) 03505 #define PORT_PCR_ISF_MASK (0x1000000U) 03506 #define PORT_PCR_ISF_SHIFT (24U) 03507 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) 03508 03509 /* The count of PORT_PCR */ 03510 #define PORT_PCR_COUNT (32U) 03511 03512 /*! @name GPCLR - Global Pin Control Low Register */ 03513 #define PORT_GPCLR_GPWD_MASK (0xFFFFU) 03514 #define PORT_GPCLR_GPWD_SHIFT (0U) 03515 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) 03516 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) 03517 #define PORT_GPCLR_GPWE_SHIFT (16U) 03518 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) 03519 03520 /*! @name GPCHR - Global Pin Control High Register */ 03521 #define PORT_GPCHR_GPWD_MASK (0xFFFFU) 03522 #define PORT_GPCHR_GPWD_SHIFT (0U) 03523 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) 03524 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) 03525 #define PORT_GPCHR_GPWE_SHIFT (16U) 03526 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) 03527 03528 /*! @name ISFR - Interrupt Status Flag Register */ 03529 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) 03530 #define PORT_ISFR_ISF_SHIFT (0U) 03531 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) 03532 03533 03534 /*! 03535 * @} 03536 */ /* end of group PORT_Register_Masks */ 03537 03538 03539 /* PORT - Peripheral instance base addresses */ 03540 /** Peripheral PORTA base address */ 03541 #define PORTA_BASE (0x40049000u) 03542 /** Peripheral PORTA base pointer */ 03543 #define PORTA ((PORT_Type *)PORTA_BASE) 03544 /** Peripheral PORTB base address */ 03545 #define PORTB_BASE (0x4004A000u) 03546 /** Peripheral PORTB base pointer */ 03547 #define PORTB ((PORT_Type *)PORTB_BASE) 03548 /** Peripheral PORTC base address */ 03549 #define PORTC_BASE (0x4004B000u) 03550 /** Peripheral PORTC base pointer */ 03551 #define PORTC ((PORT_Type *)PORTC_BASE) 03552 /** Peripheral PORTD base address */ 03553 #define PORTD_BASE (0x4004C000u) 03554 /** Peripheral PORTD base pointer */ 03555 #define PORTD ((PORT_Type *)PORTD_BASE) 03556 /** Peripheral PORTE base address */ 03557 #define PORTE_BASE (0x4004D000u) 03558 /** Peripheral PORTE base pointer */ 03559 #define PORTE ((PORT_Type *)PORTE_BASE) 03560 /** Array initializer of PORT peripheral base addresses */ 03561 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } 03562 /** Array initializer of PORT peripheral base pointers */ 03563 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } 03564 /** Interrupt vectors for the PORT peripheral type */ 03565 #define PORT_IRQS { PORTA_IRQn, NotAvail_IRQn, PORTC_PORTD_IRQn, PORTC_PORTD_IRQn, NotAvail_IRQn } 03566 03567 /*! 03568 * @} 03569 */ /* end of group PORT_Peripheral_Access_Layer */ 03570 03571 03572 /* ---------------------------------------------------------------------------- 03573 -- RCM Peripheral Access Layer 03574 ---------------------------------------------------------------------------- */ 03575 03576 /*! 03577 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer 03578 * @{ 03579 */ 03580 03581 /** RCM - Register Layout Typedef */ 03582 typedef struct { 03583 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ 03584 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ 03585 uint8_t RESERVED_0[2]; 03586 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ 03587 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ 03588 } RCM_Type; 03589 03590 /* ---------------------------------------------------------------------------- 03591 -- RCM Register Masks 03592 ---------------------------------------------------------------------------- */ 03593 03594 /*! 03595 * @addtogroup RCM_Register_Masks RCM Register Masks 03596 * @{ 03597 */ 03598 03599 /*! @name SRS0 - System Reset Status Register 0 */ 03600 #define RCM_SRS0_WAKEUP_MASK (0x1U) 03601 #define RCM_SRS0_WAKEUP_SHIFT (0U) 03602 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) 03603 #define RCM_SRS0_LVD_MASK (0x2U) 03604 #define RCM_SRS0_LVD_SHIFT (1U) 03605 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) 03606 #define RCM_SRS0_LOC_MASK (0x4U) 03607 #define RCM_SRS0_LOC_SHIFT (2U) 03608 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK) 03609 #define RCM_SRS0_LOL_MASK (0x8U) 03610 #define RCM_SRS0_LOL_SHIFT (3U) 03611 #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK) 03612 #define RCM_SRS0_WDOG_MASK (0x20U) 03613 #define RCM_SRS0_WDOG_SHIFT (5U) 03614 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) 03615 #define RCM_SRS0_PIN_MASK (0x40U) 03616 #define RCM_SRS0_PIN_SHIFT (6U) 03617 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) 03618 #define RCM_SRS0_POR_MASK (0x80U) 03619 #define RCM_SRS0_POR_SHIFT (7U) 03620 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) 03621 03622 /*! @name SRS1 - System Reset Status Register 1 */ 03623 #define RCM_SRS1_LOCKUP_MASK (0x2U) 03624 #define RCM_SRS1_LOCKUP_SHIFT (1U) 03625 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) 03626 #define RCM_SRS1_SW_MASK (0x4U) 03627 #define RCM_SRS1_SW_SHIFT (2U) 03628 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) 03629 #define RCM_SRS1_MDM_AP_MASK (0x8U) 03630 #define RCM_SRS1_MDM_AP_SHIFT (3U) 03631 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) 03632 #define RCM_SRS1_SACKERR_MASK (0x20U) 03633 #define RCM_SRS1_SACKERR_SHIFT (5U) 03634 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) 03635 03636 /*! @name RPFC - Reset Pin Filter Control register */ 03637 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U) 03638 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U) 03639 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) 03640 #define RCM_RPFC_RSTFLTSS_MASK (0x4U) 03641 #define RCM_RPFC_RSTFLTSS_SHIFT (2U) 03642 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) 03643 03644 /*! @name RPFW - Reset Pin Filter Width register */ 03645 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) 03646 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U) 03647 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) 03648 03649 03650 /*! 03651 * @} 03652 */ /* end of group RCM_Register_Masks */ 03653 03654 03655 /* RCM - Peripheral instance base addresses */ 03656 /** Peripheral RCM base address */ 03657 #define RCM_BASE (0x4007F000u) 03658 /** Peripheral RCM base pointer */ 03659 #define RCM ((RCM_Type *)RCM_BASE) 03660 /** Array initializer of RCM peripheral base addresses */ 03661 #define RCM_BASE_ADDRS { RCM_BASE } 03662 /** Array initializer of RCM peripheral base pointers */ 03663 #define RCM_BASE_PTRS { RCM } 03664 03665 /*! 03666 * @} 03667 */ /* end of group RCM_Peripheral_Access_Layer */ 03668 03669 03670 /* ---------------------------------------------------------------------------- 03671 -- ROM Peripheral Access Layer 03672 ---------------------------------------------------------------------------- */ 03673 03674 /*! 03675 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer 03676 * @{ 03677 */ 03678 03679 /** ROM - Register Layout Typedef */ 03680 typedef struct { 03681 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */ 03682 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */ 03683 uint8_t RESERVED_0[4028]; 03684 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ 03685 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 03686 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 03687 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 03688 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 03689 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 03690 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 03691 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 03692 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 03693 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 03694 } ROM_Type; 03695 03696 /* ---------------------------------------------------------------------------- 03697 -- ROM Register Masks 03698 ---------------------------------------------------------------------------- */ 03699 03700 /*! 03701 * @addtogroup ROM_Register_Masks ROM Register Masks 03702 * @{ 03703 */ 03704 03705 /*! @name ENTRY - Entry */ 03706 #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU) 03707 #define ROM_ENTRY_ENTRY_SHIFT (0U) 03708 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK) 03709 03710 /* The count of ROM_ENTRY */ 03711 #define ROM_ENTRY_COUNT (3U) 03712 03713 /*! @name TABLEMARK - End of Table Marker Register */ 03714 #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU) 03715 #define ROM_TABLEMARK_MARK_SHIFT (0U) 03716 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK) 03717 03718 /*! @name SYSACCESS - System Access Register */ 03719 #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU) 03720 #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U) 03721 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK) 03722 03723 /*! @name PERIPHID4 - Peripheral ID Register */ 03724 #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 03725 #define ROM_PERIPHID4_PERIPHID_SHIFT (0U) 03726 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK) 03727 03728 /*! @name PERIPHID5 - Peripheral ID Register */ 03729 #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 03730 #define ROM_PERIPHID5_PERIPHID_SHIFT (0U) 03731 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK) 03732 03733 /*! @name PERIPHID6 - Peripheral ID Register */ 03734 #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 03735 #define ROM_PERIPHID6_PERIPHID_SHIFT (0U) 03736 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK) 03737 03738 /*! @name PERIPHID7 - Peripheral ID Register */ 03739 #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 03740 #define ROM_PERIPHID7_PERIPHID_SHIFT (0U) 03741 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK) 03742 03743 /*! @name PERIPHID0 - Peripheral ID Register */ 03744 #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 03745 #define ROM_PERIPHID0_PERIPHID_SHIFT (0U) 03746 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK) 03747 03748 /*! @name PERIPHID1 - Peripheral ID Register */ 03749 #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 03750 #define ROM_PERIPHID1_PERIPHID_SHIFT (0U) 03751 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK) 03752 03753 /*! @name PERIPHID2 - Peripheral ID Register */ 03754 #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 03755 #define ROM_PERIPHID2_PERIPHID_SHIFT (0U) 03756 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK) 03757 03758 /*! @name PERIPHID3 - Peripheral ID Register */ 03759 #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 03760 #define ROM_PERIPHID3_PERIPHID_SHIFT (0U) 03761 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK) 03762 03763 /*! @name COMPID - Component ID Register */ 03764 #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU) 03765 #define ROM_COMPID_COMPID_SHIFT (0U) 03766 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK) 03767 03768 /* The count of ROM_COMPID */ 03769 #define ROM_COMPID_COUNT (4U) 03770 03771 03772 /*! 03773 * @} 03774 */ /* end of group ROM_Register_Masks */ 03775 03776 03777 /* ROM - Peripheral instance base addresses */ 03778 /** Peripheral ROM base address */ 03779 #define ROM_BASE (0xF0002000u) 03780 /** Peripheral ROM base pointer */ 03781 #define ROM ((ROM_Type *)ROM_BASE) 03782 /** Array initializer of ROM peripheral base addresses */ 03783 #define ROM_BASE_ADDRS { ROM_BASE } 03784 /** Array initializer of ROM peripheral base pointers */ 03785 #define ROM_BASE_PTRS { ROM } 03786 03787 /*! 03788 * @} 03789 */ /* end of group ROM_Peripheral_Access_Layer */ 03790 03791 03792 /* ---------------------------------------------------------------------------- 03793 -- RTC Peripheral Access Layer 03794 ---------------------------------------------------------------------------- */ 03795 03796 /*! 03797 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer 03798 * @{ 03799 */ 03800 03801 /** RTC - Register Layout Typedef */ 03802 typedef struct { 03803 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ 03804 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ 03805 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ 03806 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ 03807 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ 03808 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ 03809 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ 03810 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ 03811 } RTC_Type; 03812 03813 /* ---------------------------------------------------------------------------- 03814 -- RTC Register Masks 03815 ---------------------------------------------------------------------------- */ 03816 03817 /*! 03818 * @addtogroup RTC_Register_Masks RTC Register Masks 03819 * @{ 03820 */ 03821 03822 /*! @name TSR - RTC Time Seconds Register */ 03823 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU) 03824 #define RTC_TSR_TSR_SHIFT (0U) 03825 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) 03826 03827 /*! @name TPR - RTC Time Prescaler Register */ 03828 #define RTC_TPR_TPR_MASK (0xFFFFU) 03829 #define RTC_TPR_TPR_SHIFT (0U) 03830 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) 03831 03832 /*! @name TAR - RTC Time Alarm Register */ 03833 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU) 03834 #define RTC_TAR_TAR_SHIFT (0U) 03835 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) 03836 03837 /*! @name TCR - RTC Time Compensation Register */ 03838 #define RTC_TCR_TCR_MASK (0xFFU) 03839 #define RTC_TCR_TCR_SHIFT (0U) 03840 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) 03841 #define RTC_TCR_CIR_MASK (0xFF00U) 03842 #define RTC_TCR_CIR_SHIFT (8U) 03843 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) 03844 #define RTC_TCR_TCV_MASK (0xFF0000U) 03845 #define RTC_TCR_TCV_SHIFT (16U) 03846 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) 03847 #define RTC_TCR_CIC_MASK (0xFF000000U) 03848 #define RTC_TCR_CIC_SHIFT (24U) 03849 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) 03850 03851 /*! @name CR - RTC Control Register */ 03852 #define RTC_CR_SWR_MASK (0x1U) 03853 #define RTC_CR_SWR_SHIFT (0U) 03854 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) 03855 #define RTC_CR_WPE_MASK (0x2U) 03856 #define RTC_CR_WPE_SHIFT (1U) 03857 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) 03858 #define RTC_CR_SUP_MASK (0x4U) 03859 #define RTC_CR_SUP_SHIFT (2U) 03860 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) 03861 #define RTC_CR_UM_MASK (0x8U) 03862 #define RTC_CR_UM_SHIFT (3U) 03863 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) 03864 #define RTC_CR_WPS_MASK (0x10U) 03865 #define RTC_CR_WPS_SHIFT (4U) 03866 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) 03867 #define RTC_CR_OSCE_MASK (0x100U) 03868 #define RTC_CR_OSCE_SHIFT (8U) 03869 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) 03870 #define RTC_CR_CLKO_MASK (0x200U) 03871 #define RTC_CR_CLKO_SHIFT (9U) 03872 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) 03873 #define RTC_CR_SC16P_MASK (0x400U) 03874 #define RTC_CR_SC16P_SHIFT (10U) 03875 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) 03876 #define RTC_CR_SC8P_MASK (0x800U) 03877 #define RTC_CR_SC8P_SHIFT (11U) 03878 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) 03879 #define RTC_CR_SC4P_MASK (0x1000U) 03880 #define RTC_CR_SC4P_SHIFT (12U) 03881 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) 03882 #define RTC_CR_SC2P_MASK (0x2000U) 03883 #define RTC_CR_SC2P_SHIFT (13U) 03884 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) 03885 03886 /*! @name SR - RTC Status Register */ 03887 #define RTC_SR_TIF_MASK (0x1U) 03888 #define RTC_SR_TIF_SHIFT (0U) 03889 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) 03890 #define RTC_SR_TOF_MASK (0x2U) 03891 #define RTC_SR_TOF_SHIFT (1U) 03892 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) 03893 #define RTC_SR_TAF_MASK (0x4U) 03894 #define RTC_SR_TAF_SHIFT (2U) 03895 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) 03896 #define RTC_SR_TCE_MASK (0x10U) 03897 #define RTC_SR_TCE_SHIFT (4U) 03898 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) 03899 03900 /*! @name LR - RTC Lock Register */ 03901 #define RTC_LR_TCL_MASK (0x8U) 03902 #define RTC_LR_TCL_SHIFT (3U) 03903 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) 03904 #define RTC_LR_CRL_MASK (0x10U) 03905 #define RTC_LR_CRL_SHIFT (4U) 03906 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) 03907 #define RTC_LR_SRL_MASK (0x20U) 03908 #define RTC_LR_SRL_SHIFT (5U) 03909 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) 03910 #define RTC_LR_LRL_MASK (0x40U) 03911 #define RTC_LR_LRL_SHIFT (6U) 03912 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) 03913 03914 /*! @name IER - RTC Interrupt Enable Register */ 03915 #define RTC_IER_TIIE_MASK (0x1U) 03916 #define RTC_IER_TIIE_SHIFT (0U) 03917 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) 03918 #define RTC_IER_TOIE_MASK (0x2U) 03919 #define RTC_IER_TOIE_SHIFT (1U) 03920 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) 03921 #define RTC_IER_TAIE_MASK (0x4U) 03922 #define RTC_IER_TAIE_SHIFT (2U) 03923 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) 03924 #define RTC_IER_TSIE_MASK (0x10U) 03925 #define RTC_IER_TSIE_SHIFT (4U) 03926 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) 03927 #define RTC_IER_WPON_MASK (0x80U) 03928 #define RTC_IER_WPON_SHIFT (7U) 03929 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) 03930 03931 03932 /*! 03933 * @} 03934 */ /* end of group RTC_Register_Masks */ 03935 03936 03937 /* RTC - Peripheral instance base addresses */ 03938 /** Peripheral RTC base address */ 03939 #define RTC_BASE (0x4003D000u) 03940 /** Peripheral RTC base pointer */ 03941 #define RTC ((RTC_Type *)RTC_BASE) 03942 /** Array initializer of RTC peripheral base addresses */ 03943 #define RTC_BASE_ADDRS { RTC_BASE } 03944 /** Array initializer of RTC peripheral base pointers */ 03945 #define RTC_BASE_PTRS { RTC } 03946 /** Interrupt vectors for the RTC peripheral type */ 03947 #define RTC_IRQS { RTC_IRQn } 03948 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } 03949 03950 /*! 03951 * @} 03952 */ /* end of group RTC_Peripheral_Access_Layer */ 03953 03954 03955 /* ---------------------------------------------------------------------------- 03956 -- SIM Peripheral Access Layer 03957 ---------------------------------------------------------------------------- */ 03958 03959 /*! 03960 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer 03961 * @{ 03962 */ 03963 03964 /** SIM - Register Layout Typedef */ 03965 typedef struct { 03966 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ 03967 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ 03968 uint8_t RESERVED_0[4092]; 03969 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ 03970 uint8_t RESERVED_1[4]; 03971 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ 03972 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ 03973 uint8_t RESERVED_2[4]; 03974 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ 03975 uint8_t RESERVED_3[8]; 03976 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ 03977 uint8_t RESERVED_4[12]; 03978 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ 03979 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ 03980 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ 03981 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ 03982 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ 03983 uint8_t RESERVED_5[4]; 03984 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ 03985 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ 03986 uint8_t RESERVED_6[4]; 03987 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ 03988 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ 03989 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ 03990 uint8_t RESERVED_7[156]; 03991 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */ 03992 __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */ 03993 } SIM_Type; 03994 03995 /* ---------------------------------------------------------------------------- 03996 -- SIM Register Masks 03997 ---------------------------------------------------------------------------- */ 03998 03999 /*! 04000 * @addtogroup SIM_Register_Masks SIM Register Masks 04001 * @{ 04002 */ 04003 04004 /*! @name SOPT1 - System Options Register 1 */ 04005 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) 04006 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U) 04007 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) 04008 #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U) 04009 #define SIM_SOPT1_USBVSTBY_SHIFT (29U) 04010 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK) 04011 #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U) 04012 #define SIM_SOPT1_USBSSTBY_SHIFT (30U) 04013 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK) 04014 #define SIM_SOPT1_USBREGEN_MASK (0x80000000U) 04015 #define SIM_SOPT1_USBREGEN_SHIFT (31U) 04016 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK) 04017 04018 /*! @name SOPT1CFG - SOPT1 Configuration Register */ 04019 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) 04020 #define SIM_SOPT1CFG_URWE_SHIFT (24U) 04021 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK) 04022 #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U) 04023 #define SIM_SOPT1CFG_UVSWE_SHIFT (25U) 04024 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK) 04025 #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U) 04026 #define SIM_SOPT1CFG_USSWE_SHIFT (26U) 04027 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK) 04028 04029 /*! @name SOPT2 - System Options Register 2 */ 04030 #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U) 04031 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U) 04032 #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK) 04033 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U) 04034 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U) 04035 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK) 04036 #define SIM_SOPT2_PLLFLLSEL_MASK (0x10000U) 04037 #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U) 04038 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK) 04039 #define SIM_SOPT2_USBSRC_MASK (0x40000U) 04040 #define SIM_SOPT2_USBSRC_SHIFT (18U) 04041 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK) 04042 #define SIM_SOPT2_TPMSRC_MASK (0x3000000U) 04043 #define SIM_SOPT2_TPMSRC_SHIFT (24U) 04044 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK) 04045 #define SIM_SOPT2_UART0SRC_MASK (0xC000000U) 04046 #define SIM_SOPT2_UART0SRC_SHIFT (26U) 04047 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_UART0SRC_SHIFT)) & SIM_SOPT2_UART0SRC_MASK) 04048 04049 /*! @name SOPT4 - System Options Register 4 */ 04050 #define SIM_SOPT4_TPM1CH0SRC_MASK (0xC0000U) 04051 #define SIM_SOPT4_TPM1CH0SRC_SHIFT (18U) 04052 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK) 04053 #define SIM_SOPT4_TPM2CH0SRC_MASK (0x100000U) 04054 #define SIM_SOPT4_TPM2CH0SRC_SHIFT (20U) 04055 #define SIM_SOPT4_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK) 04056 #define SIM_SOPT4_TPM0CLKSEL_MASK (0x1000000U) 04057 #define SIM_SOPT4_TPM0CLKSEL_SHIFT (24U) 04058 #define SIM_SOPT4_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK) 04059 #define SIM_SOPT4_TPM1CLKSEL_MASK (0x2000000U) 04060 #define SIM_SOPT4_TPM1CLKSEL_SHIFT (25U) 04061 #define SIM_SOPT4_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK) 04062 #define SIM_SOPT4_TPM2CLKSEL_MASK (0x4000000U) 04063 #define SIM_SOPT4_TPM2CLKSEL_SHIFT (26U) 04064 #define SIM_SOPT4_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK) 04065 04066 /*! @name SOPT5 - System Options Register 5 */ 04067 #define SIM_SOPT5_UART0TXSRC_MASK (0x3U) 04068 #define SIM_SOPT5_UART0TXSRC_SHIFT (0U) 04069 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK) 04070 #define SIM_SOPT5_UART0RXSRC_MASK (0x4U) 04071 #define SIM_SOPT5_UART0RXSRC_SHIFT (2U) 04072 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK) 04073 #define SIM_SOPT5_UART1TXSRC_MASK (0x30U) 04074 #define SIM_SOPT5_UART1TXSRC_SHIFT (4U) 04075 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK) 04076 #define SIM_SOPT5_UART1RXSRC_MASK (0x40U) 04077 #define SIM_SOPT5_UART1RXSRC_SHIFT (6U) 04078 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK) 04079 #define SIM_SOPT5_UART0ODE_MASK (0x10000U) 04080 #define SIM_SOPT5_UART0ODE_SHIFT (16U) 04081 #define SIM_SOPT5_UART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0ODE_SHIFT)) & SIM_SOPT5_UART0ODE_MASK) 04082 #define SIM_SOPT5_UART1ODE_MASK (0x20000U) 04083 #define SIM_SOPT5_UART1ODE_SHIFT (17U) 04084 #define SIM_SOPT5_UART1ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1ODE_SHIFT)) & SIM_SOPT5_UART1ODE_MASK) 04085 #define SIM_SOPT5_UART2ODE_MASK (0x40000U) 04086 #define SIM_SOPT5_UART2ODE_SHIFT (18U) 04087 #define SIM_SOPT5_UART2ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART2ODE_SHIFT)) & SIM_SOPT5_UART2ODE_MASK) 04088 04089 /*! @name SOPT7 - System Options Register 7 */ 04090 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) 04091 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) 04092 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) 04093 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) 04094 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) 04095 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) 04096 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U) 04097 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U) 04098 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK) 04099 04100 /*! @name SDID - System Device Identification Register */ 04101 #define SIM_SDID_PINID_MASK (0xFU) 04102 #define SIM_SDID_PINID_SHIFT (0U) 04103 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) 04104 #define SIM_SDID_DIEID_MASK (0xF80U) 04105 #define SIM_SDID_DIEID_SHIFT (7U) 04106 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK) 04107 #define SIM_SDID_REVID_MASK (0xF000U) 04108 #define SIM_SDID_REVID_SHIFT (12U) 04109 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) 04110 #define SIM_SDID_SRAMSIZE_MASK (0xF0000U) 04111 #define SIM_SDID_SRAMSIZE_SHIFT (16U) 04112 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK) 04113 #define SIM_SDID_SERIESID_MASK (0xF00000U) 04114 #define SIM_SDID_SERIESID_SHIFT (20U) 04115 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) 04116 #define SIM_SDID_SUBFAMID_MASK (0xF000000U) 04117 #define SIM_SDID_SUBFAMID_SHIFT (24U) 04118 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) 04119 #define SIM_SDID_FAMID_MASK (0xF0000000U) 04120 #define SIM_SDID_FAMID_SHIFT (28U) 04121 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) 04122 04123 /*! @name SCGC4 - System Clock Gating Control Register 4 */ 04124 #define SIM_SCGC4_I2C0_MASK (0x40U) 04125 #define SIM_SCGC4_I2C0_SHIFT (6U) 04126 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) 04127 #define SIM_SCGC4_I2C1_MASK (0x80U) 04128 #define SIM_SCGC4_I2C1_SHIFT (7U) 04129 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK) 04130 #define SIM_SCGC4_UART0_MASK (0x400U) 04131 #define SIM_SCGC4_UART0_SHIFT (10U) 04132 #define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK) 04133 #define SIM_SCGC4_UART1_MASK (0x800U) 04134 #define SIM_SCGC4_UART1_SHIFT (11U) 04135 #define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK) 04136 #define SIM_SCGC4_UART2_MASK (0x1000U) 04137 #define SIM_SCGC4_UART2_SHIFT (12U) 04138 #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK) 04139 #define SIM_SCGC4_USBOTG_MASK (0x40000U) 04140 #define SIM_SCGC4_USBOTG_SHIFT (18U) 04141 #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK) 04142 #define SIM_SCGC4_CMP_MASK (0x80000U) 04143 #define SIM_SCGC4_CMP_SHIFT (19U) 04144 #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK) 04145 #define SIM_SCGC4_SPI0_MASK (0x400000U) 04146 #define SIM_SCGC4_SPI0_SHIFT (22U) 04147 #define SIM_SCGC4_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI0_SHIFT)) & SIM_SCGC4_SPI0_MASK) 04148 #define SIM_SCGC4_SPI1_MASK (0x800000U) 04149 #define SIM_SCGC4_SPI1_SHIFT (23U) 04150 #define SIM_SCGC4_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI1_SHIFT)) & SIM_SCGC4_SPI1_MASK) 04151 04152 /*! @name SCGC5 - System Clock Gating Control Register 5 */ 04153 #define SIM_SCGC5_LPTMR_MASK (0x1U) 04154 #define SIM_SCGC5_LPTMR_SHIFT (0U) 04155 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK) 04156 #define SIM_SCGC5_TSI_MASK (0x20U) 04157 #define SIM_SCGC5_TSI_SHIFT (5U) 04158 #define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK) 04159 #define SIM_SCGC5_PORTA_MASK (0x200U) 04160 #define SIM_SCGC5_PORTA_SHIFT (9U) 04161 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) 04162 #define SIM_SCGC5_PORTB_MASK (0x400U) 04163 #define SIM_SCGC5_PORTB_SHIFT (10U) 04164 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) 04165 #define SIM_SCGC5_PORTC_MASK (0x800U) 04166 #define SIM_SCGC5_PORTC_SHIFT (11U) 04167 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) 04168 #define SIM_SCGC5_PORTD_MASK (0x1000U) 04169 #define SIM_SCGC5_PORTD_SHIFT (12U) 04170 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK) 04171 #define SIM_SCGC5_PORTE_MASK (0x2000U) 04172 #define SIM_SCGC5_PORTE_SHIFT (13U) 04173 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK) 04174 04175 /*! @name SCGC6 - System Clock Gating Control Register 6 */ 04176 #define SIM_SCGC6_FTF_MASK (0x1U) 04177 #define SIM_SCGC6_FTF_SHIFT (0U) 04178 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK) 04179 #define SIM_SCGC6_DMAMUX_MASK (0x2U) 04180 #define SIM_SCGC6_DMAMUX_SHIFT (1U) 04181 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK) 04182 #define SIM_SCGC6_I2S_MASK (0x8000U) 04183 #define SIM_SCGC6_I2S_SHIFT (15U) 04184 #define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK) 04185 #define SIM_SCGC6_PIT_MASK (0x800000U) 04186 #define SIM_SCGC6_PIT_SHIFT (23U) 04187 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK) 04188 #define SIM_SCGC6_TPM0_MASK (0x1000000U) 04189 #define SIM_SCGC6_TPM0_SHIFT (24U) 04190 #define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK) 04191 #define SIM_SCGC6_TPM1_MASK (0x2000000U) 04192 #define SIM_SCGC6_TPM1_SHIFT (25U) 04193 #define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK) 04194 #define SIM_SCGC6_TPM2_MASK (0x4000000U) 04195 #define SIM_SCGC6_TPM2_SHIFT (26U) 04196 #define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK) 04197 #define SIM_SCGC6_ADC0_MASK (0x8000000U) 04198 #define SIM_SCGC6_ADC0_SHIFT (27U) 04199 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) 04200 #define SIM_SCGC6_RTC_MASK (0x20000000U) 04201 #define SIM_SCGC6_RTC_SHIFT (29U) 04202 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK) 04203 #define SIM_SCGC6_DAC0_MASK (0x80000000U) 04204 #define SIM_SCGC6_DAC0_SHIFT (31U) 04205 #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK) 04206 04207 /*! @name SCGC7 - System Clock Gating Control Register 7 */ 04208 #define SIM_SCGC7_DMA_MASK (0x100U) 04209 #define SIM_SCGC7_DMA_SHIFT (8U) 04210 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) 04211 04212 /*! @name CLKDIV1 - System Clock Divider Register 1 */ 04213 #define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U) 04214 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) 04215 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) 04216 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) 04217 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) 04218 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) 04219 04220 /*! @name FCFG1 - Flash Configuration Register 1 */ 04221 #define SIM_FCFG1_FLASHDIS_MASK (0x1U) 04222 #define SIM_FCFG1_FLASHDIS_SHIFT (0U) 04223 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) 04224 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U) 04225 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U) 04226 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) 04227 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U) 04228 #define SIM_FCFG1_PFSIZE_SHIFT (24U) 04229 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) 04230 04231 /*! @name FCFG2 - Flash Configuration Register 2 */ 04232 #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U) 04233 #define SIM_FCFG2_MAXADDR1_SHIFT (16U) 04234 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK) 04235 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) 04236 #define SIM_FCFG2_MAXADDR0_SHIFT (24U) 04237 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) 04238 04239 /*! @name UIDMH - Unique Identification Register Mid-High */ 04240 #define SIM_UIDMH_UID_MASK (0xFFFFU) 04241 #define SIM_UIDMH_UID_SHIFT (0U) 04242 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) 04243 04244 /*! @name UIDML - Unique Identification Register Mid Low */ 04245 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU) 04246 #define SIM_UIDML_UID_SHIFT (0U) 04247 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) 04248 04249 /*! @name UIDL - Unique Identification Register Low */ 04250 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU) 04251 #define SIM_UIDL_UID_SHIFT (0U) 04252 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) 04253 04254 /*! @name COPC - COP Control Register */ 04255 #define SIM_COPC_COPW_MASK (0x1U) 04256 #define SIM_COPC_COPW_SHIFT (0U) 04257 #define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK) 04258 #define SIM_COPC_COPCLKS_MASK (0x2U) 04259 #define SIM_COPC_COPCLKS_SHIFT (1U) 04260 #define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK) 04261 #define SIM_COPC_COPT_MASK (0xCU) 04262 #define SIM_COPC_COPT_SHIFT (2U) 04263 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK) 04264 04265 /*! @name SRVCOP - Service COP */ 04266 #define SIM_SRVCOP_SRVCOP_MASK (0xFFU) 04267 #define SIM_SRVCOP_SRVCOP_SHIFT (0U) 04268 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK) 04269 04270 04271 /*! 04272 * @} 04273 */ /* end of group SIM_Register_Masks */ 04274 04275 04276 /* SIM - Peripheral instance base addresses */ 04277 /** Peripheral SIM base address */ 04278 #define SIM_BASE (0x40047000u) 04279 /** Peripheral SIM base pointer */ 04280 #define SIM ((SIM_Type *)SIM_BASE) 04281 /** Array initializer of SIM peripheral base addresses */ 04282 #define SIM_BASE_ADDRS { SIM_BASE } 04283 /** Array initializer of SIM peripheral base pointers */ 04284 #define SIM_BASE_PTRS { SIM } 04285 04286 /*! 04287 * @} 04288 */ /* end of group SIM_Peripheral_Access_Layer */ 04289 04290 04291 /* ---------------------------------------------------------------------------- 04292 -- SMC Peripheral Access Layer 04293 ---------------------------------------------------------------------------- */ 04294 04295 /*! 04296 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer 04297 * @{ 04298 */ 04299 04300 /** SMC - Register Layout Typedef */ 04301 typedef struct { 04302 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ 04303 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ 04304 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */ 04305 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ 04306 } SMC_Type; 04307 04308 /* ---------------------------------------------------------------------------- 04309 -- SMC Register Masks 04310 ---------------------------------------------------------------------------- */ 04311 04312 /*! 04313 * @addtogroup SMC_Register_Masks SMC Register Masks 04314 * @{ 04315 */ 04316 04317 /*! @name PMPROT - Power Mode Protection register */ 04318 #define SMC_PMPROT_AVLLS_MASK (0x2U) 04319 #define SMC_PMPROT_AVLLS_SHIFT (1U) 04320 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) 04321 #define SMC_PMPROT_ALLS_MASK (0x8U) 04322 #define SMC_PMPROT_ALLS_SHIFT (3U) 04323 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) 04324 #define SMC_PMPROT_AVLP_MASK (0x20U) 04325 #define SMC_PMPROT_AVLP_SHIFT (5U) 04326 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) 04327 04328 /*! @name PMCTRL - Power Mode Control register */ 04329 #define SMC_PMCTRL_STOPM_MASK (0x7U) 04330 #define SMC_PMCTRL_STOPM_SHIFT (0U) 04331 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) 04332 #define SMC_PMCTRL_STOPA_MASK (0x8U) 04333 #define SMC_PMCTRL_STOPA_SHIFT (3U) 04334 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) 04335 #define SMC_PMCTRL_RUNM_MASK (0x60U) 04336 #define SMC_PMCTRL_RUNM_SHIFT (5U) 04337 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) 04338 04339 /*! @name STOPCTRL - Stop Control Register */ 04340 #define SMC_STOPCTRL_VLLSM_MASK (0x7U) 04341 #define SMC_STOPCTRL_VLLSM_SHIFT (0U) 04342 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK) 04343 #define SMC_STOPCTRL_PORPO_MASK (0x20U) 04344 #define SMC_STOPCTRL_PORPO_SHIFT (5U) 04345 #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK) 04346 #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U) 04347 #define SMC_STOPCTRL_PSTOPO_SHIFT (6U) 04348 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK) 04349 04350 /*! @name PMSTAT - Power Mode Status register */ 04351 #define SMC_PMSTAT_PMSTAT_MASK (0x7FU) 04352 #define SMC_PMSTAT_PMSTAT_SHIFT (0U) 04353 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) 04354 04355 04356 /*! 04357 * @} 04358 */ /* end of group SMC_Register_Masks */ 04359 04360 04361 /* SMC - Peripheral instance base addresses */ 04362 /** Peripheral SMC base address */ 04363 #define SMC_BASE (0x4007E000u) 04364 /** Peripheral SMC base pointer */ 04365 #define SMC ((SMC_Type *)SMC_BASE) 04366 /** Array initializer of SMC peripheral base addresses */ 04367 #define SMC_BASE_ADDRS { SMC_BASE } 04368 /** Array initializer of SMC peripheral base pointers */ 04369 #define SMC_BASE_PTRS { SMC } 04370 04371 /*! 04372 * @} 04373 */ /* end of group SMC_Peripheral_Access_Layer */ 04374 04375 04376 /* ---------------------------------------------------------------------------- 04377 -- SPI Peripheral Access Layer 04378 ---------------------------------------------------------------------------- */ 04379 04380 /*! 04381 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 04382 * @{ 04383 */ 04384 04385 /** SPI - Register Layout Typedef */ 04386 typedef struct { 04387 __IO uint8_t S; /**< SPI Status Register, offset: 0x0 */ 04388 __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */ 04389 __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */ 04390 __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */ 04391 __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */ 04392 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */ 04393 __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */ 04394 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */ 04395 uint8_t RESERVED_0[2]; 04396 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */ 04397 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */ 04398 } SPI_Type; 04399 04400 /* ---------------------------------------------------------------------------- 04401 -- SPI Register Masks 04402 ---------------------------------------------------------------------------- */ 04403 04404 /*! 04405 * @addtogroup SPI_Register_Masks SPI Register Masks 04406 * @{ 04407 */ 04408 04409 /*! @name S - SPI Status Register */ 04410 #define SPI_S_RFIFOEF_MASK (0x1U) 04411 #define SPI_S_RFIFOEF_SHIFT (0U) 04412 #define SPI_S_RFIFOEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RFIFOEF_SHIFT)) & SPI_S_RFIFOEF_MASK) 04413 #define SPI_S_TXFULLF_MASK (0x2U) 04414 #define SPI_S_TXFULLF_SHIFT (1U) 04415 #define SPI_S_TXFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TXFULLF_SHIFT)) & SPI_S_TXFULLF_MASK) 04416 #define SPI_S_TNEAREF_MASK (0x4U) 04417 #define SPI_S_TNEAREF_SHIFT (2U) 04418 #define SPI_S_TNEAREF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TNEAREF_SHIFT)) & SPI_S_TNEAREF_MASK) 04419 #define SPI_S_RNFULLF_MASK (0x8U) 04420 #define SPI_S_RNFULLF_SHIFT (3U) 04421 #define SPI_S_RNFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RNFULLF_SHIFT)) & SPI_S_RNFULLF_MASK) 04422 #define SPI_S_MODF_MASK (0x10U) 04423 #define SPI_S_MODF_SHIFT (4U) 04424 #define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK) 04425 #define SPI_S_SPTEF_MASK (0x20U) 04426 #define SPI_S_SPTEF_SHIFT (5U) 04427 #define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK) 04428 #define SPI_S_SPMF_MASK (0x40U) 04429 #define SPI_S_SPMF_SHIFT (6U) 04430 #define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK) 04431 #define SPI_S_SPRF_MASK (0x80U) 04432 #define SPI_S_SPRF_SHIFT (7U) 04433 #define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK) 04434 04435 /*! @name BR - SPI Baud Rate Register */ 04436 #define SPI_BR_SPR_MASK (0xFU) 04437 #define SPI_BR_SPR_SHIFT (0U) 04438 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK) 04439 #define SPI_BR_SPPR_MASK (0x70U) 04440 #define SPI_BR_SPPR_SHIFT (4U) 04441 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK) 04442 04443 /*! @name C2 - SPI Control Register 2 */ 04444 #define SPI_C2_SPC0_MASK (0x1U) 04445 #define SPI_C2_SPC0_SHIFT (0U) 04446 #define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK) 04447 #define SPI_C2_SPISWAI_MASK (0x2U) 04448 #define SPI_C2_SPISWAI_SHIFT (1U) 04449 #define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK) 04450 #define SPI_C2_RXDMAE_MASK (0x4U) 04451 #define SPI_C2_RXDMAE_SHIFT (2U) 04452 #define SPI_C2_RXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_RXDMAE_SHIFT)) & SPI_C2_RXDMAE_MASK) 04453 #define SPI_C2_BIDIROE_MASK (0x8U) 04454 #define SPI_C2_BIDIROE_SHIFT (3U) 04455 #define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK) 04456 #define SPI_C2_MODFEN_MASK (0x10U) 04457 #define SPI_C2_MODFEN_SHIFT (4U) 04458 #define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK) 04459 #define SPI_C2_TXDMAE_MASK (0x20U) 04460 #define SPI_C2_TXDMAE_SHIFT (5U) 04461 #define SPI_C2_TXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_TXDMAE_SHIFT)) & SPI_C2_TXDMAE_MASK) 04462 #define SPI_C2_SPIMODE_MASK (0x40U) 04463 #define SPI_C2_SPIMODE_SHIFT (6U) 04464 #define SPI_C2_SPIMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPIMODE_SHIFT)) & SPI_C2_SPIMODE_MASK) 04465 #define SPI_C2_SPMIE_MASK (0x80U) 04466 #define SPI_C2_SPMIE_SHIFT (7U) 04467 #define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK) 04468 04469 /*! @name C1 - SPI Control Register 1 */ 04470 #define SPI_C1_LSBFE_MASK (0x1U) 04471 #define SPI_C1_LSBFE_SHIFT (0U) 04472 #define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK) 04473 #define SPI_C1_SSOE_MASK (0x2U) 04474 #define SPI_C1_SSOE_SHIFT (1U) 04475 #define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK) 04476 #define SPI_C1_CPHA_MASK (0x4U) 04477 #define SPI_C1_CPHA_SHIFT (2U) 04478 #define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK) 04479 #define SPI_C1_CPOL_MASK (0x8U) 04480 #define SPI_C1_CPOL_SHIFT (3U) 04481 #define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK) 04482 #define SPI_C1_MSTR_MASK (0x10U) 04483 #define SPI_C1_MSTR_SHIFT (4U) 04484 #define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK) 04485 #define SPI_C1_SPTIE_MASK (0x20U) 04486 #define SPI_C1_SPTIE_SHIFT (5U) 04487 #define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK) 04488 #define SPI_C1_SPE_MASK (0x40U) 04489 #define SPI_C1_SPE_SHIFT (6U) 04490 #define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK) 04491 #define SPI_C1_SPIE_MASK (0x80U) 04492 #define SPI_C1_SPIE_SHIFT (7U) 04493 #define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK) 04494 04495 /*! @name ML - SPI Match Register low */ 04496 #define SPI_ML_Bits_MASK (0xFFU) 04497 #define SPI_ML_Bits_SHIFT (0U) 04498 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_ML_Bits_SHIFT)) & SPI_ML_Bits_MASK) 04499 04500 /*! @name MH - SPI match register high */ 04501 #define SPI_MH_Bits_MASK (0xFFU) 04502 #define SPI_MH_Bits_SHIFT (0U) 04503 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_MH_Bits_SHIFT)) & SPI_MH_Bits_MASK) 04504 04505 /*! @name DL - SPI Data Register low */ 04506 #define SPI_DL_Bits_MASK (0xFFU) 04507 #define SPI_DL_Bits_SHIFT (0U) 04508 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DL_Bits_SHIFT)) & SPI_DL_Bits_MASK) 04509 04510 /*! @name DH - SPI data register high */ 04511 #define SPI_DH_Bits_MASK (0xFFU) 04512 #define SPI_DH_Bits_SHIFT (0U) 04513 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DH_Bits_SHIFT)) & SPI_DH_Bits_MASK) 04514 04515 /*! @name CI - SPI clear interrupt register */ 04516 #define SPI_CI_SPRFCI_MASK (0x1U) 04517 #define SPI_CI_SPRFCI_SHIFT (0U) 04518 #define SPI_CI_SPRFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPRFCI_SHIFT)) & SPI_CI_SPRFCI_MASK) 04519 #define SPI_CI_SPTEFCI_MASK (0x2U) 04520 #define SPI_CI_SPTEFCI_SHIFT (1U) 04521 #define SPI_CI_SPTEFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPTEFCI_SHIFT)) & SPI_CI_SPTEFCI_MASK) 04522 #define SPI_CI_RNFULLFCI_MASK (0x4U) 04523 #define SPI_CI_RNFULLFCI_SHIFT (2U) 04524 #define SPI_CI_RNFULLFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RNFULLFCI_SHIFT)) & SPI_CI_RNFULLFCI_MASK) 04525 #define SPI_CI_TNEAREFCI_MASK (0x8U) 04526 #define SPI_CI_TNEAREFCI_SHIFT (3U) 04527 #define SPI_CI_TNEAREFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TNEAREFCI_SHIFT)) & SPI_CI_TNEAREFCI_MASK) 04528 #define SPI_CI_RXFOF_MASK (0x10U) 04529 #define SPI_CI_RXFOF_SHIFT (4U) 04530 #define SPI_CI_RXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFOF_SHIFT)) & SPI_CI_RXFOF_MASK) 04531 #define SPI_CI_TXFOF_MASK (0x20U) 04532 #define SPI_CI_TXFOF_SHIFT (5U) 04533 #define SPI_CI_TXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFOF_SHIFT)) & SPI_CI_TXFOF_MASK) 04534 #define SPI_CI_RXFERR_MASK (0x40U) 04535 #define SPI_CI_RXFERR_SHIFT (6U) 04536 #define SPI_CI_RXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFERR_SHIFT)) & SPI_CI_RXFERR_MASK) 04537 #define SPI_CI_TXFERR_MASK (0x80U) 04538 #define SPI_CI_TXFERR_SHIFT (7U) 04539 #define SPI_CI_TXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFERR_SHIFT)) & SPI_CI_TXFERR_MASK) 04540 04541 /*! @name C3 - SPI control register 3 */ 04542 #define SPI_C3_FIFOMODE_MASK (0x1U) 04543 #define SPI_C3_FIFOMODE_SHIFT (0U) 04544 #define SPI_C3_FIFOMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_FIFOMODE_SHIFT)) & SPI_C3_FIFOMODE_MASK) 04545 #define SPI_C3_RNFULLIEN_MASK (0x2U) 04546 #define SPI_C3_RNFULLIEN_SHIFT (1U) 04547 #define SPI_C3_RNFULLIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLIEN_SHIFT)) & SPI_C3_RNFULLIEN_MASK) 04548 #define SPI_C3_TNEARIEN_MASK (0x4U) 04549 #define SPI_C3_TNEARIEN_SHIFT (2U) 04550 #define SPI_C3_TNEARIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEARIEN_SHIFT)) & SPI_C3_TNEARIEN_MASK) 04551 #define SPI_C3_INTCLR_MASK (0x8U) 04552 #define SPI_C3_INTCLR_SHIFT (3U) 04553 #define SPI_C3_INTCLR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_INTCLR_SHIFT)) & SPI_C3_INTCLR_MASK) 04554 #define SPI_C3_RNFULLF_MARK_MASK (0x10U) 04555 #define SPI_C3_RNFULLF_MARK_SHIFT (4U) 04556 #define SPI_C3_RNFULLF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLF_MARK_SHIFT)) & SPI_C3_RNFULLF_MARK_MASK) 04557 #define SPI_C3_TNEAREF_MARK_MASK (0x20U) 04558 #define SPI_C3_TNEAREF_MARK_SHIFT (5U) 04559 #define SPI_C3_TNEAREF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEAREF_MARK_SHIFT)) & SPI_C3_TNEAREF_MARK_MASK) 04560 04561 04562 /*! 04563 * @} 04564 */ /* end of group SPI_Register_Masks */ 04565 04566 04567 /* SPI - Peripheral instance base addresses */ 04568 /** Peripheral SPI0 base address */ 04569 #define SPI0_BASE (0x40076000u) 04570 /** Peripheral SPI0 base pointer */ 04571 #define SPI0 ((SPI_Type *)SPI0_BASE) 04572 /** Peripheral SPI1 base address */ 04573 #define SPI1_BASE (0x40077000u) 04574 /** Peripheral SPI1 base pointer */ 04575 #define SPI1 ((SPI_Type *)SPI1_BASE) 04576 /** Array initializer of SPI peripheral base addresses */ 04577 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } 04578 /** Array initializer of SPI peripheral base pointers */ 04579 #define SPI_BASE_PTRS { SPI0, SPI1 } 04580 /** Interrupt vectors for the SPI peripheral type */ 04581 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } 04582 04583 /*! 04584 * @} 04585 */ /* end of group SPI_Peripheral_Access_Layer */ 04586 04587 04588 /* ---------------------------------------------------------------------------- 04589 -- TPM Peripheral Access Layer 04590 ---------------------------------------------------------------------------- */ 04591 04592 /*! 04593 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer 04594 * @{ 04595 */ 04596 04597 /** TPM - Register Layout Typedef */ 04598 typedef struct { 04599 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */ 04600 __IO uint32_t CNT; /**< Counter, offset: 0x4 */ 04601 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ 04602 struct { /* offset: 0xC, array step: 0x8 */ 04603 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ 04604 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ 04605 } CONTROLS[6]; 04606 uint8_t RESERVED_0[20]; 04607 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ 04608 uint8_t RESERVED_1[48]; 04609 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ 04610 } TPM_Type; 04611 04612 /* ---------------------------------------------------------------------------- 04613 -- TPM Register Masks 04614 ---------------------------------------------------------------------------- */ 04615 04616 /*! 04617 * @addtogroup TPM_Register_Masks TPM Register Masks 04618 * @{ 04619 */ 04620 04621 /*! @name SC - Status and Control */ 04622 #define TPM_SC_PS_MASK (0x7U) 04623 #define TPM_SC_PS_SHIFT (0U) 04624 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK) 04625 #define TPM_SC_CMOD_MASK (0x18U) 04626 #define TPM_SC_CMOD_SHIFT (3U) 04627 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK) 04628 #define TPM_SC_CPWMS_MASK (0x20U) 04629 #define TPM_SC_CPWMS_SHIFT (5U) 04630 #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK) 04631 #define TPM_SC_TOIE_MASK (0x40U) 04632 #define TPM_SC_TOIE_SHIFT (6U) 04633 #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK) 04634 #define TPM_SC_TOF_MASK (0x80U) 04635 #define TPM_SC_TOF_SHIFT (7U) 04636 #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK) 04637 #define TPM_SC_DMA_MASK (0x100U) 04638 #define TPM_SC_DMA_SHIFT (8U) 04639 #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK) 04640 04641 /*! @name CNT - Counter */ 04642 #define TPM_CNT_COUNT_MASK (0xFFFFU) 04643 #define TPM_CNT_COUNT_SHIFT (0U) 04644 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK) 04645 04646 /*! @name MOD - Modulo */ 04647 #define TPM_MOD_MOD_MASK (0xFFFFU) 04648 #define TPM_MOD_MOD_SHIFT (0U) 04649 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK) 04650 04651 /*! @name CnSC - Channel (n) Status and Control */ 04652 #define TPM_CnSC_DMA_MASK (0x1U) 04653 #define TPM_CnSC_DMA_SHIFT (0U) 04654 #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK) 04655 #define TPM_CnSC_ELSA_MASK (0x4U) 04656 #define TPM_CnSC_ELSA_SHIFT (2U) 04657 #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK) 04658 #define TPM_CnSC_ELSB_MASK (0x8U) 04659 #define TPM_CnSC_ELSB_SHIFT (3U) 04660 #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK) 04661 #define TPM_CnSC_MSA_MASK (0x10U) 04662 #define TPM_CnSC_MSA_SHIFT (4U) 04663 #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK) 04664 #define TPM_CnSC_MSB_MASK (0x20U) 04665 #define TPM_CnSC_MSB_SHIFT (5U) 04666 #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK) 04667 #define TPM_CnSC_CHIE_MASK (0x40U) 04668 #define TPM_CnSC_CHIE_SHIFT (6U) 04669 #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK) 04670 #define TPM_CnSC_CHF_MASK (0x80U) 04671 #define TPM_CnSC_CHF_SHIFT (7U) 04672 #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK) 04673 04674 /* The count of TPM_CnSC */ 04675 #define TPM_CnSC_COUNT (6U) 04676 04677 /*! @name CnV - Channel (n) Value */ 04678 #define TPM_CnV_VAL_MASK (0xFFFFU) 04679 #define TPM_CnV_VAL_SHIFT (0U) 04680 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK) 04681 04682 /* The count of TPM_CnV */ 04683 #define TPM_CnV_COUNT (6U) 04684 04685 /*! @name STATUS - Capture and Compare Status */ 04686 #define TPM_STATUS_CH0F_MASK (0x1U) 04687 #define TPM_STATUS_CH0F_SHIFT (0U) 04688 #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK) 04689 #define TPM_STATUS_CH1F_MASK (0x2U) 04690 #define TPM_STATUS_CH1F_SHIFT (1U) 04691 #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK) 04692 #define TPM_STATUS_CH2F_MASK (0x4U) 04693 #define TPM_STATUS_CH2F_SHIFT (2U) 04694 #define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK) 04695 #define TPM_STATUS_CH3F_MASK (0x8U) 04696 #define TPM_STATUS_CH3F_SHIFT (3U) 04697 #define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK) 04698 #define TPM_STATUS_CH4F_MASK (0x10U) 04699 #define TPM_STATUS_CH4F_SHIFT (4U) 04700 #define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK) 04701 #define TPM_STATUS_CH5F_MASK (0x20U) 04702 #define TPM_STATUS_CH5F_SHIFT (5U) 04703 #define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK) 04704 #define TPM_STATUS_TOF_MASK (0x100U) 04705 #define TPM_STATUS_TOF_SHIFT (8U) 04706 #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK) 04707 04708 /*! @name CONF - Configuration */ 04709 #define TPM_CONF_DOZEEN_MASK (0x20U) 04710 #define TPM_CONF_DOZEEN_SHIFT (5U) 04711 #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK) 04712 #define TPM_CONF_DBGMODE_MASK (0xC0U) 04713 #define TPM_CONF_DBGMODE_SHIFT (6U) 04714 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK) 04715 #define TPM_CONF_GTBEEN_MASK (0x200U) 04716 #define TPM_CONF_GTBEEN_SHIFT (9U) 04717 #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK) 04718 #define TPM_CONF_CSOT_MASK (0x10000U) 04719 #define TPM_CONF_CSOT_SHIFT (16U) 04720 #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK) 04721 #define TPM_CONF_CSOO_MASK (0x20000U) 04722 #define TPM_CONF_CSOO_SHIFT (17U) 04723 #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK) 04724 #define TPM_CONF_CROT_MASK (0x40000U) 04725 #define TPM_CONF_CROT_SHIFT (18U) 04726 #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK) 04727 #define TPM_CONF_TRGSEL_MASK (0xF000000U) 04728 #define TPM_CONF_TRGSEL_SHIFT (24U) 04729 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK) 04730 04731 04732 /*! 04733 * @} 04734 */ /* end of group TPM_Register_Masks */ 04735 04736 04737 /* TPM - Peripheral instance base addresses */ 04738 /** Peripheral TPM0 base address */ 04739 #define TPM0_BASE (0x40038000u) 04740 /** Peripheral TPM0 base pointer */ 04741 #define TPM0 ((TPM_Type *)TPM0_BASE) 04742 /** Peripheral TPM1 base address */ 04743 #define TPM1_BASE (0x40039000u) 04744 /** Peripheral TPM1 base pointer */ 04745 #define TPM1 ((TPM_Type *)TPM1_BASE) 04746 /** Peripheral TPM2 base address */ 04747 #define TPM2_BASE (0x4003A000u) 04748 /** Peripheral TPM2 base pointer */ 04749 #define TPM2 ((TPM_Type *)TPM2_BASE) 04750 /** Array initializer of TPM peripheral base addresses */ 04751 #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE } 04752 /** Array initializer of TPM peripheral base pointers */ 04753 #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 } 04754 /** Interrupt vectors for the TPM peripheral type */ 04755 #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn } 04756 04757 /*! 04758 * @} 04759 */ /* end of group TPM_Peripheral_Access_Layer */ 04760 04761 04762 /* ---------------------------------------------------------------------------- 04763 -- TSI Peripheral Access Layer 04764 ---------------------------------------------------------------------------- */ 04765 04766 /*! 04767 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer 04768 * @{ 04769 */ 04770 04771 /** TSI - Register Layout Typedef */ 04772 typedef struct { 04773 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */ 04774 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */ 04775 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ 04776 } TSI_Type; 04777 04778 /* ---------------------------------------------------------------------------- 04779 -- TSI Register Masks 04780 ---------------------------------------------------------------------------- */ 04781 04782 /*! 04783 * @addtogroup TSI_Register_Masks TSI Register Masks 04784 * @{ 04785 */ 04786 04787 /*! @name GENCS - TSI General Control and Status Register */ 04788 #define TSI_GENCS_CURSW_MASK (0x2U) 04789 #define TSI_GENCS_CURSW_SHIFT (1U) 04790 #define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK) 04791 #define TSI_GENCS_EOSF_MASK (0x4U) 04792 #define TSI_GENCS_EOSF_SHIFT (2U) 04793 #define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK) 04794 #define TSI_GENCS_SCNIP_MASK (0x8U) 04795 #define TSI_GENCS_SCNIP_SHIFT (3U) 04796 #define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK) 04797 #define TSI_GENCS_STM_MASK (0x10U) 04798 #define TSI_GENCS_STM_SHIFT (4U) 04799 #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK) 04800 #define TSI_GENCS_STPE_MASK (0x20U) 04801 #define TSI_GENCS_STPE_SHIFT (5U) 04802 #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK) 04803 #define TSI_GENCS_TSIIEN_MASK (0x40U) 04804 #define TSI_GENCS_TSIIEN_SHIFT (6U) 04805 #define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK) 04806 #define TSI_GENCS_TSIEN_MASK (0x80U) 04807 #define TSI_GENCS_TSIEN_SHIFT (7U) 04808 #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK) 04809 #define TSI_GENCS_NSCN_MASK (0x1F00U) 04810 #define TSI_GENCS_NSCN_SHIFT (8U) 04811 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK) 04812 #define TSI_GENCS_PS_MASK (0xE000U) 04813 #define TSI_GENCS_PS_SHIFT (13U) 04814 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK) 04815 #define TSI_GENCS_EXTCHRG_MASK (0x70000U) 04816 #define TSI_GENCS_EXTCHRG_SHIFT (16U) 04817 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK) 04818 #define TSI_GENCS_DVOLT_MASK (0x180000U) 04819 #define TSI_GENCS_DVOLT_SHIFT (19U) 04820 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK) 04821 #define TSI_GENCS_REFCHRG_MASK (0xE00000U) 04822 #define TSI_GENCS_REFCHRG_SHIFT (21U) 04823 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK) 04824 #define TSI_GENCS_MODE_MASK (0xF000000U) 04825 #define TSI_GENCS_MODE_SHIFT (24U) 04826 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK) 04827 #define TSI_GENCS_ESOR_MASK (0x10000000U) 04828 #define TSI_GENCS_ESOR_SHIFT (28U) 04829 #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK) 04830 #define TSI_GENCS_OUTRGF_MASK (0x80000000U) 04831 #define TSI_GENCS_OUTRGF_SHIFT (31U) 04832 #define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK) 04833 04834 /*! @name DATA - TSI DATA Register */ 04835 #define TSI_DATA_TSICNT_MASK (0xFFFFU) 04836 #define TSI_DATA_TSICNT_SHIFT (0U) 04837 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK) 04838 #define TSI_DATA_SWTS_MASK (0x400000U) 04839 #define TSI_DATA_SWTS_SHIFT (22U) 04840 #define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK) 04841 #define TSI_DATA_DMAEN_MASK (0x800000U) 04842 #define TSI_DATA_DMAEN_SHIFT (23U) 04843 #define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK) 04844 #define TSI_DATA_TSICH_MASK (0xF0000000U) 04845 #define TSI_DATA_TSICH_SHIFT (28U) 04846 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK) 04847 04848 /*! @name TSHD - TSI Threshold Register */ 04849 #define TSI_TSHD_THRESL_MASK (0xFFFFU) 04850 #define TSI_TSHD_THRESL_SHIFT (0U) 04851 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK) 04852 #define TSI_TSHD_THRESH_MASK (0xFFFF0000U) 04853 #define TSI_TSHD_THRESH_SHIFT (16U) 04854 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK) 04855 04856 04857 /*! 04858 * @} 04859 */ /* end of group TSI_Register_Masks */ 04860 04861 04862 /* TSI - Peripheral instance base addresses */ 04863 /** Peripheral TSI0 base address */ 04864 #define TSI0_BASE (0x40045000u) 04865 /** Peripheral TSI0 base pointer */ 04866 #define TSI0 ((TSI_Type *)TSI0_BASE) 04867 /** Array initializer of TSI peripheral base addresses */ 04868 #define TSI_BASE_ADDRS { TSI0_BASE } 04869 /** Array initializer of TSI peripheral base pointers */ 04870 #define TSI_BASE_PTRS { TSI0 } 04871 /** Interrupt vectors for the TSI peripheral type */ 04872 #define TSI_IRQS { TSI0_IRQn } 04873 04874 /*! 04875 * @} 04876 */ /* end of group TSI_Peripheral_Access_Layer */ 04877 04878 04879 /* ---------------------------------------------------------------------------- 04880 -- UART Peripheral Access Layer 04881 ---------------------------------------------------------------------------- */ 04882 04883 /*! 04884 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer 04885 * @{ 04886 */ 04887 04888 /** UART - Register Layout Typedef */ 04889 typedef struct { 04890 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */ 04891 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */ 04892 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 04893 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 04894 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 04895 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 04896 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 04897 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 04898 __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */ 04899 } UART_Type; 04900 04901 /* ---------------------------------------------------------------------------- 04902 -- UART Register Masks 04903 ---------------------------------------------------------------------------- */ 04904 04905 /*! 04906 * @addtogroup UART_Register_Masks UART Register Masks 04907 * @{ 04908 */ 04909 04910 /*! @name BDH - UART Baud Rate Register: High */ 04911 #define UART_BDH_SBR_MASK (0x1FU) 04912 #define UART_BDH_SBR_SHIFT (0U) 04913 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) 04914 #define UART_BDH_SBNS_MASK (0x20U) 04915 #define UART_BDH_SBNS_SHIFT (5U) 04916 #define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK) 04917 #define UART_BDH_RXEDGIE_MASK (0x40U) 04918 #define UART_BDH_RXEDGIE_SHIFT (6U) 04919 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) 04920 #define UART_BDH_LBKDIE_MASK (0x80U) 04921 #define UART_BDH_LBKDIE_SHIFT (7U) 04922 #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK) 04923 04924 /*! @name BDL - UART Baud Rate Register: Low */ 04925 #define UART_BDL_SBR_MASK (0xFFU) 04926 #define UART_BDL_SBR_SHIFT (0U) 04927 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) 04928 04929 /*! @name C1 - UART Control Register 1 */ 04930 #define UART_C1_PT_MASK (0x1U) 04931 #define UART_C1_PT_SHIFT (0U) 04932 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) 04933 #define UART_C1_PE_MASK (0x2U) 04934 #define UART_C1_PE_SHIFT (1U) 04935 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) 04936 #define UART_C1_ILT_MASK (0x4U) 04937 #define UART_C1_ILT_SHIFT (2U) 04938 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) 04939 #define UART_C1_WAKE_MASK (0x8U) 04940 #define UART_C1_WAKE_SHIFT (3U) 04941 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) 04942 #define UART_C1_M_MASK (0x10U) 04943 #define UART_C1_M_SHIFT (4U) 04944 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) 04945 #define UART_C1_RSRC_MASK (0x20U) 04946 #define UART_C1_RSRC_SHIFT (5U) 04947 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) 04948 #define UART_C1_UARTSWAI_MASK (0x40U) 04949 #define UART_C1_UARTSWAI_SHIFT (6U) 04950 #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK) 04951 #define UART_C1_LOOPS_MASK (0x80U) 04952 #define UART_C1_LOOPS_SHIFT (7U) 04953 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) 04954 04955 /*! @name C2 - UART Control Register 2 */ 04956 #define UART_C2_SBK_MASK (0x1U) 04957 #define UART_C2_SBK_SHIFT (0U) 04958 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) 04959 #define UART_C2_RWU_MASK (0x2U) 04960 #define UART_C2_RWU_SHIFT (1U) 04961 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) 04962 #define UART_C2_RE_MASK (0x4U) 04963 #define UART_C2_RE_SHIFT (2U) 04964 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) 04965 #define UART_C2_TE_MASK (0x8U) 04966 #define UART_C2_TE_SHIFT (3U) 04967 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) 04968 #define UART_C2_ILIE_MASK (0x10U) 04969 #define UART_C2_ILIE_SHIFT (4U) 04970 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) 04971 #define UART_C2_RIE_MASK (0x20U) 04972 #define UART_C2_RIE_SHIFT (5U) 04973 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) 04974 #define UART_C2_TCIE_MASK (0x40U) 04975 #define UART_C2_TCIE_SHIFT (6U) 04976 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) 04977 #define UART_C2_TIE_MASK (0x80U) 04978 #define UART_C2_TIE_SHIFT (7U) 04979 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) 04980 04981 /*! @name S1 - UART Status Register 1 */ 04982 #define UART_S1_PF_MASK (0x1U) 04983 #define UART_S1_PF_SHIFT (0U) 04984 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) 04985 #define UART_S1_FE_MASK (0x2U) 04986 #define UART_S1_FE_SHIFT (1U) 04987 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) 04988 #define UART_S1_NF_MASK (0x4U) 04989 #define UART_S1_NF_SHIFT (2U) 04990 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) 04991 #define UART_S1_OR_MASK (0x8U) 04992 #define UART_S1_OR_SHIFT (3U) 04993 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) 04994 #define UART_S1_IDLE_MASK (0x10U) 04995 #define UART_S1_IDLE_SHIFT (4U) 04996 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) 04997 #define UART_S1_RDRF_MASK (0x20U) 04998 #define UART_S1_RDRF_SHIFT (5U) 04999 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) 05000 #define UART_S1_TC_MASK (0x40U) 05001 #define UART_S1_TC_SHIFT (6U) 05002 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) 05003 #define UART_S1_TDRE_MASK (0x80U) 05004 #define UART_S1_TDRE_SHIFT (7U) 05005 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) 05006 05007 /*! @name S2 - UART Status Register 2 */ 05008 #define UART_S2_RAF_MASK (0x1U) 05009 #define UART_S2_RAF_SHIFT (0U) 05010 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) 05011 #define UART_S2_LBKDE_MASK (0x2U) 05012 #define UART_S2_LBKDE_SHIFT (1U) 05013 #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK) 05014 #define UART_S2_BRK13_MASK (0x4U) 05015 #define UART_S2_BRK13_SHIFT (2U) 05016 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) 05017 #define UART_S2_RWUID_MASK (0x8U) 05018 #define UART_S2_RWUID_SHIFT (3U) 05019 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) 05020 #define UART_S2_RXINV_MASK (0x10U) 05021 #define UART_S2_RXINV_SHIFT (4U) 05022 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) 05023 #define UART_S2_RXEDGIF_MASK (0x40U) 05024 #define UART_S2_RXEDGIF_SHIFT (6U) 05025 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) 05026 #define UART_S2_LBKDIF_MASK (0x80U) 05027 #define UART_S2_LBKDIF_SHIFT (7U) 05028 #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK) 05029 05030 /*! @name C3 - UART Control Register 3 */ 05031 #define UART_C3_PEIE_MASK (0x1U) 05032 #define UART_C3_PEIE_SHIFT (0U) 05033 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) 05034 #define UART_C3_FEIE_MASK (0x2U) 05035 #define UART_C3_FEIE_SHIFT (1U) 05036 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) 05037 #define UART_C3_NEIE_MASK (0x4U) 05038 #define UART_C3_NEIE_SHIFT (2U) 05039 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) 05040 #define UART_C3_ORIE_MASK (0x8U) 05041 #define UART_C3_ORIE_SHIFT (3U) 05042 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) 05043 #define UART_C3_TXINV_MASK (0x10U) 05044 #define UART_C3_TXINV_SHIFT (4U) 05045 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) 05046 #define UART_C3_TXDIR_MASK (0x20U) 05047 #define UART_C3_TXDIR_SHIFT (5U) 05048 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) 05049 #define UART_C3_T8_MASK (0x40U) 05050 #define UART_C3_T8_SHIFT (6U) 05051 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) 05052 #define UART_C3_R8_MASK (0x80U) 05053 #define UART_C3_R8_SHIFT (7U) 05054 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) 05055 05056 /*! @name D - UART Data Register */ 05057 #define UART_D_R0T0_MASK (0x1U) 05058 #define UART_D_R0T0_SHIFT (0U) 05059 #define UART_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R0T0_SHIFT)) & UART_D_R0T0_MASK) 05060 #define UART_D_R1T1_MASK (0x2U) 05061 #define UART_D_R1T1_SHIFT (1U) 05062 #define UART_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R1T1_SHIFT)) & UART_D_R1T1_MASK) 05063 #define UART_D_R2T2_MASK (0x4U) 05064 #define UART_D_R2T2_SHIFT (2U) 05065 #define UART_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R2T2_SHIFT)) & UART_D_R2T2_MASK) 05066 #define UART_D_R3T3_MASK (0x8U) 05067 #define UART_D_R3T3_SHIFT (3U) 05068 #define UART_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R3T3_SHIFT)) & UART_D_R3T3_MASK) 05069 #define UART_D_R4T4_MASK (0x10U) 05070 #define UART_D_R4T4_SHIFT (4U) 05071 #define UART_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R4T4_SHIFT)) & UART_D_R4T4_MASK) 05072 #define UART_D_R5T5_MASK (0x20U) 05073 #define UART_D_R5T5_SHIFT (5U) 05074 #define UART_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R5T5_SHIFT)) & UART_D_R5T5_MASK) 05075 #define UART_D_R6T6_MASK (0x40U) 05076 #define UART_D_R6T6_SHIFT (6U) 05077 #define UART_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R6T6_SHIFT)) & UART_D_R6T6_MASK) 05078 #define UART_D_R7T7_MASK (0x80U) 05079 #define UART_D_R7T7_SHIFT (7U) 05080 #define UART_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R7T7_SHIFT)) & UART_D_R7T7_MASK) 05081 05082 /*! @name C4 - UART Control Register 4 */ 05083 #define UART_C4_RDMAS_MASK (0x20U) 05084 #define UART_C4_RDMAS_SHIFT (5U) 05085 #define UART_C4_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_RDMAS_SHIFT)) & UART_C4_RDMAS_MASK) 05086 #define UART_C4_TDMAS_MASK (0x80U) 05087 #define UART_C4_TDMAS_SHIFT (7U) 05088 #define UART_C4_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_TDMAS_SHIFT)) & UART_C4_TDMAS_MASK) 05089 05090 05091 /*! 05092 * @} 05093 */ /* end of group UART_Register_Masks */ 05094 05095 05096 /* UART - Peripheral instance base addresses */ 05097 /** Peripheral UART1 base address */ 05098 #define UART1_BASE (0x4006B000u) 05099 /** Peripheral UART1 base pointer */ 05100 #define UART1 ((UART_Type *)UART1_BASE) 05101 /** Peripheral UART2 base address */ 05102 #define UART2_BASE (0x4006C000u) 05103 /** Peripheral UART2 base pointer */ 05104 #define UART2 ((UART_Type *)UART2_BASE) 05105 /** Array initializer of UART peripheral base addresses */ 05106 #define UART_BASE_ADDRS { 0u, UART1_BASE, UART2_BASE } 05107 /** Array initializer of UART peripheral base pointers */ 05108 #define UART_BASE_PTRS { (UART_Type *)0u, UART1, UART2 } 05109 /** Interrupt vectors for the UART peripheral type */ 05110 #define UART_RX_TX_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn } 05111 #define UART_ERR_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn } 05112 05113 /*! 05114 * @} 05115 */ /* end of group UART_Peripheral_Access_Layer */ 05116 05117 05118 /* ---------------------------------------------------------------------------- 05119 -- UART0 Peripheral Access Layer 05120 ---------------------------------------------------------------------------- */ 05121 05122 /*! 05123 * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer 05124 * @{ 05125 */ 05126 05127 /** UART0 - Register Layout Typedef */ 05128 typedef struct { 05129 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */ 05130 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */ 05131 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 05132 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 05133 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 05134 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 05135 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 05136 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 05137 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ 05138 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ 05139 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ 05140 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ 05141 } UART0_Type; 05142 05143 /* ---------------------------------------------------------------------------- 05144 -- UART0 Register Masks 05145 ---------------------------------------------------------------------------- */ 05146 05147 /*! 05148 * @addtogroup UART0_Register_Masks UART0 Register Masks 05149 * @{ 05150 */ 05151 05152 /*! @name BDH - UART Baud Rate Register High */ 05153 #define UART0_BDH_SBR_MASK (0x1FU) 05154 #define UART0_BDH_SBR_SHIFT (0U) 05155 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_SBR_SHIFT)) & UART0_BDH_SBR_MASK) 05156 #define UART0_BDH_SBNS_MASK (0x20U) 05157 #define UART0_BDH_SBNS_SHIFT (5U) 05158 #define UART0_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_SBNS_SHIFT)) & UART0_BDH_SBNS_MASK) 05159 #define UART0_BDH_RXEDGIE_MASK (0x40U) 05160 #define UART0_BDH_RXEDGIE_SHIFT (6U) 05161 #define UART0_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_RXEDGIE_SHIFT)) & UART0_BDH_RXEDGIE_MASK) 05162 #define UART0_BDH_LBKDIE_MASK (0x80U) 05163 #define UART0_BDH_LBKDIE_SHIFT (7U) 05164 #define UART0_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_LBKDIE_SHIFT)) & UART0_BDH_LBKDIE_MASK) 05165 05166 /*! @name BDL - UART Baud Rate Register Low */ 05167 #define UART0_BDL_SBR_MASK (0xFFU) 05168 #define UART0_BDL_SBR_SHIFT (0U) 05169 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDL_SBR_SHIFT)) & UART0_BDL_SBR_MASK) 05170 05171 /*! @name C1 - UART Control Register 1 */ 05172 #define UART0_C1_PT_MASK (0x1U) 05173 #define UART0_C1_PT_SHIFT (0U) 05174 #define UART0_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_PT_SHIFT)) & UART0_C1_PT_MASK) 05175 #define UART0_C1_PE_MASK (0x2U) 05176 #define UART0_C1_PE_SHIFT (1U) 05177 #define UART0_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_PE_SHIFT)) & UART0_C1_PE_MASK) 05178 #define UART0_C1_ILT_MASK (0x4U) 05179 #define UART0_C1_ILT_SHIFT (2U) 05180 #define UART0_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_ILT_SHIFT)) & UART0_C1_ILT_MASK) 05181 #define UART0_C1_WAKE_MASK (0x8U) 05182 #define UART0_C1_WAKE_SHIFT (3U) 05183 #define UART0_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_WAKE_SHIFT)) & UART0_C1_WAKE_MASK) 05184 #define UART0_C1_M_MASK (0x10U) 05185 #define UART0_C1_M_SHIFT (4U) 05186 #define UART0_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_M_SHIFT)) & UART0_C1_M_MASK) 05187 #define UART0_C1_RSRC_MASK (0x20U) 05188 #define UART0_C1_RSRC_SHIFT (5U) 05189 #define UART0_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_RSRC_SHIFT)) & UART0_C1_RSRC_MASK) 05190 #define UART0_C1_DOZEEN_MASK (0x40U) 05191 #define UART0_C1_DOZEEN_SHIFT (6U) 05192 #define UART0_C1_DOZEEN(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_DOZEEN_SHIFT)) & UART0_C1_DOZEEN_MASK) 05193 #define UART0_C1_LOOPS_MASK (0x80U) 05194 #define UART0_C1_LOOPS_SHIFT (7U) 05195 #define UART0_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_LOOPS_SHIFT)) & UART0_C1_LOOPS_MASK) 05196 05197 /*! @name C2 - UART Control Register 2 */ 05198 #define UART0_C2_SBK_MASK (0x1U) 05199 #define UART0_C2_SBK_SHIFT (0U) 05200 #define UART0_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_SBK_SHIFT)) & UART0_C2_SBK_MASK) 05201 #define UART0_C2_RWU_MASK (0x2U) 05202 #define UART0_C2_RWU_SHIFT (1U) 05203 #define UART0_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RWU_SHIFT)) & UART0_C2_RWU_MASK) 05204 #define UART0_C2_RE_MASK (0x4U) 05205 #define UART0_C2_RE_SHIFT (2U) 05206 #define UART0_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RE_SHIFT)) & UART0_C2_RE_MASK) 05207 #define UART0_C2_TE_MASK (0x8U) 05208 #define UART0_C2_TE_SHIFT (3U) 05209 #define UART0_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TE_SHIFT)) & UART0_C2_TE_MASK) 05210 #define UART0_C2_ILIE_MASK (0x10U) 05211 #define UART0_C2_ILIE_SHIFT (4U) 05212 #define UART0_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_ILIE_SHIFT)) & UART0_C2_ILIE_MASK) 05213 #define UART0_C2_RIE_MASK (0x20U) 05214 #define UART0_C2_RIE_SHIFT (5U) 05215 #define UART0_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RIE_SHIFT)) & UART0_C2_RIE_MASK) 05216 #define UART0_C2_TCIE_MASK (0x40U) 05217 #define UART0_C2_TCIE_SHIFT (6U) 05218 #define UART0_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TCIE_SHIFT)) & UART0_C2_TCIE_MASK) 05219 #define UART0_C2_TIE_MASK (0x80U) 05220 #define UART0_C2_TIE_SHIFT (7U) 05221 #define UART0_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TIE_SHIFT)) & UART0_C2_TIE_MASK) 05222 05223 /*! @name S1 - UART Status Register 1 */ 05224 #define UART0_S1_PF_MASK (0x1U) 05225 #define UART0_S1_PF_SHIFT (0U) 05226 #define UART0_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_PF_SHIFT)) & UART0_S1_PF_MASK) 05227 #define UART0_S1_FE_MASK (0x2U) 05228 #define UART0_S1_FE_SHIFT (1U) 05229 #define UART0_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_FE_SHIFT)) & UART0_S1_FE_MASK) 05230 #define UART0_S1_NF_MASK (0x4U) 05231 #define UART0_S1_NF_SHIFT (2U) 05232 #define UART0_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_NF_SHIFT)) & UART0_S1_NF_MASK) 05233 #define UART0_S1_OR_MASK (0x8U) 05234 #define UART0_S1_OR_SHIFT (3U) 05235 #define UART0_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_OR_SHIFT)) & UART0_S1_OR_MASK) 05236 #define UART0_S1_IDLE_MASK (0x10U) 05237 #define UART0_S1_IDLE_SHIFT (4U) 05238 #define UART0_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_IDLE_SHIFT)) & UART0_S1_IDLE_MASK) 05239 #define UART0_S1_RDRF_MASK (0x20U) 05240 #define UART0_S1_RDRF_SHIFT (5U) 05241 #define UART0_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_RDRF_SHIFT)) & UART0_S1_RDRF_MASK) 05242 #define UART0_S1_TC_MASK (0x40U) 05243 #define UART0_S1_TC_SHIFT (6U) 05244 #define UART0_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_TC_SHIFT)) & UART0_S1_TC_MASK) 05245 #define UART0_S1_TDRE_MASK (0x80U) 05246 #define UART0_S1_TDRE_SHIFT (7U) 05247 #define UART0_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_TDRE_SHIFT)) & UART0_S1_TDRE_MASK) 05248 05249 /*! @name S2 - UART Status Register 2 */ 05250 #define UART0_S2_RAF_MASK (0x1U) 05251 #define UART0_S2_RAF_SHIFT (0U) 05252 #define UART0_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RAF_SHIFT)) & UART0_S2_RAF_MASK) 05253 #define UART0_S2_LBKDE_MASK (0x2U) 05254 #define UART0_S2_LBKDE_SHIFT (1U) 05255 #define UART0_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_LBKDE_SHIFT)) & UART0_S2_LBKDE_MASK) 05256 #define UART0_S2_BRK13_MASK (0x4U) 05257 #define UART0_S2_BRK13_SHIFT (2U) 05258 #define UART0_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_BRK13_SHIFT)) & UART0_S2_BRK13_MASK) 05259 #define UART0_S2_RWUID_MASK (0x8U) 05260 #define UART0_S2_RWUID_SHIFT (3U) 05261 #define UART0_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RWUID_SHIFT)) & UART0_S2_RWUID_MASK) 05262 #define UART0_S2_RXINV_MASK (0x10U) 05263 #define UART0_S2_RXINV_SHIFT (4U) 05264 #define UART0_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RXINV_SHIFT)) & UART0_S2_RXINV_MASK) 05265 #define UART0_S2_MSBF_MASK (0x20U) 05266 #define UART0_S2_MSBF_SHIFT (5U) 05267 #define UART0_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_MSBF_SHIFT)) & UART0_S2_MSBF_MASK) 05268 #define UART0_S2_RXEDGIF_MASK (0x40U) 05269 #define UART0_S2_RXEDGIF_SHIFT (6U) 05270 #define UART0_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RXEDGIF_SHIFT)) & UART0_S2_RXEDGIF_MASK) 05271 #define UART0_S2_LBKDIF_MASK (0x80U) 05272 #define UART0_S2_LBKDIF_SHIFT (7U) 05273 #define UART0_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_LBKDIF_SHIFT)) & UART0_S2_LBKDIF_MASK) 05274 05275 /*! @name C3 - UART Control Register 3 */ 05276 #define UART0_C3_PEIE_MASK (0x1U) 05277 #define UART0_C3_PEIE_SHIFT (0U) 05278 #define UART0_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_PEIE_SHIFT)) & UART0_C3_PEIE_MASK) 05279 #define UART0_C3_FEIE_MASK (0x2U) 05280 #define UART0_C3_FEIE_SHIFT (1U) 05281 #define UART0_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_FEIE_SHIFT)) & UART0_C3_FEIE_MASK) 05282 #define UART0_C3_NEIE_MASK (0x4U) 05283 #define UART0_C3_NEIE_SHIFT (2U) 05284 #define UART0_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_NEIE_SHIFT)) & UART0_C3_NEIE_MASK) 05285 #define UART0_C3_ORIE_MASK (0x8U) 05286 #define UART0_C3_ORIE_SHIFT (3U) 05287 #define UART0_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_ORIE_SHIFT)) & UART0_C3_ORIE_MASK) 05288 #define UART0_C3_TXINV_MASK (0x10U) 05289 #define UART0_C3_TXINV_SHIFT (4U) 05290 #define UART0_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_TXINV_SHIFT)) & UART0_C3_TXINV_MASK) 05291 #define UART0_C3_TXDIR_MASK (0x20U) 05292 #define UART0_C3_TXDIR_SHIFT (5U) 05293 #define UART0_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_TXDIR_SHIFT)) & UART0_C3_TXDIR_MASK) 05294 #define UART0_C3_R9T8_MASK (0x40U) 05295 #define UART0_C3_R9T8_SHIFT (6U) 05296 #define UART0_C3_R9T8(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_R9T8_SHIFT)) & UART0_C3_R9T8_MASK) 05297 #define UART0_C3_R8T9_MASK (0x80U) 05298 #define UART0_C3_R8T9_SHIFT (7U) 05299 #define UART0_C3_R8T9(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_R8T9_SHIFT)) & UART0_C3_R8T9_MASK) 05300 05301 /*! @name D - UART Data Register */ 05302 #define UART0_D_R0T0_MASK (0x1U) 05303 #define UART0_D_R0T0_SHIFT (0U) 05304 #define UART0_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R0T0_SHIFT)) & UART0_D_R0T0_MASK) 05305 #define UART0_D_R1T1_MASK (0x2U) 05306 #define UART0_D_R1T1_SHIFT (1U) 05307 #define UART0_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R1T1_SHIFT)) & UART0_D_R1T1_MASK) 05308 #define UART0_D_R2T2_MASK (0x4U) 05309 #define UART0_D_R2T2_SHIFT (2U) 05310 #define UART0_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R2T2_SHIFT)) & UART0_D_R2T2_MASK) 05311 #define UART0_D_R3T3_MASK (0x8U) 05312 #define UART0_D_R3T3_SHIFT (3U) 05313 #define UART0_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R3T3_SHIFT)) & UART0_D_R3T3_MASK) 05314 #define UART0_D_R4T4_MASK (0x10U) 05315 #define UART0_D_R4T4_SHIFT (4U) 05316 #define UART0_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R4T4_SHIFT)) & UART0_D_R4T4_MASK) 05317 #define UART0_D_R5T5_MASK (0x20U) 05318 #define UART0_D_R5T5_SHIFT (5U) 05319 #define UART0_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R5T5_SHIFT)) & UART0_D_R5T5_MASK) 05320 #define UART0_D_R6T6_MASK (0x40U) 05321 #define UART0_D_R6T6_SHIFT (6U) 05322 #define UART0_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R6T6_SHIFT)) & UART0_D_R6T6_MASK) 05323 #define UART0_D_R7T7_MASK (0x80U) 05324 #define UART0_D_R7T7_SHIFT (7U) 05325 #define UART0_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R7T7_SHIFT)) & UART0_D_R7T7_MASK) 05326 05327 /*! @name MA1 - UART Match Address Registers 1 */ 05328 #define UART0_MA1_MA_MASK (0xFFU) 05329 #define UART0_MA1_MA_SHIFT (0U) 05330 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART0_MA1_MA_SHIFT)) & UART0_MA1_MA_MASK) 05331 05332 /*! @name MA2 - UART Match Address Registers 2 */ 05333 #define UART0_MA2_MA_MASK (0xFFU) 05334 #define UART0_MA2_MA_SHIFT (0U) 05335 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART0_MA2_MA_SHIFT)) & UART0_MA2_MA_MASK) 05336 05337 /*! @name C4 - UART Control Register 4 */ 05338 #define UART0_C4_OSR_MASK (0x1FU) 05339 #define UART0_C4_OSR_SHIFT (0U) 05340 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_OSR_SHIFT)) & UART0_C4_OSR_MASK) 05341 #define UART0_C4_M10_MASK (0x20U) 05342 #define UART0_C4_M10_SHIFT (5U) 05343 #define UART0_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_M10_SHIFT)) & UART0_C4_M10_MASK) 05344 #define UART0_C4_MAEN2_MASK (0x40U) 05345 #define UART0_C4_MAEN2_SHIFT (6U) 05346 #define UART0_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_MAEN2_SHIFT)) & UART0_C4_MAEN2_MASK) 05347 #define UART0_C4_MAEN1_MASK (0x80U) 05348 #define UART0_C4_MAEN1_SHIFT (7U) 05349 #define UART0_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_MAEN1_SHIFT)) & UART0_C4_MAEN1_MASK) 05350 05351 /*! @name C5 - UART Control Register 5 */ 05352 #define UART0_C5_RESYNCDIS_MASK (0x1U) 05353 #define UART0_C5_RESYNCDIS_SHIFT (0U) 05354 #define UART0_C5_RESYNCDIS(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_RESYNCDIS_SHIFT)) & UART0_C5_RESYNCDIS_MASK) 05355 #define UART0_C5_BOTHEDGE_MASK (0x2U) 05356 #define UART0_C5_BOTHEDGE_SHIFT (1U) 05357 #define UART0_C5_BOTHEDGE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_BOTHEDGE_SHIFT)) & UART0_C5_BOTHEDGE_MASK) 05358 #define UART0_C5_RDMAE_MASK (0x20U) 05359 #define UART0_C5_RDMAE_SHIFT (5U) 05360 #define UART0_C5_RDMAE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_RDMAE_SHIFT)) & UART0_C5_RDMAE_MASK) 05361 #define UART0_C5_TDMAE_MASK (0x80U) 05362 #define UART0_C5_TDMAE_SHIFT (7U) 05363 #define UART0_C5_TDMAE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_TDMAE_SHIFT)) & UART0_C5_TDMAE_MASK) 05364 05365 05366 /*! 05367 * @} 05368 */ /* end of group UART0_Register_Masks */ 05369 05370 05371 /* UART0 - Peripheral instance base addresses */ 05372 /** Peripheral UART0 base address */ 05373 #define UART0_BASE (0x4006A000u) 05374 /** Peripheral UART0 base pointer */ 05375 #define UART0 ((UART0_Type *)UART0_BASE) 05376 /** Array initializer of UART0 peripheral base addresses */ 05377 #define UART0_BASE_ADDRS { UART0_BASE } 05378 /** Array initializer of UART0 peripheral base pointers */ 05379 #define UART0_BASE_PTRS { UART0 } 05380 /** Interrupt vectors for the UART0 peripheral type */ 05381 #define UART0_RX_TX_IRQS { UART0_IRQn } 05382 #define UART0_ERR_IRQS { UART0_IRQn } 05383 05384 /*! 05385 * @} 05386 */ /* end of group UART0_Peripheral_Access_Layer */ 05387 05388 05389 /* ---------------------------------------------------------------------------- 05390 -- USB Peripheral Access Layer 05391 ---------------------------------------------------------------------------- */ 05392 05393 /*! 05394 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer 05395 * @{ 05396 */ 05397 05398 /** USB - Register Layout Typedef */ 05399 typedef struct { 05400 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ 05401 uint8_t RESERVED_0[3]; 05402 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ 05403 uint8_t RESERVED_1[3]; 05404 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ 05405 uint8_t RESERVED_2[3]; 05406 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ 05407 uint8_t RESERVED_3[3]; 05408 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */ 05409 uint8_t RESERVED_4[3]; 05410 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */ 05411 uint8_t RESERVED_5[3]; 05412 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */ 05413 uint8_t RESERVED_6[3]; 05414 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ 05415 uint8_t RESERVED_7[99]; 05416 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ 05417 uint8_t RESERVED_8[3]; 05418 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ 05419 uint8_t RESERVED_9[3]; 05420 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ 05421 uint8_t RESERVED_10[3]; 05422 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ 05423 uint8_t RESERVED_11[3]; 05424 __I uint8_t STAT; /**< Status register, offset: 0x90 */ 05425 uint8_t RESERVED_12[3]; 05426 __IO uint8_t CTL; /**< Control register, offset: 0x94 */ 05427 uint8_t RESERVED_13[3]; 05428 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ 05429 uint8_t RESERVED_14[3]; 05430 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */ 05431 uint8_t RESERVED_15[3]; 05432 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */ 05433 uint8_t RESERVED_16[3]; 05434 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */ 05435 uint8_t RESERVED_17[3]; 05436 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */ 05437 uint8_t RESERVED_18[3]; 05438 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */ 05439 uint8_t RESERVED_19[3]; 05440 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ 05441 uint8_t RESERVED_20[3]; 05442 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ 05443 uint8_t RESERVED_21[11]; 05444 struct { /* offset: 0xC0, array step: 0x4 */ 05445 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ 05446 uint8_t RESERVED_0[3]; 05447 } ENDPOINT[16]; 05448 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ 05449 uint8_t RESERVED_22[3]; 05450 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ 05451 uint8_t RESERVED_23[3]; 05452 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ 05453 uint8_t RESERVED_24[3]; 05454 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */ 05455 uint8_t RESERVED_25[7]; 05456 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ 05457 } USB_Type; 05458 05459 /* ---------------------------------------------------------------------------- 05460 -- USB Register Masks 05461 ---------------------------------------------------------------------------- */ 05462 05463 /*! 05464 * @addtogroup USB_Register_Masks USB Register Masks 05465 * @{ 05466 */ 05467 05468 /*! @name PERID - Peripheral ID register */ 05469 #define USB_PERID_ID_MASK (0x3FU) 05470 #define USB_PERID_ID_SHIFT (0U) 05471 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) 05472 05473 /*! @name IDCOMP - Peripheral ID Complement register */ 05474 #define USB_IDCOMP_NID_MASK (0x3FU) 05475 #define USB_IDCOMP_NID_SHIFT (0U) 05476 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) 05477 05478 /*! @name REV - Peripheral Revision register */ 05479 #define USB_REV_REV_MASK (0xFFU) 05480 #define USB_REV_REV_SHIFT (0U) 05481 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) 05482 05483 /*! @name ADDINFO - Peripheral Additional Info register */ 05484 #define USB_ADDINFO_IEHOST_MASK (0x1U) 05485 #define USB_ADDINFO_IEHOST_SHIFT (0U) 05486 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) 05487 #define USB_ADDINFO_IRQNUM_MASK (0xF8U) 05488 #define USB_ADDINFO_IRQNUM_SHIFT (3U) 05489 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK) 05490 05491 /*! @name OTGISTAT - OTG Interrupt Status register */ 05492 #define USB_OTGISTAT_AVBUSCHG_MASK (0x1U) 05493 #define USB_OTGISTAT_AVBUSCHG_SHIFT (0U) 05494 #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK) 05495 #define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U) 05496 #define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U) 05497 #define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK) 05498 #define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U) 05499 #define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U) 05500 #define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK) 05501 #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) 05502 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) 05503 #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) 05504 #define USB_OTGISTAT_ONEMSEC_MASK (0x40U) 05505 #define USB_OTGISTAT_ONEMSEC_SHIFT (6U) 05506 #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) 05507 #define USB_OTGISTAT_IDCHG_MASK (0x80U) 05508 #define USB_OTGISTAT_IDCHG_SHIFT (7U) 05509 #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK) 05510 05511 /*! @name OTGICR - OTG Interrupt Control register */ 05512 #define USB_OTGICR_AVBUSEN_MASK (0x1U) 05513 #define USB_OTGICR_AVBUSEN_SHIFT (0U) 05514 #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK) 05515 #define USB_OTGICR_BSESSEN_MASK (0x4U) 05516 #define USB_OTGICR_BSESSEN_SHIFT (2U) 05517 #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK) 05518 #define USB_OTGICR_SESSVLDEN_MASK (0x8U) 05519 #define USB_OTGICR_SESSVLDEN_SHIFT (3U) 05520 #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK) 05521 #define USB_OTGICR_LINESTATEEN_MASK (0x20U) 05522 #define USB_OTGICR_LINESTATEEN_SHIFT (5U) 05523 #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) 05524 #define USB_OTGICR_ONEMSECEN_MASK (0x40U) 05525 #define USB_OTGICR_ONEMSECEN_SHIFT (6U) 05526 #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) 05527 #define USB_OTGICR_IDEN_MASK (0x80U) 05528 #define USB_OTGICR_IDEN_SHIFT (7U) 05529 #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK) 05530 05531 /*! @name OTGSTAT - OTG Status register */ 05532 #define USB_OTGSTAT_AVBUSVLD_MASK (0x1U) 05533 #define USB_OTGSTAT_AVBUSVLD_SHIFT (0U) 05534 #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK) 05535 #define USB_OTGSTAT_BSESSEND_MASK (0x4U) 05536 #define USB_OTGSTAT_BSESSEND_SHIFT (2U) 05537 #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK) 05538 #define USB_OTGSTAT_SESS_VLD_MASK (0x8U) 05539 #define USB_OTGSTAT_SESS_VLD_SHIFT (3U) 05540 #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK) 05541 #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) 05542 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) 05543 #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) 05544 #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U) 05545 #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U) 05546 #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK) 05547 #define USB_OTGSTAT_ID_MASK (0x80U) 05548 #define USB_OTGSTAT_ID_SHIFT (7U) 05549 #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK) 05550 05551 /*! @name OTGCTL - OTG Control register */ 05552 #define USB_OTGCTL_OTGEN_MASK (0x4U) 05553 #define USB_OTGCTL_OTGEN_SHIFT (2U) 05554 #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) 05555 #define USB_OTGCTL_DMLOW_MASK (0x10U) 05556 #define USB_OTGCTL_DMLOW_SHIFT (4U) 05557 #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) 05558 #define USB_OTGCTL_DPLOW_MASK (0x20U) 05559 #define USB_OTGCTL_DPLOW_SHIFT (5U) 05560 #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) 05561 #define USB_OTGCTL_DPHIGH_MASK (0x80U) 05562 #define USB_OTGCTL_DPHIGH_SHIFT (7U) 05563 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) 05564 05565 /*! @name ISTAT - Interrupt Status register */ 05566 #define USB_ISTAT_USBRST_MASK (0x1U) 05567 #define USB_ISTAT_USBRST_SHIFT (0U) 05568 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) 05569 #define USB_ISTAT_ERROR_MASK (0x2U) 05570 #define USB_ISTAT_ERROR_SHIFT (1U) 05571 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) 05572 #define USB_ISTAT_SOFTOK_MASK (0x4U) 05573 #define USB_ISTAT_SOFTOK_SHIFT (2U) 05574 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) 05575 #define USB_ISTAT_TOKDNE_MASK (0x8U) 05576 #define USB_ISTAT_TOKDNE_SHIFT (3U) 05577 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) 05578 #define USB_ISTAT_SLEEP_MASK (0x10U) 05579 #define USB_ISTAT_SLEEP_SHIFT (4U) 05580 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) 05581 #define USB_ISTAT_RESUME_MASK (0x20U) 05582 #define USB_ISTAT_RESUME_SHIFT (5U) 05583 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) 05584 #define USB_ISTAT_ATTACH_MASK (0x40U) 05585 #define USB_ISTAT_ATTACH_SHIFT (6U) 05586 #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) 05587 #define USB_ISTAT_STALL_MASK (0x80U) 05588 #define USB_ISTAT_STALL_SHIFT (7U) 05589 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) 05590 05591 /*! @name INTEN - Interrupt Enable register */ 05592 #define USB_INTEN_USBRSTEN_MASK (0x1U) 05593 #define USB_INTEN_USBRSTEN_SHIFT (0U) 05594 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) 05595 #define USB_INTEN_ERROREN_MASK (0x2U) 05596 #define USB_INTEN_ERROREN_SHIFT (1U) 05597 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) 05598 #define USB_INTEN_SOFTOKEN_MASK (0x4U) 05599 #define USB_INTEN_SOFTOKEN_SHIFT (2U) 05600 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) 05601 #define USB_INTEN_TOKDNEEN_MASK (0x8U) 05602 #define USB_INTEN_TOKDNEEN_SHIFT (3U) 05603 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) 05604 #define USB_INTEN_SLEEPEN_MASK (0x10U) 05605 #define USB_INTEN_SLEEPEN_SHIFT (4U) 05606 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) 05607 #define USB_INTEN_RESUMEEN_MASK (0x20U) 05608 #define USB_INTEN_RESUMEEN_SHIFT (5U) 05609 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) 05610 #define USB_INTEN_ATTACHEN_MASK (0x40U) 05611 #define USB_INTEN_ATTACHEN_SHIFT (6U) 05612 #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) 05613 #define USB_INTEN_STALLEN_MASK (0x80U) 05614 #define USB_INTEN_STALLEN_SHIFT (7U) 05615 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) 05616 05617 /*! @name ERRSTAT - Error Interrupt Status register */ 05618 #define USB_ERRSTAT_PIDERR_MASK (0x1U) 05619 #define USB_ERRSTAT_PIDERR_SHIFT (0U) 05620 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) 05621 #define USB_ERRSTAT_CRC5EOF_MASK (0x2U) 05622 #define USB_ERRSTAT_CRC5EOF_SHIFT (1U) 05623 #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) 05624 #define USB_ERRSTAT_CRC16_MASK (0x4U) 05625 #define USB_ERRSTAT_CRC16_SHIFT (2U) 05626 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) 05627 #define USB_ERRSTAT_DFN8_MASK (0x8U) 05628 #define USB_ERRSTAT_DFN8_SHIFT (3U) 05629 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) 05630 #define USB_ERRSTAT_BTOERR_MASK (0x10U) 05631 #define USB_ERRSTAT_BTOERR_SHIFT (4U) 05632 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) 05633 #define USB_ERRSTAT_DMAERR_MASK (0x20U) 05634 #define USB_ERRSTAT_DMAERR_SHIFT (5U) 05635 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) 05636 #define USB_ERRSTAT_BTSERR_MASK (0x80U) 05637 #define USB_ERRSTAT_BTSERR_SHIFT (7U) 05638 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) 05639 05640 /*! @name ERREN - Error Interrupt Enable register */ 05641 #define USB_ERREN_PIDERREN_MASK (0x1U) 05642 #define USB_ERREN_PIDERREN_SHIFT (0U) 05643 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) 05644 #define USB_ERREN_CRC5EOFEN_MASK (0x2U) 05645 #define USB_ERREN_CRC5EOFEN_SHIFT (1U) 05646 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) 05647 #define USB_ERREN_CRC16EN_MASK (0x4U) 05648 #define USB_ERREN_CRC16EN_SHIFT (2U) 05649 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) 05650 #define USB_ERREN_DFN8EN_MASK (0x8U) 05651 #define USB_ERREN_DFN8EN_SHIFT (3U) 05652 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) 05653 #define USB_ERREN_BTOERREN_MASK (0x10U) 05654 #define USB_ERREN_BTOERREN_SHIFT (4U) 05655 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) 05656 #define USB_ERREN_DMAERREN_MASK (0x20U) 05657 #define USB_ERREN_DMAERREN_SHIFT (5U) 05658 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) 05659 #define USB_ERREN_BTSERREN_MASK (0x80U) 05660 #define USB_ERREN_BTSERREN_SHIFT (7U) 05661 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) 05662 05663 /*! @name STAT - Status register */ 05664 #define USB_STAT_ODD_MASK (0x4U) 05665 #define USB_STAT_ODD_SHIFT (2U) 05666 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) 05667 #define USB_STAT_TX_MASK (0x8U) 05668 #define USB_STAT_TX_SHIFT (3U) 05669 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) 05670 #define USB_STAT_ENDP_MASK (0xF0U) 05671 #define USB_STAT_ENDP_SHIFT (4U) 05672 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) 05673 05674 /*! @name CTL - Control register */ 05675 #define USB_CTL_USBENSOFEN_MASK (0x1U) 05676 #define USB_CTL_USBENSOFEN_SHIFT (0U) 05677 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) 05678 #define USB_CTL_ODDRST_MASK (0x2U) 05679 #define USB_CTL_ODDRST_SHIFT (1U) 05680 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) 05681 #define USB_CTL_RESUME_MASK (0x4U) 05682 #define USB_CTL_RESUME_SHIFT (2U) 05683 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) 05684 #define USB_CTL_HOSTMODEEN_MASK (0x8U) 05685 #define USB_CTL_HOSTMODEEN_SHIFT (3U) 05686 #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) 05687 #define USB_CTL_RESET_MASK (0x10U) 05688 #define USB_CTL_RESET_SHIFT (4U) 05689 #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) 05690 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) 05691 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) 05692 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) 05693 #define USB_CTL_SE0_MASK (0x40U) 05694 #define USB_CTL_SE0_SHIFT (6U) 05695 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) 05696 #define USB_CTL_JSTATE_MASK (0x80U) 05697 #define USB_CTL_JSTATE_SHIFT (7U) 05698 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) 05699 05700 /*! @name ADDR - Address register */ 05701 #define USB_ADDR_ADDR_MASK (0x7FU) 05702 #define USB_ADDR_ADDR_SHIFT (0U) 05703 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) 05704 #define USB_ADDR_LSEN_MASK (0x80U) 05705 #define USB_ADDR_LSEN_SHIFT (7U) 05706 #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) 05707 05708 /*! @name BDTPAGE1 - BDT Page register 1 */ 05709 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU) 05710 #define USB_BDTPAGE1_BDTBA_SHIFT (1U) 05711 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) 05712 05713 /*! @name FRMNUML - Frame Number register Low */ 05714 #define USB_FRMNUML_FRM_MASK (0xFFU) 05715 #define USB_FRMNUML_FRM_SHIFT (0U) 05716 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) 05717 05718 /*! @name FRMNUMH - Frame Number register High */ 05719 #define USB_FRMNUMH_FRM_MASK (0x7U) 05720 #define USB_FRMNUMH_FRM_SHIFT (0U) 05721 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) 05722 05723 /*! @name TOKEN - Token register */ 05724 #define USB_TOKEN_TOKENENDPT_MASK (0xFU) 05725 #define USB_TOKEN_TOKENENDPT_SHIFT (0U) 05726 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) 05727 #define USB_TOKEN_TOKENPID_MASK (0xF0U) 05728 #define USB_TOKEN_TOKENPID_SHIFT (4U) 05729 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) 05730 05731 /*! @name SOFTHLD - SOF Threshold register */ 05732 #define USB_SOFTHLD_CNT_MASK (0xFFU) 05733 #define USB_SOFTHLD_CNT_SHIFT (0U) 05734 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) 05735 05736 /*! @name BDTPAGE2 - BDT Page Register 2 */ 05737 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU) 05738 #define USB_BDTPAGE2_BDTBA_SHIFT (0U) 05739 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) 05740 05741 /*! @name BDTPAGE3 - BDT Page Register 3 */ 05742 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU) 05743 #define USB_BDTPAGE3_BDTBA_SHIFT (0U) 05744 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) 05745 05746 /*! @name ENDPT - Endpoint Control register */ 05747 #define USB_ENDPT_EPHSHK_MASK (0x1U) 05748 #define USB_ENDPT_EPHSHK_SHIFT (0U) 05749 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) 05750 #define USB_ENDPT_EPSTALL_MASK (0x2U) 05751 #define USB_ENDPT_EPSTALL_SHIFT (1U) 05752 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) 05753 #define USB_ENDPT_EPTXEN_MASK (0x4U) 05754 #define USB_ENDPT_EPTXEN_SHIFT (2U) 05755 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) 05756 #define USB_ENDPT_EPRXEN_MASK (0x8U) 05757 #define USB_ENDPT_EPRXEN_SHIFT (3U) 05758 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) 05759 #define USB_ENDPT_EPCTLDIS_MASK (0x10U) 05760 #define USB_ENDPT_EPCTLDIS_SHIFT (4U) 05761 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) 05762 #define USB_ENDPT_RETRYDIS_MASK (0x40U) 05763 #define USB_ENDPT_RETRYDIS_SHIFT (6U) 05764 #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) 05765 #define USB_ENDPT_HOSTWOHUB_MASK (0x80U) 05766 #define USB_ENDPT_HOSTWOHUB_SHIFT (7U) 05767 #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) 05768 05769 /* The count of USB_ENDPT */ 05770 #define USB_ENDPT_COUNT (16U) 05771 05772 /*! @name USBCTRL - USB Control register */ 05773 #define USB_USBCTRL_PDE_MASK (0x40U) 05774 #define USB_USBCTRL_PDE_SHIFT (6U) 05775 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) 05776 #define USB_USBCTRL_SUSP_MASK (0x80U) 05777 #define USB_USBCTRL_SUSP_SHIFT (7U) 05778 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) 05779 05780 /*! @name OBSERVE - USB OTG Observe register */ 05781 #define USB_OBSERVE_DMPD_MASK (0x10U) 05782 #define USB_OBSERVE_DMPD_SHIFT (4U) 05783 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) 05784 #define USB_OBSERVE_DPPD_MASK (0x40U) 05785 #define USB_OBSERVE_DPPD_SHIFT (6U) 05786 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) 05787 #define USB_OBSERVE_DPPU_MASK (0x80U) 05788 #define USB_OBSERVE_DPPU_SHIFT (7U) 05789 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) 05790 05791 /*! @name CONTROL - USB OTG Control register */ 05792 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) 05793 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) 05794 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) 05795 05796 /*! @name USBTRC0 - USB Transceiver Control register 0 */ 05797 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) 05798 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) 05799 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) 05800 #define USB_USBTRC0_SYNC_DET_MASK (0x2U) 05801 #define USB_USBTRC0_SYNC_DET_SHIFT (1U) 05802 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) 05803 #define USB_USBTRC0_USBRESMEN_MASK (0x20U) 05804 #define USB_USBTRC0_USBRESMEN_SHIFT (5U) 05805 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) 05806 #define USB_USBTRC0_USBRESET_MASK (0x80U) 05807 #define USB_USBTRC0_USBRESET_SHIFT (7U) 05808 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) 05809 05810 /*! @name USBFRMADJUST - Frame Adjust Register */ 05811 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU) 05812 #define USB_USBFRMADJUST_ADJ_SHIFT (0U) 05813 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) 05814 05815 05816 /*! 05817 * @} 05818 */ /* end of group USB_Register_Masks */ 05819 05820 05821 /* USB - Peripheral instance base addresses */ 05822 /** Peripheral USB0 base address */ 05823 #define USB0_BASE (0x40072000u) 05824 /** Peripheral USB0 base pointer */ 05825 #define USB0 ((USB_Type *)USB0_BASE) 05826 /** Array initializer of USB peripheral base addresses */ 05827 #define USB_BASE_ADDRS { USB0_BASE } 05828 /** Array initializer of USB peripheral base pointers */ 05829 #define USB_BASE_PTRS { USB0 } 05830 /** Interrupt vectors for the USB peripheral type */ 05831 #define USB_IRQS { USB0_IRQn } 05832 05833 /*! 05834 * @} 05835 */ /* end of group USB_Peripheral_Access_Layer */ 05836 05837 05838 /* 05839 ** End of section using anonymous unions 05840 */ 05841 05842 #if defined(__ARMCC_VERSION) 05843 #pragma pop 05844 #elif defined(__CWCC__) 05845 #pragma pop 05846 #elif defined(__GNUC__) 05847 /* leave anonymous unions enabled */ 05848 #elif defined(__IAR_SYSTEMS_ICC__) 05849 #pragma language=default 05850 #else 05851 #error Not supported compiler type 05852 #endif 05853 05854 /*! 05855 * @} 05856 */ /* end of group Peripheral_access_layer */ 05857 05858 05859 /* ---------------------------------------------------------------------------- 05860 -- SDK Compatibility 05861 ---------------------------------------------------------------------------- */ 05862 05863 /*! 05864 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 05865 * @{ 05866 */ 05867 05868 #define FPTA_BASE FGPIOA_BASE 05869 #define FPTA FGPIOA 05870 #define FPTB_BASE FGPIOB_BASE 05871 #define FPTB FGPIOB 05872 #define FPTC_BASE FGPIOC_BASE 05873 #define FPTC FGPIOC 05874 #define FPTD_BASE FGPIOD_BASE 05875 #define FPTD FGPIOD 05876 #define FPTE_BASE FGPIOE_BASE 05877 #define FPTE FGPIOE 05878 #define PTA_BASE GPIOA_BASE 05879 #define PTA GPIOA 05880 #define PTB_BASE GPIOB_BASE 05881 #define PTB GPIOB 05882 #define PTC_BASE GPIOC_BASE 05883 #define PTC GPIOC 05884 #define PTD_BASE GPIOD_BASE 05885 #define PTD GPIOD 05886 #define PTE_BASE GPIOE_BASE 05887 #define PTE GPIOE 05888 #define I2C_FLT_STOPIE_MASK This_symbol_has_been_deprecated 05889 #define I2C_FLT_STOPIE_SHIFT This_symbol_has_been_deprecated 05890 #define I2S_RCR2_CLKMODE_MASK I2S_RCR2_MSEL_MASK 05891 #define I2S_RCR2_CLKMODE_SHIFT I2S_RCR2_MSEL_SHIFT 05892 #define I2S_RCR2_CLKMODE(x) I2S_RCR2_MSEL(x) 05893 #define I2S_TCR2_CLKMODE_MASK I2S_TCR2_MSEL_MASK 05894 #define I2S_TCR2_CLKMODE_SHIFT I2S_TCR2_MSEL_SHIFT 05895 #define I2S_TCR2_CLKMODE(x) I2S_TCR2_MSEL(x) 05896 #define MCG_S_LOLS_MASK MCG_S_LOLS0_MASK 05897 #define MCG_S_LOLS_SHIFT MCG_S_LOLS0_SHIFT 05898 #define NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<NVIC_ISPR_SETPEND_SHIFT))&NVIC_ISPR_SETPEND_MASK) 05899 #define LPTimer_IRQn LPTMR0_IRQn 05900 #define LPTimer_IRQHandler LPTMR0_IRQHandler 05901 #define LLW_IRQn LLWU_IRQn 05902 #define LLW_IRQHandler LLWU_IRQHandler 05903 05904 /*! 05905 * @} 05906 */ /* end of group SDK_Compatibility_Symbols */ 05907 05908 05909 #endif /* _MKL26Z4_H_ */ 05910
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